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TLV172, TLV2172, TLV4172
SBOS784C – NOVEMBER 2016 – REVISED JANUARY 2019
TLVx172 36-V, single-supply, low-power
operational amplifier for cost-sensitive systems
1 Features
•
•
•
•
•
•
•
•
•
•
•
1
Supply Range: 4.5 V to 36 V, ±2.25 V to ±18 V
Low Noise: 9 nV/√Hz
Low Offset Drift: ±1 μV/°C (Typical)
EMI-Hardened
Input Range Includes Negative Supply
Rail-to-Rail Output
Gain Bandwidth: 10 MHz
Slew Rate: 10 V/μs
Low Quiescent Current: 1.6 mA per Amplifier
High Common-Mode Rejection: 116 dB (Typical)
Low Input Bias Current: 10 pA
2 Applications
•
•
•
•
•
•
•
•
•
•
TFT-LCD Drive Circuits
Touch-Screen Displays
Wireless LANs
Portable Instrumentation
Analog-to-Digital Converter (ADC) Buffers
Active Filters
Line Drivers or Line Receivers
Ultrasound
Currency Counters
Transducer Amplifiers
3 Description
The TLVx172 family of electromagnetic interference
(EMI)-hardened, 36-V, single-supply, low-noise
operational amplifiers (op amps) features a THD+N of
0.0002% at 1 kHz with the ability to operate on
supplies ranging from 4.5 V (±2.25 V) to 36 V (±18V).
These features, along with low noise and very high
PSRR, enable the TLVx172 to amplify microvolt-level
signals in applications such as HEV and EV
automobiles
and
power
trains,
medical
instrumentation, and more. The TLVx172 device
offers good offset and drift, a high bandwidth of 10
MHz, and a slew rate of 10 V/μs with only 2.3 mA of
quiescent current over temperature (maximum).
Unlike most op amps that are specified at only one
supply voltage, the TLVx172 device is specified from
4.5 V to 36 V. Input signals beyond the supply rails
do not cause phase reversal. TLVx172 device is
stable with capacitive loads up to 300 pF. The input
can operate 100 mV below the negative rail and
within 2 V of the positive rail for normal operation.
Note that the device can operate with a full rail-to-rail
input 100 mV beyond the positive rail, but with
reduced performance within 2 V of the positive rail.
The TLVx172 op amp is specified from –40°C to
+125°C.
Device Information(1)
PART NUMBER
PACKAGE
TLV172
TLV2172
TLV4172
BODY SIZE (NOM)
SOIC (8)
4.90 mm × 3.91 mm
SC70 (5)
2.00 mm × 1.25 mm
SOT-23 (5)
2.90 mm × 1.60 mm
SOIC (8)
4.90 mm × 3.91 mm
VSSOP (8)
3.00 mm × 3.00 mm
SOIC (14)
8.65 mm × 3.91 mm
TSSOP (14)
5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
VCC
VCC
V1
15 V
VEE
V2
15 V
R1
3.9 kŸ
R2
3.9 kŸ
VEE
++
LSK489
Q1
VCC
VOUT
R3
1.13 kŸ
Q2
VCC
R6
27.4 kŸ
Q3
R4
11.5 Ÿ
MMBT4401
Q4
MMBT4401
R5
300 Ÿ
VEE
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLV172, TLV2172, TLV4172
SBOS784C – NOVEMBER 2016 – REVISED JANUARY 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
8
1
1
1
2
3
4
7
Absolute Maximum Ratings ...................................... 7
ESD Ratings.............................................................. 7
Recommended Operating Conditions....................... 7
Thermal Information: TLV172 ................................... 8
Thermal Information: TLV2172 ................................. 8
Thermal Information: TLV4172 ................................. 8
Electrical Characteristics........................................... 9
Typical Characteristics ............................................ 10
Detailed Description ............................................ 15
8.1 Overview ................................................................. 15
8.2 Functional Block Diagram ...................................... 15
8.3 Feature Description................................................. 16
8.4 Device Functional Modes........................................ 19
9
Application and Implementation ........................ 20
9.1 Application Information............................................ 20
9.2 Typical Application .................................................. 20
10 Power Supply Recommendations ..................... 22
11 Layout................................................................... 22
11.1 Layout Guidelines ................................................. 22
11.2 Layout Example .................................................... 23
12 Device and Documentation Support ................. 24
12.1
12.2
12.3
12.4
12.5
12.6
12.7
12.8
Device Support......................................................
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
24
25
25
25
25
25
25
25
13 Mechanical, Packaging, and Orderable
Information ........................................................... 26
4 Revision History
Changes from Revision B (September 2018) to Revision C
•
Page
Changed the datasheet title From: TLV2172 36-V, Single-Supply, Low-Power.. To: TLVx172 36-V, single-supply,
low-power... ............................................................................................................................................................................ 1
Changes from Revision A (May 2018) to Revision B
Page
•
Deleted the Device Family Comparison table ........................................................................................................................ 3
•
Added the 5-pin SC70 and SOT-23, and the 8-pin SOIC pinout diagrams to the data sheet ............................................... 4
•
Added TLV172 Pin Functions table to the data sheet............................................................................................................ 4
•
Added 14-pin SOIC and TSSOP pinout diagram to the data sheet ...................................................................................... 6
Changes from Original (November 2016) to Revision A
•
2
Page
Updated supply voltage values in Absolute Maximum Ratings table..................................................................................... 7
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SBOS784C – NOVEMBER 2016 – REVISED JANUARY 2019
5 Device Comparison Table
DEVICE
PACKAGE
TLV172 (single)
SC70-5, SOT-23-5, SOIC-8
TLV2172 (dual)
SOIC-8, VSSOP-8
TLV4172 (quad)
SOIC-14, TSSOP-14
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SBOS784C – NOVEMBER 2016 – REVISED JANUARY 2019
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6 Pin Configuration and Functions
TLV172 DCK Package
5-Pin SC70
Top View
1
V±
2
±IN
3
5
V+
1
V±
2
+IN
3
+
±
+
OUT
4
OUT
Not to scale
5
V+
4
±IN
±
+IN
TLV172 DBV Package
5-Pin SOT-23
Top View
Not to scale
TLV172 D Package
8-Pin SOIC
Top View
NC
1
±IN
2
+IN
3
V±
4
8
NC
±
7
V+
+
6
OUT
5
NC
Not to scale
NC- no internal connection
Pin Functions: TLV172
PIN
NAME
I/O
DESCRIPTION
SC70
SOT-23
SOIC
–IN
3
4
2
I
Negative (inverting) input
+IN
1
3
3
I
Positive (noninverting) input
NC
—
—
1, 5, 8
—
No internal connection (can be left floating)
OUT
4
1
6
O
Output
V–
2
2
4
—
Negative (lowest) power supply
V+
5
5
7
—
Positive (highest) power supply
4
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SBOS784C – NOVEMBER 2016 – REVISED JANUARY 2019
TLV2172 D and DGK Packages
8-Pin SOIC and VSSOP
Top View
OUT A
1
8
V+
±IN A
2
7
OUT B
+IN A
3
6
±IN B
V±
4
5
+IN B
Not to scale
Pin Functions: TLV2172
PIN
SOIC
(D)
VSSOP
(DGK)
I/O
–IN A
2
2
I
Inverting input, channel A
–IN B
6
6
I
Inverting input, channel B
+IN A
3
3
I
Noninverting input, channel A
+IN B
5
5
I
Noninverting input, channel B
OUT A
1
1
O
Output, channel A
OUT B
7
7
O
Output, channel B
V–
4
4
—
Negative (lowest) power supply
V+
8
8
—
Positive (highest) power supply
NAME
DESCRIPTION
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SBOS784C – NOVEMBER 2016 – REVISED JANUARY 2019
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TLV4172 D and PW Packages
14-Pin SOIC and TSSOP
Top View
OUT A
1
14
OUT D
±IN A
2
13
±IN D
+IN A
3
12
+IN D
V+
4
11
V±
+IN B
5
10
+IN C
±IN B
6
9
±IN C
OUT B
7
8
OUT C
Not to scale
Pin Functions: TLV4172
PIN
SOIC
(D)
TSSOP
(PW)
I/O
–IN A
2
2
I
Inverting input, channel A
–IN B
6
6
I
Inverting input, channel B
NAME
DESCRIPTION
–IN C
9
9
I
Inverting input, channel C
–IN D
13
13
I
Inverting input, channel D
+IN A
3
3
I
Noninverting input, channel A
+IN B
5
5
I
Noninverting input, channel B
+IN C
10
10
I
Noninverting input, channel C
+IN D
12
12
I
Noninverting input, channel D
OUT A
1
1
O
Output, channel A
OUT B
7
7
O
Output, channel B
OUT C
8
8
O
Output, channel C
OUT D
14
14
O
Output, channel D
V–
11
11
—
Negative (lowest) power supply
V+
4
4
—
Positive (highest) power supply
6
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SBOS784C – NOVEMBER 2016 – REVISED JANUARY 2019
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
Supply voltage, [(V+) – (V−)]
Single-supply voltage
Voltage
Signal input pin
40
Common-mode
(2)
(V–) – 0.5
(V+) + 0.5
–0.5
0.5
–10
10
Differential (3)
Signal input pin
Current
Output short-circuit (4)
–55
Junction, TJ
(2)
(3)
(4)
mA
150
150
Storage, Tstg
(1)
V
Continuous
Operating, TA
Temperature
UNIT
40
–65
°C
150
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Transient conditions that exceed these voltage ratings must be current limited to 10 mA or less.
See the Electrical Overstress section for more information.
Short-circuit to ground, one amplifier per package.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
UNIT
±4000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
V
±1000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
Supply voltage, (V+) – (V–)
Single-supply
Dual-supply
Specified temperature
NOM
MAX
4.5
36
±2.25
±18
–40
125
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UNIT
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V
°C
7
TLV172, TLV2172, TLV4172
SBOS784C – NOVEMBER 2016 – REVISED JANUARY 2019
www.ti.com
7.4 Thermal Information: TLV172
TLV172
THERMAL METRIC (1)
D (SOIC)
DBV (SOT-23)
DCK (SC70)
8 PINS
5 PINS
5 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
126.5
227.9
285.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
80.6
115.7
60.5
°C/W
RθJB
Junction-to-board thermal resistance
67.1
65.9
78.9
°C/W
ψJT
Junction-to-top characterization parameter
31.0
10.7
0.8
°C/W
ψJB
Junction-to-board characterization parameter
65.6
65.3
77.9
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
—
—
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Thermal Information: TLV2172
TLV2172
THERMAL METRIC (1)
D (SOIC)
DGK (VSSOP)
8 PINS
8 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
116.1
158
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
69.8
48.6
°C/W
RθJB
Junction-to-board thermal resistance
56.6
78.7
°C/W
ψJT
Junction-to-top characterization parameter
22.5
3.9
°C/W
ψJB
Junction-to-board characterization parameter
56.1
77.3
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
—
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.6 Thermal Information: TLV4172
TLV4172
THERMAL METRIC
(1)
D (SOIC)
PW (TSSOP)
14 PINS
14 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
82.7
111.1
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
42.3
40.8
°C/W
RθJB
Junction-to-board thermal resistance
37.3
54.1
°C/W
ψJT
Junction-to-top characterization parameter
8.9
3.8
°C/W
ψJB
Junction-to-board characterization parameter
37
53.3
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
—
°C/W
(1)
8
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SBOS784C – NOVEMBER 2016 – REVISED JANUARY 2019
7.7 Electrical Characteristics
at TA = 25°C, VS = ±2.25 V to ±18 V, VCM = VOUT = VS / 2, and RL = 10 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
0.5
1.7
UNIT
OFFSET VOLTAGE
TA = 25°C
VOS
Input offset voltage
dVOS/dT
Input offset voltage drift
TA = –40°C to +125°C
PSRR
Power-supply rejection ratio
VS = 4 V to 36 V, TA = –40°C to +125°C
TA = –40°C to +125°C
mV
2
1
100
Channel separation, dc
µV/°C
120
dB
5
µV/V
INPUT BIAS CURRENT
IB
Input bias current
TA = 25°C
±10
pA
IOS
Input offset current
TA = 25°C
±2
pA
Input voltage noise
f = 0.1 Hz to 10 Hz
2.5
µVPP
f = 100 Hz
14
nV/√Hz
f = 1 kHz
9
nV/√Hz
f = 1 kHz
1.6
fA/√Hz
NOISE
en
Input voltage noise density
in
Input current noise density
INPUT VOLTAGE
VCM
Common-mode voltage range (1)
CMRR
Common-mode rejection ratio
(V–) –
0.1
VS = ±18 V, (V–) – 0.1 V < VCM < (V+) – 2 V,
TA = –40°C to +125°C
94
(V+) – 2
V
116
dB
INPUT IMPEDANCE
Differential
Common-mode
100 || 4
MΩ || pF
6 || 4
1013 Ω ||
pF
OPEN-LOOP GAIN
(V–) + 0.35 V < VO < (V+) – 0.35 V, TA = –40°C to +125°C
AOL
Open-loop voltage gain
97
(V–) + 0.5 V < VO < (V+) – 0.5 V,
RL = 2 kΩ, TA = –40°C to +125°C
115
dB
107
FREQUENCY RESPONSE
GBP
Gain bandwidth product
SR
Slew rate
tS
Settling time
Overload recovery time
THD+N
G = +1
To 0.1%, VS = ±18 V, G = +1, 10-V step
10
MHz
10
V/µs
2
To 0.01% (12-bit), VS = ±18 V, G = +1, 10-V step
µs
3.2
VIN × gain > VS
200
Total harmonic distortion + noise VS = 36 V, G = +1, f = 1 kHz, VO = 3.5 VRMS
ns
0.0002%
OUTPUT
VS = ±18 V, RL = 10 kΩ
VO
Voltage output swing from rail
VS = ±18 V, RL = 2 kΩ
ISC
Short-circuit current
CLOAD
Capacitive load drive
RO
Open-loop output resistance
TA = 25°C
70
TA = –40°C to +125°C
95
TA = 25°C
330
400
TA = –40°C to +125°C
470
530
±75
mV
mA
See Typical Characteristics
f = 1 MHz, IO = 0 A
pF
60
Ω
POWER SUPPLY
VS
Specified voltage range
IQ
Quiescent current per amplifier
(1)
4.5
IO = 0 A, TA = –40°C to +125°C
1.6
36
V
2.3
mA
The input range can be extended beyond (V+) – 2 V up to V+. See the Typical Characteristics and Application and Implementation
sections for additional information.
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7.8 Typical Characteristics
at VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
Table 1. Characteristic Performance Measurements
10
DESCRIPTION
FIGURE
Offset Voltage Production Distribution
Figure 1
Offset Voltage vs Common-Mode Voltage
Figure 2
Offset Voltage vs Common-Mode Voltage (Upper Stage)
Figure 3
Input Bias Current vs Temperature
Figure 4
Output Voltage Swing vs Output Current (Maximum Supply)
Figure 5
CMRR and PSRR vs Frequency (Referred-to-Input)
Figure 6
0.1-Hz to 10-Hz Noise
Figure 7
Input Voltage Noise Spectral Density vs Frequency
Figure 8
Quiescent Current vs Supply Voltage
Figure 9
Open-Loop Gain and Phase vs Frequency
Figure 10
Closed-Loop Gain vs Frequency
Figure 11
Open-Loop Output Impedance vs Frequency
Figure 12
Small-Signal Overshoot vs Capacitive Load
Figure 13, Figure 14
No Phase Reversal
Figure 15
Small-Signal Step Response (10 mV)
Figure 16, Figure 17
Large-Signal Step Response
Figure 18, Figure 19
Large-Signal Settling Time
Figure 20, Figure 21
Short-Circuit Current vs Temperature
Figure 22
Maximum Output Voltage vs Frequency
Figure 23
EMIRR IN+ vs Frequency
Figure 24
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SBOS784C – NOVEMBER 2016 – REVISED JANUARY 2019
at VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
225
VCM = -18.1 V
VCM = 16 V
150
20
Offset Voltage(PV)
Percentage of Amplifiers ( )
25
15
10
75
0
-75
5
-150
0
-1
-0.8 -0.6 -0.4 -0.2
0.0
0.2
0.4
0.6
0.8
Offset Voltage (mV)
-225
-20
1
-10
-5
0
5
10
Common-Mode Voltage (V)
15
20
D001
5 typical units shown, VS = ±18 V
Distribution taken from 5185 amplifiers
Figure 2. Offset Voltage vs Common-Mode Voltage
Figure 1. Offset Voltage Production Distribution Histogram
8000
20
IB+
IBIOS
10
Input Bias Current (pA)
6000
Offset Voltage (mV)
-15
D013
0
-10
-20
-30
4000
2000
0
-40
-50
14
15
16
17
Common-Mode Voltage (V)
-2000
-50
18
-25
0
D015
25
50
75
Temperature (qC)
100
125
150
D009
5 typical units shown, VS = ±18 V
Figure 4. Input Bias Current vs Temperature
160
(V+) + 1
(V +)
(V +) - 1
(V+) - 2
(V+) - 3
(V+) - 4
(V +) - 5
(V- )+ 5
(V - )+ 4
(V - ) + 3
(V - ) +2
(V - ) +1
(V - )
(V -) - 1
125°C
85°C
25°C
-40°C
~
~
~
~
Common-Mode Rejsction Ratio (dB),
Power-Supply Rejection Ratio (dB)
Output Voltage (V)
Figure 3. Offset Voltage vs Common-Mode Voltage
(Upper Stage)
140
120
100
80
60
40
+PSRR
-PSRR
CMRR
20
0
0
10
20
30
40
50
60
70
Output Current (mA)
80
90
100
Figure 5. Output Voltage Swing vs Output Current
(Maximum Supply)
1
10
D008
100
1k
10k
Frequency (Hz)
100k
1M
D012
Figure 6. CMRR and PSRR vs Frequency (Referred-to-Input)
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1mV/div
Noise Spectral Density (nV/rtHz)
at VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
100
10
1
1
10
100
1k
10k
100k
Frequency (Hz)
Figure 7. 0.1-Hz to 10-Hz Noise
Figure 8. Input Voltage Noise Spectral Density vs Frequency
140
120
1.6
100
1.5
80
Gain (dB)
1.7
1.4
1.3
180
Open-Loop Gain
Phase
135
60
90
40
1.2
20
1.1
0
45
-20
1
0
4
8
12
16
20
24
Supply Voltage (V)
28
32
Phase (q)
1.8
Quiescent Current (mA)
C001
0
1
36
10
100
D007
1k
10k
100k
Frequency (Hz)
1M
10M
D004
CLOAD = 15 pF
Figure 9. Quiescent Current vs Supply Voltage
Figure 10. Open-Loop Gain and Phase vs Frequency
100
25
20
15
10
5
ZO (:)
Gain (dB)
10
0
-5
-10
-15
-20
1000
1
G = +1
G = -10
G = -1
10k
100k
1M
10M
Frequency (Hz)
Figure 11. Closed-Loop Gain vs Frequency
12
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10
100
1k
C003
10k
100k
Frequency (Hz)
1M
10M
100M
D017
Figure 12. Open-Loop Output Impedance vs Frequency
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at VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
60
RI = 1 k
50
RF = 1 k
+ 18 V
50
-
+
VIN = 100mV
-
40
CL
± 18 V
40
Overshoot (%)
Overshoot (%)
ROUT
+
30
20
30
20
+ 18 V
ROUT = 0
10
ROUT= 0
10
R
25
RO
OUT==25
R
RO
= 25
25
OUT =
100p
200p
300p
400p
500p
Capacitive Load (F)
RL
CL
± 18 V
RO
= 50
50
R
OUT =
0
0p
ROUT
+
+
VIN = 100mV
-
R
50
RO
OUT==50
0
-
0p
100p
200p
300p
400p
500p
Capacitive Load (F)
C013
100-mV output step, G = –1
C013
100-mV output step, G = 1
Figure 13. Small-Signal Overshoot vs Capacitive Load
Figure 14. Small-Signal Overshoot vs Capacitive Load
+ 18 V
+18 V
-
VOUT
+
37 VPP
Sine Wave
(±18.5 V)
+
+
-18 V
+
VIN = 10 mV
- 18 V
CL
-
5 V/div
2 mV/div
-
VOUT
VIN
Time (200 µs/div)
Time (200 ns/div)
D011
D016
CL = 10 pF
Figure 15. No Phase Reversal
10-mV step
Figure 16. Small-Signal Step Response
+ 18 V
+
+
- 18 V
CL
-
2 V/div
2 mV/div
VIN = 10 mV
RI = 1 NW
RF = 1 NW
+18 V
VIN = 10 mV
+
-
+
RL
CL
-18 V
Copyright © 2016, Texas Instruments Incorporated
Time (200 ns/div)
Time (500 ns/div)
D006
RL = 1 kΩ
CL = 10 pF
D014
10-mV step
Figure 17. Small-Signal Step Response
CL = 10 pF
Figure 18. Large-Signal Step Response
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at VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
2 V/div
Output Delta from Final Value (mV)
20
RI = 1 NW
RF = 1 NW
+18 V
VIN = 10 V
+
-
-
15
10
5
0
-5
0.1% Settling = ±10 mV
-10
-15
+
RL
CL
-20
-18 V
0
0.5
1
1.5
D005
RL = 1 kΩ
2.5
3
3.5
4
4.5
10-V positive step
G=1
5
C034
CL = 10 pF
CL = 10 pF
Figure 20. Large-Signal Settling Time
Figure 19. Large-Signal Step Response
20
100
ISC, Sink ±18 V
ISC, Source ±18 V
15
10
75
5
ISC (mA)
Output Delta from Final Value (mV)
2
Time (s)
Time (500 ns/div)
0
-5
50
0.1% Settling = ±10 mV
-10
25
-15
-20
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
Time (s)
10-V negative step
5
0
-75
C034
30
Output Voltage (VPP )
20
VS = ±15 V
VS = ±5 V
VS = ±2.25 V
15
10
5
0
100k
1M
Frequency (Hz)
10M
EMIRR IN+ (dB)
Maximum output voltage without
slew-rate induced distortion.
10k
-25
160
150
140
130
120
110
100
90
80
70
60
50
40
30
20
10
0
10M
Figure 23. Maximum Output Voltage vs Frequency
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25
50
75
Temperature (qC)
100
125
150
D010
100M
1G
Frequency (Hz)
C033
PRF = –10 dBm
14
0
Figure 22. Short-Circuit Current vs Temperature
Figure 21. Large-Signal Settling Time
25
-50
CL = 10 pF
G=1
VSUPPLY = ±18 V
10G
D018
VCM = 0 V
Figure 24. EMIRR IN+ vs Frequency
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8 Detailed Description
8.1 Overview
The TLVx172 operational amplifier provides high overall performance, making these devices designed for many
general-purpose applications. The excellent offset drift of only 1 μV/°C provides excellent stability over the entire
temperature range. In addition, the device offers very good overall performance with high CMRR, PSRR, and
AOL.
8.2 Functional Block Diagram
PCH
FF Stage
Ca
Cb
+IN
PCH
Input Stage
2nd Stage
Output
Stage
OUT
-IN
NCH
Input Stage
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8.3 Feature Description
8.3.1 Operating Characteristics
The TLVx172 amplifier is specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V). Many of the
specifications apply from –40°C to +125°C. Parameters that can exhibit significant variance with regard to
operating voltage or temperature are shown in the Typical Characteristics section.
8.3.2 Phase-Reversal Protection
The TLVx172 device has an internal phase-reversal protection. Many operational amplifiers exhibit a phase
reversal when the input is driven beyond the linear common-mode range. This condition is most often
encountered in noninverting circuits when the input is driven beyond the specified common-mode voltage range,
causing the output to reverse into the opposite rail. The input of the TLVx172 prevents phase reversal with
excessive common-mode voltage. Instead, the output limits into the appropriate rail. This performance is shown
in Figure 25.
+18 V
VOUT
+
37 VPP
Sine Wave
(-18.5V)
VOUT
-18 V
5 V/div
-
+
VIN
Time (200 ms/div)
Figure 25. No Phase Reversal
8.3.3 Electrical Overstress
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress.
These questions tend to focus on the device inputs, but can involve the supply voltage pins or even the output
pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown
characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.
Additionally, internal electrostatic discharge (ESD) protection is built into these circuits for protection from
accidental ESD events both before and during product assembly.
A good understanding of this basic ESD circuitry and the relevance to an electrical overstress event is helpful.
Figure 26 shows the ESD circuits contained in the TLVx172 (indicated by the dashed box). The ESD protection
circuitry involves several current-steering diodes connected from the input and output pins and routed back to the
internal power-supply lines, where the diodes meet at an absorption device internal to the operational amplifier.
This protection circuitry is intended to remain inactive during normal circuit operation.
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Feature Description (continued)
TVS
+
±
RF
+VS
R1
IN±
RS
IN+
2.5 NŸ
2.5 NŸ
+
Power-Supply
ESD Cell
ID
VIN
RL
+
±
+
±
±VS
TVS
Figure 26. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application
An ESD event produces a short-duration, high-voltage pulse that is transformed into a short-duration, highcurrent pulse when discharging through a semiconductor device. The ESD protection circuits are designed to
provide a current path around the operational amplifier core to prevent damage. The energy absorbed by the
protection circuitry is then dissipated as heat.
When an ESD voltage develops across two or more amplifier device pins, current flows through one or more
steering diodes. Depending on the path that the current takes, the absorption device can activate. The absorption
device has a trigger, or threshold voltage, that is above the normal operating voltage of the TLVx172 but below
the device breakdown voltage level. When this threshold is exceeded, the absorption device quickly activates
and clamps the voltage across the supply rails to a safe level.
When the operational amplifier connects into a circuit, as shown in Figure 26, the ESD protection components
are intended to remain inactive and do not become involved in the application circuit operation. However,
circumstances can arise where an applied voltage exceeds the operating voltage range of a given pin. If this
condition occurs, there is a risk that some internal ESD protection circuits can turn on and conduct current. Any
such current flow occurs through steering-diode paths and rarely involves the absorption device.
Figure 26 shows a specific example where the input voltage (VIN) exceeds the positive supply voltage (V+) by
500 mV or more. Much of what happens in the circuit depends on the supply characteristics. If V+ can sink the
current, then one of the upper input steering diodes conducts and directs current to V+. Excessively high current
levels can flow with increasingly higher VIN. As a result, the data sheet specifications recommend that
applications limit the input current to 10 mA.
If the supply is not capable of sinking the current, VIN can begin sourcing current to the operational amplifier and
then take over as the source of positive supply voltage. The danger in this case is that the voltage can rise to
levels that exceed the operational amplifier absolute maximum ratings.
Another common question involves what happens to the amplifier if an input signal is applied to the input when
the power supplies (V+ or V–) are at 0 V. Again, this question depends on the supply characteristic when at 0 V,
or at a level below the input signal amplitude. If the supplies appear as high impedance, then the input source
supplies the operational amplifier current through the current-steering diodes. This state is not a normal bias
condition; most likely, the amplifier does not operate normally. If the supplies are low impedance, then the current
through the steering diodes can become quite high. The current level depends on the ability of the input source
to deliver current and any resistance in the input path.
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Feature Description (continued)
If there is any uncertainty about the ability of the supply to absorb this current, add external Zener diodes to the
supply pins; see Figure 26. Select the Zener voltage so that the diode does not turn on during normal operation.
However, the Zener voltage must be low enough so that the Zener diode conducts if the supply pin begins to rise
above the safe-operating, supply-voltage level.
The input pins of the TLVx172 are protected from excessive differential voltage with back-to-back diodes; see
Figure 26. In most circuit applications, the input protection circuitry has no effect. However, in low-gain or G = 1
circuits, fast-ramping input signals can forward-bias these diodes because the output of the amplifier cannot
respond rapidly enough to the input ramp. If the input signal is fast enough to create this forward-bias condition,
then limit the input signal current to 10 mA or less. If the input signal current is not inherently limited, an input
series resistor can limit the input signal current. This input series resistor degrades the low-noise performance of
the TLVx172. Figure 26 shows an example configuration that implements a current-limiting feedback resistor.
8.3.4 Capacitive Load and Stability
The dynamic characteristics of the TLVx172 are optimized for common operating conditions. The combination of
low closed-loop gain and high capacitive loads decreases the phase margin of the amplifier and can lead to gain
peaking or oscillations. As a result, heavier capacitive loads must be isolated from the output. The simplest way
to achieve this isolation is to add a small resistor (for example, ROUT equal to 50 Ω) in series with the output.
Figure 27 and Figure 28 show graphs of small-signal overshoot versus capacitive load for several values of
ROUT. See the Feedback Plots Define Op Amp AC Performance application note for details of analysis
techniques and application circuits.
60
RI = 1 k
50
RF = 1 k
+ 18 V
50
-
+
VIN = 100mV
40
CL
± 18 V
40
Overshoot (%)
Overshoot (%)
ROUT
+
-
30
20
30
20
+ 18 V
ROUT = 0
10
ROUT= 0
10
-
R
RO
= 25
25
OUT =
R
25
RO
OUT==25
+
VIN = 100mV
ROUT
+
RL
CL
± 18 V
-
R
50
RO
OUT==50
0
0p
100p
200p
300p
Capacitive Load (F)
400p
500p
Figure 27. Small-Signal Overshoot vs Capacitive Load
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0p
100p
200p
300p
Capacitive Load (F)
C013
100-mV output step, G = –1
18
RO
= 50
50
R
OUT =
0
400p
500p
C013
100-mV output step, G = 1
Figure 28. Small-Signal Overshoot vs Capacitive Load
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8.4 Device Functional Modes
8.4.1 Common-Mode Voltage Range
The input common-mode voltage range of the TLVx172 device extends 100 mV below the negative rail and
within 2 V of the top rail for normal operation.
This device can operate with full rail-to-rail input 100 mV beyond the top rail, but with reduced performance within
2 V of the top rail. Table 2 lists the typical performances in this range.
Table 2. Typical Performance for Common-Mode Voltages Within 2 V of the Positive Supply
PARAMETER
MIN
Input common-mode voltage
TYP
(V+) – 2
MAX
(V+) + 0.1
UNIT
V
Offset voltage
7
mV
Offset voltage vs temperature
12
µV/°C
Common-mode rejection
65
dB
Open-loop gain
60
dB
Gain-bandwidth product
0.3
MHz
Slew rate
0.3
V/µs
8.4.2 Overload Recovery
Overload recovery is defined as the time required for the operational amplifier output to recover from the
saturated state to the linear state. The output devices of the operational amplifier enter the saturation region
when the output voltage exceeds the rated operating voltage, which is a result from the high input voltage or the
high gain. After the device enters the saturation region, the charge carriers in the output devices require time to
return back to the normal state. After the charge carriers return back to the equilibrium state, the device begins to
slew at the normal slew rate. As a result, the propagation delay in case of an overload condition is the sum of the
overload recovery time and the slew time. The overload recovery time for the TLVx172 is approximately 2 µs.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TLVx172 operational amplifier provides high overall performance in a large number of general-purpose
applications. As with all amplifiers, applications with noisy or high-impedance power supplies require decoupling
capacitors placed close to the device pins. In most cases, 0.1-µF capacitors are adequate. Follow the additional
recommendations in the Layout Guidelines section to achieve the maximum performance from this device. Many
applications introduce capacitive loading to the output of the amplifier (which potentially causes instability). To
stabilize the amplifier, add an isolation resistor between the amplifier output and the capacitive load. Typical
Application section shows the process for selecting a resistor.
9.2 Typical Application
This circuit can drive capacitive loads (such as cable shields, reference buffers, MOSFET gates, and diodes).
The circuit uses an isolation resistor (RISO) to stabilize the output of an operational amplifier. RISO modifies the
open-loop gain of the system to ensure that the circuit has sufficient phase margin.
+VS
VOUT
RISO
+
VIN
+
±
CLOAD
-VS
Copyright © 2017, Texas Instruments Incorporated
Figure 29. Unity-Gain Buffer With RISO Stability Compensation
9.2.1 Design Requirements
The design requirements are:
• Supply voltage: 30 V (±15 V)
• Capacitive loads: 100 pF, 1000 pF, 0.01 μF, 0.1 μF, and 1 μF
• Phase margin: 45° and 60°
9.2.2 Detailed Design Procedure
Figure 29 shows a unity-gain buffer driving a capacitive load. Equation 1 shows the transfer function for the
circuit in Figure 29.Figure 29 does not show the open-loop output resistance of the operational amplifier (Ro).
1 + CLOAD × RISO × s
T(s) =
1 + Ro + RISO × CLOAD × s
(1)
The transfer function in Equation 1 has a pole and a zero. The frequency of the pole (fp) is determined by (Ro +
RISO) and CLOAD. The RISO and CLOAD components determine the frequency of the zero (fz). A stable system is
obtained by selecting RISO so that the rate of closure (ROC) between the open-loop gain (AOL) and 1/β is 20 dB
per decade. Figure 30 shows the concept. The 1/β curve for a unity-gain buffer is 0 dB.
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Typical Application (continued)
120
AOL
100
1
fp
2 u Πu RISO
Gain (dB)
80
60
Ro
u CLOAD
40 dB
fz
40
1
2 u Πu RISO u CLOAD
1 dec
1/
20
ROC
20 dB
dec
0
10
100
1k
10k
100k
1M
10M
100M
Frequency (Hz)
Figure 30. Unity-Gain Amplifier With RISO Compensation
Typically, ROC stability analysis is simulated. The validity of the analysis depends on multiple factors, especially
the accurate modeling of Ro. In addition to simulating the ROC, a robust stability analysis includes a
measurement of overshoot percentage and AC gain peaking of the circuit using a function generator,
oscilloscope, and gain and phase analyzer. Phase margin is then calculated from these measurements. Table 3
shows the overshoot percentage and AC gain peaking that correspond to phase margins of 45° and 60°. For
more details on this design and other alternative devices that can replace the TLVx172, see the Capacitive Load
Drive Solution Using an Isolation Resistor precision design.
Table 3. Phase Margin versus Overshoot and AC Gain
Peaking
PHASE
MARGIN
OVERSHOOT
AC GAIN PEAKING
45°
23.3%
2.35 dB
60°
8.8%
0.28 dB
9.2.3 Application Curve
The values of RISO that yield phase margins of 45º and 60º for various capacitive loads are determined using the
described methodology. Figure 31 shows the results.
1000
60° Phase Margin
45° Phase Margin
RISO (Ÿ)
100
10
1
0.01
0.1
1
10
100
CLOAD (nF)
1000
C041
Figure 31. Isolation Resistor Required for Various Capacitive Loads to Achieve a Target Phase Margin
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10 Power Supply Recommendations
The TLVx172 is specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V); many specifications apply from
–40°C to +125°C. Parameters that can exhibit significant variance with regard to operating voltage or
temperature are shown in the Typical Characteristics section.
CAUTION
Supply voltages larger than 40 V can permanently damage the device; see the
Absolute Maximum Ratings table.
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or highimpedance power supplies. For more detailed information on bypass capacitor placement, see the Layout
section.
11 Layout
11.1 Layout Guidelines
For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and the
operational amplifier itself. Bypass capacitors are used to reduce the coupled noise by providing lowimpedance power sources local to the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for singlesupply applications.
• Separate grounding for analog and digital portions of the circuitry is one of the simplest and mosteffective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to
ground planes. A ground plane helps distribute heat and reduces electromagnetic interference (EMI)
noise pickup. Make sure to physically separate digital and analog grounds, paying attention to the flow of
the ground current.
• In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicularly is much
better than in parallel with the noisy trace.
• Place the external components as close to the device as possible. As shown in Figure 33, keeping RF
and RG close to the inverting input minimizes parasitic capacitance.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly
reduce leakage currents from nearby traces that are at different potentials.
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11.2 Layout Example
VIN
+
VOUT
RG
RF
Copyright © 2016, Texas Instruments Incorporated
Figure 32. Schematic Representation
Place components
close to device
and to each other
to reduce parasitic
errors
Run the input traces
as far away from
the supply lines
as possible
VS+
RF
N/C
N/C
GND
±IN
V+
VIN
+IN
OUTPUT
V±
N/C
RG
Use low-ESR,
ceramic bypass
capacitor
GND
VS±
GND
Use low-ESR,
ceramic bypass
capacitor
VOUT
Copyright © 2016, Texas Instruments Incorporated
Figure 33. Operational Amplifier Board Layout for a Noninverting Configuration
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.1.2 Development Support
12.1.2.1 TINA-TI™ (Free Software Download)
TINA-TI™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINATI™ is a free, fully-functional version of the TINA software, preloaded with a library of macromodels in addition to
a range of both passive and active models. TINA-TI™ provides all the conventional dc, transient, and frequency
domain analysis of SPICE, as well as additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI™ offers extensive post-processing
capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select
input waveforms and probe circuit nodes, voltages, and waveforms, thus creating a dynamic quick-start tool.
NOTE
These files require that either the TINA software (from DesignSoft™) or the TINA-TI™
software be installed. Download the free TINA-TI™ software from the TINA-TI™ folder.
12.1.2.2 DIP Adapter EVM
The DIP Adapter EVM tool provides an easy, low-cost way to prototype small surface-mount devices. The
evaluation tool uses these TI packages: D or U (SOIC-8), PW (TSSOP-8), DGK (VSSOP-8), DBV (SOT23-6,
SOT23-5, and SOT23-3), DCK (SC70-6 and SC70-5), and DRL (SOT563-6). The DIP adapter EVM can also be
used with terminal strips or can be wired directly to existing circuits.
12.1.2.3 Universal Op Amp EVM
The Universal Op Amp EVM is a series of general-purpose, blank circuit boards that simplify prototyping circuits
for a variety of device package types. The evaluation module board design allows many different circuits to be
constructed easily and quickly. Five models are offered, with each model intended for a specific package type.
PDIP, SOIC, VSSOP, TSSOP, and SOT23 packages are all supported.
NOTE
These boards are unpopulated, so users must provide their own devices. TI recommends
requesting several op amp device samples when ordering the Universal Op Amp EVM.
12.1.2.4 TI Precision Designs
TI precision designs are analog solutions created by TI’s precision analog applications experts and offer the
theory of operation, component selection, simulation, a complete PCB schematic and layout, bill of materials, and
measured performance of many useful circuits. TI precision designs are available online at
www.ti.com/ww/en/analog/precision-designs/.
12.1.2.5 WEBENCH® Filter Designer
The WEBENCH® Filter Designer is a simple, powerful, and easy-to-use active filter design program. The
WEBENCH® Filter Designer allows optimized filter designs to be created by using a selection of TI operational
amplifiers and passive components from TI's vendor partners.
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TLV172, TLV2172, TLV4172
www.ti.com
SBOS784C – NOVEMBER 2016 – REVISED JANUARY 2019
Device Support (continued)
Available as a web-based tool from the WEBENCH® design center, the WEBENCH® filter designer allows
complete multistage active filter solutions to be designed, optimized, and simulated within minutes.
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation see the following:
• Feedback Plots Define Op Amp AC Performance
• EMI Rejection Ratio of Operational Amplifiers
• Compensate Transimpedance Amplifiers Intuitively
• Noise Analysis for High-Speed Op Amps
12.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 4. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TLV172
Click here
Click here
Click here
Click here
Click here
TLV2172
Click here
Click here
Click here
Click here
Click here
TLV4172
Click here
Click here
Click here
Click here
Click here
12.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.5 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.6 Trademarks
TINA-TI, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
DesignSoft is a trademark of DesignSoft, Inc.
12.7 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
Copyright © 2016–2019, Texas Instruments Incorporated
Product Folder Links: TLV172 TLV2172 TLV4172
Submit Documentation Feedback
25
TLV172, TLV2172, TLV4172
SBOS784C – NOVEMBER 2016 – REVISED JANUARY 2019
www.ti.com
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
26
Submit Documentation Feedback
Copyright © 2016–2019, Texas Instruments Incorporated
Product Folder Links: TLV172 TLV2172 TLV4172
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TLV172IDBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
18VV
TLV172IDBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
18VV
TLV172IDCKR
ACTIVE
SC70
DCK
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
15W
TLV172IDCKT
ACTIVE
SC70
DCK
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
15W
TLV172IDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TLV172
TLV2172IDGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
14P6
TLV2172IDGKT
ACTIVE
VSSOP
DGK
8
250
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
14P6
TLV2172IDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TL2172
TLV4172IDR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
TLV4172
TLV4172IPWR
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TLV4172
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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