SGLS192B − OCTOBER 2003 − REVISED APRIL 2008
D Qualified for Automotive Applications
D ESD Protection Exceeds 2000 V Per
D
D
D
D
MIL-STD-883, Method 3015; Exceeds 150 V
(TLV2252/52A) and 100 V (TLV2254/54A)
Using Machine Model (C = 200 pF, R = 0)
Output Swing Includes Both Supply Rails
Low Noise . . . 19 nV/√Hz Typ at f = 1 kHz
Low Input Bias Current . . . 1 pA Typ
Fully Specified for Both Single-Supply and
Split-Supply Operation
D Very Low Power . . . 34 µA Per Channel Typ
D Common-Mode Input Voltage Range
Includes Negative Rail
D Low Input Offset Voltage
D
D
850 µV Max at TA = 25°C
Wide Supply Voltage Range
2.7 V to 16 V
Macromodel Included
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
description
3
VDD = 3 V
VOH − High-Level Output Voltage − V
The TLV2252 and TLV2254 are dual and
quadruple low-voltage operational amplifiers from
Texas Instruments. Both devices exhibit rail-to-rail
output performance for increased dynamic range
in single- or split-supply applications. The
TLV225x family consumes only 34 µA of supply
current per channel. This micropower operation
makes them good choices for battery-powered
applications. This family is fully characterized at
3 V and 5 V and is optimized for low-voltage
applications. The noise performance has been
dramatically improved over previous generations
of CMOS amplifiers. The TLV225x has a noise
level of 19 nV/√Hz at 1kHz, four times lower than
competitive micropower solutions.
2.5
TA = − 40°C
2
TA = 25°C
1.5
TA = 85°C
1
TA = 125°C
0.5
The TLV225x, exhibiting high input impedance
and low noise, are excellent for small-signal
0
600
800
0
200
400
conditioning for high-impedance sources, such as
| IOH | − High-Level Output Current − µ A
piezoelectric transducers. Because of the micropower dissipation levels combined with 3-V
Figure 1
operation, these devices work well in hand-held
monitoring and remote-sensing applications. In addition, the rail-to-rail output feature with single or split supplies
makes this family a great choice when interfacing with analog-to-digital converters (ADCs). For precision
applications, the TLV225xA family is available and has a maximum input offset voltage of 850 µV.
The TLV2252/4 also make great upgrades to the TLV2322/4 in standard designs. They offer increased output
dynamic range, lower noise voltage, and lower input offset voltage. This enhanced feature set allows them to
be used in a wider range of applications. For applications that require higher output drive and wider input voltage
range, see the TLV2432 and TLV2442 devices. If your design requires single amplifiers, please see the
TLV2211/21/31 family. These devices are single rail-to-rail operational amplifiers in the SOT-23 package. Their
small size and low power consumption, make them ideal for high density, battery-powered equipment.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Advanced LinCMOS is a trademark of Texas Instruments.
Copyright 2008 Texas Instruments Incorporated
!" ! #$%&'$ ( )%%' ( $# *)+,'$ ' %$ )'( $#$%& '$ (*#'$( *% '. '%&( $# ( ('%)&'(
(' % /%%'0- %$ )'$ *%$((1 $( $' ((%,0 ,)
'('1 $# ,, *%&'%(-
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SGLS192B − OCTOBER 2003 − REVISED APRIL 2008
ORDERING INFORMATION†
VIOmax
AT 25°C
TA
850 µV
V
−40°C to 125°C
V
1500 µV
850 µV
V
−40°C to 125°C
1500 µV
V
ORDERABLE
PART NUMBER
PACKAGE‡
SOIC (D)
Tape and reel
TLV2252AQDRQ1
TSSOP (PW)
Tape and reel
TLV2252AQPWRQ1§
SOIC (D)
Tape and reel
TLV2252QDRQ1
TSSOP (PW)
Tape and reel
TLV2252QPWRQ1§
SOIC (D)
Tape and reel
TLV2254AQDRQ1
TSSOP (PW)
Tape and reel
TLV2254AQPWRQ1§
SOIC (D)
Tape and reel
TLV2254QDRQ1
TSSOP (PW)
Tape and reel
TLV2254QPWRQ1§
TOP-SIDE
MARKING
2252AQ
2252Q1
TLV2254AQ1
TLV2254Q1
† For the most current package and ordering information, see the Package Option Addendum at the end of this document,
or see the TI web site at http://www.ti.com.
‡ Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging.
§ Product preview
TLV2252, TLV2252A
D OR PW PACKAGE
(TOP VIEW)
1OUT
1IN −
1IN +
VDD − /GND
2
1
8
2
7
3
6
4
5
VDD +
2OUT
2IN −
2IN +
TLV2254, TLV2254A
PW PACKAGE
(TOP VIEW)
TLV2254, TLV2254A
D PACKAGE
(TOP VIEW)
1OUT
1IN −
1IN +
VDD +
2IN +
2IN −
2OUT
1
14
2
13
3
12
4
11
5
10
6
9
7
8
POST OFFICE BOX 655303
4OUT
4IN −
4IN +
VDD − / GND
3IN +
3IN −
3OUT
• DALLAS, TEXAS 75265
1OUT
1IN −
1IN +
VDD+
2IN +
2IN −
2OUT
1
7
14
8
4OUT
4IN −
4IN +
VDD − / GND
3IN +
3IN −
3OUT
IN −
IN +
Q1
Q5
R4
Q2
R3
Q3
Q4
equivalent schematic (each amplifier)
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Q10
R6
Q9
3
Capacitors
6
18
56
76
TLV2254
† Includes both amplifiers and all ESD, bias, and trim circuitry
9
30
Resistors
Diodes
38
TLV2252
Transistors
R1
Q13
C1
Q12
VDD −/ GND
Q11
R5
ACTUAL DEVICE COMPONENT COUNT†
Q8
COMPONENT
Q7
Q6
VDD +
R2
Q15
Q14
D1
Q17
Q16
OUT
2
2
2 2 2
SGLS192A − OCTOBER 2003 − REVISED MARCH 2004
3
SGLS192A − OCTOBER 2003 − REVISED MARCH 2004
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 V
Differential input voltage, VID (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±VDD
Input voltage range, VI (any input, see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD − −0.3 V to VDD+
Input current, II (each input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±5 mA
Output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Total current into VDD + . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Total current out of VDD − . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Duration of short-circuit current (at or below) 25°C (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . unlimited
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, TA: Q Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D and PW packages . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential voltages, are with respect to VDD − .
2. Differential voltages are at the noninverting input with respect to the inverting input. Excessive current flows when input is brought
below VDD − − 0.3 V.
3. The output may be shorted to either supply. Temperature and /or supply voltages must be limited to ensure that the maximum
dissipation rating is not exceeded.
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
25 C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
85°C
TA = 85
C
POWER RATING
125°C
TA = 125
C
POWER RATING
D−8
725 mW
5.8 mW/°C
377 mW
145 mW
D−14
950 mW
7.6 mW/°C
494 mW
190 mW
PW−8
525 mW
4.2 mW/°C
273 mW
105 mW
PW−14
700 mW
5.6 mW/°C
364 mW
140 mW
recommended operating conditions
Supply voltage, VDD
Input voltage range, VI
MAX
2.7
16
VDD −
VDD −
Common-mode input voltage, VIC
Operating free-air temperature, TA
NOTE 1: All voltage values, except differential voltages, are with respect to VDD − .
4
MIN
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
−40
UNIT
V
VDD + − 1.3
VDD + − 1.3
V
125
°C
V
SGLS192A − OCTOBER 2003 − REVISED MARCH 2004
TLV2252-Q1 electrical characteristics at specified free-air temperature, VDD = 3 V (unless otherwise
noted)
PARAMETER
VIO
Input offset voltage
αVIO
Temperature coefficient
of input offset voltage
Input offset voltage
long-term drift
(see Note 4)
IIO
Input offset current
IIB
Input bias current
TEST CONDITIONS
TA†
25°C
Common-mode input
voltage range
High-level output
voltage
AVD
Low-level output
voltage
Large-signal differential
voltage amplification
1500
VIC = 0,
RS = 50 Ω
200
0.003
µV/mo
25°C
0.5
60
0.5
1000
1
60
1
1000
0
to
2
0
to
1.7
−0.3
to
2.2
0
to
2
0
to
1.7
IOH = − 75 µA
25°C
2.9
2.9
Full range
2.8
2.8
25°C
2.8
2.98
10
25°C
100
Full range
200
Full range
RL = 100 kه
25°C
100
VIC = 1.5 V,
VO = 1 V to 2 V
Full range
10
pA
V
2.98
V
10
150
100
165
IOL = 1 A
RL = 1 Mه
−0.3
to
2.2
pA
2.8
25°C
VIC = 1.5 V,
60
1000
25°C
25°C
60
1000
IOH = − 20 µA
IOL = 500 µA
µV
0.003
|VIO | ≤ 5 mV
VIC = 1.5 V,
850
1000
UNIT
25°C
25°C
IOL = 50 µA
MAX
µV/°C
125°C
RS = 50 Ω
Ω,
TYP
0.5
125°C
IOH = − 150 µA
VIC = 1.5 V,
VOL
200
MIN
0.5
Full range
VOH
MAX
1750
25°C
25
C
to 85°C
VDD ± = ± 1.5 V,
VO = 0,
TLV2252A-Q1
TYP
Full range
25°C
25
C
VICR
TLV2252-Q1
MIN
165
300
200
300
250
150
mV
300
300
100
250
10
V/mV
25°C
800
800
ri(d)
Differential input
resistance
25°C
1012
1012
Ω
ri(c)
Common-mode input
resistance
25°C
1012
1012
Ω
ci(c)
Common-mode input
capacitance
f = 10 kHz
25°C
8
8
pF
zo
Closed-loop output
impedance
f = 25 kHz,
AV = 10
25°C
220
220
Ω
CMRR
Common-mode rejection
ratio
VIC = 0 to 1.7 V,
RS = 50 Ω
VO = 1.5 V,
kSVR
Supply voltage rejection
ratio ((∆V
VDD /∆V
/ VIO)
VDD = 2.7 V to 8 V,
VIC = VDD /2,
No load
IDD
Supply current
VO = 1.5 V,
No load
25°C
65
Full range
60
25°C
80
Full range
80
25°C
Full range
75
65
77
dB
60
95
80
100
dB
80
68
125
150
68
125
150
µA
† Full range is −40°C to 125°C for Q level part.
‡ Referenced to 1.5 V
NOTE 4: Typical values are based on the input offset voltage shift observed through 500 hours of operating life test at TA = 150°C extrapolated
to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
SGLS192A − OCTOBER 2003 − REVISED MARCH 2004
TLV2252-Q1 operating characteristics at specified free-air temperature, VDD = 3 V
PARAMETER
TEST CONDITIONS
VO = 0.8 V to 1.4 V,
CL = 100 pF‡
RL = 100 kه,
TLV2252-Q1
TA†
MIN
TYP
25°C
0.07
0.1
Full
range
0.05
MAX
TLV2252A-Q1
MIN
TYP
0.07
0.1
MAX
UNIT
SR
Slew rate at unity gain
Equivalent input noise
voltage
f = 10 Hz
25°C
35
35
Vn
f = 1 kHz
25°C
19
19
Peak-to-peak
equivalent input
noise voltage
f = 0.1 Hz to 1 Hz
25°C
0.6
0.6
VN(PP)
f = 0.1 Hz to 10 Hz
25°C
1.1
1.1
In
Equivalent input noise
current
25°C
0.6
0.6
25°C
0.187
0.187
MHz
25°C
60
60
kHz
25°C
63°
63°
25°C
15
15
Gain-bandwidth
product
f = 1 kHz,
CL = 100 pF‡
RL = 50 kه,
BOM
Maximum
output-swing
bandwidth
VO(PP) = 1 V,
RL = 50 kه,
AV = 1,
CL = 100 pF‡
φm
Phase margin at unity
gain
RL = 50 kه,
CL = 100 pF‡
Gain margin
† Full range is −40°C to 125°C for Q level part.
‡ Referenced to 1.5 V
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
V/µs
0.05
nV/√Hz
µV
V
fA /√Hz
dB
SGLS192A − OCTOBER 2003 − REVISED MARCH 2004
TLV2252-Q1 electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise
noted)
PARAMETER
VIO
Input offset voltage
αVIO
Temperature coefficient
of input offset voltage
Input offset voltage longterm drift (see Note 4)
IIO
Input offset current
IIB
Input bias current
VICR
Common-mode input
voltage range
TEST CONDITIONS
High-level output voltage
AVD
Low-level output voltage
Large-signal differential
voltage amplification
MAX
200
1500
VIC = 0,
RS = 50 Ω
VIC = 2.5 V,
IOL = 1 A
VIC = 2.5 V,
VO = 1 V to 4 V
RL = 100 kه
RL = 1 Mه
1000
µV
0.003
0.003
µV/mo
25°C
0.5
60
0.5
1000
1
25°C
0
to
4
60
Full range
0
to
3.5
−0.3
to
4.2
1
4.9
Full range
4.8
25°C
4.8
0
to
4
−0.3
to
4.2
4.9
4.94
4.88
0.09
Full range
4.8
4.88
0.01
0.15
0.09
0.15
0.2
Full range
100
Full range
10
350
0.15
0.15
0.3
0.2
0.3
25°C
V
4.8
0.01
pA
4.98
4.94
25°C
pA
V
0
to
3.5
25°C
25°C
60
1000
4.98
25°C
60
1000
1000
25°C
IOL = 500 µA
850
25°C
RS = 50 Ω
VIC = 2.5 V,
200
UNIT
µV/°C
25°C
IOL = 50 µA
MAX
0.5
125°C
IOH = − 75 µA
TYP
0.5
125°C
|VIO | ≤ 5 mV,
MIN
1750
25°C
25
C
to 85°C
VDD ± = ± 2.5 V,
VO = 0,
TLV2252A-Q1
TYP
Full range
IOH = − 150 µA
VIC = 2.5 V,
VOL
TLV2252-Q1
MIN
25°C
IOH = − 20 µA
VOH
TA†
V
0.3
0.3
100
350
10
V/mV
25°C
1700
1700
ri(d)
Differential input
resistance
25°C
1012
1012
Ω
ri(c)
Common-mode input
resistance
25°C
1012
1012
Ω
ci(c)
Common-mode input
capacitance
f = 10 kHz
25°C
8
8
pF
zo
Closed-loop output
impedance
f = 25 kHz,
25°C
200
200
Ω
CMRR
Common-mode rejection
ratio
VIC = 0 to 2.7 V,
VO = 2.5 V,
RS = 50 Ω
25°C
70
Full range
70
kSVR
Supply voltage rejection
ratio (∆VDD /∆VIO)
VDD = 4.4 V to 8 V,
VIC = VDD /2,
No load
25°C
80
Full range
80
AV = 10
83
70
83
70
95
80
80
95
dB
dB
† Full range is −40°C to 125°C for Q level part.
‡ Referenced to 2.5 V
NOTE 4: Typical values are based on the input offset voltage shift observed through 500 hours of operating life test at TA = 150°C extrapolated
to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
SGLS192A − OCTOBER 2003 − REVISED MARCH 2004
TLV2252-Q1 electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise
noted) (continued)
PARAMETER
IDD
Supply current
TA†
TEST CONDITIONS
VO = 2.5 V,
No load
TLV2252-Q1
MIN
25°C
TLV2252A-Q1
TYP
MAX
70
125
Full range
MIN
TYP
MAX
70
125
150
150
UNIT
µA
† Full range is −40°C to 125°C for Q level part.
TLV2252-Q1 operating characteristics at specified free-air temperature, VDD = 5 V
PARAMETER
SR
Slew rate at unity gain
TEST CONDITIONS
MIN
TYP
0.12
VO = 1.25 V to 2.75 V,
RL = 100 kkه,
CL = 100 pF‡
25 C
25°C
0.07
Full
range
0.05
MAX
TLV2252A-Q1
MIN
TYP
0.07
0.12
MAX
UNIT
V/µs
0.05
f = 10 Hz
25°C
36
36
f = 1 kHz
25°C
19
19
f = 0.1 Hz to 1 Hz
25°C
0.7
0.7
f = 0.1 Hz to 10 Hz
25°C
1.1
1.1
25°C
0.6
0.6
0.2%
0.2%
1%
1%
25°C
0.2
0.2
MHz
25°C
30
30
kHz
25°C
63°
63°
25°C
15
15
Vn
Equivalent input noise
voltage
VN(PP)
Peak-to-peak
equivalent input
noise voltage
In
Equivalent input noise
current
Total harmonic
distortion plus noise
VO = 0.5 V to 2.5 V,
f = 20 kHz,
RL = 50 kه
AV = 1
THD + N
Gain-bandwidth product
f = 50 kHz,
CL = 100 pF‡
RL = 50 kه,
BOM
Maximum output-swing
bandwidth
VO(PP) = 2 V,
RL = 50 kه,
AV = 1,
CL = 100 pF‡
φm
Phase margin at unity
gain
RL = 50 kه,
CL = 100 pF‡
nV/√Hz
µV
V
fA /√Hz
25°C
AV = 10
Gain margin
† Full range is −40°C to 125°C for Q level part.
‡ Referenced to 2.5 V
8
TLV2252-Q1
TA†
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
dB
SGLS192A − OCTOBER 2003 − REVISED MARCH 2004
TLV2254-Q1 electrical characteristics at specified free-air temperature, VDD = 3 V (unless otherwise
noted)
PARAMETER
VIO
Input offset voltage
αVIO
Temperature coefficient
of input offset voltage
Input offset voltage
longterm drift (see Note 4)
IIO
Input offset current
IIB
Input bias current
VICR
Common-mode input
voltage range
TEST CONDITIONS
High-level output
voltage
25°C
VDD ± = ± 1.5 V,
VO = 0,
VIC = 0,
RS = 50 Ω
Low-level output
voltage
Large-signal differential
voltage amplification
200
1500
IOL = 1 A
VIC = 1.5 V,
VO = 1 V to 2 V
RL = 100 kه
RL = 1 Mه
850
1000
UNIT
µV
25°C
0.003
0.003
µV/mo
25°C
0.5
60
0.5
1000
1
25°C
25
C
0
to
2
60
Full range
0
to
1.7
−0.3
to
2.2
1
0
to
2
−0.3
to
2.2
2.98
Full range
2.8
2.8
25°C
2.8
V
2.8
25°C
10
25°C
100
Full range
10
150
100
165
200
Full range
10
225
150
165
300
200
300
Full range
pA
2.98
2.9
100
pA
V
0
to
1.7
2.9
25°C
60
1000
25°C
25°C
60
1000
1000
25°C
IOL = 500 µA
VIC = 1.5 V,
200
MAX
µV/°C
|VIO | ≤ 5 mV
IOL = 50 µA
TYP
0.5
25°C
IOH = − 75 µA
MIN
0.5
125°C
VIC = 1.5 V,
AVD
MAX
125°C
RS = 50 Ω
Ω,
TLV2254A-Q1
TYP
1750
25°C
25
C
to 125°C
IOH = − 150 µA
VIC = 1.5 V,
VOL
TLV2254-Q1
MIN
Full range
IOH = − 20 µA
VOH
TA†
mV
300
300
100
225
10
V/mV
25°C
800
800
ri(d)
Differential input
resistance
25°C
1012
1012
Ω
ri(c)
Common-mode input
resistance
25°C
1012
1012
Ω
ci(c)
Common-mode input
capacitance
f = 10 kHz
25°C
8
8
pF
zo
Closed-loop output
impedance
f = 25 kHz,
AV = 10
25°C
220
220
Ω
CMRR
Common-mode
rejection ratio
VIC = 0 to 1.7 V,
RS = 50 Ω
VO = 1.5 V,
kSVR
Supply voltage
rejection ratio
(∆VDD /∆VIO)
VDD = 2.7 V to 8 V,
VIC = VDD /2,
No load
25°C
65
Full range
60
25°C
80
Full range
80
75
65
77
60
95
80
dB
100
dB
80
† Full range is −40°C to 125°C for Q level part.
‡ Referenced to 1.5 V
NOTE 4: Typical values are based on the input offset voltage shift observed through 500 hours of operating life test at TA = 150°C extrapolated
to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
9
SGLS192A − OCTOBER 2003 − REVISED MARCH 2004
TLV2254-Q1 electrical characteristics at specified free-air temperature, VDD = 3 V (unless otherwise
noted) (continued)
PARAMETER
IDD
Supply current
(four amplifiers)
TA†
TEST CONDITIONS
VO = 1.5 V,
TLV2254-Q1
MIN
25°C
No load
TLV2254A-Q1
TYP
MAX
135
250
Full range
MIN
TYP
MAX
135
250
300
300
UNIT
µA
† Full range is −40°C to 125°C for Q level part.
TLV2254-Q1 operating characteristics at specified free-air temperature, VDD = 3 V
SR
TLV2254-Q1
PARAMETER
TEST CONDITIONS
TA†
MIN
TYP
VO = 0.5 V to 1.7 V,
RL = 100 kه,
CL = 100 pF‡
25°C
0.07
0.1
Slew rate at unity gain
Full range
0.05
Vn
Equivalent input noise voltage
VN(PP)
Peak-to-peak equivalent input
noise voltage
In
Equivalent input noise current
TLV2254A-Q1
MAX
MIN
TYP
0.07
0.1
MAX
UNIT
V/µs
0.05
f = 10 Hz
25°C
35
35
f = 1 kHz
25°C
19
19
f = 0.1 Hz to 1 Hz
25°C
0.6
0.6
f = 0.1 Hz to 10 Hz
25°C
1.1
1.1
25°C
0.6
0.6
nV/√Hz
µV
V
fA /√Hz
Gain-bandwidth product
f = 1 kHz,
RL = 50 kΩ ‡,
CL = 100 pF ‡
25°C
0.187
0.187
MHz
BOM
Maximum output-swing
bandwidth
VO(PP) = 1 V,
AV = 1,
RL = 50 kه,
CL = 100 pF ‡
25°C
60
60
kHz
φm
Phase margin at unity gain
25°C
63°
63°
25°C
15
15
Gain margin
RL = 50 kه,
CL = 100 pF ‡
† Full range is −40°C to 125°C for Q level part.
‡ Referenced to 1.5 V
10
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
dB
SGLS192A − OCTOBER 2003 − REVISED MARCH 2004
TLV2254-Q1 electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise
noted)
PARAMETER
VIO
Input offset voltage
αVIO
Temperature coefficient
of input offset voltage
Input offset voltage
long-term drift
(see Note 4)
IIO
Input offset current
IIB
Input bias current
VICR
Common-mode input
voltage range
TEST CONDITIONS
VOH
VOL
VDD ± = ± 2.5 V,
VO = 0,
VIC = 0,
RS = 50 Ω
Large-signal differential
voltage amplification
TYP
MAX
200
1500
IOL = 1 A
VIC = 2.5 V,
VO = 1 V to 4 V
RL = 100 kه
RL = 1 Mه
µV
0.003
0.003
µV/mo
25°C
0.5
60
0.5
1000
1
25°C
25
C
0
to
4
60
Full range
0
to
3.5
−0.3
to
4.2
1
4.9
Full range
4.8
25°C
4.8
0
to
4
−0.3
to
4.2
4.9
4.94
4.88
0.09
Full range
4.8
4.88
0.01
0.15
0.09
0.15
0.2
Full range
100
Full range
10
350
0.15
0.15
0.3
0.2
0.3
25°C
V
4.8
25°C
pA
4.98
4.94
0.01
pA
V
0
to
3.5
25°C
25°C
60
1000
4.98
25°C
60
1000
1000
25°C
IOL = 500 µA
850
1000
UNIT
25°C
RS = 50 Ω
VIC = 2.5 V,
200
MAX
µV/°C
25°C
IOL = 50 µA
TYP
0.5
125°C
IOH = − 75 µA
MIN
0.5
125°C
|VIO | ≤ 5 mV,
TLV2254A-Q1
1750
25°C
25
C
to 125°C
VIC = 2.5 V,
AVD
MIN
25°C
IOH = − 150 µA
VIC = 2.5 V,
Low-level output
voltage
TLV2254-Q1
Full range
IOH = − 20 µA
High-level output
voltage
TA†
V
0.3
0.3
100
350
10
V/mV
25°C
1700
1700
ri(d)
Differential input
resistance
25°C
1012
1012
Ω
ri(c)
Common-mode input
resistance
25°C
1012
1012
Ω
ci(c)
Common-mode input
capacitance
f = 10 kHz
25°C
8
8
pF
zo
Closed-loop output
impedance
f = 25 kHz,
AV = 10
25°C
200
200
Ω
CMRR
Common-mode
rejection ratio
VIC = 0 to 2.7 V,
RS = 50 Ω
VO = 2.5 V,
25°C
70
Full range
70
83
70
70
83
dB
Supply voltage
25°C
80
95
80
95
VDD = 4.4 V to 8 V,
rejection ratio
dB
VIC = VDD /2,
No load
Full range
80
80
(∆VDD /∆VIO)
† Full range is −40°C to 125°C for Q level part.
‡ Referenced to 2.5 V
NOTE 4: Typical values are based on the input offset voltage shift observed through 500 hours of operating life test at TA = 150°C extrapolated
to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
kSVR
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
11
SGLS192A − OCTOBER 2003 − REVISED MARCH 2004
TLV2254-Q1 electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise
noted) (continued)
PARAMETER
Supply current
(four amplifiers)
IDD
TA†
TEST CONDITIONS
TLV2254-Q1
MIN
25°C
VO = 2.5 V,
No load
TLV2254A-Q1
TYP
MAX
140
250
Full range
MIN
TYP
MAX
140
250
300
300
UNIT
µA
A
† Full range is −40°C to 125°C for Q level part.
TLV2254-Q1 operating characteristics at specified free-air temperature, VDD = 5 V
PARAMETER
TEST CONDITIONS
RL = 100 kΩ ‡,
TLV2254-Q1
TA†
MIN
TYP
25°C
0.07
0.12
Full
range
0.05
MAX
TLV2254A-Q1
MIN
TYP
0.07
0.12
MAX
UNIT
Slew rate at unity
gain
VO = 0.5 V to 3.5 V,
CL = 100 pF ‡
Equivalent input
noise voltage
f = 10 Hz
25°C
36
36
Vn
f = 1 kHz
25°C
19
19
Peak-to-peak
equivalent input
noise voltage
f = 0.1 Hz to 1 Hz
25°C
0.7
0.7
VN(PP)
f = 0.1 Hz to 10 Hz
25°C
1.1
1.1
In
Equivalent input
noise current
25°C
0.6
0.6
Total harmonic
distortion plus
noise
VO = 0.5 V to 2.5 V,
f = 20 kHz,
RL = 50 kΩ ‡
AV = 1
0.2%
0.2%
THD + N
1%
1%
Gain-bandwidth
product
f = 50 kHz,
CL = 100 pF ‡
RL = 50 kΩ ‡,
25°C
0.2
0.2
MHz
BOM
Maximum outputswing bandwidth
VO(PP) = 2 V,
RL = 50 kΩ ‡,
AV = 1,
CL = 100 pF ‡
25°C
30
30
kHz
φm
Phase margin at
unity gain
RL = 50 kΩ ‡,
CL = 100 pF ‡
25°C
63°
63°
25°C
15
15
SR
nV/√Hz
µV
V
fA /√Hz
25°C
AV = 10
Gain margin
† Full range is −40°C to 125°C for Q level part.
‡ Referenced to 2.5 V
12
V/µs
0.05
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
dB
SGLS192A − OCTOBER 2003 − REVISED MARCH 2004
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
VIO
Input offset voltage
Distribution
vs Common-mode voltage
2−5
6, 7
αVIO
IIB /IIO
Input offset voltage temperature coefficient
Distribution
8 − 11
Input bias and input offset currents
vs Free-air temperature
12
VI
Input voltage
vs Supply voltage
vs Free-air temperature
13
14
VOH
VOL
High-level output voltage
vs High-level output current
15, 18
Low-level output voltage
vs Low-level output current
16, 17, 19
VO(PP)
Maximum peak-to-peak output voltage
vs Frequency
20
IOS
Short-circuit output current
vs Supply voltage
vs Free-air temperature
21
22
VID
AVD
Differential input voltage
vs Output voltage
23, 24
Differential voltage amplification
vs Load resistance
25
AVD
Large-signal differential voltage amplification
vs Frequency
vs Free-air temperature
26, 27
28, 29
zo
Output impedance
vs Frequency
30, 31
CMRR
Common-mode rejection ratio
vs Frequency
vs Free-air temperature
32
33
kSVR
Supply-voltage rejection ratio
vs Frequency
vs Free-air temperature
34, 35
36
IDD
Supply current
vs Supply voltage
37, 38
SR
Slew rate
vs Load capacitance
vs Free-air temperature
VO
VO
Inverting large-signal pulse response
41, 42
Voltage-follower large-signal pulse response
43, 44
VO
VO
Inverting small-signal pulse response
45, 46
Vn
Equivalent input noise voltage
vs Frequency
Input noise voltage
Over a 10-second period
51
Integrated noise voltage
vs Frequency
52
Total harmonic distortion plus noise
vs Frequency
53
Gain-bandwidth product
vs Supply voltage
vs Free-air temperature
54
55
Phase margin
vs Frequency
vs Load capacitance
26, 27
56
Gain margin
vs Load capacitance
57
Unity-gain bandwidth
vs Load capacitance
58
Overestimation of phase margin
vs Load capacitance
59
THD + N
φm
B1
Voltage-follower small-signal pulse response
POST OFFICE BOX 655303
39
40
47, 48
• DALLAS, TEXAS 75265
49, 50
13
SGLS192A − OCTOBER 2003 − REVISED MARCH 2004
TYPICAL CHARACTERISTICS
DISTRIBUTION OF TLV2252
INPUT OFFSET VOLTAGE
DISTRIBUTION OF TLV2252
INPUT OFFSET VOLTAGE
20
20
1020 Amplifiers From 1 Wafer Lot
VDD = ± 2.5 V
TA = 25°C
Precentage of Amplifiers − %
Precentage of Amplifiers − %
1020 Amplifiers From 1 Wafer Lot
VDD = ± 1.5 V
TA = 25°C
15
10
5
0
−1.6
−0.8
0
0.8
VIO − Input Offset Voltage − mV
15
10
5
0
−1.6
1.6
Figure 2
DISTRIBUTION OF TLV2254
INPUT OFFSET VOLTAGE
35
35
682 Amplifiers From 1 Wafer Lot
VDD ± = ± 2.5 V
30 TA = 25°C
Percentage of Amplifiers − %
Percentage of Amplifiers − %
682 Amplifiers From 1 Wafer Lot
VDD ± = ± 1.5 V
30 TA = 25°C
25
20
15
10
5
25
20
15
10
5
−0.8
0
0.8
VIO − Input Offset Voltage − mV
1.6
0
−1.6
Figure 4
14
1.6
Figure 3
DISTRIBUTION OF TLV2254
INPUT OFFSET VOLTAGE
0
−1.6
−0.8
0
0.8
VIO − Input Offset Voltage − mV
−0.8
0
0.8
VIO − Input Offset Voltage − mV
Figure 5
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1.6
SGLS192A − OCTOBER 2003 − REVISED MARCH 2004
TYPICAL CHARACTERISTICS
INPUT OFFSET VOLTAGE†
vs
COMMON-MODE INPUT VOLTAGE
INPUT OFFSET VOLTAGE†
vs
COMMON-MODE INPUT VOLTAGE
1
1
VDD = 3 V
RS = 50 Ω
TA = 25°C
0.8
VIO − Input Offset Voltage − mV
VIO − Input Offset Voltage − mV
0.6
0.4
0.2
0
−0.2
0.6
0.4
0.2
0
−0.2
ÁÁ
ÁÁ
−0.4
ÁÁ
ÁÁ
VDD = 5 V
RS = 50 Ω
TA = 25°C
0.8
−0.6
−0.4
−0.6
−0.8
−0.8
−1
−1
0
1
−1
−1
3
2
0
Figure 6
4
5
25
62 Amplifiers From 1 Wafer Lot
VDD± = ± 1.5 V
P Package
TA = 25°C to 85°C
Percentage of Amplifiers − %
Percentage of Amplifiers − %
3
DISTRIBUTION OF TLV2252 INPUT OFFSET
VOLTAGE TEMPERATURE COEFFICIENT †
25
15
10
5
0
−2
2
Figure 7
DISTRIBUTION OF TLV2252 INPUT OFFSET
VOLTAGE TEMPERATURE COEFFICIENT †
20
1
VIC − Common-Mode Input Voltage − V
VIC − Common-Mode Input Voltage − V
−1
0
1
α VIO − Temperature Coefficient − µ V / °C
2
62 Amplifiers From 1 Wafer Lot
VDD± = ± 2.5 V
P Package
20 T = 25°C to 85°C
A
15
10
5
0
−2
−1
0
1
α VIO − Temperature Coefficient − µ V / °C
Figure 8
2
Figure 9
† For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
15
SGLS192A − OCTOBER 2003 − REVISED MARCH 2004
TYPICAL CHARACTERISTICS
DISTRIBUTION OF TLV2254 INPUT OFFSET
VOLTAGE TEMPERATURE COEFFICIENT
25
62 Amplifiers From 1 Wafer Lot
VDD± = ± 1.5 V
P Package
TA = 25°C to 85°C
20
62 Amplifiers From 1 Wafer Lot
VDD ± = ± 2.5 V
P Package
20 TA = 25°C to 85°C
Percentage of Amplifiers − %
Percentage of Amplifiers − %
25
DISTRIBUTION OF TLV2254 INPUT OFFSET
VOLTAGE TEMPERATURE COEFFICIENT
15
10
5
15
10
5
0
−2
−1
0
1
0
2
−2
−1
0
1
αVIO − Temperature Coefficient
of Input Offset Voltage − µV / °C
αVIO − Temperature Coefficient
of Input Offset Voltage − µV / °C
Figure 11
INPUT VOLTAGE
vs
SUPPLY VOLTAGE
INPUT BIAS AND INPUT OFFSET CURRENTS†
vs
FREE-AIR TEMPERATURE
35
30
2.5
VDD± = ± 2.5 V
VIC = 0
VO = 0
RS = 50 Ω
1.5
25
20
15
IIB
1
0.5
0
| VIO | ≤ 5 mV
ÁÁ
ÁÁ
10
−0.5
−1
−1.5
IIO
5
0
25
RS = 50 Ω
TA = 25°C
2
VI − Input Voltage − V
IIIB
IB and IIIO
IO − Input Bias and Input Offset Currents − pA
Figure 10
−2
−2.5
105
85
45
65
TA − Free-Air Temperature − °C
125
1
1.5
2
2.5
3
3.5
| VDD ± | − Supply Voltage − V
Figure 13
Figure 12
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
16
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
4
SGLS192A − OCTOBER 2003 − REVISED MARCH 2004
TYPICAL CHARACTERISTICS
INPUT VOLTAGE†‡
vs
FREE-AIR TEMPERATURE
HIGH-LEVEL OUTPUT VOLTAGE†‡
vs
HIGH-LEVEL OUTPUT CURRENT
5
3
VDD = 5 V
VDD = 3 V
VOH − High-Level Output Voltage − V
4
VI − Input Voltage − V
3
| VIO | ≤ 5 mV
2
ÁÁ
1
0
−1
−55 −35 −15
5
25
45
65 85 105
TA − Free-Air Temperature − °C
125
ÁÁ
ÁÁ
ÁÁ
2.5
TA = − 40°C
2
TA = 25°C
1.5
TA = 85°C
1
TA = 125°C
0.5
0
0
200
800
Figure 15
LOW-LEVEL OUTPUT VOLTAGE†‡
vs
LOW-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT VOLTAGE‡
vs
LOW-LEVEL OUTPUT CURRENT
1.4
1.2
VDD = 3 V
TA = 25°C
VOL − Low-Level Output Voltage − V
VOL − Low-Level Output Voltage − V
600
| IOH | − High-Level Output Current − µ A
Figure 14
1
VIC = 0
0.8
VIC = 0.75 V
0.6
VIC = 1.5 V
0.4
ÁÁ
ÁÁ
400
ÁÁ
ÁÁ
0.2
VDD = 3 V
VIC = 1.5 V
1.2
TA = 125°C
1
TA = 85°C
0.8
TA = 25°C
0.6
0.4
TA = − 40°C
0.2
0
0
0
1
2
3
4
5
IOL − Low-Level Output Current − mA
0
1
2
3
4
IOL − Low-Level Output Current − mA
Figure 16
5
Figure 17
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
‡ For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
17
SGLS192A − OCTOBER 2003 − REVISED MARCH 2004
TYPICAL CHARACTERISTICS
HIGH-LEVEL OUTPUT VOLTAGE†‡
vs
HIGH-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT VOLTAGE†‡
vs
LOW-LEVEL OUTPUT CURRENT
5
1.4
VDD = 5 V
VIC = 2.5 V
ÁÁ
ÁÁ
1.2
4
VOL − Low-Level Output Voltage − V
VOH − High-Level Output Voltage − V
VDD = 5 V
TA = − 40°C
3
TA = 25°C
2
TA = 85°C
ÁÁ
ÁÁ
1
TA = 125°C
0
0
200
400
600
TA = 125°C
1
TA = 85°C
0.8
TA = 25°C
0.6
0.4
TA = − 40°C
0.2
0
800
0
| IOH | − High-Level Output Current − µA
1
2
Figure 18
5
10
5
RI = 50 kΩ
TA = 25°C
VDD = 5 V
4
3
VDD = 3 V
2
1
0
10 2
9
8
6
5
10 5
VO = VDD/2
TA = 25°C
VIC = VDD/2
4
3
2
1
VID = 100 mV
0
−1
10 3
10 4
f − Frequency − Hz
VID = − 100 mV
7
2
Figure 20
3
6
4
5
VDD − Supply Voltage − V
7
Figure 21
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
‡ For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V.
18
6
SHORT-CIRCUIT OUTPUT CURRENT
vs
SUPPLY VOLTAGE
I OS − Short-Circuit Output Current − mA
VO(PP) − Maximum Peak-to-Peak Output Voltage − V
4
Figure 19
MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE‡
vs
FREQUENCY
ÁÁ
ÁÁ
ÁÁ
3
IOL − Low-Level Output Current − mA
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
8
SGLS192A − OCTOBER 2003 − REVISED MARCH 2004
TYPICAL CHARACTERISTICS
DIFFERENTIAL INPUT VOLTAGE‡
vs
OUTPUT VOLTAGE
SHORT-CIRCUIT OUTPUT CURRENT †
vs
FREE-AIR TEMPERATURE
1000
VO = 2.5 V
VDD = ± 5 V
10
9
8
VID = − 100 mV
7
6
5
4
3
2
1
600
400
200
0
−200
−400
−600
−800
VID = 100 mV
0
−1
−75
−50
−25
0
25
50
75
100
TA − Free-Air Temperature − °C
VDD = 3 V
RI = 50 kΩ
VIC = 1.5 V
TA = 25°C
800
V ID − Differential Input Voltage − µ V
I OS − Short-Circuit Output Current − mA
11
−1000
125
0
0.5
1
1.5
2
VO − Output Voltage − V
Figure 22
DIFFERENTIAL VOLTAGE AMPLIFICATION†‡
vs
LOAD RESISTANCE
V ID − Differential Input Voltage − µ V
AVD − Differential Voltage Amplification − V/mV
1000
VDD = 5 V
VIC = 2.5 V
RL = 50 kΩ
TA = 25°C
600
400
200
0
−200
−400
−600
−800
−1000
0
1
3
Figure 23
DIFFERENTIAL INPUT VOLTAGE‡
vs
OUTPUT VOLTAGE
800
2.5
3
2
4
VO − Output Voltage − V
5
10 4
VO(PP) = 2 V
TA = 25°C
10 3
VDD = 5 V
10 2
VDD = 3 V
101
ÁÁ
ÁÁ
1
1
101
10 2
10 3
RL − Load Resistance − kΩ
Figure 24
Figure 25
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
‡ For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
19
SGLS192A − OCTOBER 2003 − REVISED MARCH 2004
TYPICAL CHARACTERISTICS
LARGE-SIGNAL DIFFERENTIAL VOLTAGE†
AMPLIFICATION AND PHASE MARGIN
vs
FREQUENCY
AVD
A
VD − Large-Signal Differential
Voltage Amplification − dB
60
ÁÁ
ÁÁ
ÁÁ
180°
VDD = 5 V
RL = 50 kΩ
CL= 100 pF
TA = 25°C
135°
40
90°
Phase Margin
20
45°
Gain
0
0°
−20
φom
m − Phase Margin
80
−45°
−40
10 3
10 4
10 5
10 6
f − Frequency − Hz
−90°
10 7
Figure 26
LARGE-SIGNAL DIFFERENTIAL VOLTAGE†
AMPLIFICATION AND PHASE MARGIN
vs
FREQUENCY
AVD
A
VD − Large-Signal Differential
Voltage Amplification − dB
60
ÁÁ
ÁÁ
ÁÁ
180°
VDD = 3 V
RL= 50 kΩ
CL= 100 pF
TA = 25°C
135°
40
Phase Margin
20
45°
Gain
0
0°
−20
−40
10 3
90°
φom
m − Phase Margin
80
−45°
10 4
10 5
10 6
f − Frequency − Hz
−90°
10 7
Figure 27
† For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V.
20
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SGLS192A − OCTOBER 2003 − REVISED MARCH 2004
TYPICAL CHARACTERISTICS
LARGE-SIGNAL DIFFERENTIAL†‡
VOLTAGE AMPLIFICATION
vs
FREE-AIR TEMPERATURE
LARGE-SIGNAL DIFFERENTIAL†‡
VOLTAGE AMPLIFICATION
vs
FREE-AIR TEMPERATURE
10 4
VDD = 3 V
VIC = 1.5 V
VO = 0.5 V to 2.5 V
AVD − Large-Signal Differential Voltage
Amplification − V/mV
AVD − Large-Signal Differential Voltage
Amplification − V/mV
10 4
RL = 1 MΩ
10 3
RL = 50 kΩ
10 2
101
−75
−50
−25
0
25
50
75 100
TA − Free-Air Temperature − °C
VDD = 5 V
VIC = 2.5 V
VO = 1 V to 4 V
RL = 1 MΩ
10 3
RL = 50 kΩ
10 2
101
−75
125
−50
−25
0
25
50
75
100
TA − Free-Air Temperature − °C
Figure 28
Figure 29
OUTPUT IMPEDANCE‡
vs
FREQUENCY
OUTPUT IMPEDANCE‡
vs
FREQUENCY
1000
1000
VDD = 5 V
TA = 25°C
z o − Output Impedance − Ω
z o − Output Impedance − Ω
VDD = 3 V
TA = 25°C
100
125
AV = 100
10
AV = 10
1
100
AV = 100
10
AV = 10
1
AV = 1
AV = 1
0.1
10 2
10 3
10 4
f− Frequency − Hz
10 5
10 6
0.1
10 2
Figure 30
10 3
10 4
f− Frequency − Hz
10 5
10 6
Figure 31
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
‡ For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V.
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SGLS192A − OCTOBER 2003 − REVISED MARCH 2004
TYPICAL CHARACTERISTICS
COMMON-MODE REJECTION RATIO†‡
vs
FREE-AIR TEMPERATURE
COMMON-MODE REJECTION RATIO†
vs
FREQUENCY
94
VDD = 5 V
VIC = 2.5 V
CMMR − Common-Mode Rejection Ratio − dB
CMRR − Common-Mode Rejection Ratio − dB
100
TA = 25°C
80
VDD = 3 V
VIC = 1.5 V
60
40
20
0
10 1
10 2
10 4
10 3
f − Frequency − Hz
10 5
92
90
VDD = 5 V
88
VDD = 3 V
86
84
82
80
0
25
50
75 100
− 75 − 50 − 25
TA − Free-Air Temperature − °C
10 6
Figure 33
Figure 32
SUPPLY-VOLTAGE REJECTION RATIO†
vs
FREQUENCY
SUPPLY-VOLTAGE REJECTION RATIO†
vs
FREQUENCY
100
VDD = 3 V
TA = 25°C
k SVR − Supply-Voltage Rejection Ratio − dB
k SVR − Supply-Voltage Rejection Ratio − dB
100
Á
Á
Á
80
60
kSVR +
40
kSVR −
20
0
−20
10 1
125
10 2
10 3
10 4
f − Frequency − Hz
10 5
10 6
VDD = 5 V
TA = 25°C
kSVR +
80
60
kSVR −
40
20
ÁÁ
ÁÁ
ÁÁ
0
−20
101
Figure 34
10 2
10 3
10 4
10 5
f − Frequency − Hz
Figure 35
† For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V.
‡ Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
22
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10 6
SGLS192A − OCTOBER 2003 − REVISED MARCH 2004
TYPICAL CHARACTERISTICS
TLV2252
SUPPLY CURRENT †
vs
SUPPLY VOLTAGE
SUPPLY-VOLTAGE REJECTION RATIO†
vs
FREE-AIR TEMPERATURE
120
VDD = 2.7 V to 8 V
VIC = VO = VDD / 2
VO = 0
No Load
100
I DD − Supply Current − µ A
k SVR − Supply-Voltage Rejection Ratio − dB
110
105
100
ÁÁ
ÁÁ
95
ÁÁ
ÁÁ
90
−75 −50
TA = − 40°C
80
60
TA = 85°C
TA = 25°C
40
20
0
−25
0
25
50
75 100
TA − Free-Air Temperature − °C
125
0
1
2
3
4
5
6
VDD − Supply Voltage − V
Figure 36
SLEW RATE‡
vs
LOAD CAPACITANCE
0.2
240
VO = 0
No Load
0.18
200
VDD = 5 V
AV = − 1
TA = 25°C
0.16
SR − Slew Rate − V/ µ s
I DD − Supply Current − µ A
8
Figure 37
TLV2254
SUPPLY CURRENT †
vs
SUPPLY VOLTAGE
ÁÁ
ÁÁ
ÁÁ
7
TA = − 40°C
160
120
TA = 85°C
TA = 25°C
80
0.14
SR −
0.12
0.1
SR +
0.08
0.06
0.04
40
0.02
0
0
1
6
2
3
4
5
| VDD ± | − Supply Voltage − V
7
8
0
101
Figure 38
10 2
10 3
CL − Load Capacitance − pF
10 4
Figure 39
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
‡ For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V.
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23
SGLS192A − OCTOBER 2003 − REVISED MARCH 2004
TYPICAL CHARACTERISTICS
SLEW RATE†‡
vs
FREE-AIR TEMPERATURE
INVERTING LARGE-SIGNAL PULSE
RESPONSE†
0.2
0.16
VDD = 3 V
RL = 50 kΩ
CL = 100 pF
AV = −1
TA = 25°C
2.5
SR −
VO − Output Voltage − V
SR − Slew Rate − V/ µ s
3
VDD = 5 V
RL = 50 kΩ
CL = 100 pF
AV = 1
0.12
SR +
0.08
0.04
2
1.5
1
0.5
0
−75
0
−50
−25
0
25
50
75 100
TA − Free-Air Temperature − °C
125
0
10
20
Figure 40
40 50 60 70
t − Time − µs
80
90
VOLTAGE-FOLLOWER LARGE-SIGNAL
PULSE RESPONSE†
5
3
VDD = 5 V
RL = 50 kΩ
CL = 100 pF
4 A = −1
V
TA = 25°C
VDD = 3 V
RL = 50 kΩ
CL = 100 pF
AV = 1
TA = 25°C
VO − Output Voltage − V
2.5
3
2
1
2
1.5
1
0.5
0
0
0
10
20
30
40
50
60
70
80
90 100
0
10
t − Time − µs
20
30
40
50
60
70
80
90 100
t − Time − µs
Figure 42
Figure 43
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
‡ For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V.
24
100
Figure 41
INVERTING LARGE-SIGNAL PULSE
RESPONSE†
VO − Output Voltage − V
30
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SGLS192A − OCTOBER 2003 − REVISED MARCH 2004
TYPICAL CHARACTERISTICS
INVERTING SMALL-SIGNAL
PULSE RESPONSE†
VOLTAGE-FOLLOWER LARGE-SIGNAL
PULSE RESPONSE†
0.95
5
VDD = 5 V
RL = 50 kΩ
CL = 100 pF
AV = 1
TA = 25°C
0.9
VO − Output Voltage − V
VO − Output Voltage − V
4
VDD = 3 V
RL = 50 kΩ
CL = 100 pF
AV = − 1
TA = 25°C
3
2
0.85
0.8
0.75
0.7
1
0.65
0.6
0
0
10
20
30
40 50 60
t − Time − µs
70
80
0
90 100
10
30
40
50
t − Time − µs
Figure 44
Figure 45
VOLTAGE-FOLLOWER SMALL-SIGNAL
PULSE RESPONSE†
INVERTING SMALL-SIGNAL
PULSE RESPONSE†
0.95
2.65
VDD = 5 V
RL = 50 kΩ
CL = 100 pF
AV = − 1
TA = 25°C
VDD = 3 V
RL = 50 kΩ
CL = 100 pF
AV = 1
TA = 25°C
0.9
VO
VO − Output Voltage − V
2.6
VO
VO − Output Voltage − V
20
2.55
2.5
0.85
0.8
0.75
0.7
2.45
0.65
0.6
2.4
0
10
20
30
t − Time − µs
40
50
0
Figure 46
10
20
30
t − Time − µs
40
50
Figure 47
† For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V.
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25
SGLS192A − OCTOBER 2003 − REVISED MARCH 2004
TYPICAL CHARACTERISTICS
EQUIVALENT INPUT NOISE VOLTAGE†
vs
FREQUENCY
VOLTAGE-FOLLOWER SMALL-SIGNAL
PULSE RESPONSE†
60
2.65
VO
VO − Output Voltage − V
2.6
V n − Equivalent Input Noise Voltage − nV/ Hz
VDD = 5 V
RL = 50 kΩ
CL = 100 pF
AV = 1
TA = 25°C
2.55
2.5
2.45
2.4
0
10
20
30
t − Time − µs
40
50
VDD = 3 V
RS = 20 Ω
TA = 25°C
40
30
20
10
0
10 1
50
10 2
10 3
f − Frequency − Hz
Figure 48
Figure 49
EQUIVALENT INPUT NOISE VOLTAGE†
vs
FREQUENCY
INPUT NOISE VOLTAGE OVER
A 10-SECOND PERIOD†
1000
VDD = 5 V
RS = 20 Ω
TA = 25°C
VDD = 5 V
f = 0.1 Hz to 10 Hz
TA = 25°C
750
500
Noise Voltage − nV
V n − Equivalent Input Noise Voltage − nV/ Hz
60
50
10 4
40
30
20
250
0
−250
−500
10
−750
0
101
10 2
10 3
f − Frequency − Hz
10 4
−1000
0
2
4
6
8
t − Time − s
Figure 51
Figure 50
† For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V.
26
POST OFFICE BOX 655303
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10
SGLS192A − OCTOBER 2003 − REVISED MARCH 2004
TYPICAL CHARACTERISTICS
INTEGRATED NOISE VOLTAGE†
vs
FREQUENCY
THD + N − Total Harmonic Distortion Plus Noise − %
TOTAL HARMONIC DISTORTION PLUS NOISE†
vs
FREQUENCY
Integrated Noise Voltage − µ V
100
Calculated Using Ideal Pass-Band Filter
Low Frequency = 1 Hz
TA = 25°C
10
1
0.1
101
1
10 2
10 3
f − Frequency − Hz
10 4
10 5
1
AV = 100
0.1
AV = 10
0.01
AV = 1
VDD = 5 V
RL = 50 kΩ
TA = 25°C
0.001
101
10 2
10 3
Figure 52
10 5
Figure 53
GAIN-BANDWIDTH PRODUCT†‡
vs
FREE-AIR TEMPERATURE
GAIN-BANDWIDTH PRODUCT
vs
SUPPLY VOLTAGE
300
VDD = 5 V
f = 10 kHz
RL = 50 kHz
CL = 100 pF
Gain-Bandwidth Product − kHz
220
Gain-Bandwidth Product − kHz
10 4
f − Frequency − Hz
210
200
190
260
220
180
140
180
100
−75
170
0
1
4
6
2
3
5
VDD − Supply Voltage − V
7
8
−50 −25
0
25
50
75
100
TA − Free-Air Temperature − °C
125
Figure 55
Figure 54
† For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V.
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27
SGLS192A − OCTOBER 2003 − REVISED MARCH 2004
TYPICAL CHARACTERISTICS
PHASE MARGIN
vs
LOAD CAPACITANCE
75°
GAIN MARGIN
vs
LOAD CAPACITANCE
20
Rnull = 200 Ω
TA = 25°C
Rnull = 500 Ω
Rnull = 500 Ω
60°
Gain Margin − dB
φom
m − Phase Margin
15
45°
Rnull = 100 Ω
Rnull = 50 Ω
30°
Rnull = 10 Ω
50 kΩ
VI
0°
101
Rnull = 100 Ω
10
Rnull = 50 Ω
Rnull = 10 Ω
50 kΩ
15°
Rnull = 200 Ω
5
VDD +
Rnull
−
+
Rnull = 0
Rnull = 0
CL
TA = 25°C
VDD −
10 2
10 3
CL − Load Capacitance − pF
0
101
10 4
10 4
10 2
10 3
CL − Load Capacitance − pF
Figure 56
Figure 57
OVERESTIMATION OF PHASE MARGIN†
vs
LOAD CAPACITANCE
UNITY-GAIN BANDWIDTH
vs
LOAD CAPACITANCE
25
TA = 25°C
200
TA = 25°C
Rnull = 500 Ω
Overestimation of Phase Margin
B1 − Unity-Gain Bandwidth − kHz
175
ÁÁ
ÁÁ
150
125
100
75
50
20
15
Rnull = 100 Ω
10
Rnull = 200 Ω
Rnull = 50 Ω
Rnull = 10 Ω
5
25
0
101
0
101
10 2
10 3
10 4
CL − Load Capacitance − pF
10 5
10 2
10 3
10 4
CL − Load Capacitance − pF
† See application information
Figure 59
Figure 58
† For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V.
‡ Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
28
10 5
POST OFFICE BOX 655303
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10 5
SGLS192A − OCTOBER 2003 − REVISED MARCH 2004
APPLICATION INFORMATION
driving large capacitive loads
The TLV2252 is designed to drive larger capacitive loads than most CMOS operational amplifiers. Figure 56
and Figure 57 illustrate its ability to drive loads up to 1000 pF while maintaining good gain and phase margins
(Rnull = 0).
A smaller series resistor (Rnull) at the output of the device (see Figure 60) improves the gain and phase margins
when driving large capacitive loads. Figure 55 and Figure 56 show the effects of adding series resistances of
10 Ω, 50 Ω, 100 Ω, 200 Ω, and 500 Ω. The addition of this series resistor has two effects: the first adds a zero
to the transfer function and the second reduces the frequency of the pole associated with the output load in the
transfer function.
The zero introduced to the transfer function is equal to the series resistance times the load capacitance. To
calculate the improvement in phase margin, equation 1 can be used.
ǒ
∆φ m1 + tan –1 2 × π × UGBW × R
null
×C
Ǔ
(1)
L
Where :
∆φ m1 + improvement in phase margin
UGBW + unity-gain bandwidth frequency
R null + output series resistance
C L + load capacitance
The unity-gain bandwidth (UGBW) frequency decreases as the capacitive load increases (see Figure 58). To
use equation 1, UGBW must be approximated from Figure 58.
Using equation 1 alone overestimates the improvement in phase margin as illustrated in Figure 59. The
overestimation is caused by the decrease in the frequency of the pole associated with the load, providing
additional phase shift and reducing the overall improvement in phase margin.
Using Figure 60, with equation 1 enables the designer to choose the appropriate output series resistance to
optimize the design of circuits driving large capacitance loads.
50 kΩ
VDD +
VI
50 kΩ
Rnull
−
+
CL
VDD − / GND
Figure 60. Series-Resistance Circuit
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29
SGLS192A − OCTOBER 2003 − REVISED MARCH 2004
APPLICATION INFORMATION
macromodel information
Macromodel information provided was derived using Microsim Parts, the model generation software used
with Microsim PSpice. The Boyle macromodel (see Note 5) and subcircuit in Figure 61 are generated using
the TLV2252 typical electrical and operating characteristics at TA = 25°C. Using this information, output
simulations of the following key parameters can be generated to a tolerance of 20% (in most cases):
D
D
D
D
D
D
D
D
D
D
D
D
Maximum positive output voltage swing
Maximum negative output voltage swing
Slew rate
Quiescent power dissipation
Input bias current
Open-loop voltage amplification
Unity-gain frequency
Common-mode rejection ratio
Phase margin
DC output resistance
AC output resistance
Short-circuit output current limit
NOTE 4: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Integrated Circuit Operational Amplifiers,” IEEE Journal
of Solid-State Circuits, SC-9, 353 (1974).
99
3
VCC +
9
RSS
10
J1
DP
VC
J2
IN +
11
RD1
VAD
DC
12
C1
R2
−
53
HLIM
−
+
C2
6
−
−
+
+
GCM
GA
−
RD2
−
RO1
DE
5
+
VE
.SUBCKT TLV225x 1 2 3 4 5
C1
11
12
6.369E−12
C2
6
7
25.00E−12
DC
5
53
DX
DE
54
5
DX
DLP
90
91
DX
DLN
92
90
DX
DP
4
3
DX
EGND
99
0
POLY (2) (3,0) (4,0) 0 .5 .5
FB
7
99
POLY (5) VB VC VE VLP
+ VLN 0 57.62E6 −60E6 60E6 60E6 −60E6
GA
6
0
11
12 26.86E−6
GCM
0
6
10
99 2.686E−9
ISS
3
10
DC 3.1E−6
HLIM
90
0
VLIM 1K
J1
11
2
10 JX
J2
12
1
10 JX
R2
6
9
100.0E3
OUT
RD1
60
11
37.23E3
RD2
60
12
37.23E3
R01
8
5
84
R02
7
99
84
RP
3
4
71.43E3
RSS
10
99
64.52E6
VAD
60
4
−.5
VB
9
0
DC 0
VC
3
53
DC .605
VE
54
4
DC .605
VLIM
7
8
DC 0
VLP
91
0
DC −0.235
VLN
0
92
DC 7.5
.MODEL DX D (IS=800.0E−18)
.MODEL JX PJF (IS=500.0E−15 BETA=139E−6
+ VTO=−.05)
.ENDS
Figure 61. Boyle Macromodel and Subcircuit
PSpice and Parts are trademarks of MicroSim Corporation.
30
−
VLIM
8
54
4
91
+
VLP
7
60
+
−
+ DLP
90
RO2
VB
IN −
VCC −
92
FB
−
+
ISS
RP
2
1
DLN
EGND +
POST OFFICE BOX 655303
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VLN
PACKAGE OPTION ADDENDUM
www.ti.com
23-Apr-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TLV2252AQDRG4Q1
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
2252AQ
TLV2252AQDRQ1
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
2252AQ
TLV2252QDRQ1
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
2252Q1
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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