TLV2262A-Q1, TLV2264A-Q1
www.ti.com ........................................................................................................................................................................................... SGLS193 – DECEMBER 2008
Advanced LinCMOS™ RAIL-TO-RAIL OPERATIONAL AMPLIFIERS
FEATURES
1
•
•
•
•
•
23
•
•
•
•
•
Qualified for Automotive Applications
Output Swing Includes Both Supply Rails
Low Noise . . . 12 nV/√Hz Typ at f = 1 kHz
Low Input Bias Current . . . 1 pA Typ
Fully Specified for Both Single-Supply and
Split-Supply Operation
Low Power . . . 500 µA Max
Common-Mode Input Voltage Range Includes
Negative Rail
Low Input Offset Voltage . . .
950 µV Max at TA = 25°C
Wide Supply Voltage Range . . . 2.7 V to 8 V
Macromodel Included
TLV2262A
PW PACKAGE
(TOP VIEW)
1OUT
1IN1IN+
VDD - /GND
1
8
2
7
3
6
4
5
VDD +
2OUT
2IN2IN+
TLV2264A
PW PACKAGE
(TOP VIEW)
1OUT
1IN
1IN +
1
14
2
13
3
12
VDD +
2IN +
2IN 2OUT
4
11
5
10
6
9
7
8
4OUT
4IN
4IN +
VDD - /GND
3IN +
3IN 3OUT
DESCRIPTION
The TLV2262 and TLV2264 are dual and quad low voltage operational amplifiers from Texas Instruments. Both
devices exhibit rail-to-rail output performance for increased dynamic range in single or split supply applications.
The TLV226x family offers a compromise between the micropower TLV225x and the ac performance of the
TLC227x. It has low supply current for battery-powered applications, while still having adequate ac performance
for applications that demand it. This family is fully characterized at 3 V and 5 V and is optimized for low-voltage
applications. The noise performance has been dramatically improved over previous generations of CMOS
amplifiers. Figure 1 depicts the low level of noise voltage for this CMOS amplifier, which has only 200 µA (typ) of
supply current per amplifier.
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Advanced LinCMOS is a trademark of Texas Instruments.
Parts, PSpice are trademarks of MicroSim Corporation.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008, Texas Instruments Incorporated
TLV2262A-Q1, TLV2264A-Q1
SGLS193 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
4
VDD = 3 V
VOH − High-Level Output Voltage − V
3.5
3
TA = − 55°C
2.5
TA = 125°C
2
ÁÁ
ÁÁ
ÁÁ
ÁÁ
TA = 25°C
1.5
TA = 85°C
1
TA = − 40°C
0.5
0
0
500
1000
1500
2000
| IOH | − High-Level Output Current − µ A
Figure 1.
The TLV226x, exhibiting high input impedance and low noise, are excellent for small-signal conditioning for
high-impedance sources, such as piezoelectric transducers. Because of the micropower dissipation levels
combined with 3-V operation, these devices work well in hand-held monitoring and remote-sensing applications.
In addition, the rail-to-rail output feature with single or split supplies makes this family a great choice when
interfacing with analog-to-digital converters (ADCs). For precision applications, the TLV226xA family is available
and has a maximum input offset voltage of 950 µV.
The TLV2262/4 also makes great upgrades to the TLV2332/4 in standard designs. They offer increased output
dynamic range, lower noise voltage and lower input offset voltage. This enhanced feature set allows them to be
used in a wider range of applications. For applications that require higher output drive and wider input voltage
range, see the TLV2432 and TLV2442 devices. If your design requires single amplifiers, please see the
TLV2211/21/31 family. These devices are single rail-to-rail operational amplifiers in the SOT-23 package. Their
small size and low power consumption make them ideal for high density, battery-powered equipment.
ORDERING INFORMATION (1)
TA
–40°C to 125°C
(1)
(2)
2
PACKAGE (2)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
TSSOP – PW (8 pin)
Reel of 2000
TLV2262AQPWRQ1
TQ262A
TSSOP – PW (14 pin)
Reel of 2000
TLV2264AQPWRQ1
P2264AQ
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
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Product Folder Link(s): TLV2262A-Q1 TLV2264A-Q1
TLV2262A-Q1, TLV2264A-Q1
www.ti.com ........................................................................................................................................................................................... SGLS193 – DECEMBER 2008
EQUIVALENT SCHEMATIC (EACH AMPLIFIER)
VDD +
Q3
Q6
Q9
Q12
Q14
Q16
R6
IN +
OUT
C1
IN −
R5
Q1
Q4
Q13
Q15
Q17
D1
Q2
Q5
R3
R4
Q7
Q8
Q10
Q11
R1
R2
VDD − / GND
Table 1. Actual Device Component Count
TLV2262
TLV2264
Transistors
COMPONENT
38
76
Resistors
28
54
Diodes
9
18
Capacitors
3
6
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): TLV2262A-Q1 TLV2264A-Q1
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TLV2262A-Q1, TLV2264A-Q1
SGLS193 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
VDD
Supply voltage (2)
VID
Differential input voltage (3)
VI
Input voltage range
II
Input current, any input
±5 mA
IO
Output current
±50 mA
Total current into VDD+
±50 mA
–0.3 V to 16 V
±VDD
(VDD– – 0.3 V) to VDD+
Total current out of VDD–
±50 mA
Duration of short-circuit current (at or below) 25°C (4)
Unlimited
PD
Continuous total power dissipation
TA
Operating free-air temperature range
–40°C to 125°C
Tstg
Storage temperature range
–65°C to 150°C
(1)
(2)
(3)
(4)
See Dissipation Rating Table
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential voltages, are with respect to VDD–.
Differential voltages are at the noninverting input with respect to the inverting input. Excessive current flows when input is brought below
VDD– – 0.3 V.
The output may be shorted to either supply. Temperature and/or supply voltages must be limited to ensure that the maximum dissipation
rating is not exceeded.
DISSIPATION RATINGS
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 85°C
POWER RATING
TA = 125°C
POWER RATING
PW-8
525 mW
4.2 mW/°C
273 mW
105 mW
PW-14
700 mW
5.6 mW/°C
364 mW
140 mW
RECOMMENDED OPERATING CONDITIONS
MIN
MAX
2.7
8
V
Input voltage
VDD–
VDD+ –1.3
V
VIC
Common-mode input voltage
VDD–
VDD+ –1.3
V
TA
Operating free-air temperature
–40
125
°C
VDD±
Supply voltage (1)
VI
(1)
4
UNIT
All voltage values, except differential voltages, are with respect to VDD–.
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www.ti.com ........................................................................................................................................................................................... SGLS193 – DECEMBER 2008
TLV2262A ELECTRICAL CHARACTERISTICS
VDD = 3 V, over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIO
Input offset voltage
VDD± = ±1.5 V, VIC = 0, VO = 0, RS = 50 Ω
αVIO
Temperature coefficient
of input offset voltage
VDD± = ±1.5 V, VIC = 0, VO = 0, RS = 50 Ω
TA
Input offset current
VDD± = ±1.5 V, VIC = 0, VO = 0, RS = 50 Ω
IIB
Input bias current
VDD± = ±1.5 V, VIC = 0, VO = 0, RS = 50 Ω
VICR
Common-mode input voltage
RS = 50 Ω, | VIO | ≤ 5 mV
range
High-level output voltage
VIC = 1.5 V
Large-signal differential
voltage amplification
VIC = 1.5 V, VO = 1 V to 2 V
0.003
µV/mo
25°C
0.5
Full range
1
0
to 2
RL = 1 MΩ
–0.3
to 2.2
pA
pA
V
0
to 1.7
2.99
25°C
2.85
Full range
2.82
25°C
2.7
Full range
2.55
V
25°C
10
25°C
100
Full range
150
165
25°C
(2)
60
800
200
Full range
RL = 50 kΩ (2)
60
800
25°C
IOL = 1 mA
AVD
25°C
25°C
IOL = 500 µA
mV
µV/°C
125°C
IOH = –100 µA
UNIT
2
25°C
IOL = 50 µA
Low-level output voltage
950
125°C
IOH = –400 µA
VOL
MAX
300
1500
25°C to 125°C
IOH = –20 µA
VOH
TYP
Full range
Input offset voltage long-term
VDD± = ±1.5 V, VIC = 0, VO = 0, RS = 50 Ω
drift (1)
IIO
MIN
25°C
mV
300
300
25°C
60
Full range
25
100
V/mV
25°C
100
ri(d)
Differential input resistance
25°C
1012
Ω
ri(c)
Common-mode input
resistance
25°C
1012
Ω
ci(c)
Common-mode input
capacitance
f = 10 kHz
25°C
8
pF
zo
Closed-loop output
impedance
f = 100 kHz, AV = 10
25°C
270
Ω
CMRR
Common-mode rejection
ratio
VIC = 0 to 1.7 V, VO = 1.5 V, RS = 50 Ω
kSVR
Supply voltage rejection ratio
VDD = 2.7 V to 8 V, VIC = VDD/2, No load
(ΔVDD/ΔVIO)
IDD
Supply current
(1)
(2)
VO = 1.5 V, No load
25°C
65
Full range
60
25°C
80
Full range
80
25°C
Full range
77
dB
100
400
dB
500
500
µA
Typical values are based on the input offset voltage shift observed through 500 hours of operating life test at TA = 150°C extrapolated to
TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
Referenced to 1.5 V
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): TLV2262A-Q1 TLV2264A-Q1
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TLV2262A-Q1, TLV2264A-Q1
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TLV2262A OPERATING CHARACTERISTICS
VDD = 3 V, over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
(1)
VO = 0.5 V to 1.7 V, RL = 50 kΩ ,
CL = 100 pF (1)
TA
MIN
TYP
25°C
0.35
0.55
Full range
0.25
SR
Slew rate at unity gain
Vn
Equivalent input noise
voltage
f = 10 Hz
25°C
43
f = 1 kHz
25°C
12
VN(PP)
Peak-to-peak equivalent
input noise voltage
f = 0.1 Hz to 1 Hz
25°C
0.6
f = 0.1 Hz to 10 Hz
25°C
1
In
Equivalent input noise current
THD+N
Total harmonic distortion plus VO = 0.5 V to 2.5 V, f = 20 kHz,
noise
RL = 50 kΩ (1)
25°C
0.6
AV = 1
25°C
0.03
AV = 10
25°C
0.05
MAX
UNIT
V/µs
nV/√Hz
µV
fA/√Hz
%
Gain-bandwidth product
f = 1 kHz, RL = 50 kΩ (1), CL = 100 pF (1)
25°C
0.67
MHz
BOM
Maximum output-swing
bandwidth
VO(PP) = 1 V, AV = 1, RL = 50 kΩ (1),
CL = 100 pF (1)
25°C
395
kHz
ts
Settling time
AV = –1, Step = 1 V to 2 V,
RL = 50 kΩ (1), CL = 100 pF (1)
φm
Phase margin at unity gain
RL = 50 kΩ (1), CL = 100 pF (1)
Gm
(1)
6
Gain margin
(1)
RL = 50 kΩ , CL = 100 pF
(1)
To 0.1%
25°C
5.6
To 0.01%
25°C
12.5
25°C
55
°
25°C
11
dB
µs
Referenced to 1.5 V
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www.ti.com ........................................................................................................................................................................................... SGLS193 – DECEMBER 2008
TLV2262A ELECTRICAL CHARACTERISTICS
VDD = 5 V, over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIO
Input offset voltage
VDD± = ±2.5 V, VIC = 0, VO = 0, RS = 50 Ω
αVIO
Temperature coefficient
of input offset voltage
VDD± = ±2.5 V, VIC = 0, VO = 0, RS = 50 Ω
TA
Input offset current
VDD± = ±2.5 V, VIC = 0, VO = 0, RS = 50 Ω
IIB
Input bias current
VDD± = ±2.5 V, VIC = 0, VO = 0, RS = 50 Ω
VICR
Common-mode input voltage
RS = 50 Ω, | VIO | ≤ 5 mV
range
High-level output voltage
VIC = 2.5 V
Large-signal differential
voltage amplification
VIC = 2.5 V, VO = 1 V to 4 V
0.003
µV/mo
25°C
0.5
Full range
1
0
to 4
RL = 1 MΩ
–0.3
to 4.2
pA
pA
V
0
to 3.5
4.99
25°C
4.85
Full range
4.82
25°C
4.7
Full range
4.5
4.94
V
4.85
25°C
0.01
25°C
0.09
Full range
0.15
0.15
25°C
(2)
60
800
0.2
Full range
RL = 50 kΩ (2)
60
800
25°C
IOL = 1 mA
AVD
25°C
25°C
IOL = 500 µA
mV
µV/°C
125°C
IOH = –100 µA
UNIT
2
25°C
IOL = 50 µA
Low-level output voltage
950
125°C
IOH = –400 µA
VOL
MAX
300
1500
25°C to 125°C
IOH = –20 µA
VOH
TYP
Full range
Input offset voltage long-term
VDD± = ±2.5 V, VIC = 0, VO = 0, RS = 50 Ω
drift (1)
IIO
MIN
25°C
V
0.3
0.3
25°C
80
Full range
50
170
V/mV
25°C
550
ri(d)
Differential input resistance
25°C
1012
Ω
ri(c)
Common-mode input
resistance
25°C
1012
Ω
ci(c)
Common-mode input
capacitance
f = 10 kHz
25°C
8
pF
zo
Closed-loop output
impedance
f = 100 kHz, AV = 10
25°C
240
Ω
CMRR
Common-mode rejection
ratio
VIC = 0 to 2.7 V, VO = 2.5 V, RS = 50 Ω
kSVR
Supply voltage rejection ratio
VDD = 4.4 V to 8 V, VIC = VDD/2, No load
(ΔVDD/ΔVIO)
IDD
Supply current
(1)
(2)
VO = 2.5 V, No load
25°C
70
Full range
70
25°C
80
Full range
80
25°C
Full range
83
dB
95
400
dB
500
500
µA
Typical values are based on the input offset voltage shift observed through 500 hours of operating life test at TA = 150°C extrapolated to
TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
Referenced to 2.5 V
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): TLV2262A-Q1 TLV2264A-Q1
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TLV2262A-Q1, TLV2264A-Q1
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TLV2262A OPERATING CHARACTERISTICS
VDD = 5 V, over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
(1)
VO = 0.5 V to 3.5 V, RL = 50 kΩ ,
CL = 100 pF (1)
TA
MIN
TYP
25°C
0.35
0.55
Full range
0.25
SR
Slew rate at unity gain
Vn
Equivalent input noise
voltage
f = 10 Hz
25°C
40
f = 1 kHz
25°C
12
VN(PP)
Peak-to-peak equivalent
input noise voltage
f = 0.1 Hz to 1 Hz
25°C
0.7
f = 0.1 Hz to 10 Hz
25°C
1.3
In
Equivalent input noise current
THD+N
Total harmonic distortion plus VO = 0.5 V to 2.5 V, f = 20 kHz,
noise
RL = 50 kΩ (1)
25°C
0.6
AV = 1
25°C
0.017
AV = 10
25°C
0.03
MAX
UNIT
V/µs
nV/√Hz
µV
fA/√Hz
%
Gain-bandwidth product
f = 50 kHz, RL = 50 kΩ (1), CL = 100 pF (1)
25°C
0.71
MHz
BOM
Maximum output-swing
bandwidth
VO(PP) = 2 V, AV = 1, RL = 50 kΩ (1),
CL = 100 pF (1)
25°C
185
kHz
ts
Settling time
AV = –1, Step = 0.5 V to 2.5 V,
RL = 50 kΩ (1), CL = 100 pF (1)
φm
Phase margin at unity gain
RL = 50 kΩ (1), CL = 100 pF (1)
Gm
(1)
8
Gain margin
(1)
RL = 50 kΩ , CL = 100 pF
(1)
To 0.1%
25°C
6.4
To 0.01%
25°C
14.1
25°C
56
°
25°C
11
dB
µs
Referenced to 2.5 V
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www.ti.com ........................................................................................................................................................................................... SGLS193 – DECEMBER 2008
TLV2264A ELECTRICAL CHARACTERISTICS
VDD = 3 V, over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIO
Input offset voltage
VDD± = ±1.5 V, VIC = 0, VO = 0, RS = 50 Ω
αVIO
Temperature coefficient
of input offset voltage
VDD± = ±1.5 V, VIC = 0, VO = 0, RS = 50 Ω
TA
Input offset current
VDD± = ±1.5 V, VIC = 0, VO = 0, RS = 50 Ω
IIB
Input bias current
VDD± = ±1.5 V, VIC = 0, VO = 0, RS = 50 Ω
VICR
Common-mode input voltage
RS = 50 Ω, | VIO | ≤ 5 mV
range
High-level output voltage
VIC = 1.5 V
Large-signal differential
voltage amplification
VIC = 1.5 V, VO = 1 V to 2 V
0.003
µV/mo
25°C
0.5
Full range
1
0
to 2
RL = 1 MΩ
–0.3
to 2.2
pA
pA
V
0
to 1.7
2.99
25°C
2.85
Full range
2.82
25°C
2.7
Full range
2.6
V
25°C
10
25°C
100
Full range
150
150
25°C
(2)
60
800
200
Full range
RL = 50 kΩ (2)
60
800
25°C
IOL = 1 mA
AVD
25°C
25°C
IOL = 500 µA
mV
µV/°C
125°C
IOH = –100 µA
UNIT
2
25°C
IOL = 50 µA
Low-level output voltage
950
125°C
IOH = –400 µA
VOL
MAX
300
1500
25°C to 125°C
IOH = –20 µA
VOH
TYP
Full range
Input offset voltage long-term
VDD± = ±1.5 V, VIC = 0, VO = 0, RS = 50 Ω
drift (1)
IIO
MIN
25°C
mV
300
300
25°C
60
Full range
25
100
V/mV
25°C
100
ri(d)
Differential input resistance
25°C
1012
Ω
ri(c)
Common-mode input
resistance
25°C
1012
Ω
ci(c)
Common-mode input
capacitance
f = 10 kHz
25°C
8
pF
zo
Closed-loop output
impedance
f = 100 kHz, AV = 10
25°C
270
Ω
CMRR
Common-mode rejection
ratio
VIC = 0 to 1.7 V, VO = 1.5 V, RS = 50 Ω
kSVR
Supply voltage rejection ratio
VDD = 2.7 V to 8 V, VIC = VDD/2, No load
(ΔVDD/ΔVIO)
IDD
Supply current
(1)
(2)
VO = 1.5 V, No load
25°C
65
Full range
60
25°C
80
Full range
80
25°C
Full range
77
dB
100
0.8
dB
1
1
mA
Typical values are based on the input offset voltage shift observed through 500 hours of operating life test at TA = 150°C extrapolated to
TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
Referenced to 1.5 V
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): TLV2262A-Q1 TLV2264A-Q1
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TLV2262A-Q1, TLV2264A-Q1
SGLS193 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com
TLV2264A OPERATING CHARACTERISTICS
VDD = 3 V, over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
(1)
VO = 0.5 V to 1.7 V, RL = 50 kΩ ,
CL = 100 pF (1)
TA
MIN
TYP
25°C
0.35
0.55
Full range
0.25
SR
Slew rate at unity gain
Vn
Equivalent input noise
voltage
f = 10 Hz
25°C
43
f = 1 kHz
25°C
12
VN(PP)
Peak-to-peak equivalent
input noise voltage
f = 0.1 Hz to 1 Hz
25°C
0.6
f = 0.1 Hz to 10 Hz
25°C
1
In
Equivalent input noise current
THD+N
Total harmonic distortion plus VO = 0.5 V to 2.5 V, f = 20 kHz,
noise
RL = 50 kΩ (1)
25°C
0.6
AV = 1
25°C
0.03
AV = 10
25°C
0.05
MAX
UNIT
V/µs
nV/√Hz
µV
fA/√Hz
%
Gain-bandwidth product
f = 1 kHz, RL = 50 kΩ (1), CL = 100 pF (1)
25°C
0.67
MHz
BOM
Maximum output-swing
bandwidth
VO(PP) = 1 V, AV = 1, RL = 50 kΩ (1),
CL = 100 pF (1)
25°C
395
kHz
ts
Settling time
AV = –1, Step = 1 V to 2 V,
RL = 50 kΩ (1), CL = 100 pF (1)
φm
Phase margin at unity gain
RL = 50 kΩ (1), CL = 100 pF (1)
Gm
(1)
10
Gain margin
(1)
RL = 50 kΩ , CL = 100 pF
(1)
To 0.1%
25°C
5.6
To 0.01%
25°C
12.5
25°C
55
°
25°C
11
dB
µs
Referenced to 1.5 V
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TLV2264A ELECTRICAL CHARACTERISTICS
VDD = 5 V, over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIO
Input offset voltage
VDD± = ±2.5 V, VIC = 0, VO = 0, RS = 50 Ω
αVIO
Temperature coefficient
of input offset voltage
VDD± = ±2.5 V, VIC = 0, VO = 0, RS = 50 Ω
TA
Input offset current
VDD± = ±2.5 V, VIC = 0, VO = 0, RS = 50 Ω
IIB
Input bias current
VDD± = ±2.5 V, VIC = 0, VO = 0, RS = 50 Ω
VICR
Common-mode input voltage
RS = 50 Ω, | VIO | ≤ 5 mV
range
High-level output voltage
VIC = 2.5 V
Large-signal differential
voltage amplification
VIC = 2.5 V, VO = 1 V to 4 V
0.003
µV/mo
25°C
0.5
Full range
1
0
to 4
RL = 1 MΩ
–0.3
to 4.2
pA
pA
V
0
to 3.5
4.99
25°C
4.85
Full range
4.82
25°C
4.7
Full range
4.5
4.94
V
4.85
25°C
0.01
25°C
0.09
Full range
0.15
0.15
25°C
(2)
60
800
0.2
Full range
RL = 50 kΩ (2)
60
800
25°C
IOL = 1 mA
AVD
25°C
25°C
IOL = 500 µA
mV
µV/°C
125°C
IOH = –100 µA
UNIT
2
25°C
IOL = 50 µA
Low-level output voltage
950
125°C
IOH = –400 µA
VOL
MAX
300
1500
25°C to 125°C
IOH = –20 µA
VOH
TYP
Full range
Input offset voltage long-term
VDD± = ±2.5 V, VIC = 0, VO = 0, RS = 50 Ω
drift (1)
IIO
MIN
25°C
V
0.3
0.3
25°C
80
Full range
50
170
V/mV
25°C
550
ri(d)
Differential input resistance
25°C
1012
Ω
ri(c)
Common-mode input
resistance
25°C
1012
Ω
ci(c)
Common-mode input
capacitance
f = 10 kHz
25°C
8
pF
zo
Closed-loop output
impedance
f = 100 kHz, AV = 10
25°C
240
Ω
CMRR
Common-mode rejection
ratio
VIC = 0 to 2.7 V, VO = 2.5 V, RS = 50 Ω
kSVR
Supply voltage rejection ratio
VDD = 4.4 V to 8 V, VIC = VDD/2, No load
(ΔVDD/ΔVIO)
IDD
Supply current
(1)
(2)
VO = 2.5 V, No load
25°C
70
Full range
70
25°C
80
Full range
80
25°C
Full range
83
dB
95
0.8
dB
1
1
mA
Typical values are based on the input offset voltage shift observed through 500 hours of operating life test at TA = 150°C extrapolated to
TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
Referenced to 2.5 V
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TLV2264A OPERATING CHARACTERISTICS
VDD = 5 V, over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
(1)
VO = 0.5 V to 3.5 V, RL = 50 kΩ ,
CL = 100 pF (1)
TA
MIN
TYP
25°C
0.35
0.55
Full range
0.25
SR
Slew rate at unity gain
Vn
Equivalent input noise
voltage
f = 10 Hz
25°C
40
f = 1 kHz
25°C
12
VN(PP)
Peak-to-peak equivalent
input noise voltage
f = 0.1 Hz to 1 Hz
25°C
0.7
f = 0.1 Hz to 10 Hz
25°C
1.3
In
Equivalent input noise current
THD+N
Total harmonic distortion plus VO = 0.5 V to 2.5 V, f = 20 kHz,
noise
RL = 50 kΩ (1)
25°C
0.6
AV = 1
25°C
0.017
AV = 10
25°C
0.03
MAX
UNIT
V/µs
nV/√Hz
µV
fA/√Hz
%
Gain-bandwidth product
f = 50 kHz, RL = 50 kΩ (1), CL = 100 pF (1)
25°C
0.71
MHz
BOM
Maximum output-swing
bandwidth
VO(PP) = 2 V, AV = 1, RL = 50 kΩ (1),
CL = 100 pF (1)
25°C
185
kHz
ts
Settling time
AV = –1, Step = 0.5 V to 2.5 V,
RL = 50 kΩ (1), CL = 100 pF (1)
φm
Phase margin at unity gain
RL = 50 kΩ (1), CL = 100 pF (1)
Gm
(1)
12
Gain margin
(1)
RL = 50 kΩ , CL = 100 pF
(1)
To 0.1%
25°C
6.4
To 0.01%
25°C
14.1
25°C
56
°
25°C
11
dB
µs
Referenced to 2.5 V
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TYPICAL CHARACTERISTICS
For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are
referenced to 1.5 V. Data at high and low temperatures are applicable only within the rated operating free-air
temperature ranges of the various devices.
Table of Graphs
FIGURE
Distribution
2–5
vs Common–mode voltage
6, 7
8–11
VIO
Input offset voltage
αVIO
Input offset voltage temperature coefficient
Distribution
IIB/IIO
Input bias and input offset currents
vs Free–air temperature
12
vs Supply voltage
13
VI
Input voltage
VOH
High-level output voltage
vs High-level output current
15, 18
VOL
Low-level output voltage
vs Low-level output current
16, 17, 19
VO(PP)
Maximum peak-to-peak output voltage
vs Frequency
20
IOS
Short-circuit output current
vs Supply voltage
21
VID
Differential input voltage
vs Output voltage
AVD
Differential voltage amplification
vs Load resistance
vs Free–air temperature
vs Free-air temperature
AVD
Large-signal differential voltage amplification
zo
Output impedance
CMRR
Common-mode rejection ratio
kSVR
Supply-voltage rejection ratio
IDD
Supply current
14
22
23, 24
25
vs Frequency
26, 27
vs Free-air temperature
28, 29
vs Frequency
30, 31
vs Frequency
32
vs Free-air temperature
33
vs Frequency
34, 35
vs Free-air temperature
36, 37
vs Free-air temperature
38, 39
vs Load capacitance
40
SR
Slew rate
VO
Inverting large-signal pulse response
42, 43
VO
Voltage-follower large-signal pulse response
44, 45
VO
Inverting small-signal pulse response
46, 47
VO
Voltage-follower small-signal pulse response
Vn
Equivalent input noise voltage
vs Frequency
Input noise voltage
Over a 10-second period
52
Integrated noise voltage
vs Frequency
53
Total harmonic distortion plus noise
vs Frequency
54
vs Supply voltage
55
THD+N
vs Free-air temperature
Gain-bandwidth product
φm
Phase margin
Gm
B1
41
48, 49
50, 51
vs Free-air temperature
vs Frequency
56
26, 27
vs Load capacitance
57
Gain margin
vs Load capacitance
58
Unity-gain bandwidth
vs Load capacitance
59
Overestimation of phase margin
vs Load capacitance
60
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DISTRIBUTION OF TLV2262
INPUT OFFSET VOLTAGE
DISTRIBUTION OF TLV2262
INPUT OFFSET VOLTAGE
12
15
841 Amplifiers From 2 Wafer Lots
VDD± = ± 1.5 V
TA = 25°C
Precentage of Amplifiers − %
Precentage of Amplifiers − %
15
9
6
3
0
−1.6
−0.8
0
0.8
VIO − Input Offset Voltage − mV
12
841 Amplifiers From 2 Wafer Lots
VDD± = ± 2.5 V
TA = 25°C
9
6
3
0
−1.6
1.6
−0.8
0
0.8
VIO − Input Offset Voltage − mV
Figure 2.
Figure 3.
DISTRIBUTION OF TLV2264
INPUT OFFSET VOLTAGE
20
2272 Amplifiers From 2 Wafer Lots
VDD ± = ± 1.5 V
TA = 25°C
16
12
8
4
0
−1.6
14
DISTRIBUTION OF TLV2264
INPUT OFFSET VOLTAGE
Percentage of Amplifiers − %
Percentage of Amplifiers − %
20
−0.8
0
0.8
VIO − Input Offset Voltage − mV
Figure 4.
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1.6
1.6
2272 Amplifiers From 2 Wafer Lots
VDD ± = ± 2.5 V
TA = 25°C
16
12
8
4
0
−1.6
−0.8
0
0.8
VIO − Input Offset Voltage − mV
Figure 5.
1.6
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INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
1
1
VDD = 5 V
RS = 50 Ω
TA = 25°C
VIO − Input Offset Voltage − mV
VIO − Input Offset Voltage − mV
VDD = 3 V
RS = 50 Ω
TA = 25°C
0.5
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
0.5
ÁÁ
ÁÁ
ÁÁ
ÁÁ
0
−0.5
−1
−1
−0.5
0
0.5
1
1.5
2
2.5
0
−0.5
−1
−1
3
0
Figure 6.
3
4
5
Figure 7.
DISTRIBUTION OF TLV2262 INPUT OFFSET
VOLTAGE TEMPERATURE COEFFICIENT
DISTRIBUTION OF TLV2262 INPUT OFFSET
VOLTAGE TEMPERATURE COEFFICIENT
30
30
128 Amplifiers From 2 Wafer Lots
VDD± = ± 1.5 V
25 P Package
TA = 25°C to 85°C
Percentage of Amplifiers − %
Percentage of Amplifiers − %
2
VIC − Common-Mode Input Voltage − V
VIC − Common-Mode Input Voltage − V
20
15
10
5
0
−5
1
128 Amplifiers From 2 Wafer Lots
VDD± = ± 2.5 V
25 P Package
TA = 25°C to 85°C
20
15
10
5
−4 −3 −2 −1 0
1
2
3
4
α VIO − Temperature Coefficient − µ V / °C
Figure 8.
5
0
−5
−4 −3 −2 −1 0
1
2
3
4
α VIO − Temperature Coefficient − µ V / °C
Figure 9.
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DISTRIBUTION OF TLV2264 INPUT OFFSET
VOLTAGE TEMPERATURE COEFFICIENT
DISTRIBUTION OF TLV2264 INPUT OFFSET
VOLTAGE TEMPERATURE COEFFICIENT
35
128 Amplifiers From
2 Wafer Lots
30 VDD± = ± 1.5 V
N Package
TA = 25°C to 125°C
25
128 Amplifiers From
2 Wafer Lots
VDD ± = ± 2.5 V
N Package
TA = 25°C to 125°C
30
Percentage of Amplifiers − %
Percentage of Amplifiers − %
35
20
15
10
25
20
15
10
5
5
0
−5
−4
−3
−2
−1
0
1
2
3
4
0
5
−5
αVIO − Temperature Coefficient
of Input Offset Voltage − µV / °C
−4
−3 −2 −1 0
1
2
3
αVIO − Temperature Coefficient
of Input Offset Voltage − µV / °C
Figure 10.
16
INPUT VOLTAGE
vs
SUPPLY VOLTAGE
2.5
35
VDD ± = ± 2.5 V
VIC = 0
VO = 0
RS = 50 Ω
2
RS = 50 Ω
TA = 25°C
1.5
25
VI − Input Voltage − V
IIO − Input Bias and Input Offset Currents − pA
IIIB
IB and IIO
ÁÁ
ÁÁ
ÁÁ
ÁÁ
5
Figure 11.
INPUT BIAS AND INPUT OFFSET CURRENTS
vs
FREE-AIR TEMPERATURE
30
4
IIB
1
ÁÁ
ÁÁ
ÁÁ
ÁÁ
20
15
IIO
10
0.5
0
| VIO | ≤ 5 mV
−0.5
−1
−1.5
5
−2
0
25
45
65
85
105
TA − Free-Air Temperature − °C
125
−2.5
1
1.5
2
2.5
3
3.5
| VDD± | − Supply Voltage − V
Figure 12.
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4
Figure 13.
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INPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
4
5
VDD = 5 V
VDD = 3 V
3.5
ÁÁ
ÁÁ
ÁÁ
VOH − High-Level Output Voltage − V
VI − Input Voltage − V
4
3
| VIO | ≤ 5 mV
2
ÁÁ
ÁÁ
ÁÁ
ÁÁ
1
0
−1
−55 −35 −15
5
25
45
65 85
TA − Free-Air Temperature − °C
3
TA = − 55°C
2.5
TA = 125°C
2
TA = 25°C
1.5
TA = 85°C
1
TA = − 40°C
0.5
0
105 125
0
500
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
1.4
VOL − Low-Level Output Voltage − V
VDD = 3 V
TA = 25°C
1
VOL − Low-Level Output Voltage − V
2000
Figure 15.
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
ÁÁ
ÁÁ
ÁÁ
ÁÁ
1500
| IOH | − High-Level Output Current − µ A
Figure 14.
1.2
1000
VIC = 0
0.8
VIC = 0.75 V
ÁÁ
ÁÁ
ÁÁ
ÁÁ
0.6
VIC = 1.5 V
0.4
0.2
VDD = 3 V
VIC = 1.5 V
1.2
TA = 125°C
1
TA = 85°C
0.8
TA = 25°C
0.6
TA = − 55°C
0.4
TA = − 40°C
0.2
0
0
0
1
2
3
4
IOL − Low-Level Output Current − mA
5
0
4
1
2
3
IOL − Low-Level Output Current − mA
Figure 16.
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5
Figure 17.
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LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
6
1.4
VDD = 5 V
VIC = 2.5 V
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
1.2
5
VOL − Low-Level Output Voltage − V
VOH − High-Level Output Voltage − V
VDD = 5 V
TA = − 55°C
4
TA = − 40°C
3
TA = 25°C
TA = 125°C
2
TA = 85°C
1
0
0
500
1000
1500
2000
2500
3000
ÁÁ
ÁÁ
ÁÁ
ÁÁ
1
TA = 85°C
0.8
TA = 25°C
0.6
TA = 125°C
TA = − 40°C
0.2
0
0
| IOH | − High-Level Output Current − µA
1
2
3
4
5
IOL − Low-Level Output Current − mA
Figure 18.
Figure 19.
12
RI = 10 kΩ
TA = 25°C
VDD = 5 V
I OS − Short-Circuit Output Current − mA
VO(PP) − Maximum Peak-to-Peak Output Voltage − V
18
5
4
3
VDD = 3 V
2
1
0
10 3
6
SHORT-CIRCUIT OUTPUT CURRENT
vs
SUPPLY VOLTAGE
MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE
vs
FREQUENCY
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
TA = − 55°C
0.4
10 4
10 5
f − Frequency − Hz
Figure 20.
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10 6
10
VIC = VDD/2
TA = 25°C
VID = − 100 mV
8
6
4
2
0
VID = 100 mV
−2
2
3
4
5
6
VDD − Supply Voltage − V
7
8
Figure 21.
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SHORT-CIRCUIT OUTPUT CURRENT
vs
FREE-AIR TEMPERATURE
DIFFERENTIAL INPUT VOLTAGE
vs
OUTPUT VOLTAGE
1000
VO = 2.5 V
VDD = 5 V
10
VID = − 100 mV
8
6
4
2
0
VID = 100 mV
−2
−4
−75
−50
−25
0
25
50
75
100
TA − Free-Air Temperature − °C
Figure 22.
600
400
200
0
−200
−400
−600
−800
−1000
0
125
1000
V ID − Differential Input Voltage − µ V
AVD − Differential Voltage Amplification − V/mV
1000
600
VDD = 5 V
VIC = 2.5 V
RL = 50 kΩ
TA = 25°C
400
200
0
−200
−400
−600
−800
−1000
0
1
3
2
4
VO − Output Voltage − V
0.5
1
1.5
2
VO − Output Voltage − V
Figure 23.
2.5
3
DIFFERENTIAL VOLTAGE AMPLIFICATION
vs
LOAD RESISTANCE
DIFFERENTIAL INPUT VOLTAGE
vs
OUTPUT VOLTAGE
800
VDD = 3 V
RI = 50 kΩ
VIC = 1.5 V
TA = 25°C
800
V ID − Differential Input Voltage − µ V
I OS − Short-Circuit Output Current − mA
12
5
VO(PP) = 2 V
TA = 25°C
VDD = 5 V
100
ÁÁ
ÁÁ
ÁÁ
ÁÁ
VDD = 3 V
10
1
10 3
10 4
10 5
10 6
RL − Load Resistance − kΩ
Figure 24.
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Figure 25.
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LARGE-SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE MARGIN
vs
FREQUENCY
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
40
Phase Margin
20
180°
80
135°
60
90°
45°
Gain
0
0°
−20
−45°
−40
103
104
105
106
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
180°
VDD = 3 V
CL = 100 pF
TA = 25°C
135°
40
20
45°
Gain
0
0°
−20
−45°
103
104
105
Figure 26.
LARGE-SIGNAL DIFFERENTIAL
VOLTAGE AMPLIFICATION
vs
FREE-AIR TEMPERATURE
1000
10000
AVD − Large-Signal Differential Voltage
Amplification − V/mV
AVD − Large-Signal Differential Voltage
Amplification − V/mV
RL = 1 MΩ
RL = 50 kΩ
100
RL = 10 kΩ
VDD = 3 V
VIC = 1.5 V
VO = 0.5 V to 2.5 V
−25
0
25
50
75 100
TA − Free-Air Temperature − °C
125
VDD = 5 V
VIC = 2.5 V
VO = 1 V to 4 V
RL = 1 MΩ
1000
RL = 50 kΩ
100
10
−75
RL = 10 kΩ
−50
−25
0
25
50
75
100
TA − Free-Air Temperature − °C
Figure 28.
20
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−90°
107
Figure 27.
LARGE-SIGNAL DIFFERENTIAL
VOLTAGE AMPLIFICATION
vs
FREE-AIR TEMPERATURE
−50
106
f − Frequency − Hz
f − Frequency − Hz
10
−75
90°
Phase Margin
−40
−90°
107
φom
m − Phase Margin
AVD
A
VD − Large-Signal Differential
Voltage Amplification − dB
60
VDD = 5 V
CL= 100 pF
TA = 25°C
φom
m − Phase Margin
A
AVD
−
VD Large-Signal Differential
Voltage Amplification − dB
80
LARGE-SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE MARGIN
vs
FREQUENCY
125
Figure 29.
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OUTPUT IMPEDANCE
vs
FREQUENCY
100
10
1000
VDD = 3 V
TA = 25°C
VDD = 5 V
TA = 25°C
A V = 100
z o − Output Impedance − Ω
z o − Output Impedance − Ω
1000
OUTPUT IMPEDANCE
vs
FREQUENCY
A V = 10
AV = 1
1
100
A V = 100
10
A V = 10
AV = 1
1
0.1
0.1
10 2
10 3
10 4
f− Frequency − Hz
Figure 30.
10 2
10 5
100
90
VDD = 5 V
VIC = 2.5 V
CMMR − Common-Mode Rejection Ratio − dB
CMRR − Common-Mode Rejection Ratio − dB
10 5
COMMON-MODE REJECTION RATIO
vs
FREE-AIR TEMPERATURE
COMMON-MODE REJECTION RATIO
vs
FREQUENCY
TA = 25°C
80
VDD = 5 V
VIC = 1.5 V
60
40
20
0
10 1
10 3
10 4
f− Frequency − Hz
Figure 31.
10 2
10 4
10 3
f − Frequency − Hz
10 5
10 6
88
86
84
VDD = 5 V
82
80
78
VDD = 3 V
76
74
72
70
− 75 − 50 − 25
0
25 50
75 100
TA − Free-Air Temperature − °C
Figure 32.
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Product Folder Link(s): TLV2262A-Q1 TLV2264A-Q1
125
Figure 33.
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SUPPLY-VOLTAGE REJECTION RATIO
vs
FREQUENCY
SUPPLY-VOLTAGE REJECTION RATIO
vs
FREQUENCY
100
100
80
60
kSVR +
40
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
kSVR −
20
0
−20
10 1
10 2
10 3
10 4
f − Frequency − Hz
Figure 34.
10 5
VDD = 5 V
TA = 25°C
k SVR − Supply-Voltage Rejection Ratio − dB
k SVR − Supply-Voltage Rejection Ratio − dB
VDD = 3 V
TA = 25°C
10 6
80
60
kSVR +
40
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
kSVR −
20
0
−20
10 1
TLV2262
SUPPLY-VOLTAGE REJECTION RATIO
vs
FREE-AIR TEMPERATURE
22
110
VDD = 2.7 V to 8 V
VIC = VO = VDD / 2
105
100
ÁÁ
ÁÁ
ÁÁ
ÁÁ
95
90
−75 −50
−25
0
25
50
75 100
TA − Free-Air Temperature − °C
Figure 36.
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10 3
10 4
f − Frequency − Hz
Figure 35.
10 5
10 6
TLV2264
SUPPLY-VOLTAGE REJECTION RATIO
vs
FREE-AIR TEMPERATURE
k SVR − Supply-Voltage Rejection Ratio − dB
k SVR − Supply-Voltage Rejection Ratio − dB
110
10 2
125
VDD = 2.7 V to 8 V
VIC = VO = VDD / 2
105
100
ÁÁ
ÁÁ
ÁÁ
ÁÁ
95
90
−75
−50
−25
0
25
50
75 100
TA − Free-Air Temperature − °C
Figure 37.
125
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): TLV2262A-Q1 TLV2264A-Q1
TLV2262A-Q1, TLV2264A-Q1
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ÁÁ
ÁÁ
ÁÁ
ÁÁ
TLV2264
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
600
1200
500
1000
I DD − Supply Current − µ A
I DD − Supply Current − µ A
TLV2262
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
VDD = 5 V
VO = 2.5 V
ÁÁ
ÁÁ
ÁÁ
ÁÁ
400
VDD = 3 V
VO = 1.5 V
300
200
−75 −50
−25
0
25
50
75
100
TA − Free-Air Temperature − °C
Figure 38.
VDD = 5 V
VO = 2.5 V
800
VDD = 3 V
VO = 1.5 V
600
400
−75
125
−50
−25
0
25
50
75 100
TA − Free-Air Temperature − °C
Figure 39.
125
SLEW RATE
vs
FREE-AIR TEMPERATURE
SLEW RATE
vs
LOAD CAPACITANCE
1
1.2
SR −
1
SR −
SR − Slew Rate − V/ µ s
SR − Slew Rate − V/ µ s
0.8
0.6
SR +
0.4
0.2
10 2
10 3
CL − Load Capacitance − pF
Figure 40.
10 4
SR +
0.6
0.4
0.2
VDD = 5 V
AV = −1
TA = 25°C
0
10 1
0.8
0
−75
VDD = 5 V
RL = 50 kΩ
CL = 100 pF
AV = 1
−50
−25
0
25
50
75 100
TA − Free-Air Temperature − °C
Copyright © 2008, Texas Instruments Incorporated
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125
Figure 41.
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TLV2262A-Q1, TLV2264A-Q1
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INVERTING LARGE-SIGNAL PULSE
RESPONSE
INVERTING LARGE-SIGNAL PULSE
RESPONSE
3
5
VDD = 3 V
RL = 50 kΩ
CL = 100 pF
AV = −1
TA = 25°C
4
VO − Output Voltage − V
VO − Output Voltage − V
2.5
2
1.5
1
3
2
1
0.5
0
VDD = 5 V
RL = 50 kΩ
CL = 100 pF
AV = −1
TA = 25°C
0
2
4
6
8
10 12 14
t − Time − µs
16
18
0
20
0
2
4
6
Figure 42.
5
VDD = 3 V
RL = 50 kΩ
CL = 100 pF
AV = −1
TA = 25°C
VO − Output Voltage − V
VO − Output Voltage − V
18
20
VDD = 5 V
RL = 50 kΩ
CL = 100 pF
AV = −1
TA = 25°C
4
2
1.5
1
3
2
1
0.5
0
2
4
6
8
10
12
14
16
18
20
0
0
2
4
6
t − Time − µs
Figure 44.
24
16
Figure 43.
3
0
14
VOLTAGE-FOLLOWER LARGE-SIGNAL
PULSE RESPONSE
VOLTAGE-FOLLOWER LARGE-SIGNAL
PULSE RESPONSE
2.5
8
10 12
t − Time − µs
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8
10 12
t − Time − µs
Figure 45.
14
16
18
20
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INVERTING SMALL-SIGNAL
PULSE RESPONSE
INVERTING SMALL-SIGNAL
PULSE RESPONSE
0.95
0.85
VO
VO − Output Voltage − V
0.9
VO − Output Voltage − V
2.65
VDD = 3 V
RL = 50 kΩ
CL = 100 pF
AV = − 1
TA = 25°C
0.8
0.75
0.7
VDD = 5 V
RL = 50 kΩ
CL = 100 pF
2.6 A = − 1
V
TA = 25°C
2.55
2.5
2.45
0.65
0.6
2.4
0
2
4
6
8
10
12
14
16
18
20
0
2
4
6
10
12
14
16
18
20
Figure 47.
VOLTAGE-FOLLOWER SMALL-SIGNAL
PULSE RESPONSE
VOLTAGE-FOLLOWER SMALL-SIGNAL
PULSE RESPONSE
0.95
2.65
VDD = 3 V
RL = 50 kΩ
CL = 100 pF
AV = 1
TA = 25°C
VDD = 5 V
RL = 50 kΩ
CL = 100 pF
AV = 1
TA = 25°C
2.6
VO
VO − Output Voltage − V
0.9
VO
VO − Output Voltage − V
8
t − Time − µs
t − Time − µs
Figure 46.
0.85
0.8
0.75
2.55
2.5
2.45
0.7
2.4
0
2
4
6
8
10 12
t − Time − µs
Figure 48.
14
16
18
20
0
2
4
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): TLV2262A-Q1 TLV2264A-Q1
6
8
10 12
t − Time − µs
Figure 49.
14
16
18
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20
25
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EQUIVALENT INPUT NOISE VOLTAGE
vs
FREQUENCY
EQUIVALENT INPUT NOISE VOLTAGE
vs
FREQUENCY
60
V n − Equivalent Input Noise Voltage − nV/ Hz
V n − Equivalent Input Noise Voltage − nV/ Hz
60
VDD = 3 V
RS = 20 Ω
50 T = 25°C
A
40
30
20
10
0
10 1
10 2
10 3
VDD = 5 V
RS = 20 Ω
50 T = 25°C
A
40
30
20
10
0
10 1
10 4
10 2
f − Frequency − Hz
Figure 50.
10 3
10 4
f − Frequency − Hz
Figure 51.
INPUT NOISE VOLTAGE OVER
A 10-SECOND PERIOD
INTEGRATED NOISE VOLTAGE
vs
FREQUENCY
1000
100
Calculated Using Ideal Pass-Band Filter
Lower Frequency = 1 Hz
TA = 25°C
500
Integrated Noise Voltage − µ V
Input Noise Voltage − nV
750
250
0
−250
−500
−750
−1000
0
VDD = 5 V
f = 0.1 Hz
to 10 Hz
TA = 25°C
2
4
6
t − Time − s
8
10
10
1
0.1
1
10 1
10 2
10 3
10 4
10 5
f − Frequency − Hz
Figure 52.
26
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Figure 53.
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GAIN-BANDWIDTH PRODUCT
vs
SUPPLY VOLTAGE
10 − 1
900
A V = 100
10 − 2
Gain-Bandwidth Product − kHz
THD + N − Total Harmonic Distortion Plus Noise − %
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
FREQUENCY
A V = 10
AV = 1
10 − 3
10 1
860
820
780
740
VDD = 5 V
RL = 50 kΩ
TA = 25°C
10 2
10 3
10 4
700
10 4
0
1
2
f − Frequency − Hz
Figure 54.
Figure 55.
GAIN-BANDWIDTH PRODUCT
vs
FREE-AIR TEMPERATURE
PHASE MARGIN
vs
LOAD CAPACITANCE
1200
8
TA = 25°C
60°
Rnull = 100 Ω
φom
m − Phase Margin
1000
800
Rnull = 50 Ω
45°
Rnull = 20 Ω
30°
Rnull = 10 Ω
50 kΩ
600
15°
50 kΩ
VI
400
−75
7
75°
VDD = 5 V
f = 10 kHz
CL = 100 pF
Gain-Bandwidth Product − kHz
4
6
3
5
VDD − Supply Voltage − V
−50 −25
0
25
50
75
TA − Free-Air Temperature − °C
100
125
VDD +
−
+
Rnull
CL
Rnull = 0
VDD −/GND
0°
10
10 2
10 3
CL − Load Capacitance − pF
Figure 56.
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): TLV2262A-Q1 TLV2264A-Q1
10 4
Figure 57.
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GAIN MARGIN
vs
LOAD CAPACITANCE
UNITY-GAIN BANDWIDTH
vs
LOAD CAPACITANCE
1000
20
RL = 50 kΩ
AV = 1
TA = 25°C
Rnull = 100 Ω
15
Gain Margin − dB
B1 − Unity-Gain Bandwidth − kHz
TA = 25°C
ÁÁ
ÁÁ
ÁÁ
ÁÁ
10
Rnull = 50 Ω
Rnull = 20 Ω
5
Rnull = 10 Ω
Rnull = 0
0
10
10 2
10 3
CL − Load Capacitance − pF
Figure 58.
10 4
800
600
400
200
10
10 2
10 3
CL − Load Capacitance − pF
10 4
Figure 59.
OVERESTIMATION OF PHASE MARGIN
vs
LOAD CAPACITANCE
14°
TA = 25°C
Overestimation of Phase Margin
12°
Rnull = 100 Ω
10°
8°
Rnull = 50 Ω
6°
4°
Rnull = 10 Ω
2°
Rnull = 20 Ω
0
10
10 2
10 3
CL − Load Capacitance − pF
10 4
NOTE: See application information.
Figure 60.
28
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APPLICATION INFORMATION
Driving Large Capacitive Loads
The TLV226x is designed to drive larger capacitive loads than most CMOS operational amplifiers. Figure 51 and
Figure 52 illustrate its ability to drive loads greater than 400 pF while maintaining good gain and phase margins
(Rnull = 0).
A smaller series resistor (Rnull) at the output of the device (see Figure 61) improves the gain and phase margins
when driving large capacitive loads. Figure 51 and Figure 52 show the effects of adding series resistances of 10
Ω, 20 Ω, 50 Ω, and 100 Ω. The addition of this series resistor has two effects: the first is that it adds a zero to the
transfer function and the second is that it reduces the frequency of the pole associated with the output load in the
transfer function.
The zero introduced to the transfer function is equal to the series resistance times the load capacitance. To
calculate the improvement in phase margin, Equation 1 can be used.
ǒ
∆θ m1 + tan–1 2 × π × UGBW × R
null
×C
Ǔ
L
Where :
∆θ m1 + improvement in phase margin
UGBW + unity-gain bandwidth frequency
R null + output series resistance
C L + load capacitance
(1)
The unity-gain bandwidth (UGBW) frequency decreases as the capacitive load increases (see Figure 53). To use
Equation 1, UGBW must be approximated from Figure 53.
Using Equation 1 alone overestimates the improvement in phase margin as illustrated in Figure 60. The
overestimation is caused by the decrease in the frequency of the pole associated with the load, providing
additional phase shift and reducing the overall improvement in phase margin. The pole associated with the load
is reduced by the factor calculated in Equation 2.
1
F +
1 ) gm × R null
Where :
F + factor reducing frequency of pole
g m + small-signal output transconductance (typically 4.83 × 10 – 3 mhos)
R null + output series resistance
(2)
For the TLV226x, the pole associated with the load is typically 7 MHz with 100-pF load capacitance. This value
varies inversely with CL: at CL = 10 pF, use 70 MHz, at CL = 1000 pF, use 700 kHz, and so on.
Reducing the pole associated with the load introduces phase shift, thereby reducing phase margin. This results
in an error in the increase in phase margin expected by considering the zero alone (see Equation 1). Equation 3
approximates the reduction in phase margin due to the movement of the pole associated with the load. The
result of this equation can be subtracted from the result of the Equation 1 to better approximate the improvement
in phase margin.
ȱ
ȧ
Ȳ
ǒ
ȳ
ȧ
ȴ
∆θ m2 + tan–1 UGBW – tan –1 UGBW
P2
ǒF × P2Ǔ
Where :
∆θ m2 + reduction in phase margin
Ǔ
UGBW + unity-gain bandwidth frequency
F + factor from equation (2)
P 2 + unadjusted pole (70 MHz @ 10 pF, 7 MHz @ 100 pF, etc.)
(3)
Using these equations with Figure 60 and Figure 61 enables the designer to choose the appropriate output
series resistance to optimize the design of circuits driving large capacitive loads.
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50 kΩ
VDD +
50 kΩ
VI
Rnull
−
+
CL
VDD − / GND
Figure 61. Series-Resistance Circuit
Macromodel Information
Macromodel information provided was derived using Microsim Parts™, the model generation software used with
Microsim PSpice™. The Boyle macromodel (1) and subcircuit in Figure 62 are generated using the TLV226x
typical electrical and operating characteristics at TA = 25°C. Using this information, output simulations of the
following key parameters can be generated to a tolerance of 20% (in most cases):
• Maximum positive output voltage swing
• Maximum negative output voltage swing
• Slew rate
• Quiescent power dissipation
• Input bias current
• Open-loop voltage amplification
• Unity-gain frequency
• Common-mode rejection ratio
• Phase margin
• DC output resistance
• AC output resistance
• Short-circuit output current limit
(1)
30
G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, "Macromodeling of Integrated Circuit Operational Amplifiers," IEEE
Journal of Solid-State Circuits, SC-9, 353 (1974).
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99
3
VCC +
9
RSS
92
FB
10
J1
DP
VC
J2
IN +
11
VAD
DC
12
C1
RD1
R2
−
53
−
C2
6
−
−
+
VLN
+
GCM
GA
VLIM
8
−
RD2
RO1
DE
5
54
4
DLP
91
+
VLP
7
60
+
−
+
HLIM
−
+
90
RO2
VB
IN −
VCC −
−
+
ISS
RP
2
1
DLN
EGND +
−
+
VE
.SUBCKT TLV226x 1 2 3 4 5
C1
11
12
5.5E−12
C2
6
7
20.00E−12
DC
5
53
DX
DE
54
5
DX
DLP
90
91
DX
DLN
92
90
DX
DP
4
3
DX
EGND
99
0
POLY (2) (3,0) (4,0) 0 .5 .5
FB
7
99
POLY (5) VB VC VE VLP
+ VLN 0 8.84E6 −10E6 10E6 10E6 −10E6
GA
6
0
11
12 62.83E−6
GCM
0
6
10
99 12.34E−9
ISS
3
10
DC 11.05E−6
HLIM
90
0
VLIM 1K
J1
11
2
10 JX
J2
12
1
10 JX
R2
6
9
100.0E3
OUT
RD1
60
11
15.92E3
RD2
60
12
15.92E3
R01
8
5
135
R02
7
99
135
RP
3
4
15.87E3
RSS
10
99
18.18E6
VAD
60
4
−.5
VB
9
0
DC 0
VC
3
53
DC .615
VE
54
4
DC .615
VLIM
7
8
DC 0
VLP
91
0
DC 1
VLN
0
92
DC 5.1
.MODEL DX D (IS=800.0E−18)
.MODEL JX PJF (IS=500.0E−15 BETA=325E−6
+ VTO=−.08)
.ENDS
Figure 62. Boyle Macromodel and Subcircuit
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31
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TLV2262AQPWRQ1
ACTIVE
TSSOP
PW
8
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TQ262A
TLV2264AQPWRQ1
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
P2264AQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
