TLV2332, TLV2332Y, TLV2334, TLV2334Y
LinCMOS LOW-VOLTAGE MEDIUM-POWER
OPERATIONAL AMPLIFIERS
SLOS189 – FEBRUARY 1997
D
D
D
D
D
D
D
D
TLV2332
D OR P PACKAGE
(TOP VIEW)
Wide Range of Supply Voltages Over
Specified Temperature Range:
TA = – 40°C to 85°C . . . 2 V to 8 V
Fully Characterized at 3 V and 5 V
Single-Supply Operation
Common-Mode Input-Voltage Range
Extends Below the Negative Rail and up to
VDD – 1 V at TA = 25°C
Output Voltage Range Includes Negative
Rail
High Input Impedance . . . 1012 Ω Typ
ESD-Protection Circuitry
Designed-In Latch-Up Immunity
1OUT
1IN –
1IN +
VDD– / GND
1
8
2
7
3
6
4
5
VDD
2OUT
2IN –
2IN +
TLV2332
PW PACKAGE
(TOP VIEW)
1
2
3
4
1OUT
1IN–
1IN +
VDD – / GND
description
8
7
6
5
VDD +
2OUT
2IN –
2IN +
TLV2334
D OR N PACKAGE
(TOP VIEW)
The TLV233x operational amplifiers are in a family
of devices that has been specifically designed for
use in low-voltage single-supply applications.
Unlike the TLV2322 which is optimized for
ultra-low power, the TLV233x is designed to
provide a combination of low power and good ac
performance. Each amplifier is fully functional
down to a minimum supply voltage of 2 V, is fully
characterized, tested, and specified at both 3-V
and 5-V power supplies. The common-mode
input-voltage range includes the negative rail and
extends to within 1 V of the positive rail.
1OUT
1IN –
1IN +
VDD +
2IN +
2N –
2OUT
1
14
2
13
3
12
4
11
5
10
6
9
7
8
4OUT
4IN –
4IN +
VDD – / GND
3IN +
3IN –
3OUT
TLV2334
PW PACKAGE
(TOP VIEW)
Having a maximum supply current of only 310 µA
per amplifier over full temperature range, the
TLV233x devices offer a combination of good ac
performance and microampere supply currents.
From a 3-V power supply, the amplifier’s typical
slew rate is 0.38 V/µs and its bandwidth is
300 kHz.
1OUT
1IN –
1IN +
VDD +
2IN +
2IN –
2OUT
1
14
7
8
4OUT
4IN –
4IN +
VDD – / GND
3IN +
3IN –
3OUT
AVAILABLE OPTIONS
TA
– 40°C to 85°C
VIOmax
AT 25°C
PACKAGED DEVICES
SMALL OUTLINE†
(D)
PLASTIC DIP
(N)
PLASTIC DIP
(P)
TSSOP‡
(PW)
CHIP FORM§
(Y)
9 mV
TLV2332ID
—
TLV2332IP
TLV2332IPWLE
TLV2332Y
10 mV
TLV2334ID
TLV2334IN
—
TLV2334IPWLE
TLV2334Y
† The D package is available taped and reeled. Add R suffix to the device type (e.g., TLV2332IDR).
‡ The PW package is only available left-end taped and reeled (e.g., TLV2332IPWLE).
§ Chip forms are tested at 25°C only.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
LinCMOS is a trademark of Texas Instruments Incorporated.
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
TLV2332, TLV2332Y, TLV2334, TLV2334Y
LinCMOS LOW-VOLTAGE MEDIUM-POWER
OPERATIONAL AMPLIFIERS
SLOS189 – FEBRUARY 1997
description (continued)
These amplifiers offer a level of ac performance greater than that of many other devices operating at
comparable power levels. The TLV233x operational amplifiers are especially well suited for use in low-current
or battery-powered applications.
Low-voltage and low-power operation has been made possible by using the Texas Instruments silicon-gate
LinCMOS technology. The LinCMOS process also features extremely high input impedance and ultra-low bias
currents making these amplifiers ideal for interfacing to high-impedance sources such as sensor circuits or filter
applications.
To facilitate the design of small portable equipment, the TLV233x is made available in a wide range of package
options, including the small-outline and thin-shrink small-outline package (TSSOP). The TSSOP package has
significantly reduced dimensions compared to a standard surface-mount package. Its maximum height of only
1.1 mm makes it particularly attractive when space is critical.
The device inputs and outputs are designed to withstand –100-mA currents without sustaining latch-up. The
TLV233x incorporates internal ESD-protection circuits that prevents functional failures at voltages up to
2000 V as tested under MIL-STD 883C, Method 3015.2; however, care should be exercised in handling these
devices as exposure to ESD may result in the degradation of the device parametric performance.
TLV2332Y chip information
This chip, when properly assembled, display characteristics similar to the TLV2332. Thermal compression or
ultrasonic bonding may be used on the doped-aluminum bonding pads. Chips may be mounted with conductive
epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
(5)
(4)
(3)
1IN +
(2)
(6)
VDD
(8)
(3)
+
(2)
1IN –
(1)
1OUT
–
(5)
59
2OUT
(7)
+
–
(6)
2IN +
2IN –
(4)
VDD – / GND
CHIP THICKNESS: 15 MILS TYPICAL
(1)
(7)
(8)
BONDING PADS: 4 × 4 MILS MINIMUM
TJmax = 150°C
TOLERANCES ARE ± 10%.
72
ALL DIMENSIONS ARE IN MILS.
PIN (4) IS INTERNALLY CONNECTED
TO BACKSIDE OF CHIP.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TLV2332, TLV2332Y, TLV2334, TLV2334Y
LinCMOS LOW-VOLTAGE MEDIUM-POWER
OPERATIONAL AMPLIFIERS
SLOS189 – FEBRUARY 1997
TLV2334Y chip information
This chip, when properly assembled, displays characteristics similar to the TLV2334. Thermal compression or
ultrasonic bonding may be used on the doped-aluminum bonding pads. Chips may be mounted with conductive
epoxy or a gold-silicon preform.
VDD
(4)
BONDING PAD ASSIGNMENTS
(14)
(13)
(12) (11)
(10)
(9)
(8)
1IN +
(3)
+
–
1IN –
2IN +
2IN –
68
3IN +
(1)
1OUT
(2)
(5)
+
(6)
(7)
2OUT
–
(10)
+
(8)
3OUT
(9)
–
3IN –
(12)
+
4IN +
(1)
(2)
(3)
(4) (5)
(6)
(7)
4IN –
(14)
(13)
4OUT
–
(11)
108
VDD– /GND
CHIP THICKNESS: 15 MILS TYPICAL
BONDING PADS: 4 × 4 MILS MINIMUM
TJmax = 150°C
TOLERANCES ARE ± 10%.
ALL DIMENSIONS ARE IN MILS.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
TLV2332, TLV2332Y, TLV2334, TLV2334Y
LinCMOS LOW-VOLTAGE MEDIUM-POWER
OPERATIONAL AMPLIFIERS
SLOS189 – FEBRUARY 1997
equivalent schematic (each amplifier)
VDD
P4
P3
R6
P2
P1
IN –
N5
R2
R1
IN +
R5
P5
C1
N3
P6
OUT
N4
N1
R3
D1
N2
N6
N7
D2
R4
R7
GND
ACTUAL DEVICE COMPONENT COUNT†
COMPONENT
TLV2332
TLV2334
Transistors
54
108
Resistors
14
28
Diodes
4
8
Capacitors
2
4
† Includes both amplifiers and all ESD, bias, and trim
circuitry.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TLV2332, TLV2332Y, TLV2334, TLV2334Y
LinCMOS LOW-VOLTAGE MEDIUM-POWER
OPERATIONAL AMPLIFIERS
SLOS189 – FEBRUARY 1997
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 V
Differential input voltage, VID (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD ±
Input voltage range, VI (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VDD
Input current, II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 5 mA
Output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 30 mA
Duration of short-circuit current at (or below) TA = 25°C (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . unlimited
Continuous total dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential voltages, are with respect to network ground.
2. Differential voltages are at the noninverting input with respect to the inverting input.
3. The output may be shorted to either supply. Temperature and /or supply voltages must be limited to ensure that the maximum
dissipation rating is not exceeded (see application section).
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 85°C
POWER RATING
D–8
725 mW
5.8 mW/°C
377 mW
D–14
950 mW
7.6 mW/°C
494 mW
N
1575 mW
12.6 mW/°C
819 mW
P
1000 mW
8.0 mW/°C
520 mW
PW–8
525 mW
4.2 mW/°C
273 mW
PW–14
700 mW
5.6 mW/°C
364 mW
recommended operating conditions
Supply voltage, VDD
Common mode input voltage,
Common-mode
voltage VIC
VDD = 3 V
VDD = 5 V
Operating free-air temperature, TA
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MIN
MAX
2
8
– 0.2
1.8
– 0.2
3.8
– 40
85
UNIT
V
V
°C
5
TLV2332, TLV2332Y, TLV2334, TLV2334Y
LinCMOS LOW-VOLTAGE MEDIUM-POWER
OPERATIONAL AMPLIFIERS
SLOS189 – FEBRUARY 1997
TLV2332I electrical characteristics at specified free-air temperature
TLV2332I
PARAMETER
VIO
Input offset voltage
TEST
CONDITIONS
VO = 1 V,
VIC = 1 V,,
RS = 50 Ω,
RL = 100 kΩ
TA†
VDD = 3 V
MIN
TYP
MAX
VDD = 5 V
MIN
TYP
MAX
25°C
0.6
1.1
11
Average temperature coefficient of
input offset voltage
25°C to
85°C
IIO
Input offset current (see Note 4)
VO = 1 V,,
VIC = 1 V
IIB
Input bias current (see Note 4)
VO = 1 V,,
VIC = 1 V
25°C
0.6
85°C
175
VIC = 1 V,
VID = 100 mV
mV,
IOH = – 1 mA
High-level
High level output voltage
VOL
Low level output voltage
Low-level
AVD
Large-signal
g
g
differential
voltage amplification
VIC = 1 V,
RL = 100 kΩ
kΩ,
See Note 6
CMRR
Common mode rejection ratio
Common-mode
VO = 1 V,
min,
VIC = VICRmin
RS = 50 Ω
VIC = 1 V,
VID = – 100 mV
mV,
IOL = 1 mA
kSVR
Supply-voltage
y
g rejection
j
ratio
(∆VDD /∆VIO)
VIC = 1 V,
VO = 1 V,
V
RS = 50 Ω
IDD
Supply current
VO = 1 V,
VIC = 1 V
V,
No load
11
1
1.7
25°C
0.1
0.1
85°C
22
25°C
– 0.2
to
2
Full range
– 0.2
to
1.8
25°C
1.75
Full range
1.7
Common-mode input
voltage range (see Note 5)
VOH
1000
24
2000
200
µV/°C
1000
0.6
– 0.3
to
2.3
– 0.2
to
4
2000
– 0.3
to
4.2
1.9
3.2
pA
pA
V
– 0.2
to
3.8
3.9
V
25°C
3
115
150
95
150
mV
Full range
190
25°C
25
Full range
15
25°C
65
Full range
60
25°C
70
Full range
65
83
190
25
170
V/mV
15
92
65
91
dB
60
94
70
94
dB
25°C
Full range
65
160
500
210
620
† Full range is – 40°C to 85°C.
NOTES: 4. The typical values of input bias current and input offset current below 5 pA are determined mathematically.
5. This range also applies to each input individually.
6. At VDD = 5 V, VO = 0.25 V to 2 V; at VDD = 3 V, VO = 0.5 V to 1.5 V.
6
9
mV
Full range
αVIO
VICR
9
UNIT
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
560
800
µA
TLV2332, TLV2332Y, TLV2334, TLV2334Y
LinCMOS LOW-VOLTAGE MEDIUM-POWER
OPERATIONAL AMPLIFIERS
SLOS189 – FEBRUARY 1997
TLV2332I operating characteristics at specified free-air temperature, VDD = 3 V
PARAMETER
SR
Slew rate at unity gain
TEST CONDITIONS
VIC = 1 V,
RL = 100 kΩ
kΩ,
See Figure 34
VI(PP) = 1 V,
CL = 20 pF
F,
TA
TLV2332I
MIN
TYP
25°C
0.38
85°C
0.29
25°C
32
MAX
UNIT
V/µs
Vn
Equivalent input noise voltage
f =1 kHz,
See Figure 35
RS = 20 Ω,
BOM
Maximum output
output-swing
swing bandwidth
VO = VOH,
RL = 100 kΩ,
CL = 20 pF,,
See Figure 34
25°C
34
85°C
32
B1
Unity gain bandwidth
Unity-gain
VI = 10 mV,,
RL = 100 kΩ,
CL = 20 pF,,
See Figure 36
25°C
300
85°C
235
f = B1,
RL = 100 kΩ,
42°
Phase margin
VI = 10 mV,
CL = 20 pF,
See Figure 36
– 40°C
φm
25°C
39°
85°C
36°
nV/√Hz
kHz
kHz
TLV2332I operating characteristics at specified free-air temperature, VDD = 5 V
PARAMETER
SR
Slew rate at unity gain
TEST CONDITIONS
VIC = 1 V
V,
RL = 100 kΩ,,
CL = 20 pF,
S Figure
See
Fi
34
VI(PP) = 1 V
RS = 20 Ω,
5V
VI(PP) = 2
2.5
TA
TLV2332I
MIN
TYP
25°C
0.43
85°C
0.35
25°C
0.40
85°C
0.32
25°C
32
Vn
Equivalent input noise voltage
f =1 kHz,
See Figure 35
BOM
swing bandwidth
Maximum output
output-swing
VO = VOH,
RL = 100 kΩ,
CL = 20 pF,,
See Figure 34
25°C
55
85°C
45
B1
Unity gain bandwidth
Unity-gain
VI = 10 mV,,
RL = 100 kΩ,
CL = 20 pF,,
See Figure 36
25°C
525
85°C
370
f = B1,
RL = 100 kΩ,
43°
Phase margin
VI = 10 mV,
CL = 20 pF,
See Figure 36
– 40°C
φm
25°C
40°
85°C
38°
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MAX
UNIT
V/µs
nV/√Hz
kHz
kHz
7
TLV2332, TLV2332Y, TLV2334, TLV2334Y
LinCMOS LOW-VOLTAGE MEDIUM-POWER
OPERATIONAL AMPLIFIERS
SLOS189 – FEBRUARY 1997
TLV2334I electrical characteristics at specified free-air temperature
TLV2334I
PARAMETER
TEST CONDITIONS
TA†
VDD = 3 V
MIN
TYP
MAX
VDD = 5 V
MIN
TYP
MAX
0.6
1.1
Input offset voltage
VO = 1 V, VIC = 1 V,
RS = 50 Ω,
Ω
RL = 100 kΩ
25°C
VIO
αVIO
Average temperature coefficient
of input offset voltage
IIO
Input offset current (see Note 4)
V VIC = 1 V
VO = 1 V,
IIB
Input bias current (see Note 4)
VO = 1 V,
V VIC = 1 V
VICR
12
VIC = 1 V,
VID = 100 mV
mV,
IOH = – 1 mA
VOL
Low level output voltage
Low-level
AVD
Large-signal
g
g
differential
voltage amplification
VIC = 1 V,
RL = 100 kΩ
kΩ,
See Note 6
CMRR
Common mode rejection ratio
Common-mode
VO = 1 V,
VIC = VICRmin
min,
RS = 50 Ω
VIC = 1 V,
VID = – 100 mV
mV,
IOL = 1 mA
12
1
25°C
0.1
85°C
22
25°C
0.6
85°C
175
25°C
– 0.2
to
2
Full range
– 0.2
to
1.8
25°C
1.75
Full range
1.7
Common-mode input voltage
g
range (see Note 5)
High level output voltage
High-level
µV/°C
1.7
0.1
1000
24
2000
200
1000
0.6
– 0.3
to
2.3
– 0.2
to
4
2000
– 0.3
to
4.2
3.2
pA
V
– 0.2
to
3.8
1.9
pA
V
3.9
V
25°C
3
115
150
95
150
mV
Full range
190
25°C
25
Full range
15
25°C
65
Full range
60
83
190
25
170
V/mV
15
92
65
91
dB
Supply-voltage
y
g rejection
j
ratio
(∆VDD /∆VIO)
VDD = 3 V to 5 V,
VIC = 1 V
V, VO = 1 V
V,
RS = 50 Ω
25°C
70
kSVR
Full range
65
IDD
Supply current
VO = 1 V, VIC = 1 V,
No load
Full range
60
94
70
94
dB
25°C
65
320
1000
420
1200
† Full range is – 40°C to 85°C.
NOTES: 4. The typical values of input bias current and input offset current below 5 pA are determined mathematically.
5. This range also applies to each input individually.
6. At VDD = 5 V, VO = 0.25 V to 2 V; at VDD = 3 V, VO = 0.5 V to 1.5 V.
8
10
mV
Full range
25°C to
85°C
VOH
10
UNIT
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1120
1600
µA
TLV2332, TLV2332Y, TLV2334, TLV2334Y
LinCMOS LOW-VOLTAGE MEDIUM-POWER
OPERATIONAL AMPLIFIERS
SLOS189 – FEBRUARY 1997
TLV2334I operating characteristics at specified free-air temperature, VDD = 3 V
PARAMETER
SR
Slew rate at unity gain
TEST CONDITIONS
VIC = 1 V,
RL = 100 kΩ
kΩ,
See Figure 34
VI(PP) = 1 V,
CL = 20 pF
F,
TA
TLV2334I
MIN
TYP
25°C
0.38
85°C
0.29
25°C
32
UNIT
V/µs
Vn
Equivalent input noise voltage
f = 1 kHz,
See Figure 35
RS = 20 Ω,
BOM
Maximum output
output-swing
swing bandwidth
VO = VOH,
RL = 100 kΩ,
CL = 20 pF,,
See Figure 34
25°C
34
85°C
32
B1
Unity gain bandwidth
Unity-gain
VI = 10 mV,,
RL = 100 kΩ,
CL = 20 pF,,
See Figure 36
25°C
300
85°C
235
– 40°C
42°
Phase margin
VI = 10 mV,
CL = 20 pF,
S Figure
See
Fi
36
f = B1,
RL = 100 kΩ,
25°C
39°
85°C
36°
φm
MAX
nV/√Hz
kHz
kHz
TLV2334I operating characteristics at specified free-air temperature, VDD = 5 V
PARAMETER
SR
Slew rate at unity gain
TEST CONDITIONS
VIC = 1 V
V,
RL = 100 kΩ,,
CL = 20 pF,
S Figure
See
Fi
34
VI(PP) = 1 V
5V
VI(PP) = 2
2.5
TA
TLV2334I
MIN
TYP
25°C
0.43
85°C
0.35
25°C
0.40
85°C
0.32
25°C
32
Vn
Equivalent input noise voltage
f = 1 kHz,
See Figure 35
RS = 20 Ω,
BOM
swing bandwidth
Maximum output
output-swing
VO = VOH,
RL = 100 kΩ,
CL = 20 pF,,
See Figure 34
25°C
55
85°C
45
B1
Unity gain bandwidth
Unity-gain
VI = 10 mV,,
RL = 100 kΩ,
CL = 20 pF,,
See Figure 36
25°C
525
85°C
370
f = B1,
RL = 100 kΩ,
– 40°C
43°
Phase margin
VI = 10 mV,
CL = 20 pF,
S Figure
Fi
See
36
25°C
40°
85°C
38°
φm
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MAX
UNIT
V/µs
nV/√Hz
kHz
kHz
9
TLV2332, TLV2332Y, TLV2334, TLV2334Y
LinCMOS LOW-VOLTAGE MEDIUM-POWER
OPERATIONAL AMPLIFIERS
SLOS189 – FEBRUARY 1997
TLV2332Y electrical characteristics, TA = 25°C
TLV2332Y
PARAMETER
VIO
Input offset voltage
IIO
IIB
Input offset current (see Note 4)
Input bias current (see Note 4)
TEST CONDITIONS
VO = 1 V,
RS = 50 Ω,
VIC = 1 V,
RL = 100 kΩ
VO = 1 V,
VO = 1 V,
VIC = 1 V
VIC = 1 V
VDD = 3 V
MIN
TYP
MAX
MIN
VDD = 5 V
TYP
MAX
UNIT
0.6
1.1
mV
0.1
0.1
pA
0.6
0.6
pA
– 0.3
to
2.3
– 0.3
to
4.2
V
VICR
Common-mode input voltage
range (see Note 5)
VOH
High-level output voltage
VIC = 1 V,
IOH = – 1 mA
VID = 100 mV,
1.9
3.9
V
VOL
Low-level output voltage
VIC = 1 V,
IOL = 1 mA
VID = 100 mV,
115
95
mV
AVD
Large-signal differential voltage
amplification
VIC = 1 V,
See Note 6
RL = 100 kΩ,
83
170
V/mV
CMRR
Common-mode rejection ratio
VO = 1 V,
RS = 50 Ω
VIC = VICRmin,
92
91
dB
kSVR
Supply-voltage rejection ratio
(∆VDD /∆VID)
VO = 1 V,
RS = 50 Ω
VIC = 1 V,
94
94
dB
IDD
Supply current
VO = 1 V,
No load
VIC = 1 V,
160
210
µA
NOTES: 4.
5.
6.
10
The typical values of input bias current and input offset current below 5 pA are determined mathematically.
This range also applies to each input individually.
At VDD = 5 V, VO = 0.25 V to 2 V; at VDD = 3 V, VO = 0.5 V to 1.5 V.
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TLV2334Y electrical characteristics, TA = 25°C
TLV2334Y
PARAMETER
VIO
Input offset voltage
IIO
IIB
Input offset current (see Note 4)
Input bias current (see Note 4)
TEST CONDITIONS
VO = 1 V,
RS = 50 Ω,
VIC = 1 V
RL = 100 kΩ
VO = 1 V,
VO = 1 V,
VIC = 1 V
VIC = 1 V
VDD = 3 V
MIN
TYP
MAX
VDD = 5 V
TYP
MAX
UNIT
MIN
0.6
1.1
mV
0.1
0.1
pA
0.6
0.6
pA
– 0.3
to
2.3
– 0.3
to
4.2
V
VICR
Common-mode input voltage
range (see Note 5)
VOH
High-level output voltage
VIC = 1 V,
VID = 100 mV,
IOH = – 1 mA
1.9
3.9
V
VOL
Low-level output voltage
VIC = 1 V,
IOL = 1 mA
VID = – 100 mV,
115
95
mV
AVD
Large-signal differential voltage
amplification
VIC = 1 V,
See Note 6
RL = 100 kΩ,
83
170
V/mV
CMRR
Common-mode rejection ratio
VO = 1 V,
RS = 50 Ω
VIC = VICRmin,
92
91
dB
kSVR
Supply-voltage rejection ratio
(∆VDD /∆VID)
VIC = 1 V,
RS = 50 Ω
VO = 1 V,
94
94
dB
IDD
Supply current
VO = 1 V,
No load
VIC = 1 V,
320
420
µA
NOTES: 4. The typical values of input bias current offset current below 5 pA are determined mathematically.
5. This range also applies to each input individually.
6. At VDD = 5 V, VO = 0.25 V to 2 V; at VDD = 3 V, VO = 0.5 V to 1.5 V.
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TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
VIO
αVIO
Input offset voltage
Distribution
1–4
Input offset voltage temperature coefficient
Distribution
5–8
IIB
IIO
Input bias current
vs Free-air temperature
Input offset current
vs Free-air temperature
9
VIC
Common-mode input voltage
vs Supply voltage
10
VOH
High-level output voltage
vs High-level output current
vs Supply voltage
vs Free-air temperature
11
12
13
VOL
Low-level output voltage
vs Common-mode input voltage
vs Free-air temperature
vs Differential input voltage
vs Low-level output current
14
15, 16
17
18
AVD
Large-signal differential voltage amplification
vs Supply voltage
vs Free-air temperature
vs Frequency
19
20
21, 22
IDD
Supply current
vs Supply voltage
vs Free-air temperature
23
24
SR
Slew rate
vs Supply voltage
vs Free-air temperature
25
26
VO(PP)
Maximum peak-to-peak output voltage
vs Frequency
27
B1
Unity-gain bandwidth
vs Supply voltage
vs Free-air temperature
28
29
φm
Phase margin
vs Supply voltage
vs Free-air temperature
vs Load capacitance
30
31
32
Phase shift
vs Frequency
21, 22
Equivalent input noise voltage
vs Frequency
33
Vn
12
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TYPICAL CHARACTERISTICS
DISTRIBUTION OF TLV2332
INPUT OFFSET VOLTAGE
50
DISTRIBUTION OF TLV2332
INPUT OFFSET VOLTAGE
60
VDD = 3 V
TA = 25°C
P Package
50
Percentage of Units – %
Percentage of Units – %
40
30
20
10
VDD = 5 V
TA = 25°C
P Package
40
30
20
10
0
–5 –4 –3 –2 –1 0
1
2
3
VIO – Input Offset Voltage – mV
4
0
–5 –4 –3 –2 –1 0
1
2
3
VIO – Input Offset Voltage – mV
5
5
4
5
Figure 2
Figure 1
DISTRIBUTION OF TLV2334
INPUT OFFSET VOLTAGE
50
4
DISTRIBUTION OF TLV2334
INPUT OFFSET VOLTAGE
60
VDD = 3 V
TA = 25°C
N Package
50
VDD = 5 V
TA = 25°C
N Package
Percentage of Units – %
Percentage of Units – %
40
30
20
40
30
20
10
10
0
–5 –4
–3
–2
–1
0
1
2
3
4
5
0
–5
–4
–3
–2
–1
0
1
2
3
VIO – Input Offset Voltage – mV
VIO – Input Offset Voltage – mV
Figure 3
Figure 4
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TYPICAL CHARACTERISTICS
DISTRIBUTION OF TLV2332
INPUT OFFSET VOLTAGE
TEMPERATURE COEFFICIENT
DISTRIBUTION OF TLV2332
INPUT OFFSET VOLTAGE
TEMPERATURE COEFFICIENT
60
50
VDD = 3 V
TA = 25°C to 85°C
P Package
50
Percentage of Units – %
Percentage of Units – %
40
30
20
10
40
VDD = 5 V
TA = 25°C to 85°C
P Package
Outliers:
(1) 33 mV/°C
30
20
10
0
– 10 – 8 – 6 – 4 – 2 0
2
4
6
8
αVIO – Temperature Coefficient – µV/°C
0
– 10 – 8 – 6 – 4 – 2 0
2
4
6
8
αVIO – Temperature Coefficient – µV/°C
10
Figure 5
Figure 6
DISTRIBUTION OF TLV2334
INPUT OFFSET VOLTAGE
TEMPERATURE COEFFICIENT
DISTRIBUTION OF TLV2334
INPUT OFFSET VOLTAGE
TEMPERATURE COEFFICIENT
50
60
VDD = 3 V
TA = 25°C to 85°C
N Package
50
Percentage of Units – %
Percentage of Units – %
40
30
20
10
0
–10 – 8
VDD = 5 V
TA = 25°C to 85°C
N Package
Outliers:
(1) 33 mV/°C
40
30
20
10
–6
–4
–2
0
2
4
6
8
10
0
–10 – 8
αVIO – Temperature Coefficient – µV/°C
–6
–4
–2
0
Figure 8
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4
6
8
αVIO – Temperature Coefficient – µV/°C
Figure 7
14
10
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COMMON-MODE INPUT VOLTAGE
vs
SUPPLY VOLTAGE
INPUT BIAS CURRENT AND INPUT OFFSET CURRENT
vs
FREE-AIR TEMPERATURE
8
104
VDD = 3 V
VIC = 1 V
See Note A
103
102
VVIC
IC – Common-Mode Input Voltage – V
IIB
I IB and IIIO
IO – Input Bias and Input Offset Currents – pA
TYPICAL CHARACTERISTICS
IIB
101
IIO
1
0.1
25
TA = 25°C
Positive Limit
6
4
2
0
45
65
85
105
TA – Free-Air Temperature – °C
0
125
2
4
6
VDD – Supply Voltage – V
8
NOTE: The typical values of input bias current and input offset
current below 5 pA were determined mathematically.
Figure 9
Figure 10
HIGH-LEVEL OUTPUT VOLTAGE
vs
SUPPLY VOLTAGE
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
8
VIC = 1 V
VID = 100 mV
TA = 25°C
4
VV0H
OH – High-Level Output Voltage – V
VV0H
OH – High-Level Output Voltage – V
5
VDD = 5 V
3
VDD = 3 V
2
1
VIC = 1 V
VID = 100 mV
RL = 100 kΩ
TA = 25°C
6
4
2
0
0
0
–2
–4
–6
–8
0
IOH – High-Level Output Current – mA
2
4
6
VDD – Supply Voltage – V
8
Figure 12
Figure 11
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TLV2332, TLV2332Y, TLV2334, TLV2334Y
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SLOS189 – FEBRUARY 1997
TYPICAL CHARACTERISTICS
HIGH-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
2.4
700
VDD = 3 V
VIC = 1 V
VID = 100 mV
1.8
1.2
0.6
IOH = – 500 µA
IOH = – 1 mA
IOH = – 2 mA
IOH = – 3 mA
IOH = – 4 mA
0
– 75
– 50
VDD = 5 V
IOL = 5 mA
TA = 25°C
650
VOL
VOL – Low-Level Output Voltage – mV
VV0H
OH – High-Level Output Voltage – V
3
LOW-LEVEL OUTPUT VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
– 25
0
25
50
75 100
TA – Free-Air Temperature – °C
600
550
VID = –100 mV
500
450
400
VID = –1 V
350
300
125
0
0.5
1
1.5
2
2.5
3
3.5
VIC – Common-Mode Input Voltage – V
Figure 13
Figure 14
LOW-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
185
170
900
VDD = 3 V
VIC = 1 V
VID = – 100 mV
IOL = 1 mA
VOL
VOL – Low-Level Output Voltage – mV
VOL
VOL – Low-Level Output Voltage – mV
200
LOW-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
155
140
125
110
95
80
65
50
– 75
800
700
VDD = 5 V
VIC = 0.5 V
VID = – 1 V
IOL = 5 mA
600
500
400
300
200
100
– 50
– 25
0
25
50
75 100
TA – Free-Air Temperature – °C
125
0
– 75
– 50
Figure 15
16
– 25
0
25
50
75 100
TA – Free-Air Temperature – °C
Figure 16
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TYPICAL CHARACTERISTICS
LOW-LEVEL OUTPUT VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
1
VDD = 5 V
VIC = |VID / 2|
IOL = 5 mA
TA = 25°C
700
600
VOL
VOL – Low-Level Output Voltage – V
VOL
VOL – Low-Level Output Voltage – mV
800
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
500
400
300
200
100
VIC = 1 V
VID = – 100 mV
TA = 25°C
0.9
0.8
VDD = 5 V
0.7
0.6
0.5
VDD = 3 V
0.4
0.3
0.2
0.1
0
0
0
–1
–2
–3
–4
–5
–6
–7
VID – Differential Input Voltage – V
–8
7
1
2
3
4
5
6
IOL – Low-Level Output Current – mA
0
Figure 17
Figure 18
LARGE-SIGNAL
DIFFERENTIAL VOLTAGE AMPLIFICATION
vs
SUPPLY VOLTAGE
LARGE-SIGNAL
DIFFERENTIAL VOLTAGE AMPLIFICATION
vs
FREE-AIR TEMPERATURE
500
500
RL = 100 kΩ
450
450
A VD – Large-Signal Differential Voltage
Amplification – V/mV
A VD – Large-Signal Differential Voltage
Amplification – V/mV
RL = 100 kΩ
400
350
TA = – 40°C
300
250
TA = 25°C
200
150
TA = 85°C
100
50
0
8
0
2
4
6
8
400
350
300
250
VDD = 5 V
200
150
VDD = 3 V
100
50
0
– 75
– 50
– 25
0
25
50
75
100
125
TA – Free-Air Temperature – °C
VDD – Supply Voltage – V
Figure 19
Figure 20
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TYPICAL CHARACTERISTICS
107
– 60°
VDD = 3 V
RL = 100 kΩ
CL = 20 pF
TA = 25°C
106
105
– 30°
0°
104
30°
Phase Shift
A VD – Large-Signal Differential Voltage Amplification
LARGE-SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE SHIFT
vs
FREQUENCY
AVD
103
60°
102
90°
Phase Shift
101
120°
1
150°
0.1
1
10
100
1k
10 k
180°
1M
100 k
f – Frequency – Hz
Figure 21
107
– 60°
VDD = 5 V
RL = 100 kΩ
CL = 20 pF
TA = 25°C
106
105
104
0°
30°
AVD
103
60°
102
90°
Phase Shift
101
120°
1
150°
0.1
1
10
100
1k
10 k
f – Frequency – Hz
100 k
Figure 22
18
– 30°
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180°
1M
Phase Shift
A VD – Large-Signal Differential Voltage Amplification
LARGE-SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE SHIFT
vs
FREQUENCY
TLV2332, TLV2332Y, TLV2334, TLV2334Y
LinCMOS LOW-VOLTAGE MEDIUM-POWER
OPERATIONAL AMPLIFIERS
SLOS189 – FEBRUARY 1997
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
400
450
VIC = 1 V
VO = 1 V
No Load
350
TA = – 40°C
350
uA
IIDD
A
DD – Supply Current – µ
uA
IIDD
A
DD – Supply Current – µ
400
300
TA = 25°C
250
200
TA = 85°C
150
100
300
250
VDD = 5 V
VDD = 3 V
200
150
100
50
50
0
VIC = 1 V
VO = 1 V
No Load
0
2
4
6
0
– 75
8
– 50
VDD – Supply Voltage – V
– 25
0
25
50
75 100
TA – Free-Air Temperature – °C
Figure 23
Figure 24
SLEW RATE
vs
SUPPLY VOLTAGE
0.9
0.9
0.7
0.8
V/µ s
SR – Slew Rate – V/us
V/µ s
SR – Slew Rate – V/us
SLEW RATE
vs
FREE-AIR TEMPERATURE
VIC = 1 V
VI(PP) = 1 V
AV = 1
RL = 100 kΩ
CL = 20 pF
TA = 25°C
0.8
125
0.6
0.5
0.7
VIC = 1 V
VI(PP) = 1 V
AV = 1
RL = 100 kΩ
CL = 20 pF
0.6
0.5
VDD = 5 V
0.4
VDD = 3 V
0.4
0.3
0.3
0
2
4
6
VDD – Supply Voltage – V
8
0.2
– 75
– 50
– 25
0
25
50
75
100
125
TA – Free-Air Temperature – °C
Figure 25
Figure 26
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TYPICAL CHARACTERISTICS
UNITY-GAIN BANDWIDTH
vs
SUPPLY VOLTAGE
1000
5
VI = 10 mV
RL = 100 kΩ
CL = 20 pF
TA = 25°C
RL = 100 kΩ
900
VDD = 5 V
4
B1 – Unity-Gain Bandwidth – kHz
B1
V O(PP) – Maximum Peak-to-Peak Output Voltage – V
MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE
vs
FREQUENCY
TA = – 40°C
3
VDD = 3 V
2
TA = 85°C
1
800
700
600
500
400
300
TA = 25°C
200
0
1
10
100
f – Frequency – kHz
0
1000
1
2
Figure 27
1000
VI = 10 mV
RL = 100 kΩ
CL = 20 pF
B1 – Unity-Gain Bandwidth – kHz
B1
900
800
700
600
VDD = 5 V
500
400
VDD = 3 V
300
– 50
– 25
0
25
50
75 100
TA – Free-Air Temperature – °C
Figure 29
20
4
Figure 28
UNITY-GAIN BANDWIDTH
vs
FREE-AIR TEMPERATURE
200
– 75
3
5
6
VDD – Supply Voltage – V
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TYPICAL CHARACTERISTICS
PHASE MARGIN
vs
SUPPLY VOLTAGE
PHASE MARGIN
vs
FREE-AIR TEMPERATURE
50°
45°
VI = 10 mV
RL = 100 kΩ
CL = 20 pF
TA = 25°C
48°
43°
44°
xm
φ m – Phase Margin
xm
φ m – Phase Margin
46°
VI = 10 mV
RL = 100 kΩ
CL = 20 pF
42°
40°
38°
36°
34°
43°
VDD = 5 V
39°
VDD = 3 V
37°
32°
30°
0
1
2
3
4
5
6
7
35°
– 75 – 50 – 25
0
25
50
75 100
TA – Free-Air Temperature – °C
8
VDD – Supply Voltage – V
Figure 31
Figure 30
PHASE MARGIN
vs
LOAD CAPACITANCE
EQUIVALENT INPUT NOISE VOLTAGE
vs
FREQUENCY
44°
300
VVn
nVxHz
Hz
n – Equivalent Input Noise Voltage – nV/
VI = 10 mV
RL = 100 KΩ
TA = 25°C
42°
xm
φ m – Phase Margin
40°
VDD = 5 V
38°
VDD = 3 V
36°
34°
32°
30°
28°
0
125
RS = 20 Ω
TA = 25°C
250
200
150
100
VDD = 5 V
VDD = 3 V
50
0
20
40
60
80
100
1
CL – Load Capacitance – pF
10
100
1000
f – Frequency – Hz
Figure 32
Figure 33
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PARAMETER MEASUREMENT INFORMATION
single-supply versus split-supply test circuits
Because the TLV233x is optimized for single-supply operation, circuit configurations used for the various tests
often present some inconvenience since the input signal, in many cases, must be offset from ground. This
inconvenience can be avoided by testing the device with split supplies and the output load tied to the negative
rail. A comparison of single-supply versus split-supply test circuits is shown below. The use of either circuit gives
the same result.
VDD
VDD +
–
+
VI
–
VO
VO
+
VI
RL
CL
CL
RL
VDD –
(a) SINGLE SUPPLY
(b) SPLIT SUPPLY
Figure 34. Unity-Gain Amplifier
2 kΩ
2 kΩ
VDD
VDD +
20 Ω
–
1/2 VDD
–
VO
+
+
20 Ω
20 Ω
VO
20 Ω
VDD –
(a) SINGLE SUPPLY
(b) SPLIT SUPPLY
Figure 35. Noise-Test Circuit
10 kΩ
10 kΩ
VDD
VDD +
100 Ω
VI
–
1/2 VDD
+
VI
100 Ω
VO
–
+
CL
CL
VDD –
(a) SINGLE SUPPLY
(b) SPLIT SUPPLY
Figure 36. Gain-of-100 Inverting Amplifier
22
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PARAMETER MEASUREMENT INFORMATION
input bias current
Because of the high input impedance of the TLV233x operational amplifier, attempts to measure the input bias
current can result in erroneous readings. The bias current at normal ambient temperature is typically less than
1 pA, a value that is easily exceeded by leakages on the test socket. Two suggestions are offered to avoid
erroneous measurements:
•
•
Isolate the device from other potential leakage sources. Use a grounded shield around and between the
device inputs (see Figure 37). Leakages that would otherwise flow to the inputs are shunted away.
Compensate for the leakage of the test socket by actually performing an input bias current test (using a
picoammeter) with no device in the test socket. The actual input bias current can then be calculated by
subtracting the open-socket leakage readings from the readings obtained with a device in the test
socket.
Many automatic testers as well as some bench-top operational amplifier testers use the servo-loop
technique with a resistor in series with the device input to measure the input bias current (the voltage
drop across the series resistor is measured and the bias current is calculated). This method requires
that a device be inserted into a test socket to obtain a correct reading; therefore, an open-socket reading
is not feasible using this method.
8
5
V = VIC
1
4
Figure 37. Isolation Metal Around Device Inputs (P package)
low-level output voltage
To obtain low-level supply-voltage operation, some compromise is necessary in the input stage. This
compromise results in the device low-level output voltage being dependent on both the common-mode input
voltage level as well as the differential input voltage level. When attempting to correlate low-level output
readings with those quoted in the electrical specifications, these two conditions should be observed. If
conditions other than these are to be used, please refer to the Typical Characteristics section of this data sheet.
input offset voltage temperature coefficient
Erroneous readings often result from attempts to measure temperature coefficient of input offset voltage. This
parameter is actually a calculation using input offset voltage measurements obtained at two different
temperatures. When one (or both) of the temperatures is below freezing, moisture can collect on both the device
and the test socket. This moisture results in leakage and contact resistance which can cause erroneous input
offset voltage readings. The isolation techniques previously mentioned have no effect on the leakage since the
moisture also covers the isolation metal itself, thereby rendering it useless. These measurements should be
performed at temperatures above freezing to minimize error.
full-power response
Full-power response, the frequency above which the operational amplifier slew rate limits the output voltage
swing, is often specified two ways: full-linear response and full-peak response. The full-linear response is
POST OFFICE BOX 655303
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TLV2332, TLV2332Y, TLV2334, TLV2334Y
LinCMOS LOW-VOLTAGE MEDIUM-POWER
OPERATIONAL AMPLIFIERS
SLOS189 – FEBRUARY 1997
PARAMETER MEASUREMENT INFORMATION
generally measured by monitoring the distortion level of the output while increasing the frequency of a sinusoidal
input signal until the maximum frequency is found above which the output contains significant distortion. The
full-peak response is defined as the maximum output frequency, without regard to distortion, above which full
peak-to-peak output swing cannot be maintained.
Because there is no industry-wide accepted value for significant distortion, the full-peak response is specified
in this data sheet and is measured using the circuit of Figure 34. The initial setup involves the use of a sinusoidal
input to determine the maximum peak-to-peak output of the device (the amplitude of the sinusoidal wave is
increased until clipping occurs). The sinusoidal wave is then replaced with a square wave of the same
amplitude. The frequency is then increased until the maximum peak-to-peak output can no longer be maintained
(Figure 38). A square wave is used to allow a more accurate determination of the point at which the maximum
peak-to-peak output is reached.
(a) f = 100 Hz
(b) BOM > f > 100 Hz
(c) f = BOM
(d) f > BOM
Figure 38. Full-Power-Response Output Signal
test time
Inadequate test time is a frequent problem, especially when testing CMOS devices in a high-volume,
short-test-time environment. Internal capacitances are inherently higher in CMOS than in bipolar and BiFET
devices and require longer test times than their bipolar and BiFET counterparts. The problem becomes more
pronounced with reduced supply levels and lower temperatures.
APPLICATION INFORMATION
single-supply operation
While the TLV233x performs well using dualpower supplies (also called balanced or split
supplies), the design is optimized for singlesupply operation. This includes an input commonmode voltage range that encompasses ground as
well as an output voltage range that pulls down to
ground. The supply voltage range extends down
to 2 V, thus allowing operation with supply levels
commonly available for TTL and HCMOS.
Many single-supply applications require that a
voltage be applied to one input to establish a
reference level that is above ground. This virtual
ground can be generated using two large
resistors, but a preferred technique is to use a
virtual-ground generator such as the TLE2426
(see Figure 39).
24
POST OFFICE BOX 655303
VDD
R2
R1
VI
–
TLE2426
ǒ Ǔ
VO
+
V
O
+
V
–V
DD I
2
R2
R1
) VDD
2
Figure 39. Inverting Amplifier With Voltage
Reference
• DALLAS, TEXAS 75265
TLV2332, TLV2332Y, TLV2334, TLV2334Y
LinCMOS LOW-VOLTAGE MEDIUM-POWER
OPERATIONAL AMPLIFIERS
SLOS189 – FEBRUARY 1997
APPLICATION INFORMATION
single-supply operation (continued)
The TLE2426 supplies an accurate voltage equal to VDD/2, while consuming very little power and is suitable
for supply voltages of greater than 4 V. The TLV233x works well in conjunction with digital logic; however, when
powering both linear devices and digital logic from the same power supply, the following precautions are
recommended:
•
•
Power the linear devices from separate bypassed supply lines (see Figure 40); otherwise, the linear
device supply rails can fluctuate due to voltage drops caused by high switching currents in the digital
logic.
Use proper bypass techniques to reduce the probability of noise-induced errors. Single capacitive
decoupling is often adequate; however, RC decoupling may be necessary in high-frequency
applications.
–
+
Logic
Logic
Logic
Power
Supply
(a) COMMON-SUPPLY RAILS
–
+
Logic
Logic
Logic
Power
Supply
(b) SEPARATE-BYPASSED SUPPLY RAILS (preferred)
Figure 40. Common Versus Separate Supply Rails
input characteristics
The TLV233x is specified with a minimum and a maximum input voltage that, if exceeded at either input, could
cause the device to malfunction. Exceeding this specified range is a common problem, especially in
single-supply operation. The lower the range limit includes the negative rail, while the upper range limit is
specified at VDD – 1 V at TA = 25°C and at VDD – 1.2 V at all other temperatures.
The use of the polysilicon-gate process and the careful input circuit design gives the TLV233x very good input
offset voltage drift characteristics relative to conventional metal-gate processes. Offset voltage drift in CMOS
devices is highly influenced by threshold voltage shifts caused by polarization of the phosphorus dopant
implanted in the oxide. Placing the phosphorus dopant in a conductor (such as a polysilicon gate) alleviates the
polarization problem, thus reducing threshold voltage shifts by more than an order of magnitude. The offset
voltage drift with time has been calculated to be typically 0.1 µV/month, including the first month of operation.
Because of the extremely high input impedance and resulting low bias-current requirements, the TLV233x is
well suited for low-level signal processing; however, leakage currents on printed-circuit boards and sockets can
easily exceed bias-current requirements and cause a degradation in device performance.
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APPLICATION INFORMATION
input characteristics (continued)
It is good practice to include guard rings around inputs (similar to those of Figure 37 in the Parameter
Measurement Information section). These guards should be driven from a low-impedance source at the same
voltage level as the common-mode input (see Figure 41).
The inputs of any unused amplifiers should be tied to ground to avoid possible oscillation.
–
VI
+
VO
VI
–
+
(a) NONINVERTING AMPLIFIER
VO
(b) INVERTING AMPLIFIER
–
+
VI
VO
(c) UNITY-GAIN AMPLIFIER
Figure 41. Guard-Ring Schemes
noise performance
The noise specifications in operational amplifiers circuits are greatly dependent on the current in the first-stage
differential amplifier. The low input bias-current requirements of the TLV233x results in a very low noise current,
which is insignificant in most applications. This feature makes the device especially favorable over bipolar
devices when using values of circuit impedance greater than 50 kΩ, since bipolar devices exhibit greater noise
currents.
feedback
Operational amplifiers circuits nearly always
employ feedback, and since feedback is the first
prerequisite for oscillation, caution is appropriate.
Most oscillation problems result from driving
capacitive loads and ignoring stray input
capacitance. A small-value capacitor connected
in parallel with the feedback resistor is an effective
remedy (see Figure 42). The value of this
capacitor is optimized empirically.
electrostatic-discharge protection
–
+
Figure 42. Compensation for Input Capacitance
The TLV233x incorporates an internal electrostatic-discharge (ESD)-protection circuit that prevents functional
failures at voltages up to 2000 V as tested under MIL-PRF-38535. Method 3015.2. Care should be exercised,
however, when handling these devices as exposure to ESD may result in the degradation of the device
parametric performance. The protection circuit also causes the input bias currents to be temperature dependent
and have the characteristics of a reverse-biased diode.
26
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SLOS189 – FEBRUARY 1997
APPLICATION INFORMATION
latch-up
Because CMOS devices are susceptible to latch-up due to their inherent parasitic thyristors, the TLV233x inputs
and outputs are designed to withstand – 100-mA surge currents without sustaining latch-up; however,
techniques should be used to reduce the chance of latch-up whenever possible. Internal-protection diodes
should not by design be forward biased. Applied input and output voltage should not exceed the supply voltage
by more than 300 mV. Care should be exercised when using capacitive coupling on pulse generators. Supply
transients should be shunted by the use of decoupling capacitors (0.1 µF typical) located across the supply rails
as close to the device as possible.
The current path established if latch-up occurs is usually between the positive supply rail and ground and can
be triggered by surges on the supply lines and/or voltages on either the output or inputs that exceed the supply
voltage. Once latch-up occurs, the current flow is limited only by the impedance of the power supply and the
forward resistance of the parasitic thyristor and usually results in the destruction of the device. The chance of
latch-up occurring increases with increasing temperature and supply voltages.
output characteristics
The output stage of the TLV233x is designed to
sink and source relatively high amounts of current
(see Typical Characteristics). If the output is
subjected to a short-circuit condition, this highcurrent capability can cause device damage
under certain conditions. Output current capability
increases with supply voltage.
Although the TLV233x possesses excellent
high-level output voltage and current capability,
methods are available for boosting this capability
if needed. The simplest method involves the use
of a pullup resistor (RP) connected from the output
to the positive supply rail (see Figure 43). There
are two disadvantages to the use of this circuit.
First, the NMOS pulldown transistor N4 (see
equivalent schematic) must sink a comparatively
large amount of current. In this circuit, N4 behaves
like a linear resistor with an on resistance between
approximately 60 Ω and 180 Ω, depending on
how hard the operational amplifier input is driven.
With very low values of RP , a voltage offset from
0 V at the output occurs. Secondly, pullup resistor
RP acts as a drain load to N4 and the gain of the
operational amplifier is reduced at output voltage
levels where N5 is not supplying the output
current.
VDD
IP
–
VI
RP
R
+
VO
IF
R2
IL
R1
P
* VO
+ IVDD
)I )I
F
L
P
IP = Pullup Current
Required by the
Operational Amplifier
(typically 500 µA)
RL
Figure 43. Resistive Pullup to Increase VOH
2.5 V
–
VI
VO
+
CL
TA = 25°C
f = 1 kHz
VI(PP) = 1 V
– 2.5 V
Figure 44. Test Circuit for Output Characteristics
All operating characteristics of the TLV233x are measured using a 20-pF load. The device drives higher
capacitive loads; however, as output load capacitance increases, the resulting response pole occurs at lower
frequencies thereby causing ringing, peaking, or even oscillation (see Figure 44 and Figure 45). In many cases,
adding some compensation in the form of a series resistor in the feedback loop alleviates the problem.
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TLV2332, TLV2332Y, TLV2334, TLV2334Y
LinCMOS LOW-VOLTAGE MEDIUM-POWER
OPERATIONAL AMPLIFIERS
SLOS189 – FEBRUARY 1997
APPLICATION INFORMATION
output characteristics (continued)
(a) CL = 20 pF, RL = NO LOAD
(b) CL = 170 pF, RL = NO LOAD
Figure 45. Effect of Capacitive Loads
28
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(c) CL = 190 pF, RL = NO LOAD
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TLV2332ID
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
2332I
Samples
TLV2332IDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
2332I
Samples
TLV2332IP
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 85
TLV2332IP
Samples
TLV2332IPWR
ACTIVE
TSSOP
PW
8
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TY2332
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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