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TLV2371-Q1, TLV2372-Q1, TLV2374-Q1
SGLS244B – MAY 2004 – REVISED DECEMBER 2016
TLV237x-Q1 550-µA/Channel, 3-MHz Rail-to-Rail Input and Output Operational Amplifiers
1 Features
3 Description
•
•
The TLV237x-Q1 devices are single-supply
operational amplifiers providing rail-to-rail input and
output capability. The TLV237x-Q1 takes the
minimum operating supply voltage down to 2.7 V and
up to 16 V over the extended automotive temperature
range. Therefore, the wide voltage range can support
both start-stop functionality and a connection directly
to the typical 12-V battery. The rail-to-rail capabilities
allow the device to maximize the output signal and
avoid clipping.
1
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: –40°C to 125°C
Ambient Operating Temperature Range
– Device HBM ESD Classification Level 2
– Device CDM ESD Classification Level C4B
Rail-to-Rail Input and Output
Wide Bandwidth: 3 MHz
High Slew Rate: 2.4 V/µs
Supply Voltage Range: 2.7 V to 16 V
Supply Current: 550 µA/Channel
Input Noise Voltage: 39 nV/√Hz
Input Bias Current: 1 pA
Ultra-Small Packaging:
– 5-Pin SOT-23 (TLV2371-Q1)
Additionally, the TLV237x-Q1 family supports a high
common-mode rail to the supply voltage. This feature
sets no gain limitations and can support the input at
any level without the concern for any phase reversal.
2 Applications
•
•
•
•
•
•
The CMOS inputs enable high-impedance suitable for
engine control units (ECU), body control modules
(BCM), battery management systems (BMS), and
HEV/EV inverters. This also allows the user to draw a
lower offset voltage and maintain low power
consumption to help meet overall system needs for
quiescent current such as in infotainment or cluster,
HEV/EV, and powertrain.
Engine Control Units (ECU)
Body Control Modules (BCM)
Battery Management Systems
HEV/EV Inverters
Lane Departure Warning
White Goods
Device Information(1)
PART NUMBER
TLV2371-Q1
TLV2372-Q1
TLV2374-Q1
PACKAGE
BODY SIZE (NOM)
SOT-23 (5)
2.90 mm × 1.60 mm
SOIC (8)
4.90 mm × 3.91 mm
SOIC (8)
4.90 mm × 3.91 mm
SOIC (14)
8.65 mm × 3.91 mm
TSSOP (14)
5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Output Voltage vs Differential Input
in High Current Sensing
12
11
Output Voltage in Volts
10
9
8
7
6
5
4
3
2
VOUT in Volts
VOUT Ideal
1
0
0
100
200
300
400
500
Voltage Across The Sense Resistor in mV
600
D001
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLV2371-Q1, TLV2372-Q1, TLV2374-Q1
SGLS244B – MAY 2004 – REVISED DECEMBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
5
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
5
5
5
6
6
6
6
9
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information: TLV2371-Q1 ...........................
Thermal Information: TLV2372-Q1 ...........................
Thermal Information: TLV2374-Q1 ...........................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 15
8.1 Overview ................................................................. 15
8.2 Functional Block Diagram ....................................... 15
8.3 Feature Description................................................. 15
8.4 Device Functional Modes........................................ 17
9
Application and Implementation ........................ 18
9.1 Application Information............................................ 18
9.2 Typical Applications ................................................ 18
10 Power Supply Recommendations ..................... 21
11 Layout................................................................... 22
11.1 Layout Guidelines ................................................. 22
11.2 Layout Examples................................................... 23
11.3 Power Dissipation Considerations ........................ 23
12 Device and Documentation Support ................. 24
12.1
12.2
12.3
12.4
12.5
12.6
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
24
24
24
24
24
24
13 Mechanical, Packaging, and Orderable
Information ........................................................... 24
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (June 2008) to Revision B
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
•
Deleted 8-Pin MSOP (TLV2372) because the TLV2372-Q1 is not available in MSOP; also removed all references
throughout the data sheet....................................................................................................................................................... 1
•
Changed list items in Applications ......................................................................................................................................... 1
•
Removed Family Package and Available Options tables, see POA at the end of the data sheet ........................................ 1
•
Renamed Selection of Signal Amplifier Products table toDevice Comparison Table ............................................................ 3
•
Changed SHUTDOWN for the TLV237x in the Device Comparison Table From: Yes To: —............................................... 3
•
Changed IIB (pA) for the TLV246x in the Device Comparison Table From: 1300 To: 1.3...................................................... 3
•
Changed SHUTDOWN for the TLV237x in the Device Comparison Table From: Yes To: —............................................... 3
•
Changed GND DESCRIPTION in Pin Functions: TLV2371-Q1 From: Ground connection To: Negative (lowest)
power supply........................................................................................................................................................................... 3
•
Changed GND DESCRIPTION in Pin Functions: TLV2372-Q1 From: Ground connection To: Negative (lowest)
power supply........................................................................................................................................................................... 4
•
Removed Typical Pin 1 Indicators image .............................................................................................................................. 4
•
Changed GND DESCRIPTION in Pin Functions: TLV2374-Q1 From: Ground connection To: Negative (lowest)
power supply........................................................................................................................................................................... 4
•
Deleted Lead temperature (260°C maximum)........................................................................................................................ 5
•
Added additional thermal values to all Thermal Information tables........................................................................................ 6
•
Changed RθJA values in Thermal Information: TLV2371-Q1 From: 325.1 To: 228.5 (DBV) and From: 176 To: 138.4 (D) ... 6
•
Changed RθJA value in Thermal Information: TLV2372-Q1 From: 176 To: 138.4 (D) ............................................................ 6
•
Deleted entire DGK (MSOP) column from Thermal Information: TLV2372-Q1 ..................................................................... 6
•
Changed RθJA values in Thermal Information: TLV2374-Q1 From: 122.3 To: 67 (D) and From: 173.6 To: 121 (PW) .......... 6
•
Deleted Maximum Power Dissipation vs Free-Air Temperature graph ................................................................................ 23
2
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Product Folder Links: TLV2371-Q1 TLV2372-Q1 TLV2374-Q1
TLV2371-Q1, TLV2372-Q1, TLV2374-Q1
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SGLS244B – MAY 2004 – REVISED DECEMBER 2016
5 Device Comparison Table
Typical values measured at 5 V and 25°C
DEVICE
VDD (V)
VIO (µV)
Iq/Ch (µA)
IIB (pA)
GBW
(MHz)
SR
(V/µs)
SHUTDOWN
RAIL-TORAIL
SINGLES,
DUALS,
QUADS
TLV237x-Q1
2.7 to 16
500
550
1
3
2.4
—
I/O
S, D, Q
TLC227x-Q1
4 to 16
300
1100
1
2.2
3.6
—
O
D, Q
TLV27x-Q1
2.7 to 16
500
550
1
3
2.4
—
O
S, D, Q
TLV246x-Q1
2.7 to 6
150
550
1.3
6.4
1.6
Yes
I/O
S, D, Q
TLV247x-Q1
2.7 to 6
250
600
2
2.8
1.5
—
I/O
S, D, Q
TLV244x-Q1
2.7 to 10
300
725
1
1.8
1.4
—
O
D, Q
6 Pin Configuration and Functions
TLV2371-Q1 DBV Package
5-Pin SOT-23
Top View
OUT
1
GND
2
IN+
3
TLV2371-Q1 D Package
8-Pin SOIC
Top View
VDD
5
4
NC
IN −
IN +
GND
IN −
1
8
2
7
3
6
4
5
NC
VDD
OUT
NC
Pin Functions: TLV2371-Q1
PIN
NAME
I/O
DESCRIPTION
SOT-23
SOIC
GND
2
4
—
IN–
4
2
I
Negative (inverting) input
Positive (noninverting) input
Negative (lowest) power supply
IN+
3
3
I
NC
—
1, 5, 8
—
No internal connection (can be left floating)
OUT
1
6
O
Output
VDD
5
7
—
Positive power supply
Copyright © 2004–2016, Texas Instruments Incorporated
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3
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SGLS244B – MAY 2004 – REVISED DECEMBER 2016
www.ti.com
TLV2372-Q1 D Package
8-Pin SOIC
Top View
1OUT
1IN −
1IN +
GND
1
8
2
7
3
6
4
5
VDD
2OUT
2IN −
2IN+
Pin Functions: TLV2372-Q1
PIN
NAME
I/O
NO.
DESCRIPTION
1IN–
2
I
Inverting input, channel 1
1IN+
3
I
Noninverting input, channel 1
1OUT
1
O
Output, channel 1
2IN–
6
I
Inverting input, channel 2
2IN+
5
I
Noninverting input, channel 2
2OUT
7
O
Output, channel 2
GND
4
—
Negative (lowest) power supply
VDD
8
—
Positive power supply
TLV2374-Q1 D and PW Packages
14-Pin SOIC or TSSOP
Top View
1OUT
1IN −
1IN+
VDD
2IN+
2IN −
2OUT
1
14
2
13
3
12
4
11
5
10
6
9
7
8
4OUT
4IN −
4IN+
GND
3IN+
3IN −
3OUT
Pin Functions: TLV2374-Q1
PIN
NAME
NO.
I/O
DESCRIPTION
1IN–
2
I
Inverting input, channel 1
1IN+
3
I
Noninverting input, channel 1
1OUT
1
O
Output, channel 1
2IN–
6
I
Inverting input, channel 2
2IN+
5
I
Noninverting input, channel 2
2OUT
7
O
Output, channel 2
3IN–
9
I
Inverting input, channel 3
3IN+
10
I
Noninverting input, channel 3
3OUT
8
O
Output, channel 3
4IN–
13
I
Inverting input, channel 4
4IN+
12
I
Noninverting input, channel 4
4OUT
14
O
Output, channel 4
GND
11
—
Negative (lowest) power supply
VDD
4
—
Positive power supply
4
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TLV2371-Q1, TLV2372-Q1, TLV2374-Q1
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SGLS244B – MAY 2004 – REVISED DECEMBER 2016
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
Supply voltage, VDD
Differential input voltage, VID
MAX
UNIT
16.5
V
±VDD
Input voltage, VI
–0.2
VDD + 0.2
V
Input current, II
±10
mA
Output current, IO
±100
mA
Maximum junction temperature, TJ
150
°C
150
°C
Storage temperature, Tstg
(1)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
UNIT
TLV2371-Q1 in DBV package
Human-body model (HBM), per AEC Q100-002 (1)
V(ESD)
Electrostatic discharge
Charged-device model (CDM), per AEC Q100-011
All pins
±2000
All pins
±500
Corner pins (1, 3, 4, and 5)
±750
All pins
±2000
All pins
±500
Corner pins (1, 4, 5, and 8)
±750
All pins
±2000
All pins
±500
Corner pins (1, 4, 5, and 8)
±750
All pins
±2000
All pins
±500
Corner pins (1, 7, 8, and 14)
±750
V
TLV2371-Q1 in D package
Human-body model (HBM), per AEC Q100-002 (1)
V(ESD)
Electrostatic discharge
Charged-device model (CDM), per AEC Q100-011
V
TLV2372-Q1 in D package
Human-body model (HBM), per AEC Q100-002 (1)
V(ESD)
Electrostatic discharge
Charged-device model (CDM), per AEC Q100-011
V
TLV2374-Q1 in D and PW packages
Human-body model (HBM), per AEC Q100-002 (1)
V(ESD)
(1)
Electrostatic discharge
Charged-device model (CDM), per AEC Q100-011
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
Single supply
MIN
MAX
2.7
16
±1.35
±8
0
VDD
V
2
V
125
°C
VDD
Supply voltage
VICR
Common-mode input voltage
V(ON)
Turnon voltage level (relative to GND pin voltage)
V(OFF)
Turnoff voltage level (relative to GND pin voltage)
0.8
TA
Operating free-air temperature (Q-suffix)
–40
Split supply
Copyright © 2004–2016, Texas Instruments Incorporated
UNIT
V
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V
5
TLV2371-Q1, TLV2372-Q1, TLV2374-Q1
SGLS244B – MAY 2004 – REVISED DECEMBER 2016
www.ti.com
7.4 Thermal Information: TLV2371-Q1
TLV2371-Q1
THERMAL METRIC (1)
DBV (SOT-23)
D (SOIC)
5 PINS
8 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
228.5
138.4
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
99.1
89.5
°C/W
RθJB
Junction-to-board thermal resistance
54.6
78.6
°C/W
ψJT
Junction-to-top characterization parameter
7.7
29.9
°C/W
ψJB
Junction-to-board characterization parameter
53.8
78.1
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
—
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Thermal Information: TLV2372-Q1
TLV2372-Q1
THERMAL METRIC
(1)
D (SOIC)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
138.4
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
89.5
°C/W
RθJB
Junction-to-board thermal resistance
78.6
°C/W
ψJT
Junction-to-top characterization parameter
29.9
°C/W
ψJB
Junction-to-board characterization parameter
78.1
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.6 Thermal Information: TLV2374-Q1
TLV2374-Q1
THERMAL METRIC
(1)
D (SOIC)
PW (TSSOP)
14 PINS
14 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
67
121
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
24.1
49.4
°C/W
RθJB
Junction-to-board thermal resistance
22.5
62.8
°C/W
ψJT
Junction-to-top characterization parameter
2.2
5.9
°C/W
ψJB
Junction-to-board characterization parameter
22.1
62.2
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
—
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.7 Electrical Characteristics
at specified free-air temperature, VDD = 2.7 V, 5 V, and 15 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
2
4.5
UNIT
DC PERFORMANCE
TA = 25°C
VIO
Input offset voltage
VIC = VDD/2, VO = VDD/2, RS = 50 Ω
αVIO
Offset voltage drift
VIC = VDD/2, VO = VDD/2, RS = 50 Ω, TA = 25°C
6
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TA = –40°C to 125°C
6
2
mV
µV/°C
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SGLS244B – MAY 2004 – REVISED DECEMBER 2016
Electrical Characteristics (continued)
at specified free-air temperature, VDD = 2.7 V, 5 V, and 15 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VDD = 2.7 V
CMRR
Common-mode
rejection ratio
VDD = 5 V
VDD = 15 V
Large-signal differential VO(PP) = VDD/2,
voltage amplification
RS = 10 Ω
TYP
68
VIC = 0 to VDD,
RS = 50 Ω
TA = 25°C
50
TA = –40°C to 125°C
49
VIC = 0 to
VDD – 1.35 V,
RS = 50 Ω
TA = 25°C
53
TA = –40°C to 125°C
54
VIC = 0 to VDD,
RS = 50 Ω
TA = 25°C
55
TA = –40°C to 125°C
54
VIC = 0 to
VDD – 1.35 V,
RS = 50 Ω
TA = 25°C
58
TA = –40°C to 125°C
57
VIC = 0 to VDD,
RS = 50 Ω
TA = 25°C
64
TA = –40°C to 125°C
63
VIC = 0 to
VDD – 1.35 V,
RS = 50 Ω
TA = 25°C
67
TA = –40°C to 125°C
66
TA = 25°C
95
TA = –40°C to 125°C
76
TA = 25°C
80
TA = –40°C to 125°C
82
TA = 25°C
77
TA = –40°C to 125°C
79
VDD = 2.7 V
AVD
MIN
VDD = 5 V
VDD = 15 V
MAX
UNIT
70
72
dB
80
82
84
106
110
dB
83
INPUT
IIO
Input offset current
VDD = 15 V, VIC = VDD/2, VO = VDD/2
IIB
Input bias current
VDD = 15 V, VIC = VDD/2, VO = VDD/2
ri(d)
Differential input
resistance
TA = 25°C
CIC
Common-mode input
capacitance
f = 21 kHz, TA = 25°C
TA = 25°C
1
TA = –40°C to 125°C
60
500
TA = 25°C
1
TA = –40°C to 125°C
60
500
pA
pA
1000
GΩ
8
pF
OUTPUT
VDD = 2.7 V
VIC = VDD/2,
IOH = –1 mA,
VID = 1 V
VDD = 5 V
VDD = 15 V
VOH
High-level output
voltage
VDD = 2.7 V
VIC = VDD/2,
IOH = –5 mA,
VID = 1 V
VDD = 5 V
VDD = 15 V
Copyright © 2004–2016, Texas Instruments Incorporated
TA = 25°C
2.55
TA = –40°C to 125°C
2.48
TA = 25°C
4.9
TA = –40°C to 125°C
2.58
4.93
4.85
TA = 25°C
14.92
TA = –40°C to 125°C
14.9
TA = 25°C
1.88
TA = –40°C to 125°C
1.42
TA = 25°C
4.58
TA = –40°C to 125°C
4.44
TA = 25°C
14.7
TA = –40°C to 125°C
14.6
14.96
2
4.68
14.8
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7
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SGLS244B – MAY 2004 – REVISED DECEMBER 2016
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Electrical Characteristics (continued)
at specified free-air temperature, VDD = 2.7 V, 5 V, and 15 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VDD = 2.7 V
VIC = VDD/2,
IOH = 1 mA,
VID = 1 V
VDD = 5 V
VDD = 15 V
VOL
Low-level output
voltage
VDD = 2.7 V
VIC = VDD/2,
IOH = 5 mA,
VID = 1 V
VDD = 5 V
VDD = 15 V
MIN
TA = 25°C
TYP
MAX
0.1
0.15
TA = –40°C to 125°C
UNIT
0.22
TA = 25°C
0.05
TA = –40°C to 125°C
0.1
0.15
TA = 25°C
0.05
TA = –40°C to 125°C
0.08
0.1
TA = 25°C
0.52
TA = –40°C to 125°C
0.7
V
1.15
TA = 25°C
0.28
TA = –40°C to 125°C
0.4
0.54
TA = 25°C
0.19
TA = –40°C to 125°C
0.3
0.35
POWER SUPPLY
IDD
Supply current
(per channel)
VO = VDD/2
VDD = 2.7 V
TA = 25°C
470
560
VDD = 5 V
TA = 25°C
550
660
TA = 25°C
750
900
VDD = 15 V
PSRR
Supply voltage
rejection ratio
(ΔVDD/ΔVIO)
VDD = 2.7 V to 15 V, VIC = VDD/2,
no load
TA = –40°C to 125°C
µA
1200
TA = 25°C
70
TA = –40°C to 125°C
65
80
dB
DYNAMIC PERFORMANCE
VDD = 2.7 V, TA = 25°C
UGBW
Unity gain bandwidth
RL = 2 kΩ, CL = 10 pF
VDD = 2.7 V
SR
Slew rate at unity gain
VO(PP) = VDD/2,
RL = 10 kΩ,
CL = 50 pF
VDD = 5 V
VDD = 15 V
φm
ts
2.4
VDD = 5 V to 15 V,
TA = 25°C
TA = 25°C
3
1.4
TA = –40°C to 125°C
2
1
TA = 25°C
1.4
TA = –40°C to 125°C
1.2
TA = 25°C
1.9
TA = –40°C to 125°C
1.4
2.4
RL = 2 kΩ, CL = 100 pF, TA = 25°C
65°
Gain margin
RL = 2 kΩ, CL = 10 pF, TA = 25°C
18
VDD = 2.7 V, V(STEP)PP = 1 V, AV = –1, RL = 2 kΩ, CL = 10 pF,
0.1% at 25°C
2.9
VDD = 5 V or 15 V, V(STEP)PP = 1 V, AV = –1, RL = 2 kΩ,
CL = 47 pF, 0.1% at 25°C
V/µs
2.1
Phase margin
Settling time
MHz
dB
µs
2
NOISE/DISTORTION PERFORMANCE
VDD = 2.7 V, VO(PP) = VDD/2 V,
RL = 2 kΩ, f = 10 kHz, TA = 25°C
THD+N
Total harmonic
distortion plus noise
VDD = 5 V or 15 V, VO(PP) = VDD/2 V,
RL = 2 kΩ, f = 10 kHz, TA = 25°C
Vn
Equivalent input noise
voltage
In
Equivalent input noise
current
8
AV = 1
0.02%
AV = 10
0.05%
AV = 100
0.18%
AV = 1
0.02%
AV = 10
0.09%
AV = 100
0.5%
f = 1 kHz, TA = 25°C
39
f = 10 kHz, TA = 25°C
35
f = 1 kHz, TA = 25°C
0.6
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nV√Hz
fA√Hz
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7.8 Typical Characteristics
Table 1. Table of Graphs
FIGURE
VIO
Input offset voltage
vs Common-mode input voltage
CMRR
Common-mode rejection ratio
vs Frequency
Figure 1, Figure 2, Figure 3
Figure 4
Input bias and offset current
vs Free-air temperature
VOL
Low-level output voltage
vs Low-level output current
Figure 6, Figure 8, Figure 10
VOH
High-level output voltage
vs High-level output current
Figure 7, Figure 9, Figure 11
VO(PP)
Peak-to-peak output voltage
vs Frequency
Figure 12
IDD
Supply current
vs Supply voltage
Figure 13
PSRR
Power supply rejection ratio
vs Frequency
Figure 14
AVD
Differential voltage gain & phase
vs Frequency
Figure 15
Gain-bandwidth product
vs Free-air temperature
Figure 16
vs Supply voltage
Figure 17
vs Free-air temperature
Figure 18
Figure 19
SR
Slew rate
φm
Phase margin
vs Capacitive load
Vn
Equivalent input noise voltage
vs Frequency
Figure 5
Figure 20
Voltage-follower large-signal pulse response
Figure 21, Figure 22
Voltage-follower small-signal pulse response
Figure 23
Inverting large-signal response
Figure 24, Figure 25
Inverting small-signal response
Figure 26
Crosstalk
vs Frequency
Figure 27
1000
VDD = 2.7 V
TA = 25°C
800
V IO − Input Offset Voltage − µV
V IO − Input Offset Voltage − µV
1000
600
400
200
0
−200
VDD = 5 V
TA = 25 °C
800
600
400
200
0
−200
0
0.4
0.8
1.2
1.6
2
2.4 2.7
VICR − Common-Mode Input Voltage − V
1
2
3
4
5
VICR − Common-Mode Input Voltage − V
Figure 1. Input Offset Voltage
vs Common-Mode Input Voltage
Figure 2. Input Offset Voltage
vs Common-Mode Input Voltage
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V IO − Input Offset Voltage − µV
1000
VDD =15 V
TA = 25 °C
800
600
400
200
0
−200
2
4
6
8
10
12
14 15
120
100
VDD = 5 V, 15 V
80
60
40
20
0
10
1k
100 k
10 k
1M
Figure 3. Input Offset Voltage
vs Common-Mode Input Voltage
Figure 4. Common-Mode Rejection Ratio
vs Frequency
300
2.80
VDD = 2.7 V, 5 V and 15 V
VIC = VDD/2
250
200
150
100
50
0
VDD = 2.7 V
2.40
TA = 125 °C
2
1.60
1.20
TA = 70 °C
TA = 25 °C
0.80
TA = 0 °C
0.40
TA = 40 °C
0
−40 −25 −10 5
20 35 50 65 80 95 110 125
0
TA − Free-Air Temperature − °C
Figure 5. Input Bias and Offset Current
vs Free-Air Temperature
2 4 6 8 10 12 14 16 18 20 22 24
IOL − Low-Level Output Current − mA
Figure 6. Low-Level Output Voltage
vs Low-Level Output Current
2.80
5
VDD = 2.7 V
2.40
TA =−40°C
2
TA = 125°C
1.60
TA = 70°C
1.20
TA = 25°C
0.80
TA = 0°C
0.40
VDD = 5 V
VOL − Low-Level Output Voltage − V
V OH − High-Level Output Voltage − V
100
f − Frequency − Hz
−50
4.50
4
3.50
TA = 125 °C
TA = 70 °C
3
2.50
TA = 25 °C
2
1.50
TA = 0 °C
1
TA = −40 °C
0.50
0
0
0
1 2 3 4 5 6 7 8 9 10 11 12
IOH − High-Level Output Current − mA
Figure 7. High-Level Output Voltage
vs High-Level Output Current
10
VDD = 2.7 V
VICR − Common-Mode Input Voltage −V
VOL − Low-Level Output Voltage − V
I IB / I IO − Input Bias / Offset Current − pA
0
CMRR − Common-Mode Rejection Ratio − dB
SGLS244B – MAY 2004 – REVISED DECEMBER 2016
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0 5 10 15 20 25 30 35 40 45 50 55 60 65 70
IOL − Low-Level Output Current − mA
Figure 8. Low-Level Output Voltage
vs Low-Level Output Current
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VCC = 5 V
4.50
VOL − Low-Level Output Voltage − V
V OH − High-Level Output Voltage − V
5
TA = −40°C
4
TA = 0°C
3.50
3
2.50
TA = 25°C
2
1.50
TA = 70°C
1
TA = 125°C
0.50
15
14
VDD = 15 V
TA =125°C
12
TA =70°C
10
TA =25°C
8
TA =0°C
6
TA =−40°C
4
2
0
0
0
5
10
15
20
25
30
35
40
45
0
IOH − High-Level Output Current − mA
Figure 10. Low-Level Output Voltage
vs Low-Level Output Current
VDD = 15 V
12
TA = −40°C
10
TA = 0°C
8
6
TA = 25°C
4
TA = 70°C
TA = 125°C
2
0
0
20
40
60
80
V O(PP) − Peak-to-Peak Output Voltage − V
V OH − High-Level Output Voltage − V
Figure 9. High-Level Output Voltage
vs High-Level Output Current
15
14
20 40 60 80 100 120 140 160
IOL − Low-Level Output Current − mA
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
VDD = 15 V
AV = −10
RL = 2 kΩ
CL = 10 pF
TA = 25°C
THD = 5%
VDD = 5 V
VDD = 2.7 V
10
100 120 140 160
100
I DD − Supply Current − mA/Ch
AV = 1
VIC = VDD / 2
TA = 125°C
0.8
TA = 70°C
0.7
0.6
0.5
0.4
0.3
0.2
TA = 25°C
TA = 0°C
TA = −40°C
0.1
0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
VCC − Supply Voltage − V
Figure 13. Supply Current vs Supply Voltage
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PSRR − Power Supply Rejection Ratio − dB
1
10 k
100 k
1M
10 M
Figure 12. Peak-to-Peak Output Voltage
vs Frequency
Figure 11. High-Level Output Voltage
vs High-Level Output Current
0.9
1k
f − Frequency − Hz
IOH − High-Level Output Current − mA
120
TA = 25°C
100
VDD = 5 V, 15 V
80
VDD = 2.7 V
60
40
20
0
10
100
1k
10 k
100 k
1M
f − Frequency − Hz
Figure 14. Power Supply Rejection Ratio
vs Frequency
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180
100
135
Phase
80
4
90
45
60
40
0
Gain
−45
20
−90
VDD=5 Vdc
RL=2 kΩ
CL=10 pF
TA=25°C
0
−20
−40
10
100
−135
1k
10 k
100 k 1 M
GBWP − Gain Bandwidth Product − MHz
120
Phase − °
AVD − Differential Voltage Gain − dB
SGLS244B – MAY 2004 – REVISED DECEMBER 2016
3.5
VDD = 15 V
3
2.5
VDD = 5 V
2
VDD = 2.7 V
1.5
1
0.5
0
−40 −25 −10 5
−180
10 M
20 35 50 65 80 95 110 125
TA − Free-Air Temperature − °C
f − Frequency − Hz
Figure 16. Gain Bandwidth Product
vs Free-Air Temperature
Figure 15. Differential Voltage Gain and Phase
vs Frequency
3.5
3
SR−
3
SR − Slew Rate − V/ µs
SR − Slew Rate − V/ µs
2.5
2
1.5
SR+
1
AV = 1
RL = 10 kΩ
CL = 50 pF
TA = 25°C
0.5
4.5
6.5
8.5
10.5
12.5
2
SR+
1.5
VDD = 5 V
AV = 1
RL = 10 kΩ
CL = 50 pF
VI = 3 V
1
0.5
0
2.5
SR−
2.5
0
−40 −25 −10 5
14.5
VCC − Supply Voltage −V
Figure 17. Slew Rate vs Supply Voltage
VDD = 5 V
RL= 2 kΩ
TA = 25°C
AV = Open Loop
70
Rnull = 100
60
50
40
Rnull = 0
30
Rnull = 50
20
10
0
10
100
CL − Capacitive Load − pF
1000
Figure 19. Phase Margin vs Capacitive Load
12
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100
VDD = 2.7, 5, 15 V
TA = 25°C
90
V n − Equivalent Input Noise Voltage − nV/
Phase Margin − °
80
Figure 18. Slew Rate vs Free-Air Temperature
Hz
100
90
20 35 50 65 80 95 110 125
TA − Free-Air Temperature − °C
80
70
60
50
40
30
20
10
0
10
100
1k
10 k
f − Frequency − Hz
100 k
Figure 20. Equivalent Input Noise Voltage
vs Frequency
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0
4
3
2
1
VO
0
0
2
4
6
8
VDD = 15 V
AV = 1
RL = 2 kΩ
CL = 10 pF
VI = 9 VPP
TA = 25°C
6
3
VI
0
9
6
3
VO
0
0
10 12 14 16 18
2
t − Time − µs
0.12
0.08
0.04
VO
0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
V − Input Voltage − V
I
VI
V − Output Voltage − mV
O
V − Input Voltage − mV
I
VDD = 5 V
AV = 1
RL = 2 kΩ
CL = 10 pF
VI = 100 mVPP
TA = 25°C
0
VI
VDD = 5 V
AV = 1
RL = 2 kΩ
CL = 10 pF
VI = 3 VPP
TA = 25°C
2
1
0
3
2
1
0
VO
0
2
9
VO
6
3
0
4
6
8
10
12
14
16
t − Time − µs
Figure 25. Inverting Large-Signal Response
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V I − Input Voltage − V
VI
V O − Output Voltage − V
V I − Input Voltage − V
VDD = 15 V
AV = −1
RL = 2 kΩ
CL = 10 pF
VI = 9 Vpp
TA = 25°C
2
6
8
10
12
14
16
Figure 24. Inverting Large-Signal Response
9
0
4
t − Time − µs
12
0
10 12 14 16 18
3
Figure 23. Voltage-Follower Small-Signal
Pulse Response
3
8
4
t − Time − µs
6
6
Figure 22. Voltage-Follower Large-Signal
Pulse Response
0.12
0.04
4
t − Time − µs
Figure 21. Voltage-Follower Large-Signal
Pulse Response
0.08
12
V − Output Voltage − V
O
VI
9
VO − Output Voltage − V
1
VDD = 5 V
AV = 1
RL = 2 kΩ
CL = 10 pF
VI = 3 VPP
TA = 25°C
12
0.10
VDD = 5 V
AV = −1
RL = 2 kΩ
CL = 10 pF
VI = 100 mVpp
TA = 25°C
0.05
0
VI
0.1
VO
0.05
0
0
0.5 1 1.5 2 2.5 3 3.5 4 4.5
V O − Output Voltage − V
2
V − Output Voltage − V
O
3
V − Input Voltage − V
I
V − Input Voltage − V
I
4
t − Time − µs
Figure 26. Inverting Small-Signal Response
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0
VDD = 2.7, 5, & 15 V
VI = VDD/2
AV = 1
RL = 2 kΩ
TA = 25°C
−20
Crosstalk − dB
−40
−60
−80
Crosstalk in Shutdown
−100
−120
Crosstalk
−140
10
100
1k
10 k
f − Frequency −Hz
100 k
Figure 27. Crosstalk vs Frequency
14
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8 Detailed Description
8.1 Overview
The TLV237x-Q1 single-supply operational amplifiers provide rail-to-rail input and output capability with 3-MHz
bandwidth. Consuming only 550 µA, the TLV237x-Q1 is the perfect choice for portable and battery-operated
applications. The maximum recommended supply voltage is 16 V, which allows the devices to be operated from
a variety of rechargeable cells (±8-V supplies down to ±1.35 V). The rail-to-rail inputs with high input impedance
make the TLV237x-Q1 ideal for sensor signal-conditioning applications.
8.2 Functional Block Diagram
V+
Reference
Current
VIN+
VINVBIAS1
Class AB
Control
Circuitry
VO
VBIAS2
V(Ground)
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8.3 Feature Description
8.3.1 Rail-to-Rail Input Operation
The TLV237x-Q1 input stage consists of two differential transistor pairs, NMOS and PMOS, that operate together
to achieve rail-to-rail input operation. The transition point between these two pairs can be seen in Figure 1
through Figure 3 for a 2.7-V, 5-V, and 15-V supply. As the common-mode input voltage approaches the positive
supply rail, the input pair switches from the PMOS differential pair to the NMOS differential pair. This transition
occurs approximately 1.35 V from the positive rail and results in a change in offset voltage due to different device
characteristics between the NMOS and PMOS pairs. If the input signal to the device is large enough to swing
between both rails, this transition results in a reduction in common-mode rejection ratio (CMRR). If the input
signal does not swing between both rails, it is best to bias the signal in the region where only one input pair is
active. This is the region in Figure 1 through Figure 3 where the offset voltage varies slightly across the input
range and optimal CMRR can be achieved. This has the greatest impact when operating from a 2.7-V supply
voltage.
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Feature Description (continued)
8.3.2 Driving a Capacitive Load
When the amplifier is configured in this manner, capacitive loading directly on the output decreases the device’s
phase margin, leading to high-frequency ringing or oscillations. Therefore, for capacitive loads of greater than
10 pF, TI recommends placing a resistor in series (RNULL) with the output of the amplifier, as shown in Figure 28.
A minimum value of 20 Ω works well for most applications.
RF
RG
RNULL
−
Input
Output
+
CLOAD
VDD/2
Figure 28. Driving a Capacitive Load
8.3.3 Offset Voltage
The output offset voltage, (VOO) is the sum of the input offset volt age (VIO) and both input bias currents (IIB)
times the corresponding gains. The schematic and formula in Figure 29 can be used to calculate the output
offset voltage.
RF
RG
IIB−
+
VI
−
VO
+
RS
IIB+
æ æR
VOO = VIO ç 1 + ç F
ç
è è RG
æ æ RF
öö
÷ ÷÷ ± IIB+ RS çç 1 + ç
øø
è è RG
öö
÷ ÷÷ ± IIB- RF
øø
Figure 29. Output Offset Voltage Model
8.3.4 General Configurations
When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often required.
The simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifier (see
Figure 30).
16
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Feature Description (continued)
RG
RF
VDD/2
−
VO
+
VI
R1
C1
f-3dB =
VO æ
R
= ç1 + F
VI è RG
1
2pR1C1
öæ
1
ö
֍
÷
1
sR1C1
+
è
ø
ø
Figure 30. Single-Pole Low-Pass Filter
If even more attenuation is required, a multiple pole filter is required. The Sallen-Key filter can be used for this
task (see Figure 31). For best results, the amplifier must have a bandwidth that is 8 to 10 times the filter
frequency bandwidth. Failure to do this can result in phase shift of the amplifier.
C1
R1 = R2 = R
C1 = C2 = C
VI
R1
1 = Peaking Factor
+
_
R2
(Butterworth Q = 0.707)
C2
f-3dB
RG
VDD/2
RF
RG =
1
2 RC
RF
1ö
æ
ç2 - Q ÷
è
ø
Figure 31. 2-Pole Low-Pass Sallen-Key Filter
8.4 Device Functional Modes
The TLV2371-Q1, TLV2372-Q1, and TLV2374-Q1 have a single functional mode. These devices are operational
as long as the power supply voltage is between 2.7 V (±1.35 V) and 16 V (±8 V).
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
When designing for low power, choose system components carefully. To minimize current consumption, select
large-value resistors. Any resistors can react with stray capacitance in the circuit and the input capacitance of the
operational amplifier. These parasitic RC combinations can affect the stability of the overall system. Use of a
feedback capacitor assures stability and limits overshoot or gain peaking.
9.2 Typical Applications
9.2.1 High-Side Current Monitor
The TLV237x-Q1 is rail-to-rail input and output capability and up to 16-V supply voltage. That makes the device
suitable in body control model applications and more specific high-side current sensing. The input common mode
is at the supply voltage so there is no limitation in differential gain.
VBAT
Rs
V1
V2
Rg
0.005
220k
R1
11K
VBAT
R
Load
0.1uF
8
11K
2
1
VOUT
3
A
R2
220K
47K
4
TLV2372
GND
Figure 32. Application Circuit
9.2.1.1 Design Requirements
For this design example, use these parameters listed in Table 2 as the input parameters.
Table 2. Design Parameters
PARAMETER
VBAT
Battery voltage
RSENSE
ILOAD
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12 V
0.05 Ω
Load current
Operational amplifier
18
VALUE
0 A to 10 A
Set in differential configuration
with gain = 20
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9.2.1.2 Detailed Design Procedure
This circuit is designed for measuring the high-side current in automotive body control modules with a 12-V
battery or similar applications. The operational amplifier is set as differential with an external resistor network.
9.2.1.2.1 Differential Amplifier Equations
Equation 1 and Equation 2 are used to calculate VOUT.
VOUT
VOUT
æ R R
ö
1 æ R R1 ö
+ ÷
1+ ç
ç
÷
- 1
2 çè Rg R2 ÷ø
Rg ç Rg R2 V 1 + V 2
÷
=
´
+
V 1 - V 2 )÷
(
ç
R
R 1 + R1
2
1+ 1
ç
÷
R2
R2
ç
÷
è
ø
(1)
æ R R
ö
1 æ R R1 ö
+ ÷
1+ ç
ç
÷
- 1
2 çè Rg R2 ÷ø
Rg ç Rg R2 V 1 + V 2
÷
=
´
+
´ RS ´ I load ÷
R1
R ç 1 + R1
2
+
1
ç
÷
R2
R2
ç
÷
è
ø
(2)
In an ideal case, R1 = R, R2 = Rg, and VOUT can then be calculated using Equation 3.
VOUT =
Rg
R
´ RS ´ I load
(3)
However, as the resistors have tolerances, they cannot be perfectly matched.
R1 = R ± ΔR1
R2 = R ± ΔR2
R = R ± ΔR
Rg = Rg ± ΔR
Tol =
(4)
(5)
(6)
(7)
DR
R
(8)
By developing the equations and neglecting the second order, the worst case is when the tolerances add up.
This is shown by Equation 9.
V
r 4 Tol
Rg
x Vbat
R+ Rg
( 1 r 2 Tol ( 1
2R
Rg
))
u Rs uI load
R+ Rg R
where
•
•
Tol = 0.01 for 1%
Tol = 0.001 for 0.1%
(9)
If the resistors are perfectly matched, then Tol = 0 and Vout is calculated using Equation 10.
Vout
Rg
u Rs u I load
R
(10)
The highest error is from the common mode in Equation 11.
(4 Tol )
Rg
u Vbat
R+ Rg
(11)
Gain of 20, Rg/R = 20, and Tol = 1% in Equation 12.
Common mode error = ((4 × 0.01) / 1.05) × 12 V = 0.457 V
(12)
When the gain of 20 and Tol = 0.1%, the common-mode error = 45.7 mV.
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The resistors were chosen from 1% batches.
• R1 and R are 11 kΩ
• R2 and Rg are 220 kΩ
Ideal Gain = 220 / 11 = 20
The measured value of the resistors:
• R1 = 10.97 kΩ
• R = 10.96 kΩ
• R2 = 220.23 kΩ
• Rg = 220.15 kΩ
9.2.1.3 Application Curve
12
11
Output Voltage in Volts
10
9
8
7
6
5
4
3
2
VOUT in Volts
VOUT Ideal
1
0
0
100
200
300
400
500
Voltage Across The Sense Resistor in mV
600
D001
Figure 33. Output Voltage vs Differential Input in High Current Sensing
9.2.2 Inverting Amplifier
A typical application for an operational amplifier is an inverting amplifier, as shown in Figure 34. An inverting
amplifier takes a positive voltage on the input and outputs a signal inverted to the input, making a negative
voltage of the same magnitude. In the same manner, the amplifier also makes negative input voltages positive on
the output. In addition, amplification can be added by selecting the input resistor RI and the feedback resistor RF.
RF
VSUP+
RI
VOUT
+
VIN
VSUP±
Copyright © 2016, Texas Instruments Incorporated
Figure 34. Amplifier Schematic
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SGLS244B – MAY 2004 – REVISED DECEMBER 2016
9.2.3 Design Requirements
The supply voltage must be chosen to be larger than the input voltage range and the desired output range. The
limits of the input common-mode range (VCM) and the output voltage swing to the rails (VO) must also be
considered. For instance, this application scales a signal of ±0.5 V (1 V) to ±1.8 V (3.6 V). Setting the supply at
±2.5 V is sufficient to accommodate this application.
9.2.4 Detailed Design Procedure
Determine the gain required by the inverting amplifier using Equation 13 and Equation 14.
VOUT
AV
VIN
AV
1.8
0.5
3.6
(13)
(14)
When the desired gain is determined, choose a value for RI or RF. Choosing a value in the kΩ range is desirable
for general-purpose applications because the amplifier circuit uses currents in the milliamp range. This milliamp
current range ensures the device does not draw too much current. The trade-off is that large resistors (hundreds
of kΩ) draw the smallest current but generate the highest noise. Small resistors (hundreds of Ω) generate low
noise but draw high current. This example uses 10 kΩ for RI, meaning 36 kΩ is used for RF. These values are
determined by Equation 15.
RF
AV
RI
(15)
9.2.5 Application Curve
2
1.5
Input
Output
Voltage (V)
1
0.5
0
-0.5
-1
-1.5
-2
Time
Figure 35. Inverting Amplifier Input and Output
10 Power Supply Recommendations
The TLV237x-Q1 family is specified for operation from 2.7 V to 15 V (±1.35 V to ±7.5 V); many specifications
apply from –40°C to 125°C. The Typical Characteristics presents parameters that can exhibit significant variance
with regard to operating voltage or temperature.
CAUTION
Supply voltages larger than 16 V can permanently damage the device (see the
Absolute Maximum Ratings).
Place 0.1-µF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or highimpedance power supplies. For more detailed information on bypass capacitor placement (see Layout).
Copyright © 2004–2016, Texas Instruments Incorporated
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SGLS244B – MAY 2004 – REVISED DECEMBER 2016
www.ti.com
11 Layout
11.1 Layout Guidelines
To achieve the levels of high performance of the TLV237x-Q1, follow proper printed-circuit board design
techniques. The following is a general set of guidelines:
• Ground planes: TI highly recommends a ground plane be used on the board to provide all components with a
low inductive ground connection. However, in the areas of the amplifier inputs and output, the ground plane
can be removed to minimize the stray capacitance.
• Proper power supply decoupling: Use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic capacitor
on each supply terminal. It may be possible to share the tantalum capacitor among several amplifiers
depending on the application, but a 0.1-µF ceramic capacitor must always be used on the supply terminal of
every amplifier. In addition, the 0.1-µF capacitor must be placed as close as possible to the supply terminal.
As this distance increases, the inductance in the connecting trace makes the capacitor less effective. The
designer must strive for distances of less than 0.1 inches between the device power terminals and the
ceramic capacitors.
• Sockets: Sockets can be used but are not recommended. The additional lead inductance in the socket pins
often leads to stability problems. Surface-mount packages soldered directly to the printed-circuit board is the
best implementation.
• Short trace runs or compact part placements: Optimum high performance is achieved when stray series
inductance has been minimized. To realize this, the circuit layout must be made as compact as possible,
thereby minimizing the length of all trace runs. Pay particular attention to the inverting input of the amplifier.
Its length must be kept as short as possible. This helps to minimize stray capacitance at the input of the
amplifier.
• Surface-mount passive components: Using surface-mount passive components is recommended for high
performance amplifier circuits for several reasons. First, because of the extremely low lead inductance of
surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small
size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray
inductance and capacitance. If leaded components are used, TI recommends that the lead lengths be kept as
short as possible.
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www.ti.com
SGLS244B – MAY 2004 – REVISED DECEMBER 2016
11.2 Layout Examples
+
VIN
VOUT
±
RG
RF
Copyright © 2016, Texas Instruments Incorporated
Figure 36. Schematic Representation
Place components
close to device and
to eachother to
reduce parasitic
errors
Run the input traces
as far away from
the supply lines
as possible
VS+
RF
N/C
N/C
GND
–IN
V+
VIN
+IN
OUTPUT
V–
N/C
RG
GND
GND
Use low-ESR, ceramic
bypass capacitor
VS–
Use low-ESR,
ceramic bypass
capacitor
VOUT
Copyright © 2016, Texas Instruments Incorporated
Figure 37. Operational Amplifier Board Layout for Noninverting Configuration
11.3 Power Dissipation Considerations
For a given RθJA, the maximum power dissipation is calculated by Equation 16.
æT
- TA ö
PD = ç MAX
÷
q
JA
è
ø
where
•
•
•
•
PD = Maximum power dissipation of TLV237x-Q1 IC (watts)
TMAX = Absolute maximum junction temperature (150°C)
TA = Free-ambient air temperature (°C)
RθJA = RθJC + RθCA
– RθJC = Thermal coefficient from junction-to-case
– RθCA = Thermal coefficient from case-to-ambient air (°C/W)
Copyright © 2004–2016, Texas Instruments Incorporated
(16)
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SGLS244B – MAY 2004 – REVISED DECEMBER 2016
www.ti.com
12 Device and Documentation Support
12.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 3. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TLV2371-Q1
Click here
Click here
Click here
Click here
Click here
TLV2372-Q1
Click here
Click here
Click here
Click here
Click here
TLV2374-Q1
Click here
Click here
Click here
Click here
Click here
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
24
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TLV2371QDBVRQ1
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
371Q
TLV2371QDRG4Q1
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
2371Q1
TLV2372QDRG4Q1
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
2372Q1
TLV2372QDRQ1
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
2372Q1
TLV2374QDRG4Q1
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
2374Q1
TLV2374QDRQ1
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
2374Q1
TLV2374QPWRG4Q1
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
2374Q1
TLV2374QPWRQ1
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
2374Q1
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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