0
登录后你可以
  • 下载海量资料
  • 学习在线课程
  • 观看技术视频
  • 写文章/发帖/加入社区
会员中心
创作中心
发布
  • 发文章

  • 发资料

  • 发帖

  • 提问

  • 发视频

创作活动
TLV2463AQPWRG4Q1

TLV2463AQPWRG4Q1

  • 厂商:

    BURR-BROWN(德州仪器)

  • 封装:

    TSSOP14

  • 描述:

    TLV2463A-Q1 DUAL 6.4MHZ AUTOMOTI

  • 数据手册
  • 价格&库存
TLV2463AQPWRG4Q1 数据手册
Product Folder Order Now Support & Community Tools & Software Technical Documents TLV2460-Q1, TLV2460A-Q1, TLV2461-Q1, TLV2461A-Q1 TLV2462-Q1, TLV2462A-Q1, TLV2463-Q1, TLV2463A-Q1, TLV2464A-Q1 SGLS008G – MARCH 2003 – REVISED FEBRUARY 2018 TLV246xx-Q1 Low-Power Rail-to-Rail Input/Output Operational Amplifiers With Shutdown 1 1 Features • • • • • • • • • • Qualified for Automotive Applications AEC-Q100 Qualified With the Following Results: – Device Temperature Grade 1: –40°C to +125°C Ambient Operating Temperature Range – Device HBM ESD Classification Level 2 – Device CDM ESD Classification Level C6 ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model C = 200 pF, R = 0) Rail-to-Rail Output Swing Gain Bandwidth Product: 6.4 MHz Output Drive Capability: ±80-mA Supply Current: 500 μA/Channel Input Noise Voltage: 11 nV/√Hz Slew Rate: 1.6 V/μs Micropower Shutdown Mode (TLV2460-Q1 and TLV2463-Q1): 0.3 μA/Channel Universal Operational Amplifier EVM Available in Single, Dual, and Quad Versions The operational amplifier has 6.4-MHz bandwidth and a 1.6-V/μs slew rate with only 500-μA supply current, which provides good ac performance with low-power consumption. Devices are available with an optional shutdown terminal, which places the amplifier in an ultra-low supply-current mode (IDD = 0.3 μA per channel). While in shutdown, the operational amplifier output is placed in a high-impedance state. DC applications are designed with an input noise voltage of 11 nV/√Hz and input offset voltage of 100 μV. Device Information(1) PART NUMBER TLV246x-Q1, TLV246xA-Q1 TLV2462-Q1, TLV2462A-Q1 TLV246x-Q1, TLV246xA-Q1 TSSOP (8) 4.40 mm × 3.00 mm SOIC (8) 3.91 mm × 4.90 mm TSSOP (8) 4.40 mm × 3.00 mm VSSOP (8) 3.00 mm × 3.00 mm TSSOP (14) 4.40 mm × 5.00 mm Typical Application C1 33 pF C2 R2 47 kŸ 680 pF C3 R3 330 pF V IN VCC 4.7 k R1 62 NŸ U1B 6 7 VCC/2 5 OUT 4 Clusters Telematics HEV/EV and Powertrains DC-to-DC Inverters Power Steering Lighting Modules Battery Management Systems BODY SIZE (NOM) (1) For all available packages, see the orderable addendum at the end of the data sheet. (2) For all available device options, see the Mechanical, Packaging, and Orderable Information. 2 Applications • • • • • • • PACKAGE 8 • • 3 Description GND The devices in the TLV246x-Q1 family of low-power rail-to-rail input/output operational amplifiers are designed for battery management systems in HEV/EV and Powertrain, and lighting and roof module systems in body and lighting applications. The input common-mode voltage range extends beyond the supply rails for maximum dynamic range in lowvoltage systems. The amplifier output has rail-to-rail performance with high-output-drive capability, solving one of the limitations of older rail-to-rail input/output operational amplifiers. This rail-to-rail dynamic range and high output drive make the TLV246x-Q1 designed for buffering analog-to-digital converters. 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TLV2460-Q1, TLV2460A-Q1, TLV2461-Q1, TLV2461A-Q1 TLV2462-Q1, TLV2462A-Q1, TLV2463-Q1, TLV2463A-Q1, TLV2464A-Q1 SGLS008G – MARCH 2003 – REVISED FEBRUARY 2018 www.ti.com Table of Contents 1 2 3 4 5 6 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 6.12 6.13 7 1 1 1 2 4 6 Absolute Maximum Ratings ..................................... 6 ESD Ratings.............................................................. 6 Recommended Operating Conditions....................... 6 Thermal Information: TLV2460x-Q1 ......................... 6 Thermal Information: TLV2461x-Q1 ......................... 7 Thermal Information: TLV2462-Q1 ........................... 7 Thermal Information: TLV2462A-Q1......................... 7 Thermal Information: TLV2463x-Q1 ......................... 7 Electrical Characteristics: VDD = 3 V......................... 8 Electrical Characteristics: VDD = 5 V....................... 9 Operating Characteristics: VDD = 3 V ................... 11 Operating Characteristics: VDD = 5 V ................... 12 Typical Characteristics .......................................... 13 Parameter Measurement Information ................ 22 8 Detailed Description ............................................ 22 8.1 8.2 8.3 8.4 9 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ 22 22 22 25 Application and Implementation ........................ 26 9.1 Application Information............................................ 26 9.2 Typical Application ................................................. 28 10 Power Supply Recommendations ..................... 30 11 Layout................................................................... 31 11.1 Layout Guidelines ................................................. 31 11.2 Layout Example .................................................... 31 12 Device and Documentation Support ................. 32 12.1 12.2 12.3 12.4 12.5 12.6 Documentation Support ....................................... Related Links ........................................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 32 32 32 32 32 32 13 Mechanical, Packaging, and Orderable Information ........................................................... 33 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision F (December 2015) to Revision G Page • Updated data sheet text to latest data sheet and translation standards ................................................................................ 1 • Deleted "Input Offset Voltage: 100 µV" bullet from Features section ................................................................................... 1 • Deleted "Universal Operational Amplifier EVM" bullet from Features section ...................................................................... 1 • Deleted TLV2464 device from document ............................................................................................................................... 1 • Deleted Device Comparison table ......................................................................................................................................... 4 • Reformatted Thermal Information tables and table notes ..................................................................................................... 6 • Changed IIO and IIB unit from pA to nA in Electrical Characteristics: VDD = 3 V table ............................................................ 8 • Changed IIO and IIB unit from pA to nA in Electrical Characteristics: VDD = 5 V table ............................................................ 9 • Reformatted document references in Related Documentation section ............................................................................... 32 Changes from Revision E (October 2012) to Revision F Page • Added AEC-Q100 bulleted items ........................................................................................................................................... 1 • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ................................................................................................. 1 • Deleted D package from TLV2460-Q1, TLV2461-Q1, TLV2463-Q1, and TLV2464A-Q1 and added TLV246xA-Q1 device number to pin drawings............................................................................................................................................... 4 • Deleted table note 3 reference to JESD 51-5 from Absolute Maximum Ratings table .......................................................... 6 2 Submit Documentation Feedback Copyright © 2003–2018, Texas Instruments Incorporated Product Folder Links: TLV2460-Q1 TLV2460A-Q1 TLV2461-Q1 TLV2461A-Q1 TLV2462-Q1 TLV2462A-Q1 TLV2463Q1 TLV2463A-Q1 TLV2464A-Q1 TLV2460-Q1, TLV2460A-Q1, TLV2461-Q1, TLV2461A-Q1 TLV2462-Q1, TLV2462A-Q1, TLV2463-Q1, TLV2463A-Q1, TLV2464A-Q1 www.ti.com SGLS008G – MARCH 2003 – REVISED FEBRUARY 2018 Changes from Revision D (September 2010) to Revision E Page • Changed device names from TLV246xx to TLV246xx-Q1 throughout document.................................................................. 1 • Changed IDD unit from µA to mA. .......................................................................................................................................... 8 • Changed IDD unit from µA to mA ............................................................................................................................................ 9 Copyright © 2003–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLV2460-Q1 TLV2460A-Q1 TLV2461-Q1 TLV2461A-Q1 TLV2462-Q1 TLV2462A-Q1 TLV2463Q1 TLV2463A-Q1 TLV2464A-Q1 3 TLV2460-Q1, TLV2460A-Q1, TLV2461-Q1, TLV2461A-Q1 TLV2462-Q1, TLV2462A-Q1, TLV2463-Q1, TLV2463A-Q1, TLV2464A-Q1 SGLS008G – MARCH 2003 – REVISED FEBRUARY 2018 www.ti.com 5 Pin Configuration and Functions TLV2460-Q1, TLV2460A-Q1 PW Package 8-Pin TSSOP Top View NC IN IN + GND 1 8 2 7 3 6 4 5 TLV2461-Q1, TLV2461A-Q1 PW Package 8-Pin TSSOP Top View SHDN VDD+ OUT NC NC IN IN + GND NC- no internal connection 1 8 2 7 3 6 4 5 NC VDD+ OUT NC NC- no internal connection TLV2462-Q1, TLV2462A-Q1 D, DGK, or PW Package 8-Pin SOIC, TSSOP, or VSSOP Top View 1OUT 1IN 1IN + GND 1 8 2 7 3 6 4 5 VDD+ 2OUT 2IN 2IN+ NC – No internal connection Pin Functions PIN TLV2460-Q1, TLV2460A-Q1 TLV2461-Q1, TLV2461A-Q1 TLV2462-Q1, TLV2462A-Q1 I/O 1IN — — 2 I Inverting input, channel 1 1IN+ — — 3 I Noninverting input, channel 1 1OUT — — 1 O Output, channel 1 2IN — — 6 I Inverting input, channel 2 2IN+ — — 5 I Noninverting input, channel 2 2OUT — — 7 O Output, channel 2 IN 2 2 — I Inverting input IN+ 3 3 — I Noninverting input GND 4 4 4 — Negative (lowest) supply NAME NC DESCRIPTION 1, 5 1, 5, 8 — — No internal connection OUT 6 6 — O Output SHDN 8 — — I Shutdown VDD+ 7 7 8 — 4 Submit Documentation Feedback Positive (highest) supply Copyright © 2003–2018, Texas Instruments Incorporated Product Folder Links: TLV2460-Q1 TLV2460A-Q1 TLV2461-Q1 TLV2461A-Q1 TLV2462-Q1 TLV2462A-Q1 TLV2463Q1 TLV2463A-Q1 TLV2464A-Q1 TLV2460-Q1, TLV2460A-Q1, TLV2461-Q1, TLV2461A-Q1 TLV2462-Q1, TLV2462A-Q1, TLV2463-Q1, TLV2463A-Q1, TLV2464A-Q1 www.ti.com SGLS008G – MARCH 2003 – REVISED FEBRUARY 2018 TLV2463-Q1, TLV2463A-Q1 PW Package 14-Pin TSSOP Top View 1OUT 1IN 1IN+ GND NC 1SHDN NC 1 14 2 13 3 12 4 11 5 10 6 9 7 8 TLV2463-Q1, TLV2463A-Q1 PW Package 14-Pin TSSOP Top View VDD+ 2OUT 2IN 2IN+ NC 2SHDN NC 1OUT 1IN 1IN+ VDD+ 2IN+ 2IN 2OUT 1 14 2 13 3 12 4 11 5 10 6 9 7 8 4OUT 4IN 4IN+ GND 3IN+ 3IN 3OUT NC – No internal connection Pin Functions PIN NAME I/O DESCRIPTION TLV2463-Q1, TLV2463A-Q1 TLV2464A-Q1 1IN 2 2 I Inverting input, channel 1 1IN+ 3 3 I Noninverting input, channel 1 1OUT 1 1 O Output, channel 1 1SHDN 6 — I Shutdown for channel 1 2IN 12 6 I Inverting input, channel 2 2IN+ 11 5 I Noninverting input, channel 2 2OUT 13 7 O Output, channel 2 2SHDN 9 — I Shutdown for channel 2 3N — 9 I Inverting input, channel 3 3IN+ — 10 I Noninverting input, channel 3 3OUT — 8 O Output, channel 3 4IN — 13 I Inverting input, channel 4 4IN+ — 12 I Noninverting input, channel 4 4OUT — 14 O Output, channel 4 IN — — I Inverting input IN+ — — I Noninverting input GND 4 11 — Negative (lowest) supply 5, 7, 8, 10 — — No internal connection OUT — — O Output SHDN — — I Shutdown VDD+ 14 4 — NC Copyright © 2003–2018, Texas Instruments Incorporated Positive (highest) supply Submit Documentation Feedback Product Folder Links: TLV2460-Q1 TLV2460A-Q1 TLV2461-Q1 TLV2461A-Q1 TLV2462-Q1 TLV2462A-Q1 TLV2463Q1 TLV2463A-Q1 TLV2464A-Q1 5 TLV2460-Q1, TLV2460A-Q1, TLV2461-Q1, TLV2461A-Q1 TLV2462-Q1, TLV2462A-Q1, TLV2463-Q1, TLV2463A-Q1, TLV2464A-Q1 SGLS008G – MARCH 2003 – REVISED FEBRUARY 2018 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT 6 V Supply voltage (2), VDD Differential input voltage, VID –0.2 VDD + 0.2 V Input current (any input), II –200 200 mA Output current, IO –175 175 mA Total input current (into VDD+), II 175 mA Total output current (out of GND), IO 175 mA 125 °C Maximum junction temperature, TJ 150 °C Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds 260 °C 150 °C Operating free-air temperature, TA –40 Storage temperature, Tstg (1) (2) –65 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values, except differential voltages, are with respect to GND. 6.2 ESD Ratings VALUE V(ESD) (1) Electrostatic discharge Human-body model (HBM), per AEC Q100-002 (1) ±2000 Charged-device model (CDM), per AEC Q100-011 ±1000 UNIT V AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification. 6.3 Recommended Operating Conditions Single-supply VDD Supply voltage VICR Common-mode input voltage range TA Operating free-air temperature Split-supply (1) Shutdown on and off voltage level (1) (1) MIN MAX 2.7 6 ±1.35 ±3 –0.2 VDD + 0.2 V –40 125 °C VIH UNIT 2 VIL 0.7 V V Relative to voltage on the GND terminal of the device 6.4 Thermal Information: TLV2460x-Q1 TLV2460x-Q1 THERMAL METRIC (1) PW (TSSOP) UNIT 8 PINS RθJA Junction-to-ambient thermal resistance RθJC(top) Junction-to-case (top) thermal resistance RθJB Junction-to-board thermal resistance ψJT Junction-to-top characterization parameter ψJB Junction-to-board characterization parameter RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W (1) 6 185.7 °C/W 69 °C/W 114.5 °C/W 9.6 °C/W 112.7 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Documentation Feedback Copyright © 2003–2018, Texas Instruments Incorporated Product Folder Links: TLV2460-Q1 TLV2460A-Q1 TLV2461-Q1 TLV2461A-Q1 TLV2462-Q1 TLV2462A-Q1 TLV2463Q1 TLV2463A-Q1 TLV2464A-Q1 TLV2460-Q1, TLV2460A-Q1, TLV2461-Q1, TLV2461A-Q1 TLV2462-Q1, TLV2462A-Q1, TLV2463-Q1, TLV2463A-Q1, TLV2464A-Q1 www.ti.com SGLS008G – MARCH 2003 – REVISED FEBRUARY 2018 6.5 Thermal Information: TLV2461x-Q1 TLV2461x-Q1 THERMAL METRIC (1) PW (TSSOP) UNIT 8 PINS RθJA Junction-to-ambient thermal resistance RθJC(top) Junction-to-case (top) thermal resistance RθJB Junction-to-board thermal resistance ψJT Junction-to-top characterization parameter ψJB RθJC(bot) (1) 185.7 °C/W 69 °C/W 114.5 °C/W 9.6 °C/W Junction-to-board characterization parameter 112.7 °C/W Junction-to-case (bottom) thermal resistance N/A °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 6.6 Thermal Information: TLV2462-Q1 TLV2462-Q1 THERMAL METRIC RθJA (1) Junction-to-ambient thermal resistance D (SOIC) DGK (VSSOP) PW (TSSOP) 8 PINS 8 PINS 8 PINS UNIT 120.1 179.3 183.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance 68.3 71.1 67 °C/W RθJB Junction-to-board thermal resistance 60.4 100.4 112.3 °C/W ψJT Junction-to-top characterization parameter 20.6 10.7 9 °C/W ψJB Junction-to-board characterization parameter 59.9 98.8 110.6 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 6.7 Thermal Information: TLV2462A-Q1 TLV2462A-Q1 THERMAL METRIC (1) D (SOIC) PW (TSSOP) 8 PINS 8 PINS UNIT RθJA Junction-to-ambient thermal resistance 120.1 185.7 °C/W RθJC(top) Junction-to-case (top) thermal resistance 68.3 69 °C/W RθJB Junction-to-board thermal resistance 60.4 114.5 °C/W ψJT Junction-to-top characterization parameter 20.6 9.6 °C/W ψJB Junction-to-board characterization parameter 59.9 112.7 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 6.8 Thermal Information: TLV2463x-Q1 TLV2463x-Q1 THERMAL METRIC (1) PW (TSSOP) UNIT 8 PINS RθJA Junction-to-ambient thermal resistance RθJC(top) Junction-to-case (top) thermal resistance RθJB Junction-to-board thermal resistance ψJT Junction-to-top characterization parameter ψJB RθJC(bot) (1) 185.7 °C/W 69 °C/W 114.5 °C/W 9.6 °C/W Junction-to-board characterization parameter 112.7 °C/W Junction-to-case (bottom) thermal resistance N/A °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Copyright © 2003–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLV2460-Q1 TLV2460A-Q1 TLV2461-Q1 TLV2461A-Q1 TLV2462-Q1 TLV2462A-Q1 TLV2463Q1 TLV2463A-Q1 TLV2464A-Q1 7 TLV2460-Q1, TLV2460A-Q1, TLV2461-Q1, TLV2461A-Q1 TLV2462-Q1, TLV2462A-Q1, TLV2463-Q1, TLV2463A-Q1, TLV2464A-Q1 SGLS008G – MARCH 2003 – REVISED FEBRUARY 2018 www.ti.com 6.9 Electrical Characteristics: VDD = 3 V at specified free-air temperature, VDD = 3 V, (unless otherwise noted) PARAMETER VIO Input offset voltage TEST CONDITIONS VDD = 3 V VIC = 1.5 V VO = 1.5 V RS = 50 Ω TLV246x-Q1 TLV246xA-Q1 MIN TA = 25°C VDD = 3 V VIC = 1.5 V VO = 1.5 V RS = 50 Ω TA = 25°C Input offset current Input bias current VIC = 1.5 V VO = 1.5 V RS = 50 Ω TA = 25°C IIB IO = –10 mA VOL IO Output current Measured 1 V from rail AVD Large-signal differential voltage amplification RL = 10 kΩ ri(d) Differential input resistance ci(o) Common-mode input capacitance zo CMRR 7 75 4.4 (1) nA 14 75 nA 2.9 Full range (1) 2.8 TA = 25°C V 2.7 Full range (1) 2.5 0.1 Full range (1) 0.2 0.3 Full range (1) V 0.5 TA = 25°C 50 Full range (1) 20 TA = 25°C mA 40 Full range 20 TA = 25°C ±40 TA = 25°C 90 Full range (1) 89 mA 105 dB Ω f = 10 kHz TA = 25°C 7 pF Closed-loop output impedance f = 100 kHz AV = 10 TA = 25°C 33 Ω Common-mode rejection ratio VICR = 0 V to 3 V RS = 50 Ω TA = 25°C 66 Full range (1) 60 VDD = 2.7 V to 6 V VIC = VDD / 2; no load TA = 25°C 80 VDD = 3 V to 5 V VIC = VDD / 2; no load TA = 25°C 85 Full range (1) 80 Supply-voltage rejection ratio (ΔVDD± / ΔVIO) VO = 1.5 V; no load IDD(SHD Supply current in shutdown (TLV2460-Q1, TLV2463-Q1) SHDN < 0.7 V, per channel in shutdown 8 μV/°C 109 Supply current (per channel) (1) μV TA = 25°C IDD N) 2.8 TA = 25°C VIC = 1.5 V IOL = 10 mA Sinking kSVR Full range TA = 25°C Short circuit output current 1500 UNIT 1700 Full range (1) TA = 25°C Sourcing IOS 150 2 VIC = 1.5 V IOL = 2.5 mA Low-level output voltage 2000 Full range (1) IIO High-level output voltage 100 2200 TA = 25°C VDD = 3 V Temperature coefficient of VIC = 1.5 V input offset voltage VO = 1.5 V RS = 50 Ω VOH MAX Full range (1) αVIO IO = –2.5 mA TYP Full range (1) TA = 25°C 80 85 75 Full range dB 95 0.5 Full range (1) TA = 25°C dB 0.575 0.9 mA 0.3 (1) 2.5 μA Full range is –40°C to +125°C. Submit Documentation Feedback Copyright © 2003–2018, Texas Instruments Incorporated Product Folder Links: TLV2460-Q1 TLV2460A-Q1 TLV2461-Q1 TLV2461A-Q1 TLV2462-Q1 TLV2462A-Q1 TLV2463Q1 TLV2463A-Q1 TLV2464A-Q1 TLV2460-Q1, TLV2460A-Q1, TLV2461-Q1, TLV2461A-Q1 TLV2462-Q1, TLV2462A-Q1, TLV2463-Q1, TLV2463A-Q1, TLV2464A-Q1 www.ti.com SGLS008G – MARCH 2003 – REVISED FEBRUARY 2018 6.10 Electrical Characteristics: VDD = 5 V at specified free-air temperature, VDD = 5 V, (unless otherwise noted) PARAMETER VIO Input offset voltage TEST CONDITIONS VDD = 5 V VIC = 2.5 V VO = 2.5 V RS = 50 Ω TLV246x-Q1 TLV246xA-Q1 TA = 25°C VDD = 5 V VIC = 2.5 V VO = 2.5 V RS = 50 Ω TA = 25°C Input offset current Input bias current VDD = 5 V VIC = 2.5 V VO = 2.5 V RS = 50 Ω TA = 25°C IIB 150 0.3 1.3 4.7 Full range (1) 4.4 TA = 25°C VIC = 2.5 V IOL = 10 mA TA = 25°C Low-level output voltage Sourcing Short circuit output current Sinking 4.8 (1) TA = 25°C V 0.1 Full range (1) 0.2 0.2 Full range (1) V 0.3 TA = 25°C 145 Full range (1) 60 TA = 25°C mA 100 Full range (1) 60 Measured 1 V from rail TA = 25°C Large-signal differential voltage amplification TA = 25°C 92 AVD VIC = 2.5 V RL = 10 kΩ VO = 1 V to 4 V Full range (1) 90 ri(d) Differential input resistance ci(o) Common-mode input capacitance zo CMRR (1) nA 4.8 Output current IDD 14 4.8 TA = 25°C VIC = 2.5 V IOL = 2.5 mA nA 4.9 Full range (1) Full range 7 60 TA = 25°C TLV246x-Q1, TLV246xA-Q1 μV μV/°C 60 Full range (1) TLV2462QDGKRQ1 kSVR 1500 UNIT 1700 Full range (1) IO = –10 mA IO 2000 2 IO = –2.5 mA IOS 150 Full range (1) IIO VOL MAX 2200 TA = 25°C VDD = 5 V Temperature coefficient of VIC = 2.5 V input offset voltage VO = 2.5 V RS = 50 Ω High-level output voltage TYP Full range (1) αVIO VOH MIN ±80 mA 109 dB TA = 25°C 109 Ω f = 10 kHz TA = 25°C 7 pF Closed-loop output impedance f = 100 kHz, AV = 10 TA = 25°C 29 Ω Common-mode rejection ratio VICR = 0 V to 5 V RS = 50 Ω TA = 25°C 71 Full range (1) 60 VDD = 2.7 V to 6 V VIC = VDD / 2; no load TA = 25°C 80 VDD = 3 V to 5 V VIC = VDD / 2; no load TA = 25°C 85 Full range (1) 80 Supply-voltage rejection ratio (ΔVDD± / ΔVIO) Supply current (per channel) VO = 2.5 V; no load Full range (1) TA = 25°C Full range (1) 85 dB 85 75 dB 95 0.55 0.65 1 mA Full range is –40°C to +125°C. Copyright © 2003–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLV2460-Q1 TLV2460A-Q1 TLV2461-Q1 TLV2461A-Q1 TLV2462-Q1 TLV2462A-Q1 TLV2463Q1 TLV2463A-Q1 TLV2464A-Q1 9 TLV2460-Q1, TLV2460A-Q1, TLV2461-Q1, TLV2461A-Q1 TLV2462-Q1, TLV2462A-Q1, TLV2463-Q1, TLV2463A-Q1, TLV2464A-Q1 SGLS008G – MARCH 2003 – REVISED FEBRUARY 2018 www.ti.com Electrical Characteristics: VDD = 5 V (continued) at specified free-air temperature, VDD = 5 V, (unless otherwise noted) PARAMETER IDD(SHD N) 10 Supply current in shutdown (TLV2460-Q1, TLV2463-Q1) TEST CONDITIONS SHDN < 0.7 V, Per channel in shutdown Submit Documentation Feedback MIN TA = 25°C Full range TYP MAX UNIT 1 (1) 3 μA Copyright © 2003–2018, Texas Instruments Incorporated Product Folder Links: TLV2460-Q1 TLV2460A-Q1 TLV2461-Q1 TLV2461A-Q1 TLV2462-Q1 TLV2462A-Q1 TLV2463Q1 TLV2463A-Q1 TLV2464A-Q1 TLV2460-Q1, TLV2460A-Q1, TLV2461-Q1, TLV2461A-Q1 TLV2462-Q1, TLV2462A-Q1, TLV2463-Q1, TLV2463A-Q1, TLV2464A-Q1 www.ti.com SGLS008G – MARCH 2003 – REVISED FEBRUARY 2018 6.11 Operating Characteristics: VDD = 3 V VDD = 3 V , at specified free-air temperature (unless otherwise noted) PARAMETER SR Slew rate at unity gain Vn Equivalent input noise voltage In Equivalent input noise current TEST CONDITIONS VO(PP) = 2 V CL = 160 pF RL = 10 kΩ TA = 25°C Full range (1) f = 100 Hz TA = 25°C f = 1 kHz f = 1 kHz TA = 25°C AV = 1 THD + N t(on) Total harmonic distortion plus noise Amplifier turn-on time VO(PP) = 2 V RL = 10 kΩ, f = 1 kHz AV = 1 RL = 10 kΩ AV = 10 Amplifier turn-off time AV = 1 RL = 10 kΩ ts φm (1) Settling time 1 1.6 16 11 0.13 TA = 25°C 7.6 f = 10 kHz CL = 160 pF RL = 10 kΩ nV/√Hz pA/√Hz 0.02% 0.08% Channel 1 only, Channel 2 on UNIT V/μs Both channels Channel 1 only, Channel 2 on MAX 0.8 AV = 100 TA = 25°C μs 7.65 333 328 TA = 25°C Channel 2 only, Channel 1 on Gain-bandwidth product TYP 0.006% Both channels t(off) MIN ns 329 TA = 25°C 5.2 V(STEP)PP = 2 V AV = –1 CL = 10 pF RL = 10 kΩ 0.1% 1.47 0.01% 1.78 V(STEP)PP = 2 V AV = –1 CL = 56 pF RL = 10 kΩ 0.1% TA = 25°C 0.01% 1.77 MHz μs 1.98 Phase margin at unity gain RL = 10 kΩ CL = 160 pF TA = 25°C 44 ° Gain margin RL = 10 kΩ CL = 160 pF TA = 25°C 7 dB Full range is –40°C to +125°C. Copyright © 2003–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLV2460-Q1 TLV2460A-Q1 TLV2461-Q1 TLV2461A-Q1 TLV2462-Q1 TLV2462A-Q1 TLV2463Q1 TLV2463A-Q1 TLV2464A-Q1 11 TLV2460-Q1, TLV2460A-Q1, TLV2461-Q1, TLV2461A-Q1 TLV2462-Q1, TLV2462A-Q1, TLV2463-Q1, TLV2463A-Q1, TLV2464A-Q1 SGLS008G – MARCH 2003 – REVISED FEBRUARY 2018 www.ti.com 6.12 Operating Characteristics: VDD = 5 V VDD = 5 V, at specified free-air temperature, (unless otherwise noted) PARAMETER TEST CONDITIONS Slew rate at unity gain Vn Equivalent input noise voltage In Equivalent input noise current f = 100 Hz THD + N Total harmonic distortion plus noise TA = 25°C VO(PP) = 2 V CL = 160 pF RL = 10 kΩ SR Full range (1) f = 100 Hz TA = 25°C f = 1 kHz VO(PP) = 4 V RL = 10 kΩ f = 10 kHz TA = 25°C AV = 1 AV = 10 TA = 25°C t(off) Amplifier turn-on time Amplifier turn-off time AV = 1 RL = 10 kΩ AV = 1 RL = 10 kΩ ts φm (1) 12 Settling time 1.6 V/μs 0.8 14 11 0.13 μs Both channels 333 328 TA = 25°C 0.1% V(STEP)PP = 2 V AV = –1 CL = 56 pF RL = 10 kΩ 0.1% ns 329 TA = 25°C V(STEP)PP = 2 V AV = –1 CL = 10 pF RL = 10 kΩ pA/√Hz 7.65 TA = 25°C 7.25 f = 10 kHz CL = 160 pF RL = 10 kΩ nV/√Hz 0.01% Channel 2 only, Channel 1 on Channel 1 only, Channel 2 on UNIT 7.6 Channel 2 only, Channel 1 on Gain-bandwidth product 1 MAX 0.04% Both channels t(on) TYP 0.004% AV = 100 Channel 1 only, Channel 2 on MIN 6.4 MHz 1.53 0.01% 1.83 TA = 25°C 0.01% 3.13 μs 3.33 Phase margin at unity gain RL = 10 kΩ CL = 160 pF TA = 25°C 45 ° Gain margin RL = 10 kΩ CL = 160 pF TA = 25°C 7 dB Full range is –40°C to +125°C. Submit Documentation Feedback Copyright © 2003–2018, Texas Instruments Incorporated Product Folder Links: TLV2460-Q1 TLV2460A-Q1 TLV2461-Q1 TLV2461A-Q1 TLV2462-Q1 TLV2462A-Q1 TLV2463Q1 TLV2463A-Q1 TLV2464A-Q1 TLV2460-Q1, TLV2460A-Q1, TLV2461-Q1, TLV2461A-Q1 TLV2462-Q1, TLV2462A-Q1, TLV2463-Q1, TLV2463A-Q1, TLV2464A-Q1 www.ti.com SGLS008G – MARCH 2003 – REVISED FEBRUARY 2018 6.13 Typical Characteristics CONDITION STATEMENT TBD Table 1. Table of Graphs GRAPH TITLE VIO FIGURE Input offset voltage vs common-mode input voltage 1, 2 IIB Input bias current vs free-air temperature 3, 4 IIO Input offset current vs free-air temperature 3, 4 High-level output voltage vs high-level output current 5, 6 VOH VOL Low-level output voltage vs low-level output current 7, 8 VO(PP) Maximum peak-to-peak output voltage vs frequency 9, 10 Open-loop gain vs frequency 11, 12 Phase vs frequency 11, 12 Differential voltage amplification vs load resistance 13 AVD zo Capacitive load vs load resistance 14 Output impedance vs frequency 15, 16 CMRR Common-mode rejection ratio vs frequency 17 kSVR Supply-voltage rejection ratio vs frequency 18, 19 Supply current vs supply voltage 20 Supply current vs free-air temperature 21 Amplifier turnon characteristics 22 Amplifier turnoff characteristics 23 Supply current turnon 24 Supply current turnoff 25 Shutdown supply current vs free-air temperature 26 Slew rate vs load capacitance 27 IDD SR Vn THD THD + N φm Equivalent input noise voltage vs frequency 28, 29 Equivalent input noise voltage vs common-mode input voltage 30, 31 Total harmonic distortion vs frequency 32, 33 Total harmonic distortion plus noise vs peak-to-peak signal amplitude 34, 35 Phase margin vs frequency 11, 12 Phase margin vs load capacitance 36 Phase margin vs free-air temperature 37 Gain-bandwidth product vs supply voltage 38 Gain-bandwidth product vs free-air temperature 39 Large signal follower 40, 41 Small signal follower 42, 43 Inverting large signal 44, 45 Inverting small signal 46, 47 Copyright © 2003–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLV2460-Q1 TLV2460A-Q1 TLV2461-Q1 TLV2461A-Q1 TLV2462-Q1 TLV2462A-Q1 TLV2463Q1 TLV2463A-Q1 TLV2464A-Q1 13 TLV2460-Q1, TLV2460A-Q1, TLV2461-Q1, TLV2461A-Q1 TLV2462-Q1, TLV2462A-Q1, TLV2463-Q1, TLV2463A-Q1, TLV2464A-Q1 SGLS008G – MARCH 2003 – REVISED FEBRUARY 2018 www.ti.com 1 1 VDD = 5 V TA = 25°C 0.8 0.6 Input Offset Voltage, VIO (mV) Input Offset Voltage, VIO (mV) VDD = 3 V TA = 25°C 0.4 0.2 0 0.2 0.4 0.6 0.6 0.4 0.2 0 0.2 0.4 0.6 0.8 0.8 1 1 0 0.5 1.5 1 3 2.5 2 0 Common-Mode Input Voltage, VICR (V) 1 2 3 4 Common-Mode Input Voltage, VICR (V) VDD = 5 V VDD = 3 V 5 VDD = 3 V VI = 1.5 V 4.5 IIB 4 3.5 3 2.5 2 1.5 1 0.5 IIO 0.5 –55 5 –35 –15 25 45 65 85 105 125 Figure 2. Input Offset Voltage vs Common-Mode Input Voltage Input Bias and Input Offset Current, IIB and IIO (nA) Input Bias and Input Offset Current, IIB and IIO (nA) Figure 1. Input Offset Voltage vs Common-Mode Input Voltage 0 5 6 VDD = 5 V VI = 2.5 V 5 IIB 4 3 2 1 IIO 0 1 –55 5 –35 –15 25 45 65 85 105 125 Free-Air Temperature, TA (°C) Free-Air Temperature, TA (°C) VDD = 5 V VDD = 3 V Figure 3. Input Bias and Input Offset Current vs Free-Air Temperature Figure 4. Input Bias and Input Offset Current vs Free-Air Temperature 3 5 VDD = 3 V DC VDD = 5 V DC High-Level Output Voltage, VOH (V) High-Level Output Voltage, VOH (V) 4.5 2.5 TA = 55 °C 2 1.5 TA = 125°C TA = 85°C TA = 25°C 1 TA = 40 °C 0.5 TA = 55 °C 4 3.5 3 TA = 125°C TA = 85°C 2.5 2 TA = 25°C 1.5 TA = 40 °C 1 0.5 0 0 0 10 20 30 40 50 60 70 80 High-Level Output Current, IOH (mA) VDD = 3 VDC Figure 5. High-Level Output Voltage vs High-Level Output Current 14 Submit Documentation Feedback 0 20 40 60 80 100 120 140 160 180 200 High-Level Output Current, IOH (mA) VDD = 5 VDC Figure 6. High-Level Output Voltage vs High-Level Output Current Copyright © 2003–2018, Texas Instruments Incorporated Product Folder Links: TLV2460-Q1 TLV2460A-Q1 TLV2461-Q1 TLV2461A-Q1 TLV2462-Q1 TLV2462A-Q1 TLV2463Q1 TLV2463A-Q1 TLV2464A-Q1 TLV2460-Q1, TLV2460A-Q1, TLV2461-Q1, TLV2461A-Q1 TLV2462-Q1, TLV2462A-Q1, TLV2463-Q1, TLV2463A-Q1, TLV2464A-Q1 www.ti.com SGLS008G – MARCH 2003 – REVISED FEBRUARY 2018 4.5 3 VDD = 3 V DC VDD = 5 V DC Low-Level Output Voltage, VOL (V) 4 Low-Level Output Voltage, VOL (V) 2.5 TA = 40 °C 2 TA = 25°C TA = 85°C TA = 125°C 1.5 1 0.5 20 30 40 50 3 TA = 25°C 2.5 TA = 85°C TA = 125°C 1.5 1 TA = 55 °C 0.5 0 10 TA = 40 °C 2 TA = 55 °C 0 3.5 60 70 0 Low-Level Output Current, IOL (mA) 0 20 Figure 7. Low-Level Output Voltage vs Low-Level Output Current 60 80 100 120 140 160 Figure 8. Low-level Output Voltage vs Low-Level Output Current 5.5 3 VDD = 3 V AV = 10 THD = 1% RL = 10 kΩ 2.5 Peak-to-Peak Output Voltage, VO(PP) (V) Peak-to-Peak Output Voltage, VO(PP) (V) 40 VDD = 5 VDC VDD = 3 VDC 2 1.5 1 0.5 VDD = 5 V AV = 10 THD = 1% RL = 10 kΩ 5 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 0 10k 10M Frequency, f (Hz) VDD = 3 V VDD = 5 V Figure 9. Peak-to-Peak Output Voltage vs Frequency 100 VDD = ±1.5 V RL = 10 kΩ CL = 0 TA = 25°C 90 80 60 100 20° 90 0° 80 20° 70 40° AVD 50 60° 40 80° 30 100 ° Phase 20 Figure 10. Peak-to-Peak Output Voltage vs Frequency 40° Phase Open-Loop Gain (dB) 70 120 ° 10M 1M 100k Frequency, f (Hz) 40° VDD = ±2.5 V RL = 10 kΩ CL = 0 TA = 25°C 60 20° 0° 20° 40° AVD 50 60° 40 80° 100° 30 Phase 20 120° 10 140 ° 10 140° 0 160 ° 0 160° –10 180 ° –10 180° –20 200 ° 10M –20 10 100 1k 10k 100k 1M Frequency, f (Hz) VDD = ±1.5 V Figure 11. Open-Loop Gain and Phase vs Frequency Copyright © 2003–2018, Texas Instruments Incorporated Phase 1M 100k Open-Loop Gain (dB) 10k 200° 10 100 1k 10k 100k 1M 10M Frequency, f (Hz) VDD = ±2.5 V Figure 12. Open-Loop Gain and Phase vs Frequency Submit Documentation Feedback Product Folder Links: TLV2460-Q1 TLV2460A-Q1 TLV2461-Q1 TLV2461A-Q1 TLV2462-Q1 TLV2462A-Q1 TLV2463Q1 TLV2463A-Q1 TLV2464A-Q1 15 TLV2460-Q1, TLV2460A-Q1, TLV2461-Q1, TLV2461A-Q1 TLV2462-Q1, TLV2462A-Q1, TLV2463-Q1, TLV2463A-Q1, TLV2464A-Q1 SGLS008G – MARCH 2003 – REVISED FEBRUARY 2018 www.ti.com 10000 TA = 25°C 160 140 Capacitance, CL (pF) Differential Voltage Amplification, AVD (V/mV) 180 120 VDD = ±2.5 V 100 VDD = ±1.5 V 80 60 Phase Margin < 30° 1000 Phase Margin > 30° 40 VDD = 5 V Phase Margin = 30° TA = 25°C 20 100 0 100 1k 100k 10k Load Resistance, RL (Ω) Figure 13. Differential Voltage Amplification vs Load Resistance 1000 VDD = ±1.5 V TA = 25°C VDD = ±2.5 V TA = 25°C 100 100 Output Impedance, ZO (Ω) Output Impedance, ZO (Ω) 10k Figure 14. Capacitive Load vs Load Resistance 1000 10 AV = 100 1 AV = 10 0.1 100 1k Load Resistance, RL (Ω) 10 1M 10 AV = 100 1 AV = 10 0.1 AV = 1 AV = 1 0.01 100 1k 10k 100k 1M 0.01 100 10M 1k Frequency, f (Hz) VDD = ±1.5 V 1M 10M Figure 16. Output Impedance vs Frequency 110 Supply Voltage Rejection Ratio , kSVR (dB) 90 Common-Mode Rejection Ratio,CMRR (dB) 100k VDD = ±2.5 V Figure 15. Output Impedance vs Frequency 85 80 VDD = 5 V VIC = 2.5 V 75 VDD = 3 V VIC = 1.5 V 70 65 60 10 10k Frequency, f (Hz) 100 10k 100k 1k Frequency, f (Hz) 1M 10M +kSVR VDD = ±1.5 V TA = 25°C 100 90 k SVR 80 70 60 +kSVR 50 k SVR 40 10 100 10k 100k 1k Frequency, f (Hz) 1M 10M VDD = ±1.5 V Figure 17. Common-Mode Rejection Ratio vs Frequency 16 Submit Documentation Feedback Figure 18. Supply-Voltage Rejection Ratio vs Frequency Copyright © 2003–2018, Texas Instruments Incorporated Product Folder Links: TLV2460-Q1 TLV2460A-Q1 TLV2461-Q1 TLV2461A-Q1 TLV2462-Q1 TLV2462A-Q1 TLV2463Q1 TLV2463A-Q1 TLV2464A-Q1 TLV2460-Q1, TLV2460A-Q1, TLV2461-Q1, TLV2461A-Q1 TLV2462-Q1, TLV2462A-Q1, TLV2463-Q1, TLV2463A-Q1, TLV2464A-Q1 www.ti.com SGLS008G – MARCH 2003 – REVISED FEBRUARY 2018 0.8 +kSVR 80 IDD = 125°C VDD = ±2.5 V TA = 25°C k SVR 70 60 +kSVR 50 IDD = 85°C 0.7 Supply Current, IDD (mA) Supply Voltage Rejection Ratio , kSVR (dB) 90 0.6 0.5 0.40 IDD = 25°C 0.30 IDD = 55 °C IDD = 40 °C 0.20 k SVR 0.10 40 10 10k 100k 1k Frequency, f (Hz) 100 1M 2.5 10M 3 3.5 4 4.5 5 5.5 6 Supply Voltage, VDD (V) VDD = ±2.5 V Figure 19. Supply-Voltage Rejection Ratio vs Frequency Figure 20. Supply Current vs Supply Voltage 0.8 0.80 IDD = 125°C 0.75 0.70 VDD = 5 V VI = 2.5 V 0.65 Supply Current, IDD (mA) Supply Current, IDD (mA) IDD = 85°C 0.7 0.60 0.55 VDD = 3 V VI = 1.5 V 0.50 0.45 0.6 0.5 0.40 IDD = 25°C 0.30 IDD = 55 °C 0.40 IDD = 40 °C 0.20 0.35 0.30 –55 –35 0.10 –15 5 45 25 65 85 105 2.5 125 3 Figure 21. Supply Current vs Free-Air Temperature 5 5.5 6 VDD = 5 V RL = 10 kΩ AV = 1 TA = 25°C Shutdown Pin 3 Shutdown Voltage, VSD (V) Shutdown Voltage, VSD (V) 4 Shutdown Pin 3 2 1 0 Amplifier Output 3 0 –5 4.5 5 4 2 4 Figure 22. Amplifier With a Shutdown Pulse Turnon Characteristics 5 1 3.5 Supply Voltage, VDD (V) Free-Air Temperature, TA (°C) VDD = 5 V RL = 10 kΩ AV = 1 TA = 25°C –3 –1 2 1 0 3 Amplifier Output 2 1 1 3 5 7 9 11 Time, t (μs) Figure 23. Amplifier With a Shutdown Pulse Turnoff Characteristics Copyright © 2003–2018, Texas Instruments Incorporated 0 –5 –3 –1 3 1 Time, t (μs) 5 7 Figure 24. Supply Current With a Shutdown Pulse Turnon Characteristics Submit Documentation Feedback Product Folder Links: TLV2460-Q1 TLV2460A-Q1 TLV2461-Q1 TLV2461A-Q1 TLV2462-Q1 TLV2462A-Q1 TLV2463Q1 TLV2463A-Q1 TLV2464A-Q1 17 TLV2460-Q1, TLV2460A-Q1, TLV2461-Q1, TLV2461A-Q1 TLV2462-Q1, TLV2462A-Q1, TLV2463-Q1, TLV2463A-Q1, TLV2464A-Q1 SGLS008G – MARCH 2003 – REVISED FEBRUARY 2018 www.ti.com Shutdown Pin 4.5 0.6 0.4 3.5 Supply Current 2.5 0.2 1.5 0 0.5 0.2 –0.40 0.2 0 Time, t (μs) –0.20 0.4 2.5 Shutdown Supply Current, IDD (mA) VDD = 5 V VI = 2.5 V AV = 1 TA = 25°C Shutdown Voltage, VSD (V) Supply Current, IDD (mA) 0.8 3 5.5 1 1.5 1 0 1 0.5 0.6 –55 –35 Equivalent Input Noise Voltage, Vn (nV/ Hz) Slew Rate, SR (V/ms) 1.7 SR+ 1.6 1.55 SR 1.5 VO(PP) = 2 V CL = 160 pF AV = 1 RL = 10 kΩ TA = 25°C 3 5 3.5 4 4.5 Supply Voltage, VDD (V) 5.5 Figure 27. Slew Rate vs Supply Voltage 85 105 125 VDD = 3 V AV = 10 VI = 1.5 V TA = 25°C 16 15 14 13 12 11 10k 1k Frequency, f (Hz) 100k Figure 28. Equivalent Input Noise Voltage vs Frequency 17 Equivalent Input Noise Voltage, Vn (nV/ Hz) Equivalent Input Noise Voltage, Vn (nV/ Hz) 65 20 VDD = 5 V AV = 10 VI = 2.5 V TA = 25°C 16 15 14 13 12 11 VDD = 3 V AV = 10 f = 1 kHz TA = 25°C 15 14 13 12 11 10 10k 1k Frequency, f (Hz) 100k Figure 29. Equivalent Input Noise Voltage vs Frequency 18 45 17 10 100 6 18 10 100 25 18 1.65 1.3 2.5 5 Figure 26. Shutdown Supply Current vs Free-Air Temperature 1.8 1.35 –15 Free-Air Temperature, TA (°C) 1.75 1.4 VDD = 3 V VI = 1.5 V 0.5 0.5 Figure 25. Turnoff Supply Current With a Shutdown Pulse 1.45 VDD = 5 V VI = 2.5 V 2 Submit Documentation Feedback 0 0.5 1.5 2.5 1 2 Common-Mode Input Voltage, VICR (V) Figure 30. Equivalent Input Noise Voltage vs Common-Mode Input Voltage Copyright © 2003–2018, Texas Instruments Incorporated Product Folder Links: TLV2460-Q1 TLV2460A-Q1 TLV2461-Q1 TLV2461A-Q1 TLV2462-Q1 TLV2462A-Q1 TLV2463Q1 TLV2463A-Q1 TLV2464A-Q1 TLV2460-Q1, TLV2460A-Q1, TLV2461-Q1, TLV2461A-Q1 TLV2462-Q1, TLV2462A-Q1, TLV2463-Q1, TLV2463A-Q1, TLV2464A-Q1 www.ti.com SGLS008G – MARCH 2003 – REVISED FEBRUARY 2018 0.5 20 15 VDD = ±1.5 V VO(PP) = 2 V RL = 10 kΩ Total Harmonic Distortion, THD (%) VDD = 5 V AV = 10 f = 1 kHz TA = 25°C 14 13 12 11 AV = 10 AV = 1 0.001 10 0 1 2 3 4 Common-Mode Input Voltage, VICR (V) AV = 100 0.1 5 10 100 1k 10k 100k Frequency, f (Hz) VDD = ±1.5 V Figure 31. Equivalent Input Noise Voltage vs Common-Mode Input Voltage Figure 32. Total Harmonic Distortion vs Frequency 1 VDD = ±2.5 V VO(PP) = 4 V RL = 10 kΩ Total Harmonic Distortion + Noise, THD+N (%) Total Harmonic Distortion, THD (%) 1 0.1 AV = 100 AV = 10 AV = 1 0.001 10 100 1k 10k VDD = 3 V AV = 1 TA = 25°C RL = 250 Ω RL = 2 kΩ 0.1 RL = 10 kΩ 0.010 RL = 100 kΩ 0.001 100k 1 Frequency, f (Hz) 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 Peak-to-Peak Signal Amplitude ( V) VDD = ±2.5 V VDD = 3 V Figure 33. Total Harmonic Distortion vs Frequency Figure 34. Total Harmonic Distortion Plus Noise vs Peak-toPeak Signal Amplitude 90 RL = 250 Ω VDD = ±2.5 V TA = 25°C RL = 10 kΩ 80 Phase Margin, φm (degrees) Total Harmonic Distortion + Noise, THD+N (%) 1 RL = 2 kΩ 0.1 3.2 RL = 10 kΩ 0.010 RL = 100 kΩ 70 Rnull = 50 Ω 60 50 40 Rnull = 20 Ω 30 20 VDD = 5 V AV = 1 TA = 25°C Rnull = 0 Ω 10 0.001 0 4 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 Peak-to-Peak Signal Amplitude (V) 5 10 100 1k 10k 100k Load Capacitance, CL (pF) VDD = 5 V Figure 35. Total Harmonic Distortion Plus Noise vs Peak-toPeak Signal Amplitude Copyright © 2003–2018, Texas Instruments Incorporated Figure 36. Phase Margin vs Load Capacitance Submit Documentation Feedback Product Folder Links: TLV2460-Q1 TLV2460A-Q1 TLV2461-Q1 TLV2461A-Q1 TLV2462-Q1 TLV2462A-Q1 TLV2463Q1 TLV2463A-Q1 TLV2464A-Q1 19 TLV2460-Q1, TLV2460A-Q1, TLV2461-Q1, TLV2461A-Q1 TLV2462-Q1, TLV2462A-Q1, TLV2463-Q1, TLV2463A-Q1, TLV2464A-Q1 SGLS008G – MARCH 2003 – REVISED FEBRUARY 2018 www.ti.com 60 5 RL = 10 kΩ CL = 160 pF 4.75 Gain Bandwidth Product (MHz) Phase Margin, φm (degrees) 55 CL = 160 pF RL = 10 kΩ f = 10 kHz TA = 25°C 50 VDD = ±2.5 V 45 VDD = ±1.5 V 40 35 4.5 4.25 4 3.75 30 –55 –35 5 –15 25 45 65 85 105 3.5 2.5 125 5 3.5 4 4.5 Supply Voltage, VDD (V) 3 Free-Air Temperature, TA (°C) Figure 37. Phase Margin vs Free-Air Temperature 2.2 RL = 10 kΩ CL = 160 pF 2 VDD = ±2.5 V 4.25 4 3.75 3.5 Input 1.8 Voltage, VO (V) Gain Bandwidth Product (MHz) 4.5 6 Figure 38. Gain Bandwidth Product vs Supply Voltage 5 4.75 5.5 VDD = ±1.5 V Output 1.6 1.4 VDD = 3 V VI(PP) = 1 V VI = 1.5 V RL = 10 kΩ CL = 160 pF AV = 1 TA = 25°C 1.2 1 3.25 3 –55 –35 5 –15 25 45 65 85 105 0.8 –2 125 0 Free-Air Temperature, TA (°C) 2 4 Input Output 8 6 10 Time, t (μs) 12 14 16 18 VDD = 3 V Figure 40. Large Signal Follower Figure 39. Gain Bandwidth Product vs Free-Air Temperature 3.7 1.6 3.3 1.55 Voltage, VO (V) Voltage, VO (V) Input 2.9 Output 2.5 VDD = 5 V VI(PP) = 2 V VI = 2.5 V RL = 10 kΩ CL = 160 pF AV = 1 TA = 25°C 2.1 1.7 1.3 –2 0 2 4 Input 12 14 16 VDD = 5 V Figure 41. Large Signal Follower 20 Submit Documentation Feedback 1.5 Output 1.45 Output 8 6 10 Time, t (μs) Input 18 1.4 –0.2 VDD = 3 V VI(PP) = 100 mV VI = 1.5 V RL = 10 kΩ 0 CL = 160 pF AV = 1 TA = 25°C 0.2 0.4 0.6 0.8 1 Time, t (μs) 1.2 1.4 1.6 1.8 VDD = 3 V Figure 42. Small Signal Follower Copyright © 2003–2018, Texas Instruments Incorporated Product Folder Links: TLV2460-Q1 TLV2460A-Q1 TLV2461-Q1 TLV2461A-Q1 TLV2462-Q1 TLV2462A-Q1 TLV2463Q1 TLV2463A-Q1 TLV2464A-Q1 TLV2460-Q1, TLV2460A-Q1, TLV2461-Q1, TLV2461A-Q1 TLV2462-Q1, TLV2462A-Q1, TLV2463-Q1, TLV2463A-Q1, TLV2464A-Q1 www.ti.com SGLS008G – MARCH 2003 – REVISED FEBRUARY 2018 2.6 2.3 Input 2.1 1.9 Voltage, VO (V) Voltage, VO (V) 2.55 Input 2.5 Output VDD = 3 V VI(PP) = 1 V VI = 1.5 V RL = 10 kΩ CL = 160 pF AV = 1 TA = 25°C 1.7 1.5 1.3 1.1 2.45 2.4 –0.2 VDD = 5 V VI(PP) = 100 mV VI = 2.5 V RL = 10 kΩ 0 Output 0.9 CL = 160 pF AV = 1 TA = 25°C 0.2 0.4 0.6 0.8 1 Time, t (μs) 1.2 1.4 0.7 0.5 –0.2 1.6 1.8 0 VDD = 5 V 0.2 0.4 0.6 0.8 1 Time, t (μs) 1.2 1.4 1.6 1.8 VDD = 3 V Figure 43. Small Signal Follower Figure 44. Inverting Large Signal 1.6 4 Input Input 1.55 VDD = 5 V VI(PP) = 2 V VI = 2.5 V RL = 10 kΩ CL = 160 pF AV = 1 TA = 25°C 3 2.5 Voltage, VO (V) Voltage, VO (V) 3.5 VDD = 3 V VI(PP) = 100 mV VI = 1.5 V RL = 10 kΩ CL = 160 pF AV = 1 TA = 25°C 1.5 2 1.45 Output Output 1.5 1 –0.2 0 0.2 0.4 0.6 0.8 1 Time, t (μs) 1.2 1.4 1.4 –0.2 1.6 1.8 0 0.2 0.4 0.6 0.8 1 Time, t (μs) 1.2 1.4 1.6 1.8 VDD = 3 V VDD = 5 V Figure 46. Inverting Small Signal Figure 45. Inverting Large Signal 2.6 Input Voltage, VO (V) 2.55 VDD = 5 V VI(PP) = 100 mV VI = 2.5 V RL = 10 kΩ CL = 160 pF AV = 1 TA = 25°C 2.5 2.45 Output 2.4 –0.2 0 0.2 0.4 0.6 0.8 1 Time, t (μs) 1.2 1.4 1.6 1.8 VDD = 5 V Figure 47. Inverting Small Signal Copyright © 2003–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLV2460-Q1 TLV2460A-Q1 TLV2461-Q1 TLV2461A-Q1 TLV2462-Q1 TLV2462A-Q1 TLV2463Q1 TLV2463A-Q1 TLV2464A-Q1 21 TLV2460-Q1, TLV2460A-Q1, TLV2461-Q1, TLV2461A-Q1 TLV2462-Q1, TLV2462A-Q1, TLV2463-Q1, TLV2463A-Q1, TLV2464A-Q1 SGLS008G – MARCH 2003 – REVISED FEBRUARY 2018 www.ti.com 7 Parameter Measurement Information Rnull _ + RL CL Figure 48. Capacitive Load Drive 8 Detailed Description 8.1 Overview The TLV246x-Q1 family of devices are low-power rail-to-rail input and output operational amplifiers. The input common-mode voltage range extends beyond the supply rails for maximum dynamic range in a low-voltage system. The amplifier output has rail-to-rail performance with high drive capability, solving one of the limitations of older rail-to-rail input and output operational amplifiers 8.2 Functional Block Diagram 8.3 Feature Description The TLV246x-Q1 family features 6.4-MHz bandwidth and voltage noise of 11 nV/√Hz with performance rated from 2.7 V to 6 V across an automotive temperature range (–40⁰C to +125⁰C). This family is designed for a wide range of automotive applications. 8.3.1 Driving a Capacitive Load When the amplifier configuration is in this manner, capacitive loading directly on the output decreases the phase margin of the device leading to high-frequency ringing or oscillations. Therefore, for capacitive loads of greater than 10 pF, TI recommends placing a resistor in series (RNULL) with the output of the amplifier; see Figure 49. A minimum value of 20 Ω works well for most applications. RF RG Input _ RNULL Output + CLOAD Figure 49. Driving a Capacitive Load 22 Submit Documentation Feedback Copyright © 2003–2018, Texas Instruments Incorporated Product Folder Links: TLV2460-Q1 TLV2460A-Q1 TLV2461-Q1 TLV2461A-Q1 TLV2462-Q1 TLV2462A-Q1 TLV2463Q1 TLV2463A-Q1 TLV2464A-Q1 TLV2460-Q1, TLV2460A-Q1, TLV2461-Q1, TLV2461A-Q1 TLV2462-Q1, TLV2462A-Q1, TLV2463-Q1, TLV2463A-Q1, TLV2464A-Q1 www.ti.com SGLS008G – MARCH 2003 – REVISED FEBRUARY 2018 Feature Description (continued) 8.3.2 Offset Voltage The output offset voltage (VOO) is the sum of the input offset voltage (VIO) and both input-bias currents (IIB) times the corresponding gains. Use the schematic and formula in Figure 50 to calculate the output offset voltage. RF IIB RG + VI VO + RS IIB+ VOO = VIO (1 + ( RF RF )) ± IIB + RS (1 + ( )) ± IIB - RF RG RG Figure 50. Output Offset Voltage Model 8.3.3 General Configurations When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often required. To limit bandwidth, place an RC filter at the noninverting terminal of the amplifier (see Figure 51). RG RF VI VO + R1 C1 f –3dB = 1 2pR1C1 VO RF 1 = (1 + )( ) VI RG 1 + sR1C1 Figure 51. Single-Pole Low-Pass Filter If even more attenuation is required, a multiple pole filter is required. Use a Sallen-Key filter for this task; see Figure 52. For best results, the amplifier must have a bandwidth that is eight to ten times the filter frequency bandwidth. Failure to do this can result in phase shift of the amplifier. C1 + _ VI R1 R1 = R2 = R C1 = C2 = C Q = Peaking Factor (Butterworth Q = 0.707) R2 f –3dB = C2 RG RF RG = 1 2pRC RF 1 2 –Q Figure 52. 2-Pole Low-Pass Sallen-Key Filter Copyright © 2003–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLV2460-Q1 TLV2460A-Q1 TLV2461-Q1 TLV2461A-Q1 TLV2462-Q1 TLV2462A-Q1 TLV2463Q1 TLV2463A-Q1 TLV2464A-Q1 23 TLV2460-Q1, TLV2460A-Q1, TLV2461-Q1, TLV2461A-Q1 TLV2462-Q1, TLV2462A-Q1, TLV2463-Q1, TLV2463A-Q1, TLV2464A-Q1 SGLS008G – MARCH 2003 – REVISED FEBRUARY 2018 www.ti.com Feature Description (continued) 8.3.4 General Power Dissipation Considerations For a given θJA value, the maximum power dissipation is shown in Figure 53 and is calculated by Equation 1: TMAX - TA ) PD = ( q JA Where: • • • • • • PD = Maximum power dissipation of TLV246x-Q1 (watts) TMAX = Absolute maximum junction temperature (150°C) TA = Ambient free-air temperature (°C) θJA = θJC + θCA θJC = Thermal coefficient from junction to case θCA = Thermal coefficient from case to ambient air (°C/W) (1) 2 Maximum Power Dissipation (W) 1.75 1.5 1.25 TJ = 150°C PDIP Package Low-K Test PCB θJA = 104°C/W SOIC Package Low-K Test PCB θJA = 176°C/W MSOP Package Low-K Test PCB θJA = 260°C/W 1 0.75 0.5 0.25 SOT-23 Package Low-K Test PCB θJA = 324°C/W 0 –55 –40 –25 –10 5 20 35 50 65 80 95 110 125 Free-Air Temperature, TA (°C) Figure 53. Maximum Power Dissipation vs Free-Air Temperature 24 Submit Documentation Feedback Copyright © 2003–2018, Texas Instruments Incorporated Product Folder Links: TLV2460-Q1 TLV2460A-Q1 TLV2461-Q1 TLV2461A-Q1 TLV2462-Q1 TLV2462A-Q1 TLV2463Q1 TLV2463A-Q1 TLV2464A-Q1 TLV2460-Q1, TLV2460A-Q1, TLV2461-Q1, TLV2461A-Q1 TLV2462-Q1, TLV2462A-Q1, TLV2463-Q1, TLV2463A-Q1, TLV2464A-Q1 www.ti.com SGLS008G – MARCH 2003 – REVISED FEBRUARY 2018 8.4 Device Functional Modes The TLV2461-Q1, TLV2462-Q1, and TLV2464A-Q1 devices power on when the supply is connected. These devices can operate with a single supply or dual supplies, depending on the application. The devices are in their full performance once the supply is above the recommended value. The TLV2460-Q1 and TLV2463-Q1 devices feature a shutdown mode, which reduces the quiescent current to 0.3 µA in shutdown mode. 8.4.1 Shutdown Function Two members of the TLV246x-Q1 family (TLV2460-Q1 and TLV2463-Q1) feature a shutdown terminal that conserves battery life in portable applications. When the shutdown terminal is tied low, the supply current is reduced to 0.3 μA per channel, the amplifier is disabled and the outputs are placed in a high-impedance mode. To enable the amplifier, leave the shutdown terminal floating or pull the shutdown terminal high. When the shutdown terminal is left floating, take care to ensure that parasitic leakage current at the shutdown terminal does not inadvertently place the operational amplifier into shutdown. The shutdown terminal threshold is always referenced to VDD / 2. As a result, when operating the device with split-supply voltages (for example, ±2.5 V), the shutdown terminal must be pulled to VDD− (not GND) to disable the operational amplifier. The output of the amplifier with a shutdown pulse is shown in Figure 22, Figure 23, Figure 24, and Figure 25. The amplifier is powered with a single 5-V supply and configured as a noninverting configuration with a gain of 5. The amplifier turnon and turnoff times are measured from the 50% point of the shutdown pulse to the 50% point of the output waveform. The times for the single, dual, and quad are listed in the data tables. Copyright © 2003–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLV2460-Q1 TLV2460A-Q1 TLV2461-Q1 TLV2461A-Q1 TLV2462-Q1 TLV2462A-Q1 TLV2463Q1 TLV2463A-Q1 TLV2464A-Q1 25 TLV2460-Q1, TLV2460A-Q1, TLV2461-Q1, TLV2461A-Q1 TLV2462-Q1, TLV2462A-Q1, TLV2463-Q1, TLV2463A-Q1, TLV2464A-Q1 SGLS008G – MARCH 2003 – REVISED FEBRUARY 2018 www.ti.com 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information Most DC-to-DC converters use output-filter ceramic capacitors with very low equivalent series resistance (ESR). 1 This causes a double pole at the resonance frequency 2Œ LC . To achieve an adequate bandwidth and phase margin for the DC-to-DC converter, the device requires 1 compensation around the 2Œ LC resonance frequency. To achieve this, configure the error amplifier as type-3 compensation. The TLV2426x-Q1 series features a wide bandwidth UGBD of 6 MHz with rail-to-rail output for increased dynamic range. These features are designed for DC-to-DC loop compensation with any LC filter. 9.1.1 Macromodel Information Macromodel information provided was derived using Microsim Parts™ Release 8, the model generation software used with Microsim PSpice™. The Boyle macromodel (1) and subcircuit in Figure 54 are generated using the TLV246x-Q1 typical electrical and operating characteristics at TA = 25°C. Using this information, output simulations of the following key parameters are generated to a tolerance of 20% (in most cases): (1) • • • • • • 26 G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Integrated Circuit Operational Amplifiers,” IEEE Journal of Solid-State Circuits, SC-9, 353 (1974). Maximum positive output voltage swing Maximum negative output voltage swing Slew rate Quiescent power dissipation Input bias current Open-loop voltage amplification Submit Documentation Feedback • • • • • • Unity gain frequency Common-mode rejection ratio Phase margin DC output resistance AC output resistance Short-circuit output current limit Copyright © 2003–2018, Texas Instruments Incorporated Product Folder Links: TLV2460-Q1 TLV2460A-Q1 TLV2461-Q1 TLV2461A-Q1 TLV2462-Q1 TLV2462A-Q1 TLV2463Q1 TLV2463A-Q1 TLV2464A-Q1 TLV2460-Q1, TLV2460A-Q1, TLV2461-Q1, TLV2461A-Q1 TLV2462-Q1, TLV2462A-Q1, TLV2463-Q1, TLV2463A-Q1, TLV2464A-Q1 www.ti.com SGLS008G – MARCH 2003 – REVISED FEBRUARY 2018 99 EGND + FB RO2 R2 3 VDD + C2 6 7 + + ISS RSS CSS 9 VD VLIM + VB RP IN J1 GCM 53 10 2 8 GA DC J2 RO1 OUT IN + 1 11 12 92 54 C1 DP RD1 5 DLN DE + RD2 VE 90 HLIM + DLP 91 + VLP VLN + 4 GND .SUBCKT TLV246X 1 2 3 4 5 11 12 2.46034E-12 C1 7 10.0000E-12 6 C2 10 99 443.21E-15 CSS 53 DY 5 DC 54 5 DE DY 90 91 DX DLP 92 90 DX DLN 3 4 DP DX POLY (2) (3,0) (4,0) 0 .5 .5 EGND 99 0 99 POLY (5) VB VC VE VLP 7 FB + VLN 0 21.600E6 – 1E3 1E3 22E6 – 22E6 0 6 12 345.26E- 6 11 GA 10 99 15.4226E- 9 6 GCM 0 DC 18.850E- 6 10 4 ISS VLIM 1K HLIM 90 0 10 JX1 J1 11 2 10 JX2 12 1 J2 9 6 100.00E3 R2 11 2.8964E3 3 RD1 12 2.8964E3 3 RD2 5.6000 5 8 R01 99 6.2000 7 R02 4 8.9127 3 RP 99 10.610E6 10 RSS 9 0 DC 0 VB 53 3 VC DC .7836 4 VE 54 DC .7436 8 DC 0 7 VLIM 0 DC 117 VLP 91 0 92 DC 117 VLN .MODEL DX D (IS=800.00E–18) .MODEL DY D (IS=800.00E–18 Rs = 1m Cjo=10p) .MODEL JX1 NJF (IS=1.0000E–12 BETA=6.3239E–3 + VTO=–1 ) .MODEL JX2 NJF (IS=1.0000E–12 BETA=6.3239E–3 + VTO=–1 ) .ENDS .subckt TLV_246Y 1 2 3 4 5 6 11 12 2.4603E-12 c1 72 7 10.000E-12 c2 10 99 443.21E-15 css 70 53 dy dc 54 70 dy de 90 91 dx dlp 92 90 dx dln 4 dp 3 dx poly(2) (3,0) (4,0) 0 .5 .5 egnd 99 0 99 poly(5) vb vc ve vlp vln 0 7 fb 21.600E6 – 1E3 1E3 22E6 – 22E6 72 0 ga 11 12 345.26E- 6 gcm 0 72 10 99 15.422E- 9 dc 18.850E- 6 74 iss 4 vlim 1K hlim 90 0 j1 11 2 10 jx1 10 jx2 j2 12 1 100.00E3 r2 72 9 3 rd1 11 2.8964E3 3 12 2.8964E3 rd2 ro1 8 70 5.6000 ro2 7 99 6.2000 rp 8.9127 3 71 rss 10.610E6 99 10 rs1 6 4 1G rs2 4 6 1G rs3 4 6 1G rs4 4 6 1G s1 4 71 6 4 s1x 5 s2 70 6 4 s1x 74 s3 10 6 4 s1x 4 s4 6 4 s2x 74 0 9 dc 0 vb vc 53 3 dc .7836 ve 4 dc .7436 54 vlim 8 7 dc 0 vlp 0 91 dc 117 0 92 dc 117 vln .model dx D(Is=800.00E–18) .model dy D(Is=800.00E–18 Rs=1m Cjo=10p) .model jx1 NJF(Is=1.0000E–12 Beta=6.3239E–3 Vto=–1) .model jx2 NJF(Is=1.0000E–12 Beta=6.3239E–3 Vto=–1) .model s1x VSWITCH(Roff=1E8 Ron=1.0 Voff=2.5 Von=0.0) .model s2x VSWITCH(Roff=1E8 Ron=1.0 Voff=0 Von=2.5) .ends Figure 54. Boyle Macromodel and Sub-Circuit Copyright © 2003–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLV2460-Q1 TLV2460A-Q1 TLV2461-Q1 TLV2461A-Q1 TLV2462-Q1 TLV2462A-Q1 TLV2463Q1 TLV2463A-Q1 TLV2464A-Q1 27 TLV2460-Q1, TLV2460A-Q1, TLV2461-Q1, TLV2461A-Q1 TLV2462-Q1, TLV2462A-Q1, TLV2463-Q1, TLV2463A-Q1, TLV2464A-Q1 SGLS008G – MARCH 2003 – REVISED FEBRUARY 2018 www.ti.com 9.2 Typical Application C1 33 pF C2 R2 47 kŸ 680 pF C3 R3 8 330 pF VCC 4.7 k R1 V IN U1B 6 7 VCC/2 5 OUT 4 62 NŸ GND Figure 55. Typical Operational Amplifier Application 9.2.1 Design Requirements See Table 2 for design requirements. Table 2. Recommended Design Parameters PARAMETER VALUE Supply voltage 5V Reference voltage 2.5 V Input voltage 2.5 V DC and maximum ripple 40 mV peak-topeak Capacitors Better than X5R Resistors Better than 2% tolerance 9.2.2 Detailed Design Procedure The following section shows the detailed design procedure. See Equation 2 for the type-3 compensation gain. (1 R2C2s) (1 (R1 R3)C3s) Type 3 Compensation Gain = C1C2 R1(C1 C2)s(1 R2 s)(1 R3Cs) C1 C2 (2) Type-3 compensation poles and zeros are shown in the preferred asymptotic graph; see Figure 56. Relocate the compensation poles and zeroes by changing the values of the resistors and capacitors according to the compensation requirement. The operational amplifier cannot achieve the preferred case because of the openloop gain and phase limitation of the amplifier. 28 Submit Documentation Feedback Copyright © 2003–2018, Texas Instruments Incorporated Product Folder Links: TLV2460-Q1 TLV2460A-Q1 TLV2461-Q1 TLV2461A-Q1 TLV2462-Q1 TLV2462A-Q1 TLV2463Q1 TLV2463A-Q1 TLV2464A-Q1 TLV2460-Q1, TLV2460A-Q1, TLV2461-Q1, TLV2461A-Q1 TLV2462-Q1, TLV2462A-Q1, TLV2463-Q1, TLV2463A-Q1, TLV2464A-Q1 www.ti.com SGLS008G – MARCH 2003 – REVISED FEBRUARY 2018 1 2SR1C3 1 2SR2C2 GAIN (dB) 20 log 1 2SR2C1 R2 R1 20 log 1 2SR3C3 R2 R3 FREQUENCY (Hz) +90° PHASE (°) 0° 0° í90° í90° FREQUENCY (Hz) Figure 56. Preferred Asymptotic Graph The poles and zeros are calculated assuming C2 >> C1 and R1 >> R3. This assumption is correct because the C1 and R3 components set the high frequencies. This TLV226x-Q1 device type-3 compensation circuit design boosts the gain and phase for the DC-to-DC converter around 30-KHz resonance frequencies. This corresponds to 1 µH and 22 µF for the output filter. The operational amplifier is configured as type-2 compensation by omitting the C3 capacitor. Type-2 compensates the DC-to-DC converter with an output capacitor with a series resistor ESR; see Equation 3. (1 R2C2s) Type 2 Compensation Gain = C1C2 s) R1(C1 C2) s (1 R2 C1 C2 (3) 9.2.3 Application Curve 50 30 240 Gain (db) 200 Phase (q) 160 20 120 Gain (dB) 40 10 80 0 40 -10 0 -20 -40 -30 -80 -40 -120 -50 -160 -60 10 Frequency: 10 Hz to 1 MHz 100 1k 10k Frequency (Hz) 100k Gain boost = 12 dB around 30 KHz -200 1M D001 Phase boost = 30⁰ around 30 KHz Figure 57. Gain and Phase Plot Copyright © 2003–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLV2460-Q1 TLV2460A-Q1 TLV2461-Q1 TLV2461A-Q1 TLV2462-Q1 TLV2462A-Q1 TLV2463Q1 TLV2463A-Q1 TLV2464A-Q1 29 TLV2460-Q1, TLV2460A-Q1, TLV2461-Q1, TLV2461A-Q1 TLV2462-Q1, TLV2462A-Q1, TLV2463-Q1, TLV2463A-Q1, TLV2464A-Q1 SGLS008G – MARCH 2003 – REVISED FEBRUARY 2018 www.ti.com 10 Power Supply Recommendations The TLV246X-Q1 family of devices operation specification is from 2.7 V to 6 V for a single power supply and ±1.35 V to ±3 V for dual power supplies. TI recommends placing a 0.1-µF bypass capacitor close to the power supply pins to reduce errors coupling in from noisy or high-impedance power supplies. 30 Submit Documentation Feedback Copyright © 2003–2018, Texas Instruments Incorporated Product Folder Links: TLV2460-Q1 TLV2460A-Q1 TLV2461-Q1 TLV2461A-Q1 TLV2462-Q1 TLV2462A-Q1 TLV2463Q1 TLV2463A-Q1 TLV2464A-Q1 TLV2460-Q1, TLV2460A-Q1, TLV2461-Q1, TLV2461A-Q1 TLV2462-Q1, TLV2462A-Q1, TLV2463-Q1, TLV2463A-Q1, TLV2464A-Q1 www.ti.com SGLS008G – MARCH 2003 – REVISED FEBRUARY 2018 11 Layout 11.1 Layout Guidelines To achieve the levels of high performance of the TLV246x-Q1, follow proper printed-circuit board design techniques. A general set of guidelines is shown in the following list. • TI recommends using a ground plane on the board to provide all components with a low inductive ground connection. However, in the areas of the amplifier inputs and output, the ground plane is removed to minimize the stray capacitance. • Use a 6.8-μF tantalum capacitor in parallel with a 0.1-μF ceramic capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers depending on the application, but a 0.1-μF ceramic capacitor must always be used on the supply terminal of every amplifier. In addition, the 0.1-μF capacitor must be placed as close as possible to the supply terminal. As this distance increases, the inductance in the connecting trace makes the capacitor less effective. The designer must strive for distances of less than 0.1 inches between the device power terminals and the ceramic capacitors. • TI does not recommend using sockets. The additional lead inductance in the socket pins often leads to stability problems. For best implementation, solder surface-mount packages directly to the printed circuit board. • Optimum high performance is achieved when stray series inductance is minimized. The circuit layout must be made as compact as possible, which minimizes the length of all trace runs. Take care to pay attention to the inverting input of the amplifier; keep the length as short as possible. This minimizes stray capacitance at the input of the amplifier. • TI recommends using surface mount passive components for high performance amplifier circuits. Stray series inductance is reduced because of the low lead inductance of surface mount components.. The small size of surface-mount components leads to a compact layout, which minimizes stray inductance and capacitance. TI recommends that lead lengths be kept as short as possible if leaded components are used. 11.2 Layout Example Run the input traces as far away from the supply lines as possible Place components close to device and to each other to reduce parasitic errors VS+ RF N/C N/C GND ±IN V+ VIN +IN OUTPUT V± N/C Use a low-ESR, ceramic bypass capacitor RG GND VS± GND VOUT Ground (GND) plane on another layer Use low-ESR, ceramic bypass capacitor Copyright © 2017, Texas Instruments Incorporated Figure 58. Operational Amplifier Board Layout for Noninverting Configuration Copyright © 2003–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLV2460-Q1 TLV2460A-Q1 TLV2461-Q1 TLV2461A-Q1 TLV2462-Q1 TLV2462A-Q1 TLV2463Q1 TLV2463A-Q1 TLV2464A-Q1 31 TLV2460-Q1, TLV2460A-Q1, TLV2461-Q1, TLV2461A-Q1 TLV2462-Q1, TLV2462A-Q1, TLV2463-Q1, TLV2463A-Q1, TLV2464A-Q1 SGLS008G – MARCH 2003 – REVISED FEBRUARY 2018 www.ti.com 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 Related Documentation For related documentation see the following: • Texas Instruments, An audio circuit collection, Part 1 • G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Integrated Circuit Operational Amplifiers,” IEEE Journal of Solid-State Circuits, SC-9, 353 (1974). 12.2 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 3. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY TLV2460-Q1 Click here Click here Click here Click here Click here TLV2461-Q1 Click here Click here Click here Click here Click here TLV2462-Q1 Click here Click here Click here Click here Click here TLV2463-Q1 Click here Click here Click here Click here Click here TLV2460A-Q1 Click here Click here Click here Click here Click here TLV2461A-Q1 Click here Click here Click here Click here Click here TLV2462A-Q1 Click here Click here Click here Click here Click here TLV2463A-Q1 Click here Click here Click here Click here Click here TLV2464A-Q1 Click here Click here Click here Click here Click here 12.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.4 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 12.5 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.6 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 32 Submit Documentation Feedback Copyright © 2003–2018, Texas Instruments Incorporated Product Folder Links: TLV2460-Q1 TLV2460A-Q1 TLV2461-Q1 TLV2461A-Q1 TLV2462-Q1 TLV2462A-Q1 TLV2463Q1 TLV2463A-Q1 TLV2464A-Q1 TLV2460-Q1, TLV2460A-Q1, TLV2461-Q1, TLV2461A-Q1 TLV2462-Q1, TLV2462A-Q1, TLV2463-Q1, TLV2463A-Q1, TLV2464A-Q1 www.ti.com SGLS008G – MARCH 2003 – REVISED FEBRUARY 2018 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright © 2003–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLV2460-Q1 TLV2460A-Q1 TLV2461-Q1 TLV2461A-Q1 TLV2462-Q1 TLV2462A-Q1 TLV2463Q1 TLV2463A-Q1 TLV2464A-Q1 33 PACKAGE OPTION ADDENDUM www.ti.com 6-Aug-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TLV2460AQPWRG4Q1 ACTIVE TSSOP PW 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 2460AQ TLV2461AQPWRG4Q1 ACTIVE TSSOP PW 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 2461AQ TLV2462AQDRQ1 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 2462AQ TLV2462AQPWRG4Q1 ACTIVE TSSOP PW 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 2462AQ TLV2462AQPWRQ1 ACTIVE TSSOP PW 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 2462AQ TLV2462QDGKRQ1 ACTIVE VSSOP DGK 8 2500 RoHS & Green NIPDAU | NIPDAUAG Level-2-260C-1 YEAR -40 to 125 QVM TLV2462QDRG4Q1 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 2462Q1 TLV2462QDRQ1 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 2462Q1 TLV2462QPWRG4Q1 ACTIVE TSSOP PW 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 2462Q1 TLV2463AQPWRG4Q1 ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 2463AQ1 TLV2464AQPWRG4Q1 ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 V2464AQ TLV2464AQPWRQ1 ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 V2464AQ (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
TLV2463AQPWRG4Q1 价格&库存

很抱歉,暂时无法提供与“TLV2463AQPWRG4Q1”相匹配的价格&库存,您可以联系我们找货

免费人工找货