TLV2470,, TLV2471
TLV2472, TLV2473
TLV2474, TLV2475, TLV247xA
®
®
www.ti.com
SLOS232E – JUNE 1999 – REVISED JULY 2007
FAMILY OF 600μA/Ch 2.8MHz RAIL-TO-RAIL INPUT/OUTPUT
HIGH-DRIVE OPERATIONAL AMPLIFIERS WITH SHUTDOWN
FEATURES
•
•
•
•
•
•
•
•
•
DESCRIPTION
CMOS Rail-To-Rail Input/Output
Input Bias Current: 2.5pA
Low Supply Current: 600μA/Channel
Ultra-Low Power Shutdown Mode:
IDD(SHDN): 350nA/ch at 3V
IDD(SHDN): 1000nA/ch at 5V
Gain-Bandwidth Product: 2.8MHz
High Output Drive Capability:
– ±10mA at 180mV
– ±35mA at 500mV
Input Offset Voltage: 250μV (typ)
Supply Voltage Range: 2.7V to 6V
Ultra-Small Packaging
– SOT23-5 or -6 (TLV2470/1)
– MSOP-8 or -10 (TLV2472/3)
The TLV247x is a family of CMOS rail-to-rail input/
output operational amplifiers that establishes a new
performance point for supply current versus ac
performance.
These
devices
consume
just
600μA/channel
while
offering
2.8MHz
of
gain-bandwidth product. Along with increased ac
performance, the amplifier provides high output drive
capability, solving a major shortcoming of older
micropower operational amplifiers. The TLV247x can
swing to within 180mV of each supply rail while
driving a 10mA load. For non-RRO applications, the
TLV247x can supply ±35mA at 500mV off the rail.
Both the inputs and outputs swing rail-to-rail for
increased dynamic range in low-voltage applications.
This performance makes the TLV247x family ideal
for sensor interface, portable medical equipment,
and other data acquisition circuits.
FAMILY PACKAGE TABLE
PACKAGE TYPES
DEVICE
NUMBER OF
CHANNELS
PDIP
SOIC
SOT23
TSSOP
MSOP
TLV2470
1
8
8
6
—
—
Yes
TLV2471
1
8
8
5
—
—
—
TLV2472
2
8
8
—
—
8
—
TLV2473
2
14
14
—
—
10
Yes
TLV2474
4
14
14
—
14
—
—
TLV2475
4
16
16
—
16
—
Yes
SHUTDOWN
UNIVERSAL EVM BOARD
Refer to the EVM Selection
Guide (SLOU060)
A SELECTION OF SINGLE-SUPPLY OPERATIONAL AMPLIFIER PRODUCTS (1)
(1)
DEVICE
VDD
(V)
VIO
(μV)
BW
(MHz)
SLEW RATE
(V/μs)
IDD (per channel)
(μA)
OUTPUT DRIVE
RAIL-TO-RAIL
TLV247X
2.7 – 6.0
250
2.8
1.5
600
±35mA
I/O
TLV245X
2.7 – 6.0
20
0.22
0.11
23
±10mA
I/O
TLV246X
2.7 – 6.0
150
6.4
1.6
550
±90mA
I/O
TLV277X
2.5 – 6.0
360
5.1
10.5
1000
±10mA
O
All specifications measured at 5V.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
Microsim PARTS is a trademark of MicroSim Corporation.
Microsim PSpice is a registered trademark of MicroSim Corporation.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1999–2007, Texas Instruments Incorporated
TLV2470,, TLV2471
TLV2472, TLV2473
TLV2474, TLV2475, TLV247xA
www.ti.com
SLOS232E – JUNE 1999 – REVISED JULY 2007
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
TLV2470 and TLV2471 AVAILABLE OPTIONS (1)
PACKAGED DEVICES
TA
0°C to +70°C
–40°C to +125°C
(1)
(2)
SOT23
SMALL OUTLINE (D) (2)
(DBV)
(2)
SYMBOL
PLASTIC DIP (P)
TLV2470CD
TLV2471CD
TLV2470CDBV
TLV2471CDBV
VAUC
VAVC
TLV2470CP
TLV2471CP
TLV2470ID
TLV2471ID
TLV2470IDBV
TLV2471IDBV
VAUI
VAVI
TLV2470IP
TLV2471IP
TLV2470AID
TLV2471AID
——
——
TLV2470AIP
TLV2471AIP
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (for example,
TLV2470CDR).
TLV2472 AND TLV2473 AVAILABLE OPTIONS (1)
PACKAGED DEVICES
SMALL
OUTLINE
(D) (2)
TA
0°C to +70°C
–40°C to +125°C
(1)
(2)
(3)
MSOP
(DGN)
(2)
MSOP
SYMBOL
(3)
(DGQ)
(2)
SYMBOL (3)
PLASTIC DIP
(N)
PLASTIC DIP
(P)
TLV2472CD
TLV2473CD
TLV2472CDGN
—
xxTIABU
—
—
TLV2473CDGQ
—
xxTIABW
—
TLV2473CN
TLV2472CP
—
TLV2472ID
TLV2473ID
TLV2472IDGN
—
xxTIABV
—
—
TLV2473IDGQ
—
xxTIABX
—
TLV2473IN
TLV2472IP
—
TLV2472AID
TLV2473AID
——
——
——
——
—
TLV2473AIN
TLV2472AIP
—
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (for example,
TLV2472CDR).
xx represents the device date code.
TLV2474 and TLV2475 AVAILABLE OPTIONS (1)
TA
0°C to +70°C
–40°C to +125°C
(1)
(2)
2
PACKAGED DEVICES
SMALL OUTLINE (D) (2)
PLASTIC DIP (N)
TSSOP (PWP) (2)
TLV2474CD
TLV2475CD
TLV2474CN
TLV2475CN
TLV2474CPWP
TLV2475CPWP
TLV2474ID
TLV2475ID
TLV2474IN
TLV2475IN
TLV2474IPWP
TLV2475IPWP
TLV2474AID
TLV2475AID
TLV2474AIN
TLV2475AIN
TLV2474AIPWP
TLV2475AIPWP
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (for example,
TLV2474CDR).
Submit Documentation Feedback
TLV2470,, TLV2471
TLV2472, TLV2473
TLV2474, TLV2475, TLV247xA
www.ti.com
SLOS232E – JUNE 1999 – REVISED JULY 2007
TLV247X PACKAGE PINOUTS
TLV2470
D OR P PACKAGE
(TOP VIEW)
TLV2470
DBV PACKAGE
(TOP VIEW)
OUT
1
6
VDD
GND
2
5
SHDN
IN+
3
4
IN −
TLV2471
D OR P PACKAGE
(TOP VIEW)
NC
IN−
IN+
GND
1
8
2
7
3
6
4
5
NC
VDD
OUT
NC
1
14
2
13
3
12
4
5
6
7
11
10
9
8
1
8
2
7
3
6
4
5
SHDN
VDD
OUT
NC
OUT
1
GND
2
IN+
3
1OUT
1IN−
1IN+
GND
1
8
2
7
3
6
4
5
VDD
2OUT
2IN−
2IN+
TLV2474
D, N, OR PWP PACKAGE
(TOP VIEW)
VDD
2OUT
2IN−
2IN+
NC
2SHDN
NC
1OUT
1IN−
1IN+
VDD
2IN+
2IN−
2OUT
1
14
2
13
3
12
4
11
5
10
6
9
7
8
4OUT
4IN−
4IN+
GND
3IN+
3IN−
3OUT
5
VDD
4
IN −
TLV2473
DGQ PACKAGE
(TOP VIEW)
TLV2472
D, DGN, OR P PACKAGE
(TOP VIEW)
TLV2473
D OR N PACKAGE
(TOP VIEW)
1OUT
1IN−
1IN+
GND
NC
1SHDN
NC
NC
IN−
IN+
GND
TLV2471
DBV PACKAGE
(TOP VIEW)
1OUT
1IN−
1IN+
GND
1SHDN
1
2
3
4
5
10
9
8
7
6
VDD
2OUT
2IN−
2IN+
2SHDN
TLV2475
D, N, OR PWP PACKAGE
(TOP VIEW)
1OUT
1IN−
1IN+
VDD
2IN+
2IN−
2OUT
1/2SHDN
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
4OUT
4IN−
4IN+
GND
3IN+
3IN−
3OUT
3/4SHDN
NC − No internal connection
TYPICAL PIN 1 INDICATORS
Pin 1
Printed or
Molded Dot
Pin 1
Stripe
Pin 1
Beveled Edges
Submit Documentation Feedback
Pin 1
Molded U Shape
3
TLV2470,, TLV2471
TLV2472, TLV2473
TLV2474, TLV2475, TLV247xA
www.ti.com
SLOS232E – JUNE 1999 – REVISED JULY 2007
DESCRIPTION (CONTINUED)
Three members of the family (TLV2470/3/5) offer a shutdown terminal for conserving battery life in portable
applications. During shutdown, the outputs are placed in a high-impedance state and the amplifier consumes
only 350nA/channel. The family is fully specified at 3V and 5V across an expanded industrial temperature range
(–40°C to +125°C). The singles and duals are available in the SOT23 and MSOP packages, while the quads are
available in TSSOP. The TLV2470 offers an amplifier with shutdown functionality all in a SOT23-6 package,
making it perfect for high-density power-sensitive circuits.
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range, unless otherwise noted.
UNIT
Supply voltage, VDD (2)
7V
±VDD
Differential input voltage, VID
Continuous total power dissipation
See Dissipation Rating table
Operating free-air temperature range, TA
C-suffix
0°C to +70°C
I-suffix
–40°C to +125°C
Maximum junction temperature, TJ
+150°C
Storage temperature range, Tstg
–65°C to +150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1)
(2)
+260°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated underrecommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential voltages, are with respect to GND.
DISSIPATION RATING TABLE
PACKAGE
θJC
(°C/W)
θJA
(°C/W)
TA ≤ +25°C
POWER RATING
D (8)
38.3
176
710mW
D (14)
26.9
122.3
1022mW
D (16)
25.7
114.7
1090mW
DBV (5)
55
324.1
385mW
DBV (6)
55
294.3
425mW
2.37W
DGN (8)
4.7
52.7
DGQ (10)
4.7
52.3
2.39W
N (14, 16)
32
78
1600mW
P (8)
41
104
1200mW
PWP (14)
2.07
30.7
4.07W
PWP (16)
2.07
29.7
4.21W
RECOMMENDED OPERATING CONDITIONS
MIN
Supply voltage, VDD
Single supply
Split supply
Common-mode input voltage range, VICR
Operating free-air temperature, TA
Shutdown on/off voltage level (1)
(1)
4
C-suffix
I-suffix
VIH
VIL
Relative to GND.
Submit Documentation Feedback
MAX
2.7
6
±1.35
±3
0
VDD
0
+70
–40
+125
2
0.8
UNIT
V
V
°C
V
TLV2470,, TLV2471
TLV2472, TLV2473
TLV2474, TLV2475, TLV247xA
www.ti.com
SLOS232E – JUNE 1999 – REVISED JULY 2007
ELECTRICAL CHARACTERISTICS
At specified free-air temperature, VDD = 3V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
TLV247x
VIO
Input offset voltage
TLV247xA
αVIO
Temperature coefficient of
input offset voltage
IIO
Input offset current
TA (1)
MIN
+25°C
2400
+25°C
250
Full range
High-level output voltage
25°C
1.5
Low-level output voltage
Full range
300
Full range
100
Full range
300
Sourcing
Short-circuit output current
Sinking
Output current
VO = 0.5V from rail
AVD
Large-signal differential
voltage amplification
VO(PP) = 1V, RL = 10kΩ
ri(d)
Differential input resistance
CIC
Common-mode input
capacitance
zo
Closed-loop output
impedance
CMRR
(1)
50
TLV247xI
VIC = VDD/2
IO
2
TLV247xC
IOL = 10mA
IOS
50
TLV247xI
IOL = 2.5mA
μV
μV/°C
100
VIC = VDD/2
UNIT
1800
Full range
IOH = –10mA
VOL
1600
TLV247xC
IOH = –2.5mA
VOH
2200
0.4
VIC = VDD/2,
VO = VDD/2, RS = 50Ω
Input bias current
MAX
250
Full range
+25°C
IIB
TYP
+25°C
2.85
Full range
2.8
+25°C
2.6
Full range
2.5
+25°C
2.94
V
2.74
0.07
0.15
0.2
0.35
Full range
0.2
+25°C
pA
Full range
V
0.5
+25°C
30
Full range
20
+25°C
30
Full range
20
mA
±22
+25°C
+25°C
90
Full range
88
116
mA
dB
+25°C
1012
Ω
f = 10kHz
+25°C
19.3
pF
f = 10kHz, AV = 10
+25°C
2
Ω
Common-mode rejection ratio VIC = 0V to 3V,
RS = 50Ω
+25°C
61
TLV247xC
Full range
59
TLV247xI
Full range
58
78
dB
Full range is 0°C to +70°C for C-suffix and –40°C to +125°C for I-suffix. If not specified, full range is –40°C to +125°C.
Submit Documentation Feedback
5
TLV2470,, TLV2471
TLV2472, TLV2473
TLV2474, TLV2475, TLV247xA
www.ti.com
SLOS232E – JUNE 1999 – REVISED JULY 2007
ELECTRICAL CHARACTERISTICS (continued)
At specified free-air temperature, VDD = 3V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
VDD = 2.7V to 6V, VIC = VDD/2, No load
kSVR
Supply voltage rejection ratio
(ΔVDD/ΔVIO)
VDD = 3V to 5V, VIC = VDD/2, No load
IDD
Supply current (per channel)
IDD(SHDN)
Supply current in shutdown
mode (TLV2470, TLV2473,
TLV2475) (per channel)
(1)
TA (1)
MIN
TYP
+25°C
74
90
Full range
66
+25°C
77
Full range
68
+25°C
VO = 1.5V, No load
UNIT
dB
92
550
750
Full range
800
+25°C
SHDN = 0V
MAX
350
μA
1500
TLV247xC
Full range
2000
TLV247xI
Full range
4000
nA
Full range is 0°C to +70°C for C-suffix and –40°C to +125°C for I-suffix. If not specified, full range is –40°C to +125°C.
OPERATING CHARACTERISTICS
At specified free-air temperature, VDD = 3V, unless otherwise noted.
PARAMETER
TA (1)
MIN
TYP
+25°C
1.1
1.4
Full range
0.6
SR
Slew rate at unity gain
VO(PP) = 0.8V, CL = 150pF, RL= 10kΩ
Vn
Equivalent input noise
voltage
f = 100Hz
+25°C
28
f = 1kHz
+25°C
15
In
Equivalent input noise
current
f = 1kHz
+25°C
0.405
THD+N
Total harmonic
distortion plus noise
VO(PP) = 2V,
RL= 10kΩ,
f = 1kHz
t(on)
Amplifier turn-on time
t(off)
Amplifier turn-off time
Gain-bandwidth
product
ts
Φm
(1)
(2)
6
TEST CONDITIONS
Settling time
AV = 1
AV = 10
f = 10kHz, RL = 600Ω
V(STEP)PP = 2V,
AV = –1, CL = 10pF,
RL = 10kΩ
0.1%
V(STEP)PP = 2V,
AV = –1, CL = 56pF,
RL = 10kΩ
0.1%
UNIT
V/μs
nV/√Hz
pA/√Hz
0.02%
+25°C
AV = 100
RL= OPEN (2)
MAX
0.1%
0.5%
+25°C
5
μs
+25°C
250
ns
+25°C
2.8
MHz
1.5
0.01%
3.9
+25°C
0.01%
1.6
μs
4
Phase margin
RL = 10kΩ, CL = 1000pF
+25°C
61
°
Gain margin
RL = 10kΩ, CL = 1000pF
+25°C
15
dB
Full range is 0°C to +70°C for C-suffix and –40°C to +125°C for I-suffix. If not specified, full range is –40°C to +125°C.
Disable and enable time are defined as the interval between application of logic signal to SHDN and the point at which the supply
current has reached half its final value.
Submit Documentation Feedback
TLV2470,, TLV2471
TLV2472, TLV2473
TLV2474, TLV2475, TLV247xA
www.ti.com
SLOS232E – JUNE 1999 – REVISED JULY 2007
ELECTRICAL CHARACTERISTICS
At specified free-air temperature, VDD = 5V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
TLV247x
VIO
Input offset voltage
TLV247xA
αVIO
Temperature coefficient of input
offset voltage
IIO
Input offset current
VIC = VDD/2,
VO = VDD/2,
RS = 50Ω
TA (1)
MIN
+25°C
Input bias current
Full range
2400
+25°C
250 1600
Full range
VOH
High-level output voltage
+25°C
1.7
100
TLV247xI
Full range
300
50
Full range
100
TLV247xI
Full range
300
VIC = VDD/2
IOL = 10mA
Sourcing
IOS
2.5
TLV247xC
IOL = 2.5mA
Low-level output voltage
50
Full range
IOH = –10mA
VOL
μV/°C
TLV247xC
VIC = VDD/2
Short-circuit output current
Sinking
μV
2000
0.4
IOH = –2.5mA
UNIT
250 2200
+25°C
IIB
TYP MAX
+25°C
4.85
Full range
4.8
+25°C
4.72
Full range
4.65
+25°C
4.96
V
4.82
0.07
0.15
0.178
0.28
Full range
0.2
+25°C
pA
Full range
V
0.35
+25°C
110
Full range
60
+25°C
90
Full range
60
mA
±35
IO
Output current
VO = 0.5V from rail
AVD
Large-signal differential voltage
amplification
VO(PP) = 3V, RL = 10kΩ
ri(d)
Differential input resistance
+25°C
1012
Ω
CIC
Common-mode input capacitance f = 10kHz
+25°C
18.9
pF
zo
Closed-loop output impedance
+25°C
1.8
Ω
CMRR
kSVR
IDD
(1)
Common-mode rejection ratio
Supply voltage rejection ratio
(ΔVDD/ΔVIO)
Supply current (per channel)
+25°C
f = 10kHz, AV = 10
VIC = 0V to 5V,
RS = 50Ω
+25°C
92
Full range
91
+25°C
64
TLV247xC
Full range
63
TLV247xI
Full range
58
+25°C
74
Full range
66
+25°C
77
Full range
66
VDD = 2.7V to 6V, VIC = VDD/2,
No load
VDD = 3V to 5V, VIC = VDD/2,
No load
VO = 2.5V, No load
+25°C
mA
120
dB
84
dB
90
dB
92
600
Full range
900
1000
μA
Full range is 0°C to +70°C for C-suffix and –40°C to +125°C for I-suffix. If not specified, full range is –40°C to +125°C.
Submit Documentation Feedback
7
TLV2470,, TLV2471
TLV2472, TLV2473
TLV2474, TLV2475, TLV247xA
www.ti.com
SLOS232E – JUNE 1999 – REVISED JULY 2007
ELECTRICAL CHARACTERISTICS (continued)
At specified free-air temperature, VDD = 5V, unless otherwise noted.
PARAMETER
IDD(SHDN)
(1)
TA (1)
TEST CONDITIONS
MIN
TYP MAX
+25°C
Supply current in shutdown mode
(TLV2470, TLV2473, TLV2475)
SHDN = 0V
(per channel)
UNIT
1000 2500
TLV247xC
Full range
3000
TLV247xI
Full range
6000
nA
nA
Full range is 0°C to +70°C for C-suffix and –40°C to +125°C for I-suffix. If not specified, full range is –40°C to +125°C.
OPERATING CHARACTERISTICS
At specified free-air temperature, VDD = 5V, unless otherwise noted.
PARAMETER
TA (1)
MIN
TYP
+25°C
1.1
1.5
Full range
0.7
SR
Slew rate at unity gain
VO(PP) = 2V, CL = 150pF, RL= 10kΩ
Vn
Equivalent input noise
voltage
f = 100Hz
+25°C
28
f = 1kHz
+25°C
15
In
Equivalent input noise
current
f = 1kHz
+25°C
0.39
THD + N
Total harmonic
distortion plus noise
VO(PP) = 4V,
RL= 10kΩ,
f = 1kHz
t(on)
Amplifier turn-on time
t(off)
Amplifier turn-off time
Gain-bandwidth
product
ts
Φm
(1)
(2)
8
TEST CONDITIONS
Settling time
AV = 1
AV = 10
f = 10kHz, RL = 600Ω
V(STEP)PP = 2V,
AV = –1, CL = 10pF,
RL = 10kΩ
0.1%
V(STEP)PP = 2V,
AV = –1, CL = 56pF,
RL = 10kΩ
0.1%
UNIT
V/μs
nV/√Hz
pA/√Hz
0.01%
+25°C
AV = 100
RL= OPEN (2)
MAX
0.05%
0.3%
+25°C
5
μs
+25°C
250
ns
+25°C
2.8
MHz
1.8
0.01%
3.3
+25°C
0.01%
1.7
μs
3
Phase margin
RL = 10kΩ, CL = 1000pF
+25°C
68
°C
Gain margin
RL = 10kΩ, CL = 1000pF
+25°C
23
dB
Full range is 0°C to +70°C for C suffix and –40°C to +125°C for I suffix. If not specified, full range is –40°C to +125°C.
Disable and enable time are defined as the interval between application of logic signal to SHDN and the point at which the supply
current has reached half its final value.
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SLOS232E – JUNE 1999 – REVISED JULY 2007
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
VIO
Input offset voltage
IIB
Input bias current
vs Common-mode input voltage
Figure 1, Figure 2
IIO
Input offset current
vs Free-air temperature
Figure 3, Figure 4
VOH
High-level output voltage
vs High-level output current
Figure 5, Figure 7
VOL
Low-level output voltage
vs Low-level output current
Figure 6, Figure 8
Zo
Output impedance
vs Frequency
Figure 9
IDD
Supply current
vs Supply voltage
Figure 10
PSRR
Power-supply rejection ratio
vs Frequency
Figure 11
CMRR
Common-mode rejection ratio
vs Frequency
Figure 12
Vn
Equivalent input noise voltage
vs Frequency
Figure 13
VO(PP)
Maximum peak-to-peak output voltage
vs Frequency
Figure 14, Figure 15
AVD
Differential voltage gain and phase
vs Frequency
Figure 16, Figure 17
Φm
Phase margin
vs Load capacitance
Figure 18, Figure 19
Gain margin
vs Load capacitance
Figure 20, Figure 21
Gain-bandwidth product
vs Supply voltage
SR
vs Supply voltage
Slew rate
vs Free-air temperature
Figure 22
Figure 23
Figure 24, Figure 25
Crosstalk
vs Frequency
Figure 26
THD+N
Total harmonic distortion + noise
vs Frequency
Figure 27, Figure 28
VO
Large and small signal follower
vs Time
Figure 29–Figure 32
Shutdown pulse response
vs Time
Figure 33, Figure 34
Shutdown forward and reverse isolation
vs Frequency
Figure 35, Figure 36
IDD(SHDN)
Shutdown supply current
vs Supply voltage
Figure 37
IDD(SHDN)
Shutdown supply current
vs Free-air temperature
Figure 38
IDD(SHDN)
Shutdown pulse current
vs Time
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Figure 39, Figure 40
9
TLV2470,, TLV2471
TLV2472, TLV2473
TLV2474, TLV2475, TLV247xA
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SLOS232E – JUNE 1999 – REVISED JULY 2007
TYPICAL CHARACTERISTICS
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
50
600
TA = +25° C
200
0
−200
−400
−600
−800
−0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
VICR − Common-Mode Input Voltage − V
0
−200
−400
−600
30
IIB
20
10
0
IIO
−10
−55 −35 −15 5 25 45 65 85 105 125
TA − Free-Air Temperature − °C
−800
−0.5
0.5
1.5
2.5
3.5
4.5
5.5
VICR − Common-Mode Input Voltage − V
Figure 2.
Figure 3.
INPUT BIAS AND INPUT OFFSET
CURRENTS
vs
FREE-AIR TEMPERATURE
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
40
30
20
IIB
10
0
IIO
−10
−55 −35 −15 5 25 45 65 85 105 125
TA − Free-Air Temperature − °C
VDD = 3V
3.0
2.5
2.0
TA = +125°C
1.5
TA = +85°C
1.0
TA = +25°C
0.5
TA = −40°C
3.0
VOL − Low-Level Output Voltage − V
3.5
V OH − High-Level Output Voltage − V
0.0
VDD = 3V
2.5
TA = +125°C
TA = +85°C
2.0
TA = +25°C
1.5
TA = −40°C
1.0
0.5
0.0
0
10
20
30
40
50
60
IOH − High-Level Output Current − mA
0
10
20
30
40
50
IOL − Low-Level Output Current − mA
Figure 4.
Figure 5.
Figure 6.
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
OUTPUT IMPEDANCE
vs
FREQUENCY
5.0
VDD = 5V
5.0
4.5
4.0
3.5
3.0
2.5
TA = +125°C
2.0
TA = +85°C
1.5
1.0
TA = +25°C
0.5
TA = −40°C
VOL − Low-Level Output Voltage − V
5.5
1000
4.5
TA = +125°C
4.0
TA = +85°C
3.5
Z o − Output Impedance − Ω
I IB − Input Bias Current − pA
40
Figure 1.
VDD = 5V
I IO − Input Offset Current − pA
TA = +25 °C
200
50
V OH − High-Level Output Voltage − V
VDD = 3V
VDD = 5V
400
I IO − Input Offset Current − pA
400
VIO − Input Offset Voltage − µ V
VIO − Input Offset Voltage − µ V
VDD = 3V
I IB − Input Bias Current − pA
600
TA = +25°C
3.0
TA = −40°C
2.5
2.0
1.5
1.0
0
20 40 60 80 100 120 140 160
IOH − High-Level Output Current − mA
Figure 7.
VDD = 3V, 5V
TA = +25°C
100
AV = 100
10
AV = 10
1
AV = 1
0.1
0.5
VDD = 5V
0.0
0.0
10
INPUT BIAS AND INPUT OFFSET
CURRENTS
vs
FREE-AIR TEMPERATURE
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
0
20
40
60
80 100 120 140
IOL − Low-Level Output Current − mA
Figure 8.
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0.01
100
1k
10k
100k
f − Frequency − Hz
Figure 9.
1M
10M
TLV2470,, TLV2471
TLV2472, TLV2473
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SLOS232E – JUNE 1999 – REVISED JULY 2007
TYPICAL CHARACTERISTICS (continued)
POWER-SUPPLY REJECTION
RATIO
vs
FREQUENCY
TA = +125°C
TA = +85°C
0.8
0.7
0.6
TA = +25°C
0.5
TA = −40°C
0.4
0.3
0.2
AV = 1
SHDN = VDD
Per Channel
0.1
0.0
3.0
3.5 4.0 4.5 5.0 5.5
VDD − Supply Voltage − V
100
VDD = 3V, 5V
RF = 5kΩ
RI = 50Ω
TA = +25°C
PSRR+
90
80
PSRR−
70
60
50
40
30
6.0
10
100
1k
10k
100k
f − Frequency − Hz
1M
10M
130
120
110
100
VDD = 5V
90
VIC = 2.5V
80
VDD = 3V
70
VIC = 1.5V
60
50
100
1k
10k
100k
f − Frequency − Hz
1M
10M
Figure 11.
Figure 12.
EQUIVALENT NOISE VOLTAGE
vs
FREQUENCY
MAXIMUM PEAK-TO-PEAK
OUTPUT VOLTAGE
vs
FREQUENCY
MAXIMUM PEAK-TO-PEAK
OUTPUT VOLTAGE
vs
FREQUENCY
VDD = 3V, 5V
AV = 10
VIN = VDD/2
TA = +25°C
70
60
50
40
30
20
10
0
100
1k
10k
f − Frequency − Hz
100k
THD+N ≤ 2.0%
RL = 10kΩ
TA = +25°C
5.0
4.5
VO(PP) = 5V
4.0
3.5
3.0
2.5
VO(PP) = 3V
2.0
1.5
1.0
0.5
0.0
10k
100k
f − Frequency − Hz
Figure 13.
DIFFERENTIAL VOLTAGE GAIN
AND PHASE
vs
FREQUENCY
THD+N ≤ 2.0%
RL = 600Ω
TA = +25°C
5.0
4.5
VO(PP) = 5V
4.0
3.5
3.0
2.5
2.0
VO(PP) = 3V
1.5
1.0
0.5
0.0
10k
100k
f − Frequency − Hz
VDD = ±3
RL = 600Ω
CL = 0
TA = +25°C
80
45
−45
40
−90
20
−135
0
−180
−20
−225
1k
10k
100k
1M
Frequency − Hz
10M
−270
100M
Figure 15.
100
0
60
1M
DIFFERENTIAL VOLTAGE GAIN
AND PHASE
vs
FREQUENCY
AVD − Differential Voltage Gain − dB
100
−40
100
1M
5.5
Figure 14.
Phase − °
10
5.5
VDD = ±5
RL = 600Ω
CL = 0
TA = +25°C
80
45
0
60
−45
40
−90
20
−135
0
−180
−20
−225
−40
100
1k
Figure 16.
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10k
100k
1M
Frequency − Hz
10M
Phase − °
80
V O(PP) − Maximum Peak-To-Peak Output Voltage − V
Figure 10.
AVD − Differential Voltage Gain − dB
V n − Equivalent Input Noise Voltage − nV/
Hz
2.5
V O(PP) − Maximum Peak-To-Peak Output Voltage − V
I DD − Supply Current − mA
0.9
PSRR − Power Supply Rejection Ratio − dB
1.0
COMMON-MODE REJECTION RATIO
vs
FREQUENCY
CMRR − Common-Mode Rejection Ratio − dB
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
−270
100M
Figure 17.
11
TLV2470,, TLV2471
TLV2472, TLV2473
TLV2474, TLV2475, TLV247xA
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SLOS232E – JUNE 1999 – REVISED JULY 2007
TYPICAL CHARACTERISTICS (continued)
PHASE MARGIN
vs
LOAD CAPACITANCE
60
RNULL = 50
80
RNULL = 100
50
RNULL = 20
40
30
20
10
0
100
RNULL = 0
1k
10k
CL − Load Capacitance − pF
40
30
10
15
RNULL = 20
RNULL = 20
25
RNULL = 50
RNULL = 0
1k
10k
CL − Load Capacitance − pF
30
100
100k
1k
10k
CL − Load Capacitance − pF
Figure 19.
Figure 20.
GAIN MARGIN
vs
LOAD CAPACITANCE
GAIN-BANDWIDTH PRODUCT
vs
SUPPLY VOLTAGE
SLEW RATE
vs
SUPPLY VOLTAGE
4.0
10
RNULL = 20
20
RNULL = 50
RNULL = 100
VDD = 5V
RL = 10kΩ
TA = +25°C
30
1k
10k
CL − Load Capacitance − pF
1.8
RL = 10kΩ
3.5
3.0
RL = 600Ω
2.5
2.0
1.5
CL = 11pF
f = 10kHz
TA = +25°C
1.0
SR−
1.6
SR+
1.4
1.2
1.0
0.8
0.6
VO(PP) = 1.5V
AV = −1
RL = 10kΩ
CL = 150pF
0.4
0.5
0.2
0.0
100k
0.0
2.5
3.0
3.5 4.0 4.5 5.0 5.5
VDD − Supply Voltage − V
6.0
2.5
3.0
3.5 4.0 4.5 5.0 5.5
VDD − Supply Voltage − V
Figure 22.
SLEW RATE
vs
FREE-AIR TEMPERATURE
Figure 23.
SLEW RATE
vs
FREE-AIR TEMPERATURE
2.00
2.00
1.75
1.75
SR+
SR − Slew Rate − V/µs
SR − Slew Rate − V/µs
SR−
1.50
SR−
1.25
1.00
0.75
0.50
0.25
100k
2.0
Figure 21.
VDD = 3V
RL = 10kΩ
CL = 150pF
AV = −1
1.50
SR+
1.25
1.00
0.75
0.50
0.25
0.00
−55 −35 −15 5 25 45 65 85 105 125
TA − Free-Air Temperature − °C
VDD = 5V
RL = 10kΩ
CL = 150pF
AV = −1
0.00
−55 −35 −15 5 25 45 65 85 105 125
TA − Free-Air Temperature − °C
Figure 24.
12
RNULL = 100
20
Figure 18.
Gain-Bandwidth Product − MHz
Gain Margin − dB
50
0
100
100k
RNULL = 0
35
100
RNULL = 0
RNULL = 100
10
5
25
5
70
60
VDD = 3V
RL = 10kΩ
TA = +25°C
RNULL = 50
20
0
15
0
VDD = 5V
RL = 10kΩ
TA = +25°C
See Figure 42
90
Gain Margin − dB
70
100
VDD = 3V
RL = 10kΩ
TA = +25°C
See Figure 42
GAIN MARGIN
vs
LOAD CAPACITANCE
SR − Slew Rate − V/µs
φ m − Phase Margin − °
80
φ m − Phase Margin − °
90
PHASE MARGIN
vs
LOAD CAPACITANCE
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Figure 25.
6.0
TLV2470,, TLV2471
TLV2472, TLV2473
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SLOS232E – JUNE 1999 – REVISED JULY 2007
TYPICAL CHARACTERISTICS (continued)
THD+N−Total Harmonic Distortion + Noise
0
VDD = 3V, 5V
AV = 1
RL = 600Ω
VI(PP) = 2V
All Channels
−20
Crosstalk − dB
−40
−60
−80
−100
−120
−140
−160
10
100
10 k
1k
f − Frequency − Hz
100 k
1
TOTAL HARMONIC
DISTORTION PLUS NOISE
vs
FREQUENCY
THD+N−Total Harmonic Distortion + Noise
TOTAL HARMONIC
DISTORTION PLUS NOISE
vs
FREQUENCY
CROSSTALK
vs
FREQUENCY
AV = 100
AV = 10
0.1
AV = 1
0.01
VDD = 3V
RL = 10kΩ
V0 = 2VPP
TA = +25°C
0.001
10
100
1k
10k
100k
1
0.1
AV = 100
AV = 10
AV = 1
0.01
VDD = 5V
RL = 10kΩ
V0 = 4VPP
TA = +25°C
0.001
10
100
1k
Figure 27.
Figure 28.
LARGE-SIGNAL FOLLOWER
PULSE RESPONSE
vs
TIME
LARGE-SIGNAL FOLLOWER
PULSE RESPONSE
vs
TIME
SMALL-SIGNAL FOLLOWER
PULSE RESPONSE
vs
TIME
VI (50mV/DIV)
VO (1V/DIV)
VDD = 3V
RL = 10kΩ
CL = 8pF
f = 85kHz
TA = +25°C
1
2
3
4 5 6
t − Time − µs
7
8
9
10
VO (1V/DIV)
VDD = 5V
RL = 10kΩ
CL = 8pF
f = 85kHz
TA = +25°C
0
1
2
3
4 5
6
t − Time − µs
VDD = 3V
RL = 10kΩ
CL = 8pF
f = 1MHz
TA = +25°C
V O − Output Voltage
V O − Output Voltage
V O − Output Voltage
VI (2V/DIV)
VO (50mV/DIV)
7
8
9
0
10
100
200
300
t − Time − µs
400
500
Figure 29.
Figure 30.
Figure 31.
SMALL-SIGNAL FOLLOWER
PULSE RESPONSE
vs
TIME
SHUTDOWN (ON AND OFF)
PULSE RESPONSE
vs
TIME
SHUTDOWN (ON AND OFF)
PULSE RESPONSE
vs
TIME
VSHDN (2V/DIV)
VI (50mV/DIV)
VO (50mV/DIV)
100
200
300
t − Time − µs
Figure 32.
400
500
RL = 600Ω
RL = 10kΩ
VO (500mV/DIV)
VDD = 3V
CL = 8pF
TA = +25°C
0
2
V O − Output Voltage
VSHDN (2V/DIV)
V O − Output Voltage
V O − Output Voltage
VDD = 5V
RL = 10kΩ
CL = 8pF
f = 1MHz
TA = +25°C
0
100k
Figure 26.
VI (2V/DIV)
0
10k
f − Frequency − Hz
f − Frequency − Hz
RL = 600Ω
RL = 10kΩ
VO (1V/DIV)
VDD = 5V
CL = 8pF
TA = +25°C
4 6
8
t − Time − µs
10 12
14 16
Figure 33.
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0
2
4
6 8 10
t − Time − µs
12 14
16 18
Figure 34.
13
TLV2470,, TLV2471
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SLOS232E – JUNE 1999 – REVISED JULY 2007
TYPICAL CHARACTERISTICS (continued)
100
80
RL = 600Ω
60
RL = 10kΩ
40
20
0
1k
10k
100k
f − Frequency − Hz
1M
VDD = 3V, 5V
RL = 10kΩ
CL = 0pF
AV = 1
VIN = 0.1VPP, 1.5VPP, 3VPP
20
100
1k
10k
100k
f − Frequency − Hz
1M
2.0
1.8
1.6
1.4
TA = +125°C
1.2
TA = +85°C
1.0
TA = +25°C
0.8
TA = −40°C
0.6
0.4
Shutdown On
RL = OPEN
VI = VDD/2
0.2
0.0
10M
2.5
3.0
3.5 4.0 4.5 5.0 5.5
VDD − Supply Voltage − V
6.0
Figure 35.
Figure 36.
Figure 37.
SHUTDOWN SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
SHUTDOWN PULSE CURRENT
vs
TIME
SHUTDOWN PULSE CURRENT
vs
TIME
VDD = 5V
0.8
0.6
VDD = 3V
0.0
−55 −35 −15 5 25 45 65 85 105 125
TA − Free-Air Temperature − °C
Figure 38.
2.00
3
1.75
2
1.50
1
1.25
0
IDD RL = 10kΩ
1.00
−1
0.75
−2
0.50
−3
IDD RL = 600Ω
−4
0.25
−5
VDD = 3V
CL = 8pF
TA = +25°C
0
−0.25
0.2
4
−6
−0.50
0
4
8
12 16 20
t − Time − µs
24
28 30
Figure 39.
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Shutdown Pulse − V
1.0
I DD − Supply Current − mA
1.2
Shutdown Pulse
1.75
I DD − Supply Current − mA
2.00
SD MODE Channel 1 and 2
AV = 1
RL = OPEN
VIN = VDD/2
1.4
0.4
RL = 600Ω
RL = 10kΩ
40
10M
1.6
I DD − Shutdown Supply Current − µ A
80
0
100
14
100
60
SHUTDOWN SUPPLY CURRENT
vs
SUPPLY VOLTAGE
I DD(SHDN)− Shutdown Supply Current − µA
120
VDD = 3V, 5V
CL = 0pF
AV = 1
VI(PP) = 0.1V, 1.5V, 3V
Shutdown Forward Isolation - dB
Shutdown Forward Isolation - dB
120
SHUTDOWN REVERSE ISOLATION
vs
FREQUENCY
6
4
Shutdown Pulse
1.50
2
1.25
0
1.00
IDD RL = 10kΩ
−2
0.75
0.50
−4
IDD RL = 600Ω
−6
0.25
−7
−0.25
−8
−0.50
−8
VDD = 5V
CL = 8pF
TA = +25°C
0
Shutdown Pulse − V
SHUTDOWN FORWARD
ISOLATION
vs
FREQUENCY
−10
−12
0
4
8
12 16
t − Time − µs
20
Figure 40.
24 28 30
TLV2470,, TLV2471
TLV2472, TLV2473
TLV2474, TLV2475, TLV247xA
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SLOS232E – JUNE 1999 – REVISED JULY 2007
PARAMETER MEASUREMENT INFORMATION
RNULL
_
+
RL
CL
Figure 41.
APPLICATION INFORMATION
DRIVING A CAPACITIVE LOAD
When the amplifier is configured in this manner, capacitive loading directly on the output will decrease the
device phase margin leading to high-frequency ringing or oscillations. Therefore, for capacitive loads of greater
than 10pF, it is recommended that a resistor (RNULL) be placed in series with the output of the amplifier, as
shown in Figure 42. A minimum value of 20Ω should work well for most applications.
RF
RG
RNULL
_
Input
Output
+
CLOAD
Figure 42. Driving a Capacitive Load
OFFSET VOLTAGE
The output offset voltage (VOO) is the sum of the input offset voltage (VIO) and both input bias currents (IIB) times
the corresponding gains. The following schematic and formula can be used to calculate the output offset voltage:
RF
IIB−
RG
+
VI
RS
−
VO
+
IIB+
ǒ ǒ ǓǓ
VOO + VIO 1 )
RF
RG
ǒ ǒ ǓǓ
" IIB) RS 1 )
RF
RG
" IIB* RF
Figure 43. Output Offset Voltage Model
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SLOS232E – JUNE 1999 – REVISED JULY 2007
APPLICATION INFORMATION (continued)
GENERAL CONFIGURATIONS
When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often
required. The simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifier
(see Figure 44).
RG
RF
–
VO
+
VI
R1
C1
f
V
O +
V
I
ǒ
R
1)
R
F
G
Ǔǒ
–3dB
+
1
2pR1C1
Ǔ
1
1 ) sR1C1
Figure 44. Single-Pole Low-Pass Filter
If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter can be used for this
task. For best results, the amplifier should have a bandwidth that is eight to ten times the filter frequency
bandwidth. Failure to do this can result in phase shift of the amplifier.
C1
+
_
VI
R1
R1 = R2 = R
C1 = C2 = C
Q = Peaking Factor
(Butterworth Q = 0.707)
R2
f
C2
RG
RF
–3dB
RG =
+
(
1
2pRC
RF
1
2–
Q
)
Figure 45. 2-Pole Low-Pass Sallen-Key Filter
SHUTDOWN FUNCTION
Three members of the TLV247x family (TLV2470/3/5) have a shutdown terminal for conserving battery life in
portable applications. When the shutdown terminal is tied low, the supply current is reduced to 350nA/channel,
the amplifier is disabled, and the outputs are placed in a high impedance mode. To enable the amplifier, the
shutdown terminal can either be left floating or pulled high. When the shutdown terminal is left floating, care
should be taken to ensure that parasitic leakage current at the shutdown terminal does not inadvertently place
the operational amplifier into shutdown. The shutdown terminal threshold is always referenced to VDD/2.
Therefore, when operating the device with split supply voltages (e.g., ±2.5V), the shutdown terminal needs to be
pulled to VDD– (not GND) to disable the operational amplifier.
The amplifier output with a shutdown pulse is shown in Figure 33 and Figure 34. The amplifier is powered with a
single 5V supply and configured as a noninverting configuration with a gain of 5. The amplifier turn-on and
turn-off times are measured from the 50% point of the shutdown pulse to the 50% point of the output waveform.
The times for the single, dual, and quad versions are listed in the data tables.
16
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TLV2474, TLV2475, TLV247xA
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SLOS232E – JUNE 1999 – REVISED JULY 2007
APPLICATION INFORMATION (continued)
Figure 35 and Figure 36 show the amplifier forward and reverse isolation in shutdown. The operational amplifier
is powered by ±1.35V supplies and configured as a voltage follower (AV= 1). The isolation performance is plotted
across frequency using 0.1VPP, 1.5VPP, and 2.5VPP input signals. During normal operation, the amplifier would
not be able to handle a 2.5VPP input signal with a supply voltage of ±1.35V since it exceeds the common-mode
input voltage range (VICR). However, this curve illustrates that the amplifier remains in shutdown even under a
worst case scenario.
CIRCUIT LAYOUT CONSIDERATIONS
To achieve the levels of high performance of the TLV247x, follow proper printed circuit board (PCB) design
techniques. A general set of guidelines is given below:
• Ground planes—It is highly recommended that a ground plane be used on the board to provide all
components with a low inductive ground connection. However, in the areas of the amplifier inputs and output,
the ground plane can be removed to minimize the stray capacitance.
• Proper power supply decoupling—Use a 6.8μF tantalum capacitor in parallel with a 0.1μF ceramic capacitor
on each supply terminal. It may be possible to share the tantalum among several amplifiers depending on the
application, but a 0.1μF ceramic capacitor should always be used on the supply terminal of every amplifier. In
addition, the 0.1μF capacitor should be placed as close as possible to the supply terminal. As this distance
increases, the inductance in the connecting trace makes the capacitor less effective. The designer should
strive for distances of less than 0.1 inches between the device power terminals and the ceramic capacitors.
• Sockets—Sockets can be used but are not recommended. The additional lead inductance in the socket pins
will often lead to stability problems. Surface-mount packages soldered directly to the printed-circuit board is
the best implementation.
• Short trace runs/compact part placements—Optimum high performance is achieved when stray series
inductance has been minimized. To realize this, the circuit layout should be made as compact as possible,
thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting input of the
amplifier. Its length should be kept as short as possible. This will help to minimize stray capacitance at the
input of the amplifier.
• Surface-mount passive components—Using surface-mount passive components is recommended for
high-performance amplifier circuits for several reasons. First, because of the extremely low lead inductance
of surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small
size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray
inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be kept
as short as possible.
GENERAL PowerPAD™ DESIGN CONSIDERATIONS
The TLV247x is available in a thermally-enhanced PowerPAD family of packages. These packages are
constructed using a downset leadframe upon which the die is mounted (see Figure 46a and Figure 46b). This
arrangement results in the lead frame being exposed as a thermal pad on the underside of the package (see
Figure 46c). Because this thermal pad has direct thermal contact with the die, excellent thermal performance
can be achieved by providing a good thermal path away from the thermal pad.
The PowerPAD package allows for both assembly and thermal management in one manufacturing operation.
During the surface-mount solder operation (when the leads are being soldered), the thermal pad must be
soldered to a copper area underneath the package. Through the use of thermal paths within this copper area,
heat can be conducted away from the package into either a ground plane or other heat dissipating device.
Soldering the PowerPAD to the PCB is always recommended, even with applications that have low power
dissipation. It provides the necessary mechanical and thermal connection between the lead frame die pad and
the PCB.
The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of
surface mount with previously awkward mechanical methods of heatsinking.
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17
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TLV2472, TLV2473
TLV2474, TLV2475, TLV247xA
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SLOS232E – JUNE 1999 – REVISED JULY 2007
APPLICATION INFORMATION (continued)
DIE
Side View (a)
Thermal
Pad
DIE
End View (b)
Bottom View (c)
The thermal pad is electrically isolated from all terminals in the package.
Figure 46. Views of Thermally Enhanced DGN Package
Although there are many ways to properly heatsink the PowerPAD package, the following steps illustrate the
recommended approach.
1. The thermal pad must be connected to the most negative supply voltage on the device (GND pin).
2. Prepare the PCB with a top side etch pattern as illustrated in the thermal land pattern mechanical drawing
at the end of this document. There should be etch for the leads as well as etch for the thermal pad.
3. Place holes in the area of the thermal pad as illustrated in the land pattern mechanical drawing at the end
of this document. These holes should be 13mils (0.013 inches or 0.3302mm) in diameter. Keep them
small so that solder wicking through the holes is not a problem during reflow.
4. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. This
helps dissipate the heat generated by the TLV247x IC. These additional vias may be larger than the 13mil
diameter vias directly under the thermal pad. They can be larger because they are not in the thermal pad
area to be soldered so that wicking is not a problem.
5. Connect all holes to the internal ground plane that is at the same voltage potential as the device GND pin.
6. When connecting these holes to the ground plane, do not use the typical web or spoke via connection
methodology. Web connections have a high thermal resistance connection that is useful for slowing the
heat transfer during soldering operations. This makes the soldering of vias that have plane connections
easier. In this application, however, low thermal resistance is desired for the most efficient heat transfer.
Therefore, the holes under the TLV247x PowerPAD package should make their connection to the internal
ground plane with a complete connection around the entire circumference of the plated-through hole.
7. The top-side solder mask should leave the terminals of the package and the thermal pad area with its
holes exposed. The bottom-side solder mask should cover the holes of the thermal pad area. This
prevents solder from being pulled away from the thermal pad area during the reflow process.
8. Apply solder paste to the exposed thermal pad area and all of the IC terminals.
9. With these preparatory steps in place, the TLV247x IC is simply placed in position and run through the
solder reflow operation as any standard surface-mount component. This results in a part that is properly
installed.
For a given θJA, the maximum power dissipation is shown in Figure 47 and is calculated by Equation 1:
PD +
ǒT
MAX
* TA
q JA
Ǔ
(1)
Where:
•
•
•
•
18
PD = Maximum power dissipation of TLV247x IC (watts)
TMAX = Absolute maximum junction temperature (+150°C)
TA = Free-ambient air temperature (°C)
θJA = θJC + θCA
– θJC = Thermal coefficient from junction to case
– θCA = Thermal coefficient from case to ambient air (°C/W)
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TLV2470,, TLV2471
TLV2472, TLV2473
TLV2474, TLV2475, TLV247xA
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SLOS232E – JUNE 1999 – REVISED JULY 2007
APPLICATION INFORMATION (continued)
MAXIMUM POWER DISSIPATION
vs
FREE-AIR TEMPERATURE
7
Maximum Power Dissipation − W
6
5
4
3
2
PWP Package
Low-K Test PCB
θJA = 29.7°C/W
DGN Package
Low-K Test PCB
θJA = 52.3°C/W
PDIP Package
Low-K Test PCB
θJA = 104°C/W
TJ = +150°C
SOT-23 Package
Low-K Test PCB
θJA = 324°C/W
SOIC Package
Low-K Test PCB
θJA = 176°C/W
1
0
−55 −40 −25 −10 5 20 35 50 65 80 95 110 125
TA − Free-Air Temperature − °C
Results are obtained with no air flow and using JEDEC Standard Low-K test PCB.
Figure 47. Maximum Power Dissipation vs Free-Air Temperature
The next consideration is the package constraints. The two sources of heat within an amplifier are quiescent
power and output power. The designer should never forget about the quiescent heat generated within the
device, especially multi-amplifier devices. Because these devices have linear output stages (Class A-B), most of
the heat dissipation is at low output voltages with high output currents. Figure 48 to Figure 53 show this effect,
along with the quiescent heat, with an ambient air temperature of +70°C and +125°C. When using VDD = 3V,
there is generally not a heat problem with an ambient air temperature of +70°C. But, when using VDD = 5V, the
package is severely limited in the amount of heat it can dissipate. The other key factor when looking at these
graphs is how the devices are mounted on the PCB. The PowerPAD devices are extremely useful for heat
dissipation. But the device should always be soldered to a copper plane to fully use the heat dissipation
properties of the PowerPAD. The SOIC package, on the other hand, is highly dependent on how it is mounted
on the PCB. As more trace and copper area is placed around the device,θJA decreases and the heat dissipation
capability increases. The currents and voltages shown in these graphs are for the total package. For the dual or
quad amplifier packages, the sum of the RMS output currents and voltages should be used to choose the proper
package.
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19
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TLV2472, TLV2473
TLV2474, TLV2475, TLV247xA
www.ti.com
SLOS232E – JUNE 1999 – REVISED JULY 2007
APPLICATION INFORMATION (continued)
TLV2470, TLV2471(1)
MAXIMUM RMS OUTPUT CURRENT
vs
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
180
160
140
Packages With
θJA ≤ 110°C/W
at TA = +125°C
or
θJA ≤ 355°C/W
at TA = +70°C
C
120
100
B
A
80
60
Safe Operating Area
40
VDD = ±3V
20 TJ = +150°C
TA = +125°C
0
0
0.25
0.50
0.75
1.00
1.25
| VO | − RMS Output Voltage − V
Maximum Output
Current Limit Line
160
140
G
C
120
B
100
A
80
Packages With
θJA ≤ 210°C/W
at TA = +70°C
60
40
VDD = ± 5V
20 T = +150°C
J
TA = +125°C
0
0
0.5
Safe Operating Area
1.0
1.5
2.0
| VO | − RMS Output Voltage − V
1.50
2.5
Figure 48.
Figure 49.
TLV2472, TLV2473(1)
MAXIMUM RMS OUTPUT CURRENT
vs
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
TLV2472, TLV2473(1)
MAXIMUM RMS OUTPUT CURRENT
vs
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
180
| IO | − Maximum RMS Output Current − mA
| IO | − Maximum RMS Output Current − mA
Maximum Output
Current Limit Line
180
Maximum Output
Current Limit Line
160
140
G
H
C
120
Packages With
θJA ≤ 55°C/W
at TA = +125°C
or
θJA ≤ 178°C/W
at TA = +70°C
D
100
80
60
40
VDD = ± 3V
TJ = +150°C
TA = +125°C
20
| IO | − Maximum RMS Output Current − mA
| IO | − Maximum RMS Output Current − mA
180
TLV2470, TLV2471(1)
MAXIMUM RMS OUTPUT CURRENT
vs
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
Safe Operating Area
0
Maximum Output
Current Limit Line
160
140
F
120
G
100
H
D
80
C
60
40
VDD = ± 5V
TJ = +150°C
TA = +125°C
20
0
0
0.25
0.50
0.75
1.00
1.25
| VO | − RMS Output Voltage − V
1.50
Packages With
θJA ≤ 105°C/W
at TA = +70°C
0
Figure 50.
Safe Operating Area
0.5
1.0
1.5
2.0
| VO | − RMS Output Voltage − V
2.5
Figure 51.
Note: (1) A - SOT23 (5); B - SOT23 (6); C - SOIC (8); D - SOIC (14); E - SOIC (16); F - MSOP PP (8); G - PDIP
(8); H - PDIP (14): I - PDIP (16); J - TSSOP PP (14/16)
20
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TLV2470,, TLV2471
TLV2472, TLV2473
TLV2474, TLV2475, TLV247xA
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SLOS232E – JUNE 1999 – REVISED JULY 2007
APPLICATION INFORMATION (continued)
TLV2474, TLV2475(1)
MAXIMUM RMS OUTPUT CURRENT
vs
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
180
Maximum Output
Current Limit Line
160
140
| IO | − Maximum RMS Output Current − mA
| IO | − Maximum RMS Output Current − mA
180
J
120
H and I
100
E
Packages With
θJA ≤ 88°C/W
D
at TA = +70°C
80
60
40
VDD = ±3V
TJ = +150°C
TA = +125°C
20
0
0
TLV2474, TLV2475(1)
MAXIMUM RMS OUTPUT CURRENT
vs
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
Safe Operating Area
Maximum Output
Current Limit Line
160
140
J
120
100
H and I
80
VDD = ±5V
TJ = +150°C
TA = +125°C
60
0.50
0.75
1.00
1.25
| VO | − RMS Output Voltage − V
1.50
D
40
20
Safe Operating Area
0
0.25
E
0
Figure 52.
0.5
Packages With
θJA ≤ 52°C/W
at TA = +70°C
1.0
1.5
2.0
| VO | − RMS Output Voltage − V
2.5
Figure 53.
NOTE: (1) A - SOT23 (5); B - SOT23 (6); C - SOIC (8); D - SOIC (14); E - SOIC (16); F - MSOP PP (8); G PDIP (8); H - PDIP (14): I - PDIP (16); J - TSSOP PP (14/16)
Submit Documentation Feedback
21
TLV2470,, TLV2471
TLV2472, TLV2473
TLV2474, TLV2475, TLV247xA
www.ti.com
SLOS232E – JUNE 1999 – REVISED JULY 2007
APPLICATION INFORMATION (continued)
MACROMODEL INFORMATION
Macromodel information provided was derived using Microsim PARTS™, the model generation software used
with Microsim PSpice®. The Boyle macromodel and subcircuit in Figure 54 are generated using the TLV247x
typical electrical and operating characteristics at TA = 25°C. Using this information, output simulations of the
following key parameters can be generated to a tolerance of 20% (in most cases):
•
•
•
•
•
•
•
•
•
•
•
•
Maximum positive output voltage swing
Maximum negative output voltage swing
Slew rate
Quiescent power dissipation
Input bias current
Open-loop voltage amplification
Unity-gain frequency
Common-mode rejection ratio
Phase margin
DC output resistance
AC output resistance
Short-circuit output current limit
3
VDD
99
+
rd1
rp
rd2
rss
egnd
css
11
IN+
+
D
D
ga
gcm
ro1
ioff
S
OUT
dp
iss
90
vlp
–
ve
+ 54
* TLV247x operational amplifier ”macromodel” subcircuit
* created using Parts release 8.0 on 4/27/99 at 14:31
* Parts is a MicroSim product.
*
* connections: non–inverting input
*
| inverting input
*
| | positive power supply
*
| | | negative power supply
*
| | | | output
*
| ||||
.subckt TLV247x 1 2 3 4 5
*
c1
11
12
1.1094E–12
c2
6
7
5.5000E–12
css
10
99
556.53E–15
dc
5
53
dy
de
54
5
dy
dlp
90
91
dx
dln
92
90
dx
dp
4
3
dx
egnd
99
0
poly(2) (3,0) (4,0) 0 .5 .5
fb
7
99
poly(5) vb vc ve vlp vln 0
+ 39.614E6 –1E3 1E3 40E6 –40E6
ga
6
0
11
12 79.828E–6
gcm
0
6
10
99 32.483E–9
dln
+
hlim
–
+
dc
–
dlp
91
10
4
–
8
vb
–
53
GND
vlim
6
+
–
G
S
c2
r2
9
vc
G
IN–
7
+
12
1
2
ro2
fb
–
c1
5
92
–
vln
+
de
iss
hlim
ioff
j1
j2
r2
rd1
rd2
ro1
ro2
rp
rss
vb
vc
ve
vlim
vlp
vln
.model
.model
.model
.model
.ends
*$
10
90
0
11
12
6
3
3
8
7
3
10
9
3
54
7
91
0
dx
dy
jx1
jx2
4
dc
10.714E–6
0
vlim 1K
6
dc
75E–9
2
10 jx1
1
10 jx2
9
100.00E3
11
12.527E3
12
12.527E3
5
10
99
10
4
3.8023E3
99
18.667E6
0
dc 0
53
dc .842
4
dc .842
8
dc 0
0
dc 110
92
dc 110
D(Is=800.00E–18)
D(Is=800.00E–18 Rs=1m Cjo=10p)
NJF(Is=1.0825E–12 Beta=594.78E–06 + Vto=–1)
NJF(Is=1.0825E–12 Beta=594.78E–06 + Vto=–1)
G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, "Macromodeling of Integrated Circuit Operational
Amplifiers, ”IEEE Journal of Solid-State Circuits, SC-9, 353 (1974).
Figure 54. Boyle Macromodel and Subcircuit
22
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PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TLV2470AID
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
2470AI
Samples
TLV2470AIP
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 125
TLV2470AI
Samples
TLV2470CD
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
2470C
Samples
TLV2470CDBVR
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
VAUC
Samples
TLV2470CDBVT
ACTIVE
SOT-23
DBV
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
VAUC
Samples
TLV2470CDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
2470C
Samples
TLV2470CP
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
TLV2470C
Samples
TLV2470ID
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
2470I
Samples
TLV2470IDBVR
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
VAUI
Samples
TLV2470IDBVT
ACTIVE
SOT-23
DBV
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
VAUI
Samples
TLV2470IDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
2470I
Samples
TLV2471AID
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
2471AI
Samples
TLV2471AIDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
2471AI
Samples
TLV2471AIP
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 125
TLV2471AI
Samples
TLV2471CD
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
2471C
Samples
TLV2471CDBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
VAVC
Samples
TLV2471CDBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
VAVC
Samples
TLV2471CDBVTG4
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
VAVC
Samples
TLV2471CDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
2471C
Samples
TLV2471CP
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
TLV2471C
Samples
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TLV2471ID
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
2471I
Samples
TLV2471IDBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
VAVI
Samples
TLV2471IDBVRG4
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
VAVI
Samples
TLV2471IDBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
VAVI
Samples
TLV2471IDBVTG4
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
VAVI
Samples
TLV2471IDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
2471I
Samples
TLV2471IP
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 125
TLV2471I
Samples
TLV2472AID
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
2472AI
Samples
TLV2472AIDG4
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
2472AI
Samples
TLV2472AIDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
2472AI
Samples
TLV2472AIP
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 125
TLV2472AI
Samples
TLV2472CD
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
2472C
Samples
TLV2472CDGN
ACTIVE
HVSSOP
DGN
8
80
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
ABU
Samples
TLV2472CDGNR
ACTIVE
HVSSOP
DGN
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
ABU
Samples
TLV2472CDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
2472C
Samples
TLV2472CP
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
TLV2472CP
Samples
TLV2472ID
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
2472I
Samples
TLV2472IDGN
ACTIVE
HVSSOP
DGN
8
80
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
ABV
Samples
TLV2472IDGNG4
ACTIVE
HVSSOP
DGN
8
80
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
ABV
Samples
TLV2472IDGNR
ACTIVE
HVSSOP
DGN
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
ABV
Samples
TLV2472IDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
2472I
Samples
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TLV2472IP
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 125
TLV2472IP
Samples
TLV2473AID
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TLV2473AI
Samples
TLV2473AIDR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TLV2473AI
Samples
TLV2473AIN
ACTIVE
PDIP
N
14
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 125
TLV2473AIN
Samples
TLV2473CD
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TLV2473C
Samples
TLV2473CDGQR
ACTIVE
HVSSOP
DGQ
10
2500
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
0 to 70
ABW
Samples
TLV2473CDR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TLV2473C
Samples
TLV2473IDGQR
ACTIVE
HVSSOP
DGQ
10
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
ABX
Samples
TLV2473IN
ACTIVE
PDIP
N
14
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 125
TLV2473IN
Samples
TLV2474AID
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
2474AI
Samples
TLV2474AIDR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
2474AI
Samples
TLV2474AIN
ACTIVE
PDIP
N
14
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 125
TLV2474AI
Samples
TLV2474AIPWP
ACTIVE
HTSSOP
PWP
14
90
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
2474AI
Samples
TLV2474AIPWPR
ACTIVE
HTSSOP
PWP
14
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
2474AI
Samples
TLV2474AIPWR
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
2474AI
Samples
TLV2474CD
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
2474C
Samples
TLV2474CDR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
2474C
Samples
TLV2474CN
ACTIVE
PDIP
N
14
25
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
TLV2474C
Samples
TLV2474CPWP
ACTIVE
HTSSOP
PWP
14
90
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
0 to 70
2474C
Samples
TLV2474CPWPR
ACTIVE
HTSSOP
PWP
14
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
0 to 70
2474C
Samples
TLV2474ID
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
2474I
Samples
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TLV2474IDR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
2474I
Samples
TLV2474IN
ACTIVE
PDIP
N
14
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 125
TLV2474I
Samples
TLV2474IPWP
ACTIVE
HTSSOP
PWP
14
90
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
2474I
Samples
TLV2474IPWPR
ACTIVE
HTSSOP
PWP
14
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
2474I
Samples
TLV2475AIDR
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TLV2475AI
Samples
TLV2475AIPWP
ACTIVE
HTSSOP
PWP
16
90
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
2475AI
Samples
TLV2475AIPWPR
ACTIVE
HTSSOP
PWP
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
2475AI
Samples
TLV2475CDR
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TLV2475C
Samples
TLV2475CN
ACTIVE
PDIP
N
16
25
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
TLV2475C
Samples
TLV2475CPWPR
ACTIVE
HTSSOP
PWP
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
0 to 70
2475C
Samples
TLV2475IPWPR
ACTIVE
HTSSOP
PWP
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
2475I
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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