TLV2542IDGKG4

TLV2541, TLV2542, TLV2545 2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN SLAS245E −MARCH 2000 − REVISED APRIL 2010 D Maximum Throughput . . . 140/200 KSPS D Built-In Conversion Clock D INL/DNL: ±1 LSB Max, SINAD: 72 dB, D D D D SFDR: 85 dB, fi = 20 kHz SPI/DSP-Compatible Serial Interface Single Supply: 2.7 Vdc to 5.5 Vdc Rail-to-Rail Analog Input With 500 kHz BW Three Options Available: − TLV2541: Single Channel Input TOP VIEW TLV2541 CS VREF GND AIN D D − TLV2542: Dual Channels With Autosweep − TLV2545: Single Channel With Pseudo-Differential Input Low Power With Autopower Down − Operating Current: 1 mA at 2.7 V, 1.5 mA at 5 V Autopower Down: 2 μA at 2.7 V, 5 μA at 5 V Small 8-Pin MSOP and SOIC Packages TOP VIEW TLV2542 1 8 2 7 3 6 4 5 SDO FS VDD SCLK CS VREF GND AIN0 TOP VIEW TLV2545 1 8 2 7 3 6 4 5 SDO SCLK VDD AIN1 CS VREF GND AIN(+) 1 8 2 7 3 6 4 5 SDO SCLK VDD AIN(−) description The TLV2541, TLV2542, and TLV2545 are a family of high performance, 12-bit, low power, miniature, CMOS analog-to-digital converters (ADC). The TLV254x family operates from a single 2.7-V to 5.5-V supply. Devices are available with single, dual, or single pseudo-differential inputs. Each device has a chip select (CS), serial clock (SCLK), and serial data output (SDO) that provides a direct 3-wire interface to the serial port of most popular host microprocessors (SPI interface). When interfaced with a TMS320t DSP, a frame sync signal (FS) can be used to indicate the start of a serial data frame on CS for all devices or FS for the TLV2541. TLV2541, TLV2542, and TLV2545 are designed to operate with very low power consumption. The power saving feature is further enhanced with an autopower-down mode. This product family features a high-speed serial link to modern host processors with SCLK up to 20 MHz. The maximum SCLK frequency is dependent upon the mode of operation (see Table 1). The TLV254x family uses the built-in oscillator as the conversion clock, providing a 3.5-μs conversion time. AVAILABLE OPTIONS PACKAGED DEVICES TA 8-MSOP (DGK) 8-SOIC (D) TLV2541CDGK (AGZ) 0°C 70°C 0 C to 70 C TLV2542CDGK (AHB) TLV2545CDGK (AHD) −40°C 40 C to 85°C 85 C TLV2541IDGK (AHA) TLV2541ID TLV2542IDGK (AHC) TLV2542ID TLV2545IDGK (AHE) TLV2545ID Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. TMS320 is a trademark of Texas Instruments. Copyright © 2000 − 2003, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 1 TLV2541, TLV2542, TLV2545 2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN SLAS245E −MARCH 2000 − REVISED APRIL 2010 functional block diagram TLV2541 TLV2542 VDD VDD VREF VREF AIN0 S/H AIN OSC SCLK CS FS LOW POWER 12-BIT SAR ADC Mux AIN1 SDO Conversion Clock OSC CONTROL LOGIC SCLK CS GND Conversion Clock CONTROL LOGIC GND TLV2545 VDD VREF AIN (+) OSC SCLK CS LOW POWER 12-BIT SAR ADC S/H AIN (−) Conversion Clock CONTROL LOGIC GND 2 LOW POWER SAR ADC S/H • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • SDO SDO TLV2541, TLV2542, TLV2545 2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN SLAS245E −MARCH 2000 − REVISED APRIL 2010 Terminal Functions TLV2541 TERMINAL NAME NO. I/O DESCRIPTION AIN 4 I Analog input channel CS 1 I Chip select. A high-to-low transition on the CS input removes SDO from 3-state within a maximum setup time. CS can be used as the FS pin when a dedicated DSP serial port is used. FS 7 I DSP frame sync input. Indication of the start of a serial data frame. Tie this terminal to VDD if not used. GND 3 I Ground return for the internal circuitry. Unless otherwise noted, all voltage measurements are with respect to GND. SCLK 5 I Output serial clock. This terminal receives the serial SCLK from the host processor. SDO 8 O The 3-state serial output for the A/D conversion result. SDO is kept in the high-impedance state until CS falling edge or FS rising edge, whichever occurs first. The output format is MSB first. When FS is not used (FS = 1 at the falling edge of CS): The MSB is presented to the SDO pin after CS falling edge and output data is valid on the first falling edge of SCLK. When CS and FS are both used (FS = 0 at the falling edge of CS): The MSB is presented to the SDO pin after the falling edge of CS. When CS is tied/held low, the MSB is presented on SDO after the rising FS. Output data is valid on the first falling edge of SCLK. (This is typically used with an active FS from a DSP using a dedicated serial port.) VDD 6 I Positive supply voltage VREF 2 I External reference input TLV2542/45 TERMINAL I/O DESCRIPTION NAME NO. AIN0 /AIN(+) 4 I Analog input channel 0 for TLV2542—Positive input for TLV2545. AIN1/AIN (−) 5 I Analog input channel 1 for TLV2542—Inverted input for TLV2545. CS 1 I Chip select. A high-to-low transition on CS removes SDO from 3-state within a maximum delay time. This pin can be connected to the frame sync of a DSP using a dedicated serial port. GND 3 I Ground return for the internal circuitry. Unless otherwise noted, all voltage measurements are with respect to GND. SCLK 7 I Output serial clock. This terminal receives the serial SCLK from the host processor. SDO 8 O The 3-state serial output for the A/D conversion result. SDO is kept in the high-impedance state when CS is high and presents output data after the CS falling edge until the LSB is presented. The output format is MSB first. SDO returns to the Hi-Z state after the 16th SCLK. Output data is valid on the falling SCLK edge. VDD 6 I Positive supply voltage VREF 2 I External reference input detailed description The TLV2541, TLV2542, and TLV2545 are successive approximation (SAR) ADCs utilizing a charge redistribution DAC. Figure 1 shows a simplified version of the ADC. The sampling capacitor acquires the signal on AIN during the sampling period. When the conversion process starts, the SAR control logic and charge redistribution DAC are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator into a balanced condition. When the comparator is balanced, the conversion is complete and the ADC output code is generated. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 3 TLV2541, TLV2542, TLV2545 2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN SLAS245E −MARCH 2000 − REVISED APRIL 2010 detailed description (continued) Charge Redistribution DAC _ AIN Control Logic + ADC Code GND/AIN(−) Figure 1. Simplified SAR Circuit serial interface OUTPUT DATA FORMAT MSB LSB D15−D4 D3−D0 Conversion result (OD11−OD0) Don’t care The output data format is binary (unipolar straight binary). binary Zero-scale code = 000h, Vcode = GND Full-scale code = FFFh, Vcode = VREF − 1 LSB pseudo-differential inputs The TLV2545 operates in pseudo-differential mode. The inverted input is available on pin 5. It can have a maximum input ripple of ±0.2 V. This is normally used for ground noise rejection. control and timing start of the cycle Each cycle may be started by either CS, FS, or a combination of both. The internal state machine requires one SCLK high-to-low transition to determine the state of these control signals so internal blocks can be powered up in an active cycle. Special care to SPI mode is necessary. Make sure there is at least one SCLK whenever CS (pin 1) is high to ensure proper operation. TLV2541 D Control via CS ( FS = 1 at the falling edge of CS)—The falling edge of CS is the start of the cycle. The MSB should be read on the first falling SCLK edge after CS is low. Output data changes on the rising edge of SCLK. This is typically used for a microcontroller with an SPI interface, although it can also be used for a DSP. The microcontroller SPI interface should be programmed for CPOL = 0 (serial clock referenced to ground) and CPHA = 1 (data is valid on the falling edge of the serial clock). At least one falling edge transition on SCLK is needed whenever CS is brought high. D Control via FS (CS is tied/held low)—The MSB is presented after the rising edge of FS. The falling edge of FS is the start of the cycle. The MSB should be read on the first falling edge of SCLK after FS is low. This is the typical configuration when the ADC is the only device on the DSP serial port. 4 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • TLV2541, TLV2542, TLV2545 2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN SLAS245E −MARCH 2000 − REVISED APRIL 2010 control and timing (continued) D Control via both CS and FS—The MSB is presented after the falling edge of CS. The falling edge of FS is the start of the sampling cycle. The MSB should be read on the first falling SCLK edge after FS is low. Output data changes on the rising edge of SCLK. This configuration is typically used for multiple devices connected to a TMS320 DSP. TLV2542/5 All control is provided using CS (pin 1) on the TLV2542 and TLV2545. The cycle is started on the falling edge transition provided by either a CS signal from an SPI microcontroller or FS signal from a TMS320 DSP. Timing is similar to the TLV2541, with control via CS only. TLV2542 channel MUX reset cycle The TLV2542 uses CS to reset the analog input multiplexer. A short active CS cycle (4 to 7 SCLKs) resets the MUX to AIN0. When the CS cycle time is greater than 7 SCLKs in duration, as in the case for a complete conversion cycle (CS is low for 16 SCLKs plus maximum conversion time), the MUX toggles to the next channel (see Figure 4 for timing). One dummy conversion cycle is recommended after power up before attempting to reset the MUX. sampling The converter sample time is 12 SCLKs in duration, beginning on the fifth SCLK received after the converter has received a high-to-low CS transition (or a high-to-low FS transition for the TLV2541). conversion The TLV2541, TLV2542, and TLV2545 complete conversions in the following manner. The conversion is started after the 16th SCLK falling edge and takes 3.5 μs to complete. Enough time (for conversion) should be allowed before a rising CS or FS edge so that no conversion is terminated prematurely. TLV2542 input channel selection is toggled on each rising CS edge. The MUX channel can be reset to AIN0 via CS as described in the earlier section and in Figure 4. The input is sampled for 12 SCLKs, converted, and the result is presented on SDO during the next cycle. Care should also be taken to allow enough time between samples to avoid prematurely terminating the cycle, which occurs on a rising CS transition if the conversion is not complete. The SDO data presented during a cycle is the result of the conversion of the sample taken during the previous cycle. timing diagrams/conversion cycles 1 2 3 4 5 6 7 12 13 14 15 16 1 SCLK CS FS ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ t(sample) SDO OD11 OD10 OD9 OD8 OD7 OD6 OD5 tc t(powerdown) OD0 Figure 2. TLV2541 Timing: Control via CS (FS = 1) • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 5 TLV2541, TLV2542, TLV2545 2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN SLAS245E −MARCH 2000 − REVISED APRIL 2010 timing diagrams/conversion cycles (continued) 1 2 3 4 5 6 12 13 14 15 16 1 SCLK CS FS ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ t(sample) SDO OD11 OD10 OD9 OD8 OD7 OD6 t(powerdown) tc OD0 Figure 3. TLV2541 Timing: Control via CS and FS or FS Only 1 2 3 4 5 1 4 12 16 1 4 12 16 SCLK >8 SCLKs, MUX Toggles to AIN1