SLAS198E − FEBRUARY 1999 − REVISED JUNE 2003
D Maximum Throughput 200-KSPS
D Built-In Reference, Conversion Clock and
8× FIFO
D Differential/Integral Nonlinearity Error:
D
D
D
±1 LSB
Signal-to-Noise and Distortion Ratio:
70 dB, fi = 12-kHz
Spurious Free Dynamic Range: 75 dB,
fi = 12- kHz
SPI (CPOL = 0, CPHA = 0)/DSP-Compatible
Serial Interfaces With SCLK up to 20-MHz
TLV2548
DW OR PW PACKAGE
(TOP VIEW)
SDO
SDI
SCLK
EOC/(INT)
VCC
A0
A1
A2
A3
A4
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
CS
REFP
REFM
FS
PWDN
GND
CSTART
A7
A6
A5
D Single Wide Range Supply 2.7 Vdc to
D
D
D
D
D
5.5 Vdc
Analog Input Range 0-V to Supply Voltage
With 500 kHz BW
Hardware Controlled and Programmable
Sampling Period
Low Operating Current (1.0-mA at 3.3-V,
1.1-mA at 5.5-V With External Ref
Power Down: Software/Hardware
Power-Down Mode (1 µA Max, Ext Ref),
Autopower-Down Mode (1 µA, Ext Ref)
Programmable Auto-Channel Sweep
TLV2544
D OR PW PACKAGE
(TOP VIEW)
SDO
SDI
SCLK
EOC/(INT)
VCC
A0
A1
A2
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
CS
REFP
REFM
FS
PWDN
GND
CSTART
A3
description
The TLV2548 and TLV2544 are a family of high performance, 12-bit low power, 3.86 µs, CMOS analog-to-digital
converters (ADC) which operate from a single 2.7-V to 5.5-V power supply. These devices have three digital
inputs and a 3-state output [chip select (CS), serial input-output clock (SCLK), serial data input (SDI), and serial
data output (SDO)] that provide a direct 4-wire interface to the serial port of most popular host microprocessors
(SPI interface). When interfaced with a TI DSP, a frame sync (FS) signal is used to indicate the start of a serial
data frame.
In addition to a high-speed A/D converter and versatile control capability, these devices have an on-chip analog
multiplexer that can select any analog inputs or one of three internal self-test voltages. The sample-and-hold
function is automatically started after the fourth SCLK edge (normal sampling) or can be controlled by a special
pin, CSTART, to extend the sampling period (extended sampling). The normal sampling period can also be
programmed as short (12 SCLKs) or as long (24 SCLKs) to accommodate faster SCLK operation popular
among high-performance signal processors. The TLV2548 and TLV2544 are designed to operate with very low
power consumption. The power-saving feature is further enhanced with software/hardware/autopower-down
modes and programmable conversion speeds. The conversion clock (OSC) and reference are built-in. The
converter can use the external SCLK as the source of the conversion clock to achieve higher (up to 2.8 µs when
a 20 MHz SCLK is used) conversion speed. Two different internal reference voltages are available. An optional
external reference can also be used to achieve maximum flexibility.
The TLV2544C and the TLV2548C are characterized for operation from 0°C to 70°C. The TLV2544I and the
TLV2548I are characterized for operation from − 40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1999 − 2003, Texas Instruments Incorporated
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functional block diagram
VCC
REFP
REFM
2544
A0
X
A1
X
A2
X
A3
X
FIFO
12 Bit × 8
Analog
MUX
2548
A0
A1
A2
A3
A4
A5
A6
A7
4/2 V
Reference
Low Power
12-BIT
SAR ADC
S/H
OSC
INT
Command
Decode
Conversion
Clock
EXT
CFR
SDI
M
U
X
SDO
CMR (4 MSBs) DIV
SCLK
CS
FS
CSTART
PWDN
Control Logic
EOC/(INT)
GND
AVAILABLE OPTIONS
PACKAGED DEVICES
TA
2
20-TSSOP
(PW)
20-SOIC
(DW)
16-SOIC
(D)
16-TSSOP
(PW)
20-CDIP
(J)
20-LCCC
(FK)
0°C to 70°C
TLV2548CPW
TLV2548CDW
TLV2544CD
TLV2544CPW
—
—
−40°C to 85°C
TLV2548IPW
TLV2548IDW
TLV2544ID
TLV2544IPW
—
—
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Terminal Functions
TERMINAL
NO.
I/O
DESCRIPTION
6
7
8
9
10
11
12
13
I
Analog signal inputs. The analog inputs are applied to these terminals and are internally
multiplexed. The driving source impedance should be less than or equal to 1 kΩ.
16
20
I
Chip select. A high-to-low transition on the CS input resets the internal 4-bit counter, enables SDI,
and removes SDO from 3-state within a maximum setup time. SDI is disabled within a setup time
after the 4-bit counter counts to 16 (clock edges) or a low-to-high transition of CS whichever
happens first.
NOTE: CS falling and rising edges need to happen when SCLK is low for a microprocessor interface
such as SPI.
CSTART
10
14
I
This terminal controls the start of sampling of the analog input from a selected multiplex channel.
Sampling time starts with the falling edge of CSTART and ends with the rising edge of CSTART as
long as CS is held high. In mode 01, select cycle, CSTART can be issued as soon as CHANNEL
is selected which means the fifth SCLK during the select cycle, but the effective sampling time is
not started until CS goes to high. The rising edge of CSTART (when CS = 1) also starts the
conversion. Tie this terminal to VCC if not used.
EOC/(INT)
4
4
O
End of conversion or interrupt to host processor.
[PROGRAMMED AS EOC]: This output goes from a high-to-low logic level at the end of the
sampling period and remains low until the conversion is complete and data are ready for transfer.
EOC is used in conversion mode 00 only.
NAME
TLV2544
TLV2548
6
7
8
9
CS
A0
A1
A2
A3
A0
A1
A2
A3
A4
A5
A6
A7
For a source impedance greater than 1 kΩ, use the asynchronous conversion start signal CSTART
(CSTART low time controls the sampling period) or program long sampling period to increase the
sampling time.
[PROGRAMMED AS INT]: This pin can also be programmed as an interrupt output signal to the host
processor. The falling edge of INT indicates data are ready for output. The following CS↓ or FS
clears INT.
FS
13
17
I
DSP frame sync input. Indication of the start of a serial data frame in or out of the device. If FS
remains low after the falling edge of CS, SDI is not enabled until an active FS is presented. A
high-to-low transition on the FS input resets the internal 4-bit counter and enables SDI within a
maximum setup time. SDI is disabled within a setup time after the 4-bit counter counts to 16 (clock
edges) or a low-to-high transition of CS whichever happens first.
GND
11
15
I
Ground return for the internal circuitry. Unless otherwise noted, all voltage measurements are with
respect to GND.
PWDN
12
16
I
Both analog and reference circuits are powered down when this pin is at logic zero. The device can
be restarted by active CS, FS or CSTART after this pin is pulled back to logic one.
SCLK
3
3
I
Input serial clock. This terminal receives the serial SCLK from the host processor. SCLK is used to
clock the input SDI to the input register. When programmed, it may also be used as the source of
the conversion clock.
NOTE: This device supports CPOL (clock polarity) = 0, which is SCLK returns to zero when idling
for SPI compatible interface.
SDI
2
2
I
Serial data input. The input data is presented with the MSB (D15) first. The first 4-bit MSBs,
D(15−12) are decoded as one of the 16 commands (12 only for the TLV2544). The configure write
commands require an additional 12 bits of data.
When FS is not used (FS =1), the first MSB (D15) is expected after the falling edge of CS and is
latched in on the rising edges of SCLK (after CS↓).
When FS is used (typical with an active FS from a DSP) the first MSB (D15) is expected after the
falling edge of FS and is latched in on the falling edges of SCLK.
SDI is disabled within a setup time after the 4-bit counter counts to 16 (clock edges) or a low-to-high
transition of CS whichever happens first.
Tie this terminal to VCC if not used. See the date code information section, item (1).
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Terminal Functions (Continued)
TERMINAL
NAME
SDO
NO.
TLV2544
TLV2548
1
1
I/O
DESCRIPTION
O
The 3-state serial output for the A/D conversion result. SDO is kept in the high-impedance state
when CS is high and after the CS falling edge and until the MSB is presented. The output format
is MSB first.
When FS is not used (FS = 1 at the falling edge of CS), the MSB is presented to the SDO pin after
the CS falling edge, and successive data are available at the rising edge of SCLK and changed on
the falling edge.
When FS is used (FS = 0 at the falling edge of CS), the MSB is presented to SDO after the falling
edge of CS and FS = 0 is detected. Successive data are available at the falling edge of SCLK and
changed on the rising edge. (This is typically used with an active FS from a DSP.)
For conversion and FIFO read cycles, the first 12 bits are result from previous conversion (data)
followed by 4 don’t care bits. The first four bits from SDO for CFR read cycles should be ignored.
The register content is in the last 12 bits. SDO is 3-state (float) after the 16th bit. See the date code
information section, item (2).
REFM
14
18
I
External reference input or internal reference decoupling. Tie this pin to analog ground if internal
reference is used.
REFP
15
19
I
External reference input or internal reference decoupling. (Shunt capacitors of 10 µF and 0.1 µF
between REFP and REFM.) The maximum input voltage range is determined by the difference
between the voltage applied to this terminal and the REFM terminal when an external reference is
used.
VCC
5
5
I
Positive supply voltage
detailed description
analog inputs and internal test voltages
The 4/8 analog inputs and three internal test inputs are selected by the analog multiplexer depending on the
command entered. The input multiplexer is a break-before-make type to reduce input-to-input noise injection
resulting from channel switching.
converter
The TLV2544/48 uses a 12-bit successive approximation ADC utilizing a charge redistribution DAC. Figure 1
shows a simplified version of the ADC.
The sampling capacitor acquires the signal on Ain during the sampling period. When the conversion process
starts, the SAR control logic and charge redistribution DAC are used to add and subtract fixed amounts of charge
from the sampling capacitor to bring the comparator into a balanced condition. When the comparator is
balanced, the conversion is complete and the ADC output code is generated.
4
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detailed description (continued)
Charge
Redistribution
DAC
_
Ain
+
Control
Logic
ADC Code
REFM
Figure 1. Simplified Model of the Successive-Approximation System
serial interface
INPUT DATA FORMAT
MSB
LSB
D15−D12
D11−D0
Command ID[15:12]
Configuration data field ID[11:0]
Input data is binary. All trailing blanks can be filled with zeros.
OUTPUT DATA FORMAT READ CFR/FIFO READ
MSB
LSB
D15−D12
Don’t care
D11−D0
Register content or FIFO content OD[11:0]
OUTPUT DATA FORMAT CONVERSION
MSB
LSB
D15−D4
D3−D0
Conversion result OD[11:0]
Don’t care
The output data format is binary (unipolar straight binary).
binary
Zero scale code = 000h, Vcode = VREFM
Full scale code = FFFh, Vcode = VREFP − 1 LSB
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control and timing
power up and initialization requirements
D Determine processor type by writing A000h to the TLV2544/48 (CS must be toggled)
D Configure the device (CS must make a high-to-low transition, then can be held low if in DSP mode; i.e.,
active FS.)
The first conversion after power up or resuming from power down is not valid.
start of the cycle:
D When FS is not used (FS = 1 at the falling edge of CS), the falling edge of CS is the start of the cycle.
D When FS is used (FS is an active signal from a DSP), the falling edge of FS is the start of the cycle.
first 4-MSBs: the command register (CMR)
The TLV2544/TLV2548 have a 4-bit command set (see Table 1) plus a 12-bit configuration data field. Most of
the commands require only the first 4 MSBs, i.e., without the 12-bit data field.
The valid commands are listed in Table 1.
Table 1. TLV2544/TLV2548 Command Set
SDI D(15−12) BINARY
TLV2548 COMMAND
TLV2544 COMMAND
0000b
0h
Select analog input channel 0
Select analog input channel 0
0001b
1h
Select analog input channel 1
N/A
0010b
2h
Select analog input channel 2
Select analog input channel 1
0011b
3h
Select analog input channel 3
N/A
0100b
4h
Select analog input channel 4
Select analog input channel 2
0101b
5h
Select analog input channel 5
N/A
0110b
6h
Select analog input channel 6
Select analog input channel 3
0111b
7h
Select analog input channel 7
N/A
1000b
8h
SW power down (analog + reference)
1001b
9h
Read CFR register data shown as SDO D(11−0)
1010b
Ah plus data
1011b
Bh
Select test, voltage = (REFP+REFM)/2
1100b
Ch
Select test, voltage = REFM
1101b
Dh
Select test, voltage = REFP
1110b
Eh
FIFO read, FIFO contents shown as SDO D(15−4), D(3−0) = 0000
Write CFR followed by 12-bit data, e.g., 0A100h means external reference,
short sampling, SCLK/4, single shot, INT
1111b
Fh plus data Reserved
NOTE: The status of the CFR can be read with a read CFR command when the device is programmed
for one-shot conversion mode (CFR D[6,5] = 00).
6
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control and timing (continued)
configuration
Configuration data is stored in one 12-bit configuration register (CFR) (see Table 2 for CFR bit definitions). Once
configured after first power up, the information is retained in the H/W or S/W power down state. When the device
is being configured, a write CFR cycle is issued by the host processor. This is a 16-bit write. If the SCLK stops
after the first 8 bits are entered, then the next eight bits can be taken after the SCLK is resumed.
Table 2. TLV2544/TLV2548 Configuration Register (CFR) Bit Definitions
BIT
DEFINITION
D11
Reference select
0: External
1: Internal (Tie REFM to analog ground if the Internal reference is selected.)
D10
Internal reference voltage select
0: Internal ref = 4 V
1: internal ref = 2 V
D9
Sample period select
0: Short sampling 12 SCLKs (1x sampling time)
1: Long sampling 24 SCLKs (2x sampling time)
D(8,7)
Conversion clock source select
00: Conversion clock = internal OSC
01: Conversion clock = SCLK
10: Conversion clock = SCLK/4
11: Conversion clock = SCLK/2
D(6,5)
Conversion mode select
00: Single shot mode [FIFO not used, D(1,0) has no effect.]
01: Repeat mode
10: Sweep mode
11: Repeat sweep mode
D(4,3)†
TLV2548
Sweep auto sequence select
00: 0−1−2−3−4−5−6−7
01: 0−2−4−6−0−2−4−6
10: 0−0−2−2−4−4−6−6
11: 0−2−0−2−0−2−0−2
TLV2544
Sweep auto sequence select
00: N/A
01: 0−1−2−3−0−1−2−3
10: 0−0−1−1−2−2−3−3
11: 0−1−0−1−0−1−0−1
D2
EOC/INT − pin function select
0: Pin used as INT
1: Pin used as EOC
D(1,0)
FIFO trigger level (sweep sequence length)
00: Full (INT generated after FIFO level 7 filled)
01: 3/4 (INT generated after FIFO level 5 filled)
10: 1/2 (INT generated after FIFO level 3 filled)
11: 1/4 (INT generated after FIFO level 1 filled)
† These bits only take effect in conversion modes 10 and 11.
sampling
The sampling period starts after the first 4 input data are shifted in if they are decoded as one of the conversion
commands. These are select analog input (channel 0 through 7) and select test (channel 1 through 3).
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normal sampling
When the converter is using normal sampling, the sampling period is programmable. It can be 12 SCLKs (short
sampling) or 24 SCLKs (long sampling). Long sampling helps when SCLK is faster than 10 MHz or when input
source resistance is high.
extended sampling
CSTART − An asynchronous (to the SCLK) signal, via dedicated hardware pin, CSTART, can be used in order
to have total control of the sampling period and the start of a conversion. This extended sampling is user-defined
and is totally independent of SCLK. While CS is high, the falling edge of CSTART is the start of the sampling
period and is controlled by the low time of CSTART. The minimum low time for CSTART should be at least equal
to the minimum t(SAMPLE). In a select cycle used in mode 01 (REPEAT MODE), CSTART can be started as soon
as the channel is selected (after the fifth SCLK). In this case the sampling period is not started until CS has
become inactive. Therefore the nonoverlapped CSTART low time must meet the minimum sampling time
requirement. The low-to-high transition of CSTART terminates the sampling period and starts the conversion
period. The conversion clock can also be configured to use either internal OSC or external SCLK. This function
is useful for an application that requires:
D The use of an extended sampling period to accommodate different input source impedance
D The use of a faster I/O clock on the serial port but not enough sampling time is available due to the fixed
number of SCLKs. This could be due to a high input source impedance or due to higher MUX ON resistance
at lower supply voltage.
Once the conversion is complete, the processor can initiate a read cycle by using either the read FIFO command
to read the conversion result or by simply selecting the next channel number for conversion. Since the device
has a valid conversion result in the output buffer, the conversion result is simply presented at the serial data
output. To completely get out of the extended sampling mode, CS must be toggled twice from a high-to-low
transition while CSTART is high. The read cycle mentioned above followed by another configuration cycle of
the ADC qualifies this condition and successfully puts the ADC back to its normal sampling mode. This can be
viewed in Figure 9.
Table 3. Sample and Convert Conditions
CSTART
CONDITIONS
SAMPLE
CS = 1
(see Figures
11 and 18)
No sampling clock (SCLK) required. Sampling
period is totally controlled by the low time of CSTART.
The high-to-low transition of CSTART (when CS=1)
starts the sampling of the analog input signal. The low
time of CSTART dictates the sampling period. The
low-to-high transition of CSTART ends sampling
period and begins the conversion cycle. (Note: this
trigger only works when internal reference is selected
for conversion modes 01, 10, and 11.)
CS
CSTART = 1
FS = 1
FS
CSTART = 1
CS = 0
8
CONVERT
1) If the internal clock OSC is selected a maximum
SCLK is required. Sampling period is programmable
conversion time of 3.86 µs can be achieved.
under normal sampling. When programmed to sample 2) If external SCLK is selected, conversion time is
under short sampling, 12 SCLKs are generated to
tconv = 14 × DIV/f(SCLK), where DIV can be 1, 2, or
complete sampling period. 24 SCLKs are generated
4.
when programmed for long sampling. A command set
to configure the device requires 4 SCLKs thereby extending to 16 or 28 SCLKs respectively before conversion takes place. (Note: Because the ADC only
bypasses a valid channel select command, the user
can use select channel 0, 0000b, as the SDI input
when either CS or FS is used as trigger for conversion.
The ADC responds to commands such as SW powerdown, 1000b.)
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TLV2544/TLV2548 conversion modes
The TLV2544 and TLV2548 have four different conversion modes (mode 00, 01, 10, 11). The operation of each
mode is slightly different, depending on how the converter performs the sampling and which host interface is
used. The trigger for a conversion can be an active CSTART (extended sampling), CS (normal sampling, SPI
interface), or FS (normal sampling, TMS320 DSP interface). When FS is used as the trigger, CS can be held
active, i.e. CS does not need to be toggled through the trigger sequence. SDI can be one of the channel select
commands, such as SELECT CHANNEL 0. Different types of triggers should not be mixed throughout the repeat
and sweep operations. When CSTART is used as the trigger, the conversion starts on the rising edge of
CSTART. The minimum low time for CSTART is equal to t(SAMPLE). If an active CS or FS is used as the trigger,
the conversion is started after the 16th or 28th SCLK edge. Enough time (for conversion) should be allowed
between consecutive triggers so that no conversion is terminated prematurely.
one shot mode (mode 00)
One shot mode (mode 00) does not use the FIFO, and the EOC is generated as the conversion is in progress
(or INT is generated after the conversion is done).
repeat mode (mode 01)
Repeat mode (mode 01) uses the FIFO. This mode setup requires configuration cycle and channel select cycle.
Once the programmed FIFO threshold is reached, the FIFO must be read, or the data is lost when the sequence
starts over again with the SELECT cycle and series of triggers. No configuration is required except for
reselecting the channel unless the operation mode is changed. This allows the host to set up the converter and
continue monitoring a fixed input and come back to get a set of samples when preferred.
Triggered by CSTART: The first conversion can be started with a select cycle or CSTART. To do so, the user
can issue CSTART during the select cycle, immediately after the four-bit channel select command. The first
sample started as soon as the select cycle is finished (i.e., CS returns to 1). If there is enough time (2 µs) left
between the SELECT cycle and the following CSTART, a conversion is carried out. In this case, you need one
less trigger to fill the FIFO. Succeeding samples are triggered by CSTART.
sweep mode (mode 10)
Sweep mode (mode 10) also uses the FIFO. Once it is programmed in this mode, all of the channels listed in
the selected sweep sequence are visited in sequence. The results are converted and stored in the FIFO. This
sweep sequence may not be completed if the FIFO threshold is reached before the list is completed. This allows
the system designer to change the sweep sequence length. Once the FIFO has reached its programmed
threshold, an interrupt (INT) is generated. The host must issue a read FIFO command to read and clear the FIFO
before the next sweep can start.
repeat sweep mode (mode 11)
Repeat sweep mode (mode 11) works the same way as mode 10 except the operation has an option to continue
even if the FIFO threshold is reached. Once the FIFO has reached its programmed threshold, an interrupt (INT)
is generated. Then two things may happen:
1. The host may choose to act on it (read the FIFO) or ignore it. If the next cycle is a read FIFO cycle, all of
the data stored in the FIFO is retained until it has been read in order.
2. If the next cycle is not a read FIFO cycle, or another CSTART is generated, all of the content stored in the
FIFO is cleared before the next conversion result is stored in the FIFO, and the sweep is continued.
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TLV2544/TLV2548 conversion modes (continued)
Table 4. TLV2544/TLV2548 Conversion Mode
CONVERSION
MODE
One shot
Repeat
Sweep
Repeat sweep
CFR
D(6,5)
00
01
10
11
SAMPLING
TYPE
OPERATION
Normal
•
•
•
•
Single conversion from a selected channel
CS or FS to start select/sampling/conversion/read
One INT or EOC generated after each conversion
Host must serve INT by selecting channel, and converting and reading the previous output.
Extended
•
•
•
•
•
Single conversion from a selected channel
CS to select/read
CSTART to start sampling and conversion
One INT or EOC generated after each conversion
Host must serve INT by selecting next channel and reading the previous output.
Normal
•
•
•
•
Repeated conversions from a selected channel
CS or FS to start sampling/conversion
One INT generated after FIFO is filled up to the threshold
Host must serve INT by either 1) (FIFO read) reading out all of the FIFO contents up to the
threshold, then repeat conversions from the same selected channel or 2) writing another
command(s) to change the conversion mode. If the FIFO is not read when INT is served, it is
cleared.
Extended
•
Same as normal sampling except CSTART starts each sampling and conversion when CS is
high.
Normal
•
•
•
•
One conversion per channel from a sequence of channels
CS or FS to start sampling/conversion
One INT generated after FIFO is filled up to the threshold
Host must serve INT by (FIFO read) reading out all of the FIFO contents up to the threshold, then
write another command(s) to change the conversion mode.
Extended
•
Same as normal sampling except CSTART starts each sampling and conversion when CS is
high.
Normal
•
•
•
•
Repeated conversions from a sequence of channels
CS or FS to start sampling/conversion
One INT generated after FIFO is filled up to the threshold
Host must serve INT by either 1) (FIFO read) reading out all of the FIFO contents up to the
threshold, then repeat conversions from the same selected channel or 2) writing another
command(s) to change the conversion mode. If the FIFO is not read when INT is served it is
cleared.
Extended
•
Same as normal sampling except CSTART starts each sampling and conversion when CS is
high.
NOTES: 1. Programming the EOC/INT pin as the EOC signal works for mode 00 only. The other three modes automatically generate an INT
signal irrespective of how EOC/INT is programmed.
2. Extended. Sampling mode using CSTART as the trigger only works when internal reference is selected for conversion modes 01,
10, and 11.
3. When using CSTART to sample in extended mode, the falling edge of the next CSTART trigger should occur no more than 2.5 µs
after the falling CS edge (or falling FS edge if FS is active) of the channel select cycle. This is to prevent an ongoing conversion from
being canceled.
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timing diagrams
The timing diagrams can be categorized into two major groups: nonconversion and conversion. The
nonconversion cycles are read and write (configuration). None of these cycles carry a conversion. Conversion
cycles are those four modes of conversion.
read cycle (read FIFO or read CFR)
read CFR cycle:
The read command is decoded in the first 4 clocks. SDO outputs the contents of the CFR after the 4th SCLK.
This command works only when the device is programmed in the single shot mode (mode 00).
1
2
3
4
5
7
6
13
12
14
15
16
1
SCLK
CS
FS
SDI
ID15
ID14
ID13
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ID12
INT
EOC
SDO
ID15
ÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏ
OD11 OD10
OD9
OD4
OD3
OD2
OD1
OD0
ÏÏÏÏ
ÏÏÏÏ
Figure 2. TLV2544/TLV2548 Read CFR Cycle (FS active)
1
2
3
4
ID14
ID13
ID12
5
6
7
12
13
14
15
16
1
SCLK
CS
FS
ÏÏÏ
SDI
ID15
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ID15
ID14
INT
EOC
SDO
ÏÏÏÏÏÏ
ÏÏÏÏÏÏ
OD11 OD10
OD9
OD4
OD3
OD2
OD1
OD0
ÏÏÏ
ÏÏÏ
Figure 3. TLV2544/TLV2548 Read CFR Cycle (FS = 1)
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SLAS198E − FEBRUARY 1999 − REVISED JUNE 2003
read cycle (read FIFO or read CFR) (continued)
FIFO read cycle
The first command in the active cycle after INT is generated, if the FIFO is used, is assumed as the FIFO read
command. The first FIFO content is output immediately before the command is decoded. If this command is
not a FIFO read, then the output is terminated but the first data in the FIFO is retained until a valid FIFO read
command is decoded. Use of more layers of the FIFO reduces the time taken to read multiple data. This is
because the read cycle does not generate EOC or INT, nor does it carry out any conversion.
1
2
3
4
ID13
ID12
5
7
6
12
13
14
15
16
1
2
ID15
ID14
SCLK
CS
FS
SDI
INT
ÏÏÏ
ÏÏÏ
ID15 ID14
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
EOC
SDO
OD11 OD10
OD9
OD8
OD7 OD6
OD5
ÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏ
OD0
OD11 OD10
These devices can perform continuous FIFO read cycles (FS = 1) controlled by SCLK; SCLK can stop between each 16 SCLKs.
Figure 4. TLV2544/TLV2548 FIFO Read Cycle (FS = 1)
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write cycle (write CFR)
The write cycle is used to write to the configuration register CFR (with 12-bit register content). The write cycle
does not generate an EOC or INT, nor does it carry out any conversion (see power up and initialization
requirements).
1
2
3
4
5
6
ID11
ID10
7
12
13
14
15
16
1
SCLK
CS
FS
ÏÏÏÏ
ÏÏÏÏ
SDI
ID15
ID14
ID13
ID12
ID9
ID4
ID3
ID2
ID1
INT
EOC
SDO
ÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏ
ID0
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
Figure 5. TLV2544/TLV2548 Write Cycle (FS Active)
1
2
3
4
5
6
7
12
13
ID15
ID14
ID13
ID12
ID11
ID10
ID9
ID4
ID3
14
15
16
ID1
ID0
ID15
ÏÏÏÏÏ
ÏÏÏÏÏ
1
SCLK
CS
FS
ÏÏÏ
SDI
ID2
ÏÏÏÏÏÏÏÏ
ID15
ID14
INT
EOC
SDO
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏ
ÏÏÏÏ
Figure 6. TLV2544/TLV2548 Write Cycle (FS = 1)
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conversion cycles
DSP/normal sampling
1
2
3
4
5
6
7
12
16 − Short Sampling
30 − Short Sampling
28 − Long Sampling
42 − Long Sampling
(If CONV
CLK = SCLK0
SCLK
tc (30 or 42 SCLKs)
CS
FS
SDI
INT
ÏÏÏ
ÏÏÏ
ID15
ID14
ID13
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ID12
ID15
t(sample) (12 or 24 SCLKs)
ÏÏÏÏÏÏ
ÏÏÏÏÏÏ
EOC
(SDOZ on SCLK16L Regardless
of Sampling Time)
SDO
MSB-1
MSB
MSB-2
MSB-3
MSB-4
MSB-5
MSB-6
t(conv)
LSB
MSB
Figure 7. Mode 00 Single Shot/Normal Sampling (FS Signal Used)
16 − Short Sampling
1
2
3
4
5
6
7
12
13
28 − Long Sampling
30 − Short Sampling
42 − Long Sampling
(If CONV
CLK = SCLK0
1
SCLK
tc (30 or 42 SCLKs)
CS
ÏÏÏÏ
ÏÏÏÏ
FS
SDI
ID15
ID14
ID13
ID12
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ID15
INT
t(sample) (12 or 24 SCLKs)
EOC
SDO
ÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏ
(SDOZ on SCLK16L Regardless
of Sampling Time)
MSB
MSB-1
MSB-2
MSB-3
MSB-4
MSB-5
MSB-6
t(conv)
LSB
Figure 8. Mode 00 Single Shot/Normal Sampling (FS = 1, FS Signal not Used)
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MSB
SLAS198E − FEBRUARY 1999 − REVISED JUNE 2003
conversion cycles (continued)
Device Going Into
Extended Sampling Mode
Select/Read
Cycle
Select/Read
Cycle
Read
Cycle
Device Get Out
Extended Sampling
Mode
CS
t(sample )
Normal
Cycle
CSTART
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
FS
t(conv)
†
SDI
†
INT
EOC
SDO
Previous Conversion
Result
Previous Conversion
Result
Hi-Z
Hi-Z
ÏÏÏÏ
Hi-Z
† This is one of the single shot commands. Conversion starts on next rising edge of CSTART.
Figure 9. Mode 00 Single Shot/Extended Sampling (FS Signal Used, FS Pin Connected to TMS320 DSP)
modes using the FIFO: modes 01, 10, 11 timing
Configure Select
Conversion #1
From Channel 2
Conversion #4
From Channel 2
Select
CS
FS
CSTART
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏ
ÏÏÏÏÏ
ÏÏ
SDI
†
§
¶
¶
¶
‡
‡
‡
‡
§
¶
INT
SDO
Hi-Z
Hi-Z
Read FIFO
#1
Top of FIFO
#2
#3
#4
† Command = Configure write for mode 01, FIFO threshold = 1/2
‡ Command = Read FIFO, first FIFO read
§ Command = Select ch2.
¶ Use any channel select command to trigger SDI input.
Figure 10. TLV2544/TLV2548 Mode 01 DSP Serial Interface (Conversions Triggered by FS)
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modes using the FIFO: modes 01, 10, 11 timing (continued)
Conversion #1 From Channel 2
Configure Select
CS
Conversion #4 From Channel 2
Select
¶
FS
(DSP)
t(sample)
t(sample)
t(sample)
t(sample)
CSTART
SDI
INT
SDO
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏ
ÏÏÏ
ÏÏÏÏ
ÏÏÏ
†
§
‡
‡
‡
‡
§
Hi-Z
Hi-Z
Read FIFO
#1
#2
First FIFO Read
Sample Times ≥ MIN t(sample)
(See Operating Characteristics)
#3
#4
† Command = Configure write for mode 01, FIFO threshold = 1/2
‡ Command = Read FIFO, first FIFO read
§ Command = Select ch2.
¶ Minimum CS low time for select cycle is 6 SCLKs. The same amount of time is required between FS low to CSTART for proper channel decoding.
The low time of CSTART, not overlapped with CS low time, is the valid sampling time for the select cycle (see Figure 18).
Figure 11. TLV2544/TLV2548 Mode 01 µp/DSP Serial Interface (Conversions Triggered by CSTART)
Conversion
From Channel 0
Configure
Conversion
From Channel 3
Conversion
From Channel 0
Conversion
From Channel 3
CS
FS
(DSP)
CSTART
SDI
INT
SDO
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏ
ÏÏ
†
§
§
§
Repeat
§
Read FIFO
‡
‡
‡
#1
#2
#3
Top of FIFO
First FIFO Read
‡
#4
§
§
Repeat
§
§
‡
Read FIFO
#1
Second FIFO Read
† Command = Configure write for mode 10 or 11, FIFO threshold = 1/2, sweep seq = 0−1−2−3.
‡ Command = Read FIFO
§ Use any channel select command to trigger SDI input.
Figure 12. TLV2544/TLV2548 Mode 10/11 DSP Serial Interface (Conversions Triggered by FS)
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modes using the FIFO: modes 01, 10, 11 timing (continued)
Conversion
From Channel 0
Conversion
From Channel 3
Conversion
From Channel 3
Conversion
From Channel 0
Configure
CS
FS
(DSP)
CSTART
t(sample)
t(sample)
t(sample)
t(sample)
SDI
INT
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
‡
†
‡
‡
‡
#3
#4
‡
SDO
Read FIFO
Repeat
#1
#2
Top of FIFO
Read FIFO
Repeat
#1
Second FIFO Read
First FIFO Read
† Command = Configure write for mode 10 or 11, FIFO threshold = 1/2, sweep seq = 0−1−2−3.
‡ Command = Read FIFO
Figure 13. TLV2544/TLV2548 Mode 10/11 DSP Serial Interface (Conversions Triggered by CSTART)
Conversion
From Channel 0
Conversion
From Channel 0
Conversion
From Channel 3
Conversion
From Channel 3
Configure
CS
CSTART
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
SDI
†
§
§
§
§
‡
‡
‡
‡
§
§
§
§
‡
INT
SDO
Read FIFO
Repeat
#1
#2
#3
Top of FIFO
First FIFO Read
#4
Read FIFO
#1
Repeat
Second FIFO Read
† Command = Configure write for mode 10 or 11, FIFO threshold = 1/2, sweep seq = 0−1−2−3.
‡ Command = Read FIFO
§ Use any channel select command to trigger SDI input.
Figure 14. TLV2544/TLV2548 Mode 10/11 µp Serial Interface (Conversions Triggered by CS)
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FIFO operation
Serial
SDO
12-BIT×8
FIFO
ADC
7
6
FIFO Full
5
4
3
2
1
0
FIFO 1/2 Full
FIFO 3/4 Full
FIFO 1/4 Full
FIFO Threshold Pointer
Figure 15. TLV2544/TLV2548 FIFO
The device has an 8-layer FIFO that can be programmed for different thresholds. An interrupt is sent to the host
after the preprogrammed threshold is reached. The FIFO can be used to store data from either a fixed channel
or a series of channels based on a preprogrammed sweep sequence. For example, an application may require
eight measurements from channel 3. In this case, the FIFO is filled with eight data sequentially taken from
channel 3. Another application may require data from channel 0, channel 2, channel 4, and channel 6 in an
orderly manner. Therefore, the threshold is set for 1/2 and the sweep sequence 0−2−4−6−0−2−4−6 is chosen.
An interrupt is sent to the host as soon as all four data are in the FIFO.
In single shot mode, the FIFO automatically uses a 1/8 FIFO depth. Therefore the CFR bits (D1,0) controlling
FIFO depth are don’t care.
SCLK and conversion speed
There are two ways to adjust the conversion speed.
D The SCLK can be used as the source of the conversion clock to get the highest throughput of the device.
The minimum onboard OSC is 3.6 MHz and 14 conversion clocks are required to complete a conversion.
(Corresponding 3.86 µs conversion time) The devices can operate with an SCLK up to 20 MHz for the
supply voltage range specified. When a more accurate conversion time is desired, the SCLK can be used as
the source of the conversion clock. The clock divider provides speed options appropriate for an application
where a high speed SCLK is used for faster I/O. The total conversion time is 14 × (DIV/fSCLK) where DIV is 1,
2, or 4. For example a 20 MHz SCLK with the divide by 4 option produces a {14 × (4/20 M)} = 2.8 µs
conversion time. When an external serial clock (SCLK) is used as the source of the conversion clock, the
maximum equivalent conversion clock (fSCLK/DIV) should not exceed 6 MHz.
D Autopower down can be used to slow down the device at a reduced power consumption level. This mode
is always used by the converter. If the device is not accessed (by CS or CSTART), the converter is powered
down to save power. The built-in reference is left on in order to quickly resume operation within one half
SCLK period. This provides unlimited choices to trade speed with power savings.
reference voltage
The device has a built-in reference with a programmable level of 2 V or 4 V. If the internal reference is used,
REFP is set to 2 V or 4 V and REFM should be connected to the analog ground of the converter. An external
reference can also be used through two reference input pins, REFP and REFM, if the reference source is
programmed as external. The voltage levels applied to these pins establish the upper and lower limits of the
analog inputs to produce a full-scale and zero-scale reading respectively. The values of REFP, REFM, and the
analog input should not exceed the positive supply or be lower than GND consistent with the specified absolute
maximum ratings. The digital output is at full scale when the input signal is equal to or higher than REFP and
at zero when the input signal is equal to or lower than REFM.
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reference block equivalent circuit
INTERNAL
REF
Close = Int Ref Used
Open = Ext Ref Used
REFP
Sample
0.1 µF
Decoupling
Cap
10 µF
Internal
Reference
Compensation
Cap
Convert
~50 pF
CDAC
REFM (See Note A)
External to the Device
NOTES: A. If internal reference is used, tie REFM to analog ground and install a 10 µF (or 4.7 µF) internal reference compensation capacitor
between REFP and REFM to store the charge as shown in the figure above.
B. If external reference is used, the 10 µF (internal reference compensation) capacitor is optional. REFM can be connected to external
REFM or AGND.
C. Internal reference voltage drift, due to temperature variations, is approximately ±10 mV about the nominal 2 V (typically) from −10°C
to 100°C. The nominal value also varies approximately ±50 mV across devices.
D. Internal reference leakage during low ON time: Leakage resistance is on the order of 100 MΩ or more. This means the time constant
is about 1000 s with 10 µF compensation capacitance. Since the REF voltage does not vary much, the reference comes up quickly
after resuming from auto power down. At power up and power down the internal reference sees a glitch of about 500 µV when 2 V
internal reference is used (1 mV when 4 V internal reference is used). This glitch settles out after about 50 µs.
power down
The device has three power-down modes.
autopower-down mode
The device enters the autopower-down state at the end of a conversion.
In autopower-down, the power consumption reduces to about 1 mA when an internal reference is selected. The
built-in reference is still on to allow the device to resume quickly. The resumption is fast enough (within 0.5
SCLK) for use between cycles. An active CS, FS, or CSTART resumes the device from power-down state. The
power current is 1 µA when an external reference is programmed and SCLK stops.
hardware/software power-down mode
Writing 8000h to the device puts the device into a software power down state, and the entire chip (including the
built-in reference) is powered down. For a hardware power-down, the dedicated PWDN pin provides another
way to power down the device asynchronously. These two power-down modes power down the entire device
including the built-in reference to save power. The power down current is reduced to about 1 µA is the SCLK
is stopped.
An active CS, FS, or CSTART restores the device. There is no time delay when an external reference is selected.
However, if an internal reference is used, it takes about 20 ms to warm up. Deselect PWDN pin to remove the
device from the hardware power-down state. This requires about 20 ms to warm up if an internal reference is
also selected.
The configuration register is not affected by any of the power down modes but the sweep operation sequence
has to be started over again. All FIFO contents are cleared by the power-down modes.
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absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage range, GND to VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6.5 V
Analog input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VCC + 0.3 V
Reference input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC + 0.3 V
Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VCC + 0.3 V
Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 150°C
Operating free-air temperature range, TA: TLV2544/48C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
TLV2544/48I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
25 C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C‡
TA = 70
70°C
C
POWER RATING
TA = 85
85°C
C
POWER RATING
TA = 125
125°C
C
POWER RATING
D
1110 mW
8.9 mW/°C
710 mW
577 mW
222 mW
DW
1294 mW
10.4 mW/°C
828 mW
673 mW
259 mW
16 PW
839 mW
6.7 mW/°C
537 mW
437 mW
—
20 PW
977 mW
7.8 mW/°C
625 mW
508 mW
—
‡ This is the inverse of the traditional junction-to-ambient thermal resistance (RΘJA). Thermal resistance is not production tested and the values
given are for informational purposes only.
recommended operating conditions
MIN
Supply voltage, VCC
2.7
Analog input voltage (see Note 4)
0
High level control input voltage, VIH
NOM
3.3
MAX
V
VCC
V
2.1
Low-level control input voltage, VIL
UNIT
5.5
V
0.6
V
Delay time, delay from CS falling edge to FS rising edge, td(CSL-FSH)
(See Figure 16)
0.5
SCLKs
Delay time, delay time from 16th SCLK falling edge to CS rising edge (FS = 1), or
17th rising edge (FS is active) td(SCLK-CSH) (See Figures 16, and 19)
0.5
SCLKs
Setup time, FS rising edge before SCLK falling edge, tsu(FSH-SCLKL
(See Figure 16)
20
ns
Hold time, FS hold high after SCLK falling edge, th(FSH-SCLKL) (See Figure 16)
30
ns
Pulse width, CS high time, twH(CS) (See Figures 16 and 19)
100
Pulse width, FS high time, twH(FS) (See Figure 16)
0.75
1
75
10000
50
10000
SCLK cycle time, tc(SCLK)
(See Figures 16, and 19)
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5V
ns
SCLKs
ns
NOTE 4: When binary output format is used, analog input voltages greater than that applied to REFP convert as all ones (111111111111), while
input voltages less than that applied to REFM convert as all zeros (000000000000). The device is functional with reference down to
1 V. (VREFP − VREFM − 1); however, the electrical specifications are no longer applicable.
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recommended operating conditions (continued)
MIN
NOM
MAX
UNIT
Pulse width, SCLK low time, twL(SCLK) (See Figures 16 and 19)
0.4
0.6
SCLKs
Pulse width, SCLK high time, twH(SCLK) (See Figures 16 and 19)
0.4
0.6
SCLKs
Setup time, SDI valid before falling edge of SCLK (FS is active) or the rising edge of
SCLK (FS=1), tsu(DI-SCLK (See Figures 16 and 19)
25
ns
Hold time, SDI hold valid after falling edge of SCLK (FS is active) or the rising edge
of SCLK (FS=1), th(DI-SCLK) (See Figure 16)
5
ns
Delay time, delay from CS falling edge to SDO valid, td(CSL-DOV)
(See Figures 16 and 19)
Delay time, delay from FS falling edge to SDO valid, td(FSL-DOV) (See Figure 16)
Delay time, delay from SCLK falling edge (FS is
active) or SCLK rising edge (FS=1) to SDO valid,
td(SCLK-DOV). (See Figures 16 and 19).
For a date code later than xxx, see the date code
information item (3).
ns
25
ns
SDO = 5 pF
0.5 SCLK
0.5 SCLK
+9
SDO = 25 pF
0.5 SCLK
0.5 SCLK
+ 10
SDO = 5 pF
0.5 SCLK
0.5 SCLK
+ 18
SDO = 25 pF
0.5 SCLK
0.5 SCLK
+ 19
VCC = 4.5 V
VCC = 2.7 V
Delay time, delay from 17th SCLK rising edge (FS is active) or the 16th falling edge
(FS=1) to EOC falling edge, td(SCLK-EOCL) (See Figures 16 and 19)
Delay time, delay from 16th SCLK falling edge to INT falling edge (FS =1) or from
the 17th rising edge SCLK to INT falling edge (when FS active), td(SCLK-INTL)
(See Figure 19)
45
Pulse width, CSTART low time, twL(CSTART) (See Figures 17 and 18)
Delay time, delay from CSTART rising edge to CSTART falling edge,
td(CSTARTH-CSTARTL) (See Figure 18)
Delay time, delay from CSTART rising edge to INT falling edge, td(CSTARTH-INTL)
(See Figures 17 and 18)
50
100
ns
ns
1
50
ns
Min t(sample)
µs
Max t(conv)
µs
TLV2544C/TLV2548C
TLV2544I/TLV2548I
POST OFFICE BOX 655303
µs
1
Delay time, delay from CSTART rising edge to EOC falling edge, td(CSTARTH-EOCL)
(See Figures 17 and 18)
ns
ns
Min t(conv)
Delay time, delay from CS falling edge or FS rising edge to INT rising edge,
td(CSL-INTH) or td(FSH-INTH). See Figures 16, 17, 18 and 19)
Delay time, delay from CS rising edge to CSTART falling edge, td(CSH-CSTARTL)
(See Figures 17 and 18)
Operating free-air temperature, TA
25
• DALLAS, TEXAS 75265
µs
Max t(conv)
0
70
−40
85
°C
21
SLAS198E − FEBRUARY 1999 − REVISED JUNE 2003
electrical characteristics over recommended operating free-air temperature range, VCC = VREFP = 2.7 V to
5.5 V, VREFM = 0 V, SCLK frequency = 20 MHz at 5 V, 15 MHz at 3 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC = 5.5 V, IOH = −0.2 mA at 25 pF load
VOH
High-level output voltage
VOL
Low-level output voltage
IOZ
Off-state output current
(high-impedance-state)
VO = VCC
CS = VCC
IOZ
Off-state output current
(high-impedance-state)
VO = 0
CS = VCC
IIH
High-level input current
VI = VCC
IIL
Low-level input current
VI = 0 V
VCC = 2.7 V, IOH = -20 µA at 25 pF load
0.1
ICC
CS at 0 V, Ext ref
Operating supply current, extended
sampling
CS at 0 V, Int ref
Selected channel leakage current
Maximum static analog reference
current into REFP (use external
reference)
Input capacitance
Zi
Input MUX ON resistance
−2.5
2.5
µA
µA
−1
0.005
2.5
µA
−0.005
2.5
µA
VCC = 4.5 V to 5.5 V
1.1
VCC = 2.7 V to 3.3 V
1
VCC = 4.5 V to 5.5 V
2.1
VCC = 2.7 V to 3.3 V
1.6
VCC = 4.5 V to 5.5 V
1.1
VCC = 2.7 V to 3.3 V
1
VCC = 4.5 V to 5.5 V
2.1
VCC = 2.7 V to 3.3 V
1.6
mA
mA
mA
mA
VCC = 4.5 V to 5.5 V, Ext clock
0.1
1
VCC = 2.7 V to 3.3 V, Ext clock
0.1
1
VCC = 4.5 V to 5.5 V, Ext clock, Ext ref
1‡
VCC = 2.7 V to 3.3 V, Ext ref, Ext clock
1.0§
Selected channel at VCC
1
Selected channel at 0 V
1
VREFP = VCC = 5.5 V, VREFM = GND
45
50
Control Inputs
5
25
VCC = 4.5 V
500
VCC = 2.7 V
600
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
µA
A
µA
A
µA
1
Analog inputs
† All typical values are at VCC = 5 V, TA = 25°C.
‡ 1.2 mA if internal reference is used, 165 µA if internal clock is used.
§ 0.8 mA if internal reference is used, 116 µA if internal clock is used.
22
1
V
µA
A
Auto power-down current for all
digital inputs, 0 ≤ VI ≤ 0.3 V or
VI ≥ VCC − 0.3 V, SCLK = 0
Ci
UNIT
V
VCC−0.2
0.4
CS at 0 V, Int ref
ICC(AUTOPWDN)
MAX
2.4
VCC = 2.7 V, IOL = 20 µA at 25 pF load
CS at 0 V, Ext ref
ICC(PD)
TYP†
VCC = 5.5 V, IOL = 0.8 mA at 25 pF load
Operating supply current, normal
short sampling
Power down supply current
for all digital inputs,
0 ≤ VI ≤ 0.3 V or
VI ≥ VCC − 0.3 V, SCLK = 0
MIN
pF
Ω
SLAS198E − FEBRUARY 1999 − REVISED JUNE 2003
electrical characteristics over recommended operating free-air temperature range, VCC = VREFP = 2.7 V to
5.5 V, VREFM = 0 V, SCLK frequency = 20 MHz at 5 V, 15 MHz at 3 V (unless otherwise noted) (continued)
ac specifications
PARAMETER
SINAD
Signal-to-noise ratio +distortion
THD
Total harmonic distortion
ENOB
Effective number of bits
SFDR
Spurious free dynamic range
TEST CONDITIONS
fI = 12 kHz at 200 KSPS
fI = 12 kHz at 200 KSPS
MIN
69
C and I suffix
TYP
70
−82
fI = 12 kHz at 200 KSPS
fI = 12 kHz at 200 KSPS
MAX
dB
−76
11.6
−84
UNIT
dB
Bits
−75
dB
Analog input
Full power-bandwidth, −3 dB
1
MHz
Full-power bandwidth, −1 dB
500
kHz
reference specifications† (0.1 µF and 10 µF between REFP and REFM pins)
PARAMETER
TEST CONDITIONS
Positive reference input voltage, REFP
VCC = 2.7 V to 5.5 V
VCC = 2.7 V to 5.5 V
Negative reference input voltage, REFM
VCC = 5.5 V
Reference Input impedance
VCC = 2.7 V
0
CS = 1,
SCLK = 0, (off)
CS = 0,
SCLK = 20 MHz (on)
CS = 1,
SCLK = 0 (off)
CS = 0,
SCLK = 15 MHz (on)
VCC = 2.7 V to 5.5 V
VCC = 5.5 V
VREF SELECT = 4 V
Internal reference voltage, REFP−REFM
VCC = 5.5 V
VCC = 2.7 V
Internal reference temperature coefficient
† Specified by design
MAX
UNIT
VCC
2
V
100
20
25
kΩ
100
20
V
MΩ
MΩ
25
3.85
4
VREF SELECT = 2 V
1.925
2
2.075
V
VREF SELECT = 2 V
1.925
2
2.075
V
• DALLAS, TEXAS 75265
2
kΩ
VCC
4.15
VCC = 5.5 V, 2.7 V with 10 µF compensation cap
VCC = 2.7 V to 5.5 V
POST OFFICE BOX 655303
TYP
2
Reference Input voltage difference, REFP−REFM
Internal reference start-up time
MIN
20
16
V
V
ms
40† PPM/°C
23
SLAS198E − FEBRUARY 1999 − REVISED JUNE 2003
operating characteristics over recommended operating free-air temperature range, VCC = VREFP = 2.7 V to
5.5 V, VREFM = 0 V, SCLK frequency = 20 MHz at 5 V, 15 MHz at 3 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
UNIT
±1
LSB
See Note 5
±1
LSB
See Note 5
±2.5
LSB
+3.5
LSB
Integral linearity error (INL) (see Note 6)
Differential linearity error (DNL)
EO
EFS
Offset error (see Note 7)
Full scale error (see Note 7)
See Note 5
Self-test output code (see Table 1 and
Note 8)
Conversion time
t(sample)
Sampling time
−1.6
SDI = B000h
800h
(2048D)
SDI = C000h
000h (0D)
SDI = D000h
FFFh
(4095D)
Internal OSC
t(conv)
TYP†
MAX
EL
ED
MIN
2.33
3.5
(14
DIV)
f
SCLK
External SCLK
With a maximum of 1-kΩ input source
impedance
600
3.86
µs
ns
† All typical values are at TA = 25°C.
NOTES: 5. Analog input voltages greater than that applied to REFP convert as all ones (111111111111), while input voltages less than that
applied to REFM convert as all zeros (000000000000).
6. Linear error is the maximum deviation from the best straight line through the A/D transfer characteristics.
7. Zero error is the difference between 000000000000 and the converted output for zero input voltage: full-scale error is the difference
between 111111111111 and the converted output for full-scale input voltage.
8. Both the input data and the output codes are expressed in positive logic.
24
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
INT
EOC
SDO
SDI
td(FSL-DOV)
1
Hi-Z
OD11
ID15
OD10
ID14
ID1
ID0
don’t care
16
td(SCLK-INTL)
td(SCLK-EOCL)
don’t care
15
td(SCLK-CSH)
t(conv)
td(CSL-INTH)
Hi-Z
Figure 16. Critical Timing, DSP Mode (Normal Sampling, FS is Active)
td(SCLK-DOV)
2
twL(SCLK)
tsu(DI-SCLK)
th(DI-SCLK)
tc(SCLK)
twH(SCLK)
th(FSH-SCLKL)
tWH(FS)
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
td(CSL-DOV)
SCLK
tsu(FSH-SCLKL)
FS
td(CSL-FSH)
twH(CS)
td(FSL-DOV)
OD15
td(FSH-INTH)
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
CS
VOL
VOH
VOL
VOH
VOL
VOH
VIL
VIH
VIL
VIH
VIL
VIH
8
8 8 8
8 8 8
8 8 88
SLAS198E − FEBRUARY 1999 − REVISED JUNE 2003
PARAMETER MEASUREMENT INFORMATION
25
SLAS198E − FEBRUARY 1999 − REVISED JUNE 2003
PARAMETER MEASUREMENT INFORMATION
SELECT CYCLE
VIH
CS
VIL
td(CSH-CSTARTL)
twL(CSTART)
VIH
CSTART
†
VIL
td(CSTARTH-INTL)
t(CONV)
VOH
EOC
VOL
td(CSTARTH-EOCL)
td(CSL-INTH)
VOH
INT
VOL
† CSTART falling edge may come before the rising edge of CS but no sooner than the fifth SCLK of the SELECT CYCLE.
Figure 17. Critical Timing (Extended Sampling, Single Shot)
SELECT CYCLE
VIH
CS
twL(CSTART)
VIL
td(CSTARTH−CSTARTL)
td(CSH-CSTARTL)
VIH
CSTART
VIL
†
VOH
EOC
td(CSL-INTH)
td(CSTARTH-EOCL)
VOL
td(CSTARTH-INTL)
VOH
INT
VOL
† CSTART falling edge may come before the rising edge of CS but no sooner than the fifth SCLK of the SELECT CYCLE. In this case, the actual
sampling time is measured from the rising edge CS to the rising edge of CSTART.
Figure 18. Critical Timing (Extended Sampling, Repeat/Sweep/Repeat Sweep)
26
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
INT
EOC
SDO
SDI
Hi-Z
td(SCLK-DOV)
td(CSL-DOV)
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
SCLK
OD10
ID14
th(DI-SCLK)
don’t care
ID0
16
td(SCLK-INTL)
td(SCLK-EOCL)
don’t care
ID1
15
td(SCLK-CSH)
t(conv)
Hi-Z
twH(CS)
td(CSL-INTH)
Figure 19. Critical Timing, Microprocessor Mode (Normal Sampling, FS = 1)
OD11
ID15
2
twL(SCLK)
tsu(DI-SCLK)
1
tc(SCLK)
twH(SCLK)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
CS
VOL
VOH
VOL
VOH
VOL
VOH
VIL
VIH
VIL
VIH
VIL
VIH
8
8 8 8
8 8 8
8 8 88
SLAS198E − FEBRUARY 1999 − REVISED JUNE 2003
PARAMETER MEASUREMENT INFORMATION
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
27
SLAS198E − FEBRUARY 1999 − REVISED JUNE 2003
TYPICAL CHARACTERISTICS
INTEGRAL NONLINEARITY
vs
TEMPERATURE
INTEGRAL NONLINEARITY
vs
TEMPERATURE
0.6
0.595
0.52
INL − Integral Nonlinearity − LSB
INL − Integral Nonlinearity − LSB
0.53
0.51
0.5
0.49
0.48
VCC = 2.7 V, Internal Reference = 2 V,
Internal Oscillator, Single Shot,
Short Sample, Mode 00 µP Mode
0.59
0.585
0.58
0.575
0.57
0.565
0.47
−40 −23.75 −7.5 8.75 25 41.25 57.5 73.75
TA − Temperature − °C
VCC = 5.5 V, Internal Reference = 2 V,
Internal Oscillator, Single Shot,
Short Sample, Mode 00 µP Mode
0.56
−40 −23.75 −7.5 8.75 25 41.25 57.5 73.75
TA − Temperature − °C
90
Figure 21
Figure 20
DIFFERENTIAL NONLINEARITY
vs
TEMPERATURE
DIFFERENTIAL NONLINEARITY
vs
TEMPERATURE
0.48
0.494
DNL − Differential Nonlinearity − LSB
DNL − Differential Nonlinearity − LSB
0.496
0.492
0.49
0.488
0.486
0.484
0.482
90
VCC = 2.7 V, Internal Reference = 2 V,
Internal Oscillator, Single Shot,
Short Sample, Mode 00 µP Mode
0.47
0.46
0.45
0.44
0.43
VCC = 5.5 V, Internal Reference = 2 V,
Internal Oscillator, Single Shot,
Short Sample, Mode 00 µP Mode
0.48
0.478
−40 −23.75 −7.5 8.75 25 41.25 57.5 73.75
TA − Temperature − °C
90
0.42
−40 −23.75 −7.5 8.75 25 41.25 57.5 73.75
TA − Temperature − °C
Figure 22
28
Figure 23
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
90
SLAS198E − FEBRUARY 1999 − REVISED JUNE 2003
TYPICAL CHARACTERISTICS
GAIN ERROR
vs
TEMPERATURE
1.2
0.5
1
0
0.8
−0.5
Gain Error − LSB
Offset Error − LSB
OFFSET ERROR
vs
TEMPERATURE
0.6
0.4
0.2
VCC = 5 V, Internal Reference = 4 V,
External Oscillator = SCLK/4,
Single Shot, Long Sample,
Mode 00 µP Mode
−1
−1.5
−2
0
−40 −23.75 −7.5 8.75 25 41.25 57.5 73.75
TA − Temperature − °C
VCC = 5 V, Internal Reference = 4 V,
External Oscillator = SCLK/4,
Single Shot, Long Sample,
Mode 00 µP Mode
−2.5
−40 −23.75 −7.5 8.75 25 41.25 57.5 73.75
TA − Temperature − °C
90
Figure 24
90
Figure 25
SUPPLY CURRENT
vs
TEMPERATURE
POWER DOWN CURRENT
vs
TEMPERATURE
1.4
0.4
External Reference = 4 V, Internal Oscillator,
Single Shot, Short Sample, Mode 00 µP Mode
0.2
Long Sample
1
Powerdown Current − µ A
Supply Current − mA
1.2
Short Sample
0.8
VCC = 5 V, External Reference = 4 V,
Internal Oscillator, Single Shot,
Short Sample, Mode 00 µP Mode
0.6
−40 −23.75 −7.5 8.75 25 41.25 57.5 73.75
TA − Temperature − °C
VCC = 5 V
0
−0.2
−0.4
VCC = 2.7 V
−0.6
VCC = 5.5 V
−0.8
90
−1
−40 −23.75 −7.5 8.75 25 41.25 57.5 73.75
TA − Temperature − °C
Figure 26
90
Figure 27
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
29
SLAS198E − FEBRUARY 1999 − REVISED JUNE 2003
TYPICAL CHARACTERISTICS
INL − Integral Nonlinearity − LSB
INTEGRAL NONLINEARITY
vs
SAMPLES
1.0
VCC = 2.7 V, Internal Reference = 2 V, Internal Oscillator,
Single Shot, Short Sample, Mode 00 µP Mode
0.5
0.0
−0.5
−1.0
0
Samples
4097
Figure 28
DNL − Differential Nonlinearity − LSB
DIFFERENTIAL NONLINEARITY
vs
SAMPLES
1.0
VCC = 2.7 V, Internal Reference = 2 V, Internal Oscillator,
Single Shot, Short Sample, Mode 00 µP Mode
0.5
0.0
−0.5
−1.0
0
Samples
4097
Figure 29
INL − Integral Nonlinearity − LSB
INTEGRAL NONLINEARITY
vs
SAMPLES
1.0
VCC = 5 V, Internal Reference = 2 V, Internal Oscillator,
Single Shot, Short Sample, Mode 00 µP Mode
0.5
0.0
−0.5
−1.0
0
Samples
Figure 30
30
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
4097
SLAS198E − FEBRUARY 1999 − REVISED JUNE 2003
DNL − Differential Nonlinearity − LSB
TYPICAL CHARACTERISTICS
DIFFERENTIAL NONLINEARITY
vs
SAMPLES
1.0
VCC = 5 V, Internal Reference = 2 V, Internal Oscillator,
Single Shot, Short Sample, Mode 00 µP Mode
0.5
0.0
−0.5
−1.0
0
4097
Samples
Magnitude − dB
Figure 31
100%
160
150
140
130
120
110
100
90
80
70
60
50
40
30
20
10
0
VCC = 5 V, External Reference = 4 V,
Internal Oscillator , Single Shot, Long Sample, Mode 00 µP
Mode @ 200 KSPS
0
5
10
15 20
25 30
35 40
45 50
55 60
65 70
75 80 85 90
95 100
f − Frequency − kHz
Figure 32
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
31
SLAS198E − FEBRUARY 1999 − REVISED JUNE 2003
TYPICAL CHARACTERISTICS
SIGNAL-TO-NOISE + DISTORTION
vs
INPUT FREQUENCY
11.50
ENOB − Effective Number of Bits − BITS
SINAD − Signal-to-Noise + Distortion − dB
−67
−67.50
−68
−68.50
−69
−69.50
VCC = 5 V,
External Reference = 4 V,
Internal Oscillator,
Single Shot, Long Sample,
Mode 00 µP Mode
−70
−70.50
−71
EFFECTIVE NUMBER OF BITS
vs
INPUT FREQUENCY
11.40
11.30
11.20
11.10
VCC = 5 V,
External Reference = 4 V,
Internal Oscillator,
Single Shot, Long Sample,
Mode 00 µP Mode
11
10.90
10.80
0
50
100
f − Frequency − kHz
0
150
50
100
f − Frequency − kHz
Figure 33
Figure 34
SPURIOUS FREE DYNAMIC RANGE
vs
INPUT FREQUENCY
−69
−73
−70
−74
Spurious Free Dynamic Range − dB
THD − Total Harmonic Distortion − dB
TOTAL HARMONIC DISTORTION
vs
INPUT FREQUENCY
−71
−72
−73
−74
−75
−76
VCC = 5 V,
External Reference = 4 V,
Internal Oscillator,
Single Shot, Long Sample,
Mode 00 µP Mode
−77
−78
−79
0
50
100
f − Frequency − kHz
−75
−76
−77
−78
−79
VCC = 5 V,
External Reference = 4 V,
Internal Oscillator,
Single Shot, Long Sample,
Mode 00 µP Mode
−80
−81
150
−82
0
Figure 35
32
150
50
100
f − Frequency − kHz
Figure 36
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
150
SLAS198E − FEBRUARY 1999 − REVISED JUNE 2003
TYPICAL CHARACTERISTICS
SIGNAL-TO-NOISE RATIO
vs
INPUT FREQUENCY
RNR − Signal-to-Noise Ratio − dB
−70.2
VCC = 5 V,
External Reference = 4 V,
Internal Oscillator,
Single Shot, Long Sample,
Mode 00 µP Mode
−70.4
−70.6
−70.8
−71
−71.2
−71.4
0
50
100
f − Frequency − kHz
150
Figure 37
PRINCIPLES OF OPERATION
vcc
10 kΩ
VDD
XF
CS
TXD
SDI
RXD
SDO
AIN
CLKR
CLKX
TMS320 DSP
BIO
FSR
FSX
INT
SCLK
TLV2544/
TLV2548
FS
GND
Figure 38. Typical Interface to a TMS320 DSP
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
33
SLAS198E − FEBRUARY 1999 − REVISED JUNE 2003
DATA CODE INFORMATION
Parts with a date code earlier than 31xxxxx have the following discrepancies:
1. Earlier devices react to FS input irrespective of the state of the CS signal
2. The earlier silicon was designed with SDO prereleased half clock ahead. This means in the microcontroller
mode (FS=1) the SDO is changed on the rising edge of SCLK with a delay; and for DSP serial port (when
FS is active) the SDO is changed on the falling edge of SCLK with a delay. This helps the setup time for
processor input data, but may reduce the hold time for processor input data. It is recommended that a
100 pF capacitance be added to the SDO line of the ADC when interfacing with a slower processor that
requires longer input data hold time.
3. For earlier silicon, the delay time is specified as:
MIN
Delay time, delay from SCLK falling edge (FS is active) or
SCLK rising edge (FS=1) to next SDO valid, td(SCLK-DOV).
VCC = 4.5 V
VCC = 2.7 V
SDO = 0 pF
16
SDO = 100 pF
20
SDO = 0 pF
24
SDO = 100 pF
30
NOM
MAX
UNIT
ns
This is because the SDO is changed at the rising edge in the up mode with a delay. This is the hold time
required by the external digital host processor, therefore, a minimum value is specified. The newer silicon
has been revised with SDO changed at the falling edge in the up mode with a delay. Since at least 0.5 SCLK
exists as the hold time for the external host processor, the specified maximum value helps with the
calculation of the setup time requirement of the external digital host processor.
For an explanation of the DSP mode, reverse the rising/falling edges in item (2) above.
34
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TLV2544CD
ACTIVE
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
2544C
Samples
TLV2544CDR
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
2544C
Samples
TLV2544CPW
ACTIVE
TSSOP
PW
16
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TV2544
Samples
TLV2544CPWR
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TV2544
Samples
TLV2544ID
ACTIVE
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
2544I
Samples
TLV2544IDR
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
2544I
Samples
TLV2544IPW
ACTIVE
TSSOP
PW
16
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TY2544
Samples
TLV2544IPWR
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TY2544
Samples
TLV2548CDW
ACTIVE
SOIC
DW
20
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
2548C
Samples
TLV2548CDWR
ACTIVE
SOIC
DW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
2548C
Samples
TLV2548CPW
ACTIVE
TSSOP
PW
20
70
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TV2548
Samples
TLV2548CPWR
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TV2548
Samples
TLV2548IDW
ACTIVE
SOIC
DW
20
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
2548I
Samples
TLV2548IDWR
ACTIVE
SOIC
DW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
2548I
Samples
TLV2548IPW
ACTIVE
TSSOP
PW
20
70
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TY2548
Samples
TLV2548IPWG4
ACTIVE
TSSOP
PW
20
70
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TY2548
Samples
TLV2548IPWR
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TY2548
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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