TLV2556-EP
www.ti.com ................................................................................................................................................... SLAS598A – NOVEMBER 2008 – REVISED JULY 2009
12-BIT 200-KSPS 11-CHANNEL LOW-POWER SERIAL ANALOG-TO-DIGITAL CONVERTER
WITH INTERNAL REFERENCE
FEATURES
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
12-Bit-Resolution Analog-to-Digital Converter
(ADC)
Up to 200-KSPS (150-KSPS for 3 V)
Throughput Bit With 12-Output Mode Over
Operating Temperature Range
11 Analog Input Channels
3 Built-In Self-Test Modes
Programmable Reference (2.048 V/4.096 V
Internal or External)
Inherent Sample and Hold Function
Linearity Error...±1 LSB Max
On-Chip Conversion Clock
Programmable Conversion Status Output: INT
or EOC
Unipolar or Bipolar Output Operation
Programmable MSB or LSB First
Programmable Power Down
Programmable Output Data Length
SPI Compatible Serial Interface With I/O Clock
Frequencies up to 15 MHz (CPOL = 0,
CPHA = 0)
SUPPORTS DEFENSE, AEROSPACE,
AND MEDICAL APPLICATIONS
•
•
•
•
•
•
•
Controlled Baseline
One Assembly/Test Site
One Fabrication Site
Available in Military (–55°C/125°C)
Temperature Range (1)
Extended Product Life Cycle
Extended Product-Change Notification
Product Traceability
APPLICATIONS
•
•
•
•
(1)
Industrial Process Control
Portable Data Logging
Battery Powered Instruments
Automotive
PW AND DW PACKAGE
(TOP VIEW)
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
GND
1
20
2
3
19
18
4
5
17
16
6
7
15
14
8
9
13
12
10
11
VCC
INT/EOC
I/O CLOCK
DATA IN
DATA OUT
CS
REF +
REF −
AIN10
AIN9
DESCRIPTION
The TLV2556 is a 12-bit, switched-capacitor,
successive-approximation, analog-to-digital converter
(ADC). The ADC has three control inputs [chip select
(CS), the input-output clock, and the address/control
input (DATAIN)], designed for communication with the
serial port of a host processor or peripheral through a
serial 3-state output.
In addition to the high-speed converter and versatile
control capability, the device has an on-chip
14-channel multiplexer that can select any one of 11
inputs or any one of three internal self-test voltages
using configuration register 1. The sample-and-hold
function is automatic. At the end of conversion, when
programmed as EOC, the pin 19 output goes high to
indicate that conversion is complete. If pin 19 is
programmed as INT, the signal goes low when the
conversion is complete. The converter incorporated in
the device features differential, high-impedance
reference inputs that facilitate ratiometric conversion,
scaling, and isolation of analog circuitry from logic
and supply noise. A switched-capacitor design allows
low-error conversion over the full operating
temperature range. An internal reference is available
and its voltage level is programmable via
configuration register 2 (CFGR2).
Additional temperature ranges are available - contact factory
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008–2009, Texas Instruments Incorporated
TLV2556-EP
SLAS598A – NOVEMBER 2008 – REVISED JULY 2009 ................................................................................................................................................... www.ti.com
The TLV2556 is characterized for operation from TA = –55°C to 125°C.
ORDERING INFORMATION (1)
PACKAGE (2)
TA
–55°C to 125°C
(1)
(2)
TSSOP – PW
ORDERABLE PART NUMBER
Reel of 2000
TLV2556MPWREP
TOP-SIDE MARKING
TL2556EP
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
Functional Block Diagram
VCC
20
3
AIN0 1
AIN1 2
AIN2 3
AIN3 4
AIN4 5
AIN5 6
AIN6 7
AIN7 8
AIN8 9
AIN9 11
AIN10 12
DATA IN
CS
I/O CLOCK
Self Test
14-Channel
Analog
Multiplexer
4.096/2.048 V
Internal Reference
Low Power
12-Bit
SAR ADC
Input Address
Register
18
19
Control Logic
and I/O
Counters
INT/EOC
12
Output Data
Register
12
12-to-1
Data
Selector
and Driver
17
15
REF −
13
Reference CTRL
Sample
and Hold
4
REF +
14
16 DATA
OUT
4
Internal
OSC
10
GND
2
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TERMINAL FUNCTIONS
TERMINAL
NAME
AIN0–AIN10
CS
DATA IN
DATA OUT
NO.
I/O
DESCRIPTION
1–9,
11, 12
I
Analog input. These 11 analog-signal inputs are internally multiplexed.
15
I
Chip select. A high-to-low transition on CS resets the internal counters and controls and enables
DATA OUT, DATA IN, and I/O CLOCK. A low-to-high transition disables DATA IN and I/O CLOCK
within a setup time.
I
Serial data input. The 4-bit serial data can be used as address selects the desired analog input
channel or test voltage to be converted next, or a command to activate other features. The input
data is presented with the MSB (D7) first and is shifted in on the first four rising edges of the I/O
CLOCK. After the four address/command bits are read into the command register CMR, I/O
CLOCK clocks the remaining four bits of configuration in.
O
The 3-state serial output for the A/D conversion result. DATA OUT is in the high-impedance state
when CS is high and active when CS is low. With a valid CS, DATA OUT is removed from the
high-impedance state and is driven to the logic level corresponding to the MSB(most significant
bit)/LSB(least significant bit) value of the previous conversion result. The next falling edge of I/O
CLOCK drives DATA OUT to the logic level corresponding to the next MSB/LSB, and the remaining
bits are shifted out in order.
O
Status output, used to indicate the end of conversion (EOC) or an interrupt (INT) to host processor.
Programmed as INT (interrupt): INT goes from a high to a low logic level after the conversion is
complete and the data is ready for transfer. INT is cleared by a rising I/O CLOCK transition.
Programmed as EOC: EOC goes from a high to a low logic level after the falling edge of the last I/O
CLOCK and remains low until the conversion is complete and the data is ready for transfer.
17
16
INT/EOC
19
GND
10
Ground. GND is the ground return terminal for the internal circuitry. Unless otherwise noted, all
voltage measurements are with respect to GND.
18
Input /output clock. I/O CLOCK receives the serial input and performs the following four functions:
1. It clocks the eight input data bits into the input data register on the first eight rising edges of
I/O CLOCK with the multiplexer address available after the fourth rising edge.
2. On the fourth falling edge of I/O CLOCK, the analog input voltage on the selected multiplexer
input begins charging the capacitor array and continues to do so until the last falling edge of
I/O CLOCK.
3. The remaining 11 bits of the previous conversion data are shifted out on DATA OUT. Data
changes on the falling edge of I/O CLOCK.
4. Control of the conversion is transferred to the internal state controller on the falling edge of the
last I/O CLOCK.
I/O CLOCK
I
REF+
14
I/O
Positive reference voltage The upper reference voltage value (nominally VCC) is applied to REF+.
The maximum analog input voltage range is determined by the difference between the voltage
applied to terminals REF+ and REF–.
When the internal reference is used it is capable of driving a 10-kΩ, 10-pF load.
REF–
13
I/O
Negative reference voltage. The lower reference voltage value (nominally ground) is applied to
REF–. This pin is connected to analog ground (GND of the ADC) when the internal reference is
used.
VCC
20
Positive supply voltage
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ABSOLUTE MAXIMUM RATINGS (1) (2)
over operating free-air temperature range (unless otherwise noted)
VCC
Supply voltage range
VI
Input voltage range (any input)
–0.3 V to VCC + 0.3 V
–0.5 V to 6.5 V
VO
Output voltage range
–0.3 V to VCC + 0.3 V
VREF+
Positive reference voltage range
–0.3 V to VCC + 0.3 V
VREF–
Negative reference voltage range
–0.3 V to VCC + 0.3 V
II
Peak input current (any input)
±20 mA
Peak total input current (all inputs)
±30 mA
TJ
Operating virtual-junction temperature range
–55°C to 150°C
TA
Operating free-air temperature range
–55°C to 125°C
Tstg
Storage temperature range
–65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds
(1)
(2)
260°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to the GND terminal with REF– and GND wired together (unless otherwise noted).
RECOMMENDED OPERATING CONDITIONS
MIN
VCC
Supply voltage
SCLK frequency
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
Aperture jitter
VCC = 4.5 V to 5.5 V
Analog input voltage (1)
VIH
High level control input voltage
VIL
Low level control input voltage
TA
Operating free-air temperature
(1)
4
MAX
2.7
5.5
16-bit I/O
0.01
15
12-bit I/O
0.01
15
8-bit I/O
0.01
15
VCC = 2.7 V to 3.6 V
Tolerable clock jitter, I/O CLOCK
NOM
0.01
100
0
(REF+) – (REF–)
VCC = 3 V to 3.6 V
0
(REF+) – (REF–)
VCC = 2.7 V to 3 V
0
(REF+) – (REF–)
2
2.1
ns
V
V
VCC = 4.5 V to 5.5 V
0.8
VCC = 2.7 V to 3.6 V
0.6
–55
MHz
ps
VCC = 4.5 V to 5.5 V
VCC = 2.7 V to 3.6 V
V
10
0.38
VCC = 4.5 V to 5.5 V
UNIT
125
V
°C
Analog input voltages greater than the voltage applied to REF+ convert as all ones (111111111111), while input voltages less than the
voltage applied to REF– convert as all zeros (000000000000).
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ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range, VREF+ = 5 V,
SCLK frequency = 15 MHz when VCC = 5 V, VREF+ = 2.5 V,
SCLK frequency = 10 MHz when VCC = 2.7 V (unless otherwise noted)
PARAMETER
VOH
High-level output voltage
VOH
Low-level output voltage
IOZ
High impedance off state output current
VCC = 4.5 V, IOH = –1.6 mA
VCC = 2.7 V, IOH = –0.2 mA
VCC = 4.5 V, IOH = –20 µA
VCC = 2.7 V, IOH = –20 µA
VCC = 5.5 V, IOL = 1.6 mA
VCC = 3.6 V, IOL = 0.8 mA
VCC = 5.5 V, IOL = –20 µA
VCC = 3.6 V, IOL = –20 µA
Software power down current
D)
ICC(AP
Auto power down current
D)
V
VCC – 0.1
0.4
30 pF
V
0.1
1
2.5
–1
–2.5
CS at 0 V, Internal reference
For all digital inputs,
0 V ≤ VI ≤ 0.5 V or
VI ≥ VCC – 0.5 V, SCLK = 0 V
For all digital inputs,
0 V ≤ VI ≤ 0.5 V or
VI ≥ VCC – 0.5 V, SCLK = 0 V
UNIT
2.4
30 pF
VO = 0 V, CS = VCC
Operating supply current
ICC(SP
MAX
VO = VCC, CS = VCC
CS at 0 V, External reference
ICC
MIN TYP (1)
TEST CONDITIONS
VCC = 5 V
1.2
VCC = 2.7 V
0.9
VCC = 5 V
3
VCC = 2.7 V
µA
mA
2.4
External
reference
0.1
10
Internal
reference
0.1
10
External
reference
0.1
10
µA
µA
Internal
reference
1800
IIH
High-level input current
VI = VCC
0.005
2.5
µA
IIL
Low-level input current
VI = 0 V
–0.005
–2.5
µA
Ilkg
Selected channel leakage current
f(OSC)
Internal oscillator frequency
tconv
Conversion time = 13.5 × f(OSC) + 25 ns
Selected channel at VCC ,
Unselected channel at 0 V
1
Selected channel at 0 V,
Unselected channel at VCC
–1
VCC = 4.5 V to 5.5 V
3.0
VCC = 2.7 V to 3.6 V
2.1
Analog input MUX impedance (2)
Ci
Input capacitance
(1)
(2)
MHz
VCC = 4.5 V to 5.5 V
4.53
VCC = 2.7 V to 3.6 V
6.46
Internal oscillator frequency
switch-over voltage
Zi
µA
3.9
VCC = 4.5 V
600
VCC = 2.7 V
500
Analog inputs
45
Control inputs
5
µs
V
Ω
pF
All typical values are at VCC = 5 V, TA = 25°C.
The switch resistance is very nonlinear and varies with input voltage and supply voltage.
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EXTERNAL REFERENCE SPECIFICATIONS (1)
PARAMETER
MIN TYP (2)
TEST CONDITIONS
MAX
VCC = 4.5 V to 5.5 V
–0.1
0
0.1
VCC = 2.7 V to 3.6 V
–0.1
0
0.1
VCC = 4.5 V to 5.5 V
2
VCC
VCC = 2.7 V to 3.6 V
2
VCC
External reference input voltage
difference, (REF+) – (REF–)
VCC = 4.5 V to 5.5 V
1.9
VCC
VCC = 2.7 V to 3.6 V
1.9
VCC
External reference supply current
CS = 0 V
Reference input voltage, REF–
Reference input voltage, REF+
VCC = 5 V
Reference input impedance
VCC = 2.7 V
(1)
(2)
VCC = 4.5 V to 5.5 V
1
VCC = 2.7 V to 3.6 V
0.7
UNIT
V
V
V
mA
Static
1
MΩ
During sampling/conversion
9
kΩ
Static
1
MΩ
During sampling/conversion
9
kΩ
Add a 0.1-µF capacitor between REF+ and REF– pins when external reference is used.
All typical values are at VCC = 5 V, TA = 25°C.
INTERNAL REFERENCE SPECIFICATIONS (1)
PARAMETER
Reference input voltage, REF–
Internal reference voltage delta, (REF+) – (REF–)
Internal reference start up time
Internal reference temperature coefficient
(1)
(2)
6
MIN TYP (2)
TEST CONDITIONS
VCC = 2.7 V to 5.5 V, REF– = Analog GND
MAX
0
V
VCC = 5.5 V, Internal 4.096-V VREF selected
3.95
4.065
4.25
VCC = 5.5 V, Internal 2.048-V VREF selected
1.94
2.019
2.15
VCC = 2.7 V, Internal 2.048-V VREF selected
1.94
2.019
2.15
VCC = 5 V
VCC = 2.7 V
With 10-µF load
VCC = 2.7 V to 5.5 V
20
20
±50
UNIT
V
ms
ppm/°C
When an internal reference is used, the following conditions are required:
a. Add 0.1-µF and 10-µF capacitors between REF+ and REF– pins.
b. REF– must be connected to analog GND (the ground pin of the ADC).
All typical values are at VCC = 5 V, TA = 25°C.
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OPERATING CHARACTERISTICS
over recommended operating free-air temperature range, VREF+ = 5 V,
SCLK frequency = 15 MHz when VCC = 5 V, VREF+ = 2.5 V,
SCLK frequency = 10 MHz when VCC = 2.7 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
(2)
MIN TYP (1)
MAX
UNIT
INL
Integral nonlinearity error
–1
1
LSB
DNL
Differential nonlinearity error
–1
1
LSB
EO
Offset error (3) (4)
–2
2
mV
(3) (4)
EG
Gain error
ET
Total unadjusted error (5)
Self-test output code (6) (see Table 2)
(1)
(2)
(3)
(4)
(5)
(6)
–3
3
±1.5
Address data input = 1011
2048
Address data input = 1100
0
Address data input = 1101
4095
mV
LSB
All typical values are at VCC = 5 V, TA = 25°C.
Linearity error is the maximum deviation from the best straight line through the A/D transfer characteristics.
Analog input voltages greater than the voltage applied to REF+ convert as all ones (111111111111), while input voltages less than the
voltage applied to REF– convert as all zeros (000000000000).
Gain error is the difference between the actual mid-step value and the nominal mid-step value in the transfer diagram at the specified
gain point after the offset error has been adjusted to zero. Offset error is the difference between the actual mid-step value and the
nominal mid-step value at the offset point.
Total unadjusted error comprises linearity, zero-scale, and full-scale errors.
Both the input address and the output codes are expressed in positive logic.
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TIMING CHARACTERISTICS (1)
operating characteristics, VREF+ = 5 V, SCLK frequency = 15 MHz, VCC = 5 V, load = 25 pF, TA= -40°C to 85°C (unless
otherwise noted)
PARAMETER
MIN
tw1
Pulse duration I/O CLOCK high or low
26.7
tsu1
Setup time DATA IN valid before I/O CLOCK rising edge (see Figure 38)
th1
Hold time DATA IN valid after I/O CLOCK rising edge (see Figure 38)
(2)
tsu2
Setup time CS low before 1st rising I/O CLOCK edge
th2
Hold time CS pulse duration high time (see Figure 39)
th3
(see Figure 39)
TYP
MAX
100000
UNIT
ns
12
ns
0
ns
25
ns
100
ns
Hold time CS low after last I/O CLOCK falling edge (see Figure 39)
0
ns
th4
Hold time DATA OUT valid after I/O CLOCK falling edge (see Figure 40)
2
ns
th5
Hold time CS high after EOC rising edge when CS is toggled (see Figure 43)
0
ns
th6
Hold time CS high after INT falling edge (see Figure 43)
0
ns
th7
Hold time I/O CLOCK low after EOC rising edge or INT falling edge when CS is held
low (see Figure 44)
10
ns
td1
Delay time CS falling edge to DATA OUT valid
(MSB or LSB) (see Figure 37)
td2
Delay time CS rising edge to DATA OUT high impedance (see Figure 37)
td3
Delay time I/O CLOCK falling edge to next DATA OUT bit valid (see Figure 40)
td4
Delay time last I/O CLOCK falling edge to EOC falling edge (see Figure 41)
td5
Delay time last I/O CLOCK falling edge to CS falling edge to abort conversion
td6
Delay time last I/O CLOCK falling edge to INT falling edge (see Figure 41)
td7
Delay time EOC rising edge or INT falling edge to DATA OUT valid: MSB or LSB first
(see Figure 42)
td9
Delay time I/O CLOCK high to INT rising edge when CS is held low (see Figure 44)
tt1
Transition time I/O CLOCK (2) (see Figure 40)
tt2
Transition time DATA OUT (see Figure 40)
tt3
tt4
Load = 25 pF
28
Load = 10 pF
20
tsample
ns
20
ns
55
ns
1.5
µs
ns
4
ns
28
ns
1
µs
5
ns
Transition time INT/EOC, CL = 7 pF (see Figure 41 and Figure 42)
2.4
ns
Transition time DATA IN, CS
10
µs
MAX(tconv) +
I/O period
(8/12/16 CLKs)
µs
1
Channel acquisition time (sample), at 1 kΩ (2)
Source impedance = 25 Ω
600
Source impedance = 100 Ω
650
Source impedance = 500 Ω
700
Source impedance = 1 kΩ
8
10
MAX(tconv)
Total cycle time (sample, conversion and delays) (2)
tcyc
(1)
(2)
2
ns
ns
1000
Timing parameters are not production tested.
I/O CLOCK period = 8x [1/(I/O CLOCK frequency)] or 12x [1/(I/O CLOCK frequency)] or 16x [1/(I/O CLOCK frequency)] depends on I/O
format selected.
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TIMING CHARACTERISTICS (1)
operating characteristics, VREF+ = 2.5 V, SCLK frequency = 10 MHz, VCC = 2.7 V, load = 25 pF, TA= -40°C to 85°C (unless
otherwise noted)
PARAMETER
MIN
TYP
MAX
Pulse duration I/O CLOCK high or low
40
tsu1
Setup time DATA IN valid before I/O CLOCK rising edge (see Figure 38)
22
ns
th1
Hold time DATA IN valid after I/O CLOCK rising edge (see Figure 38)
0
ns
(2)
tsu2
Setup time CS low before 1st rising I/O CLOCK edge
th2
Hold time CS pulse duration high time (see Figure 39)
th3
ns
33
ns
100
ns
Hold time CS low after last I/O CLOCK falling edge (see Figure 39)
0
ns
th4
Hold time DATA OUT valid after I/O CLOCK falling edge (see Figure 40)
2
ns
th5
Hold time CS high after EOC rising edge when CS is toggled (see Figure 43)
0
ns
th6
Hold time CS high after INT falling edge (see Figure 43)
0
ns
th7
Hold time I/O CLOCK low after EOC rising edge or INT falling edge when CS is held
low (see Figure 44)
10
ns
td1
Delay time CS falling edge to DATA OUT valid
(MSB or LSB) (see Figure 37)
td2
Delay time CS rising edge to DATA OUT high impedance (see Figure 37)
td3
Delay time I/O CLOCK falling edge to next DATA OUT bit valid (see Figure 40)
td4
Delay time last I/O CLOCK falling edge to EOC falling edge (see Figure 41)
td5
Delay time last I/O CLOCK falling edge to CS falling edge to abort conversion
td6
Delay time last I/O CLOCK falling edge to INT falling edge (see Figure 41)
td7
Delay time EOC rising edge or INT falling edge to DATA OUT valid: MSB or LSB first
(see Figure 42)
td9
Delay time I/O CLOCK high to INT rising edge when CS is held low (see Figure 44)
tt1
Transition time I/O CLOCK (2) (see Figure 40)
tt2
Transition time DATA OUT (see Figure 40)
tt3
Transition time INT/EOC, CL = 7 pF (see Figure 41 and Figure 42)
tt4
Transition time DATA IN, CS
Load = 25 pF
30
Load = 10 pF
22
2
1
Total cycle time (sample, conversion and delays) (2)
tcyc
tsample
(1)
(2)
(see Figure 39)
100000
UNIT
tw1
Channel acquisition time (sample), at 1 kΩ (2)
Source impedance = 25 Ω
800
Source impedance = 100 Ω
850
Source impedance = 500 Ω
1000
Source impedance = 1 kΩ
1600
ns
10
ns
33
ns
75
ns
1.5
µs
MAX(tconv)
ns
20
ns
55
ns
1
µs
5
ns
4
ns
10
µs
MAX(tconv) +
I/O period
(8/12/16 CLKs)
µs
ns
Timing parameters are not production tested.
I/O CLOCK period = 8x [1/(I/O CLOCK frequency)] or 12x [1/(I/O CLOCK frequency)] or 16x [1/(I/O CLOCK frequency)] depends on I/O
format selected.
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TYPICAL CHARACTERISTICS
All typical curves are with internal reference unless specified otherwise. See the TLV2553 data sheet (SLAS354) for typical
curves using an external reference.
AUTO POWER DOWN
vs
FREE-AIR TEMPERATURE
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
I CC − Supply Current − mA
0.78
1100
VCC = 3.3 V
VREF+ = 2.048 V
VREF− = 0 V
I/O CLOCK = 10 MHz
150 KSPS,
TA = 25°C
1050
Current − µ A
0.8
0.76
1000
0.74
VCC = 3.3 V
VREF+ = 2.048 V
VREF− = 0 V
I/O CLOCK = 10 MHz
150 KSPS,
TA = 25°C
950
0.72
900
0.7
−40
−40
25
85
TA − Free-Air Temperature − °C
Figure 1.
Figure 2.
2-V INTERNAL REFERENCE CURRENT
vs
FREE-AIR TEMPERATURE
SOFTWARE POWER DOWN
vs
FREE-AIR TEMPERATURE
Current − µ A
0.2
1.15
VCC = 3.3 V
VREF+ = 2.048 V
VREF− = 0 V
I/O CLOCK = 10 MHz
150 KSPS,
TA = 25°C
1.1
Current − mA
0.25
0.15
0.1
1.05
VCC = 3.3 V
VREF+ = 2.048 V
VREF− = 0 V
I/O CLOCK = 10 MHz
150 KSPS,
TA = 25°C
1
0.05
0.95
0
−40
25
85
TA − Free-Air Temperature − °C
Figure 3.
10
25
85
TA − Free-Air Temperature − °C
−40
25
85
TA − Free-Air Temperature − °C
Figure 4.
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TYPICAL CHARACTERISTICS (continued)
All typical curves are with internal reference unless specified otherwise. See the TLV2553 data sheet (SLAS354) for typical
curves using an external reference.
MINIMUM DIFFERENTIAL NONLINEARITY
vs
FREE-AIR TEMPERATURE
MAXIMUM DIFFERENTIAL NONLINEARITY
vs
FREE-AIR TEMPERATURE
0.9
0.8
0.7
0
VCC = 2.7 V
VREF+ = 2.048 V
VREF− = 0 V
I/O CLOCK = 10 MHz
150 KSPS,
TA = 25°C
Minimum Differential Nonlinearity − LSB
Maximum Differential Nonlinearity − LSB
1
0.6
0.5
0.4
0.3
0.2
0.1
−0.1
−0.2
−0.3
VCC = 2.7 V
VREF+ = 2.048 V
VREF− = 0 V
I/O CLOCK = 10 MHz
150 KSPS,
TA = 25°C
−0.4
−0.5
−0.6
−0.7
−0.8
−0.9
−1
0
−40
25
85
TA − Free-Air Temperature − °C
−40
25
85
TA − Free-Air Temperature − °C
Figure 5.
Figure 6.
MINIMUM INTEGRAL NONLINEARITY
vs
FREE-AIR TEMPERATURE
1
0
0.9
−0.1
Minimum Integral Nonlinearity − LSB
Maximum Integral Nonlinearity − LSB
MAXIMUM INTEGRAL NONLINEARITY
vs
FREE-AIR TEMPERATURE
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
VCC = 2.7 V
VREF+ = 2.048 V
VREF− = 0 V
I/O CLOCK = 10 MHz
150 KSPS,
TA = 25°C
−0.2
−0.3
VCC = 2.7 V
VREF+ = 2.048 V
VREF− = 0 V
I/O CLOCK = 10 MHz
150 KSPS,
TA = 25°C
−0.4
−0.5
−0.6
−0.7
−0.8
−0.9
−1
0
−40
25
TA − Free-Air Temperature − °C
85
Figure 7.
−40
25
85
TA − Free-Air Temperature − °C
Figure 8.
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TYPICAL CHARACTERISTICS (continued)
INL − Integral Nonlinearity Error − LSB
DNL − Differential Nonlinearity Error − LSB
All typical curves are with internal reference unless specified otherwise. See the TLV2553 data sheet (SLAS354) for typical
curves using an external reference.
DIFFERENTIAL NONLINEARITY ERROR
vs
CODES
1.5
VCC = 2.7 V, VREF+ = 2.048 V, VREF− = 0 V, I/O
CLOCK = 10 MHz, 150 KSPS, TA = 25°C
1
0.5
0
−0.5
−1
−1.5
0
1024
2048
3072
4096
3072
4096
Codes
Figure 9.
INTEGRAL NONLINEARITY ERROR
vs
CODES
1.5
VCC = 2.7 V, VREF+ = 2.048 V, VREF− = 0 V, I/O
CLOCK = 10 MHz, 150 KSPS, TA = 25°C
1
0.5
0
−0.5
−1
−1.5
0
1024
2048
Codes
Figure 10.
12
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TYPICAL CHARACTERISTICS (continued)
All typical curves are with internal reference unless specified otherwise. See the TLV2553 data sheet (SLAS354) for typical
curves using an external reference.
GAIN ERROR
vs
FREE-AIR TEMPERATURE
OFFSET ERROR
vs
FREE-AIR-TEMPERATURE
0.05
0
EO − Offset Error − mV
EG − Gain Error − mV
0.04
0.03
0.02
0.01
0
VCC = 3.3 V
VREF+ = 2.048 V
VREF− = 0 V
I/O CLOCK = 10 MHz
150 KSPS,
TA = 25°C
−40
−0.05
VCC = 3.3 V
VREF+ = 2.048 V
VREF− = 0 V
I/O CLOCK = 10 MHz
150 KSPS,
TA = 25°C
−0.1
−0.15
−40
25
85
TA − Free-Air Temperature − °C
25
85
TA − Free-Air Temperature − °C
Figure 11.
Figure 12.
AUTO POWER DOWN
vs
FREE-AIR TEMPERATURE
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
1120
0.99
1100
0.97
Current − µ A
I CC − Supply Current − mA
0.98
VCC = 5.5 V
VREF+ = 4.096 V
VREF− = 0 V
I/O CLOCK = 15 MHz
200 KSPS,
TA = 25°C
0.96
VCC = 5.5 V
VREF+ = 4.096 V
VREF− = 0 V
I/O CLOCK = 15 MHz
200 KSPS,
TA = 25°C
1080
1060
0.95
1040
0.94
0.93
−40
25
85
TA − Free-Air Temperature − °C
1020
Figure 13.
−40
25
85
TA − Free-Air Temperature − °C
Figure 14.
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TYPICAL CHARACTERISTICS (continued)
All typical curves are with internal reference unless specified otherwise. See the TLV2553 data sheet (SLAS354) for typical
curves using an external reference.
4-V INTERNAL REFERENCE CURRENT
vs
FREE-AIR TEMPERATURE
SOFTWARE POWER DOWN
vs
FREE-AIR TEMPERATURE
1.55
0.5
1.5
1.45
Current − mA
Current − µ A
0.4
VCC = 5.5 V
VREF+ = 4.096 V
VREF− = 0 V
I/O CLOCK = 15 MHz
200 KSPS,
TA = 25°C
0.3
0.2
1.4
1.35
VCC = 5.5 V
VREF+ = 4.096 V
VREF− = 0 V
I/O CLOCK = 15 MHz
200 KSPS,
TA = 25°C
1.3
0.1
1.25
1.2
0
−40
−40
25
85
TA − Free-Air Temperature − °C
Figure 15.
Figure 16.
MAXIMUM DIFFERENTIAL NONLINEARITY
vs
FREE-AIR TEMPERATURE
MINIMUM DIFFERENTIAL NONLINEARITY
vs
FREE-AIR TEMPERATURE
0
0.8
0.7
VCC = 5.5 V
VREF+ = 4.096 V
VREF− = 0 V
I/O CLOCK = 15 MHz
200 KSPS,
TA = 25°C
Minimum Differential Nonlinearity − LSB
Maximum Differential Nonlinearity − LSB
1
0.9
0.6
0.5
0.4
0.3
0.2
0.1
−0.1
−0.2
−0.3
VCC = 5.5 V
VREF+ = 4.096 V
VREF− = 0 V
I/O CLOCK = 15 MHz
200 KSPS,
TA = 25°C
−0.4
−0.5
−0.6
−0.7
−0.8
−0.9
−1
0
25
85
−40
TA − Free-Air Temperature − °C
Figure 17.
14
25
85
TA − Free-Air Temperature − °C
−40
25
85
TA − Free-Air Temperature − °C
Figure 18.
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TYPICAL CHARACTERISTICS (continued)
All typical curves are with internal reference unless specified otherwise. See the TLV2553 data sheet (SLAS354) for typical
curves using an external reference.
MINIMUM INTEGRAL NONLINEARITY
vs
FREE-AIR TEMPERATURE
1
0
0.9
−0.1
Minimum Integral Nonlinearity − LSB
Maximum Integral Nonlinearity − LSB
MAXIMUM INTEGRAL NONLINEARITY
vs
FREE-AIR TEMPERATURE
0.8
0.7
0.6
0.5
0.4
VCC = 5.5 V
VREF+ = 4.096 V
VREF− = 0 V
I/O CLOCK = 15 MHz
200 KSPS,
TA = 25°C
0.3
0.2
0.1
−0.2
−0.3
−0.4
−0.5
−0.6
−0.7
−0.8
−0.9
0
VCC = 5.5 V
VREF+ = 4.096 V
VREF− = 0 V
I/O CLOCK = 15 MHz
200 KSPS,
TA = 25°C
−1
−40
25
85
−40
TA − Free-Air Temperature − °C
25
85
TA − Free-Air Temperature − °C
DNL − Differential Nonlinearity Error − LSB
Figure 19.
Figure 20.
DIFFERENTIAL NONLINEARITY ERROR
vs
CODES
1.5
VCC = 5.5 V, VREF+ = 4.096 V, VREF− = 0 V, I/O
CLOCK = 15 MHz, 200 KSPS, TA = 25°C
1
0.5
0
−0.5
−1
−1.5
0
1024
2048
3072
4096
Codes
Figure 21.
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TYPICAL CHARACTERISTICS (continued)
INL − Integral Nonlinearity Error − LSB
All typical curves are with internal reference unless specified otherwise. See the TLV2553 data sheet (SLAS354) for typical
curves using an external reference.
INTEGRAL NONLINEARITY ERROR
vs
CODES
1.5
VCC = 5.5 V, VREF+ = 4.096 V, VREF− = 0 V, I/O
CLOCK = 15 MHz, 200 KSPS, TA = 25°C
1
0.5
0
−0.5
−1
−1.5
0
1024
2048
3072
4096
Codes
Figure 22.
GAIN ERROR
vs
FREE-AIR TEMPERATURE
OFFSET ERROR
vs
FREE-AIR-TEMPERATURE
0
0.15
EG − Gain Error − mV
EO − Offset Error − mV
−0.2
0.2
VCC = 5.5 V
VREF+ = 4.096 V
VREF− = 0 V
I/O CLOCK = 15 MHz
200 KSPS,
TA = 25°C
−0.4
−0.6
VCC = 5.5 V
VREF+ = 4.096 V
VREF− = 0 V
I/O CLOCK = 15 MHz
200 KSPS,
TA = 25°C
0.1
0.05
0
−0.8
−40
25
85
TA − Free-Air Temperature − °C
Figure 23.
16
−40
25
85
TA − Free-Air Temperature − °C
Figure 24.
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TYPICAL CHARACTERISTICS (continued)
All typical curves are with internal reference unless specified otherwise. See the TLV2553 data sheet (SLAS354) for typical
curves using an external reference.
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
SOFTWARE POWER DOWN
vs
FREE-AIR TEMPERATURE
0.96
0.92
0.4
Current − µ A
I CC − Supply Current − mA
0.94
0.5
VCC = 5.5 V
VREF+ = 2.048 V
VREF− = 0 V
I/O CLOCK = 15 MHz
200 KSPS,
TA = 25°C
0.9
0.88
VCC = 5.5 V
VREF+ = 2.048 V
VREF− = 0 V
I/O CLOCK = 15 MHz
200 KSPS,
TA = 25°C
0.3
0.2
0.86
0.1
0.84
0.82
0
−40
25
85
TA − Free-Air Temperature − °C
−40
Figure 25.
2-V INTERNAL REFERENCE CURRENT
vs
FREE-AIR TEMPERATURE
1.25
1010
VCC = 5.5 V
VREF+ = 2.048 V
VREF− = 0 V
I/O CLOCK = 15 MHz
200 KSPS,
TA = 25°C
1.2
VCC = 5.5 V
VREF+ = 2.048 V
VREF− = 0 V
I/O CLOCK = 15 MHz
200 KSPS,
TA = 25°C
1.15
Current − mA
Current − µ A
85
Figure 26.
AUTO POWER DOWN
vs
FREE-AIR TEMPERATURE
1005
25
TA − Free-Air Temperature − °C
1000
995
1.1
1.05
990
1
0.95
985
−40
25
85
TA − Free-Air Temperature − °C
Figure 27.
−40
25
85
TA − Free-Air Temperature − °C
Figure 28.
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TYPICAL CHARACTERISTICS (continued)
All typical curves are with internal reference unless specified otherwise. See the TLV2553 data sheet (SLAS354) for typical
curves using an external reference.
MINIMUM DIFFERENTIAL NONLINEARITY
vs
FREE-AIR TEMPERATURE
1
0
0.9
−0.1
Minimum Differential Nonlinearity − LSB
Maximum Differential Nonlinearity − LSB
MAXIMUM DIFFERENTIAL NONLINEARITY
vs
FREE-AIR TEMPERATURE
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
VCC = 5.5 V
VREF+ = 2.048 V
VREF− = 0 V
I/O CLOCK = 15 MHz
200 KSPS,
TA = 25°C
−0.2
−0.3
VCC = 5.5 V
VREF+ = 2.048 V
VREF− = 0 V
I/O CLOCK = 15 MHz
200 KSPS,
TA = 25°C
−0.4
−0.5
−0.6
−0.7
−0.8
−0.9
−1
−40
25
85
TA − Free-Air Temperature − °C
−40
25
85
TA − Free-Air Temperature − °C
Figure 29.
Figure 30.
MINIMUM INTEGRAL NONLINEARITY
vs
FREE-AIR TEMPERATURE
1
0
0.9
−0.1
Minimum Integral Nonlinearity − LSB
Maximum Integral Nonlinearity − LSB
MAXIMUM INTEGRAL NONLINEARITY
vs
FREE-AIR TEMPERATURE
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
VCC = 5.5 V
VREF+ = 2.048 V
VREF− = 0 V
I/O CLOCK = 15 MHz
200 KSPS,
TA = 25°C
−0.3
−0.4
−0.5
−0.6
−0.7
−0.8
−0.9
0
−40
−0.2
VCC = 5.5 V
VREF+ = 2.048 V
VREF− = 0 V
I/O CLOCK = 15 MHz
200 KSPS,
TA = 25°C
25
85
TA − Free-Air Temperature − °C
−1
Figure 31.
18
−40
25
85
TA − Free-Air Temperature − °C
Figure 32.
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TYPICAL CHARACTERISTICS (continued)
All typical curves are with internal reference unless specified otherwise. See the TLV2553 data sheet (SLAS354) for typical
curves using an external reference.
GAIN ERROR
vs
FREE-AIR TEMPERATURE
OFFSET ERROR
vs
FREE-AIR-TEMPERATURE
0.4
0
0.3
EG − Gain Error − mV
EO − Offset Error − mV
−0.2
VCC = 5.5 V
VREF+ = 2.048 V
VREF− = 0 V
I/O CLOCK = 15 MHz
200 KSPS,
TA = 25°C
−0.4
0.2
0.1
−0.6
−0.8
VCC = 5.5 V
VREF+ = 2.048 V
VREF− = 0 V
I/O CLOCK = 15 MHz
200 KSPS,
TA = 25°C
0
−40
25
85
TA − Free-Air Temperature − °C
−40
25
85
TA − Free-Air Temperature − °C
DNL − Differential Nonlinearity Error − LSB
Figure 33.
Figure 34.
DIFFERENTIAL NONLINEARITY ERROR
vs
CODES
1.5
VCC = 5.5 V, VREF+ = 2.048 V, VREF− = 0 V, I/O
CLOCK = 10 MHz, 200 KSPS, TA = 25°C
1
0.5
0
−0.5
−1
−1.5
0
1024
2048
3072
4096
Codes
Figure 35.
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TYPICAL CHARACTERISTICS (continued)
INL − Integral Nonlinearity Error − LSB
All typical curves are with internal reference unless specified otherwise. See the TLV2553 data sheet (SLAS354) for typical
curves using an external reference.
INTEGRAL NONLINEARITY ERROR
vs
CODES
1.5
VCC = 5.5 V, VREF+ = 2.048 V, VREF− = 0 V, I/O
CLOCK = 15 MHz, 200 KSPS, TA = 25°C
1
0.5
0
−0.5
−1
−1.5
0
1024
2048
3072
4096
Codes
Figure 36.
20
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PARAMETER MEASUREMENT INFORMATION
VIH
CS
Data Valid
VIL
td1
VIH
DATA IN
td2
VIL
th1
VOH
DATA
OUT
VOL
tsu1
I/O CLOCK
VIH
VIL
Figure 37. DATA OUT to Hi-Z Voltage Waveforms
Figure 38. DATA IN and I/O CLOCK Voltage
VIH
CS
VIL
th2
tt1
tt1
VIH
VIL
I/O CLOCK
th3
tsu2
I/O CLOCK Period
VIH
I/O CLOCK
Last
Clock
td3
VIL
th4
DATA
OUT
Figure 39. CS and I/O CLOCK Voltage Waveforms
VOL
tt2
Figure 40. I/O CLOCK and DATA OUT Voltage
Waveforms
VIH
I/O CLOCK
Last
Clock
VIL
tt3
VOL
tt3
VOH
EOC
VOL
tt3
VOL
td7
VOH
VOL
td6
Figure 41. I/O CLOCK and EOC Voltage Waveforms
CS
VOH
INT
tt3
INT
VIL
VOH
EOC
tconv
td4
VOH
VOH
DATA
OUT
MSB
Valid
Figure 42. EOC and DATA OUT Voltage Waveforms
I/O CLOCK
VIL
th7
th5
EOC
EOC
VOH
VOL
VOH
td9
th6
INT
INT
VOL
Figure 43. CS and EOC Voltage Waveforms
VOL
VOH
Figure 44. I/O CLOCK and EOC Voltage Waveforms
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PARAMETER MEASUREMENT INFORMATION (continued)
Timing Information
First Cycle After Power-Up: Configure CFGR2
Configure CFGR1
1st Conversion Cycle
CS
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
1
I/O CLOCK
Access Cycle
3
2
4
Data Cycle
7
6
5
8
9
10
11
16
12
1
Invalid Conversion Data
DATA OUT
Hi−Z State
Command 1111
DATA IN
CFGR2 Data
D3
D2
D1
D7
D0
Figure 45. Timing for CFGR2 Configuration
The host must configure CFGR2 before valid device conversions can begin. This can be accessed through
command 1111. This can be done using 8, 12, or 16 I/O CLOCK clocks. (A minimum of 8 is required to fully
program CFGR2.)
After CFGR2 is configured, the following cycle configures CFGR1 and a valid sample/conversion is performed.
CS can be held low for each remaining cycle. First valid conversion output data is available on the third cycle
after power up.
Timing Diagrams
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous Conversion Result
CS
Access
Cycle
1
I/O
CLOCK
DATA
OUT
DATA
IN
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
3
2
Sample Cycle
4
5
6
7
8
Previous Conversion Data
MSB
10
11
D6
D5
Output Data
Format
D4
D3
D2
D1
D0
12
1
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
MSB−1 MSB−2 MSB−3 MSB−4 MSB−5 MSB−6 MSB−7 MSB−8 MSB−9 LSB+1
Channel
Address
D7
9
3
2
Hi−Z State
LSB
MSB
D7
MSB−1 MSB−2
D6
D5
A/D Conversion Interval
tconv
EOC
INT
Initialize
A.
Initialize
To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after the CS falling edge before
responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum
CS setup time has elapsed.
Figure 46. Timing for 12-Clock Transfer Using CS With DATA OUT Set for MSB First
22
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PARAMETER MEASUREMENT INFORMATION (continued)
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous Conversion Result
CS
Access
Cycle
1
I/O
CLOCK
DATA
OUT
DATA IN
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Sample Cycle
3
2
4
5
7
6
8
9
10
11
12
1
3
2
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
Previous Conversion Data
MSB
MSB−1 MSB−2 MSB−3 MSB−4 MSB−5 MSB−6 MSB−7 MSB−8 MSB−9 LSB+1
Channel
Address
D7
D6
D5
Output Data
Format
D4
D3
D2
D1
LSB
Low Level
MSB−1 MSB−2
MSB
D0
D7
D6
D5
A/D Conversion Interval
tconv
EOC
INT
Initialize
A.
Initialize
To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after the CS falling edge before
responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum
CS setup time has elapsed.
Figure 47. Timing for 12-Clock Transfer Not Using CS With DATA OUT Set for MSB First
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous Conversion Result
CS
Access
Cycle
1
2
3
Sample Cycle
4
5
6
7
I/O
CLOCK
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
DATA
OUT
DATA IN
Previous Conversion Data
8
1
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
2
3
4
5
6
7
Hi−Z State
MSB
MSB−1 MSB−2 MSB−3 MSB−4 MSB−5 LSB+1
Channel
Address
D7
D6
D5
Output Data
Format
D4
D3
D2
D1
LSB
MSB
D0
D7
MSB−1 MSB−2 MSB−3 MSB−4 MSB−5 MSB−6
D6
D5
D4
D3
D2
D1
A/D Conversion Interval
tconv
EOC
INT
Initialize
A.
Initialize
To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after the CS falling edge before
responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum
CS setup time has elapsed.
Figure 48. Timing for 8-Clock Transfer Using CS With DATA OUT Set for MSB First
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PARAMETER MEASUREMENT INFORMATION (continued)
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous Conversion Result
CS
1
Access
Cycle
3
2
I/O
CLOCK
Sample Cycle
4
5
6
7
8
1
2
3
4
5
7
6
Previous Conversion Data
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
DATA
OUT
MSB
Channel
Address
D7
DATA IN
MSB−1 MSB−2 MSB−3 MSB−4 MSB−5 LSB+1
D6
Output Data
Format
D5
D4
D3
D2
D1
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
LSB
MSB−1 MSB−2 MSB−3 MSB−4 MSB−5 MSB−6
MSB
Low Level
D0
D7
D6
D5
D4
D3
D2
D1
A/D Conversion Interval
tconv
EOC
INT
Initialize
A.
Initialize
To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after the CS falling edge before
responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum
CS setup time has elapsed.
Figure 49. Timing for 8-Clock Transfer Not Using CS With DATA OUT Set for MSB First
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous Conversion Result
CS
Access Cycle
1
Sample Cycle
3
2
4
I/O
CLOCK
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
DATA
OUT
MSB
DATA IN
D7
5
6
7
8
9
10
11
12
Pad
Zeros
MSB−1 MSB−2 MSB−3 MSB−4 MSB−5 MSB−6 MSB−7 MSB−8 MSB−9 LSB+1
D6
D5
Output Data
Format
D4
D3
D2
D1
1
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Previous Conversion Data
Channel
Address
16
Hi−Z State
LSB
MSB
D0
D7
A/D Conversion Interval
tconv
EOC
INT
Initialize
A.
Initialize
To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after the CS falling edge before
responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum
CS setup time has elapsed.
Figure 50. Timing for 16-Clock Transfer Using CS With DATA OUT Set for MSB First
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PARAMETER MEASUREMENT INFORMATION (continued)
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous Conversion Result
CS
Access Cycle
1
2
3
Sample Cycle
4
I/O
CLOCK
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
DATA
OUT
6
7
8
9
10
11
12
D7
D6
D5
Output Data
Format
D4
D3
D2
D1
1
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MSB−1 MSB−2 MSB−3 MSB−4 MSB−5 MSB−6 MSB−7 MSB−8 MSB−9 LSB+1
Channel
Address
16
Pad
Zeros
Previous Conversion Data
MSB
DATA IN
5
LSB
MSB
Low Level
D0
D7
A/D Conversion Interval
tconv
EOC
INT
Initialize
A.
Initialize
To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after the CS falling edge before
responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum
CS setup time has elapsed.
Figure 51. Timing for 16-Clock Transfer Not Using CS With DATA OUT Set for MSB First
Shift in New Multiplexer Address, Simultaneously
Shift Out Previous Conversion Result
CS
1
Access Cycle
3
4
2
5
6
7
I/O CLOCK
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
DATA OUT
DATA IN
MSB
8
Sample Cycle
9
10
11
12
Pad Zeros
MSB−1 MSB−2 MSB−3 MSB−4 MSB−5 MSB−6 MSB−7 MSB−8 MSB−9 LSB+1
Output Data
Format
DATA IN Can be Tied or Held High
1
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Previous Conversion Data
Channel
Address
16
Hi−Z State
LSB
MSB
D7
A/D Conversion Interval
tconv
EOC Initialize
A.
Initialize
To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after the CS falling edge before
responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum
CS setup time has elapsed.
Figure 52. Timing for Default Mode Using CS: (16-Clock Transfer, MSB First, External Reference, Pin 19 =
EOC, Input = AIN0)
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PARAMETER MEASUREMENT INFORMATION (continued)
Shift in New Multiplexer Address, Simultaneously
Shift Out Previous Conversion Result
CS
Access Cycle
1
2
3
Sample Cycle
4
5
6
7
8
9
10
11
12
16
1
I/O CLOCK
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
DATA OUT
MSB
DATA IN
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Previous Conversion Data
Pad Zeros
MSB−1 MSB−2 MSB−3 MSB−4 MSB−5 MSB−6 MSB−7 MSB−8 MSB−9 LSB+1
Channel
Address
Output Data
Format
DATA IN Can be Tied or Held High
LSB
Low Level
MSB
D7
A/D Conversion Interval
tconv
EOC
Initialize
A.
Initialize
To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after the CS falling edge before
responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum
CS setup time has elapsed.
Figure 53. Timing for Default Mode Not Using CS: (16-Clock Transfer, MSB First, External Reference, Pin
19 = EOC, Input = AIN0)
To remove the device from default mode, CFGR2–D0 must be reset to 0. Valid sample/convert cycles can
resume on the cycle following the CFGR2 configuration.
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PRINCIPLES OF OPERATION
Initially, with chip select (CS) high, I/O CLOCK and DATA IN are disabled and DATA OUT is in the
high-impedance state. CS going low begins the conversion sequence by enabling I/O CLOCK and DATA IN and
removes DATA OUT from the high-impedance state. The input data is an 8-bit data stream consisting of a 4-bit
address or command (D7–D4) and a 4-bit configuration data (D3–D0). There are two sets of configuration
registers, configuration register 1 – CFGR1 and configuration register 2 – CFGR2. CFGR1, which controls output
data format configuration, consists of a 2-bit data length select (D3–D2), an output MSB or LSB first bit (D1), and
a unipolar or bipolar output select bit (D0) that are applied to any command (from DATA IN) except for command
1111b. CFGR2, which provides configuration information other than data format, consists of a 2-bit reference
select (D3–D2), an EOC/INT program bit (D1), and a default mode select bit (D0) that are applied to command
1111b. The I/O CLOCK sequence applied to the I/O CLOCK terminal transfers this data to the input data
register. During this transfer, the I/O CLOCK sequence also shifts the previous conversion result from the output
data register to DATA OUT. I/O CLOCK receives the input sequence of 8, 12, or 16 clock cycles long depending
on the data-length selection in the input data register. Sampling of the analog input begins on the fourth falling
edge of the input I/O CLOCK sequence and is held after the last falling edge of the I/O CLOCK sequence. The
last falling edge of the I/O CLOCK sequence also takes EOC low (if pin 19 = EOC) and begins the conversion.
Converter Operation
The operation of the converter is organized as a succession of three distinct cycles: 1) the data I/O cycle, 2) the
sampling cycle, and 3) the conversion cycle. The first two are partially overlapped.
Data I/O Cycle
The data I/O cycle is defined by the externally provided I/O CLOCK and lasts 8, 12, or 16 clock periods,
depending on the selected output data length. During the I/O cycle, the following two operations take place
simultaneously. An 8-bit data stream consisting of address/command and configuration information is provided to
DATA IN. This data is shifted into the device on the rising edge of the first eight I/O CLOCK clocks. Data input is
ignored after the first eight clocks during 12- or 16-clock I/O transfers. The data output, with a length of 8, 12, or
16 bits, is provided serially on DATA OUT. When CS is held low, the first output data bit occurs on the rising
edge of EOC. When CS is toggled between conversions, the first output data bit occurs on the falling edge of
CS. This data is the result of the previous conversion period, and after the first output data bit, each succeeding
bit is clocked out on the falling edge of each succeeding I/O CLOCK.
Sampling Period
During the sampling period, one of the analog inputs is internally connected to the capacitor array of the
converter to store the analog input signal. The converter starts sampling the selected input immediately after the
four address/command bits have been clocked into the input data register. Sampling starts on the fourth falling
edge of I/O CLOCK. The converter remains in the sampling mode until the eighth, twelfth, or sixteenth falling
edge of I/O CLOCK depending on the data-length selection.
After the 8-bit data stream has been clocked in, DATA IN should be held at a fixed digital level until EOC goes
high or INT goes low (indicating that the conversion is complete) to maximize the sampling accuracy and
minimize the influence of external digital noise.
Conversion Cycle
A conversion cycle is started only after the I/O cycle is completed, which minimizes the influence of external
digital noise on the accuracy of the conversion. This cycle is transparent to the user because it is controlled by
an internal clock (oscillator). The total conversion time is equal to 13.5 OSC clocks plus a small delay (~25 ns) to
start the OSC. During the conversion period, the device performs a successive-approximation conversion on the
analog input voltage.
When programmed as EOC, pin 19 goes low at the start of the conversion cycle and goes high when the
conversion is complete and the output data register is latched. After EOC goes low, the analog input can be
changed without affecting the conversion result. Since the delay from the falling edge of the last I/O CLOCK to
the falling edge of EOC is fixed, any time-varying analog input signals can be digitized at a fixed rate without
introducing systematic harmonic distortion or noise due to timing uncertainty.
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When programmed as INT, pin 19 goes low when the conversion is complete and the output data register is
latched. The next I/O CLOCK rising edge clears the INT output. The time from the last I/O CLOCK falling edge to
the falling INT edge is equivalent to the EOC delay mentioned above plus the maximum conversion time. INT is
cancelled by (or brought to high) by either the next CS falling edge or the next SCLK rising edge (when CS is
held low all of the time for multiple cycles). When CS is held low continuously (for multiple cycles) MSB output
occurs after the first rising edge of I/O CLOCK after EOC is inactive or the falling edge of INT.
Power Up and Initialization
After power up, CS must be taken from high to low to begin an I/O cycle. INT/EOC pin is initially high, and both
configuration registers are set to all zeroes. The contents of the output data register are random, and the first
conversion result should be ignored. To initialize during operation, CS is taken high and is then returned low to
begin the next I/O cycle. The first conversion after the device has returned from the power-down state may not
read accurately due to internal device settling.
Table 1. Operational Terminology
Current (N) I/O cycle
The entire I/O CLOCK sequence that transfers address and control data into the data register and
clocks the digital result from the previous conversion from DATA OUT.
Current (N) conversion cycle
The conversion cycle starts immediately after the current I/O cycle. The end of the current I/O cycle is
the last clock falling edge in the I/O CLOCK sequence. The current conversion result is loaded into
the output register when conversion is complete.
Current (N) conversion result
The current conversion result is serially shifted out on the next I/O cycle.
Previous (N–1) conversion cycle
The conversion cycle just prior to the current I/O cycle
Next (N+1) I/O cycle
The I/O period that follows the current conversion cycle
Example
In 12-bit mode, the result of the current conversion cycle is a 12-bit serial-data stream clocked out during the
next I/O cycle. The current I/O cycle must be exactly 12 bits long to maintain synchronization, even when this
corrupts the output data from the previous conversion. The current conversion is begun immediately after the
twelfth falling edge of the current I/O cycle.
Default Mode
When the DATA IN pin is held high, the ADC goes into hardware default mode because the CFGR2 bits are all
programmed to the default values after eight I/O CLOCK cycles. This means the ADC is programmed for an
external reference and pin 19 as EOC. In addition, channel AIN0 is selected. The first conversion is invalid
therefore the conversion result should be ignored. On the next cycle, AIN0 is sampled and converted. This mode
of operation is valid when CS is toggled or held low after the first cycle.
To remove the device from hardware default mode, CFGR2 bit D0 must be reset to 0. Once this is done, the host
must program CFGR1 on the next cycle and disregard the result from the current cycle’s conversion.
Data Input
The data input is internally connected to an 8-bit serial-input address and control register. The register defines
the operation of the converter and the output data length. The host provides the input data byte with the MSB
first. Each data bit is clocked in on the rising edge of the I/O CLOCK sequence (see Table 2 for the data
input-register format).
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Table 2. Command Set (CMR) and Configuration
SDI D[7:4]
Binary,
HEX
COMMAND
0000b
0h
SELECT analog input channel 0
0001b
1h
SELECT analog input channel 1
0010b
2h
SELECT analog input channel 2
0011b
3h
SELECT analog input channel 3
0100b
4h
SELECT analog input channel 4
0101b
5h
SELECT analog input channel 5
0110b
6h
SELECT analog input channel 6
CFGR1
0111b
7h
SELECT analog input channel 7
1000b
8h
SELECT analog input channel 8
SDI
D[3:0]
1001b
9h
SELECT analog input channel 9
1010b
Ah
SELECT analog input channel 10
1011b
Bh
SELECT TEST,
1100b
Ch
SELECT TEST, Voltage = REFM
1101b
Dh
SELECT TEST, Voltage = REFP
1110b
Eh
SW POWERDOWN (analog + reference)
1111b
Fh
ACCESS CFGR2
D[3:2]
D1
Voltage = (VREF+ + VREF−)/2
D0
CONFIGURATION
01: 8-bit output length
X0: 12-bit output length
11: 16-bit output length (default)
0: MSB out first (default)
1: LSB out first
0: Unipolar binary (default)
1: Bipolar 2s complement
CFGR2
SDI
D[3:0]
D[3:2]
D1
D0
CONFIGURATION
00:
01:
11:
0:
1:
0:
Internal 4.096 reference
Internal 2.048 reference
External reference (default)
Pin 19 output EOC (default)
Pin 19 output Int
Normal mode
(CFGR1 needs to be programmed)
1: Default mode enabled
(D[3:0] of CFGR1 and D[3:1] of
CFGR2 set to default)
Data Input – Address/Command Bits
The four MSBs (D7–D4) of the input data register are the address or command. These bits can be used to
address one of the 11 input channels, select one of three reference-test voltages, activate the software
power-down mode, or access the second configuration register, CFGR2. All address/command bits affect the
current conversion, which is the conversion that immediately follows the current I/O cycle. They also allow
access to CFGR1 except for command 1111b, which allows access to CFGR2.
Data Output Length
CFGR1 bits (D3 and D2) of the data register select the output data length. The data-length selection is valid for
the current I/O cycle (the cycle in which the data is read). The data-length selection, being valid for the current
I/O cycle, allows device start-up without losing I/O synchronization. A data length of 8, 12, or 16 bits can be
selected. Since the converter has 12-bit resolution, a data length of 12 bits is suggested.
With D3 and D2 set to 00 or 10, the device is in the 12-bit data-length mode and the result of the current
conversion is output as a 12-bit serial data stream during the next I/O cycle. The current I/O cycle must be
exactly 12 bits long for proper synchronization, even when this means corrupting the output data from a previous
conversion. The current conversion is started immediately after the twelfth falling edge of the current I/O cycle.
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With bits D3 and D2 set to 11, the 16-bit data-length mode is selected, which allows convenient communication
with 16-bit serial interfaces. In the 16-bit mode, the result of the current conversion is output as a 16-bit serial
data stream during the next I/O cycle with the four LSBs always reset to 0 (pad bits). The current I/O cycle must
be exactly 16 bits long to maintain synchronization even when this means corrupting the output data from the
previous conversion. The current conversion is started immediately after the sixteenth falling edge of the current
I/O cycle.
With bits D3 and D2 set to 01, the 8-bit data-length mode is selected, which allows fast communication with 8-bit
serial interfaces. In the 8-bit mode, the result of the current conversion is output as an 8-bit serial data stream
during the next I/O cycle. The current I/O cycle must be exactly eight bits long to maintain synchronization, even
when this means corrupting the output data from the previous conversion. The four LSBs of the conversion result
are truncated and discarded. The current conversion is started immediately after the eighth falling edge of the
current I/O cycle.
Because the D3 and D2 register settings take effect on the I/O cycle when the data length is programmed, there
can be a conflict with the previous cycle if the data-word length was changed. This may occur when the data
format is selected to be least significant bit first, since at the time the data length change becomes effective (six
rising edges of I/O CLOCK), the previous conversion result has already started shifting out. In actual operation,
when different data lengths are required within an application and the data length is changed between two
conversions, no more than one conversion result can be corrupted and only when it is shifted out in LSB-first
format.
LSB Out First
D1 in the CFGR1 controls the direction of the output (binary) data transfer. When D1 is reset to 0, the conversion
result is shifted out MSB first. When set to 1, the data is shifted out LSB first. Selection of MSB first or LSB first
always affects the next I/O cycle and not the current I/O cycle. When changing from one data direction to
another, the current I/O cycle is never disrupted.
Bipolar Output Format
D0 in the CFGR1 controls the binary data format used to represent the conversion result. When D0 is cleared to
0, the conversion result is represented as unipolar (unsigned binary) data. Nominally, the conversion result of an
input voltage equal to or less than VREF– is a code with all zeros (000...0) and the conversion result of an input
voltage equal to or greater than VREF+ is a code of all ones (111...1). The conversion result of (VREF+ + VREF–)/2 is
a code of a one followed by zeros (100 ...0).
When D0 is set to 1, the conversion result is represented as bipolar (signed binary) data. Nominally, conversion
of an input voltage equal to or less than VREF– is a code of a one followed by zeros (100...0), and the conversion
of an input voltage equal to or greater than VREF+ is a code of a zero followed by all ones (011...1). The
conversion result of (VREF+ + VREF–)/2 is a code of all zeros (000...0). The MSB is interpreted as the sign bit. The
bipolar data format is related to the unipolar format in that the MSBs are always each other’s complement.
Selection of the unipolar or bipolar format always affects the current conversion cycle, and the result is output
during the next I/O cycle. When changing between unipolar and bipolar formats, the data output during the
current I/O cycle is not affected.
Reference
The device has a built-in reference with a programmable level of 2.048 V or 4.096 V. If the internal reference is
used, REF+ is set to 2.048 V or 4.096 V and REF– is set to analog GND. An external reference can also be used
through two reference input pins, REF+ and REF–, if the reference source is programmed as external. The
voltage levels applied to these pins establish the upper and lower limits of the analog inputs to produce a
full-scale and zero-scale reading respectively. The values of REF+, REF–, and the analog input should not
exceed the positive supply or be lower than GND consistent with the specified absolute maximum ratings. The
digital output is at full scale when the input signal is equal to or higher than REF+ and at zero when the input
signal is equal to or lower than REF–.
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VCC
Analog
Supply
Internal
Reference
S1
S2
S1, S2:
Closed = Internal Reference Used
Opened = External Reference Used
REF+
Sample
C1
0.1 µF
Decoupling Cap
C2
10 µF
Int Reference
Compensation Cap
C2 and Grounding REF− Are Required
When Either 4.096 V or 2.048 Internal
Reference Is Used
Convert
∼50 pF
CDAC
REF−
GND
Figure 54. Reference Block
INT/EOC Output
Pin 19 outputs the status of the ADC conversion. When programmed as EOC, the output indicates the beginning
and the end of conversion. In the reset state, EOC is always high. During the sampling period (beginning after
the fourth falling edge of the I/O CLOCK sequence), EOC remains high until the internal sampling switch of the
converter is safely opened. The opening of the sampling switch occurs after the eighth, twelfth, or sixteenth I/O
CLOCK falling edge, depending on the data-length selection in the input data register. After the EOC signal goes
low, the analog input signal can be changed without affecting the conversion result.
The EOC signal goes high again after the conversion is completed and the conversion result is latched into the
output data register. The rising edge of EOC returns the converter to a reset state and a new I/O cycle begins.
On the rising edge of EOC, the first bit of the current conversion result is on DATA OUT when CS is low. When
CS is toggled between conversions, the first bit of the current conversion result occurs on DATA OUT at the
falling edge of CS.
When programmed as INT, the output indicates that the conversion is completed and the output data is ready to
be read. In the reset state, INT is always high. INT is high during the sampling period and until the conversion is
complete. After the conversion is finished and the output data is latched, INT goes low and remains low until it is
cleared by the host. When CS is held low, the MSB (or LSB) of the conversion result is presented on DATA OUT
on the falling edge of INT. A rising I/O CLOCK edge clears the interrupt.
Chip-Select Input (CS)
CS enables and disables the device. During normal operation, CS should be low. Although the use of CS is not
necessary to synchronize a data transfer, it can be brought high between conversions to coordinate the data
transfer of several devices sharing the same bus.
When CS is brought high, the serial-data output is immediately brought to the high-impedance state, releasing its
output data line to other devices that may share it. After an internally generated debounce time, I/O CLOCK is
inhibited, thus preventing any further change in the internal state.
When CS is subsequently brought low again, the device is reset. CS must be held low for an internal debounce
time before the reset operation takes effect. After CS is debounced low, I/O CLOCK must remain inactive (low)
for a minimum time before a new I/O cycle can start.
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TLV2556-EP
SLAS598A – NOVEMBER 2008 – REVISED JULY 2009 ................................................................................................................................................... www.ti.com
CS can interrupt any ongoing data transfer or any ongoing conversion. When CS is debounced low long enough
before the end of the current conversion cycle, the previous conversion result is saved in the internal output
buffer and shifted out during the next I/O cycle.
When CS is held low continuously for multiple cycles, the first data bit of the newly completed conversion occurs
on DATA OUT on the rising edge of EOC or falling edge of INT. Note that the first cycle in the series still requires
a transition of CS from high to low. When a new conversion is started after the last falling edge of I/O CLOCK,
EOC goes low and the serial output is forced low until EOC goes high again.
When CS is toggled between conversions, the first data bit occurs on DATA OUT on the falling edge of CS. On
each subsequent falling edge of I/O CLOCK after the first data bit appears, the data is changed to the next bit in
the serial conversion result until the required number of bits has been output.
Power-Down Features
When command (D7–D4) 1110b is clocked into the input data register during the first four I/O CLOCK cycles, the
software power-down mode is selected. Software power down is activated on the falling edge of the fourth I/O
CLOCK pulse.
During software power down, all internal circuitry is put in a low-current standby mode. The internal reference (if
being used) is powered down. No conversion is performed. The internal output buffer keeps the previous
conversion cycle data results provided that all digital inputs are held above VCC – 0.5 V or below 0.5 V. The I/O
logic remains active so the current I/O cycle must be completed even when the power-down mode is selected.
Upon power-on reset and before the first I/O cycle, the converter normally begins in the power-down mode. The
device remains in the software power-down mode until a valid input address (other than command 1110b) is
clocked in. Upon completion of that I/O cycle, a normal conversion is performed with the results being shifted out
during the next I/O cycle. If using the internal reference, care must be taken to allow the reference to power on
completely before a valid conversion can be performed. It requires 1 ms to resume from a software power down.
The ADC also has an auto power-down mode. This is transparent to users. The ADC goes into auto power down
within one I/O CLOCK cycle after the conversion is complete and resumes, with a small delay after an active CS
is sent to the ADC. This mode keeps built-in reference so resumption is fast enough to be used between cycles.
Analog Multiplexer
The 11 analog inputs, three internal voltages, and power-down mode are selected by the input multiplexer
according to the input addresses shown in Table 2. The input multiplexer is a break-before-make type to reduce
input-to-input noise rejection resulting from channel switching. Sampling of the analog inputs starts on the falling
edge of the fourth I/O CLOCK and continues for the remaining I/O CLOCK pulses. The sample is held on the
falling edge of the last I/O CLOCK pulse. The three internal test inputs are applied to the multiplexer, then
sampled and converted in the same manner as the external analog inputs. The first conversion after the device
has returned from the power-down state may not read accurately due to internal device settling.
32
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TLV2556MPWREP
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
TL2556EP
V62/08622-01XE
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
TL2556EP
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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