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TLV271, TLV272, TLV274
SLOS351E – FEBRUARY 2004 – REVISED NOVEMBER 2016
TLV27x Family of 550-µA/Ch, 3-MHz, Rail-to-Rail Output
Operational Amplifiers
1 Features
3 Description
•
•
•
•
•
•
•
•
Operating from 2.7 V to 16 V over the extended
industrial temperature range from -40°C to +125°C,
the TLV27x is a low power, wide bandwidth
operational amplifier (opamp) with rail to rail output.
This makes it an ideal alternative to the TLC27x
family for applications where rail-to-rail output swings
are essential. The TLV27x provides 3-MHz bandwidth
from only 550 µA.
1
•
•
Rail-to-Rail Output
Wide Bandwidth: 3 MHz
High Slew Rate: 2.4 V/µs
Supply Voltage Range: 2.7 V to 16 V
Supply Current: 550 µA/Channel
Input Noise Voltage: 39 nV/√Hz
Input Bias Current: 1 pA
Specified Temperature Range:
– Commercial Grade: 0°C to 70°C
– Industrial Grade: −40°C to 125°C
Ultrasmall Packaging:
– 5-Pin SOT-23 (TLV271)
– 8-Pin MSOP (TLV272)
Ideal Upgrade for TLC72x Family
2 Applications
•
•
•
•
•
•
•
E-Bike
Power Banks
Smoke detectors
Solar Inverters
Low-Power Motor Controls
Battery-Powered Instruments
Building Automation
Operational Amplifier
Like the TLC27x, the TLV27x is fully specified for 5-V
and ±5-V supplies. The maximum recommended
supply voltage is 16 V, which allows the devices to be
operated from a variety of rechargeable cells (±8 V
supplies down to ±1.35 V).
The CMOS inputs enable use in high-impedance
sensor interfaces, with the lower voltage operation
making an attractive alternative for the TLC27x in
battery-powered applications.
All members are available in PDIP and SOIC with the
singles in the small SOT-23 package, duals in the
MSOP, and quads in the TSSOP package.
The 2.7-V operation makes it compatible with Li-Ion
powered systems and the operating supply voltage
range of many micropower microcontrollers available
today including TI’s MSP430.
Device Information(1)
PART NUMBER
TLV271
−
+
Copyright © 2016,
Texas Instruments Incorporated
TLV272
TLV274
PACKAGE
BODY SIZE (NOM)
SOIC (8)
4.98 mm × 3.91 mm
SOT-23 (5)
2.90 mm × 1.60 mm
PDIP (8)
9.81 mm × 6.35 mm
SOIC (8)
4.98 mm × 3.91 mm
PDIP (8)
9.81 mm × 6.35 mm
VSSOP (8)
3.00 mm × 3.00 mm
SOIC (14)
8.65 mm × 3.91 mm
PDIP (14)
3.90 mm × 6.35 mm
TSSOP (14)
5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLV271, TLV272, TLV274
SLOS351E – FEBRUARY 2004 – REVISED NOVEMBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
Absolute Maximum Ratings ...................................... 6
Recommended Operating Conditions....................... 6
Thermal Information: TLV271 ................................... 7
Thermal Information: TLV272 ................................... 7
Thermal Information: TLV274 ................................... 7
Electrical Characteristics: DC Characteristics........... 8
Electrical Characteristics: Input Characteristics........ 8
Electrical Characteristics: Output Characteristics ..... 9
Electrical Characteristics: Power Supply ................ 10
Electrical Characteristics: Dynamic Performance . 10
Electrical Characteristics: Noise/Distortion
Performance............................................................. 10
7.12 Typical Characteristics .......................................... 11
8
Detailed Description ............................................ 16
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
16
16
17
17
Application and Implementation ........................ 18
9.1 Application Information............................................ 18
9.2 Typical Application ................................................. 18
9.3 System Examples .................................................. 19
10 Power Supply Recommendations ..................... 21
11 Layout................................................................... 21
11.1 Layout Guidelines ................................................. 21
11.2 Layout Example .................................................... 22
12 Device and Documentation Support ................. 23
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resource............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
23
23
23
23
23
23
24
13 Mechanical, Packaging, and Orderable
Information ........................................................... 24
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (February 2004) to Revision E
Page
•
Added Feature Description section, Device Functional Modes, Application and Implementation section, Power
Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical,
Packaging, and Orderable Information section ..................................................................................................................... 1
•
Deleted Continuous total power dissipation parameter from Absolute Maximum Ratings..................................................... 6
•
Deleted Dissipation Ratings table .......................................................................................................................................... 7
•
Deleted Macromodel Information ......................................................................................................................................... 21
2
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Copyright © 2004–2016, Texas Instruments Incorporated
Product Folder Links: TLV271 TLV272 TLV274
TLV271, TLV272, TLV274
www.ti.com
SLOS351E – FEBRUARY 2004 – REVISED NOVEMBER 2016
5 Device Comparison Table
VDD (V)
VIO (μV)
IQ/Ch (μA)
IIB (pA)
GBW (MHz)
SR (V/μs)
SHUTDOWN
RAIL-TO-RAIL
SINGLES/
DUALS/
QUADS
2.7 to 16
500
550
1
3
2.4
—
O
S/D/Q
TLC27x
3 to 16
1100
675
1
1.7
3.6
—
—
S/D/Q
TLV237x
2.7 to 16
500
550
1
3
2.4
Yes
I/O
S/D/Q
TLC227x
2.7 to 16
300
1100
1
2.2
3.6
—
O
D/Q
TLV246x
2.7 to 6
150
550
1300
6.4
1.6
Yes
I/O
S/D/Q
TLV247x
2.7 to 6
250
600
2
2.8
1.5
Yes
I/O
S/D/Q
TLV244x
2.7 to 10
300
725
1
1.8
1.4
—
O
D/Q
DEVICE
TLV27x
(1)
(1)
Typical values measured at 5 V, 25°C.
Copyright © 2004–2016, Texas Instruments Incorporated
Product Folder Links: TLV271 TLV272 TLV274
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TLV271, TLV272, TLV274
SLOS351E – FEBRUARY 2004 – REVISED NOVEMBER 2016
www.ti.com
6 Pin Configuration and Functions
TLV271: DBV Package
5-Pin SOT-23
Top View
OUT
1
GND
5
TLV271: D and P Packages
8-Pin SOIC and PDIP
Top View
VDD
2
3
IN+
4
IN-
NC
1
8
NC
IN-
2
7
VDD
IN+
3
6
OUT
GND
4
5
NC
Pin Functions
PIN
TLV271
NAME
I/O
DESCRIPTION
SOT-23
SOIC
PDIP
GND
2
4
—
IN–
4
2
I
Negative (inverting) input
IN+
3
3
I
Positive (noninverting) input
NC
—
1, 5, 8
—
No internal connection (can be left floating)
OUT
1
6
O
Output
VDD
5
7
—
Positive (highest) supply
Negative (lowest) supply or ground (for single-supply operation)
TLV272: D, DGK, and P Packages
8-Pin SOIC, VSSOP, and PDIP
Top View
1OUT
1
8
VDD
1IN-
2
7
2OUT
1IN+
3
6
2IN-
GND
4
5
2IN+
Pin Functions
PIN
TLV272
NAME
SOIC
VSSOP
PDIP
I/O
DESCRIPTION
GND
4
—
1IN–
2
I
Inverting input, channel 1
1IN+
3
I
Noninverting input, channel 1
2IN–
6
I
Inverting input, channel 2
2IN+
5
I
Noninverting input, channel 2
1OUT
1
O
Output, channel 1
2OUT
7
O
Output, channel 2
VDD
8
—
Positive (highest) supply
4
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Negative (lowest) supply or ground (for single-supply operation)
Copyright © 2004–2016, Texas Instruments Incorporated
Product Folder Links: TLV271 TLV272 TLV274
TLV271, TLV272, TLV274
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SLOS351E – FEBRUARY 2004 – REVISED NOVEMBER 2016
TLV274: D, PW, and N Packages
14-Pin SOIC, TSSOP, and PDIP
Top View
1OUT
1
14
4OUT
1IN-
2
13
4IN-
1IN+
3
12
4IN+
VDD
4
11
GND
2IN+
5
10
3IN+
2IN-
6
9
3IN-
2OUT
7
8
3OUT
Pin Functions
PIN
TLV274
NAME
SOIC
TSSOP
PDIP
I/O
DESCRIPTION
GND
11
—
1IN–
2
I
Negative supply or ground (for single-supply operation)
Inverting input, channel 1
1IN+
3
I
Noninverting input, channel 1
2IN–
6
I
Inverting input, channel 2
2IN+
5
I
Noninverting input, channel 2
3IN–
9
I
Inverting input, channel 3
3IN+
10
I
Noninverting input, channel 3
4IN–
13
I
Inverting input, channel 4
4IN+
12
I
Noninverting input, channel 4
1OUT
1
O
Output, channel 1
2OUT
7
O
Output, channel 2
3OUT
8
O
Output, channel 3
4OUT
14
O
Output, channel 4
VDD
4
—
Positive supply
Copyright © 2004–2016, Texas Instruments Incorporated
Product Folder Links: TLV271 TLV272 TLV274
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TLV271, TLV272, TLV274
SLOS351E – FEBRUARY 2004 – REVISED NOVEMBER 2016
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
Supply, VDD
Voltage
Current
V
V
–VDD
VDD
Input, VI
−0.2
VDD + 0.2
V
Input, II
–10
10
mA
Operating, TA
–100
100
mA
C-suffix
0
70
°C
I-suffix
–40
125
°C
150
°C
150
°C
Junction, TJ
Storage, Tstg
(1)
UNIT
16.5
Differential input, VID
Output, IO
Temperature
MAX
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage
values, except differential voltages, are with respect to GND.
7.2 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
Supply voltage, VDD
Single-supply
Split-supply
2.7
16
±8
0
VDD −1.35
6
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C-suffix
I-suffix
MAX
±1.35
Common-mode input voltage, VICR
Operating free-air temperature, TA
NOM
0
70
–40
125
UNIT
V
V
°C
Copyright © 2004–2016, Texas Instruments Incorporated
Product Folder Links: TLV271 TLV272 TLV274
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SLOS351E – FEBRUARY 2004 – REVISED NOVEMBER 2016
7.3 Thermal Information: TLV271
TLV271
THERMAL METRIC (1)
D
(SOIC)
DBV
(SOT-23)
P
(PDIP)
UNIT
8 PINS
5 PINS
8 PINS
RθJA
Junction-to-ambient thermal resistance
127.2
221.7
49.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
71.6
144.7
39.4
°C/W
RθJB
Junction-to-board thermal resistance
68.2
49.7
26.4
°C/W
ψJT
Junction-to-top characterization parameter
22
26.1
15.4
°C/W
ψJB
Junction-to-board characterization parameter
67.6
49
26.3
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
n/a
n/a
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.4 Thermal Information: TLV272
TLV272
THERMAL METRIC (1)
D
(SOIC)
DGK
(VSSOP)
P
(PDIP)
UNIT
8 PINS
8 PINS
8 PINS
RθJA
Junction-to-ambient thermal resistance
127.2
186.6
49.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
71.6
78.8
39.4
°C/W
RθJB
Junction-to-board thermal resistance
68.2
107.9
26.4
°C/W
ψJT
Junction-to-top characterization parameter
22
15.5
15.4
°C/W
ψJB
Junction-to-board characterization parameter
67.6
106.3
26.3
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
n/a
n/a
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Thermal Information: TLV274
TLV274
THERMAL METRIC (1)
D
(SOIC)
N
(PDIP)
PW
(TSSOP)
UNIT
14 PINS
14 PINS
14 PINS
RθJA
Junction-to-ambient thermal resistance
97
66.3
135
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
56
20.5
45
°C/W
RθJB
Junction-to-board thermal resistance
53
26.8
66
°C/W
ψJT
Junction-to-top characterization parameter
19
2.1
n/a
°C/W
ψJB
Junction-to-board characterization parameter
46
26.2
60
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
n/a
n/a
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2004–2016, Texas Instruments Incorporated
Product Folder Links: TLV271 TLV272 TLV274
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TLV271, TLV272, TLV274
SLOS351E – FEBRUARY 2004 – REVISED NOVEMBER 2016
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7.6 Electrical Characteristics: DC Characteristics
at specified free-air temperature, VDD = 2.7 V, 5 V, and ±5 V (unless otherwise noted)
PARAMETER
VIO
Input offset voltage
αVIO
Offset voltage drift
Common-mode
rejection ratio
VDD = 2.7 V
VDD = 5 V
VIC = –5 V to VDD − 1.35 V,
RS = 50 Ω
VDD = ±5 V
AVD
VO(PP) = VDD/2,
RL = 10 kΩ
VDD = 5 V
VDD = ±5 V
(1)
MAX
0.5
5
7
25°C
VIC = 0 to VDD − 1.35 V,
RS = 50 Ω
TYP
Full range
VDD = 2.7 V
Large-signal differential
voltage amplification
MIN
25°C
VIC = VDD/2, RL = 10 kΩ, VO = VDD/2, RS = 50 Ω
VIC = 0 to VDD − 1.35 V,
RS = 50 Ω
CMRR
TA (1)
TEST CONDITIONS
2
25°C
58
Full range
55
25°C
65
Full range
62
25°C
69
Full range
66
25°C
97
Full range
76
25°C
100
Full range
86
25°C
100
Full range
90
UNIT
mV
µV/°C
70
80
dB
85
106
110
dB
115
Full range is 0°C to 70°C for C-suffix and full range is –40°C to 125°C for I-suffix. If not specified, full range is –40°C to 125°C.
7.7 Electrical Characteristics: Input Characteristics
at specified free-air temperature, VDD = 2.7 V, 5 V, and ±5 V (unless otherwise noted).
PARAMETER
TEST CONDITIONS
TA
MIN
25°C
IIO
Input offset current
VDD = 5 V, VIC = VDD/2,
VO = VDD/2, RS = 50 Ω
Input bias current
ri(d)
Differential input resistance
CIC
Common-mode input
capacitance
8
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VDD = 5 V, VIC = VDD/2,
VO = VDD/2, RS = 50 Ω
f = 21 kHz
MAX
1
60
70°C
100
125°C
1000
25°C
IIB
TYP
1
UNIT
pA
60
70°C
100
125°C
1000
pA
25°C
1000
GΩ
25°C
8
pF
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SLOS351E – FEBRUARY 2004 – REVISED NOVEMBER 2016
7.8 Electrical Characteristics: Output Characteristics
at specified free-air temperature, VDD = 2.7 V, 5 V, and ±5 V (unless otherwise noted).
PARAMETER
TEST CONDITIONS
VDD = 2.7 V
VIC = VDD/2, IOH = –1 mA VDD = 5 V
VDD = ±5 V
VOH
High-level output voltage
VDD = 2.7 V
VIC = VDD/2, IOH = –5 mA VDD = 5 V
VDD = ±5 V
VDD = 2.7 V
VIC = VDD/2, IOH = 1 mA
VDD = 5 V
VDD = ±5 V
VOL
Low-level output voltage
VDD = 2.7 V
VIC = VDD/2, IOH = 5 mA
VDD = 5 V
VDD = ±5 V
IO
Output current
TA
MIN
TYP
25°C
2.55
2.58
Full range
2.48
25°C
4.9
Full range
4.85
25°C
4.92
Full range
4.9
25°C
1.9
Full range
1.5
25°C
4.6
Full range
4.5
25°C
4.7
Full range
4.65
25°C
4.96
4.68
4.84
0.05
Full range
Full range
0.28
0.4
–4.84
–4.7
V
0.5
Full range
–4.65
VO = 0.5 V from rail,
VDD = 2.7 V
Positive rail
25°C
4
Negative rail
25°C
5
VO = 0.5 V from rail,
VDD = 5 V
Positive rail
25°C
7
Negative rail
25°C
8
VO = 0.5 V from rail,
VDD = 10 V
Positive rail
25°C
13
Negative rail
25°C
12
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0.7
1.1
Full range
Copyright © 2004–2016, Texas Instruments Incorporated
–4.92
–4.9
0.5
25°C
0.1
0.15
–4.95
25°C
0.15
0.22
Full range
25°C
V
2.1
0.1
25°C
UNIT
4.93
Full range
25°C
MAX
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mA
9
TLV271, TLV272, TLV274
SLOS351E – FEBRUARY 2004 – REVISED NOVEMBER 2016
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7.9 Electrical Characteristics: Power Supply
at specified free-air temperature, VDD = 2.7 V, 5 V, and ±5 V (unless otherwise noted).
PARAMETER
Supply current
(per channel)
IDD
VO = VDD/2
(1)
Supply voltage rejection
ratio
(ΔVDD /ΔVIO)
MIN
TYP
MAX
VDD = 2.7 V
25°C
470
560
VDD = 5 V
25°C
550
660
25°C
625
800
VDD = 10 V
PSRR
TA (1)
TEST CONDITIONS
VDD = 2.7 V to 16 V, VIC = VDD/2, no load
Full range
UNIT
µA
1000
25°C
70
Full range
65
80
dB
Full range is 0°C to 70°C for C-suffix and full range is –40°C to 125°C for I-suffix. If not specified, full range is –40°C to 125°C.
7.10 Electrical Characteristics: Dynamic Performance
over operating free-air temperature range (unless otherwise noted).
PARAMETER
UGBW
Unity-gain bandwidth RL = 2 kΩ, CL = 10 pF
Slew rate at unity
gain
VO(PP) = VDD/2,
CL = 50 pF,
RL = 10 kΩ
tS
(1)
TYP
25°C
2.4
VDD = 5 V to 10 V
25°C
3
VDD = 5 V
VDD = ±5 V
φm
MIN
VDD = 2.7 V
VDD = 2.7 V
SR
TA (1)
TEST CONDITIONS
25°C
Full range
1.35
MAX
2.1
1
25°C
1.45
Full range
1.2
25°C
1.8
Full range
1.3
2.4
2.6
UNIT
MHz
V/µs
V/µs
V/µs
Phase margin
RL = 2 kΩ
CL = 10 pF
25°C
65
°
Gain margin
RL = 2 kΩ
CL = 10 pF
25°C
18
dB
VDD = 2.7 V,
V(STEP)PP = 1 V,
AV = –1,
CL = 10 pF
RL = 2 kΩ
0.1%
VDD = 5 V, ±5 V
V(STEP)PP = 1 V,
AV = –1,
CL = 47 pF
RL = 2 kΩ
0.1%
Setting time
2.9
25°C
µs
2
Full range is 0°C to 70°C for C suffix and full range is –40°C to 125°C for I suffix. If not specified, full range is –40°C to 125°C.
7.11 Electrical Characteristics: Noise/Distortion Performance
over operating free-air temperature range (unless otherwise noted).
PARAMETER
THD + N
Total harmonic distortion
plus noise
Vn
Equivalent input noise
voltage
In
Equivalent input noise
current
10
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TEST CONDITIONS
VDD = 2.7 V,
VO(PP) = VDD/2 V,
RL = 2 kΩ , f = 10 kHz
VDD = 5 V, ±5 V,
VO(PP) = VDD/2 V,
RL = 2 kΩ , f = 10 kHz
TA
AV = 1
MIN
TYP MAX
UNIT
0.02%
AV = 10
25°C
AV = 100
0.05%
0.18%
AV = 1
0.02%
AV = 10
25°C
AV = 100
0.09%
0.5%
f = 1 kHz
25°C
f = 10 kHz
f = 1 kHz
25°C
39
35
0.6
nV/√Hz
fA /√Hz
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SLOS351E – FEBRUARY 2004 – REVISED NOVEMBER 2016
7.12 Typical Characteristics
Table 1. Table of Graphs
DESCRIPTION
CMRR
FIGURE NO.
Common-mode rejection ratio
vs Frequency
Input bias and offset current
vs Free-air temperature
Figure 1
Figure 2
VOL
Low-level output voltage
vs Low-level output current
Figure 3,
Figure 5, Figure 7
VOH
High-level output voltage
vs High-level output current
Figure 4,
Figure 6, Figure 8
VO(PP)
Peak-to-peak output voltage
vs Frequency
Figure 9
IDD
Supply current
vs Supply voltage
Figure 10
PSRR
Power-supply rejection ratio
vs Frequency
Figure 11
AVD
Differential voltage gain and phase
vs Frequency
Figure 12
Gain-bandwidth product
vs Free-air temperature
Figure 13
vs Supply voltage
Figure 14
vs Free-air temperature
Figure 15
Figure 16
SR
Slew rate
φm
Phase margin
vs Capacitive load
Vn
Equivalent input noise voltage
vs Frequency
Figure 17
Figure 18,
Figure 19
Voltage-follower large-signal pulse response
Voltage-follower small-signal pulse response
Figure 20
Inverting large-signal response
Figure 21,
Figure 22
Inverting small-signal response
Figure 23
Crosstalk
vs Frequency
300
Input Bias and Offset Current (pA)
120
Common-Mode Rejection Ratio (dB)
Figure 24
100
VDD = 5 V, 10 V
80
60
VDD = 2.7 V
40
20
0
250
VDD = 2.7 V, 5 V, and 10 V
VIC = VDD/2
200
150
100
50
0
-50
10
100
1k
10 k
Frequency (Hz)
100 k
Figure 1. Common-Mode Rejection Ratio vs
Frequency
1M
-40 -25 -10
5
20 35 50 65
Temperature (°C)
80
95
110 125
Figure 2. Input Bias and Offset Current vs
Free-Air Temperature
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2.8
2.8
VDD = 2.7 V
2.4
High-Level Output Voltage (V)
Low-Level Output Voltage (V)
TA = 125°C
2
TA = 70°C
1.6
TA = 0°C
1.2
TA = 25°C
0.8
TA = -40°C
0.4
2.4
TA = -40°C
2
TA = 0°C
TA = 125°C
1.6
TA = 70°C
1.2
TA = 25°C
0.8
0.4
VDD = 2.7 V
0
0
0
2
4
6
8 10 12 14 16 18
Low-Level Output Current (mA)
20
22
24
0
Figure 3. Low-Level Output Voltage vs
Low-Level Output Current
5
High-Level Output Voltage (V)
Low-Level Output Voltage (V)
3.5
TA = 70°C
3
TA = 0°C
2.5
2
TA = 25°C
1.5
TA = -40°C
1
12
4
TA = 0°C
3.5
TA = -40°C
3
TA = 25°C
2.5
2
TA = 70°C
1.5
1
TA = 125°C
0
0
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70
Low-Level Output Current (mA)
0
Figure 5. Low-Level Output Voltage vs
Low-Level Output Current
5
10
15
20
25
30
35
High-Level Output Current (mA)
45
40
Figure 6. High-Level Output Voltage vs
High-Level Output Current
10
10
TA = 125°C
High-Level Output Voltage (V)
VDD = 10 V
Low-Level Output Voltage (V)
11
VCC = 5 V
4.5
0.5
0.5
8
TA = 70°C
6
TA = 25°C
4
TA = 0°C
2
TA = -40°C
TA = -40°C
VDD = 10 V
8
TA = 0°C
6
TA = 25°C
4
TA = 70°C
2
TA = 125°C
0
0
0
20
40
60
80
Low-Level Output Current (mA)
100
Figure 7. Low-Level Output Voltage vs
Low-Level Output Current
12
10
5
TA = 125°C
4
3
4
5
6
7
8
9
High-Level Output Current (mA)
Figure 4. High-Level Output Voltage vs
High-Level Output Current
VDD = 5 V
4.5
2
1
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0
20
40
60
80
100
High-Level Output Current (mA)
120
Figure 8. High-Level Output Voltage vs
High-Level Output Current
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1
VDD = 10 V
AV = -10
RL = 2 kW
CL = 10 pF
TA = 25°C
THD = 5%
9
8
7
6
VDD = 5 V
5
4
VDD = 2.7 V
3
AV = 1
VIC = VDD/2
0.9
Supply Current (mA/ch)
TA = 70°C
0.7
0.6
0.5
TA = 25°C
0.4
TA = 0°C
0.3
TA = -40°C
2
0.2
1
0.1
0
0
10
100
1k
10 k
100 k
Frequency (Hz)
1M
0
10 M
1
2
Figure 9. Peak-to-Peak Output Voltage vs
Frequency
3
5
4
6 7 8 9 10 11 12 13 14 15
Supply Voltage (V)
Figure 10. Supply Current vs
Supply Voltage
120
120
TA = 25°C
Differential Voltage Gain (dB)
Power-Supply Rejection Ratio (dB)
TA = 125°C
0.8
100
VDD = 5 V, 10 V
80
VDD = 2.7 V
60
40
20
0
180
100
135
Phase
80
90
60
45
Gain
40
0
20
-45
VDD = 5 V
RL = 2 kW
CL = 10 pF
TA = 25°C
0
-20
-90
-135
-40
10
100
1k
10 k
Frequency (Hz)
100 k
-180
10
1M
Phase (°)
Peak-to-Peak Output Voltage (V)
11
10
SLOS351E – FEBRUARY 2004 – REVISED NOVEMBER 2016
100
Figure 11. Power-Supply Rejection Ratio vs
Frequency
1k
10 k
100 k
Frequency (Hz)
1M
10 M
Figure 12. Differential Voltage Gain and Phase
3
4
3
2.5
2.5
VDD = 10 V
SR +
VDD = 5 V
Slew Rate (V/ms)
Gain Bandwidth Product (MHz)
SR -
3.5
VDD = 2.7 V
2
1.5
2
1.5
1
AV = 1
RL = 10 kW
CL = 50 pF
TA = 25°C
1
0.5
0.5
0
0
-40 -25 -10
5
20 35 50 65
Temperature (°C)
80
95
110 125
2.5
4.5
Figure 13. Gain Bandwidth Product vs
Free-Air Temperature
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6.5
8.5
10.5
Supply Voltage (V)
12.5
14.5
Figure 14. Slew Rate vs
Supply Voltage
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100
3.5
90
3
SR -
80
SR +
2
1.5
VDD = 5 V
AV = 1
RL = 10 kW
CL = 50 pF
VI = 3 V
1
0.5
70
Phase Margin (°)
RNULL = 100 W
60
50
RNULL = 0 W
40
VDD = 5 V
RL = 2 kW
TA = 25°C
AV = Open Loop
30
20
10
0
0
5
20 35 50 65
Temperature (°C)
80
95
10
110 125
100
Capacitive Load (pF)
Figure 15. Slew Rate vs
Free-Air Temperature
Figure 16. Phase Margin vs
Capacitive Load
Input Voltage (V)
Equivalent Input Noise Voltage (nV/ÖHz)
100
VDD = 2.7 V, 5 V, and 10 V
TA = 25°C
90
80
70
60
4
3
VDD = 5 V
AV = 1
RL = 2 kW
CL = 10 pF
VI = 3 VPP
TA = 25°C
2
1
0
VI
50
40
3
30
2
20
1
VO
10
0
0
10
100
1k
Frequency (Hz)
10 k
100 k
0
Figure 17. Equivalent Input Noise Voltage vs
Frequency
Input Voltage (mV)
8
6
4
2
VDD = 10 V, AV = 1
RL = 2 kW, CL = 10 pF
VI = 6 VPP ,TA = 25°C
VI
0
6
4
2
VO
0
0
2
4
6
8
10 12
Time (ms)
14
16
18
Figure 19. Voltage-Follower Large-Signal
Pulse Response
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2
4
6
8
10 12
Time (ms)
14
16
18
Figure 18. Voltage-Follower Large-Signal
Pulse Response
Output Voltage (V)
Input Voltage (V)
1000
Output Voltage (V)
-40 -25 -10
14
RNULL = 50 W
0.12
VDD = 5 V
AV = 1
RL = 2 kW
CL = 10 pF
VI = 100 mVPP
TA = 25°C
0.08
0.04
VI
0
0.12
0.08
0.01
VO
0
0
0.2
0.4
0.6
0.8
1 1.2
Time (ms)
1.4
1.6
Output Voltage (mV)
Slew Rate (V/ms)
2.5
1.8
Figure 20. Voltage-Follower Small-Signal
Pulse Response
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2
1
VI
0
VDD = 5 V, AV = 1
RL = 2 kW, CL = 10 pF
VI = 3 VPP ,TA = 25°C
3
2
1
VO
0
0
4
2
6
8
10
Time (ms)
12
14
8
6
4
VDD = 10 V
AV = VI = -1
RL = 2 kW
CL = 10 pF
TA = 25°C
2
0
16
0
0.05
0
Crosstalk (dB)
0.1
Output Voltage (V)
Input Voltage (V)
VO
4
6
8
10
Time (ms)
12
14
16
VDD = 2.7 V, 5 V, and 10 V
VI = 1 VDD/2
AV = 1
RL = 2 kW
TA = 25°C
-20
0
2
Figure 22. Inverting Large-Signal Response
0.1
VDD = 5 V
AV = VI = -1
RL = 2 kW
CL = 10 pF
VI = 100 mVPP
TA = 25°C
4
0
0
VI
6
VO
2
Figure 21. Inverting Large-Signal Response
0.05
VI
Output Voltage (V)
Input Voltage (V)
4
3
Output Voltage (V)
Input Voltage (V)
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-40
-60
-80
-100
Crosstalk
-120
-140
0
0.5
1
1.5
2 2.5
Time (ms)
3
3.5
4
4.5
Figure 23. Inverting Small-Signal Response
10
100
1k
Frequency (Hz)
10 k
100 k
Figure 24. Crosstalk vs Frequency
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8 Detailed Description
8.1 Overview
The TLV27x operates from a single power supply and consumes only 550 µA of quiescent current. With rail-torail output swing capability and 3-MHz bandwidth, the TLV27x is ideal for battery-powered and industrial
applications.
8.2 Functional Block Diagram
VDD
Bias
OUT
IN+
IN±
GND
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8.3 Feature Description
8.3.1 Rail to Rail Output
The TLV27x family of opamps features a rail to trail output stage. Rail to rail outputs allow for a wide dynamic
range in low voltage systems. This feature along with low power and wide bandwidth make the TLV27x family
suitable for portable and battery powered systems.
8.3.2 Offset Voltage
The output offset voltage (VOO) is the sum of the input offset voltage (VIO) and both input bias currents (IIB) times
the corresponding gains. Use the schematic in Figure 25 and Equation 1 to calculate the output offset voltage:
RF
IIB-
RG
+
VI
RS
−
VO
+
IIB+
Copyright © 2016, Texas Instruments Incorporated
Figure 25. Output Offset Voltage Model
VOO = VIO 1 +
( RR ( ±I
F
IB+
RS 1 +
G
( RR ( ±I
F
G
RF
IB-
(1)
8.3.3 Driving a Capacitive Load
When the amplifier is configured in this manner, capacitive loading directly on the output decreases the device
phase margin, leading to high frequency ringing or oscillations. Therefore, for capacitive loads of greater than 10
pF, TI recommends placing a resistor in series (RNULL) with the output of the amplifier, as shown in Figure 26. A
minimum value of 20 Ω should work well for most applications.
RF
RG
Input
−
RNULL
Output
+
CLOAD
VDD/2
Copyright © 2016, Texas Instruments Incorporated
Figure 26. Driving a Capacitive Load
8.4 Device Functional Modes
The TLV27x has a single functional mode. It is operational when the power supply applied to the device is
between 2.7 V (±1.35 V) and 16 V (±8 V). Electrical parameters that can vary with operating conditions are
shown in Typical Characteristics.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TLV27x family offers outstanding DC and AC performance. These devices operate up to a 16-V power
supply and offer ultra-low input bias current and 3-MHz bandwidth. These features make the TLV27x a robust
operational amplifier for battery-powered and industrial applications.
9.2 Typical Application
2.25 k
2.25 k
1.13 k
Input
1 nF
±
4 nF
Output
+
Figure 27. Second-Order, Low-Pass Filter
9.2.1 Design Requirements
• Gain = 1 V/V
• Low-pass cutoff frequency = 50 kHz
• –40-db/dec filter response
• Maintain less than 3-dB gain peaking in the gain versus frequency response
9.2.2 Detailed Design Procedure
The infinite-gain multiple-feedback circuit for a low-pass network function is shown in Figure 27. Use Equation 2
to calculate the voltage transfer function.
1 R1R3C2C5
Output
s
2
Input
s
s C2 1 R1 1 R3 1 R4 1 R3R4C2C5
(2)
This circuit produces a signal inversion. For this circuit, the gain at DC and the low-pass cutoff frequency are
calculated by Equation 3:
R4
Gain
R1
fC
18
1
2S
1 R3R 4 C2C5
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Typical Application (continued)
Software tools are readily available to simplify filter design. WEBENCH® Filter Designer is a simple, powerful,
and easy-to-use active filter design program. The WEBENCH® Filter Designer lets you create optimized filter
designs using a selection of TI operational amplifiers and passive components from TI's vendor partners.
Available as a web-based tool from the WEBENCH Design Center, WEBENCH Filter Designer allows you to
design, optimize, and simulate complete multistage active filter solutions within minutes.
9.2.3 Application Curve
20
Gain (db)
0
-20
-40
-60
100
1k
10k
Frequency (Hz)
100k
1M
Figure 28. TLV27x Second-Order, 50-kHz, Low-Pass Filter
9.3 System Examples
9.3.1 General Configurations
When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often required.
The simplest way to accomplish this limiting is to place an RC filter at the noninverting terminal of the amplifier
(see Figure 29 and Equation 4).
RG
RF
VDD/2
−
VI
+
R1
VO
C1
Copyright © 2016, Texas Instruments Incorporated
Figure 29. Single-Pole Low-Pass Filter
VO
R
= 1+ F
VI
RG
(
f-3db =
((1 + sR1 C (
1
1
1
2pR1C1
(4)
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System Examples (continued)
If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter, shown in Figure 30,
can be used for this task. For best results, the amplifier should have a bandwidth that is 8 to 10 times the filter
frequency bandwidth; refer to Equation 5. Failure to use an amplifier with this characteristic can result in phase
shift of the amplifier.
C1
VI
−
R1
R2
C2
RG
+
RF
VDD/2
Copyright © 2016, Texas Instruments Incorporated
Figure 30. Two-Pole, Low-Pass, Sallen-Key Filter
R1= R2= R
C1= C2= C
Q = Peaking Factor
(ButterworthQ = 0.707)
f-3db =
1
2pRC
RF
RG =
20
(2 - 1Q (
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10 Power Supply Recommendations
The TLV27x is specified for operation from 2.7 V to 16 V (±1.35 V to ±8 V); many specifications apply from
–40°C to 125°C. Parameters that can exhibit significant variance with regard to operating voltage or temperature
are presented in the Typical Characteristics.
CAUTION
Supply voltages larger than 16.5 V can permanently damage the device; see the
Absolute Maximum Ratings.
Place 0.1-µF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or highimpedance power supplies. For more detailed information on bypass capacitor placement, see Layout
Guidelines.
11 Layout
11.1 Layout Guidelines
To achieve the levels of high performance of the TLV27x, follow proper printed circuit board (PCB) design
techniques. A general set of guidelines is given in the following.
• Ground planes—TI highly recommends using a ground plane on the board to provide all components with a
low-inductive ground connection. However, in the areas of the amplifier inputs and output, the ground plane
can be removed to minimize the stray capacitance.
• Proper power supply decoupling—Use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic capacitor
on each supply terminal. It may be possible to share the tantalum among several amplifiers depending on the
application, but a 0.1-µF ceramic capacitor should always be used on the supply terminal of every amplifier.
In addition, the 0.1-µF capacitor should be placed as close as possible to the supply terminal. As this distance
increases, the inductance in the connecting trace makes the capacitor less effective. The designer should
strive for distances of less than 0.1 inches between the device power terminals and the ceramic capacitors.
• Sockets—Sockets can be used but are not recommended. The additional lead inductance in the socket pins
often leads to stability problems. Surface-mount packages soldered directly to the printed-circuit board is the
best implementation.
• Short trace runs/compact part placements—Optimum high performance is achieved when stray series
inductance has been minimized. To realize this, the circuit layout should be made as compact as possible,
thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting input of the
amplifier. Its length should be kept as short as possible. This helps to minimize stray capacitance at the input
of the amplifier.
• Surface-mount passive components—Using surface-mount passive components is recommended for high
performance amplifier circuits for several reasons. First, because of the extremely low lead inductance of
surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small
size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray
inductance and capacitance. If leaded components are used, TI recommends keeping the lead lengths as
short as possible.
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11.2 Layout Example
+
VIN
VOUT
RG
RF
(Schematic Representation)
Run the input traces
as far away from
the supply lines
as possible
Place components
close to device and to
each other to reduce
parasitic errors
VS+
RF
NC
NC
GND
IN±
VDD
VIN
IN+
OUT
GND
NC
RG
Use low-ESR,
ceramic bypass
capacitor
GND
VS±
GND
Use low-ESR, ceramic
bypass capacitor
VOUT
Ground (GND) plane on another layer
Copyright © 2016, Texas Instruments Incorporated
Figure 31. TLV27x Layout Example
22
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
The following documents are relevant to using the TLV27x, and recommended for reference. All are available for
download at www.ti.com unless otherwise noted.
• Compensate Transimpedance Amplifiers Intuitively (SBOA055)
• Operational amplifier gain stability, Part 3: AC gain-error analysis (SLYT383)
• Operational amplifier gain stability, Part 2: DC gain-error analysis (SLYT374)
• Using the infinite-gain, MFB filter topology in fully differential active filters (SLYT343)
• Op Amp Performance Analysis (SBOA054)
• Single-Supply Operation of Operational Amplifiers (SBOA059)
• Tuning in Amplifiers (SBOA067)
• Shelf-Life Evaluation of Lead-Free Component Finishes (SZZA046)
12.2 Related Links
Table 2 lists quick access links. Categories include technical documents, support and community resources,
tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TLV271
Click here
Click here
Click here
Click here
Click here
TLV272
Click here
Click here
Click here
Click here
Click here
TLV274
Click here
Click here
Click here
Click here
Click here
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resource
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 Trademarks
E2E is a trademark of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
24
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PACKAGE OPTION ADDENDUM
www.ti.com
13-Aug-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TLV271CD
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
T271C
TLV271CDBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
VBHC
TLV271CDBVRG4
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
VBHC
TLV271CDBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
VBHC
TLV271CDBVTG4
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
VBHC
TLV271CDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
T271C
TLV271ID
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
T271I
TLV271IDBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
VBHI
TLV271IDBVRG4
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
VBHI
TLV271IDBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
VBHI
TLV271IDBVTG4
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
VBHI
TLV271IDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
T271I
TLV271IP
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 125
T271I
TLV272CD
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
T272C
TLV272CDG4
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
T272C
TLV272CDGK
ACTIVE
VSSOP
DGK
8
80
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
0 to 70
AVF
TLV272CDGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
0 to 70
AVF
TLV272CDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
T272C
TLV272CDRG4
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
T272C
TLV272ID
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
T272I
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
13-Aug-2021
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
NIPDAU
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TLV272IDG4
ACTIVE
SOIC
D
8
75
RoHS & Green
Level-1-260C-UNLIM
-40 to 125
T272I
TLV272IDGK
ACTIVE
VSSOP
DGK
8
80
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
AVG
TLV272IDGKG4
ACTIVE
VSSOP
DGK
8
80
RoHS & Green
Level-1-260C-UNLIM
-40 to 125
AVG
TLV272IDGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
AVG
TLV272IDGKRG4
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AVG
TLV272IDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
T272I
TLV272IDRG4
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
T272I
TLV272IP
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 125
T272I
TLV274CD
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TLV274C
TLV274CDG4
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TLV274C
TLV274CDR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TLV274C
TLV274CPW
ACTIVE
TSSOP
PW
14
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TLV274C
TLV274CPWR
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TLV274C
TLV274CPWRG4
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TLV274C
TLV274ID
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TLV274I
TLV274IDG4
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TLV274I
TLV274IDR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TLV274I
TLV274IDRG4
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TLV274I
TLV274IN
ACTIVE
PDIP
N
14
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 125
TLV274I
TLV274IPW
ACTIVE
TSSOP
PW
14
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TLV274I
TLV274IPWG4
ACTIVE
TSSOP
PW
14
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TLV274I
Addendum-Page 2
NIPDAU
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
13-Aug-2021
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TLV274IPWR
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TLV274I
TLV274IPWRG4
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TLV274I
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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