SGLS317A − OCTOBER 2005 − REVISED SEPTEMBER 2007
D Controlled Baseline
D
D
D
D
D
D
D
D
D Rail-to-Rail Output
D 360 µV Input Offset Voltage
D Low Distortion Driving 600-Ω
− One Assembly/Test Site, One Fabrication
Site
Extended Temperature Performance of
−55°C to 125°C
Enhanced Diminishing Manufacturing
Sources (DMS) Support
Enhanced Product-Change Notification
Qualification Pedigree(1)
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
High Slew Rate . . . 10.5 V/µs Typ
High-Gain Bandwidth . . . 5.1 MHz Typ
Supply Voltage Range 2.5 V to 5.5 V
D
D
D
D
D
0.005% THD+N
1 mA Supply Current (Per Channel)
17 nV/√Hz Input Noise Voltage
2 pA Input Bias Current
Characterized From TA = −55°C to 125°C
Micropower Shutdown Mode . . . IDD < 1 µA
† Component qualification in accordance with JEDEC and industry
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
description
The TLV277x CMOS operational amplifier family combines high slew rate and bandwidth, rail-to-rail output
swing, high output drive, and excellent dc precision. The device provides 10.5 V/µs of slew rate and 5.1 MHz
of bandwidth while only consuming 1 mA of supply current per channel. This ac performance is much higher
than current competitive CMOS amplifiers. The rail-to-rail output swing and high output drive make these
devices a good choice for driving the analog input or reference of analog-to-digital converters (ADCs) . These
devices also have low distortion while driving a 600-Ω load for use in telecom systems.
These amplifiers have a 360-µV input offset voltage, a 17 nV/√Hz input noise voltage, and a 2-pA input bias
current for measurement, medical, and industrial applications. The TLV277x family is also specified across an
extended temperature range (−55°C to 125°C), making it useful for military and avionics systems.
These devices operate from a 2.5-V to 5.5-V single supply voltage and are characterized at 2.7 V and 5 V. The
single-supply operation and low power consumption make these devices a good solution for portable
applications. The following table lists the packages available.
FAMILY PACKAGE TABLE
PACKAGE
TYPES
DEVICE
NUMBER
OF
CHANNELS
SOIC
TSSOP
TLV2770
1
8
—
Yes
TLV2771
1
8
—
—
TLV2772
2
8
8
—
TLV2773
2
14
—
Yes
TLV2774
4
14
14
—
TLV2775
4
16
16
Yes
SHUTDOWN
UNIVERSAL
EVM BOARD
See the EVM
Selection Guide
(SLOU060)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2007 Texas Instruments Incorporated
!"#$% ! %& % '
%( )#& % !"))$% & ( *"+, !& % &$ ) "! ! %( )#
*$! ( !& % *$) $ $)# ( $& % )"#$% &% &) -&))&%.
) "! % *) !$ %/ $ % %$!$ &) ,. %!," $ $ %/ ( &,,
*&)&#$$)
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SGLS317A − OCTOBER 2005 − REVISED SEPTEMBER 2007
SELECTION OF SINGLE-SUPPLY OPERATIONAL AMPLIFIER PRODUCTS†
DEVICE
VDD
(V)
BW
(MHz)
SLEW RATE
(V/µs)
IDD (per channel)
(µA)
TLV277X
2.5 to 6
5.1
10.5
1000
O
TLV247X
2.7 to 6
2.8
1.5
600
I/O
TLV245X
2.7 to 6
0.22
0.11
23
I/O
TLV246X
2.7 to 6
6.4
1.6
550
I/O
RAIL-TO-RAIL
† All specifications measured at 5 V.
ORDERING INFORMATION†
TA
VIOMAX
AT 25°C
(mV)
ORDERABLE
PART NUMBER
SOIC (D)
Tape and reel
1.6
SOIC (D)
Tape and reel
2.5
SOIC (D)
Tape and reel
1.6
SOIC (D)
Tape and reel
SOIC (D)
Tape and reel
TSSOP (PW)
Tape and reel
TLV2772MDREP§
TLV2772MPWREP§
SOIC (D)
Tape and reel
TLV2772AMDREP
1.6
TOP SIDE
MARKING
TLV2770MDREP§
TLV2770AMDREP§
2.5
2.5
−55°C to 125°C
PACKAGE‡
TLV2771MDREP§
TLV2771AMDREP§
2772AE
TSSOP (PW)
Tape and reel
2.5
SOIC (D)
Tape and reel
TLV2772AMPWREP§
TLV2773MDREP§
1.6
SOIC (D)
Tape and reel
TLV2773AMDREP§
SOIC (D)
Tape and reel
Tape and reel
TLV2774MDREP
TLV2774MPWREP§
2774EP
TSSOP (PW)
SOIC (D)
Tape and reel
Tape and reel
SOIC (D)
Tape and reel
TLV2774AMDREP
TLV2774AMPWREP§
TLV2775MDREP§
2774AEP
TSSOP (PW)
TSSOP(PW)
Tape and reel
SOIC (D)
Tape and reel
2.7
2.1
2.7
2.1
TLV2775MPWREP§
TLV2775AMDREP§
Tape and reel
TLV2775AMPWREP§
† For the most current package and ordering information, see the Package Option Addendum at the end of this document,
or see the TI website at www.ti.com.
‡ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available
at www.ti.com/packaging.
§ Product Preview
2
TSSOP (PW)
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SGLS317A − OCTOBER 2005 − REVISED SEPTEMBER 2007
TLV277x PACKAGE PINOUTS
TLV2770†
D PACKAGE
(TOP VIEW)
NC
IN −
IN +
GND
1OUT
1IN −
1IN+
GND
NC
1SHDN
NC
1
8
2
7
3
6
4
5
TLV2771†
D PACKAGE
(TOP VIEW)
SHDN
VDD
OUT
NC
NC
IN −
IN +
GND
1
8
2
7
3
6
4
5
TLV2772
D OR PW PACKAGE
(TOP VIEW)
NC
VDD
OUT
NC
1OUT
1IN −
1IN +
GND
1
8
2
7
3
6
4
5
VDD
2OUT
2IN −
2IN+
TLV2773†
D PACKAGE
TLV2774
D OR PW PACKAGE
TLV2775†
D OR PW PACKAGE
(TOP VIEW)
(TOP VIEW)
(TOP VIEW)
1
14
2
13
3
12
4
11
5
10
6
9
7
8
VDD
2OUT
2IN −
2IN+
NC
2SHDN
NC
1OUT
1IN −
1IN+
VDD
2IN+
2IN −
2OUT
1
14
2
13
3
12
4
11
5
10
6
9
7
8
4OUT
4IN −
4IN+
GND
3IN+
3IN −
3OUT
1OUT
1IN −
1IN+
VDD
2IN+
2IN −
2OUT
1/2SHDN
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
4OUT
4IN −
4IN+
GND
3IN +
3IN−
3OUT
3/4SHDN
NC − No internal connection
† This device is in the Product Preview stage of development. Please contact your local TI sales office for availability.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SGLS317A − OCTOBER 2005 − REVISED SEPTEMBER 2007
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Differential input voltage, VID (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±VDD
Input voltage range, VI (any input, see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VDD
Input current, II (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±4 mA
Output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Total current into VDD + . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Total current out of GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Duration of short-circuit current (at or below) 25°C (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . unlimited
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, TA: M suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential voltages, are with respect to GND .
2. Differential voltages are at the noninverting input with respect to the inverting input. Excessive current flows when input is brought
below GND − 0.3 V.
3. The output may be shorted to either supply. Temperature and /or supply voltages must be limited to ensure that the maximum
dissipation rating is not exceeded.
DISSIPATION RATING TABLE
PACKAGE
QJC (°C/W)
HIGH K
LOW K
QJA (°C/W, 0 AIR FLOW)
HIGH K
LOW K
D(8)
39.4
42.4
97.1
165.5
D(14)
51.5
53.7
86.2
133.5
D(16)
36.9
38.4
73.1
111.6
PW(8)
65.1
69.4
149.4
230.5
PW(14)
45.8
46.6
111.7
131.4
PW(16)
33.6
35
108.4
147.0
NOTE 4: Thermal resistances are not production tested and are for informational purposes only.
recommended operating conditions
M SUFFIX
Supply voltage, VDD
MIN
MAX
2.5
6
Input voltage range, VI
GND
Common-mode input voltage, VIC
GND
Operating free-air temperature, TA
−55
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
UNIT
V
VDD + − 1.3
VDD + − 1.3
V
125
°C
V
SGLS317A − OCTOBER 2005 − REVISED SEPTEMBER 2007
WIREBOND LIFE
vs
JUNCTION TEMPERATURE
100M
80°C, 17M Hrs
10M
Time-to-Fail − Hrs
90°C, 5.2M Hrs
100°C, 1.7M Hrs
1M
110°C, 580k Hrs
120°C, 210k Hrs
100k
130°C, 82k Hrs
140°C, 33k Hrs
10k
1k
80
90
100
110
120
130
140
150
TJ − Junction Temperature − °C
Figure 1. Wirebond Life Estimation
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
SGLS317A − OCTOBER 2005 − REVISED SEPTEMBER 2007
electrical characteristics at specified free-air temperature, VDD = 2.7 V (unless otherwise noted)
PARAMETER
VIO
Input offset voltage
VDD = ± 1.35 V,
VIC = 0, VO = 0,
RS = 50 Ω
TLV2774/5
αVIO
IIO
Input offset current
VDD = ± 1.35 V,
VIC = 0, VO = 0,
RS = 50 Ω
TL2770/1/2/3
VDD = ± 1.35 V,
VIC = 0, VO = 0,
RS = 50 Ω
TLV2770/1/2/3
VICR
Common-mode
input voltage range
High-level output
voltage
0.8
2
25°C
1
25°C
2
Full range
TLV2774/5
IOL = 0.675 mA
VIC = 1.35 V,
VO = 0.6 V to 2.1 V
RL = 10 kΩ,‡
AVD
ri(d)
Differential input
resistance
ci(c)
Common-mode
input capacitance
f = 10 kHz,
zo
Closed-loop
output impedance
f = 100 kHz,
AV = 10
CMRR
Common-mode
rejection ratio
VIC = VICR (min),
RS = 50 Ω
VO = 1.5 V,
kSVR
Supply voltage
rejection ratio
(∆VDD /∆VIO)
VDD = 2.7 V to 5 V,
No load
VIC = VDD /2,
IDD
Supply current
(per channel)
VO = 1.5 V,
No load
POST OFFICE BOX 655303
1
200
200
60
2
pA
500
Full range
−0.3
to
1.7
2.6
V
2.6
2.45
2.45
2.4
V
2.4
2.1
2.1
0.1
Full range
0.1
0.2
0.2
0.21
Full range
V
0.21
0.6
13
pA
60
350
0
to
1.4
Full range
60
125
−0.3
to
1.7
380
0.6
20
380
V/mV
13
25°C
1012
1012
Ω
25°C
8
8
pF
25°C
25
25
Ω
25°C
60
84
60
84
Full range
60
82
60
82
25°C
70
89
70
89
Full range
70
84
70
84
dB
dB
25°C
Full range
† Full range is −55°C to 125°C for M level part.
‡ Referenced to 1.35 V
6
60
125
0
to
1.4
20
mV
µV/°C
V/°C
2
25°C
25
C
25°C
2.1
2.4
−0.3
to
1.7
25°C
Large-signal
differential voltage
amplification
0.8
0
to
1.4
Full range
UNIT
1.9
2.7
500
25°C
IOL = 2.2 mA
1.6
−0.3
to
1.7
Full range
VIC = 1.35 V,
0.44
0
to
1.4
25°C
VOL
MAX
350
IOH = − 0.675 mA
VIC = 1.35 V,
TYP
3.0
Full range
IOH = − 2.2 mA
Low-level output
voltage
2.5
MIN
2.7
25°C
VOH
0.44
25°C
to
125°C
RS = 50 Ω
CMRR > 60 dB,
MAX
Full range
TLV2774/5
TLV277xAM
TYP
Full range
25°C
VDD = ± 1.35 V,
VIC = 0, VO = 0,
RS = 50 Ω
Input bias current
TLV277xM
MIN
25°C
TLV2770/1/2/3
Temperature
coefficient of input
offset voltage
IIB
TA†
TEST CONDITIONS
• DALLAS, TEXAS 75265
1
2
2
1
2
2
mA
SGLS317A − OCTOBER 2005 − REVISED SEPTEMBER 2007
operating characteristics at specified free-air temperature, VDD = 2.7 V (unless otherwise noted)
PARAMETER
VO(PP) = 0.8 V,
RL = 10 kΩ
SR
Slew rate at unity gain
Vn
Equivalent input
noise voltage
VN(PP)
Peak-to-peak
equivalent input
noise voltage
In
Equivalent input
noise current
f = 100 Hz
THD + N
Total harmonic
distortion plus noise
RL = 600 Ω,
f = 1 kHz
CL = 100 pF,
MIN
TYP
25°C
5
Full
range
4.7
f = 1 kHz
f = 10 kHz
φm
MAX
MIN
TYP
9
5
9
6
4.7
6
0.33
0.33
µV
0.86
0.86
µV
0.6
0.6
fA /√Hz
0.0085%
0.0085%
0.025%
0.025%
0.12%
0.12%
4.8
4.8
0.186
0.186
3.92
3.92
25°C
46°
46°
25°C
12
12
25°C
RL = 600 Ω,
Settling time
AV = −1,
Step = 0.85 V to
1.85 V,
RL = 600 Ω,
CL = 100 pF
RL = 600 Ω,
25°C
25
C
25°C
0.1%
Gain margin
† Full range is −55°C to 125°C for M level part.
POST OFFICE BOX 655303
nV/√Hz
MHz
µss
25°C
0.01%
CL = 100 pF
V/µs
17
f = 0.1 Hz to 10 Hz
f = 10 kHz,
CL = 100 pF
UNIT
17
25°C
AV = 1
AV = 10
MAX
21
f = 0.1 Hz to 1 Hz
Gain-bandwidth
product
Phase margin at
unity gain
TLV277xAM
21
25°C
AV = 100
ts
TLV277xM
TA†
TEST CONDITIONS
• DALLAS, TEXAS 75265
dB
7
SGLS317A − OCTOBER 2005 − REVISED SEPTEMBER 2007
electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted)
PARAMETER
TA†
TEST CONDITIONS
TLV277xM
MIN
25°C
VIO
αVIO
IIO
IIB
VICR
Input offset voltage
VDD = ± 2.5 V,
VIC = 0, VO = 0,
RS = 50 Ω
TLV2770/1/2/3
0.8
Full range
Temperature
coefficient of input
offset voltage
25°C
to
125°C
2
25°C
1
Input offset current
VDD = ± 2.5 V,
VIC = 0, VO = 0,
RS = 50 Ω
Input bias current
Common-mode
input voltage range
VDD = ± 2.5 V,
VIC = 0, VO = 0,
RS = 50 Ω
TLV2770/1/2/3
Full range
TLV2774/5
25°C
Full range
High-level output
voltage
IOH = − 1.3 mA
Low-level output
voltage
IOL = 4.2 mA
VIC = 2.5 V,
VO = 1 V to 4 V
RL = 10 kΩ,‡
AVD
Large-signal
differential voltage
amplification
ri(d)
Differential input
resistance
ci(c)
Common-mode
input capacitance
f = 10 kHz,
zo
Closed-loop
output impedance
f = 100 kHz,
CMRR
Common-mode
rejection ratio
kSVR
IDD
0.8
60
1
125
200
200
60
2
350
500
500
Full range
−0.3
to
3.8
4.9
pA
V
4.9
4.8
4.8
4.7
V
4.7
4.4
4.4
0.1
Full range
0.1
0.2
0.2
0.21
Full range
V
0.21
0.6
13
pA
60
350
0
to
3.7
Full range
60
125
−0.3
to
3.8
20
mV
µV/°C
V/°C
2
0
to
3.7
25°C
2.1
2.4
−0.3
to
3.8
25°C
UNIT
1.9
2.5
0
to
3.7
Full range
VIC = 2.5 V,
1.6
−0.3
to
3.8
25°C
IOL = 1.3 mA
0.36
0
to
3.7
Full range
VIC = 2.5 V,
MAX
25°C
25
C
RS = 50 Ω
CMRR > 60 dB,
2
TLV2770/1/2/3
TLV2774/5
TYP
2.7
25°C
450
0.6
20
450
V/mV
13
25°C
1012
1012
Ω
25°C
8
8
pF
AV = 10
25°C
20
20
Ω
VIC = VICR (min),
RS = 50 Ω
VO = 3.7 V,
25°C
60
96
60
96
Full range
60
93
60
93
Supply voltage
rejection ratio
(∆VDD /∆VIO)
VDD = 2.7 V to 5 V,
No load
VIC = VDD /2,
25°C
70
89
70
89
Full range
70
84
70
84
Supply current
(per channel)
VO = 1.5 V,
No load
POST OFFICE BOX 655303
dB
dB
25°C
Full range
† Full range is −55°C to 125°C for M level part.
‡ Referenced to 2.5 V
8
2.5
VDD = ± 2.5 V,
VIC = 0, VO = 0,
RS = 50 Ω
IOH = − 4.2 mA
VOL
0.36
MIN
2.7
25°C
VOH
MAX
Full range
25°C
TLV2774/5
TLV277xAM
TYP
• DALLAS, TEXAS 75265
1
2
2
1
2
2
mA
SGLS317A − OCTOBER 2005 − REVISED SEPTEMBER 2007
operating characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted)
PARAMETER
VO(PP) = 1.5 V,
RL = 10 kΩ
SR
Slew rate at unity gain
Vn
Equivalent input
noise voltage
VN(PP)
Peak-to-peak
equivalent input
noise voltage
In
Equivalent input
noise current
f = 100 Hz
THD + N
Total harmonic
distortion plus noise
RL = 600 Ω,
f = 1 kHz
CL = 100 pF,
MIN
TYP
25°C
5
Full
range
4.7
φm
MAX
10.5
5
10.5
6
4.7
6
12
0.33
0.33
µV
0.86
0.86
µV
0.6
0.6
fA /√Hz
0.005%
0.005%
0.016%
0.016%
0.095%
0.095%
5.1
5.1
0.134
0.134
1.97
1.97
25°C
46°
46°
25°C
12
12
25°C
RL = 600 Ω,
Settling time
AV = −1,
Step = 1.5 V to
3.5 V,
RL = 600 Ω,
CL = 100 pF
RL = 600 Ω,
25°C
25
C
25°C
0.1%
Gain margin
† Full range is −55°C to 125°C for M level part.
POST OFFICE BOX 655303
nV/√Hz
MHz
µss
25°C
0.01%
CL = 100 pF
V/µs
12
f = 0.1 Hz to 10 Hz
f = 10 kHz,
CL = 100 pF
UNIT
17
25°C
AV = 1
AV = 10
MAX
17
f = 0.1 Hz to 1 Hz
Gain-bandwidth
product
Phase margin at unity
gain
TYP
25°C
f = 10 kHz
TLV2772xAM
MIN
f = 1 kHz
AV = 100
ts
TLV277xM
TA†
TEST CONDITIONS
• DALLAS, TEXAS 75265
dB
9
SGLS317A − OCTOBER 2005 − REVISED SEPTEMBER 2007
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
VIO
Input offset voltage
Distribution
vs Common-mode input voltage
Distribution
IIB/IIO
VOH
Input bias and input offset currents
vs Free-air temperature
High-level output voltage
vs High-level output current
8,9
VOL
VO(PP)
Low-level output voltage
vs Low-level output current
10,11
Maximum peak-to-peak output voltage
vs Frequency
12,13
IOS
Short-circuit output current
vs Supply voltage
vs Free-air temperature
VO
AVD
Output voltage
vs Differential input voltage
Large-signal differential voltage amplification and phase margin
vs Frequency
17,18
AVD
Differential voltage amplification
vs Load resistance
vs Free-air temperature
19
20,21
zo
Output impedance
vs Frequency
22,23
CMRR
Common-mode rejection ratio
vs Frequency
vs Free-air temperature
kSVR
Supply-voltage rejection ratio
vs Frequency
IDD
Supply current (per channel)
vs Supply voltage
28
SR
Slew rate
vs Load capacitance
vs Free-air temperature
29
30
VO
VO
Voltage-follower small-signal pulse response
31,32
Voltage-follower large-signal pulse response
33,34
VO
VO
Inverting small-signal pulse response
35,36
Inverting large-signal pulse response
37,38
Vn
Equivalent input noise voltage
vs Frequency
Noise voltage (referred to input)
Over a 10 second period
Total harmonic distortion plus noise
vs Frequency
THD + N
7
14
15
16
24
25
26,27
39,40
41
42,43
Gain-bandwidth product
vs Supply voltage
44
B1
Unity-gain bandwidth
vs Load capacitance
45
φm
Phase margin
vs Load capacitance
46
Gain margin
vs Load capacitance
47
Amplifier with shutdown pulse turnon/off characteristics
48 − 50
Supply current with shutdown pulse turnon/off characteristics
10
1,2
3,4
5,6
51 − 53
Shutdown supply current
vs Free-air temperature
Shutdown forward/reverse isolation
vs Frequency
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
54
55, 56
SGLS317A − OCTOBER 2005 − REVISED SEPTEMBER 2007
TYPICAL CHARACTERISTICS
DISTRIBUTION OF TLV2772
INPUT OFFSET VOLTAGE
DISTRIBUTION OF TLV2772
INPUT OFFSET VOLTAGE
40
40
VDD = 2.7 V
RL = 10 kΩ
TA = 25°C
35
Percentage of Amplifiers − %
Percentage of Amplifiers − %
35
30
25
20
15
10
VDD = 5 V
RL = 10 kΩ
TA = 25°C
30
25
20
15
10
5
5
0
−2.5 −2 −1.5 −1 −0.5 0
0.5
1
1.5
2
0
2.5
−2.5 −2 −1.5 −1 −0.5 0
VIO − Input Offset Voltage − mV
Figure 2
2
2.5
4
4.5
2
VDD = 2.7 V
TA = 25°C
1.5
VIO − Input Offset Voltage − mV
VIO − Input Offset Voltage − mV
1.5
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
2
1
0.5
0
−0.5
−1
VDD = 5 V
TA = 25°C
1
0.5
0
−0.5
−1
−1.5
−1.5
−2
−1
1
Figure 3
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
1.5
0.5
VIO − Input Offset Voltage − mV
−0.5
0
0.5
1
1.5
2
2.5
3
VIC − Common-Mode Input Voltage − V
−2
−1 −0.5
0
0.5
1
1.5
2
2.5
3
3.5
VIC − Common-Mode Input Voltage − V
Figure 4
Figure 5
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
11
SGLS317A − OCTOBER 2005 − REVISED SEPTEMBER 2007
TYPICAL CHARACTERISTICS
DISTRIBUTION OF TLV2772
INPUT OFFSET VOLTAGE
DISTRIBUTION OF TLV2772
INPUT OFFSET VOLTAGE
35
35
VDD = 2.7 V
TA = 25°C to 125°C
25
20
15
10
5
0
VDD = 5 V
TA = 25°C to 125°C
30
Percentage of Amplifiers − %
Percentage of Amplifiers − %
30
25
20
15
10
5
−6
−3
0
3
6
9
0
12
−6
αVIO − Temperature Coefficient − µV/°C
−3
0
Figure 6
9
12
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
0.20
3
VDD = 5 V
VIC = 0
VO = 0
RS = 50 Ω
VDD = 2.7 V
VOH − High-Level Output Voltage − V
I IB and I IO − Input Bias and Input Offset Currents − nA
6
Figure 7
INPUT BIAS AND OFFSET CURRENT
vs
FREE-AIR TEMPERATURE
0.15
IIB
0.10
0.05
IIO
2.5
2
TA = −40°C
1.5
TA = 125°C
1
TA = 25°C
0.5
TA = 85°C
0
−75
−50
−25
0
25
50
75
100
125
0
0
TA − Free-Air Temperature − °C
5
10
Figure 9
POST OFFICE BOX 655303
15
20
IOH − High-Level Output Current − mA
Figure 8
12
3
αVIO − Temperature Coefficient − µV/°C
• DALLAS, TEXAS 75265
25
SGLS317A − OCTOBER 2005 − REVISED SEPTEMBER 2007
TYPICAL CHARACTERISTICS
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
5
3
VDD = 5 V
TA = 25°C
4
VDD = 2.7 V
VOL − Low-Level Output Voltage − V
VOH − High-Level Output Voltage − V
4.5
TA = −40°C
3.5
TA = 25°C
3
2.5
TA = 125°C
2
1.5
TA = 85°C
1
0.5
0
0
5
10
15
20 25
30
35 40 45
50
2.5
TA = 125°C
1.5
TA = 25°C
1
TA = −40°C
0.5
0
55
TA = 85°C
2
0
5
IOH − High-Level Output Current − mA
10
Figure 10
TA = 85°C
2
1.5
TA = 25°C
1
TA = −40°C
0.5
0
20
30
40
50
VO(PP) − Maximum Peak-to-Peak Output Voltage − V
VOL − Low-Level Output Voltage − V
TA = 125°C
2.5
10
25
30
MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE
vs
FREQUENCY
3
0
20
Figure 11
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
VDD = 5 V
15
IOL − Low-Level Output Current − mA
5
RL = 10 kΩ
VDD = 5 V
1% THD
4
3
2
VDD = 2.7 V
2% THD
1
0
100
IOL − Low-Level Output Current − mA
1000
10000
f − Frequency − kHz
Figure 12
Figure 13
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
13
SGLS317A − OCTOBER 2005 − REVISED SEPTEMBER 2007
TYPICAL CHARACTERISTICS
SHORT-CIRCUIT OUTPUT CURRENT
vs
SUPPLY VOLTAGE
5
60
THD = 5%
RL = 600 Ω
TA = 25°C
4.5
4
I OS − Short-Circuit Output Current − mA
VO(PP) − Maximum Peak-to-Peak Output Voltage − V
MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE
vs
FREQUENCY
3.5
VDD = 5 V
3
2.5
VDD = 2.7 V
2
1.5
1
0.5
0
100
1000
45
VO = VDD /2
VIC = VDD /2
TA = 25°C
30
15
0
−15
−30
VID = 100 mV
−45
−60
2
10000
3
f − Frequency − kHz
VID = −100 mV
20
VDD = 5 V
VO = 2.5 V
0
−20
VID = 100 mV
−25
RL = 600 Ω
TA = 25°C
VDD = 5 V
3
VDD = 2.7 V
2
1
0
25
50
75
100
125
0
−1000 −750 −500 −250
TA − Free-Air Temperature − °C
0
Figure 17
POST OFFICE BOX 655303
250
500
750
VID − Differential Input Voltage − µV
Figure 16
14
7
4
VO − Output Voltage − V
I OS − Short-Circuit Output Current − mA
5
−50
6
OUTPUT VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
60
−60
−75
5
Figure 15
SHORT-CIRCUIT OUTPUT CURRENT
vs
FREE-AIR TEMPERATURE
−40
4
VDD − Supply Voltage − V
Figure 14
40
VID = −100 mV
• DALLAS, TEXAS 75265
1000
SGLS317A − OCTOBER 2005 − REVISED SEPTEMBER 2007
TYPICAL CHARACTERISTICS
LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION
AND PHASE MARGIN
vs
FREQUENCY
VDD = 2.7 V
RL = 600 Ω
CL = 600 pF
TA = 25°C
80
AVD
300
240
60
180
40
120
Phase
20
60
0
0
−60
−20
−40
100
φ m − Phase Margin − degrees
A VD − Large-Signal Differential Amplification − dB
100
1k
10k
100k
1M
−90
10M
f − Frequency − Hz
Figure 18
LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION
AND PHASE MARGIN
vs
FREQUENCY
VDD = 5 V
RL = 600 Ω
CL = 600 pF
TA = 25°C
80
AVD
60
240
180
40
120
Phase
20
60
0
0
−20
−40
100
300
φ m − Phase Margin − degrees
A VD − Large-Signal Differential Amplification − dB
100
−60
1k
10k
100k
1M
−90
10M
f − Frequency − Hz
Figure 19
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
15
SGLS317A − OCTOBER 2005 − REVISED SEPTEMBER 2007
TYPICAL CHARACTERISTICS
DIFFERENTIAL VOLTAGE AMPLIFICATION
vs
LOAD RESISTANCE
DIFFERENTIAL VOLTAGE AMPLIFICATION
vs
FREE-AIR TEMPERATURE
1000
TA = 25°C
A VD − Differential Voltage Amplification − V/mV
A VD − Differential Voltage Amplification − V/mV
250
200
VDD = 2.7 V
VDD = 5 V
150
100
50
0
0.1
1
100
10
1000
RL = 10 kΩ
RL = 1 MΩ
100
RL = 600 Ω
10
1
VDD = 2.7 V
VIC = 1.35 V
VO = 0.6 V to 2.1 V
0.1
−75
−50
RL − Load Resistance − kΩ
−25
0
100
125
OUTPUT IMPEDANCE
vs
FREQUENCY
1000
100
RL = 10 kΩ
VDD = 2.7 V
TA = 25°C
RL = 1 MΩ
ZO − Output Impedance − Ω
A VD − Differential Voltage Amplification − V/mV
75
Figure 21
DIFFERENTIAL VOLTAGE AMPLIFICATION
vs
FREE-AIR TEMPERATURE
RL = 600 Ω
10
1
10
AV = 100
1
AV = 10
0.10
AV = 1
VDD = 5 V
VIC = 2.5 V
VO = 1 V to 4 V
0.1
−75
−50
−25
0
25
50
75
100
125
0.01
100
TA − Free-Air Temperature − °C
1k
10k
f − Frequency − Hz
Figure 22
16
50
TA − Free-Air Temperature − °C
Figure 20
100
25
Figure 23
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
100k
1M
SGLS317A − OCTOBER 2005 − REVISED SEPTEMBER 2007
TYPICAL CHARACTERISTICS
OUTPUT IMPEDANCE
vs
FREQUENCY
COMMON-MODE REJECTION RATIO
vs
FREQUENCY
100
90
CMRR − Common-Mode Rejection Ratio − dB
Zo − Output Impedance − Ω
VDD = ±2.5 V
TA = 25°C
10
Av = 100
1
Av = 10
0.1
Av = 1
0.01
100
1k
10k
100k
VDD = 5 V
80
70
60
50
40
10
1M
100
f − Frequency − Hz
100k
1M
10M
SUPPLY-VOLTAGE REJECTION RATIO
vs
FREQUENCY
120
120
k SVR − Supply-Voltage Rejection Ratio − dB
CMRR − Common-Mode Rejection Ratio − dB
10k
Figure 25
COMMON-MODE REJECTION RATIO
vs
FREE-AIR TEMPERATURE
115
110
105
VDD = 2.7 V
95
90
VDD = 5 V
85
80
−40 −20
1k
f − Frequency − Hz
Figure 24
100
VIC = 1.35 V
and 2.5 V
TA = 25°C
VDD = 2.7 V
0
20
40
60
80
100 120 140
VDD = 2.7 V
TA = 25°C
kSVR+
100
kSVR−
80
60
40
20
0
10
100
TA − Free-Air Temperature − °C
1k
10k
100k
1M
10M
f − Frequency − Hz
Figure 26
Figure 27
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
17
SGLS317A − OCTOBER 2005 − REVISED SEPTEMBER 2007
TYPICAL CHARACTERISTICS
SUPPLY VOLTAGE REJECTION RATIO
vs
FREQUENCY
SUPPLY CURRENT (PER CHANNEL)
vs
SUPPLY VOLTAGE
100
1.6
VDD = 5 V
TA = 25°C
kSVR+
I DD − Supply Current (Per Channel) − mA
k SVR − Supply Voltage Rejection Ratio − dB
120
kSVR−
80
60
40
20
0
10
100
1k
10 k
100 k
1M
TA = 125°C
1.4
1.2
TA = 25°C
1
TA = 0°C
TA = − 40°C
0.8
0.6
0.4
0.2
0
2.5
10 M
TA = 85°C
3
f − Frequency − Hz
3.5
4
Figure 28
5
5.5
6
6.5
7
Figure 29
SLEW RATE
vs
LOAD CAPACITANCE
SLEW RATE
vs
FREE-AIR TEMPERATURE
16
14
VDD = 5 V
AV = −1
TA = 25°C
SR+
14
13
SR−
12
SR − Slew Rate − µs
SR − Slew Rate − V/ µs
4.5
VDD − Supply Voltage − V
10
8
6
VDD = 2.7 V
RL = 10 kΩ
CL = 100 pF
AV = 1
12
11
10
4
9
2
0
10
100
1k
10k
100k
8
−75
−50
CL − Load Capacitance − pF
Figure 30
18
−25
0
25
Figure 31
POST OFFICE BOX 655303
50
75
TA − Free-Air Temperature − °C
• DALLAS, TEXAS 75265
100
125
SGLS317A − OCTOBER 2005 − REVISED SEPTEMBER 2007
TYPICAL CHARACTERISTICS
VOLTAGE-FOLLOWER
SMALL-SIGNAL PULSE RESPONSE
VOLTAGE-FOLLOWER
SMALL-SIGNAL PULSE RESPONSE
100
60
VDD = 5 V
RL = 600 Ω
CL = 100 pF
AV = 1
TA = 25°C
80
VO − Output Voltage − mV
80
VO − Output Voltage − mV
100
VDD = 2.7 V
RL = 600 Ω
CL = 100 pF
AV = 1
TA = 25°C
40
20
0
−20
−40
60
40
20
0
−20
−40
−60
0
0.5
1
1.5
2
2.5
3 3.5
4
4.5
−60
5
0
0.5
1
1.5
t − Time − µs
VOLTAGE-FOLLOWER
LARGE-SIGNAL PULSE RESPONSE
3.5
4
4.5
5
6
VDD = 2.7 V
RL = 600 Ω
CL = 100 pF
AV = 1
TA = 25°C
VDD = 5 V
RL = 600 Ω
CL = 100 pF
AV = 1
TA = 25°C
5
VO − Output Voltage − V
VO − Output Voltage − V
3
VOLTAGE-FOLLOWER
LARGE-SIGNAL PULSE RESPONSE
3
2
2.5
Figure 33
Figure 32
2.5
2
t − Time − µs
1.5
1
0.5
0
−0.5
4
3
2
1
0
−1
−1
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
−2
0
0.5
t − Time − µs
1
1.5
2
2.5
3
3.5
4
4.5
5
t − Time − µs
Figure 35
Figure 34
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
19
SGLS317A − OCTOBER 2005 − REVISED SEPTEMBER 2007
TYPICAL CHARACTERISTICS
INVERTING SMALL-SIGNAL
PULSE RESPONSE
INVERTING SMALL-SIGNAL
PULSE RESPONSE
100
60
VDD = 5 V
RL = 600 Ω
CL = 100 pF
AV = −1
TA = 25°C
80
VO − Output Voltage − mV
80
VO − Output Voltage − mV
100
VDD = 2.7 V
RL = 600 Ω
CL = 100 pF
AV = −1
TA = 25°C
40
20
0
−20
−40
60
40
20
0
−20
−40
−60
0
0.5
1
1.5
2
2.5
3 3.5
4
4.5
−60
5
0
0.5
1
1.5
t − Time − µs
3
4
2.5
3.5
2
3
1.5
1
0.5
VDD = 2.7 V
RL = 600 Ω
CL = 100 pF
AV = −1
TA = 25°C
0.5
1
1.5
2
2.5
5
2
1.5
VDD = 5 V
RL = 600 Ω
CL = 100 pF
AV = −1
TA = 25°C
1
3
3.5
4
4.5
5
1
0
0.5
t − Time − µs
1
1.5
2 2.5
3
t − Time − µs
Figure 39
Figure 38
20
4.5
2.5
0.5
−1
0
4
INVERTING LARGE-SIGNAL
PULSE RESPONSE
VO − Output Voltage − V
VO − Output Voltage − V
INVERTING LARGE-SIGNAL
PULSE RESPONSE
−0.5
3.5
Figure 37
Figure 36
0
2
2.5
3
t − Time − µs
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3.5
4
4.5
5
SGLS317A − OCTOBER 2005 − REVISED SEPTEMBER 2007
TYPICAL CHARACTERISTICS
EQUIVALENT INPUT NOISE VOLTAGE
vs
FREQUENCY
EQUIVALENT INPUT NOISE VOLTAGE
vs
FREQUENCY
160
140
120
100
80
60
40
VDD = 5 V
RS = 20 Ω
TA = 25°C
120
100
80
60
40
20
20
0
10
1k
100
0
10k
10
100
f − Frequency − Hz
1k
10k
f − Frequency − Hz
Figure 40
Figure 41
NOISE VOLTAGE
OVER A 10 SECOND PERIOD
VDD = 5 V
f = 0.1 Hz to 10 Hz
TA = 25°C
300
200
Noise Voltage − nV
Vn − Input Noise Voltage − nV/ Hz
140
Vn − Input Noise Voltage − nV Hz
VDD = 2.7 V
RS = 20 Ω
TA = 25°C
100
GND
−100
−200
−300
0
1
2
3
4
5
6
7
8
9
10
t − Time − s
Figure 42
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
21
SGLS317A − OCTOBER 2005 − REVISED SEPTEMBER 2007
TYPICAL CHARACTERISTICS
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
FREQUENCY
10
VDD = 2.7 V
RL = 600 Ω
TA = 25°C
1
Av = 100
0.1
Av = 10
0.01
Av = 1
0.001
10
10
THD+N − Total Harmonic Distortion Plus Noise − %
THD+N − Total Harmonic Distortion Plus Noise − %
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
FREQUENCY
100
1k
10k
VDD = 5 V
RL = 600 Ω
TA = 25°C
1
0.1
Av = 100
Av = 10
0.01
Av = 1
0.001
10
100k
100
f − Frequency − Hz
Figure 43
Unity-Gain Bandwidth − MHz
Gain-Bandwidth Product − MHz
5
4.8
4.6
4.4
4.2
VDD = 5 V
RL = 600 Ω
TA = 25°C
4
3
Rnull = 100
2
Rnull = 50
Rnull = 20
1
Rnull = 0
4
2
2.5
3
3.5
4
4.5
5
5.5
6
0
10
VDD − Supply Voltage − V
100
1k
Figure 46
POST OFFICE BOX 655303
10k
CL − Load Capacitance − pF
Figure 45
22
100k
UNITY-GAIN BANDWIDTH
vs
LOAD CAPACITANCE
RL = 600 Ω
CL = 100 pF
f = 10 kHz
TA = 25°C
5
10k
Figure 44
GAIN-BANDWIDTH PRODUCT
vs
SUPPLY VOLTAGE
5.2
1k
f − Frequency − Hz
• DALLAS, TEXAS 75265
100k
SGLS317A − OCTOBER 2005 − REVISED SEPTEMBER 2007
TYPICAL CHARACTERISTICS
PHASE MARGIN
vs
LOAD CAPACITANCE
GAIN MARGIN
vs
LOAD CAPACITANCE
90
70
10
Rnull = 50 Ω
60
50
Rnull = 20 Ω
40
30
20
Rnull = 0
Rnull = 50 Ω
10k
40
10
100K
100
10k
1k
CL − Load Capacitance − pF
CL − Load Capacitance − pF
Figure 47
Figure 48
TLV2770
TLV2773
AMPLIFIER WITH SHUTDOWN PULSE
TURNON/OFF CHARACTERISTICS
AMPLIFIER WITH SHUTDOWN PULSE
TURNON/OFF CHARACTERISTICS
7
6
6
4
5
0
SHDN = GND
4
VDD = 5 V
AV = 5
TA = 25°C
3
2
−6
1
−8
8
7
SHDN = VDD
6
2
VDD = 5 V
SHDN = GND
AV = 5
TA = 25°C
Channel 1 Switched
Channel 2 SHDN MODE
0
−2
4
3
2
Channel 1
−4
5
1
−6
VO
VO
0
−10
−2
Shutdown Signal − V
2
8
VO − Output Voltage − V
SHDN = VDD
8
100K
VO − Output Voltage − V
1k
100
4
Shutdown Signal − V
Rnull = 100 Ω
25
Rnull = 20 Ω
6
−12
−4
20
35
0
10
−4
Rnull = 0
15
30
10
−2
VDD = 5 V
RL = 600 Ω
TA = 25°C
5
Rnull = 100 Ω
Gain Margin − dB
φ m − Phase Margin − degrees
80
0
VDD = 5 V
RL = 600 Ω
TA = 25°C
0
2
4
6
8
10
12
−1
14
0
−8
−10
−2.5
0
t − Time − µs
2.5
5
7.5
10
12.5
−1
15
t − Time − µs
Figure 49
Figure 50
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23
SGLS317A − OCTOBER 2005 − REVISED SEPTEMBER 2007
TYPICAL CHARACTERISTICS
TLV2775 − CHANNEL 1
TLV2770
AMPLIFIER WITH SHUTDOWN PULSE
TURNON/OFF CHARACTERISTICS
SUPPLY CURRENT WITH SHUTDOWN PULSE
TURNON/OFF CHARACTERISTICS
2
VDD = 5 V
SHDN = GND
AV = 5
TA = 25°C
Channel 1/2 Switched
Channel 3/4 SHDN MODE
0
−2
−10
−2.5
2
5
0
4
3
1
−6
−8
6
2
Channel 1
−4
4
VO
2.5
5
7.5
12.5
10
18
15
SHDN = GND
12
−2
VDD = 5 V
AV = 5
TA = 25°C
−4
−6
−10
−1
15
−12
−4
−2
0
2
6
8
10
12
Figure 52
TLV2773
TLV2775
SUPPLY CURRENT WITH SHUTDOWN PULSE
TURNON/OFF CHARACTERISTICS
6
60
3
50
0
SHDN = GND
40
−3
VDD = 5 V
AV = 5
TA = 25°C
Channel 1 Switched
Channel 2 SHDN MODE
30
20
10
−12
IDD
0
−15
−18
−5
−2.5
0
2.5
5
7.5
10
12.5
−3
15
70
SHDN = VDD
60
50
SHDN = GND
Shutdown Signal − V
0
70
I DD − Supply Current − mA
SHDN = VDD
−9
−3
14
t − Time − µs
6
Shutdown Signal − V
4
SUPPLY CURRENT WITH SHUTDOWN PULSE
TURNON/OFF CHARACTERISTICS
−6
6
0
Figure 51
3
9
3
IDD
t − Time − µs
40
−3
VDD = 5 V
AV = 5
TA = 25°C
Channel 1/2 Switched
Channel 3/4 SHDN MODE
−6
−9
20
IDD
−15
−18
−5
0
−2.5
0
2.5
5
7.5
t − Time − µs
Figure 53
Figure 54
POST OFFICE BOX 655303
30
10
−12
t − Time − µs
24
21
−8
0
0
SHDN = VDD
• DALLAS, TEXAS 75265
10
12.5
−3
15
I DD − Supply Current − mA
Shutdown Signal − V
4
7
24
I DD − Supply Current − mA
SHDN = VDD
6
Shutdown Signal − V
6
8
VO − Output Voltage − V
8
SGLS317A − OCTOBER 2005 − REVISED SEPTEMBER 2007
TYPICAL CHARACTERISTICS
SHUTDOWN SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
TLV2770
5
4
VDD 5 V
3
2
VDD 2.7 V
1
100
−50
−25
0
25
50
75
100
125
60
40
20
−20
10
TA − Free-Air Temperature − °C
VI(PP) = 0.1 V
80
0
0
−75
VI(PP) = 2.7 V
120
Shutdown Forward Isolation − dB
6
140
AV = 5
RL = OPEN
SHDN = GND
SHDN MODE
AV = 1
VDD = 2.7 V
RL = 10 kΩ
CL = 20 pF
TA = 25°C
102
Figure 55
103
104
f − Frequency − Hz
105
106
Figure 56
TLV2770
140
SHUTDOWN REVERSE ISOLATION
vs
FREQUENCY
VI(PP) = 2.7 V
120
Shutdown Reverse Isolation − dB
I DD − Shutdown Supply Current − µ A
7
SHUTDOWN FORWARD ISOLATION
vs
FREQUENCY
100
80
60
40
20
0
−20
10
VI(PP) = 0.1 V
SHDN MODE
AV = 1
VDD = 2.7 V
RL = 10 kΩ
CL = 20 pF
TA = 25°C
102
103
104
f − Frequency − Hz
105
106
Figure 57
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SGLS317A − OCTOBER 2005 − REVISED SEPTEMBER 2007
PARAMETER MEASUREMENT INFORMATION
_
Rnull
+
RL
CL
Figure 58
driving a capacitive load
When the amplifier is configured in this manner, capacitive loading directly on the output will decrease the
device’s phase margin leading to high frequency ringing or oscillations. Therefore, for capacitive loads of greater
than 10 pF, it is recommended that a resistor be placed in series (RNULL) with the output of the amplifier (See
Figure 59). A minimum value of 20 Ω should work well for most applications.
RF
RG
Input
_
RNULL
Output
+
CLOAD
Figure 59. Driving a Capacitive Load
26
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APPLICATION INFORMATION
offset voltage
The output offset voltage, (VOO) is the sum of the input offset voltage (VIO) and both input bias currents (IIB) times
the corresponding gains. The following schematic and formula can be used to calculate the output offset
voltage:
RF
IIB−
RG
V
+
−
VI
IO
ǒ ǒ ǓǓ
1)
R
R
F
"I
G
IB)
R
S
ǒ ǒ ǓǓ
1)
R
R
F
G
"I
IB–
R
F
VO
+
RS
+V
OO
IIB+
Figure 60. Output Offset Voltage Model
general configurations
When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often
required. The simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifier
(see Figure 61).
RG
RF
f
–3dB
−
VO
+
VI
R1
C1
V
O +
V
I
1
2pR1C1
+
ǒ
1)
R
R
F
G
Ǔǒ
Ǔ
1
1 ) sR1C1
Figure 61. Single-Pole Low-Pass Filter
If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter can be used for this
task. For best results, the amplifier should have a bandwidth that is eight to ten times the filter frequency
bandwidth. Failure to do this can result in phase shift of the amplifier.
C1
+
_
VI
R1
R1 = R2 = R
C1 = C2 = C
Q = Peaking Factor
(Butterworth Q = 0.707)
R2
f
C2
RG
RF
–3dB
RG =
+
(
1
2pRC
RF
1
2−
Q
)
Figure 62. Two Pole Low Pass Sallen Key Filter
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SGLS317A − OCTOBER 2005 − REVISED SEPTEMBER 2007
APPLICATION INFORMATION
using the TLV2772 as an accelerometer interface
The schematic (see Figure 63) shows the ACH04-08-05 interfaced to the TLV1544 10-bit analog-to-digital
converter (ADC).
The ACH04-08-05 is a shock sensor designed to convert mechanical acceleration into electrical signals. The
sensor contains three piezoelectric sensing elements oriented to simultaneously measure acceleration in three
orthogonal, linear axes (x, y, z). The operating frequency is 0.5 Hz to 5 kHz. The output is buffered with an
internal JFET and has a typical output voltage of 1.80 mV/g for the x and y axis and 1.35 mV/g for the z axis.
Amplification and frequency shaping of the shock sensor output is done by the TLV2772 rail-to-rail operational
amplifier. The TLV2772 is ideal for this application as it offers high input impedance, good slew rate, and
excellent dc precision. The rail-to-rail output swing and high output drive are perfect for driving the analog input
of the TLV1544 ADC.
1.23 V
C2
2.2 nF
R3
10 kΩ
R4
100 kΩ
3V
R2
1 MΩ
1 Axis ACH04−08−05
3V
C1
0.22 µF
R1
100 kΩ
R5
1 kΩ
8
2
+
3 _
1
4
Output to
TLV1544 (ADC)
1/2
TLV2772
C3
0.22 µF
Signal Conditioning
3V
R6
2.2 kΩ
1.23 V
Shock Sensor
1.23 V
C
R
TLV431
A
Voltage Reference
Figure 63. Accelerometer Interface Schematic
The sensor signal must be amplified and frequency-shaped to provide a signal the ADC can properly convert
into the digital domain. Figure 63 shows the topology used in this application for one axis of the sensor. This
system is powered from a single 3-V supply. Configuring the TLV431 with a 2.2-kΩ resistor produces a reference
voltage of 1.23 V. This voltage is used to bias the operational amplifier and the internal JFETs in the shock
sensor.
28
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APPLICATION INFORMATION
gain calculation
Since the TLV2772 is capable of rail-to-rail output using a 3-V supply, VO = 0 (min) to 3 V (max). With no signal
from the sensor, nominal VO = reference voltage = 1.23 V. Therefore, the maximum negative swing from nominal
is 0 V − 1.23 V = −1.23 V and the maximum positive swing is 3 V − 1.23 V = 1.77 V. By modeling the shock sensor
as a low impedance voltage source with output of 2.25 mV/g (max) in the x and y axis and 1.70 mV/g (max) in
the z axis, the gain of the circuit is calculated by equation 1.
Gain +
Output Swing
Sensor Signal Acceleration
(1)
To avoid saturation of the operational amplifier, the gain calculations are based on the maximum negative swing
of −1.23 V and the maximum sensor output of 2.25 mV/g (x and y axis) and 1.70 mV/g (z axis).
Gain (x, y) +
* 1.23 V
+ 10.9
2.25 mVńg * 50 g
(2)
and
Gain (z) +
–1.23 V
+ 14.5
1.70 mVńg –50 g
(3)
By selecting R3 = 10 kΩ and R4 = 100 kΩ, in the x and y channels, a gain of 11 is realized. By selecting
R3 = 7.5 kΩ and R4 = 100 kΩ, in the z channel, a gain of 14.3 is realized. The schematic shows the configuration
for either the x or y axis.
bandwidth calculation
To calculate the component values for the frequency shaping characteristics of the signal conditioning circuit,
1 Hz and 500 Hz are selected as the minimum required 3-dB bandwidth.
To minimize the value of the input capacitor (C1) required to set the lower cutoff frequency requires a large value
resistor for R2. A 1-MΩ resistor is used in this example. To set the lower cutoff frequency, the required capacitor
value for C1 is:
C1 +
1
+ 0.159 µF
2p f LOW R 2
(4)
Using a value of 0.22 µF, a more common value of capacitor, the lower cutoff frequency is 0.724 Hz.
To minimize the phase shift in the feedback loop caused by the input capacitance of the TLV2772, it is best to
minimize the value of the feedback resistor R4. However, to reduce the required capacitance in the feedback
loop a large value for R4 is required. Therefore, a compromise for the value of R4 must be made. In this circuit,
a value of 100 kΩ has been selected. To set the upper cutoff frequency, the required capacitor value for C2 is:
C2 +
1
+ 3.18 µF
2p f HIGH R 4
(5)
Using a 2.2-nF capacitor, the upper cutoff frequency is 724 Hz.
R5 and C3 also cause the signal response to roll off. Therefore, it is beneficial to design this roll-off point to begin
at the upper cutoff frequency. Assuming a value of 1 kΩ for R5, the value for C3 is calculated to be
0.22 µF.
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SGLS317A − OCTOBER 2005 − REVISED SEPTEMBER 2007
APPLICATION INFORMATION
circuit layout considerations
To achieve the levels of high performance of the TLV277x, follow proper printed-circuit board design techniques.
A general set of guidelines is given in the following.
D Ground planes—It is highly recommended that a ground plane be used on the board to provide all
components with a low inductive ground connection. However, in the areas of the amplifier inputs and
output, the ground plane can be removed to minimize the stray capacitance.
D Proper power supply decoupling—Use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic
capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers
depending on the application, but a 0.1-µF ceramic capacitor should always be used on the supply terminal
of every amplifier. In addition, the 0.1-µF capacitor should be placed as close as possible to the supply
terminal. As this distance increases, the inductance in the connecting trace makes the capacitor less
effective. The designer should strive for distances of less than 0.1 inches between the device power
terminals and the ceramic capacitors.
D Sockets—Sockets can be used but are not recommended. The additional lead inductance in the socket pins
will often lead to stability problems. Surface-mount packages soldered directly to the printed-circuit board
is the best implementation.
D Short trace runs/compact part placements—Optimum high performance is achieved when stray series
inductance has been minimized. To realize this, the circuit layout should be made as compact as possible,
thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting input of
the amplifier. Its length should be kept as short as possible. This minimizes stray capacitance at the input
of the amplifier.
D Surface-mount passive components—Using surface-mount passive components is recommended for high
performance amplifier circuits for several reasons. First, because of the extremely low lead inductance of
surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small
size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray
inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be
kept as short as possible.
30
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APPLICATION INFORMATION
general power dissipation considerations
For a given θJA, the maximum power dissipation is shown in Figure 64 and is calculated by the following formula:
P
D
+
ǒ
T MAX * T A
q JA
Ǔ
Where:
PD = Maximum power dissipation of TLV277x IC (watts)
TMAX = Absolute maximum junction temperature (150°C)
TA
= Free-ambient air temperature (°C)
θJA = θJC + θCA
θJC = Thermal coefficient from junction to case
θCA = Thermal coefficient from case to ambient air (°C/W)
MAXIMUM POWER DISSIPATION
vs
FREE-AIR TEMPERATURE
2
Maximum Power Dissipation − W
1.75
PDIP Package
Low-K Test PCB
θJA = 104°C/W
1.5
1.25
TJ = 150°C
MSOP Package
Low-K Test PCB
θJA = 260°C/W
SOIC Package
Low-K Test PCB
θJA = 176°C/W
1
0.75
0.5
0.25
SOT-23 Package
Low-K Test PCB
θJA = 324°C/W
0
−55 −40 −25 −10 5
20 35 50 65 80 95 110 125
TA − Free-Air Temperature − °C
NOTE A: Results are with no air flow and using JEDEC Standard Low-K test PCB.
Figure 64. Maximum Power Dissipation vs Free-Air Temperature
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31
SGLS317A − OCTOBER 2005 − REVISED SEPTEMBER 2007
APPLICATION INFORMATION
shutdown function
Three members of the TLV277x family (TLV2770/3/5) have a shutdown terminal for conserving battery life in
portable applications. When the shutdown terminal is tied low, the supply current is reduced to 0.8 µA/channel,
the amplifier is disabled, and the outputs are placed in a high impedance mode. To enable the amplifier, the
shutdown terminal can either be left floating or pulled high. When the shutdown terminal is left floating, care must
be taken to ensure that parasitic leakage current at the shutdown terminal does not inadvertently place the
operational amplifier into shutdown. The shutdown terminal threshold is always referenced to VDD/2. Therefore,
when operating the device with split supply voltages (e.g. ± 2.5 V), the shutdown terminal must be pulled to VDD−
(not GND) to disable the operational amplifier.
The amplifier output with a shutdown pulse is shown in Figures 48, 49, and 50. The amplifier is powered with
a single 5-V supply and configured as a noninverting configuration with a gain of 5. The amplifier turnon and
turnoff times are measured from the 50% point of the shutdown pulse to the 50% point of the output waveform.
The times for the single, dual, and quad are listed in the data tables. The bump on the rising edge of the TLV2770
output waveform is due to the start-up circuit on the bias generator. For the dual and quad (TLV2773/5), this
bump is attributed to the bias generator’s start-up circuit as well as the crosstalk between the other channel(s),
which are in shutdown.
Figures 55 and 56 show the amplifier’s forward and reverse isolation in shutdown. The operational amplifier is
powered by ±1.35-V supplies and configured as a voltage follower (AV = 1). The isolation performance is plotted
across frequency for both 0.1 VPP and 2.7 VPP input signals. During normal operation, the amplifier would not
be able to handle a 2.7-VPP input signal with a supply voltage of ±1.35 V since it exceeds the common-mode
input voltage range (VICR). However, this curve illustrates that the amplifier remains in shutdown even under
a worst case scenario.
32
POST OFFICE BOX 655303
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SGLS317A − OCTOBER 2005 − REVISED SEPTEMBER 2007
APPLICATION INFORMATION
macromodel information
Macromodel information provided was derived using Microsim Parts Release 8, the model generation
software used with Microsim PSpice . The Boyle macromodel (see Note 5) and subcircuit in Figure 65 are
generated using the TLV2772 typical electrical and operating characteristics at TA = 25°C. Using this
information, output simulations of the following key parameters can be generated to a tolerance of 20% (in most
cases):
D Maximum positive output voltage swing
D Unity-gain frequency
D Maximum negative output voltage swing
D Common-mode rejection ratio
D Slew rate
D Phase margin
D Quiescent power dissipation
D DC output resistance
D Input bias current
D AC output resistance
D Open-loop voltage amplification
D Short-circuit output current limit
NOTE 5: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Integrated Circuit Operational Amplifiers”, IEEE Journal
of Solid-State Circuits, SC-9, 353 (1974).
99
3
VDD +
css
egnd
9
rss
2
+
10
IN −
j1
dp
vc
j2
IN+
11
r2
−
53
C2
6
GND
−
−
+
vln
gcm
vlim
ga
8
−
ro1
rd2
54
4
−
−
7
C1
rd1
91
+
vlp
+
dc
12
hlim
−
+ dlp
90
ro2
vb
rp
1
92
fb
−
+
iss
dln
+
de
5
+
ve
* TLV2772 operational amplifier macromodel subcircuit
* created using Parts release 8.0 on 12/12/97 at 10:08
* Parts is a MicroSim product.
*
* connections: noninverting input
*
| inverting input
*
| | positive power supply
*
| | | negative power supply
*
| | | | output
*
| | | | |
.subckt TLV2772
12345
*
c1
11
12
2.8868E-12
c2
6
7
10.000E−12
css
10
99
2.6302E−12
dc
5
53
dy
de
54
5
dy
dlp
90
91
dx
dln
92
90
dx
dp
4
3
dx
egnd
99
0
poly(2) (3,0) (4,0) 0 .5 .5
fb
7
99
poly(5) vb vc ve vlp vln 0
15.513E6 −1E3 1E3 16E6 −16E6
ga
6
0
11 12 188.50E−6
gcm
0
6
10 99 9.4472E−9
iss
hlim
j1
j2
r2
rd1
rd2
ro1
ro2
rp
rss
vb
vc
ve
vlim
vlp
vln
.model
.model
.model
3
90
11
12
6
4
4
8
7
3
10
9
3
54
7
91
0
dx
dy
jx1
.model
jx2
OUT
10
dc
145.50E−6
0
vlim 1K
2
10 jx1
1
10 jx2
9
100.00E3
11
5.3052E3
12
5.3052E3
5
17.140
99
17.140
4
4.5455E3
99
1.3746E6
0
dc 0
53
dc .82001
4
dc .82001
8
dc 0
0
dc 47
92
dc 47
D(Is=800.00E−18)
D(Is=800.00E−18 Rs=1m Cjo=10p)
PJF(Is=2.2500E−12 Beta=244.20E−6
+ Vto=−.99765)
PJF(Is=1.7500E−12 Beta=244.20E−6
+ Vto=−1.002350)
.ends
*$
Figure 65. Boyle Macromodel and Subcircuit
PSpice and Parts are trademarks of MicroSim Corporation.
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33
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TLV2772AMDREP
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
2772AE
TLV2774AMDREP
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
2774AEP
TLV2774MDREP
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
2774EP
V62/06607-02XE
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
2772AE
V62/06607-03YE
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
2774EP
V62/06607-04YE
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
2774AEP
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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