TLV320AIC1110PBSR

TLV320AIC1110 SLAS359 – DECEMBER 2001 PCM CODEC
Capable of Driving 32 Ω Down to a 8-Ω FEATURES
2.7-V to 3.3-V Operation
Designed for Analog and Digital Wireless









Speaker Handsets and Telecommunications Applications Two Differential Microphone Inputs Differential Earphone Outputs and One Single-Ended Earphone Output Earphone and Microphone Mute Programmable Transmit, Receive, and Sidetone Paths With Extended Gain and Attenuation Ranges Programmable for 15-Bit Linear Data or 8-Bit Companded (µ-law and A-law) Mode Supports PCM Clock Rates of 128 kHz and 2.048 MHz Pulse Density Modulated (PDM) Buzzer Output On-Chip I2C Bus, Which Provides Simple, Standard, Two-Wire Serial Interface With Digital ICs Dual-Tone Multifrequency (DTMF) and Single-Tone Generator Capable of up to 8-kHz Tone With Three Selectable Resolutions of 7.8125 Hz, 15.625 Hz, and 31.25 Hz 2-Channel Auxiliary Multiplexer (MUX) (Analog Switch)
Programmable Power Down Modes
Pin Compatible to the TLV320AIC1103 and
TLV320AIC1109 Devices for TQFP Only Available in a 32-Pin Thin Quad Flatpack (TQFP) Package and MicroStar Junior BGA APPLICATIONS
Digital Handset
Digital Headset
Cordless Phones
Digital PABX
Digital Voice Recording DESCRIPTION The TLV320AIC1110 provides extended gain and attenuation flexibility for transmit, receive, and sidetone paths. A differential earphone output is capable of driving speaker loads as low as 8 Ω for use in speaker phone applications. The single tone function on the TLV320AIC1110 generates a single tone output of up to 8 kHz. The resolution of the DTMF tone is also selectable to 7.8125 Hz, 15.625 Hz, or 31.25 Hz through the interface control. The analog switch provides more control capabilities for voice-band audio processor (PCM codec). This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C, Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than maximum-rated voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together or the device should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriated logic voltage level, preferably either VCC or ground. Specific guidelines for handling devices of this type are contained in the publication Guidelines for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies available from Texas Instruments. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. †These options are available on some devices. Please see the table of comparison for the last two generations of PCM codecs. MicroStar Junior is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. Copyright  2001, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com 1 TLV320AIC1110 SLAS359 – DECEMBER 2001 DESCRIPTION (Continued) The PCM codec is an analog-digital interface for voice band signals designed with a combination of coders and decoders (codecs) and filters. It is a low-power device with companding options and programming features, and it meets the requirements for communication systems, including the cellular phone. The device operates in either the 15-bit linear or 8-bit companded (µ-law or A-Law) mode, which is selectable through the I2C interface. A coder, an analog-to-digital converter or ADC, digitizes the analog voice signal, and a decoder, a digital-to-analog converter or DAC, converts the digital-voice signal to an analog output. The PCM codec provides a companding option to overcome the bandwidth limitations of telephone networks without degrading the sound quality. The human auditory system is a logarithmic system in which high amplitude signals require less resolution than low amplitude signals. Therefore, an 8-bit code word with nonuniform quantization (µ-law or A-law) has the same quality as 13-bit linear coding. The PCM codec provides better digital code words by generating a 15-bit linear coding option. The human voice is effective from a frequency range of 300 Hz to 3300 Hz in telephony applications. In order to eliminate unwanted signals, the PCM codec design has two types of filters that operate in both the transmit and receive path. A low-pass filter attenuates the signals over 4 kHz. A selectable high-pass filter cleans up the signals under 100 Hz. This reduces noise that may have coupled in from 50/60-Hz power cables. The high-pass filter is bypassed by selecting the corresponding register bit. The PCM codec has many programming features that are controlled using a 2-wire standard serial I2C interface. This allows the device to interface with many digital ICs such as a DSP or a microprocessor. The device has seven registers: power control, mode control, transmit PGA, receive PGA, high DTMF, low DTMF, and auxiliary mode control. Some of the programmable features that can be controlled by I2C interface include:












Transmit amplifier gain Receive amplifier gain Sidetone gain Volume control Earphone control PLL power control Microphone selection Transmit channel high-pass filter control Receive channel high-pass filter control Companding options and selection control PCM loopback DTMF control Pulse density modulated control The PCM codec is also capable of generating its own internal clocks from a 2.048-MHz master clock input. 2 www.ti.com TLV320AIC1110 SLAS359 – DECEMBER 2001 PLLVSS VSS MCLK RESET PWRUPSEL BUZZCON PCMSYN PCMCLK PBS PACKAGE (TOP VIEW) 24 23 22 21 20 19 18 17 25 16 26 15 14 13 PCMO PCMI DVSS DVDD 12 SCL 11 SDA 10 MUXOUT2 9 MUXOUT1 27 28 29 30 31 32 1 2 3 4 5 6 7 8 MBIAS MIC1P MIC1N MIC2P MIC2N REXT MUXIN AVSS PLLVDD EARVSS EAR1ON EARVDD EAR1OP EARVSS EAR2O AVDD www.ti.com 3 TLV320AIC1110 SLAS359 – DECEMBER 2001 EAR1OP EARVDD EAR1ON EARVSS PLLVDD PLLVSS 2 3 4 5 6 7 8 9 B NC NC NC NC NC NC NC VSS C NC NC NC NC NC NC MCLK D NC NC NC NC NC NC NC RESET E NC NC NC NC NC NC NC PWRUPSEL F NC NC NC NC NC NC NC G NC NC NC NC NC NC NC H NC NC NC NC NC NC NC EAR2O EARVSS MicroStar Junior (GQE) PACKAGE (TOP VIEW) 1 REXT MUXIN J 4 BUZZCON PCMSYN PCMCLK PCMO MUXOUT1 AVSS www.ti.com PCMI MIC2N DVSS MIC2P DVDD MIC1N SCL MIC1P SDA MBIAS A MUXOUT2 AVDD PCMOUT PCMSYN PCMCLK RX Vol Control g = –18 dB to 0 dB MIC1P PCM Interface MIC1N MIC Amplifier 2 g=6 or 18 dB MIC Amplifier 1 g= 23.5 dB Analog Modulator Voice 0 dB or 6 dB RX Filter and PGA g = – 6 dB to +6 dB TX Filter and PGA g = –10 dB to 0 dB www.ti.com Sidetone g = –24 db to –12 dB MIC2P Ear Amp1 EAR1OP EAR1ON Digital Modulator and Filter DTMF GAIN MUX DTMF –12 to 12 dB in 6dB Steps MIC2N functional block diagram PCMIN Ear Amp2 EAR2O Control Bus DTMF OUT IN Buzzer Control MUX OUT BUZZCON Generator 2 I C I/F REF PLL Power and RESET TLV320AIC1110 SLAS359 – DECEMBER 2001 PWRUPSEL V SS AVDD AV SS DVDD DV SS PLLVDD PLLV SS EARVDD EARV SS RESET MCLK REXT MBIAS SDATA SCLK 5 TLV320AIC1110 SLAS359 – DECEMBER 2001 detailed description power on/reset The power for the various digital and analog circuits is separated to improve the noise performance of the device. An external reset must be applied to the active low RESET terminal to assure reset upon power on and to bring the device to an operational state. After the initial power-on sequence, the device can be functionally powered up and powered down by writing to the power control register through the I2C interface. The device has a pin-selectable power up in the default mode option. The hardwired pin-selectable PWRUPSEL function allows the PCM codec to power up in the default mode and to be used without a microcontroller. reference A precision band gap reference voltage is generated internally and supplies all required voltage references to operate the transmit and receive channels. The reference system also supplies bias voltage for use with an electret microphone at terminal MBIAS. An external precision resistor is required for reference current setting at terminal REXT. I2C control interface The I2C interface is a two-wire bidirectional serial interface. The I2C interface controls the PCM codec by writing data to seven control registers:






Power control Mode control Transmit PGA and sidetone control Receive PGA gain and volume control DTMF routing Tone selection control Auxiliary control There are two power-up modes which may be selected at the PWRUPSEL terminal: (1) The PWRUPSEL state (VDD at terminal 20) causes the device to power up in the default mode when power is applied. Without an I2C interface or controlling device, the programmable functions are fixed at the default gain levels, and functions such as the sidetone and DTMF are not accessible. (2) The PWRUPSEL state (ground at terminal 20) causes the device to go to a power-down state when power is applied. In this mode, an I2C interface is required to power up the device. phase-locked loop (PLL) The phase-lock loop generates the internal clock frequency required for digital filters and modulators by phase locking to 2.048-MHz master clock input. PCM interface The PCM interface transmits and receives data at the PCMO and PCMI terminals respectively. The data is transmitted or received at the PCMCLK speed once every PCMSYN cycle. The PCMCLK can be tied directly to the 128-kHz or 2.048-MHz master clock (MCLK). The PCMSYN can be driven by an external source or derived from the master clock and used as an interrupt to the host controller. microphone amplifiers The microphone input is a switchable interface for two differential microphone inputs. The first stage is a low-noise differential amplifier that provides a gain of 23.5 dB. The second-stage amplifier has a selectable gain of 6 dB or 18 dB. 6 www.ti.com TLV320AIC1110 SLAS359 – DECEMBER 2001 detailed description (continued) analog modulator The transmit channel modulator is a third-order sigma-delta design. transmit filter and PGA The transmit filter is a digital filter designed to meet CCITT G.714 requirements. The device operates either in the 15-bit linear or 8-bit companded µ-law or in the A-law mode, which is selectable through the I2C interface. The transmit PGA defaults to 0 dB. sidetone A portion of the transmitted audio is attenuated and fed back to the receive channel through the sidetone path. The sidetone path defaults to the mute condition. The default gain of -12 dB is set in the sidetone control register. The sidetone path can be enabled by writing to the power control register. receive volume control The receive volume control block acts as an attenuator with a range of –18 dB to 0 dB in 2-dB steps for control of the receive channel volume. The receive volume control gain defaults to 0 dB. receive filter and PGA The receive filter is a digital filter that meets CCITT G.714 requirements with a high-pass filter that is selectable through the I2C interface. The device operates either in the 15-bit linear or the 8-bit µ-law or the A-law companded mode, which is selectable through the I2C interface. The gain defaults to –4 dB, representing a 3-dBm level for a 32-Ω load impedance and the corresponding digital full scale PCMI code. digital modulator and filter The second-order digital modulator and filter convert the received digital PCM data to the analog output required by the earphone interface. earphone amplifiers The analog signal can be routed to either of two earphone amplifiers, one with differential output (EAR1ON and EAR1OP) and one with single-ended output (EAR2O). Clicks and pops are suppressed for EAR1 differential output only. tone generator The tone generator provides generation of standard DTMF tones which are output to (1) the buzzer driver, as a PDM signal, (2) the receive path DAC for outputting through the earphone, or (3) as PCMO data. The integer value is loaded into one of two 8-bit registers, the high-tone register (04), or the low-tone register (05) (see the Register Map Addressing section). The tone output is 2 dB higher when applied to the high tone register (04). The high DTMF tones must be applied to the high-tone register, and the low DTMF tones to the low-tone register. The tone signals can be generated with three different resolutions at ∆F= 7.8125 Hz, 15.625 Hz, and 31.250 Hz. The resolution option can be selected by setting the register (06). analog mux The analog switch can be used to source an analog signal to two different loads. The output can be reselected by setting the auxiliary register (06). www.ti.com 7 TLV320AIC1110 SLAS359 – DECEMBER 2001 detailed description (continued) DTMF gain MUX The DTMF gain MUX selects the signal path and applies the appropriate gain setting. Therefore the device is either in tone mode or in voice mode. When set in the voice mode, the gain is controlled by the auxiliary register and is set to 0 dB or 6 dB. When set in the tone mode, the gain is from –12 dB to 12 dB in 6-dB steps which is set by the volume control register. The gain setting is controlled by the RXPGA register. This will not create any control contention since the device is working in one mode at a time. Terminal Functions TERMINAL† NAME NO. I/O DESCRIPTION µBGA TQFP AVDD AVSS A1 32 I Analog positive power supply J1 8 I Analog negative power supply (use for ground connection) BUZZCON F9 19 O Buzzer output, a pulse-density modulated signal to apply to external buzzer driver DVDD J6 13 I Digital positive power supply DVSS J7 14 I Digital negative power supply EAR1ON A6 27 O Earphone 1 amplifier output (–) EAR1OP A4 29 O Earphone 1 amplifier output (+) EAR2O A2 31 O Earphone 2 amplifier output EARVDD EARVSS A5 28 I Analog positive power supply for the earphone amplifiers A3, A7 30, 26 I Analog negative power supply for the earphone amplifiers MBIAS B1 1 O Microphone bias supply output, no decoupling capacitors MCLK C9 22 I Master system clock input (2.048 MHz, digital) MIC1P C1 2 I MIC1 input (+) MIC1N D1 3 I MIC1 input (–) MIC2P E1 4 I MIC2 input (+) MIC2N F1 5 I MIC2 input (–) MUXIN H1 7 I Analog MUX input MUXOUT1 J2 9 I Analog MUX output MUXOUT2 J3 10 I Analog MUX output PCMI J8 15 I Receive PCM input PCMO J9 16 O Transmit PCM output PCMSYN G9 18 I PCM frame sync PCMCLK H9 17 I PCM data clock PLLVSS PLLVDD A9 24 I PLL negative power supply A8 25 I PLL digital power supply PWRUPSEL E9 20 I Selects the power-up default mode REXT G1 6 I/O Internal reference current setting terminal (use precision 100-kΩ resistor and no filtering capacitors) RESET D9 21 I SCL J5 12 I Active low reset I2C-bus serial clock. This input is used to synchronize the data transfer from and to the PCM codec. SDA J4 11 I/O I2C-bus serial address/data input/output. This is a bidirectional terminal used to transfer register control addresses and data into and out of the codec. It is an open-drain terminal and therefore requires a pullup resistor to VDD (typical 10 kΩ for 100 kHz). VSS B9 23 I Ground return for bandgap internal reference (use for ground connection) † All MicroStar Junior BGA pins that are not mentioned have no internal connection. 8 www.ti.com TLV320AIC1110 SLAS359 – DECEMBER 2001 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, AVDD, DVDD, PLLVDD, EARVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V Output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating free air temperature range (industrial temperature) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C Storage temperature range, testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C Lead temperature 1,6 mm from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C TA = 85°C POWER RATING TQFP 702 mW 7.2 mW/°C 270 mW Low dissipation printed circuit board (PCB) MicroStar Junior BGA 660 mW 164 mW/°C 220 mW Low dissipation PCB MicroStar Junior BGA 2.75 W 36 mW/°C 917 mW High dissipation PCB COMMENTS recommended operating conditions (see Notes 1 and 2) MIN Supply voltage, AVDD, DVDD, PLLVDD, EARVDD NOM 2.7 High-level input voltage, VIH MAX UNIT 3.3 V 0.7 x VDD V Low-level input voltage, VIL 0.3 x VDD Load impedance between EAR1OP and EAR1ON-RL Load impedance for EAR2OP-RL V 8 to 32 Ω 32 Ω Operating free-air temperature, TA – 40 85 C NOTES: 1. To avoid possible damage and resulting reliability problems to these CMOS devices, follow the power-on initialization paragraph, described in the Principles of Operation. 2. Voltages are with respect to AVSS, DVSS, PLLVSS , and EARVSS. electrical characteristics over recommended ranges of supply voltage and free-air temperature (unless otherwise noted) supply current PARAMETER IDD Supply current from VDD TEST CONDITIONS TYP MAX Operating, EAR1 selected, MicBias disabled 4.5 6 mA Operating, EAR2 selected, MicBias disabled 4.5 6 mA 2 10 µA 10 30 µA 5 10 ms Power down room temperature, VDD = 3 V, Reg 6 bit 7 = 1, MClk not present (see Note 3) Power down room temperature, VDD = 3 V, , Reg 6 bit 7 = 0, MClk not present (see Note 3) ton(i) Power-up time from power down MIN UNIT NOTE 3: VIHMIN = VDD, VILMAX = VSS. www.ti.com 9 TLV320AIC1110 SLAS359 – DECEMBER 2001 electrical characteristics over recommended ranges of supply voltage and free-air temperature (unless otherwise noted) (continued) digital interface PARAMETER TEST CONDITIONS MAX UNIT High-level output voltage PCMO (BUZZCON) IIH IIL High-level input current, any digital input Ci Input capacitance Co Output capacitance 20 pF RL Load impedance (BUZZCON) 5 kΩ Low-level input current, any digital input VDD = 3 V VDD = 3 V TYP VOH VOL Low-level output voltage PCMO IOH = – 3.2 mA, IOL = 3.2 mA, MIN DVDD– 0.25 V VI = VDD VI = VSS 0.25 V 10 µA 10 µA 10 pF microphone interface PARAMETER TEST CONDITIONS VIO IIB Input offset voltage at MIC1N, MIC2N Ci Input capacitance at MIC1N, MIC2N Vn Microphone input referred noise, psophometrically weighted, (C-message weighted is similar) IOmax V(mbias) See Note 4 Input bias current at MIC1N, MIC2N MIN TYP –5 – 300 MAX UNIT 5 mV 300 nA 5 MIC amp 1 gain = 23.5 dB MIC amp 2 gain = 0 dB Output source current—MBIAS 3 4.7 µVrms 1.2 mA 2.5 2.65 V 60 100 kΩ 1 Microphone bias supply voltage (see Note 5) 2.3 MICMUTE pF – 80 Input impedance Fully differential 35 dB NOTES: 4. Measured while MIC1P and MIC1N are connected together. Less than 0.5-mV offset results in 0 value code on PCMOUT. 5. Not a JEDEC symbol. 10 www.ti.com TLV320AIC1110 SLAS359 – DECEMBER 2001 electrical characteristics over recommended ranges of supply voltage and free-air temperature (unless otherwise noted) (continued) speaker interface PARAMETER TEST CONDITIONS TYP MAX VDD = 2.7 V, fully differential, 8-Ω load, 3-dBm0 output, volume control = – 3 dB, RXPGA = – 4 dB level 161 200 VDD = 2.7 V, fully differential, 16-Ω load, 3-dBm0 output, volume control = – 3 dB, RXPGA = – 2 dB level 128 160 VDD = 2.7 V, fully differential, 32-Ω load, 3-dBm0 output, volume control = – 3 dB, RXPGA = – 1 dB level 81 100 Earphone AMP2 output power (see Note 6) VDD = 2.7 V, single-ended, 32-Ω load, 3-dBm0 output 10 12.5 mW Output offset voltage at EAR1 Fully differential mV Earphone AMP1 output power (see Note 6) VOO IOmax Maximum out output ut current for EAR1 (rms) Maximum output current for EAR2 (rms) MIN ±5 ± 30 3-dBm0 input, 8-Ω load 141 178 3-dBm0 input, 16-Ω load 90 112 3-dBm0 input, 32-Ω load 50 63 17.7 22.1 3-dBm0 input EARMUTE – 80 UNIT mW mA dB NOTE 6: Maximum power is with a load impedance of –25%. transmit gain and dynamic range, companded mode (µ-law or A-law) or linear mode selected, transmit slope filter bypassed (see Notes 7 and 8) PARAMETER Transmit reference-signal level (0 dB) Overload signal level (3 dBm0) Overload-signal Absolute gain error TEST CONDITIONS MAX UNIT Differential 87.5 mVpp Differential, normal mode 124 Differential, extended mode 31.5 0-dBm0 input signal, VDD ±10% MIC1N, MIC1P to PCMO at 3 dBm0 to –30 dBm0 G i error with ith iinputt llevell relative l ti tto gain i att Gain –10 dBm0 MIC1N, MIC1N MIC1P to PCMO MIN TYP –1 1 – 0.5 0.5 MIC1N, MIC1P to PCMO at –31 dBm0 to –45 dBm0 –1 1 MIC1N, MIC1P to PCMO at –46 dBm0 to –55 dBm0 –1.2 1.2 mVpp dB dB NOTES: 7. Unless otherwise noted, the analog input is 0 dB, 1020-Hz sine wave, where 0 dB is defined as the zero-reference point of the channel under test. 8. The reference signal level, which is input to the transmit channel, is defined as a value 3 dB below the full-scale value of 88-mVrms. transmit gain and dynamic range, companded mode (µ-law or A-law) or linear mode selected, transmit slope filter enabled (see Notes 7 and 8) PARAMETER Transmit reference-signal level (0 dB) Overload signal level (3 dBm0) Overload-signal Absolute gain error MAX UNIT Differential TEST CONDITIONS 87.5 mVpp Differential, normal mode 124 Differential, extended mode 31.5 0-dBm0 input signal, VDD ±10% MIC1N, MIC1P to PCMO at 3 dBm0 to – 30 dBm0 Gain G i error with ith iinputt llevell relative l ti tto gain i att –10 dBm0 MIC1N, MIC1N MIC1P to PCMO MIN TYP –1 1 – 0.5 0.5 MIC1N, MIC1P to PCMO at – 31 dBm0 to – 45 dBm0 –1 1 MIC1N, MIC1P to PCMO at – 46 dBm0 to – 55 dBm0 –1.2 1.2 mVpp dB dB NOTES: 7. Unless otherwise noted, the analog input is 0 dB, 1020-Hz sine wave, where 0 dB is defined as the zero-reference point of the channel under test. 8 The reference signal level, which is input to the transmit channel, is defined as a value 3 dB below the full-scale value of 88-mVrms. www.ti.com 11 TLV320AIC1110 SLAS359 – DECEMBER 2001 electrical characteristics over recommended ranges of supply voltage and free-air temperature (unless otherwise noted) (continued) transmit filter transfer, companded mode (µ-law or A-law) or linear mode selected, transmit slope filter bypassed (MCLK = 2.048 MHz) PARAMETER Gain G i relative l ti tto iinputt signal i l gain i att 1020 H Hz, iinternal t l hi high-pass h filter disabled Gain relative to in input ut signal gain at 1020 Hz, internal high high-pass ass filter enabled TEST CONDITIONS MIN TYP MAX fMIC1 or fMIC2