TLV320AIC28IRGZR

  www.ti.com SLAS418B − FEBRUARY 2004 − REVISED MAY 2005 
    
 
 
      FEATURES D Stereo Audio DAC and Mono Audio ADC Support Rates Up to 48 ksps D High Quality 95-dB Stereo Audio Playback Performance D MIC Preamp and Hardware Automatic Gain Control With Up to 59.5-dB Gain D Stereo 16-
Headphone Amplifier With Capless Output Option D 400-mW 8-
Audio Power Amp With Direct Battery Supply Connection D 32-
Differential Earpiece Driver D Integrated PLL For Flexible Audio Clock Generation D Low Power 19-mW Stereo Audio Playback at 48 ksps and 3.3-V Analog Supply level D Programmable Digital Audio Bass/Treble/ EQ/De-Emphasis D Auto-Detection of Jack Insertion, Headset Type, and Button Press D Direct Battery Measurement Accepts Up to 6-V Input D On-Chip Temperature and Auxiliary Input Measurement D Programmable Measurement Converter Resolution, Speed, Averaging, and Timing D SPI and I2S Serial Interfaces D Full Power-Down Control D 48-Pin QFN Package APPLICATIONS D Personal Digital Assistants D Cellular Smartphones D Digital Still Cameras D Digital Camcorders D MP3 Players DESCRIPTION The TLV320AIC28 is a low-power, high-performance audio codec with 16/20/24/32-bit 95-dB stereo playback, mono record functionality at up to 48 ksps. Two microphone inputs include independent programmable bias voltages, built-in pre-amps, and hardware automatic gain control, with single-ended or fully-differential signal input capabilities. The stereo 16-Ω headphone drivers on the AIC28 support capless as well as ac-coupled output configurations. An 8-Ω BTL differential speaker driver provides up to 400 mW of power and 98-dB SNR, while a differential driver is also available for driving a 32-Ω speaker or telephone earpiece. A programmable digital audio effects processor enables bass, treble, midrange, or equalization playback processing. The digital audio data format is programmable to work with popular audio standard protocols (I2S, DSP, left/right justified) in master or slave mode, and also includes an on-chip programmable PLL for flexible clock generation capability. Highly configurable software power control is provided, enabling 48 ksps stereo audio playback to 16-Ω headphones at 19 mW with a 3.3-V analog supply level. The AIC28 offers a 12-bit measurement ADC and internal reference voltage. It includes an on-chip temperature sensor capable of reading 0.3°C resolution, as well as a battery measurement input capable of reading battery voltages up to 6 V, while operating at an analog supply as low as 3 V. The AIC28 is available in a 48-lead 7 x 7 mm QFN package. US Patent No. 624639 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SPI is a trademark of Motorola, Inc. I2S is a trademark of Philips Corporation.  
 
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  www.ti.com SLAS418B − FEBRUARY 2004 − REVISED MAY 2005 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION PRODUCT PACKAGE PACKAGE DESIGNATOR OPERATING TEMPERATURE RANGE TLV320AIC28 QFN-48 RGZ −40°C to +85°C ORDERING NUMBER TRANSPORT MEDIA TLV320AIC28IRGZ Rails, 52 TLV320AIC28IRGZR Tape and Reel, 2500 PIN ASSIGNMENTS DVSS DVDD BCLK WCLK SDIN SDOUT MCLK SCLK MISO MOSI SS DAV QFN PACKAGE (TOP VIEW) 48 47 46 45 44 43 42 41 40 39 38 37 IOVDD PWR_DN RESET GPIO2 GPIO1 AVDD2 AVSS2 AVDD1 NC NC NC NC 1 36 2 35 3 34 4 33 5 32 6 31 7 30 8 29 9 28 10 27 11 26 12 25 AVSS1 VREF VBAT AUX2 AUX1 BUZZ_IN CP_OUT CP_IN MICIN_HND MICBIAS_HND MICIN_HED MICBIAS_HED 13 14 15 16 17 18 19 20 21 22 23 24 2 DRVSS2 OUT8P BVDD OUT8N DRVSS1 VGND SPKFC DRVDD SPK2 SPK1 OUT32N MIC_DETECT_IN 
  www.ti.com SLAS418B − FEBRUARY 2004 − REVISED MAY 2005 Terminal Functions PIN NAME 1 IOVDD 2 PWR_DN 3 RESET 4 5 DESCRIPTION PIN NAME DESCRIPTION IO Supply 25 MIC_DETECT_IN Microphone detect input Hardware power down 26 OUT32N Hardware reset 27 SPK1 Headset driver output/receiver driver output GPIO2 General purpose IO 28 SPK2 Headset driver output GPIO1 General purpose IO 29 DRVDD Headphone driver power supply 6 AVDD2 PLL analog power supply 30 SPKFC Driver feedback/ speaker detect input 7 AVSS2 Analog ground 31 VGND Virtual ground for audio output 8 AVDD1 Audio ADC, DAC, reference, SAR ADC analog power supply 32 DRVSS1 Driver ground 9 NC No connect 33 OUT8N Loudspeaker driver output 10 NC No connect 34 BVDD Battery power supply 11 NC No connect 35 OUT8P Loudspeaker driver output 12 NC No connect 36 DRVSS2 13 AVSS1 Analog ground 37 DAV 14 VREF Reference voltage for SAR ADC 38 SS 15 VBAT Battery monitor input 39 MOSI SPI Serial data input 16 AUX2 Secondary auxiliary input 40 MISO SPI Serial data output 17 AUX1 First auxiliary input 41 SCLK SPI Serial clock input 18 BUZZ_IN Buzzer input 42 MCLK Master clock 19 CP_OUT Output to cell phone module 43 SDOUT Audio data output 20 CP_IN Input from cell phone module 44 SDIN Audio data input 21 MICIN_HND Handset microphone input 45 WCLK Audio word clock 22 MICBIAS_HND Handset microphone bias voltage 46 BCLK Audio bit clock 23 MICIN_HED Headset microphone input 47 DVDD Digital core supply 24 MICBIAS_HED Headset microphone bias voltage 48 DVSS Digital core and IO ground Receiver driver output Driver ground Auxiliary data available output SPI Slave select input ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1), (2) UNITS AVDD1/2 to AVSS1/2 −0.3 V to 3.9 V DRVDD to DRVSS1/2 −0.3 V to 3.9 V BVDD to DRVSS1/2 −0.3 V to 4.5 V IOVDD to DVSS −0.3 V to 3.9 V Digital input voltage to DVSS −0.3 V to IOVDD + 0.3 V Analog input (except VBAT) voltage to AVSS1/2 −0.3 V to AVDD + 0.3 V VBAT input voltage to AVSS1/2 −0.3 V to 6 V AVSS1/2 to DRVSS1/2 to DVSS −0.1 V to 0.1 V AVDD1/2 to DRVDD −0.1 V to 0.1 V Operating temperature range −40°C to 85°C Storage temperature range −65°C to 105°C Junction temperature (TJ Max) Power dissipation QFN package 105°C (TJ Max − TA)/θJA 27°C/W θJA Thermal impedance (with thermal pad soldered to board) Lead temperature Infrared (15 sec) 240°C (1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) If the AIC28 is used to drive high power levels to an 8-Ω load for extended intervals at an ambient temperature above 80°C, multiple vias should be used to electrically and thermally connect the thermal pad on the QFN package to an internal heat dissipating ground plane on the user’s PCB. 3 
  www.ti.com SLAS418B − FEBRUARY 2004 − REVISED MAY 2005 ELECTRICAL CHARACTERISTICS At +25°C, AVDD1, AVDD2, DRVDD, IOVDD = 3.3 V, BVDD = 3.9 V, DVDD = 1.8 V, Vref = 2.5 V, Fs (Audio) = 48 kHz, unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNITS BATTERY MONITOR INPUTS Input voltage range 0.5 Input leakage current Battery conversion not selected Accuracy Variation across temperature after system calibration at 4 V battery voltage and room temperature 6.0 V ±1 µA ±15 mV AUXILIARY A/D CONVERTER Resolution Programmable: 8-, 10-,12-bits No missing codes 12-Bit resolution 8 12 Bits 11 Bits Integral nonlinearity −5 5 LSB Offset error −6 6 LSB Gain error −6 6 Noise LSB µVrms 50 VOLTAGE REFERENCE (VREF) VREF output programmed = 2.5 V Voltage range 2.3 VREF output programmed = 1.25 V External reference Reference drift Internal VREF = 1.25 V Current drain Extra current drawn when the internal reference is turned on. 2.5 2.7 V 1.25 1.1 2.5 V 50 ppm/°C 750 µA AUDIO CODEC ADC DECIMATION FILTER CHARACTERISTICS ±0.1 dB −0.25 dB Filter gain at 0.45 Fs −3.0 dB Filter gain at 0.5 Fs −17.5 dB Filter gain from 0 to 0.39 Fs Filter gain at 0.4125 Fs Filter gain from 0.55 Fs to 64 Fs Group delay 4 −75 dB 17/Fs sec 
  www.ti.com SLAS418B − FEBRUARY 2004 − REVISED MAY 2005 ELECTRICAL CHARACTERISTICS (continued) At +25°C, AVDD1, AVDD2, DRVDD, IOVDD = 3.3 V, BVDD = 3.9 V, DVDD = 1.8 V, Int. Vref = 2.5 V, Fs (Audio) = 48 kHz, unless otherwise noted (continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS MICIN_HED 1020 Hz sine wave input, Fs = 48 ksps MICROPHONE INPUT TO ADC Full-scale input voltage (0 dB) 0.707 Input common mode SNR Measured as idle channel noise, 0 dB gain, A-weighted THD 0.63 Vrms input, 0-dB gain PSRR 217 Hz, 100 mV on AVDD1/2(1) 1020 Hz, 100 mV on AVDD1/2(1) Mute attenuation Output code with 0.63 Vrms sine wave input at 1 kHz 80 V 90 dBA −81 −72 dB 55 dB 55 dB 0000H Only ADC on Input resistance Vrms 1.5 ADC and Sidetone on 15 50 kΩ 8 16 kΩ Input capacitance 10 pF HEADSET MICROPHONE BIAS Voltage range PSRR Sourcing current Register 1DH/Page 2, D7−D8=00 3.3 Register 1DH/Page 2, D7−D8=01 2.5 Register 1DH/Page 2, D7−D8=1X 2 217 Hz, 100 mV on AVDD1/2 55 217 Hz, 100 mV on BVDD 74 1020 Hz, 100 mV on AVDD1/2 55 1020 Hz, 100 mV on BVDD 74 Voltage drop 32 ms duration (with 4 ms clock resolution) − 10 => 64 ms duration (with 8 ms clock resolution) − 11 => 128 ms duration (with 16 ms clock resolution) − Headset detect flag is available till headset is connected. D Button Detection − Interrupt polarity: Active high. − Typical interrupt duration: Button pressed time + clock resolution. Clock resolution depends upon debounce programmability. − Typical interrupt delay from button: Debounce duration + 0.5ms − Debounce programmability: − 00 => No glitch rejection − 01 => 8 ms duration (with 1 ms clock resolution) − 10 => 16 ms duration (with 2 ms clock resolution) − 11 => 32 ms duration (with 4 ms clock resolution) − Button detect flag is set when button is pressed. It gets clear when flag read is done after button press removal. AUDIO ROUTING Audio Interface for Smart-Phone Applications The AIC28 supports audio routing features to combine various analog inputs and route them to analog outputs or the ADC for smart−phone applications. In smart-phone applications, the AIC28 can be used to interface the cell-phone module to microphones and speakers. The AIC28 allows the input from the cell-phone module to be routed to different speakers through a PGA which supports a range of 12 dB to –34.5 dB in steps of 0.5 dB. The cell-phone input can also be mixed with the microphone input for recording through the ADC. The microphone or DAC audio can be routed to the cell-phone output. The buzzer input from cell-phone can be routed to the speakers through a PGA. The buzzer input supports PGA range of 0 dB to –45 dB in steps of 3 dB. The mixing and PGA are under full software control. The mixing feature can be used even when both ADC and DAC are powered down. Cell-phone PGA, microphone PGA and buzzer PGA includes soft-stepping logic. Soft-stepping logic works on Fsref if DAC is powered up otherwise; it works on internal oscillator clocks. 32 
  www.ti.com SLAS418B − FEBRUARY 2004 − REVISED MAY 2005 Analog Mixer The analog mixer can be used to route the analog input selected for the ADC through an analog volume control and then mix it with the audio DAC output. The analog mixer feature is available only if the single ended microphone input or the AUX input is selected as the input to the ADC, not when the ADC input is configured in fully-differential mode. This feature is available even if the ADC and DAC are powered down. The analog volume control has a range from +12 dB to –34.5 dB in 0.5 dB steps plus mute and includes soft−stepping logic. The internal oscillator is used for soft−stepping whenever the ADC and DAC are powered down. Keyclick A special circuit has been included for inserting a square−wave signal into the analog output signal path based on register control. This functionality is intended for generating keyclick sounds for user feedback. Register 04H/Page 2 contains bits that control the amplitude, frequency, and duration of the square−wave signal. The frequency of the signal can be varied from 62.5 Hz to 8 kHz and its duration can be programmed from 2 periods to 32 periods. Whenever this register is written, the square wave is generated and coupled into the audio output. The keyclick enable bit D15 of control register 04H/Page 2 is reset after the duration of a keyclick is played out. This capability is available even when the ADC and DAC are powered down. OPERATION—AUXILIARY MEASUREMENT Auxiliary ADC Converter The auxiliary analog inputs (battery voltage monitor, chip temperature, and auxiliary inputs) are provided via a multiplexer to the successive approximation register (SAR) analog-to-digital (A/D) converter. The ADC architecture is based on capacitive redistribution architecture, which inherently includes a sample/hold function. The ADC is controlled by an ADC control register. Several modes of operation are possible, depending upon the bits set in the control register. Channel selection, scan operation, averaging, resolution, and conversion rate may all be programmed through this register. These modes are outlined in the sections below for each type of analog input. The results of conversions made are stored in the appropriate result register. Data Format The AIC28 output data is in unsigned Binary format and can be read from registers over the SPI interface. Reference The AIC28 has an internal voltage reference that can be set to 1.25 V or 2.5 V, through the reference control register. The internal reference voltage should only be used in the single-ended mode for battery monitoring, temperature measurement, and for utilizing the auxiliary inputs. An external reference can also be applied to the VREF pin, and the internal reference can be turned off. Variable Resolution The AIC28 provides three different resolutions for the ADC: 8, 10 or 12 bits. Performing the conversions at lower resolution reduce the amount of time it takes for the ADC to complete its conversion process, which lowers power consumption. Conversion Clock and Conversion Time The AIC28 contains an internal 8 MHz clock, which is used to drive the state machines inside the device that perform the many functions of the part. This clock is divided down to provide a clock to run the ADC. The division ratio for this clock is set in the ADC control register. The ability to change the conversion clock rate allows the user to choose the optimal value for resolution, speed, and power. If the 8 MHz clock is used directly, the ADC is limited to 8-bit resolution; using higher resolutions at this speed does not result in accurate conversions. Using a 4 MHz conversion clock is suitable for 10-bit resolution; 12-bit resolution requires that the conversion clock run at 1 or 2 MHz. Regardless of the conversion clock speed, the internal clock runs nominally at 8 MHz. The conversion time of the AIC28 is dependent upon several functions. While the conversion clock speed plays an important role in the time it takes for a conversion to complete, a certain number of internal clock cycles are needed for proper 33 
  www.ti.com SLAS418B − FEBRUARY 2004 − REVISED MAY 2005 sampling of the signal. Moreover, additional times, such as the panel voltage stabilization time, can add significantly to the time it takes to perform a conversion. Conversion time can vary depending upon the mode in which the AIC28 is used. Throughout this data sheet, internal and conversion clock cycles are used to describe the times that many functions take to execute. Considering the total system design, these times must be taken into account by the user. When both the audio ADC and DAC are powered down, the auxiliary ADC uses an internal oscillator for conversions. However, to save power whenever audio ADC or DAC are powered up, the internal oscillator is powered down and MCLK and BCLK are used to clock the auxiliary ADC. The AIC28 uses the programmed value of bit D13 in control register 06H/page 2 and the PLL programmability to derive a clock from MCLK. The various combinations are listed in Table 3. Table 3. Conversion Clock Frequency D13=0 (in control register 06H/page 2) D13=1 (in control register 06H/page 2) PLL enabled MCLK × K ×13 P ×160 MCLK × K ×17 P ×192 PLL disabled MCLK ×13 Q ×10 MCLK ×17 Q ×12 Temperature Measurement In some applications, such as battery charging, a measurement of ambient temperature is required. The temperature measurement technique used in the AIC28 relies on the characteristics of a semiconductor junction operating at a fixed current level. The forward diode voltage (VBE) has a well-defined characteristic versus temperature. The ambient temperature can be predicted in applications by knowing the 25°C value of the VBE voltage and then monitoring the variation of that voltage as the temperature changes. The AIC28 offers two modes of temperature measurement. The first mode requires a single reading to predict the ambient temperature. A diode, as shown in Figure 25, is used during this measurement cycle. This voltage is typically 600 mV at +25°C with a 20-µA current through it. The absolute value of this diode voltage can vary a few millivolts. The temperature coefficient of this voltage is typically 2 mV/°C. During the final test of the end product, the diode voltage at a known room temperature should be stored in nonvolatile memory. Further calibration can be done to calculate the precise temperature coefficient of the particular. This method has a temperature resolution of approximately 0.3°C/LSB and accuracy of approximately ±2°C with two-temperature calibration. Figure 26 and Figure 27 shows typical plots with single and two-temperature calibration respectively. X+ MUX A/D Converter Temperature Select TEMP0 TEMP1 Figure 25. Functional Block Diagram of Temperature Measurement Mode 34 
  www.ti.com SLAS418B − FEBRUARY 2004 − REVISED MAY 2005 10 Error in Measurement − °C 8 6 4 2 0 −2 −4 −6 −8 −10 −40 −20 0 20 40 60 80 100 TA − Free-Air Temperature −
C Figure 26. Typical Plot of Single Measurement Method After Calibrating for Offset at Room Temperature 0.20 Error in Measurement − °C 0 −0.20 −0.40 −0.60 −0.80 −1 −1.20 −40 −20 0 20 40 60 TA − Free-Air Temperature −
C 80 100 Figure 27. Typical Plot of Single Measurement Method After Calibrating for Offset and Gain At Two Temperatures The second mode uses a two-measurement (differential) method. This mode requires a second conversion with a current 82 times larger. The voltage difference between the first (TEMP1) and second (TEMP2) conversion, using 82 times the bias current, is represented by: kT q ln(N) where: N is the current ratio = 82 k = Boltzmann’s constant (1.38054 • 10−23 electrons volts/degrees Kelvin) q = the electron charge (1.602189 • 10−19 °C) T = the temperature in degrees Kelvin The equation for the relation between differential code and temperature may vary slightly from device to device and can be calibrated at final system test by the user. This method provides resolution of approximately 1.5°C/LSB and accuracy of approximately ±4°C after calibrating at room temperature. 35 
  www.ti.com SLAS418B − FEBRUARY 2004 − REVISED MAY 2005 4 Error in Measurement − °C 3 2 1 0 −1 −2 −3 −4 −40 −20 0 20 40 60 TA − Free-Air Temperature −
C 80 100 Figure 28. Typical Plot of Differential Measurement Method After Calibrating for Offset at Room Temperature The AIC28 supports programmable auto-temperature measurement mode, which can be enabled using control register 0CH/page 1. In this mode, the AIC28 can auto-start the temperature measurement after a programmable interval. The user can program minimum and maximum threshold values through a register. If the measurement goes outside the threshold range, the AIC28 sets a flag in the read only control register 0CH/page 1, which gets cleared after the flag is read. The AIC28 can also be configured to send and active high interrupt over GPIO1 by setting D9 in control register 0CH/page 1. The duration of the interrupt is approximately 2 ms. Battery Measurement An added feature of the AIC28 is the ability to monitor the battery voltage on the other side of a voltage regulator (dc/dc converter), as shown in Figure 29. The battery voltage can vary from 0.5 V to 6 V while maintaining the analog supply voltage to the AIC28 at 3.0 V to 3.6 V. The input voltage (VBAT) is divided down by a factor of 5 so that a 6.0 V battery voltage is represented as 1.2 V to the ADC. In order to minimize the power consumption, the divider is only on during the sampling of the battery input. If the battery conversion results in A/D output code of B, the voltage at the battery pin can be calculated as: V BAT + BN 2 5 VREF Where: N is the programmed resolution of A/D VREF is the programmed value of internal reference or the applied external reference. 36 
  www.ti.com SLAS418B − FEBRUARY 2004 − REVISED MAY 2005 LDO or DC-DC Converter Battery 0.5 to 6 V 3.0 V to 3.6 V + − VDD R VBAT ADC 8 kΩ 2 kΩ Figure 29. Battery Measurement Functional Block Diagram See the section Conversion Time Calculation for the AIC28 in this data sheet for timing diagrams and conversion time calculations. For increased protection and robustness, TI recommends a minimum 100−Ω resistor be added in series between the system battery and the VBAT pin. The 100-Ω resistor will cause an approximately 1% gain change in the battery voltage measurement, which can easily be corrected in software when the battery conversion data is read by the operating system. Auxiliary Measurement The auxiliary voltage inputs (AUX1 and AUX2) can be measured in much the same way as the battery inputs except the difference that input voltage is not divided. Applications might include external temperature sensing, ambient light monitoring for controlling the backlight, or sensing the current drawn from the battery. The auxiliary input can also be monitored continuously in scan mode. The AIC28 provides feature to measure resistance using auxiliary inputs. It has two modes of operation: (1) External bias resistance measurement (2) Internal bias resistance measurement. Internal bias resistance measurement mode does not need an external bias resistance of 50 kΩ, but provides less accuracy because of on chip resistance variation, which is typically ±20%. Figure 30 shows connection diagram for resistance measurement mode on AUX1. VREF VREF 50 kΩ 50 kΩ 50 kΩ AUX1 Vsar SAR AUX1 Vsar SAR R R a. Internal bias, Resistance Measurement b. External bias, Resistance Measurement Figure 30. Connection DIagram for Resistance Measurement Resistance can be calculated using following formula: R + 50 KW Vsar VREF * Vsar Where: 37 
  www.ti.com SLAS418B − FEBRUARY 2004 − REVISED MAY 2005 VREF is the SAR ADC reference Vsar is input to the SAR ADC The AIC28 supports programmable auto−auxiliary measurement mode, which can be enabled using control register 0CH/page 1. In this mode, the AIC28 can auto start the auxiliary measurement after a programmable interval. The user can program minimum and maximum threshold values through a register. If the measurement goes outside the threshold range, the AIC28 sets a flag in the read only control register 0CH/page 1, which gets cleared after the flag is read. The AIC28 can also be configured to send an active high interrupt over GPIO1 by setting D9 of control register 0CH/page 1. The duration of the interrupt is approximately 2 ms. See the section Conversion Time Calculation for the AIC28 in this data sheet for timing diagram and conversion time calculation Port Scan If making measurements of VBAT, AUX1, and AUX2 is desired on a periodic basis, the Port Scan mode can be used. This mode causes the AIC28 to sample and convert battery input and both auxiliary inputs. At the end of this cycle, the battery and auxiliary result registers contain the updated values. Thus, with one write to the AIC28, the host can cause three different measurements to be made. See the section Issues at the end of this data sheet for details of a known issue with this mode. See the section Conversion Time Calculation for the AIC28 and subsection Port Scan Operation in this data sheet for timing diagrams and conversion time calculations. Buffer Mode The AIC28 supports a programmable buffer mode, which is applicable auxiliary (BAT, AUX1, AUX2, TEMP1, TEMP2). Buffer mode is implemented using a circular FIFO with a depth of 64. The number of interrupts required to be serviced by a host processor can be reduced significantly buffer mode. Buffer mode can be enabled using control register 02H/page1. Figure 31. Circular Buffer Converted data is automatically written into the FIFO. To control the writing, reading and interrupt process, a write pointer (WRPTR), a read pointer (RDPTR) and a trigger pointer (TGPTR) are used. The read pointer always shows the location, which will be read next. The write pointer indicates the location, in which the next converted data is going to be written. The trigger pointer indicates the location at which an interrupt will be generated if the write pointer reaches that location. Trigger level is the number of the data points needed to be present in the FIFO before generating an interrupt. Figure 31 shows the case when trigger level is programmed as 32. On resetting buffer mode, RDPTR moves to location 1, WRPTR moves to location 1, and TGPTR moves to location equal to programmed trigger level. 38 
  www.ti.com SLAS418B − FEBRUARY 2004 − REVISED MAY 2005 The user can select the input or input sequence, which needs to be converted, from the ADCSM bits of control register 00H/page 1. The converted values are written in a predefined sequence to the circular buffer. The user has flexibility to program a specific trigger level in order to choose the configuration which best fits the application. When the number of converted data, written in FIFO, becomes equal to the programmed trigger level then the device generates an interrupt signal on DAV pin. Buffer mode can be used in single-shot conversion or continuous conversion mode. In single shot conversion mode, once the number of data written reaches programmed trigger level, the AIC28 generates an interrupt and waits for the user to start reading. As soon as the user starts reading the first data from the last converted set, the AIC28 clears the interrupt and starts a new set of conversions and the trigger pointer is incremented by the programmed trigger level. An interrupt is generated again when the trigger condition is satisfied. In continuous conversion mode, once number of data written reaches the programmed trigger level, the AIC28 generates an interrupt. It immediately starts a new set of conversions and the trigger pointer is incremented by the programmed trigger level. An interrupt gets cleared either by writing the next converted data into the FIFO or by starting to read from the FIFO. See the section Conversion Time Calculation for the AIC28 and subsection Buffer Mode Operation in this data sheet for timing diagrams and conversion time calculations. Depending upon how the user is reading data, the FIFO can become empty or full. If the user is trying to read data even if the FIFO is empty, then RDPTR keeps pointing to same location. If the FIFO gets full then the next location is overwritten with newly converted data and the read pointer is incremented by one. While reading the FIFO, the AIC28 provides FIFO empty and full status flags along with the data. The user can also read a status flag from control register 02H/page 1. DIGITAL INTERFACE RESET The device requires reset after power up. This requires a low-to-high transition on the RESET pin after power up for correct operation. Reset initializes all the internal registers, counters and logic. Hardware Power-Down Hardware power-down powers down all the internal circuitry to save power. All the register contents are maintained. General Purpose I/O The AIC28 has two general purpose I/O (GPIO1 and GPIO2), which can be programmed either as inputs or outputs. As outputs they can be programmed to control external logic through the AIC28 registers or send interrupts to the host processor on events like button detect, headset insertion, headset removal, Auxiliary/temperature outside threshold range etc. As inputs they can be used by the host-processor to monitor logic states of signals on the system through the AIC28 registers. SPI Digital Interface All AIC28 control registers are programmed through a standard SPI bus. The SPI allows full-duplex, synchronous, serial communication between a host processor (the master) and peripheral devices (slaves). The SPI master generates the synchronizing clock and initiates transmissions. The SPI slave devices depend on a master to start and synchronize transmissions. A transmission begins when initiated by a master SPI. The byte from the master SPI begins shifting in on the slave MOSI pin under the control of the master serial clock. As the byte shifts in on the MOSI pin, a byte shifts out on the MISO pin to the master shift register. The idle state of the serial clock for the AIC28 is low, which corresponds to a clock polarity setting of 0 (typical microprocessor SPI control bit CPOL = 0). The AIC28 interface is designed so that with a clock phase bit setting of 1 (typical microprocessor SPI control bit CPHA = 1), the master begins driving its MOSI pin and the slave begins driving its MISO pin on the first serial clock edge. The SS pin can remain low between transmissions; however, the AIC28 only interprets command words which are transmitted after the falling edge of SS. 39 
  www.ti.com SLAS418B − FEBRUARY 2004 − REVISED MAY 2005 AIC28 COMMUNICATION PROTOCOL Register Programming The AIC28 is entirely controlled by registers. Reading and writing these registers is controlled by an SPI master and accomplished by the use of a 16-bit command, which is sent prior to the data for that register. The command is constructed as shown in Figure 32. The command word begins with an R/W bit, which specifies the direction of data flow on the SPI serial bus. The following 4 bits specify the page of memory this command is directed to, as shown in Table 4. The next six bits specify the register address on that page of memory to which the data is directed. The last five bits are reserved for future use and should be written only with zeros. Table 4. Page Addressing PG3 PG2 PG1 PG0 0 0 0 0 PAGE ADDRESSED 0 0 0 0 1 1 0 0 1 0 2 0 0 1 1 3 0 1 0 0 Reserved 0 1 0 1 Reserved 0 1 1 0 Reserved 0 1 1 1 Reserved 1 0 0 0 Reserved 1 0 0 1 Reserved 1 0 1 0 Reserved 1 0 1 1 Reserved 1 1 0 0 Reserved 1 1 0 1 Reserved 1 1 1 0 Reserved 1 1 1 1 Reserved To read all the first page of memory, for example, the host processor must send the AIC28 the command 0x8000 – this specifies a read operation beginning at page 0, address 0. The processor can then start clocking data out of the AIC28. The AIC28 automatically increments its address pointer to the end of the page; if the host processor continues clocking data out past the end of a page, the AIC28 sends back the value 0xFFFF. Likewise, writing to page 1 of memory would consist of the processor writing the command 0x0800, which specifies a write operation, with PG0 set to 1, and all the ADDR bits set to 0. This results in the address pointer pointing at the first location in memory on page 1. See the section on the AIC28 memory map for details of register locations. BIT 15 MSB BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 LSB R/W* PG3 PG2 PG1 PG0 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 0 0 0 0 0 Figure 32. AIC28 Command Word SS SCLK MOSI COMMAND WORD DATA Figure 33. Register Write Opration 40 DATA 
  www.ti.com SLAS418B − FEBRUARY 2004 − REVISED MAY 2005 SS SCLK MOSI COMMAND WORD MOSO DATA DATA Figure 34. Register Read Operation AIC28 Memory Map The AIC28 has several 16-bit registers which allow control of the device as well as providing a location for results from the AIC28 to be stored until read by the host microprocessor. These registers are separated into four pages of memory in the AIC28: a data page (page 0), control pages (page 1 and page 2) and a buffer data page (page 3). The memory map is shown in Table 5. Table 5. Memory Map PAGE 0: AUXILIARY DATA REGISTER ADDR REGISTER PAGE 1: AUXILIARY CONTROL REGISTERS ADDR REGISTER PAGE 3: BUFFER DATA REGISTERS PAGE 2: AUDIO CONTROL REGISTERS ADDR REGISTER ADDR REGISTER 00 Reserved 00 AUX ADC 00 Audio Control 1 00 Buffer Location 01 Reserved 01 Status 01 Headset PGA Control 01 Buffer Location 02 Reserved 02 Buffer Mode 02 DAC PGA Control 02 Buffer Location 03 Reserved 03 Reference 03 Mixer PGA Control 03 Buffer Location 04 Reserved 04 Reset Control Register 04 Audio Control 2 04 Buffer Location 05 BAT 05 Configuration 05 Power Down Control 05 Buffer Location 06 Reserved 06 Temperature Max 06 Audio Control 3 06 Buffer Location 07 AUX1 07 Temperature Min 07 Digital Audio Effects Filter Coefficients 07 Buffer Location 08 AUX2 08 AUX1 Max 08 Digital Audio Effects Filter Coefficients 08 Buffer Location 09 TEMP1 09 AUX1 Min 09 Digital Audio Effects Filter Coefficients 09 Buffer Location 0A TEMP2 0A AUX2 Max 0A Digital Audio Effects Filter Coefficients 0A Buffer Location 0B Reserved 0B AUX2 Min 0B Digital Audio Effects Filter Coefficients 0B Buffer Location 0C Reserved 0C Measurement Configuration 0C Digital Audio Effects Filter Coefficients 0C Buffer Location 0D Reserved 0D Programmable Delay 0D Digital Audio Effects Filter Coefficients 0D Buffer Location 0E Reserved 0E Reserved 0E Digital Audio Effects Filter Coefficients 0E Buffer Location 0F Reserved 0F Reserved 0F Digital Audio Effects Filter Coefficients 0F Buffer Location 10 Reserved 10 Reserved 10 Digital Audio Effects Filter Coefficients 10 Buffer Location 11 Reserved 11 Reserved 11 Digital Audio Effects Filter Coefficients 11 Buffer Location 12 Reserved 12 Reserved 12 Digital Audio Effects Filter Coefficients 12 Buffer Location 13 Reserved 13 Reserved 13 Digital Audio Effects Filter Coefficients 13 Buffer Location 14 Reserved 14 Reserved 14 Digital Audio Effects Filter Coefficients 14 Buffer Location 15 Reserved 15 Reserved 15 Digital Audio Effects Filter Coefficients 15 Buffer Location 16 Reserved 16 Reserved 16 Digital Audio Effects Filter Coefficients 16 Buffer Location 17 Reserved 17 Reserved 17 Digital Audio Effects Filter Coefficients 17 Buffer Location 18 Reserved 18 Reserved 18 Digital Audio Effects Filter Coefficients 18 Buffer Location 19 Reserved 19 Reserved 19 Digital Audio Effects Filter Coefficients 19 Buffer Location 1A Reserved 1A Reserved 1A Digital Audio Effects Filter Coefficients 1A Buffer Location 41 
  www.ti.com SLAS418B − FEBRUARY 2004 − REVISED MAY 2005 PAGE 0: AUXILIARY DATA REGISTER ADDR PAGE 1: AUXILIARY CONTROL REGISTERS REGISTER ADDR PAGE 3: BUFFER DATA REGISTERS PAGE 2: AUDIO CONTROL REGISTERS REGISTER ADDR REGISTER ADDR REGISTER 1B Reserved 1B Reserved 1B PLL Programmability 1B Buffer Location 1C Reserved 1C Reserved 1C PLL Programmability 1C Buffer Location 1D Reserved 1D Reserved 1D Audio Control 4 1D Buffer Location 1E Reserved 1E Reserved 1E Handset PGA Control 1E Buffer Location 1F Reserved 1F Reserved 1F Cell & Buzzer PGA Control 1F Buffer Location 20 Reserved 20 Reserved 20 Audio Control 5 20 Buffer Location 21 Reserved 21 Reserved 21 Audio Control 6 21 Buffer Location 22 Reserved 22 Reserved 22 Audio Control 7 22 Buffer Location 23 Reserved 23 Reserved 23 GPIO Control 23 Buffer Location 24 Reserved 24 Reserved 24 AGC−CP_IN Control 24 Buffer Location 25 Reserved 25 Reserved 25 Driver Powerdown Status 25 Buffer Location 26 Reserved 26 Reserved 26 Mic AGC control 26 Buffer Location 27 Reserved 27 Reserved 27 Cell-phone AGC Control 27 Buffer Location 28 Reserved 28 Reserved 28 Reserved 28 Buffer Location 29 Reserved 29 Reserved 29 Reserved 29 Buffer Location 2A Reserved 2A Reserved 2A Reserved 2A Buffer Location 2B Reserved 2B Reserved 2B Reserved 2B Buffer Location 2C Reserved 2C Reserved 2C Reserved 2C Buffer Location 2D Reserved 2D Reserved 2D Reserved 2D Buffer Location 2E Reserved 2E Reserved 2E Reserved 2E Buffer Location 2F−3F Reserved 2F−3F Reserved 2F−3F Buffer Locations 2F−3F Reserved AIC28 Control Registers This section describes each of the registers shown in the memory map of Table 5. The registers are grouped according to the function they control. Note that in the AIC28, bits in control registers may refer to slightly different functions depending upon if you are reading the register or writing to it. AIC28 Data Registers (Page 0) The data registers of the AIC28 hold data results from conversion of auxiliary ADC. All of these registers default to 0000H upon reset. These registers are read only. BAT, AUX1, AUX2, TEMP1 and TEMP2 Registers The results of all ADC conversions are placed in the appropriate data register. The data format of the result word, R, of these registers is right-justified, as follows: 42 Bit 15 MSB Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LSB 0 0 0 0 R11 MSB R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 LSB 
  www.ti.com SLAS418B − FEBRUARY 2004 − REVISED MAY 2005 PAGE 1 CONTROL REGISTER MAP REGISTER 00H: Auxiliary ADC Control BIT NAME D15 RESET VALUE READ/ WRITE FUNCTION 0 R D14 ADST 1(for read) 0 (for write) R/W Reserved. The value of this bit should always be set to zero. ADC STATUS. READ 0 =>ADC is busy 1 => ADC is not busy (default). WRITE 0 => Normal mode (default). 1 => Stop conversion and power down. D13−D10 ADCSM 0000 R/W ADC Scan Mode. 0000 => No scan 0001 => Reserved 0010 => Reserved 0011 => Reserved 0100 => Reserved 0101 => Reserved 0110 => BAT input is converted and the results returned to the BAT data register. 0111 => AUX2 input is converted and the results returned to the AUX2 data register 1000 => AUX1 input is converted and the results returned to the AUX1 data register. 1001 => Auto Scan function: For AUX1, AUX2, TEMP1 or TEMP2 as chosen using control register 0CH/page 1. Scan continues until stop bit is sent or D13−D10 are changed. 1010 => TEMP1 input is converted and the results returned to the TEMP1 data register. 1011 => Port scan function: BAT, AUX1, AUX2 inputs are measured and the results returned to the appropriate data registers. 1100 => TEMP2 input is converted and the results returned to the TEMP2 data register. 1101 => Reserved 1110 => Reserved 1111 => Reserved D9−D8 RESOL 00 R/W Resolution Control. The ADC resolution is specified with these bits. 00 => 12-bit resolution 01 => 8-bit resolution 10 => 10-bit resolution 11 => 12-bit resolution D7−D6 ADAVG 00 R/W Converter Averaging Control. These two bits allow user to specify the number of averages the converter will perform selected by bit D0, which selects either Mean Filter or Median Filter. Mean Filter Median Filter 00 => No average No average 01 => 4-data average 5-data average 10 => 8-data average 9-data average 11 => 16-data average 15-data average D5−D4 ADCR 00 R/W Conversion Rate Control. These two bits specify the internal clock rate, which the ADC uses to control performing a single conversion. These bits are the same whether reading or writing. tconv + N ) 4 ƒ INTCLK Where fINTCLK is the internal clock frequency. For example, with 12-bit resolution and a 2 MHz internal clock frequency, the conversion time is 8 µs. This yields an effective throughput rate of 125 kHz. 00 => 8 MHz internal clock rate (use for 8-bit resolution only) 01 =>4 MHz internal clock rate (use for 8-bit/10-bit resolution only) 10 =>2 MHz internal clock rate 11 =>1 MHz internal clock rate D3−D1 D0 AVGFS 0’s R 0 R/W Reserved Average Filter Select 0 => Mean Filter 1 => Median Filter 43 
  www.ti.com SLAS418B − FEBRUARY 2004 − REVISED MAY 2005 REGISTER 01H: Status Register BIT NAME RESET VALUE READ/ WRITE D15−D14 DAV 10 R/W D13 PWRDN 0 R ADC Power down status 0 => ADC is active 1 => ADC stops conversion and powers down 0 R Reserved 0 R Data Available Status 0 => No data available. 1 => Data is available(i.e one set of conversion is done) Note:− This bit gets cleared only after all the converted data have been completely read out. This bit is not valid in case of buffer mode. 0 R Reserved 0 R BAT Data Register Status 0 => No new data is available in BAT data register 1 => New data is available in BAT data register D12 D11 DAVAIL D10−D7 D6 BSTAT FUNCTION Data Available. These two bits program the function of the DAV pin. 00 => Reserved 01 => Acts as data available (active low) only. The DAV goes low as soon as one set of ADC conversion(s) is completed. For scan mode, DAV remains low as long as all the appropriate registers have not been read out. 10 => Reserved 11 => Reserved Note:− D15−D14 should be rpogrammed to 01 for the AIC28 to operate properly. Note: This bit gets cleared only after the converted data of BAT has been completely read out of the register. This bit is not valid in case of buffer mode. D5 D4 AX1STAT 0 R Reserved 0 R AUX1 Data Register Status 0 => No new data is available in AUX1−data register 1 => New data is available in AUX1−data register Note: This bit gets cleared only after the converted data of AUX1 has been completely read out of the register. This bit is not valid in case of buffer mode. D3 AX2STAT 0 R AUX2 Data Register Status 0 => No new data is available in AUX2−data register 1 => New data is available in AUX2−data register Note: This bit gets cleared only after the converted data of AUX2 has been completely read out of the register. This bit is not valid in case of buffer mode. D2 T1STAT 0 R TEMP1 Data Register Status 0 => No new data is available in TEMP1−data register 1 => New data is available in TEMP1−data register Note: This bit gets cleared only after the converted data of TEMP1 has been completely read out of the register. This bit is not valid in case of buffer mode. D1 T2STAT 0 R TEMP2 Data Register Status 0 => No new data is available in TEMP2−data register 1 => New data is available in TEMP2−data register Note: This bit gets cleared only after the converted data of TEMP2 has been completely read out of the register. This bit is not valid in case of buffer mode. D0 44 0 R Reserved 
  www.ti.com SLAS418B − FEBRUARY 2004 − REVISED MAY 2005 REGISTER 02H: Buffer Control BIT NAME RESET VALUE READ/ WRITE D15 BUFRES 0 R/W Buffer Reset. 0 => Buffer mode is disabled and RDPTR, WRPTR & TGPTR set to their reset value. 1 => Buffer mode is enabled. D14 BUFCONT 0 R/W Buffer Mode Selection 0 => Continuous conversion mode. 1 => Single shot mode. D13−D11 BUFTL 000 R/W Trigger Level TL selection of Buffer used for SAR ADC 000 => 8 001 => 16 010 => 24 011 => 32 100 => 40 101 => 48 110 => 56 111 => 64 D10 BUFOVF 0 R Buffer Full Flag 0 => Buffer is not full. 1 => Buffer is full. This means buffer contains 64 unread converted data. D9 BUFEMF 1 R Buffer Empty Flag 0 => Buffer is not empty. 1 => Buffer is empty. This means there is no unread converted data in the buffer. 0’s R Reserved D8−D0 FUNCTION REGISTER 03H: Reference Control BIT NAME RESET VALUE READ/ WRITE FUNCTION D15−D6 0’s R D5 0 R/W Reserved Reserved. Always write 0 to this bit. D4 VREFM 0 R/W Voltage Reference Mode. This bit configures the VREF pin as either external reference or internal reference. 0 => External reference 1 => Internal reference D3−D2 RPWUDL 00 R/W Reference Power Up Delay. These bits allow for a delay time for measurements to be made after the reference powers up, thereby assuring that the reference has settled 00 => 0 µs 01 => 100 µs 10 => 500 µs 11 => 1000 µs Note: This will be valid only when device is programmed for internal reference and Bit D1 = 1, i.e., reference is powered down between the conversions if not required. D1 RPWDN 1 R/W Reference Power Down. This bit controls the power down of the internal reference voltage. 0 => Powered up at all times. 1 => Powered Down between conversions. Note: When D4 = 0 i.e. device is in external reference mode then the internal reference is powered down always. D0 IREFV 0 R/W Internal Reference Voltage. This bit selects the internal voltage for AUX ADC. 0 => VREF = 1.25 V 1 => VREF = 2.50 V 45 
  www.ti.com SLAS418B − FEBRUARY 2004 − REVISED MAY 2005 REGISTER 04H: Reset Control BIT NAME RESET VALUE READ/ WRITE D15−D0 RSALL R/W FFFFH FUNCTION Reset All. Writing the code 0xBB00, as shown below, to this register causes the AIC28 to reset all its control registers to their default, power−up values. 1011101100000000 => Reset all control registers Others => Do not write other sequences to the register. REGISTER 05H: Reserved BIT NAME D15−D0 RESET VALUE READ/ WRITE 0’s R FUNCTION Reserved REGISTER 06H: Temperature Max Threshold Measurement BIT NAME D15−D13 RESET VALUE READ/ WRITE FUNCTION 0’s R D12 TMXES 0 R/W Reserved Max Temperature (TEMP1 or TEMP2) threshold check enable for Auto/Non−Auto−Scan Measurement. 0 => Max Temperature threshold check is disabled. 1 => Max Temperature threshold check is enabled. Only valid for TEMP1 or TEMP2. Depends on bit TSCAN of control register 0CH/page 1 in case of auto−scan measurement and depends on bits ADCSM of control register 00H/page 1 in case of non−auto−scan measurementa D11−D0 TTHRESH FFFH R/W Temperature Max Threshold. When code due to temperature measurement goes above or equal to programmed threshold value, interrupt is generated. REGISTER 07H: Temperature Min Threshold Measurement BIT NAME D15−D13 RESET VALUE READ/ WRITE 0’s R FUNCTION Reserved D12 TMNES 0 R/W Min Temperature (TEMP1 or TEMP2) threshold check enable for Auto/Non−Auto−Scan Measurement. 0 => Min Temperature threshold check is disabled. 1 => Min Temperature threshold check is enabled. Only valid for TEMP1 or TEMP2. Depends on bit TSCAN of control register 0CH/page 1 in case of auto−scan measurement and depends on bits ADCSM of control register 00H/page 1 in case of non−auto−scan measurement. D11−D0 TTHRESL 000H R/W Temperature Min Threshold. When code due to temperature measurement goes below or equal to programmed threshold value, interrupt is generated. REGISTER 08H: AUX1 Max Threshold Measurement BIT NAME D15−D13 RESET VALUE READ/ WRITE FUNCTION 0’s R D12 A1MXES 0 R/W Max AUX1 threshold check enable for Auto/Non−Auto−Scan Measurement. 0 => Max AUX1 threshold check is disabled. 1 => Max AUX1 threshold check is enabled. D11−D0 A1THRESH FFFH R/W AUX1 Threshold. When code due to AUX1 measurement goes above or equal to programmed threshold value, interrupt is generated. 46 Reserved 
  www.ti.com SLAS418B − FEBRUARY 2004 − REVISED MAY 2005 REGISTER 09H: AUX1 Min Threshold Measurement BIT NAME D15−D13 RESET VALUE READ/ WRITE FUNCTION 0’s R D12 A1MNES 0 R/W Reserved Min AUX1 threshold check enable for Auto/Non−Auto−Scan Measurement. 0 => Min AUX1 threshold check is disabled. 1 => Min AUX1 threshold check is enabled. D11−D0 A1THRESL 000H R/W AUX1 Threshold. When code due to AUX1 measurement goes below or equal to programmed threshold value, interrupt is generated. REGISTER 0AH: AUX2 Max Threshold Measurement BIT NAME RESET VALUE D15−D13 READ/ WRITE FUNCTION 0’s R D12 A2MXES 0 R/W Reserved Max AUX2 threshold check enable for Auto/Non−Auto−Scan Measurement. 0 => Max AUX2 threshold check is disabled. 1 => Max AUX2 threshold check is enabled. D11−D0 A1THRESH FFFH R/W AUX2 Threshold. When code due to AUX2 measurement goes above or equal to programmed threshold value, interrupt is generated. REGISTER 0BH: AUX2 Max Threshold Measurement BIT NAME D15−D13 RESET VALUE READ/ WRITE 0’s R FUNCTION Reserved D12 A2MNES 0 R/W Min AUX2 threshold check enable for Auto/Non−Auto−Scan Measurement. 0 => Min AUX2 threshold check is disabled. 1 => Min AUX2 threshold check is enabled. D11−D0 A2THRESL 000H R/W AUX2 Threshold. When code due to AUX2 measurement goes below or equal to programmed threshold value, interrupt is generated. 47 
  www.ti.com SLAS418B − FEBRUARY 2004 − REVISED MAY 2005 REGISTER 0CH: Measurement Configuration BIT NAME RESET VALUE READ/ WRITE D15 TSCAN 0 R/W TEMP Configuration when Auto−Temperature is selected 0 => TEMP1 is used for auto−temperature function 1 => TEMP2 is used for auto−temperature function D15 A1CONF 0 R/W AUX1 Configuration. 0 => AUX1 is used for voltage measurement. 1 => AUX1 is used for resistance measurement. D14 A2CONF 0 R/W AUX2 Configuration. 0 => AUX2 is used for voltage measurement. 1 => AUX2 is used for resistance measurement. D12 ATEMES 0 R/W Auto Temperature (TEMP1 or TEMP2) measurement enable 0 => Auto temperature measurement is disabled. 1 => Auto temperature measurement is enabled. TEMP1 or TEMP2 selection is depends on TSCAN bit. D11 AA1MES 0 R/W Auto AUX1 measurement enable 0 => Auto AUX1 measurement is disabled. 1 => Auto AUX1 measurement is enabled. D10 AA2MES 0 R/W Auto AUX2 measurement enable 0 => Auto AUX2 measurement is disabled. 1 => Auto AUX2 measurement is enabled. D9 IGPIO1 0 R/W Enable GPIO1 for Auto/Non−Auto−Scan interrupt (this programmability is valid only if D11 & D9 of control register 23H/page 2 are 0’s) 0 => GPIO1 is not selected for interrupt. 1 => GPIO1 is used to send an interrupt. Interrupt is generated when any of TEMP (TEMP1 or TEMP2), AUX1 or AUX2 are not passing threshold D8 THMXFL 0 R Max threshold flag for Temperature (TEMP1 or TEMP2) measurement. 0 => Temperature measurement is less than max threshold setting. 1 => Temperature measurement is greater than or equal to max threshold setting. D7 THMNFL 0 R Min threshold flag for Temperature (TEMP1 or TEMP2) measurement. 0 => Temperature measurement is greater than min threshold setting. 1 => Temperature measurement is less than or equal to max threshold setting. D6 A1HMXFL 0 R Max threshold flag for AUX1measurement. 0 => AUX1 measurement is less than max threshold setting. 1 => AUX1 measurement is greater than or equal to max threshold setting. D5 A1HMNFL 0 R Min threshold flag for AUX1 measurement. 0 => AUX1 measurement is greater than min threshold setting. 1 => AUX1 measurement is less than or equal to max threshold setting. D4 A2HMXFL 0 R Max threshold flag for AUX2measurement. 0 => AUX2 measurement is less than max threshold setting. 1 => AUX2 measurement is greater than or equal to max threshold setting. D3 A2HMNFL 0 R Min threshold flag for AUX2 measurement. 0 => AUX2 measurement is greater than min threshold setting. 1 => AUX2 measurement is less than or equal to max threshold setting. D2 EXTRES 0 R/W 0’s R D1−D0 48 FUNCTION External Bias Resistance Measurement mode 0 => Internal bias resistance measurement mode is enabled. 1 => External bias resistance measurement mode is enabled. Reserved 
  www.ti.com SLAS418B − FEBRUARY 2004 − REVISED MAY 2005 REGISTER 0DH: Programmable Delay In-Between Continuous Conversion BIT NAME RESET VALUE READ/ WRITE D15 NTSPDELEN 0 R/W Programmable delay for auxiliary auto measurement mode 0 => Programmable delay is disabled for auxiliary auto measurement mode. 1 => Programmable delay is enabled for auxiliary auto measurement mode. D14−D12 NTSPDINTV 010 R/W Programming delay in−between conversion for auxiliary auto measurement mode 000 => 1.12 min 001 => 3.36 min 010 => 5.59 min 011 => 7.83 min 100 => 10.01 min 101 => 12.30 min 110 => 14.54 min 111 => 16.78 min Note: These delays are from end of one set of conversion to the start of another set of conversion. D11−D8 FUNCTION 0’s R D7 CLKSEL 0 R/W Reserved Clock selection for the auxiliary converter 0 => Internal oscillator clock is selected. 1 => External MCLK is selected. Note: External clock is used only to control the delay programmed in between the conversion. D6−D0 CLKDIV 0000001 R/W Clock Division used to divide MCLK for getting 1 MHz clock for programmable delay, i.e. MCLK/CLKDIV = 1 MHz, 0000000 => 128, 0000001 => 1, 0000010 => 2, …… 1111110 => 126, 1111111 => 127 REGISTER 0EH: Reserved BIT NAME RESET VALUE READ/ WRITE D15−D8 RESV FFh R/W FUNCTION Reserved. Write only FFh to these bits. 49 
  www.ti.com SLAS418B − FEBRUARY 2004 − REVISED MAY 2005 PAGE 2 CONTROL REGISTER MAP REGISTER 00H: Audio Control 1 BIT NAME RESET VALUE READ/ WRITE D15−D14 ADCHPF 00 R/W D13−D12 FUNCTION ADC High Pass Filter 00 => Disabled 01 => −3db point = 0.0045xFs 10 => −3dB point = 0.0125xFs 11 => −3dB point = 0.025xFs Note: Fs is ADC sample rate 0’s R D11−D10 WLEN 00 R/W Codec Word Length 00 => Word length = 16−bit 01 => Word length = 20−bit 10 => Word length = 24−bit 11 => Word length = 32−bit D9−D8 DATFM 00 R/W Digital Data Format 00 => I2S Mode 01 => DSP Mode 10 => Right Justified 11 => Left Justified Note: Right justified valid only when the ratio between DAC and ADC sample rate is an integer. e.g. ADC = 32 kHz and DAC = 24 kHz or vice−versa is invalid for right justified Mode. 0’s R D7−D6 Reserved Reserved D5−D3 DACFS 000 R/W DAC Sampling Rate 000 => DAC FS = Fsref/1 001 => DAC FS = Fsref/(1.5) 010 => DAC FS = Fsref/2 011 => DAC FS = Fsref/3 100 => DAC FS = Fsref/4 101 => DAC FS = Fsref/5 110 => DAC FS = Fsref/(5.5) 111 => DAC FS = Fsref/6 Note: Fsref is set between 39 kHz and 53 kHz D2−D0 ADCFS 000 R/W ADC Sampling Rate 000 => ADC FS = Fsref/1 001 => ADC FS = Fsref/(1.5) 010 => ADC FS = Fsref/2 011 => ADC FS = Fsref/3 100 => ADC FS = Fsref/4 101 => ADC FS = Fsref/5 110 => ADC FS = Fsref/(5.5) 111 => ADC FS = Fsref/6 Note: Fsref is set between 39 kHz and 53 kHz 50 
  www.ti.com SLAS418B − FEBRUARY 2004 − REVISED MAY 2005 REGISTER 01H: Gain Control for Headset/Aux Input BIT NAME RESET VALUE READ/ WRITE D15 ADMUT_HED 1 R/W Headset/Aux Input Mute 1 => Headset/Aux Input Mute 0 => Headset/Aux Input not muted Note: If AGC is enabled and Headset/Aux Input is selected then ADMUT_HED+ADPGA_HED reflects gain being applied by AGC. D14−D8 ADPGA_HED 1111111 R/W ADC Headset/Aux PGA Settings 0000000 => 0 dB 0000001 => 0.5 dB 0000010 => 1.0 dB ……… 1110110 => 59.0 dB .......... 1111111 => 59.5 dB Note: If AGC is enabled and Headset/Aux Input is selected then ADMUT_HED+ADPGA_HED reflects gain being applied by AGC. If AGC is on, the decoding for read values is as follows 01110111 => +59.5 dB 01110110 => +59.0 dB ……… 00000000 => 0 dB ………. 11101001 => −11.5 dB 11101000 => −12 dB D7−D5 AGCTG_HED 000 R/W AGC Target Gain for Headset/Aux Input. These three bits set the AGC’s targeted ADC output level. 000 => −5.5 dB 001 => −8.0 dB 010 => −10 dB 011 => −12 dB 100 => −14 dB 101 => −17 dB 110 => −20 dB 111 => −24 dB D4−D1 AGCTC_HED 0000 R/W AGC Time Constant for Headset/Aux Input. These four bits set the AGC attack and decay time constants. Time constants remain same irrespective of any sampling frequency FUNCTION Attack time (ms) 0000 8 0001 11 0010 16 0011 20 0100 8 0101 11 0110 16 0111 20 1000 8 1001 11 1010 16 1011 20 1100 8 1101 11 1110 16 1111 20 D0 AGCEN_HED 0 R/W Decay time (ms) 100 100 100 100 200 200 200 200 400 400 400 400 500 500 500 500 AGC Enable for Headset/Aux Input 0 => AGC is off for Headset/Aux Input (ADC Headset/Aux PGA is controlled by ADMUT_HED+ADPGA_HED) 1 => AGC is on for Headset/Aux Input (ADC Headset/Aux PGA is controlled by AGC) 51 
  www.ti.com SLAS418B − FEBRUARY 2004 − REVISED MAY 2005 REGISTER 02H: CODEC DAC Gain Control BIT NAME RESET VALUE READ/ WRITE D15 DALMU 1 R/W DAC Left Channel Mute 1 => DAC Left Channel Muted 0 => DAC Left Channel not muted D14−D8 DALVL 1111111 R/W DAC Left Channel Volume Control 0000000 => DAC left channel volume = 0 dB 0000001 => DAC left channel volume = −0.5 dB ….. 1111110 => DAC left channel volume = −63.0 dB 1111111 => DAC left channel volume = −63.5 dB D7 DARMU 1 R/W DAC Right Channel Mute 1 => DAC Right Channel Muted 0 => DAC Right Channel not muted D6−D0 DARVL 1111111 R/W DAC Right Channel Volume Control 0000000 => DAC right channel volume = 0 dB 0000001 => DAC right channel volume = −0.5 dB ….. 1111110 => DAC right channel volume = −63.0 dB 1111111 => DAC right channel volume = −63.5 dB FUNCTION REGISTER 03H: Mixer PGA Control BIT NAME RESET VALUE READ/ WRITE D15 ASTMU 1 R/W Analog Sidetone Mute Control 1 => Analog sidetone mute 0 => Analog sidetone not muted D14−D8 ASTG 1000101 R/W Analog Sidetone Gain Setting 0000000 => Analog sidetone = −34.5 dB 0000001 => Analog sidetone = −34 dB 0000010 => Analog sidetone = −33.5 dB ... 1000101 => Analog sidetone = 0 dB 1000110 => Analog sidetone = 0.5 dB ... 1011100 => Analog sidetone = 11.5 dB 1011101 => Analog sidetone = 12 dB 1011110 => Analog sidetone = 12 dB 1011111 => Analog sidetone = 12 dB 11xxxxx => Analog sidetone = 12 dB D7−D5 MICSEL 000 R/W Selection for Mic Input and Aux Input for ADC/Cell phone−output/Analog side−tone. 000 => Single-ended input MICIN_HED selected 001 => Single-ended input MICIN_HND selected 010 => Single-ended input AUX1 selected 011 => Single-ended input AUX2 selected 100 => Differential input MICIN_HED and AUX1 connected to ADC. 101 => Differential input MICIN_HED and AUX2 connected to ADC. 110 => Differential input MICIN_HND and AUX1 connected to ADC. 111 => Differential input MICIN_HND and AUX2 connected to ADC. Note: When D7=1 (differential input selected), analog side−tone path is not valid D4 MICADC 0 R/W Selection of ADC input 0 => Nothing connected 1 => Input selected by MICSEL connected to ADC. D3 CPADC 0 R/W Connects Cell phone input to ADC 0 => Cell phone input not connected to ADC. 1 => Cell phone input connected to ADC. D2−D1 Reserved 0’s R Reserved D0 ASTGF 0 R Analog Sidetone PGA Flag (Read Only) 0 => Gain Applied ≠ PGA Register setting 1 => Gain Applied = PGA register setting. Note: This flag indicates when the soft−stepping for analog sidetone is completed. 52 FUNCTION 
  www.ti.com SLAS418B − FEBRUARY 2004 − REVISED MAY 2005 REGISTER 04H: Audio Control 2 BIT NAME RESET VALUE READ/ WRITE D15 KCLEN 0 R/W Keyclick Enable 0 => Keyclick Disabled 1 => Keyclick Enabled Note: This bit is automatically cleared after giving out the keyclick signal length equal to the programmed value. D14−D12 KCLAC 100 R/W Keyclick Amplitude Control 000 => Lowest Amplitude …. 100 => Medium Amplitude …. 111 => Highest Amplitude D11 APGASS 0 R/W Headset/Aux or Handset PGA Soft−stepping control 0 => 0.5 dB change every WCLK or ADWS 1 => 0.5 dB change every 2 WCLK or 2 ADWS FUNCTION When AGC is enabled for Headset/Aux or Handset, this bit is read only and acts as Noise Threshold Flag. The read value indicates the following 0 => signal power greater than noise threshold 1 => signal power is less than noise threshold D10−D8 KCLFRQ 100 R/W Keyclick Frequency 000 => 62.5 Hz 001 => 125 Hz 010 => 250 Hz 011 => 500 Hz 100 => 1 kHz 101 => 2 kHz 110 => 4 kHz 111 => 8 kHz D7−D4 KCLLN 0001 R/W Keyclick Length 0000 => 2 periods key click 0001 => 4 periods key click 0010 => 6 periods key click 0011 => 8 periods key click 0100 => 10 periods key click 0101 => 12 periods key click 0110 => 14 periods key click 0111 => 16 periods key click 1000 => 18 periods key click 1001 => 20 periods key click 1010 => 22 periods key click 1011 => 24 periods key click 1100 => 26 periods key click 1101 => 28 periods key click 1110 => 30 periods key click 1111 => 32 periods key click D3 DLGAF 0 R DAC Left Channel PGA Flag 0 => Gain applied ≠ PGA register setting 1 => Gain applied = PGA register setting. Note: This flag indicates when the soft−stepping for DAC left channel is completed D2 DRGAF 0 R DAC Right Channel PGA Flag 0 => Gain applied ≠ PGA register setting 1 => Gain applied = PGA register setting. Note: This flag indicates when the soft−stepping for DAC right channel is completed 53 
  www.ti.com SLAS418B − FEBRUARY 2004 − REVISED MAY 2005 BIT NAME RESET VALUE READ/ WRITE D1 DASTC 0 R/W D0 ADGAF 0 R FUNCTION DAC Channel PGA Soft−stepping control 0 => 0.5 dB change every WCLK 1 => 0.5 dB change every 2 WCLK Headset/Aux or Handset PGA Flag 1 => Gain applied = PGA register setting. 0 => Gain applied ≠ PGA Register setting Note: This flag indicates when the soft−stepping for PGA is completed. When AGC is enabled for Headset/Aux or Handset, this bit is read−only and acts as Saturation Flag. The read value of this bit indicates the following 0 => AGC is not saturated 1 => AGC is saturated (PGA has reached –12 dB or max PGA applicable). REGISTER 05H: CODEC Power Control BIT NAME RESET VALUE READ/WRITE D15 MBIAS_HND 1 R/W MICBIAS_HND Power−down Control 0 => MICBIAS_HND is powered up. 1 => MICBIAS_HND is powered down. D14 MBIAS_HED 1 R/W MICBIAS_HED Power−down Control 0 => MICBIAS_HED is powered up. 1 => MICBIAS_HED is powered down. D13 ASTPWD 1 R/W Analog Sidetone Power−down Control 0 => Analog sidetone powered up 1 => Analog sidetone powered down D12 SP1PWDN 1 R/W SPK1(Single−Ended)/OUT32N(Differential) Power−down Control 0 => SPK1/OUT32N is powered up 1 => SPK1/OUT32N is powered down D11 SP2PWDN 1 R/W SPK2 Power−down Control 0 => SPK2 is powered up 1 => SPK2 is powered down D10 DAPWDN 1 R/W DAC Power−down Control 0 => DAC powered up 1 => DAC powered down D9 ADPWDN 1 R/W ADC Power−down Control 0 => ADC powered up 1 => ADC powered down D8 VGPWDN 1 R/W Driver Virtual Ground Power−down Control 0 => VGND is powered up 1 => VGND is powered down D7 COPWDN 1 R/W CP_OUT Power−down Control 0 => CP_OUT is powered up 1 => CP_OUT is powered down D6 LSPWDN 1 R/W Loudspeaker (8−Ω Driver) Power−down Control 0 => Loudspeaker (8−Ω driver) is powered up 1 => Loudspeaker (8−Ω driver) is powered down D5 ADPWDF 1 R ADC Power Down Flag 0 => ADC power down is not complete 1 => ADC power down is complete D4 LDAPWDF 1 R DAC Left Power Down Flag 0 => DAC left power down is not complete 1 => DAC left power down is complete D3 RDAPWDF 1 R DAC Right Power Down Flag 0 => DAC right power down is not complete 1 => DAC right power down is complete D2 ASTPWF 1 R Analog Sidetone Power Down Flag 0 => Analog sidetone power down is not complete 1 => Analog sidetone power down is complete 54 FUNCTION 
  www.ti.com SLAS418B − FEBRUARY 2004 − REVISED MAY 2005 BIT NAME RESET VALUE READ/WRITE D1 EFFCTL 0 R/W Digital Audio Effects Filter 0 => Disable digital audio effects filter 1 => Enable digital audio effects filter FUNCTION D0 DEEMPF 0 R/W De−emphasis Filter Enable 0 => Disable de−emphasis filter 1 => Enable de−emphasis filter NOTE: D15−D6 are all 1’s, then full codec section is powered down. REGISTER 06H: Audio Control 3 BIT NAME RESET VALUE READ/ WRITE D15−D14 DMSVOL 00 R/W DAC Channel Master Volume Control 00 => Left channel and right channel have independent volume controls 01 => Left channel volume control is the programmed value of the right channel volume control. 10 => Right channel volume control is the programmed value of the left channel volume control. 11 => same as 00 D13 REFFS 0 R/W Reference Sampling Rate Note: This setting controls the coefficients in the de−emphasis filter, the time−constants in AGC, and internal divider values that generate the clock for the auxiliary measurement ADC. If an Fsref above 48 kHz is being used, then it is recommended to set this to the 48−kHz setting, otherwise either setting can be used. 0 => Fsref = 48.0 kHz 1 => Fsref = 44.1 kHz D12 DAXFM 0 R/W Master Transfer Mode 0 => Continuous data transfer mode 1 => 256−s data transfer mode D11 SLVMS 0 R/W CODEC Master Slave Selection 0 => The AIC28 is slave codec 1 => The AIC28 is master codec D10−D9 FUNCTION 0’s R Reserved D8 ADCOVF 0 R ADC Channel Overflow Flag 0 => ADC channel data is within saturation limits 1 => ADC channel data has exceeded saturation limits. Note: This flag gets reset after register read. D7 DALOVF 0 R DAC Left Channel Overflow Flag 0 => DAC left channel data is within saturation limits 1 => DAC left channel data has exceeded saturation limits Note: This flag gets reset after register read. D6 DAROVF 0 R DAC Right Channel Overflow Flag 0 => DAC right channel data is within saturation limits 1 => DAC right channel data has exceeded saturation limits Note: This flag gets reset after register read. D5−D4 00 R/W Reserved. D3 CLPST 0 R/W MIC AGC Clip Stepping Disable 0 => Disabled 1 => Enabled Note: Valid only when AGC is selected for the Headset/Aux or Handset input. D2−D0 REVID XXX R AIC28 Device Revision ID REGISTER 07H: Digital Audio Effects Filter Coefficients BIT NAME RESET VALUE (IN DECIMAL) READ/ WRITE D15−D0 L_N0 27619 R/W FUNCTION Left channel bass-boost coefficient N0. REGISTER 08H: Digital Audio Effects Filter Coefficients BIT NAME RESET VALUE (IN DECIMAL) READ/ WRITE D15−D0 L_N1 −27034 R/W FUNCTION Left channel bass-boost coefficient N1. 55 
  www.ti.com SLAS418B − FEBRUARY 2004 − REVISED MAY 2005 REGISTER 09H: Digital Audio Effects Filter Coefficients BIT NAME RESET VALUE (IN DECIMAL) READ/ WRITE D15−D0 L_N2 26461 R/W FUNCTION Left channel bass-boost coefficient N2. REGISTER 0AH: Digital Audio Effects Filter Coefficients BIT NAME RESET VALUE (IN DECIMAL) READ/ WRITE D15−D0 L_N3 27619 R/W FUNCTION Left channel bass-boost coefficient N3. REGISTER 0BH: Digital Audio Effects Filter Coefficients BIT NAME RESET VALUE (IN DECIMAL) READ/ WRITE D15−D0 L_N4 −27034 R/W FUNCTION Left channel bass-boost coefficient N4. REGISTER 0CH: Digital Audio Effects Filter Coefficients BIT NAME RESET VALUE (IN DECIMAL) READ/ WRITE D15−D0 L_N5 26461 R/W FUNCTION Left channel bass-boost coefficient N5. REGISTER 0DH: Digital Audio Effects Filter Coefficients BIT NAME RESET VALUE (IN DECIMAL) READ/ WRITE D15−D0 L_D1 32131 R/W FUNCTION Left channel bass-boost coefficient D1. REGISTER 0EH: Digital Audio Effects Filter Coefficients BIT NAME RESET VALUE (IN DECIMAL) READ/ WRITE D15−D0 L_D2 −31506 R/W FUNCTION Left channel bass-boost coefficient D2. REGISTER 0FH: Digital Audio Effects Filter Coefficients BIT NAME RESET VALUE (IN DECIMAL) READ/ WRITE D15−D0 L_D4 32131 R/W FUNCTION Left channel bass-boost coefficient D4. REGISTER 10H: Digital Audio Effects Filter Coefficients BIT NAME RESET VALUE (IN DECIMAL) READ/ WRITE D15−D0 L_D5 −31506 R/W FUNCTION Left channel bass-boost coefficient D5. REGISTER 11H: Digital Audio Effects Filter Coefficients BIT NAME RESET VALUE (IN DECIMAL) READ/ WRITE D15−D0 R_N0 27619 R/W FUNCTION Right channel bass-boost coefficient N0. REGISTER 12H: Digital Audio Effects Filter Coefficients BIT NAME RESET VALUE (IN DECIMAL) READ/ WRITE D15−D0 R_N1 −27034 R/W FUNCTION Right channel bass-boost coefficient N1. REGISTER 13H: Digital Audio Effects Filter Coefficients BIT NAME RESET VALUE (IN DECIMAL) READ/ WRITE D15−D0 R_N2 26461 R/W FUNCTION Right channel bass-boost coefficient N2. REGISTER 14H: Digital Audio Effects Filter Coefficients BIT NAME RESET VALUE (IN DECIMAL) READ/ WRITE D15−D0 R_N3 27619 R/W 56 FUNCTION Right channel bass-boost coefficient N3. 
  www.ti.com SLAS418B − FEBRUARY 2004 − REVISED MAY 2005 REGISTER 15H: Digital Audio Effects Filter Coefficients BIT NAME RESET VALUE (IN DECIMAL) READ/ WRITE D15−D0 R_N4 −27034 R/W FUNCTION Right channel bass-boost coefficient N4. REGISTER 16H: Digital Audio Effects Filter Coefficients BIT NAME RESET VALUE (IN DECIMAL) READ/ WRITE D15−D0 R_N5 26461 R/W FUNCTION Right channel bass-boost coefficient N5. REGISTER 17H: Digital Audio Effects Filter Coefficients BIT NAME RESET VALUE (IN DECIMAL) READ/ WRITE D15−D0 R_D1 32131 R/W FUNCTION Right channel bass-boost coefficient D1. REGISTER 18H: Digital Audio Effects Filter Coefficients BIT NAME RESET VALUE (IN DECIMAL) READ/ WRITE D15−D0 R_D2 −31506 R/W FUNCTION Right channel bass-boost coefficient D2. REGISTER 19H: Digital Audio Effects Filter Coefficients BIT NAME RESET VALUE (IN DECIMAL) READ/ WRITE D15−D0 R_D4 32131 R/W FUNCTION Right channel bass-boost coefficient D4. REGISTER 1AH: Digital Audio Effects Filter Coefficients BIT NAME RESET VALUE (IN DECIMAL) READ/ WRITE D15−D0 R_D5 −31506 R/W FUNCTION Right channel bass-boost coefficient D5. REGISTER 1BH: PLL Programmability BIT NAME RESET VALUE READ/WRITE FUNCTION D15 PLLSEL 0 R/W PLL Enable 0 => Disable PLL. 1 => Enable PLL. D14−D11 QVAL 0010 R/W Q value: Valid when PLL is disabled 0000 => 16, 0001 => 17, 0010 => 2, 0011 => 3, ……. 1100 => 12, 1101 => 13, 1110 => 14, 1111 => 15, D10−D8 PVAL 000 R/W P value: Valid when PLL is enabled 000 => 8, 001 => 1, 010 => 2, 011 => 3, 100 => 4, 101 => 5, 110 => 6, 111 => 7 57 
  www.ti.com SLAS418B − FEBRUARY 2004 − REVISED MAY 2005 D7−D2 J_VAL D1−D0 000001 R/W 00 R J value: Valid when PLL is enabled 000000 => Not valid, 000001 => 1, 000010 => 2, 000011 => 3, …….. 111100 => 60, 111101 => 61, 111110 => 62, 111111 => 63 Reserved (Write only 00) REGISTER ICH: PLL Programmability BIT NAME RESET VALUE READ/WRITE D15−D2 D_VAL 0 (decimal) R/W D1−D0 Reserved 0 R FUNCTION D value: Valid when PLL is enabled D value is valid from 0000 to 9999 in decimal. Greater than 9999 is treated as 9999. Reserved (Write only 00) REGISTER IDH: Audio Control 4 BIT NAME RESET VALUE READ/WRITE D15 ADSTPD 0 R/W Headset/Aux or Handset PGA Soft−stepping Control 0 => Enable soft−stepping 1 => Disable soft−stepping D14 DASTPD 0 R/W DAC PGA Soft−stepping Control 0 => Enable soft−stepping 1 => Disable soft−stepping D13 ASSTPD 0 R/W Analog Sidetone PGA Soft−stepping Control 0 => Enable soft−stepping 1 => Disable soft−stepping Note: When soft−stepping is enabled gain is changed 0.5 dB per Fsref. D12 CISTPD 0 R/W Cell−phone PGA Soft−stepping Control 0 => Enable soft−stepping 1 => Disable soft−stepping Note: When soft−stepping is enabled gain is changed 0.5 dB per Fsref. D11 BISTPD 0 R/W Buzzer PGA Soft−stepping Control 0 => Enable soft−stepping 1 => Disable soft−stepping Note: When soft−stepping is enabled gain is changed 3 dB per Fsref. D10−D9 AGCHYS 00 R/W MIC AGC Hysteresis selection 00 => 1 dB 01 => 2 dB 10 => 4 dB 11 => No Hysteresis Note: Valid only when AGC is selected for Headset/Aux or Handset input D8−D7 MB_HED 00 R/W Micbias for Headset 00 => MICBIAS_HED = 3.3 V 01 => MICBIAS_HED = 2.5 V 10 => MICBIAS_HED = 2.0 V 11 => MICBIAS_HED = 2.0 V D6 MB_HND 0 R/W Micbias for Handset 0 => MICBIAS_HND = 2.5 V 1 => MICBIAS_HND = 2.0 V 0’s R Reserved (Write only 0000) 0 R Driver Short Circuit Protection Flag. 0 => No short circuit happened. 1 => Short circuit detected on headphone outputs. X R Reserved (Write only 0) D5−D2 D1 D0 58 SCPFL FUNCTION 
  www.ti.com SLAS418B − FEBRUARY 2004 − REVISED MAY 2005 REGISTER 1EH: Gain Control for Handset Input BIT NAME RESET VALUE READ/WRITE D15 ADMUT_HND 1 R/W Handset Input Mute 1 => Handset Input Mute 0 => Handset Input not muted Note: If AGC is enabled and handset Input is selected then ADMUT_HND+ADPGA_HND will reflect gain being applied by AGC. FUNCTION D14−D8 ADPGA_HND 1111111 R/W D7−D5 AGCTG_HND 000 R/W ADC Handset PGA Settings 0000000 => 0 dB 0000001 => 0.5 dB 0000010 => 1.0 dB .... 1110110 => 59.0 dB ............. 1111111 => 59.5 dB Note: If AGC is enabled and handset Input is selected then ADMUT_HND+ADPGA_HND will reflect gain being applied by AGC. If AGC is on, the decoding for read values is as follows 01110111 => +59.5 dB 01110110 => +59.0 dB ……… 00000000 => 0 dB ………. 11101000 => −12 dB AGC Target Gain for Handset Input. These three bits set the AGC’s targeted ADC output level. 000 => −5.5 dB 001 => −8.0 dB 010 => −10 dB 011 => −12 dB 100 => −14 dB 101 => −17 dB 110 => −20 dB 111 => −24 dB D4−D1 AGCTC_HND 0000 R/W AGC Time Constant for Handset Input. These four bits set the AGC attack and decay time constants. Time constants remain the same irrespective of any sampling frequency. Attack time Decay time (ms) (ms) 0000 8 100 0001 11 100 0010 16 100 0011 20 100 0100 8 200 0101 11 200 0110 16 200 0111 20 200 1000 8 400 1001 11 400 1010 16 400 1011 20 400 1100 8 500 1101 11 500 1110 16 500 1111 20 500 D0 AGCEN_HND 0 R/W AGC Enable for Handset Input 0 => AGC is off for Handset Input (ADC PGA is controlled by ADMUT_HND+ADPGA_HND) 1 => AGC is on for Handset Input (ADC PGA is controlled by AGC) 59 
  www.ti.com SLAS418B − FEBRUARY 2004 − REVISED MAY 2005 REGISTER 1FH: Gain Control for Cell Phone Input and Buzzer Input BIT NAME RESET VALUE READ/WRITE D15 MUT_CP 1 R/W Cell phone Input PGA Power−down 1 => Power−down cell-phone input PGA 0 => Power−up cell phone input PGA FUNCTION D14−D8 CPGA 1000101 R/W Cell−phone Input PGA Settings. 0000000 => −34.5 dB 0000001 => −34 dB 0000010 => −33.5 dB ... 1000101 => 0 dB 1000110 => 0.5 dB ... 1011100 => 11.5 dB 1011101 => 12 dB 1011110 => 12 dB 1011111 => 12 dB 11xxxxx => 12 dB Note: These bits are read−only when AGC is enabled for CP_IN (cell-phone input) and reflect the gain applied by the AGC. D7 CPGF 0 R Cell phone Input PGA Flag (Read Only) 0 => Gain applied ≠ PGA register setting 1 => Gain applied = PGA register setting. Note: This flag indicates when the soft−stepping for cell-phone input is completed. When AGC is enabled for Cell−phone input, this bit is read−only and acts as Saturation Flag. The read value of this bit indicates the following 0 => AGC is not saturated 1 => AGC is saturated (PGA has reached –34.5 dB or max PGA applicable). D6 MUT_BU 1 R/W Buzzer Input PGA Power−down 1 => Power−down buzzer input PGA 0 => Power−up buzzer input PGA D5−D2 BPGA 1111 R/W Buzzer Input PGA settings. 1111 => 0 dB 1110 => −3 dB 1101 => −6 dB 1100 => −9 dB 1011 => −12 dB 1010 => −15 dB 1001 => −18 dB 1000 => −21 dB 0111 => −24 dB 0110 => −27 dB 0101 => −30 dB 0100 => −33 dB 0011 => −36 dB 0010 => −39 dB 0001 => −42 dB 0000 => −45 dB D1 BUGF 0 R Buzzer PGA Flag (Read Only) 0 => Gain Applied ≠ PGA Register setting 1 => Gain Applied = PGA register setting. Note: This flag indicates when the soft−stepping for buzzer input is completed. 0 R Reserved (Write only 0) D0 60 
  www.ti.com SLAS418B − FEBRUARY 2004 − REVISED MAY 2005 REGISTER 20H: Audio Control 5 DIFFIN RESET VALUE 0 READ/ WRITE R/W D14−D13 DAC2SPK1 00 R/W DAC Channel Routing to SPK1 (Single-ended)/ SPK1−OUT32N (Differential) 00 => No routing from DAC to SPK1/ SPK1−OUT32N 01 => DAC left routed to SPK1/SPK1−OUT32N 10 => DAC right routed to SPK1/SPK1−OUT32N 11 => DAC (left + right)/2 routed to SPK1/SPK1−OUT32N D12 AST2SPK1 0 R/W Analog Sidetone Routing to SPK1 (Single-ended)/SPK1−OUT32N (Differential) 0 => No routing from analog sidetone to SPK1/SPK1−OUT32N 1 => Analog sidetone routed to SPK1/SPK1−OUT32N D11 BUZ2SPK1 0 R/W Buzzer PGA Routing to SPK1 (Single-ended)/ SPK1−OUT32N (Differential) 0 => No routing from buzzer PGA to SPK1/SPK1−OUT32N 1 => Buzzer PGA routed to SPK1/ SPK1−OUT32N D10 KCL2SPK1 0 R/W Keyclick Routing to SPK1 (Single-ended)/SPK1−OUT32N (Differential) 0 => No routing from keyclick to SPK1/SPK1−OUT32N 1 => Keyclick routed to SPK1/SPK1−OUT32N D9 CPI2SPK1 0 R/W Cell−phone Input Routing to SPK1 (Single-ended)/SPK1−OUT32N (Differential) 0 => No routing from cell-phone input to SPK1/SPK1−OUT32N 1 => Cell phone input routed to SPK1/SPK1−OUT32N D8−D7 DAC2SPK2 00 R/W DAC Channel Routing to SPK2 (Valid for Only Single-ended) 00 => No routing from DAC to SPK2 01 => DAC left routed to SPK2 10 => DAC right routed to SPK2 11 => DAC (left + right)/2 routed to SPK2 D6 AST2SPK2 0 R/W Analog Sidetone Routing to SPK2 (Valid for Only Single-ended) 0 => No routing from analog sidetone to SPK2 1 => Analog sidetone routed to SPK2 D5 BUZ2SPK2 0 R/W Buzzer PGA Routing to SPK2 (Valid for Only Single-ended) 0 => No routing from buzzer PGA to SPK2 1 => Buzzer PGA routed to SPK2 D4 KCL2SPK2 0 R/W Keyclick Routing to SPK2 (Valid for Only Single-ended) 0 => No routing from keyclick to SPK2 1 => Keyclick routed to SPK2 D3 CPI2SPK2 0 R/W Cell−phone Input Routing to SPK2 (Valid for Only Single-ended) 0 => No routing from cell-phone input to SPK2 1 => Cell−phone input routed to SPK2 D2 MUTSPK1 1 R/W Mute Control for SPK1 (Single-ended)/SPK1−OUT32N (Differential) 0 => SPK1/SPK1−OUT32N is not muted. 1 => SPK1/SPK1−OUT32N is muted. D1 MUTSPK2 1 R/W Mute Control for SPK2 (Valid for Only Single-ended) 0 => SPK2 is not muted. 1 => SPK2 is muted. D0 HDSCPTC 0 W BIT NAME D15 FUNCTION Single-ended or Differential Output Selection. 0 => Single-ended output (headset/lineout) selected for SPK1 and SPK2 drivers 1 => Differential output (handset) selected for SPK1 and OUT32N drivers Note: When bit D15=1, both SPK1 and OUT32N drivers should be power−up. Otherwise the AIC28 automatically power−down both SPK1 and OUT32N drivers. Headphone Short−circuit Protection Control 0 => Enable short−circuit protection 1 => Disable short−circuit protection 61 
  www.ti.com SLAS418B − FEBRUARY 2004 − REVISED MAY 2005 REGISTER 21H: Audio Control 6 BIT NAME RESET VALUE READ/ WRITE D15 SPL2LSK 0 R/W Routing Selected for SPK1 Goes to OUT8P−OUT8N (Loudspeaker) Also. 0 => None of the routing selected for SPK1 goes to OUT8P−OUT8N. 1 => Routing selected for SPK1 using D14−D9 of control register 20H/page 2 goes to OUT8P−OUT8N. Note: This programming is valid only if SPK1/OUT32N and SPK2 are powered down. D14 AST2LSK 0 R/W Analog Sidetone Routing to OUT8P−OUT8N (Loudspeaker) 0 => No routing from analog sidetone to OUT8P−OUT8N 1 => Analog sidetone routed to OUT8P−OUT8N D13 BUZ2LSK 0 R/W Buzzer PGA Routing to OUT8P−OUT8N (Loudspeaker) 0 => No routing from buzzer PGA to OUT8P−OUT8N 1 => Buzzer PGA routed to OUT8P−OUT8N D12 KCL2LSK 0 R/W Keyclick Routing to OUT8P−OUT8N (Loudspeaker) 0 => No routing from keyclick to OUT8P−OUT8N 1 => Keyclick routed to OUT8P−OUT8N D11 CPI2LSK 0 R/W Cell−phone Input Routing to OUT8P−OUT8N (Loudspeaker) 0 => No routing from cell-phone input to OUT8P−OUT8N 1 => Cell−phone input routed to OUT8P−OUT8N D10 MIC2CPO 0 R/W MICSEL (Programmed Using Control Register 04H/Page 2) Routed to Cell-phone Output. 0 => No routing from MICSEL to CP_OUT. 1 => MICSEL routed to CP_OUT. D9 SPL2CPO 0 R/W Routing Selected for SPK1 (Other Than Cell−phone Input) Goes to Cell-phone Output Also. 0 => None of the routing selected for SPK1 goes to cell-phone output. 1 => Routing selected for SPK1 using D14−D10 of control register 20H/page 2 goes to CP_OUT. Note: This programming is valid even if SPK1/OUT32N and SPK2 are powered down. D8 SPR2CPO 0 R/W Routing Selected for SPK2 Goes to Cell−phone Output Also (Valid for Only Single-ended). 0 => None of the routing selected for SPK2 goes to cell-phone output. 1 => Routing selected for SPK2 using D8−D3 of control register 20H/page2 goes to CP_OUT. Note: 1. This programming is valid even if SPK2 is power-down. 2. This programming is not valid when routing selected for SPK1 is routed to loudspeaker D7 MUTLSPK 1 R/W Mute Control for OUT8P−OUT8N Loudspeaker 0 => OUT8P−OUT8N is not muted. 1 => OUT8P−OUT8N is muted. D6 MUTSPK2 1 R/W Mute Control for Cell−phone Output 0 => CPOUT is not muted. 1 => CPOUT is muted. D5 LDSCPTC 1 R/W Loudspeaker Short−circuit Protection Control 0 => Enable short−circuit protection for loudspeaker 1 => Disable short−circuit protection for loudspeaker D4 VGNDSCPTC 0 R/W VGND Short−circuit Protection Control 0 => Enable short−circuit protection for VGND driver 1 => Disable short−circuit protection for VGND driver D3 CAPINTF 0 R/W Cap/Cap−less Interface Select for Headset. 0 => Select cap−less interface. 1 => Select cap interface. 0’s R D2−D0 62 FUNCTION Reserved (Write only 000) 
  www.ti.com SLAS418B − FEBRUARY 2004 − REVISED MAY 2005 REGISTER 22H: Audio Control 7 BIT NAME RESET VALUE READ/ WRITE D15 DETECT 0 R/W D14−D13 HESTYPE 00 R Type of Headset Detected. 00 => No headset detected. 01 => Stereo headset detected. 10 => Cellular headset detected 11 => Stereo+cellular headset detected Note: These two bits are valid only if the headset detection is enabled. D12 HDDETFL 0 R Headset Detection Flag. 0 => Headset is not detected 1 => Headset is detected. D11 BDETFL 0 R Button Press Detection Flag. 0 => Button press is not detected 1 => Button press is detected. D10−D9 HDDEBNPG 01 R/W 0 R BDEBNPG 00 R/W D8 D7−D6 D5 FUNCTION Headset Detection 0 => Disable headset detection 1 => Enable headset detection De−bouncing Programmability for Glitch Rejection During Headset Detection. 00 => 16 ms duration (with 2 ms clock resolution) 01 => 32 ms duration (with 4 ms clock resolution) 10 => 64 ms duration (with 8 ms clock resolution) 11 => 128 ms duration (with 16 ms clock resolution) Reserved (Write only 0) De−bouncing Programmability for Glitch Rejection During Button Press Detection. 00 => No glitch rejection. 01 => 8 ms duration (with 1 ms clock resolution) 10 => 16 ms duration (with 2 ms clock resolution) 11 => 32 ms duration (with 4 ms clock resolution) 0 R D4 DGPIO2 0 R/W Reserved (Write only 0) Enable GPIO2 for Headset Detection Interrupt 0 => Disable GPIO2 for headset detection interrupt 1 => Enable GPIO2 for headset detection interrupt Note: This programmability is valid only if D15 and D13 of control register 23H/page 2 are set to 0 D3 DGPIO1 0 R/W Enable GPIO1 for Headset Detection Interrupt 0 => Disable GPIO1 for Detection interrupt 1 => Enable GPIO1 for Detection interrupt Note: This programmability is valid only if D11 and D9 of control register 23H/page 2 are set to 0 D2 CLKGPIO2 0 R/W Enable GPIO2 for CLKOUT 0 => Disable GPIO2 for CLKOUT mode. 1 => Enable GPIO2 for CLKOUT mode. In CLKOUT mode the frequency of output signal is equal to the 256xDAC_FS if DAC_FS is faster than ADC_FS otherwise equal to the 256xADC_FS. Note: This programmability is valid only if PLL is enabled, D15 and D13 of register 23H/page 2 are set to 0 and GPIO2 is not enabled for detection interrupt. D1−D0 ADWSF 00 R/W ADWS Selection 0X => GPIO1 pin output is tri−stated. 10 => GPIO1 pin acts as button press detect interrupt. 11 => GPIO1 pin acts as ADC word−select (ADWS). Note: 1. This programmability is valid only if D11 and D9 of control register 23H/page 2 are set to 0. 2. These bits should be programmed ‘11’ only if different ADC and DAC sample rates are desired. In this mode WCLK acts as DAWS i.e. DAC sample rate and GPIO1 acts as ADWS i.e. ADC sample rate. 63 
  www.ti.com SLAS418B − FEBRUARY 2004 − REVISED MAY 2005 REGISTER 23H: GPIO Control BIT NAME RESET VALUE READ/ WRITE D15 GPO2EN 0 R/W GPIO2 Enable for General Purpose Output Port 0 => GPIO2 is not programmed as general purpose output port 1 => GPIO2 programmed as general purpose output port D14 GPO2SG 0 R/W GPIO2 Output Signal Programmability 0 => GPIO2 goes to low if GPIO2 enable for general purpose output port 1 => GPIO2 goes to high if GPIO2 enable for general purpose output port D13 GPI2EN 0 R/W GPIO2 Enable for General Purpose Input Port 0 => GPIO2 is not programmed as general purpose input port 1 => GPIO2 programmed as general purpose input port D12 GPI2SGF 0 R D11 GPO1EN 0 R/W GPIO1 Enable for General Purpose Output Port 0 => GPIO1 is not programmed as general purpose output port 1 => GPIO1 programmed as general purpose output port D10 GPO1SG 0 R/W GPIO1 Output Signal Programmability 0 => GPIO1 goes to low if GPIO1 enable for general purpose output port 1 => GPIO1 goes to high if GPIO1 enable for general purpose output port D9 GPI1EN 0 R/W GPIO1 Enable for General Purpose Input Port 0 => GPIO1 is not programmed as general purpose input port 1 => GPIO1 programmed as general purpose input port D8 GPI1SGF 0 R GPIO1 Input Signal Flag 0 => GPIO1 input is low. 1 => GPIO1 input is high. Note: Valid only if GPIO1 is enable for general purpose input port 0 R Reserved (Write only 00000000) D7−D0 FUNCTION GPIO2 Input Signal Flag 0 => GPIO2 input is low. 1 => GPIO2 input is high. Note: Valid only if GPIO2 is enable for general purpose input port REGISTER 24H: AGC for Cell-Phone Input Control BIT NAME D15 RESET VALUE READ/ WRITE FUNCTION 0 R Reserved (Write only 0) D14 AGCNF_CELL 0 R Noise Threshold Flag. The read values indicate the following 0 => Signal power greater than noise threshold 1 => Signal power is less than noise threshold Note: Valid only if AGC is selected for the Cell−phone input (CP_IN). D13−D11 AGCNL 000 R/W AGC Noise Threshold. These settings apply to both Headset/Aux/Handset and Cell−phone input. 000 => −30 dB 001 => −30 dB 010 => −40 dB 011 => −50 dB 100 => −60 dB 101 => −70 dB (not valid for Cell−phone AGC) 110 => −80 dB (not valid for Cell−phone AGC) 111 => −90 dB (not valid for Cell−phone AGC) D10−D9 AGCHYS_CELL 00 R/W AGC Hysteresis Selection for Cell−phone Input 00 => 1 dB 01 => 2 dB 10 => 4 dB 11 => No Hysteresis D8 CLPST_CELL 0 R/W AGC Clip Stepping Disable for Cell−phone Input 0 => Disable clip stepping for cell-phone input 1 => Enable clip stepping for cell-phone input 64 
  www.ti.com SLAS418B − FEBRUARY 2004 − REVISED MAY 2005 BIT NAME RESET VALUE READ/ WRITE D7−D5 AGCTG_CELL 000 R/W AGC Target Gain for Cell−phone Input. These three bits set the AGC’s targeted ADC output level. 000 => −5.5 dB 001 => −8.0 dB 010 => −10 dB 011 => −12 dB 100 => −14 dB 101 => −17 dB 110 => −20 dB 111 => −24 dB D4−D1 AGCTC_CELL 0000 R/W AGC Time Constant for Cell Input. These four bits set the AGC attack and decay time constants. Time constants remain the same irrespective of any sampling frequency Attack time Decay time (ms) (ms) 0000 8 10 0001 11 100 0010 16 100 0011 20 100 0100 8 200 0101 11 200 0110 16 200 0111 20 200 1000 8 400 1001 11 400 1010 16 400 1011 20 400 1100 8 500 1101 11 500 1110 16 500 1111 20 500 D0 AGCEN_CELL 0 R/W AGC Enable for Cell−phone Input 0 => AGC is off for Cell−phone input 1 => AGC is on for Cell−phone input (Cell PGA is controlled by AGC FUNCTION REGISTER 25H: Driver Power-Down Status Note: All values reflected in control register 25H/page2 are valid only if short circuit is not detected (bit D1 of control register 1DH/page2 is set to 0) BIT NAME RESET VALUE READ/ WRITE D15 SPK1FL 1 R SPK1 Driver Power-down Status 0 => SPK1 driver not powered down. 1 => SPK1 driver powered down. D14 SPK2FL 1 R SPK2 Driver Power-down Status 0 => SPK2 driver not powered down. 1 => SPK2 driver powered down. D13 HNDFL 1 R OUT32N (Handset) Driver Power-down Status 0 => OUT32N driver not powered down. 1 => OUT32N driver powered down. D12 VGNDFL 1 R VGND Driver Power-down Status 0 => VGND driver not powered down. 1 => VGND driver powered down. D11 LSPKFL 1 R Loudspeaker Driver Power-down Status 0 => Loudspeaker driver not powered down. 1 => Loudspeaker driver powered down. D10 CELLFL 1 R Cell−phone Output (CP_OUT) Driver Power-down Status 0 => Cell-phone output driver not powered down. 1 => Cell-phone output driver powered down. FUNCTION 65 
  www.ti.com SLAS418B − FEBRUARY 2004 − REVISED MAY 2005 BIT NAME RESET VALUE D9−D6 READ/ WRITE FUNCTION 0000 R D5 PSEQ 0 R/W Disable Drivers (SPK1/SPK2/OUT32N/VGND) Pop Sequencing 0 => Enable drivers pop sequencing 1 => Disable drivers pop sequencing D4 PSTIME 0 R/W Drivers (SPK1/SPK2) Pop Sequencing Duration in Cap Mode 0 => 802 ms. 1 => 4006 ms. 0000 R D3−D0 Reserved (Write only 0000) Reserved (Write only 0000) REGISTER 26H: Mic AGC Control BIT NAME RESET VALUE READ/ WRITE D15−D9 MMPGA 1111111 R/W Max PGA Value Applicable for Headset/Aux or Handset AGC 0000000 => 0 dB 0000001 => 0.5 dB 0000010 => 1.0 dB .... 1110110 => 59.0 dB ............ 1111111 => 59.5 dB D8−D6 MDEBNS 000 R/W Debounce Time for Transition from Normal Mode to Silence Mode (Input Level is Below Noise Threshold Programmed by AGCNL). This is Valid for Headset/Aux or Handset AGC. 000 => 0 ms 001 => 0.5 ms 010 => 1.0 ms 011 => 2.0 ms 100 => 4.0 ms 101 => 8.0 ms 110 => 16.0 ms 111 => 32.0 ms D5−D3 MDEBSN 000 R/W De−bounce Time for Transition from Silence Mode to Normal Mode. This is Valid for Headset/Aux or Handset AGC. 000 => 0 ms 001 => 0.5 ms 010 => 1.0 ms 011 => 2.0 ms 100 => 4.0 ms 101 => 8.0 ms 110 => 16.0 ms 111 => 32.0 ms 000 R D2−D0 66 FUNCTION Reserved (Write only 000) 
  www.ti.com SLAS418B − FEBRUARY 2004 − REVISED MAY 2005 REGISTER 27H: Cell-Phone AGC Control BIT NAME RESET VALUE READ/ WRITE D15−D9 CMPGA 1111111 R/W D8−D6 CDEBNS 000 R De−bounce Time for Transition from Normal Mode to Silence Mode (Input Level is Below Noise Threshold Programmed by AGCNL). This is Valid for Cell−phone AGC. 000 => 0 ms 001 => 0.5 ms 010 => 1.0 ms 011 => 2.0 ms 100 => 4.0 ms 101 => 8.0 ms 110 => 16.0 ms 111 => 32.0 ms D5−D3 CDEBSN 000 R De−bounce Time for Transition from Silence Mode to Normal Mode. This is Valid for Cell−phone AGC. 000 => 0 ms 001 => 0.5 ms 010 => 1.0 ms 011 => 2.0 ms 100 => 4.0 ms 101 => 8.0 ms 110 => 16.0 ms 111 => 32.0 ms 000 R Reserved (Write only 000) D2−D0 FUNCTION Max. Cell‘−phone input PGA value applicable for Cell‘−phone AGC 0000000 => −34.5 dB 0000001 => −34 dB 0000010 => −33.5 dB ... 1000100 => −0.5 dB 1000101 => invalid 1000110 => invalid ... 1011100 => Invalid 1011101 => 12 dB 1011110 => 12 dB 1011111 => 12 dB 11xxxxx => 12 dB 67 
  www.ti.com SLAS418B − FEBRUARY 2004 − REVISED MAY 2005 AIC28 Buffer Data Registers (Page 3) The buffer data registers of the AIC28 hold data results from the SAR ADC conversions in buffer mode. Upon reset, bit D15 is set to 0, bit D14 is set to 1 and the remaining bits are don’t−care. These registers are read only. If buffer mode is enabled, then the results of all ADC conversions are placed in the buffer data register. The data format of the result word (R) of these registers is right-justified which is as follows: D15 MSB D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LSB FUF EMF X ID R11 MSB R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 LSB BIT NAME RESET VALUE READ/ WRITE D15 FUF 0 R Buffer Full Flag This flag indicates that all the 64 locations of the buffer are having unread data. D14 EMF 1 R Buffer Empty Flag This flag indicates that there is no unread data available in FIFO. This is generated while reading the last converted data. X R Reserved X R Data Identification 0 => BAT or AUX2 data in R11−R0 1 => AUX1 or TEMP data in R11−R0 D13 D12 ID FUNCTION Order for Writing Data in Buffer When Multiple Inputs are Selected For Auto Scan Conversion: AUX1 (if selected), AUX2 (if selected), TEMP (if selected) For Port Scan Conversion: BAT, AUX1, AUX2 D11−D0 R11−R0 X’s R Converted Data LAYOUT The following layout suggestions should provide optimum performance from the AIC28. However, many portable applications have conflicting requirements concerning power, cost, size, and weight. In general, most portable devices have fairly clean power and grounds because most of the internal components are very low power. This situation would mean less bypassing for the converter’s power and less concern regarding grounding. Still, each situation is unique and the following suggestions should be reviewed carefully. For optimum performance, care should be taken with the physical layout of the AIC28 circuitry. The basic SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground connections, and digital inputs that occur just prior to latching the output of the analog comparator. Therefore, during any single conversion for an n-bit SAR converter, there are n windows in which large external transient voltages can easily affect the conversion result. Such glitches might originate from switching power supplies, nearby digital logic, and high power devices. The degree of error in the digital output depends on the reference voltage, layout, and the exact timing of the external event. The error can change if the external event changes in time with respect to the timing of the critical n windows. With this in mind, power to the AIC28 should be clean and well bypassed. A 0.1 µF ceramic bypass capacitor should be placed as close to the device as possible. A 1 µF to 10 µF capacitor may also be needed if the impedance of the connection between the AIC28 supply pins and system power supply is high. A bypass capacitor on the VREF pin is generally not needed because the reference is buffered by an internal op amp, although it can be useful to reduce reference noise level. If an external reference voltage originates from an op amp, make sure that it can drive any bypass capacitor that is used without oscillation. The AIC28 architecture offers no inherent rejection of noise or voltage variation in regards to using an external reference input. This is of particular concern when the reference input is tied to the power supply. Any noise and ripple from the supply appears directly in the digital results. While high frequency noise can be filtered out, voltage variation due to line frequency (50 Hz or 60 Hz) can be difficult to remove. The ground pins should be connected to a clean ground point. In many cases, this is the analog ground. Avoid connections, which are too near the grounding point of a microcontroller or digital signal processor. If needed, run a ground trace directly from the converter to the power supply entry or battery connection point. The ideal layout includes an analog ground plane dedicated to the converter and associated analog circuitry. 68 
  www.ti.com SLAS418B − FEBRUARY 2004 − REVISED MAY 2005 CONVERSION TIME CALCULATIONS FOR THE AIC28 Auxiliary Measurement Operation The time needed to make temperature, auxiliary, or battery measurements is given by: t+ NJ ƪǒ N AVG N BITS ƫ Nj Ǔ 8 MHz ) n ) n ) 1 1 2 ƒ conv )1 t OSC ) 15 t OSC ) n3 t OSC where: n1 = 6 ; if ƒconv = 8 MHz 7 ; if ƒconv ≠ 8 MHz n2 = 24 ; if measurement is for TEMP1 case 12 ; if measurement is for other than TEMP1 case 400 ns; if measurement is for the external/internal resistance using AUX1/AUX2 n3 = 0 ; if external reference mode is selected 3 ; if tREF = 0 µs or reference is programmed for power up all the time. 1 + tREF /125 ns; if tREF ≠ 0 µs and reference needs to power down between conversions. tREF is the reference power up delay time. REG−00 of PAGE−01 Is Updated for BAT1 Scan Mode Waiting for Host to Write into REG−00 of PAGE−01 Reading BAT1−Data Register SS DEACTIVATED Wait for Reference Power-Up Delay in Case of Internal Ref Mode if Applicable Sample,Conversion & Waiting for Host to Averaging for Write into REG−00 BAT1 Input of PAGE−01 DAV (PAGE01H,REG01H [D15−D14 = 01]) The time needed for continuous autoscan mode is given by: t+N INP ǒNJ N ) n2 AVG t ƪǒ N OSC BITS )t Ǔ )1 DEL ƫ Nj 8 MHz ) n ) 12 ) 1 1 ƒ conv ) n3 ) t OSC ) n4 t t OSC )8 t OSC Ǔ OSC where: NINP = 1; if autoscan is selected for only one input AUX1, AUX2, TEMP1 or TEMP2 = 2; if autoscan is selected for two inputs AUX1−AUX2, AUX1−TEMP1, AUX1−TEMP2 etc = 3; if autoscan is selected for three inputs AUX1−AUX2−TEMP1 or AUX1−AUX2−TEMP2 n1 = 6 ; if fconv = 8 MHz 7 ; if fconv p 8 MHz n2 = 12 ; if one of the input selected is TEMP1 0 ; if measurement is for other than TEMP1 n3 = 0 ; if external reference mode is selected or tDEL = 0. 3 ; if tREF = 0 ms or reference is programmed for power up all the times. 1 + tREF/125 ns ; if tREF p 0us and reference needs to power down between conversions. tREF is the reference power up delay time. 69 
  www.ti.com SLAS418B − FEBRUARY 2004 − REVISED MAY 2005 n4 = 0 ; if tDEL = 0. = 7 ; if tDEL p 0 tDEL = Programmable delay in between conversion = 0 ; if programmable delay mode is disabled (1) The above equation is valid only from second conversion onwards. (2) t DEL delay is generated by using internal oscillator clock whose typical frequency is 1 MHz in internal clock mode, or MCLK/CLKDIV (as programmed in control register 14H/page 1) in external clock mode. REG−00 of PAGE−01 Is Updated for Continous AUX SCAN Mode Reading AUX−Data Register SS DEACTIVATED Waiting for Host to Write into REG−00 of PAGE−01 Wait for Reference Power-Up Delay in Case of Internal Ref Mode if Applicable Reading AUX−Data Register Sample,Conversion & Sample,Conversion & Averaging for Averaging for AUX input AUX input Sample,Conversion & Averaging for AUX input DAV (PAGE01H,REG01H [D15−D14 = 01]) Port Scan Operation The time needed to complete one set of port scan conversions is given by: t coordinate +3 NJ ƪǒ N AVG N BITS Ǔ )1 ƫ Nj 8 MHz ) n ) 12 ) 1 1 ƒ conv t OSC ) 31 t OSC ) n2 where: n1 = 6 ; if ƒconv = 8 MHz 7 ; if ƒconv ≠ 8 MHz n2 = 0 ; if external reference mode is selected 3 ; if tREF = 0 µs or reference is programmed for power up all the time. 1 + tREF /125 ns; if tREF ≠ 0 µs and reference needs to power down between conversions. tREF is the reference power up delay time. REG−00 of PAGE−01 is updated for PORT SCAN Mode Waiting for Host to Write into REG−00 of PAGE−01 DAV (PAGE01H,REG01H [D15−D14 = 01]) 70 Reading BAT− Data Register SS DEACTIVATED Wait for Reference Power-Up Delay in Case of Internal Ref Mode if Applicable Sample,Conversion & Averaging for BAT & AUX1 & AUX2 input Reading AUX1− Data Register Reading AUX2− Data Register Waiting for Host to Write into REG−00 of PAGE−01 t OSC 
  www.ti.com SLAS418B − FEBRUARY 2004 − REVISED MAY 2005 ADC CHANNEL DIGITAL FILTER FREQUENCY RESPONSES Figure 35. Pass-Band Frequency Response of ADC Digital Filter Figure 36. Frequency Response of ADC High-Pass Filter (Fcutoff = 0.0045 Fs) 71 
  www.ti.com SLAS418B − FEBRUARY 2004 − REVISED MAY 2005 Figure 37. Frequency Response of ADC High-Pass Filter (Fcutoff = 0.0125 Fs) Figure 38. Frequency Response of ADC High-Pass Filter (Fcutoff = 0.025 Fs) 72 
  www.ti.com SLAS418B − FEBRUARY 2004 − REVISED MAY 2005 DAC CHANNEL DIGITAL FILTER FREQUENCY RESPONSES Figure 39. DAC Channel Digital Filter Frequency Response Figure 40. DAC Channel Digital Filter Pass-Band Frequency Response 73 
  www.ti.com SLAS418B − FEBRUARY 2004 − REVISED MAY 2005 Figure 41. Default Digital Audio Effects Filter Frequency Response at 48 Ksps Figure 42. De-Emphasis Filter Response at 32 Ksps 74 
  www.ti.com SLAS418B − FEBRUARY 2004 − REVISED MAY 2005 Figure 43. De-Emphasis Error at 32 Ksps Figure 44. De-Emphasis Filter Frequency Response at 44.1 Ksps 75 
  www.ti.com SLAS418B − FEBRUARY 2004 − REVISED MAY 2005 Figure 45. De-Emphasis Error at 44.1 Ksps Figure 46. De-Emphasis Frequency Response at 48 Ksps 76 
  www.ti.com SLAS418B − FEBRUARY 2004 − REVISED MAY 2005 Figure 47. De-Emphasis Error at 48 Ksps 77 
  www.ti.com SLAS418B − FEBRUARY 2004 − REVISED MAY 2005 PLL PROGRAMMING The on-chip PLL in the AIC28 can be used to generate sampling clocks from a wide range of MCLK’s available in a system. The PLL works by generating oversampled clocks with respect to Fsref (44.1 kHz or 48 kHz). Frequency division generates all other internal clocks. Table 6 and Table 7 gives a sample programming for PLL registers for some standard MCLK’s when PLL is required. Whenever the MCLK is of the form of N × 128 × Fsref (N=2,3,...), the PLL is not required. Table 6. Fsref = 44.1 kHz MCLK (MHz) P J D ACHIEVED FSREF % ERROR 2.8224 1 32 0 44100.00 0.0000 5.6448 1 16 0 44100.00 0.0000 12 1 7 5264 44100.00 0.0000 13 1 6 9474 44099.71 0.0007 0.0000 16 1 5 6448 44100.00 19.2 1 4 7040 44100.00 0.0000 19.68 1 4 5893 44100.30 −0.0007 48 4 7 5264 44100.00 0.0000 Table 7. Fsref = 48 kHz 78 MCLK (MHz) P J D ACHIEVED FSREF % ERROR 2.048 1 48 0 48000.00 0.0000 3.072 1 32 0 48000.00 0.0000 4.096 1 24 0 48000.00 0.0000 6.144 1 16 0 48000.00 0.0000 8.192 1 12 0 48000.00 0.0000 12 1 8 1920 48000.00 0.0000 13 1 7 5618 47999.71 0.0006 16 1 6 1440 48000.00 0.0000 19.2 1 5 1200 48000.00 0.0000 19.68 1 4 9951 47999.79 0.0004 48 4 8 1920 48000.00 0.0000 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TLV320AIC28IRGZ ACTIVE VQFN RGZ 48 52 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 AIC28I TLV320AIC28IRGZR ACTIVE VQFN RGZ 48 2500 RoHS & Green Call TI | NIPDAU Level-2-260C-1 YEAR -40 to 85 AIC28I (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of