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TLV320AIC3206
SLAS649C – DECEMBER 2010 – REVISED NOVEMBER 2014
TLV320AIC3206 Ultra Low-Power Stereo Audio Codec
1 Features
2 Applications
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1
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Stereo Audio DAC with 100-dB SNR
5.8-mW Stereo 48-ksps DAC-to-Ground-Centered
Headphone Playback
Stereo Audio ADC with 93-dB SNR
5.2-mW Stereo 48-ksps ADC Record
PowerTune™
Extensive Signal Processing Options
Six Single-Ended or 3 Fully-Differential Analog
Inputs
Stereo Analog and Digital Microphone Inputs
Ground-Centered Stereo Headphone Outputs
Very Low-Noise PGA
Low Power Analog Bypass Mode
Programmable Microphone Bias
Programmable PLL
5-mm x 5-mm 40-pin QFN or 3.5-mm x 3.3-mm
42-ball WCSP (DSBGA) Package
Portable Navigation Devices (PND)
Portable Media Player (PMP)
Mobile Handsets
Communication
Portable Computing
3 Description
The TLV320AIC3206 (sometimes referred to as the
AIC3206) is a flexible, low-power, low-voltage stereo
audio codec with programmable inputs and outputs,
PowerTune capabilities, fixed predefined and
parameterizable signal processing blocks, integrated
PLL and flexible digital interfaces.
Device Information(1)
PART NUMBER
TLV320AIC3206
PACKAGE
BODY SIZE (NOM)
WQFN (40)
5.00 mm x 5.00 mm
DSBGA (42)
3.49 mm x 3.29 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
4 Simplified Block Diagram
IN1_L
IN2_L
IN3_L
0…+47.5 dB
+
Left
ADC
tpl
+
*
AGC
DRC
ADC
Signal
Proc.
DAC
Signal
Proc.
Vol . Ctrl
*
-6...+14dB
+
Left
DAC
HPL
1dB steps
Gain Adj.
0.5 dB
steps
-6...+29dB
-30...0 dB
LOL
+
1dB steps
Data Interface
-6...+29dB
-30...0 dB
LOR
+
1dB steps
0…
+47.5 dB
+
Gain Adj.
Right
ADC
IN3_R
+
tpr
*
0.5 dB steps
IN2_R
ADC
Signal
Proc.
DAC
Signal
Proc.
AGC
DRC
*
-6...+14dB
Right
DAC
HPR
+
1dB steps
Vol . Ctrl
IN1_R
GND_Sense
SPI_Select
SPI / I2C
Control Block
Reset
MicBias
MicDet
Ref
PLL
Dig
Mic
Inter
rupt
Sec.
I2S I/F
Primary
I2S Interface
VNEG
Charge
Pump
Mic
Bias
Supplies
Fly_N
Fly_P
Pin Muxing / Clock Routing
Ref
DVDD_CP
DVSS_CP
BCLK
WCLK
DIN
DOUT
GPIO
MCLK
SCLK
MISO
SDA/MOSI
SCL/SS
IOVss (GND)
DVss (GND)
Avss (GND)
GND
IOVdd
AVdd
DVdd
Vsys
DRVdd_HP
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLV320AIC3206
SLAS649C – DECEMBER 2010 – REVISED NOVEMBER 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Block Diagram .....................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
1
2
3
4
6
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
8.10
8.11
Absolute Maximum Ratings ...................................... 6
Handling Ratings....................................................... 7
Recommended Operating Conditions....................... 7
Thermal Information .................................................. 8
Electrical Characteristics, ADC ................................. 8
Electrical Characteristics, Bypass Outputs ............. 10
Electrical Characteristics, Microphone Interface..... 11
Electrical Characteristics, Audio DAC Outputs ....... 12
Electrical Characteristics, Misc. .............................. 13
Electrical Characteristics, Logic Levels................. 14
I2S/LJF/RJF Timing in Master Mode (see
Figure 1)................................................................... 14
8.12 I2S/LJF/RJF Timing in Slave Mode (see
Figure 2)................................................................... 15
8.13 DSP Timing in Master Mode (see Figure 3) ......... 16
8.14 DSP Timing in Slave Mode (see Figure 4) ........... 17
8.15 Digital Microphone PDM Timing (see Figure 5).... 18
8.16 I2C Interface Timing .............................................. 19
8.17 SPI Interface Timing ............................................. 20
8.18 Typical Characteristics .......................................... 21
9 Parameter Measurement Information ................ 23
10 Detailed Description ........................................... 23
10.1
10.2
10.3
10.4
10.5
Overview ...............................................................
Functional Block Diagram .....................................
Feature Description...............................................
Device Functional Modes......................................
Register Map.........................................................
23
24
24
31
32
11 Application and Implementation........................ 36
11.1 Application Information.......................................... 36
11.2 Typical Application ................................................ 36
12 Power Supply Recommendations ..................... 40
13 Layout................................................................... 40
13.1 Layout Guidelines ................................................. 40
13.2 Layout Example .................................................... 41
14 Device and Documentation Support ................. 42
14.1
14.2
14.3
14.4
Documentation Support ........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
42
42
42
42
15 Mechanical, Packaging, and Orderable
Information ........................................................... 42
5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (October 2012) to Revision C
Page
•
Added Pin Configuration and Functions section, Handling Rating table, Feature Description section, Device
Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information
section ................................................................................................................................................................................... 1
•
Added Note 1 to the Pin Functions table................................................................................................................................ 4
•
Added "Audio input mux ac signal swing" to the Recommended Operating Conditions table .............................................. 7
•
Added the Digital Microphone PDM Timing (see Figure 5) section ..................................................................................... 18
Changes from Revision A (December 2010) to Revision B
Page
•
Added WCSP package (YZF)................................................................................................................................................. 1
•
Corrected typos and spelling errors throughout data sheet ................................................................................................... 1
•
Updated block diagram to include Vsys pin ........................................................................................................................... 1
•
Updated diagram to include Vsys pin................................................................................................................................... 36
•
Updated power supply section to include Vsys .................................................................................................................... 40
2
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SLAS649C – DECEMBER 2010 – REVISED NOVEMBER 2014
6 Device Comparison Table
PART NUMBER
DESCRIPTION
TLV320AIC3254
Low power stereo audio codec with miniDSP.
TLV320AIC3204
Same as TLV320AIC3204 but without miniDSP.
TLV320AIC3256
Similar to TLV320AIC3254 but with ground centered headphone output.
TLV320AIC3206
Same as TLV320AIC3256 but without miniDSP.
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TLV320AIC3206
SLAS649C – DECEMBER 2010 – REVISED NOVEMBER 2014
www.ti.com
7 Pin Configuration and Functions
IOVdd
WCSP
(YZF) Package
Bottom View
DOUT/MFP2
WCLK
DIN/MFP1
MCLK
BCLK
DVss
Reset
GPIO/MFP5
DVss (1)
QFN
(RSB) Package
Bottom View
DVdd (40)
IOVss
DVdd_CP
FLY_P
SCLK/MFP3
DVss_CP
SDA/MOSI
SCL/SSZ
FLY_N
MISO/MFP4
VNEG
SPI_SELECT
MICDET
IN1_L
HPR
IN1_R
DRVDD_HP
IN2_L
HPL
IN2_R
AVss
MICBIAS
REF
IN3_R
IN3_L
LOR
LOL
AVdd
GND_Sense
Vsys
Pin Functions
PIN
NAME
WCSP
(YZF)
QFN (RSB)
BALL NO.
NO.
TYPE (1)
DESCRIPTION
DVss
1
B2
GND
Digital ground. Device substrate.
DVss
2
A1
GND
Digital ground
RESET
3
C5
DI
GPIO
4
B3
DI/O
Hardware reset
Primary function:
General purpose digital IO
MFP5
Secondary function:
CLKOUT output
INT1 output
INT2 output
Audio serial data bus ADC word clock output
Audio serial data bus (secondary) bit clock output
Audio serial data bus (secondary) word clock output
Digital microphone clock output
MCLK
5
A2
DI
BCLK
6
B4
DI/O
Master clock input
Audio serial data bus (primary) bit clock
WCLK
7
A3
DI/O
Audio serial data bus (primary) word clock
DIN
8
A5
DI
Primary function:
Audio serial data bus data input
MFP1
Secondary function:
Digital Microphone Input
General Purpose Clock Input
General Purpose Input
DOUT
(1)
4
9
A4
DO
Primary function:
DI (Digital Input), DO (Digital Output), DIO (Digital Input/Output), AI (Analog Input), AO (Analog Output), AIO (Analog Input/Output)
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Pin Functions (continued)
PIN
NAME
WCSP
(YZF)
QFN (RSB)
BALL NO.
NO.
TYPE (1)
DESCRIPTION
Audio serial data bus data output
MFP2
Secondary function:
General purpose output
Clock output
INT1 output
INT2 output
Audio serial data bus (secondary) bit clock output
Audio serial data bus (secondary) word clock output
IOVdd
10
A6
PWR
Supply for IO buffers. 1.1V to 3.6V
IOVss
11
B5
GND
Ground for IO buffers.
SCLK
12
C4
DI
Primary function: (SPI_Select = 1)
SPI serial clock
MFP3
Secondary function:: (SPI_Select = 0)
Digital microphone input
Audio serial data bus (secondary) bit clock input
Audio serial data bus (secondary) DAC/common word clock input
Audio serial data bus (secondary) ADC word clock input
Audio serial data bus (secondary) data input
General purpose input
SCL
SS
13
B6
DI
I2C interface serial clock (SPI_Select = 0)
SPI interface mode chip-select signal (SPI_Select = 1)
SDA
MOSI
14
C3
DI/O
I2C interface mode serial data input (SPI_Select = 0)
SPI interface mode serial data input (SPI_Select = 1)
MISO
15
D4
DO
Primary function: (SPI_Select = 1)
Serial data output
MFP4
Secondary function: (SPI_Select = 0)
General purpose output
CLKOUT output
INT1 output
INT2 output
Audio serial data bus (primary) ADC word clock output
Digital microphone clock output
Audio serial data bus (secondary) data output
Audio serial data bus (secondary) bit clock output
Audio serial data bus (secondary) word clock output
SPI_SELECT
16
C6
DI
Control mode select pin ( 1 = SPI, 0 = I2C )
IN1_L
17
D6
AI
Multifunction analog input,
Single-ended configuration: MIC 1 or Line 1 left
Differential configuration: MIC or Line right, negative
IN1_R
18
E6
AI
Multifunction analog input,
Single-ended configuration: MIC 1 or Line 1 right
Differential configuration: MIC or Line right, positive
IN2_L
19
F6
AI
Multifunction analog input,
Single-ended configuration: MIC 2 or Line 2 right
Differential configuration: MIC or Line left, positive
IN2_R
20
G6
AI
Multifunction analog input,
Single-ended configuration: MIC 2 or Line 2 right
Differential configuration: MIC or Line left, negative
AVss
21
E4, E5
GND
REF
22
G5
AO
Reference voltage output for filtering
MICBIAS
23
G4
AO
Microphone bias voltage output
Analog Ground
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Pin Functions (continued)
PIN
NAME
WCSP
(YZF)
QFN (RSB)
BALL NO.
NO.
IN3_L
24
TYPE (1)
F5
DESCRIPTION
AI
Multifunction analog input,
Single-ended configuration: MIC3 or Line 3 left,
Differential configuration: MIC or Line left, positive,
Differential configuration: MIC or Line right, negative
IN3_R
25
F4
AI
Multifunction analog input,
Single-ended configuration: MIC3 or Line 3 right,
Differential configuration: MIC or Line left, negative,
Differential configuration: MIC or Line right, positive
LOL
26
G3
AO
Left line output
LOR
27
F3
AO
Right line output
GND_SENSE
28
E3
AI
External ground reference for headphone interface –0.5V to 0.5V
AVdd
29
G2
PWR
Analog voltage supply 1.5V–1.95V
Vsys
30
G1
PWR
Power supply 1.5V–5.5V, Vsys must always be greater than or equal to AVdd and
DVdd (Vsys ≥ AVdd, DVdd)
HPL
31
F1
AO
DRVdd_HP
32
F2
PWR
HPR
33
E1
AO
Right headphone output
MICDET
34
E2
AI
Microphone detection
VNEG
35
D1
PWR
Negative supply for headphones. –1.8V to 0V
Input when charge pump is disabled,
Filtering output when charge pump is enabled
FLY_N
36
D2
PWR
Negative terminal for charge-pump flying capacitor
DVss_CP
37
D3
GND
Charge pump ground
FLY_P
38
C2
PWR
Positive terminal for charge pump flying capacitor
DVdd_CP
39
C1
PWR
Charge Pump supply; recommended to connect to DVdd
40
B1
PWR
Digital voltage supply 1.26V – 1.95V
Thermal
Pad
N/A
N/A
DVdd
Thermal Pad
Left headphone output
Power supply for headphone output stage
Ground-centered circuit configuration, 1.5V to 1.95V
Unipolar circuit configuration, 1.5V to 3.6V
Connect to PCB ground plane. Not internally connected.
8 Specifications
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
UNIT
AVdd to AVss
–0.3
2.2
V
DVdd to DVss
–0.3
2.2
V
Vsys to DVss
–0.3
5.5
V
IOVdd to IOVss
–0.3
3.9
V
Digital Input voltage
IOVss
IOVdd + 0.3
V
Analog input voltage
AVss
AVdd + 0.3
V
–40
85
°C
105
°C
Operating temperature range
Junction temperature (TJ Max)
(1)
6
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
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8.2 Handling Ratings
Tstg
Storage temperature range
V(ESD)
(1)
(2)
Electrostatic discharge
MIN
MAX
UNIT
–55
125
°C
–2
2
kV
–750
750
V
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins (1)
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (2)
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
8.3 Recommended Operating Conditions
(1)
MIN
NOM
MAX
1.5
1.8
1.95
UNIT
AVDD
Referenced to AVss
IOVDD
Referenced to IOVss (1)
1.1
Referenced to DVss (1)
1.5
1.8
5.5
Referenced to DVss (1)
1.26
1.8
1.95
Referenced to DVss (1)
1.26
1.8
1.95
Ground-centered config
1.5
1.8
1.95
Unipolar config
1.5
3.6
Clock divider uses fractional divide
(D > 0), P = 1, DVdd ≥ 1.65V (See table in
SLAA463, Maximum TLV320AIC3206 Clock
Frequencies)
10
20
MHz
Clock divider uses integer divide
(D = 0), P = 1, DVdd ≥ 1.65V (See table in
SLAA463, Maximum TLV320AIC3206 Clock
Frequencies)
0.512
20
MHz
50
MHz
Vsys
Power Supply Voltage Range
DVdd (2)
DVDD_CP
Power Supply Voltage Range
Referenced
to AVss (1)
DRVDD_HP
PLL Input Frequency
MCLK
Master Clock Frequency
SCL
SCL Clock Frequency
Audio input max ac signal swing
(IN1_L, IN1_R, IN2_L, IN2_R,
IN3_L, IN3_R)
LOL, LOR
HPL, HPR
Headphone output load
resistance
CLout
Digital output load capacitance
TOPR
Operating Temperature Range
(1)
(2)
(3)
MCLK; Master Clock Frequency; DVdd ≥ 1.65V
MCLK; Master Clock Frequency; DVdd ≥ 1.26V
V
V
25
400
kHz
CM = 0.75 V
0
0.530
0.75 or
AVDD - Vpeak
0.75 (3)
CM = 0.9 V
0
0.707
0.9 or
AVDD - Vpeak
0.9 (3)
0.6
10
kΩ
Single-ended configuration
14.4
16
Ω
Differential configuration
24.4
32
Ω
Stereo line output load
resistance
Stereo headphone output load
resistance
3.6
10
–40
pF
85
°C
All grounds on board are tied together; they must not differ in voltage by more than 0.2V max, for any combination of ground signals.
At DVdd values lower than 1.65V, the PLL does not function. Please see table in SLAA463, Maximum TLV320AIC3206 Clock
Frequencies for details on maximum clock frequencies.
Whichever is smaller
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8.4 Thermal Information
TLV320AIC3206
THERMAL METRIC (1)
RSB (QFN)
YZF (DSGBA)
48 PINS
42 PINS
RθJA
Junction-to-ambient thermal resistance
32.3
49.7
RθJCtop
Junction-to-case (top) thermal resistance
22.5
0.1
RθJB
Junction-to-board thermal resistance
6.1
7.7
ψJT
Junction-to-top characterization parameter
0.3
0.1
ψJB
Junction-to-board characterization parameter
6
7.7
RθJCbot
Junction-to-case (bottom) thermal resistance
1.7
–
(1)
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
8.5 Electrical Characteristics, ADC
At 25°C, Vsys, AVdd, DVdd, IOVdd, DVdd_CP, DRVdd_HP = 1.8V, fs (Audio) = 48kHz, Cref = 1µF on REF PIN, PLL and
Charge pump disabled unless otherwise noted.
PARAMETER
AUDIO ADC
(1) (2)
TEST CONDITIONS
MIN
Input signal level (for 0dB output) Single-ended, CM = 0.9V
MAX
UNIT
0.5
VRMS
1kHz sine wave input
Single-ended Configuration
IN1_R to Right ADC and IN1_L to Left ADC,
RIN = 20kΩ, fS = 48kHz,
AOSR = 128, MCLK = 256 * fS,
PLL Disabled; AGC = OFF,
Channel Gain = 0dB,
Processing Block = PRB_R1,
Power Tune = PTM_R4
Device Setup
Inputs ac-shorted to ground
SNR
Signal-to-noise ratio, Aweighted (1) (2)
DR
Dynamic range A-weighted (1)
THD+N
TYP
(CM = 0.9V)
80
IN2_R, IN3_R routed to Right ADC and ac-shorted to
ground
IN2_L, IN3_L routed to Left ADC and ac-shorted to
ground
(2)
Total Harmonic Distortion plus
Noise
93
93
–60dB full-scale, 1kHz input signal
93
–3dB full-scale, 1kHz input signal
–84
IN2_R,IN3_R routed to Right ADC
IN2_L, IN3_L routed to Left ADC
–3dB full-scale, 1kHz input signal
–84
dB
dB
–70
dB
AUDIO ADC (CM = 0.75V)
Input signal level (for 0dB output) Single-ended, CM = 0.75V, AVdd = 1.5V
0.375
VRMS
Device Setup: 1kHz sine wave input
Single-ended Configuration
INR, IN2_R, IN3_R routed to Right ADC
INL, IN2_L, IN3_L routed to Left ADC
RIN = 20kΩ, fS = 48kHz,
AOSR = 128, MCLK = 256 * fS,
PLL Disabled, AGC = OFF,
Channel Gain = 0dB,
Processing Block = PRB_R1
Power Tune = PTM_R4
SNR
(1)
(2)
8
Signal-to-noise ratio, A-weighted
(1) (2)
Inputs ac-shorted to ground
90
dB
Ratio of output level with 1kHz full-scale sine wave input, to the output level with the inputs short circuited, measured A-weighted over a
20Hz to 20kHz bandwidth using an audio analyzer.
All performance measurements done with 20kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may
result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter
removes out-of-band noise, which, although not audible, may affect dynamic specification values
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Electrical Characteristics, ADC (continued)
At 25°C, Vsys, AVdd, DVdd, IOVdd, DVdd_CP, DRVdd_HP = 1.8V, fs (Audio) = 48kHz, Cref = 1µF on REF PIN, PLL and
Charge pump disabled unless otherwise noted.
PARAMETER
TEST CONDITIONS
DR
Dynamic range A-weighted (1)
(2)
THD+N
Total Harmonic Distortion plus
Noise
MIN
TYP
MAX
UNIT
–60dB full-scale, 1kHz input signal
90
dB
–3dB full-scale, 1kHz input signal
–81
dB
10
mVRMS
Inputs ac-shorted to ground, input referred noise
2.8
μVRMS
0.1
dB
Gain Error
1kHz sine wave input
Single-ended configuration
RIN = 20kΩ, fS = 48kHz, AOSR = 128,
MCLK = 256 * fS, PLL Disabled
AGC = OFF, Channel Gain = 0dB
Processing Block = PRB_R1,
Power Tune = PTM_R4, CM = 0.9V
109
dB
Input Channel Separation
1kHz sine wave input at -3dBFS
Single-ended configuration
IN1_L routed to Left ADC
IN1_R routed to Right ADC, RIN = 20kΩ
AGC = OFF, AOSR = 128,
Channel Gain = 0dB, CM = 0.9V
108
dB
Input Pin Crosstalk
1kHz sine wave input at –3dBFS on IN2_L, IN2_L
internally not routed.
IN1_L routed to Left ADC
ac-coupled to ground
55
dB
AUDIO ADC (Gain = 40dB)
Input signal level (for 0dB output) Differential Input, CM = 0.9V, Channel Gain = 40dB
Device Setup
ICN
Idle-Channel Noise, Aweighted (1) (2)
1kHz sine wave input
Differential configuration
IN1_L and IN1_R routed to Right ADC
IN2_L and IN2_R routed to Left ADC
RIN = 10kΩ, fS = 48kHz, AOSR = 128
MCLK = 256 * fS PLL Disabled
AGC = OFF
Processing Block = PRB_R1,
Power Tune = PTM_R4
AUDIO ADC
1kHz sine wave input at –3dBFS on IN2_R,
IN2_R internally not routed.
IN1_R routed to Right ADC
ac-coupled to ground
Single-ended configuration RIN = 20kΩ,
AOSR = 128 Channel, Gain = 0dB, CM = 0.9V
PSRR
217Hz, 100mVpp signal on AVdd,
Single-ended configuration, RIN= 20kΩ,
Channel Gain = 0dB; CM = 0.9V
Single-Ended, RIN = 10kΩ, PGA gain set to 0dB
Single-Ended, RIN = 10kΩ, PGA gain set to 47.5dB
ADC programmable gain
amplifier gain
ADC programmable gain
amplifier step size
Single-Ended, RIN = 20kΩ, PGA gain set to 0dB
0
dB
47.5
dB
–6
dB
Single-Ended, RIN = 20kΩ, PGA gain set to 47.5dB
41.5
dB
Single-Ended, RIN = 40kΩ, PGA gain set to 0dB
–12
dB
Single-Ended, RIN = 40kΩ, PGA gain set to 47.5dB
35.5
dB
0.5
dB
1kHz tone
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8.6 Electrical Characteristics, Bypass Outputs
At 25°C, Vsys, AVdd, DVdd, IOVdd, DVdd_CP, DRVdd_HP = 1.8V, fs (Audio) = 48kHz, Cref = 1µF on REF PIN, PLL and
Charge pump disabled unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG BYPASS TO HEADPHONE AMPLIFIER, DIRECT MODE
Load = 16Ω (single-ended), 50pF;
Input and Output CM = 0.9V;
Headphone Output on DRVdd_HP Supply;
IN1_L routed to HPL and IN1_R routed to
HPR;
Channel Gain = 0dB
Device Setup
Gain Error
Noise, A-weighted
THD
(1)
Total Harmonic Distortion
0.8
dB
Idle Channel, IN1_L and IN1_R ac-shorted to
ground
3.3
μVRMS
446mVrms, 1kHz input signal
–81
dB
ANALOG BYPASS TO LINE-OUT AMPLIFIER, PGA MODE
Device Setup
Load = 10kΩ (single-ended), 50pF;
Input and Output CM = 0.9V;
LINE Output on DRVDD_HP Supply;
IN1_L, IN1_R routed to line out
Channel Gain = 0dB
Gain Error Gain Error
Idle Channel,
IN1_L and IN1_R ac-shorted to ground
Noise, A-weighted (1)
(1)
10
Channel Gain = 40dB,
Input Signal (0dB) = 5mVRMS
Inputs ac-shorted to ground, Input Referred
0.8
dB
6.7
μVRMS
3
μVRMS
All performance measurements done with 20kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may
result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter
removes out-of-band noise, which, although not audible, may affect dynamic specification values
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8.7 Electrical Characteristics, Microphone Interface
At 25°C, Vsys, AVdd, DVdd, IOVdd, DVdd_CP, DRVdd_HP = 1.8V, fs (Audio) = 48kHz, Cref = 1µF on REF PIN, PLL and
Charge pump disabled unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
MICROPHONE BIAS
Bias voltage
Bias voltage CM = 0.9V, DRVdd_HP = 1.8V
Micbias Mode 0, Connect to AVdd or
DRVdd_HP
1.5
V
AVdd
V
DRVdd_HP
V
Micbias Mode 0, Connect to AVdd or
DRVdd_HP
1.23
V
Micbias Mode 1, Connect to AVdd or
DRVdd_HP
1.43
V
AVdd
V
DRVdd_HP
V
Micbias Mode 0, Connect to DRVdd_HP
1.5
V
Micbias Mode 1, Connect to DRVdd_HP
1.7
V
Micbias Mode 2, Connect to DRVdd_HP
2.5
V
Micbias Mode 3, Connect to DRVdd_HP
DRVdd_HP
V
Micbias Mode 0, Connect to DRVdd_HP
1.23
V
Micbias Mode 1, Connect to DRVdd_HP
1.43
V
Micbias Mode 2, Connect to DRVdd_HP
2.1
V
Micbias Mode 3, Connect to DRVdd_HP
DRVdd_HP
V
Micbias Mode 3, Connect to AVdd
Micbias Mode 3, Connect to DRVdd_HP
CM = 0.75V, DRVdd_HP = 1.8V
Micbias Mode 3, Connect to AVdd
Micbias Mode 3, Connect to DRVdd_HP
MICROPHONE BIAS
Bias voltage
Bias voltage CM = 0.9V, DRVdd_HP = 3.3V
CM = 0.75V, DRVdd_HP = 3.3V
Output Noise
Current Sourcing
Inline Resistance
CM = 0.9V, Micbias Mode 2, A-weighted,
20Hz to 20kHz bandwidth,
Current load = 0mA.
Micbias Mode 2, Connect to DRVdd_HP
Micbias Mode 3, Connect to AVdd
Micbias Mode 3, Connect to DRVdd_HP
9.5
μVRMS
3
131
89
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8.8 Electrical Characteristics, Audio DAC Outputs
At 25°C, Vsys, AVdd, DVdd, IOVdd, DVdd_CP, DRVdd_HP = 1.8V, fs (Audio) = 48kHz, Cref = 1µF on REF PIN, PLL and
Charge pump disabled unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.5
VRMS
87
100
dB
–60dB 1kHz input full-scale signal, Word
length = 20 bits
100
dB
AUDIO DAC – STEREO SINGLE-ENDED LINE OUTPUT (CM = 0.9V)
Load = 10kΩ (single-ended), 56pF
Line Output on AVdd Supply
Input and Output CM=0.9V
DOSR = 128, MCLK = 256 x fS,
Channel Gain = 0dB, word length = 16 bits,
Processing Block = PRB_P1,
Power Tune = PTM_P3
Device Setup
Full scale output voltage (0dB)
SNR
Signal-to-noise ratio A-weighted (1)
(2)
(1) (2)
All zeros fed to DAC input
DR
Dynamic range, A-weighted
THD+N
Total Harmonic Distortion plus Noise
–3dB full-scale, 1kHz input signal
–81
DAC Gain Error
0dB, 1kHz input full scale signal
0.5
dB
DAC Mute Attenuation
Mute
121
dB
DAC channel separation
–1dB, 1kHz signal, between left and right HP
out
108
dB
100mVpp, 1kHz signal applied to AVdd
72
dB
100mVpp, 217Hz signal applied to AVdd
80
dB
DAC PSRR
–70
dB
AUDIO DAC – STEREO SINGLE-ENDED LINE OUTPUT (CM = 0.75V)
Load = 10kΩ (single-ended), 56pF
Line Output on AVdd Supply
Input and Output CM = 0.75V; AVdd = 1.5V
DOSR = 128
MCLK=256 x fS
Channel Gain = 0dB
word length = 20-bits
Processing Block = PRB_P1
Power Tune = PTM_P4
Device Setup
Full scale output voltage (0dB)
0.375
(1) (2)
SNR
Signal-to-noise ratio, A-weighted
DR
Dynamic range, A-weighted
THD+N
Total Harmonic Distortion plus Noise
(1) (2)
VRMS
All zeros fed to DAC input
99
dB
–60dB 1kHz input full-scale signal
98
dB
–1dB full-scale, 1kHz input signal
–77
dB
AUDIO DAC – STEREO SINGLE-ENDED HEADPHONE OUTPUT (GROUND-CENTERED CIRCUIT CONFIGURATION)
Load = 16Ω (single-ended), 56pF
Input CM = 0.9V, Output CM = 0V
DOSR = 128,
MCLK = 256x* fS, Channel Gain = 0dB
word length = 16 bits;
Processing Block = PRB_P1
Power Tune = PTM_P3
Device Setup
FS1
Full scale output voltage
(for THD ≤ –40dB)
SNR
Signal-to-noise ratio, A-weighted (1)
DR
Dynamic range, A-weighted
THD+N
Total Harmonic Distortion plus Noise
(1)
(2)
12
0.65
(2)
(1) (2)
All zeros fed to DAC input
85
VRMS
95
dB
–60dB 1kHz input full-scale signal, Word
Length = 20 bits, Power Tune = PTM_P4
93
dB
500mVRMS output (corresponds to FS1 –
2.3dB),
1-kHz input signal
–70
–55
dB
Ratio of output level with 1kHz full-scale sine wave input, to the output level with the inputs short circuited, measured A-weighted over a
20Hz to 20kHz bandwidth using an audio analyzer.
All performance measured with 20kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may result in higher
THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes out-ofband noise, which, although not audible, may affect dynamic specification values.
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Electrical Characteristics, Audio DAC Outputs (continued)
At 25°C, Vsys, AVdd, DVdd, IOVdd, DVdd_CP, DRVdd_HP = 1.8V, fs (Audio) = 48kHz, Cref = 1µF on REF PIN, PLL and
Charge pump disabled unless otherwise noted.
PARAMETER
TEST CONDITIONS
SNR
TYP
MAX
UNIT
500mVRMS output, 1kHz input full scale signal
0.5
dB
DAC Mute Attenuation
Mute
118
dB
DAC channel separation
–3dB, 1kHz signal, between left and right HP
out
102
dB
100mVpp, 1kHz signal applied to AVdd
66
dB
100mVpp, 217Hz signal applied to AVdd
77
dB
mW
DAC PSRR
FS2
MIN
DAC Gain Error
Power Delivered
THD ≤ –40dB
26.5
Full scale output voltage
(for THD ≤ –40dB)
Load = 32Ω
0.85
Signal-to-noise ratio, A-weighted
(1) (2)
All zeros fed to DAC input, Load = 32Ω
THD ≤ –40dB, Load = 32Ω
Power Delivered
V
96
dB
22.5
mW
0.5
VRMS
100
dB
AUDIO DAC – STEREO SINGLE-ENDED HEADPHONE OUTPUT (UNIPOLAR CIRCUIT CONFIGURATION)
Load = 16Ω (single-ended), 56pF,
Headphone Output on AVdd Supply,
Input and Output CM = 0.9V
DOSR = 128, MCLK = 256 x fS,
Channel Gain = 0dB
Processing Block = PRB_P1,
Power Tune = PTM_P3
Device Setup
Full scale output voltage (0dB)
(1) (2)
SNR
Signal-to-noise ratio, A-weighted
DR
Dynamic range, A-weighted
THD+N
Total Harmonic Distortion plus Noise
(1) (2)
All zeros fed to DAC input
87
-60dB 1kHz input full-scale signal
100
–3dB full-scale, 1kHz input signal
–83
dB
–70
dB
8.9 Electrical Characteristics, Misc.
At 25°C, Vsys, AVdd, DVdd, IOVdd, DVdd_CP, DRVdd_HP = 1.8V, fs (Audio) = 48kHz, Cref = 1µF on REF PIN, PLL and
Charge pump disabled unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
REFERENCE
Reference Voltage Settings
Reference Noise
CMMode = 0 (0.9V)
0.9
CMMode = 1 (0.75V)
0.75
CM = 0.9V, A-weighted, 20Hz to 20kHz bandwidth,
CREF = 1μF
Decoupling Capacitor
Bias Current
1.1
V
μVRMS
1
μF
120
μA
1.6V
0.7 × IOVDD
V
IIH = 5μA, 1.2V ≤ IOVDD < 1.6V
0.9 × IOVDD
V
IIH = 5μA, IOVDD < 1.2V
IOVDD
V
IIL = 5 μA, IOVDD > 1.6V
–0.3
IIL = 5μA, 1.2V ≤ IOVDD < 1.6V
0.3 × IOVDD
V
0.1 × IOVDD
V
0
V
IIL = 5μA, IOVDD < 1.2V
VOH
IOH = 2 TTL loads
VOL
IOL = 2 TTL loads
0.8 × IOVDD
V
0.1 × IOVDD
Capacitive Load
(1)
10
V
pF
Applies to all DI, DO, and DIO pins shown in Pin Configuration and Functions
8.11 I2S/LJF/RJF Timing in Master Mode (see Figure 1)
All specifications at 25°C, DVdd = 1.8 V
IOVDD=1.8V
MIN
IOVDD=3.3V
MAX
MIN
UNIT
MAX
td(WS)
WCLK delay
30
20
ns
td(DO-WS)
WCLK to DOUT delay (For LJF Mode only)
20
20
ns
td(DO-BCLK)
BCLK to DOUT delay
22
20
ns
ts(DI)
DIN setup
8
8
th(DI)
DIN hold
8
8
tr
Rise time
24
12
ns
tf
Fall time
24
12
ns
ns
ns
WCLK
td(WS)
BCLK
td(DO-WS)
td(DO-BCLK)
DOUT
tS(DI)
th(DI)
DIN
Figure 1. I2S/LJF/RJF Timing in Master Mode
14
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8.12 I2S/LJF/RJF Timing in Slave Mode (see Figure 2)
IOVDD=1.8V
MIN
IOVDD=3.3V
MAX
MIN
UNIT
MAX
tH(BCLK)
BCLK high period
35
35
tL(BCLK)
BCLK low period
35
35
ns
ts(WS)
WCLK setup
8
8
th(WS)
WCLK hold
8
td(DO-WS)
WCLK to DOUT delay (For LJF mode only)
td(DO-BCLK)
BCLK to DOUT delay
ts(DI)
DIN setup
8
8
th(DI)
DIN hold
8
8
tr
Rise time
4
4
tf
Fall time
4
4
8
20
20
22
22
WCLK
th(WS)
BCLK
tL(BCLK)
tH(BCLK)
ts(WS)
td(DO-WS)
td(DO-BCLK)
DOUT
ts(DI)
th(DI)
DIN
Figure 2. I2S/LJF/RJF Timing in Slave Mode
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8.13 DSP Timing in Master Mode (see Figure 3)
All specifications at 25°C, DVdd = 1.8 V
IOVDD=1.8V
MIN
IOVDD=3.3V
MAX
MIN
UNIT
MAX
td(WS)
WCLK delay
30
20
ns
td(DO-BCLK)
BCLK to DOUT delay
22
20
ns
ts(DI)
DIN setup
8
th(DI)
DIN hold
8
tr
Rise time
24
12
ns
tf
Fall time
24
12
ns
8
ns
8
ns
WCLK
td(WS)
td(WS)
BCLK
td(DO-BCLK)
DOUT
ts(DI)
th(DI)
DIN
Figure 3. DSP Timing in Master Mode
16
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8.14 DSP Timing in Slave Mode (see Figure 4)
IOVDD=1.8V
MIN
IOVDD=3.3V
MAX
MIN
UNIT
MAX
tH(BCLK)
BCLK high period
35
35
ns
tL(BCLK)
BCLK low period
35
35
ns
ts(WS)
WCLK setup
8
8
ns
th(WS)
WCLK hold
8
8
td(DO-BCLK)
BCLK to DOUT delay
ts(DI)
DIN setup
8
8
th(DI)
DIN hold
8
8
tr
Rise time
4
4
ns
tf
Fall time
4
4
ns
22
ns
22
ns
ns
ns
WCLK
th(ws)
BCLK
tH(BCLK)
ts(ws)
th(ws)
th(ws)
tL(BCLK)
td(DO-BCLK)
DOUT
ts(DI)
th(DI)
DIN
Figure 4. DSP Timing in Slave Mode
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8.15 Digital Microphone PDM Timing (see Figure 5)
Based on design simulation. Not tested in actual silicon.
IOVDD = 1.8V
MIN
IOVDD = 3.3V
MAX
MIN
UNIT
MAX
ts
DIN setup
20
20
th
DIN hold
5
5
tr
Rise time
4
4
ns
tf
Fall time
4
4
ns
th
tr
ns
ns
tf
ts
ADC_MOD_CLK
DIG_MIC_IN
DATA-LEFT
DATA-RIGHT
DATA-LEFT
DATA-RIGHT
Figure 5. PDM Input Timing
18
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8.16 I2C Interface Timing
Standard-Mode
MIN
0
TYP
Fast-Mode
MAX
0
TYP
UNIT
MAX
fSCL
SCL clock frequency
tH(STA)
Hold time (repeated) START condition.
After this period, the first clock pulse is
generated.
4.0
0.8
μs
tLOW
LOW period of the SCL clock
4.7
1.3
μs
tHIGH
HIGH period of the SCL clock
4.0
0.6
μs
tSU(STA)
Setup time for a repeated START
condition
4.7
0.8
μs
tH(DAT)
Data hold time: For I2C bus devices
tSU(DAT)
Data set-up time
tr
0
100
MIN
400
μs
3.45
0
SDA and SCL Rise Time
1000
20+0.1Cb
300
ns
tf
SDA and SCL Fall Time
300
20+0.1Cb
300
ns
tSU(STO)
Set-up time for STOP condition
4.0
0.8
μs
tBUF
Bus free time between a STOP and
START condition
4.7
1.3
μs
Cb
Capacitive load for each bus line
250
0.9
kHz
100
400
ns
400
pF
Figure 6. I2C Interface Timing
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8.17 SPI Interface Timing
IOVDD=1.8V
MIN
TYP
IOVDD=3.3V
MAX
MIN
TYP
UNIT
MAX
tsck
SCLK Period
100
50
ns
tsckh
SCLK Pulse width High
50
25
ns
tsckl
SCLK Pulse width Low
50
25
ns
tlead
Enable Lead Time
30
20
ns
tlag
Enable Lag Time
30
20
ns
td
Sequential Transfer Delay
40
ta
Slave DOUT access time
40
20
ns
tdis
Slave DOUT disable time
40
20
ns
tsu
DIN data setup time
15
10
th(DIN)
DIN data hold time
15
10
tv(DOUT)
DOUT data valid time
tr
tf
20
ns
ns
ns
25
18
ns
SCLK Rise Time
4
4
ns
SCLK Fall Time
4
4
ns
SS
S
t
t Lead
t Lag
t
td
sck
SCLK
t sckl
tf
tr
t sckh
t v(DOUT)
t dis
MISO
MSB OUT
ta
MOSI
t su
BIT 6 . . . 1
LSB OUT
t h(DIN)
MSB IN
BIT 6 . . . 1
LSB IN
At 25°C, DVDD = 1.8 V
Figure 7. SPI Interface Timing Diagram
20
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8.18 Typical Characteristics
8.18.1 Typical Performance
0
100
RIN = 10 kW, Differential
-10
RIN = 20 kW, Differential
90
-20
85
-30
80
RIN = 10 kW, Single Ended
THDN dB
SNR - Signal-to-Noise Ratio - dB
95
75
RIN = 20 kW, Single Ended
70
32W
-40
16W
-50
65
-60
60
-70
55
-80
50
-20
0
20
Channel Gain - dB
40
60
0
Figure 8. ADC SNR vs Channel Gain
20
30
Headphone Output Power mW
40
50
Figure 9. Total Harmonic Distortion GCHP Configuration
vs Headphone Output Power
0
0
32 W BTL Load
CM = 1.65 V,
RL = 32 W
-10
THD - Total Harmonic Distortion - dB
CM = 0.9 V,
RL = 16 W
CM = 0.9 V,
RL = 32 W
-10
THD - Total Harmonic Distortion - dB
10
-20
-30
CM = 1.65 V,
RL = 16 W
-40
-50
-60
-70
GCHP Mode
DRVDD_HP = 1.8V
CM = 0.9 V
-20
-30
Unipolar Mode
DRVDD_HP = 3.3V
CM = 1.65 V
-40
-50
-60
-70
-80
-80
-90
-90
0
20
40
60
Headphone Output Power - mW
80
0
50
100
150
Headphone Output Power - mW
200
Figure 11. Total Harmonic Distortion vs Headphone Output
Power
Figure 10. Total Harmonic Distortion Unipolar
Configuration vs Headphone Output Power
105
60
50
SNR
95
90
40
85
30
80
Output Power
75
20
Power Delivered - mW
SNR - Signal-to-Noise Ratio - dB
100
70
10
65
60
0
0
0.75
0.9
1.25
1.5
Output Common Mode Setting
1.65
Figure 12. Headphone SNR and Output Power vs Output Common Mode Setting
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8.18.2 FFT
0
0
DAC
ADC
-20
-20
-40
-60
Power - dBr
Power - dBFs
-40
-80
-100
-60
-80
-100
-120
-120
-140
-160
0
5000
10000
f - Frequency - Hz
15000
-140
20000
Figure 13. Single Ended Line Input to ADC FFT at -1dBr vs
Frequency
0
5000
10000
f - Frequency - Hz
15000
Figure 14. DAC Playback to Headphone FFT at -1dBFS
(Unipolar Mode) vs Frequency
0
0
DAC
-20
-20
-40
-40
Power - dBr
Power - dBr
DAC
-60
-80
-120
-120
0
5000
10000
f - Frequency - Hz
15000
20000
-140
0
0
0
-20
-20
-40
-40
-60
-80
-120
-120
5000
10000
f - Frequency - Hz
15000
20000
Figure 17. Line Input to Headphone FFT at 446 mVrms
(Unipolar Mode) vs Frequency
15000
20000
-80
-100
0
10000
f - Frequency - Hz
-60
-100
-140
5000
Figure 16. DAC Playback to Line-Out FFT at -1dBFS to
Frequency
Power - dBr
Power - dBr
-80
-100
Figure 15. DAC Playback to Headphone FFT at -1dBFS
(Ground-Centered Mode) vs Frequency
22
-60
-100
-140
20000
-140
0
5000
10000
f - Frequency - Hz
15000
20000
Figure 18. Line Input to Line-Out FFT at 446 mVrms (PGA
Mode) vs Frequency
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9 Parameter Measurement Information
All parameters are measured according to the conditions described in the Specifications section.
10 Detailed Description
10.1 Overview
The TLV320AIC3206 includes extensive register-based control of power, input/output channel configuration,
gains, effects, pin-multiplexing and clocks, allowing precise targeting of the device to its application. Combined
with the advanced PowerTune technology, the device covers operations from 8 kHz mono voice playback to
audio stereo 192kHz DAC playback, making it ideal for portable battery-powered audio and telephony
applications.
The record path of the TLV320AIC3206 covers operations from 8kHz mono to 192kHz stereo recording, and
contains programmable input channel configurations covering single-ended and differential setups, as well as
floating or mixing input signals. It also includes a digitally-controlled stereo microphone preamplifier and
integrated microphone bias. Digital signal processing blocks can remove audible noise that may be introduced by
mechanical coupling, e.g. optical zooming in a digital camera.
The integrated PowerTune technology allows the device to be tuned to an optimum power-performance trade-off.
Mobile applications frequently have multiple use cases requiring very low power operation while being used in a
mobile environment. When used in a docked environment power consumption typically is less of a concern, while
minimizing noise is important. With PowerTune, the TLV320AIC3206 addresses both cases.
The device offers single supply operation from 1.5V-1.95V. Digital I/O voltages are supported in the range of
1.1V-3.6V.
The required internal clock of the TLV320AIC3206 can be derived from multiple sources, including the MCLK pin,
the BCLK pin, the GPIO pin or the output of the internal PLL, where the input to the PLL again can be derived
from the MCLK pin, the BCLK or GPIO pins. Although using the PLL ensures the availability of a suitable clock
signal, PLL use is not recommended for the lowest power settings. The PLL is highly programmable and can
accept available input clocks in the range of 512 kHz to 50 MHz.
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10.2 Functional Block Diagram
Figure 19 shows the basic functional blocks of the device.
IN1_L
IN2_L
IN3_L
0…+47.5 dB
+
Left
ADC
tpl
+
*
AGC
DRC
ADC
Signal
Proc.
DAC
Signal
Proc.
Vol . Ctrl
*
-6...+14dB
+
Left
DAC
HPL
1dB steps
Gain Adj.
0.5 dB
steps
-6...+29dB
-30...0 dB
LOL
+
1dB steps
Data Interface
-6...+29dB
-30...0 dB
LOR
+
1dB steps
0…
+47.5 dB
+
Gain Adj.
Right
ADC
IN3_R
+
tpr
*
0.5 dB steps
IN2_R
ADC
Signal
Proc.
DAC
Signal
Proc.
AGC
DRC
*
-6...+14dB
Right
DAC
HPR
+
1dB steps
Vol . Ctrl
IN1_R
GND_Sense
SPI_Select
SPI / I2C
Control Block
Reset
MicBias
MicDet
Ref
PLL
Dig
Mic
Inter
rupt
Sec.
I2S I/F
Primary
I2S Interface
VNEG
Charge
Pump
Mic
Bias
Supplies
Fly_N
Fly_P
Pin Muxing / Clock Routing
Ref
DVDD_CP
DVSS_CP
BCLK
WCLK
DIN
DOUT
GPIO
MCLK
SCLK
MISO
SDA/MOSI
SCL/SS
IOVss (GND)
DVss (GND)
Avss (GND)
GND
IOVdd
AVdd
DVdd
Vsys
DRVdd_HP
Figure 19. Block Diagram
10.3 Feature Description
10.3.1 Device Connections
10.3.1.1 Digital Pins
Only a small number of digital pins are dedicated to a single function; whenever possible, the digital pins have a
default function, and also can be reprogrammed to cover alternative functions for various applications.
The fixed-function pins are Reset and the SPI_Select pin, which are HW control pins. Depending on the state of
SPI_Select, the two control-bus pins SCL/SS and SDA/MOSI are configured for either I2C or SPI protocol.
Other digital IO pins can be configured for various functions via register control. An overview of available
functionality is given in Multifunction Pins.
24
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Feature Description (continued)
10.3.1.1.1 Multifunction Pins
Table 1 shows the possible allocation of pins for specific functions. The PLL input, for example, can be
programmed to be any of 4 pins (MCLK, BCLK, DIN, GPIO).
Table 1. Multifunction Pin Assignments
Pin Function
A
1
2
3
4
5
6
7
8
MCLK
BCLK
WCLK
DIN
MFP1
DOUT
MFP2
DMDIN/
MFP3/
SCLK
DMCLK/
MFP4/
MISO
GPIO
MFP5
S (1)
S (2)
PLL Input
B
Codec Clock Input
S
2
(1)
,D
(4)
S
C
I S BCLK input
S,D
D
I2S BCLK output
E (5)
2
E
I S WCLK input
F
I2S WCLK output
G
I2S ADC word clock input
S (3)
E
(2)
S (3)
E, D
E
E
2
E
H
I S ADC WCLK out
I
I2S DIN
J
I2S DOUT
K
General Purpose Output I
K
General Purpose Output II
K
General Purpose Output III
L
General Purpose Input I
L
General Purpose Input II
L
General Purpose Input III
M
INT1 output
E
N
INT2 output
E
Q
Secondary I2S BCLK input
E
E
R
Secondary I2S WCLK in
E
E
S
2
Secondary I S DIN
E
T
Secondary I2S DOUT
U
Secondary I2S BCLK OUT
E
E
E
V
Secondary I2S WCLK OUT
E
E
E
Aux Clock Output
E
E
E
X
(1)
(2)
(3)
(4)
(5)
E
E
E, D
E, D
E
E
E
E
E
E
E
E
E
E
E
E
S(1):
S(2):
(3)
The MCLK pin can drive the PLL and Codec Clock inputs simultaneously.
The BCLK pin can drive the PLL and Codec Clock and audio interface bit clock inputs simultaneously.
S : The GPIO/MFP5 pin can drive the PLL and Codec Clock inputs simultaneously.
D: Default Function
E: The pin is exclusively used for this function, no other function can be implemented with the same pin. (If GPIO/MFP5 has been
allocated for General Purpose Output, it cannot be used as the INT1 output at the same time.)
10.3.1.2 Analog Pins
Analog functions can also be configured to a large degree. For minimum power consumption, analog blocks are
powered down by default. The blocks can be powered up with fine granularity according to the application needs.
10.3.2 Analog Audio I/O
The analog IO path of the TLV320AIC3206 features a large set of options for signal conditioning as well as signal
routing:
• 6 analog inputs which can be mixed and-or multiplexed in single-ended and-or differential configuration
• 2 programmable gain amplifiers (PGA) with a range of 0 to +47.5dB
• 2 mixer amplifiers for analog bypass
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•
•
•
•
•
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2 low power analog bypass channels
Mute function
Channel-to-channel phase adjustment
Fast charge of ac-coupling capacitors
Anti thump
10.3.2.1 Analog Bypass
The TLV320AIC3206 offers two analog-bypass modes. In either of the modes, an analog input signal can be
routed from an analog input pin to an amplifier driving an analog output pin. Neither the ADC nor the DAC
resources are required for such operation.
In analog low-power bypass mode, line-level signals can be routed directly from the analog inputs IN1_L to the
left headphone amplifier (HPL) and IN1_R to HPR.
10.3.2.2 ADC Bypass Using Mixer Amplifiers
In addition to the analog low-power bypass mode, another bypass mode uses the programmable gain amplifiers
of the input stage in conjunction with a mixer amplifier. With this mode, microphone-level signals can be amplified
and routed to the line or headphone outputs, fully bypassing the ADC and DAC.
To enable this mode, the mixer amplifiers are powered on via software command.
10.3.2.3 Headphone Output
The stereo headphone drivers on pins HPL and HPR can drive loads with impedances down to 16Ω in singleended DC-coupled headphone configurations. An integral charge pump generates the negative supply required
to operate the headphone drivers in dc-coupled mode, where the common mode of the output signal is made
equal to the ground of the headphone load using a ground-sense circuit. Operation of headphone drivers in dccoupled (ground centered mode) eliminates the need for large dc-blocking capacitors.
HPL
HPR
GND_SENSE
Figure 20. TLV320AIC3206 Ground-Centered Headphone Output
Alternatively the headphone amplifier can also be operated in a unipolar circuit configuration using DC blocking
capacitors.
10.3.2.4 Line Outputs
The stereo line level drivers on LOL and LOR pins can drive a wide range of line level resistive impedances in
the range of 600Ω to 10kΩ. The output common modes of line level drivers can be configured to equal either the
analog input common-mode setting, or 1.65V. With output common-mode setting of 1.65V and DRVdd_HP
supply at 3.3V the line-level drivers can drive up to 1Vrms output signal. The line-level drivers can drive out a
mixed combination of DAC signal and attenuated ADC PGA signal. Signal mixing is register-programmable.
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10.3.3 ADC
The TLV320AIC3206 includes a stereo audio ADC, which uses a delta-sigma modulator with a programmable
oversampling ratio, followed by a digital decimation filter. The ADC supports sampling rates from 8kHz to
192kHz. In order to provide optimal system power management, the stereo recording path can be powered up
one channel at a time, to support the case where only mono record capability is required.
The ADC path of the TLV320AIC3206 features a large set of options for signal conditioning as well as signal
routing:
• Two ADCs
• Six analog inputs which can be mixed and-or multiplexed in single-ended and-or differential configuration
• Two programmable gain amplifiers (PGA) with a range of 0 to +47.5dB
• Two mixer amplifiers for analog bypass
• Two low power analog bypass channels
• Fine gain adjustment of digital channels with 0.1dB step size
• Digital volume control with a range of -12 to +20dB
• Mute function
In addition to the standard set of ADC features the TLV320AIC3206 also offers the following special functions:
• Channel-to-channel phase adjustment
• Fast charge of ac-coupling capacitors
• Anti thump
• Adaptive filter mode
10.3.3.1 ADC Processing
The TLV320AIC3206 ADC channel includes a built-in digital decimation filter to process the oversampled data
from the to generate digital data at Nyquist sampling rate with high dynamic range. The decimation filter can be
chosen from three different types, depending on the required frequency response, group delay and sampling
rate.
10.3.3.1.1 ADC Processing Blocks
The TLV320AIC3206 offers a range of processing blocks which implement various signal processing capabilities
along with decimation filtering. These processing blocks give users the choice of how much and what type of
signal processing they may use and which decimation filter is applied.
The choice between these processing blocks is part of the PowerTune strategy to balance power conservation
and signal-processing flexibility. Less signal-processing capability reduces the power consumed by the device.
Table 2 gives an overview of the available processing blocks and their properties. The Resource Class Column
(RC) gives an approximate indication of power consumption.
The signal processing blocks available are:
• First-order IIR
• Scalable number of biquad filters
• Variable-tap FIR filter
The processing blocks are tuned for common cases and can achieve high anti-alias filtering or low group delay in
combination with various signal processing effects such as audio effects and frequency shaping. The available
first order IIR, BiQuad and FIR filters have fully user-programmable coefficients. The Resource Class Column
(RC) gives an approximate indication of power consumption.
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Table 2. ADC Processing Blocks
Processing
Blocks
Channel
Decimation
Filter
1st Order
IIR Available
Number
BiQuads
FIR
Required
AOSR Value
Resource
Class
PRB_R1 (1)
Stereo
A
Yes
0
No
128,64
6
PRB_R2
Stereo
A
Yes
5
No
128,64
8
PRB_R3
Stereo
A
Yes
0
25-Tap
128,64
8
PRB_R4
Right
A
Yes
0
No
128,64
3
PRB_R5
Right
A
Yes
5
No
128,64
4
PRB_R6
Right
A
Yes
0
25-Tap
128,64
4
PRB_R7
Stereo
B
Yes
0
No
64
3
PRB_R8
Stereo
B
Yes
3
No
64
4
PRB_R9
Stereo
B
Yes
0
20-Tap
64
4
PRB_R10
Right
B
Yes
0
No
64
2
PRB_R11
Right
B
Yes
3
No
64
2
PRB_R12
Right
B
Yes
0
20-Tap
64
2
PRB_R13
Stereo
C
Yes
0
No
32
3
PRB_R14
Stereo
C
Yes
5
No
32
4
PRB_R15
Stereo
C
Yes
0
25-Tap
32
4
PRB_R16
Right
C
Yes
0
No
32
2
PRB_R17
Right
C
Yes
5
No
32
2
PRB_R18
Right
C
Yes
0
25-Tap
32
2
(1)
Default
For more detailed information see the TLV320AIC3206 Application Reference Guide, SLAA463.
10.3.4 DAC
The TLV320AIC3206 includes a stereo audio DAC supporting data rates from 8kHz to 192kHz. Each channel of
the stereo audio DAC consists of a signal-processing engine with fixed processing blocks, a digital interpolation
filter, multi-bit digital delta-sigma modulator, and an analog reconstruction filter. The DAC is designed to provide
enhanced performance at low sampling rates through increased oversampling and image filtering, thereby
keeping quantization noise generated within the delta-sigma modulator and signal images strongly suppressed
within the audio band to beyond 20kHz. To handle multiple input rates and optimize power dissipation and
performance, the TLV320AIC3206 allows the system designer to program the oversampling rates over a wide
range from 1 to 1024. The system designer can choose higher oversampling ratios for lower input data rates and
lower oversampling ratios for higher input data rates.
The TLV320AIC3206 DAC channel includes a built-in digital interpolation filter to generate oversampled data for
the sigma-delta modulator. The interpolation filter can be chosen from three different types depending on
required frequency response, group delay and sampling rate.
The DAC path of the TLV320AIC3206 features many options for signal conditioning and signal routing:
• 2 headphone amplifiers
– Ground-centered, bipolar operation or unipolar operation
– Usable in single-ended or differential mode
– Analog volume setting with a range of -6 to +14dB
• 2 line-out amplifiers
– Usable in single-ended or differential mode
– Analog volume setting with a range of -6 to +29dB
• Digital volume control with a range of -63.5 to +24dB
• Mute function
• Dynamic range compression (DRC)
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In addition to the standard set of DAC features the TLV320AIC3206 also offers the following special features:
• Built in sine wave generation (beep generator)
• Digital auto mute
• Adaptive filter mode
10.3.4.1 DAC Processing Blocks — Overview
Table 3. Overview – DAC Predefined Processing Blocks
(1)
Processing
Block No.
Interpolation
Filter
Channel
1st Order
IIR Available
Num. of
Biquads
DRC
3D
Beep
Generator
PRB_P1 (1)
A
PRB_P2
A
Stereo
No
Stereo
Yes
3
No
No
No
6
Yes
No
PRB_P3
A
Stereo
No
Yes
6
No
No
PRB_P4
A
No
Left
No
3
No
No
No
PRB_P5
PRB_P6
A
Left
Yes
6
Yes
No
No
A
Left
Yes
6
No
No
No
PRB_P7
B
Stereo
Yes
0
No
No
No
PRB_P8
B
Stereo
No
4
Yes
No
No
PRB_P9
B
Stereo
No
4
No
No
No
PRB_P10
B
Stereo
Yes
6
Yes
No
No
PRB_P11
B
Stereo
Yes
6
No
No
No
PRB_P12
B
Left
Yes
0
No
No
No
PRB_P13
B
Left
No
4
Yes
No
No
PRB_P14
B
Left
No
4
No
No
No
PRB_P15
B
Left
Yes
6
Yes
No
No
PRB_P16
B
Left
Yes
6
No
No
No
PRB_P17
C
Stereo
Yes
0
No
No
No
PRB_P18
C
Stereo
Yes
4
Yes
No
No
PRB_P19
C
Stereo
Yes
4
No
No
No
PRB_P20
C
Left
Yes
0
No
No
No
PRB_P21
C
Left
Yes
4
Yes
No
No
PRB_P22
C
Left
Yes
4
No
No
No
PRB_P23
A
Stereo
No
2
No
Yes
No
PRB_P24
A
Stereo
Yes
5
Yes
Yes
No
PRB_P25
A
Stereo
Yes
5
Yes
Yes
Yes
Default
For more detailed information see the TLV320AIC3206 Application Reference Guide, SLAA463.
10.3.5 PowerTune
The TLV320AIC3206 features PowerTune, a mechanism to balance power-versus-performance trade-offs at the
time of device configuration. The device can be tuned to minimize power dissipation, to maximize performance,
or to an operating point between the two extremes to best fit the application. The TLV320AIC3206 PowerTune
modes are called PTM_R1 to PTM_R4 for the recording (ADC) path and PTM_P1 to PTM_P4 for the playback
(DAC) path.
For more detailed information see the TLV320AIC3206 Application Reference Guide, SLAA463.
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10.3.6 Digital Audio IO Interface
Audio data flows between the host processor and the TLV320AIC3206 on the digital audio data serial interface,
or audio bus. This very flexible bus includes left or right-justified data options, support for I2S or PCM protocols,
programmable data length options, a TDM mode for multichannel operation, very flexible master-slave
configurability for each bus clock line, and the ability to communicate with multiple devices within a system
directly.
The audio bus of the TLV320AIC3206 can be configured for left or right-justified, I2S, DSP, or TDM modes of
operation, where communication with standard PCM interfaces is supported within the TDM mode. These modes
are all MSB-first, with data width programmable as 16, 20, 24, or 32 bits by configuring Page 0, Register 27,
D(5:4). In addition, the word clock and bit clock can be independently configured in either Master or Slave mode,
for flexible connectivity to a wide variety of processors. The word clock is used to define the beginning of a
frame, and may be programmed as either a pulse or a square-wave signal. The frequency of this clock
corresponds to the maximum of the selected ADC and DAC sampling frequencies.
The bit clock is used to clock in and clock out the digital audio data across the serial bus. When in Master mode,
this signal can be programmed to generate variable clock pulses by controlling the bit-clock divider in Page 0,
Register 30. The number of bit-clock pulses in a frame may need adjustment to accommodate various word
lengths, and to support the case when multiple TLV320AIC3206s may share the same audio bus.
The TLV320AIC3206 also includes a feature to offset the position of start of data transfer with respect to the
word-clock. Control the offset in terms of number of bit-clocks by programming Page 0, Register 28.
The TLV320AIC3206 also has the feature to invert the polarity of the bit-clock used to transfer the audio data as
compared to the default clock polarity used. This feature can be used independently of the mode of audio
interface chosen. Page 0, Register 29, D(3) configures bit clock polarity.
The TLV320AIC3206 further includes programmability (Page 0, Register 27, D(0)) to place the DOUT line into a
hi-Z (3-state) condition during all bit clocks when valid data is not being sent. By combining this capability with
the ability to program at what bit clock in a frame the audio data begins, time-division multiplexing (TDM) can be
accomplished, enabling the use of multiple codecs on a single audio serial data bus. When the audio serial data
bus is powered down while configured in master mode, the pins associated with the interface are put into a hi-Z
output condition.
By default when the word-clocks and bit-clocks are generated by the TLV320AIC3206, these clocks are active
only when the codec (ADC, DAC or both) are powered up within the device. This intermittent clock operation
reduces power consumption. However, it also supports a feature when both the word clocks and bit-clocks can
be active even when the codec in the device is powered down. This continuous clock feature is useful when
using the TDM mode with multiple codecs on the same bus, or when word-clock or bit-clocks are used in the
system as general-purpose clocks.
10.3.7 Clock Generation and PLL
The TLV320AIC3206 supports a wide range of options for generating clocks for the ADC and DAC sections as
well as interface and other control blocks. The clocks for ADC and DAC require a source reference clock. This
clock can be provided on variety of device pins such as MCLK, BCLK or GPI pins. The CODEC_CLKIN can then
be routed through highly-flexible clock dividers to generate the various clocks required for the ADC and DAC
sections. In the event that the desired audio clocks cannot be generated from the reference clocks on MCLK,
BCLK or GPIO, the TLV320AIC3206 also provides the option of using the on-chip PLL which supports a wide
range of fractional multiplication values to generate the required clocks. Starting from CODEC_CLKIN the
TLV320AIC3206 provides several programmable clock dividers to help achieve a variety of sampling rates for
ADC, DAC and clocks for the processing block.
To minimize power consumption, the system ideally provides a master clock that is a suitable integer multiple of
the desired sampling frequencies. In such cases, internal dividers can be programmed to set up the required
internal clock signals at very low power consumption. For cases where such master clocks are not available, the
built-in PLL can be used to generate a clock signal that serves as an internal master clock. In fact, this master
clock can also be routed to an output pin and may be used elsewhere in the system. The clock system is flexible
enough that it even allows the internal clocks to be derived directly from an external clock source, while the PLL
is used to generate some other clock that is only used outside the TLV320AIC3206.
For more detailed information see the TLV320AIC3206 Application Reference Guide, SLAA463.
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10.3.8 Control Interfaces
The TLV320AIC3206 control interface supports SPI or I2C communication protocols, with the protocol selectable
using the SPI_SELECT pin. For SPI, SPI_SELECT should be tied high; for I2C, SPI_SELECT should be tied low.
Changing the state of SPI_SELECT during device operation is not recommended.
10.3.8.1 I2C Control
The TLV320AIC3206 supports the I2C control protocol, and will respond to the I2C address of 0011000. I2C is a
two-wire, open-drain interface supporting multiple devices and masters on a single bus. Devices on the I2C bus
only drive the bus lines LOW by connecting them to ground; they never drive the bus lines HIGH. Instead, the
bus wires are pulled HIGH by pullup resistors, so the bus wires are HIGH when no device is driving them LOW.
This circuit prevents two devices from conflicting; if two devices drive the bus simultaneously, there is no driver
contention.
10.3.8.2 SPI Control
In the SPI control mode, the TLV320AIC3206 uses the pins SCL/SS as SS, SCLK as SCLK, MISO as MISO,
SDA/MOSI as MOSI; a standard SPI port with clock polarity setting of 0 (typical microprocessor SPI control bit
CPOL = 0). The SPI port allows full-duplex, synchronous, serial communication between a host processor (the
master) and peripheral devices (slaves). The SPI master (in this case, the host processor) generates the
synchronizing clock (driven onto SCLK) and initiates transmissions. The SPI slave devices (such as the
TLV320AIC3206) depend on a master to start and synchronize transmissions. A transmission begins when
initiated by an SPI master. The byte from the SPI master begins shifting in on the slave MOSI pin under the
control of the master serial clock (driven onto SCLK). As the byte shifts in on the MOSI pin, a byte shifts out on
the MISO pin to the master shift register.
For more detailed information see the TLV320AIC3206 Application Reference Guide, SLAA463.
10.4 Device Functional Modes
The following special functions are available to support advanced system requirements:
• Headset detection
• Interrupt generation
• Flexible pin multiplexing
For more detailed information see the TLV320AIC3206 Application Reference Guide, SLAA463.
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10.5 Register Map
10.5.1 Register Map Summary
Table 4. Summary of Register Map
Decimal
Hex
DESCRIPTION
PAGE NO.
REG. NO.
PAGE NO.
REG. NO.
0
0
0x00
0x00
Page Select Register
0
1
0x00
0x01
Software Reset Register
0
2
0x00
0x02
Reserved Register
0
3
0x00
0x03
Reserved Register
0
4
0x00
0x04
Clock Setting Register 1, Multiplexers
0
5
0x00
0x05
Clock Setting Register 2, PLL P&R Values
0
6
0x00
0x06
Clock Setting Register 3, PLL J Values
0
7
0x00
0x07
Clock Setting Register 4, PLL D Values (MSB)
0
8
0x00
0x08
Clock Setting Register 5, PLL D Values (LSB)
0
9-10
0x00
0x09-0x0A
Reserved Register
0
11
0x00
0x0B
Clock Setting Register 6, NDAC Values
0
12
0x00
0x0C
Clock Setting Register 7, MDAC Values
0
13
0x00
0x0D
DAC OSR Setting Register 1, MSB Value
0
14
0x00
0x0E
DAC OSR Setting Register 2, LSB Value
0
15
0x00
0x0F
Reserved Register
0
16
0x00
0x10
Reserved Register
0
17
0x00
0x11
Reserved Register
0
18
0x00
0x12
Clock Setting Register 8, NADC Values
0
19
0x00
0x13
Clock Setting Register 9, MADC Values
0
20
0x00
0x14
ADC Oversampling (AOSR) Register
0
21
0x00
0x15
Reserved Register
0
22
0x00
0x16
Reserved Register
0
23
0x00
0x17
Reserved Register
0
24
0x00
0x18
Reserved Register
0
25
0x00
0x19
Clock Setting Register 10, Multiplexers
0
26
0x00
0x1A
Clock Setting Register 11, CLKOUT M divider value
0
27
0x00
0x1B
Audio Interface Setting Register 1
0
28
0x00
0x1C
Audio Interface Setting Register 2, Data offset setting
0
29
0x00
0x1D
Audio Interface Setting Register 3
0
30
0x00
0x1E
Clock Setting Register 12, BCLK N Divider
0
31
0x00
0x1F
Audio Interface Setting Register 4, Secondary Audio Interface
0
32
0x00
0x20
Audio Interface Setting Register 5
0
33
0x00
0x21
Audio Interface Setting Register 6
0
34
0x00
0x22
Digital Interface Misc. Setting Register
0
35
0x00
0x23
Reserved Register
0
36
0x00
0x24
ADC Flag Register
0
37
0x00
0x25
DAC Flag Register 1
0
38
0x00
0x26
DAC Flag Register 2
0
39-41
0x00
0x27-0x29
Reserved Register
0
42
0x00
0x2A
Sticky Flag Register 1
0
43
0x00
0x2B
Interrupt Flag Register 1
0
44
0x00
0x2C
Sticky Flag Register 2
0
45
0x00
0x2D
Sticky Flag Register 3
32
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Register Map (continued)
Table 4. Summary of Register Map (continued)
Decimal
Hex
DESCRIPTION
PAGE NO.
REG. NO.
PAGE NO.
REG. NO.
0
46
0x00
0x2E
Interrupt Flag Register 2
0
47
0x00
0x2F
Interrupt Flag Register 3
0
48
0x00
0x30
INT1 Interrupt Control Register
0
49
0x00
0x31
INT2 Interrupt Control Register
0
50-51
0x00
0x32-0x33
Reserved Register
0
52
0x00
0x34
GPIO/MFP5 Control Register
0
53
0x00
0x35
DOUT/MFP2 Function Control Register
0
54
0x00
0x36
DIN/MFP1 Function Control Register
0
55
0x00
0x37
MISO/MFP4 Function Control Register
0
56
0x00
0x38
SCLK/MFP3 Function Control Register
0
57-59
0x00
0x39-0x3B
Reserved Registers
0
60
0x00
0x3C
DAC Signal Processing Block Control Register
0
61
0x00
0x3D
ADC Signal Processing Block Control Register
0
62
0x00
0x3E
Reserved Register
0
63
0x00
0x3F
DAC Channel Setup Register 1
0
64
0x00
0x40
DAC Channel Setup Register 2
0
65
0x00
0x41
Left DAC Channel Digital Volume Control Register
0
66
0x00
0x42
Right DAC Channel Digital Volume Control Register
0
67
0x00
0x43
Headset Detection Configuration Register
0
68
0x00
0x44
DRC Control Register 1
0
69
0x00
0x45
DRC Control Register 2
0
70
0x00
0x46
DRC Control Register 3
0
71
0x00
0x47
Beep Generator Register 1
0
72
0x00
0x48
Beep Generator Register 2
0
73
0x00
0x49
Beep Generator Register 3
0
74
0x00
0x4A
Beep Generator Register 4
0
75
0x00
0x4B
Beep Generator Register 5
0
76
0x00
0x4C
Beep Generator Register 6
0
77
0x00
0x4D
Beep Generator Register 7
0
78
0x00
0x4E
Beep Generator Register 8
0
79
0x00
0x4F
Beep Generator Register 9
0
80
0x00
0x50
Reserved Register
0
81
0x00
0x51
ADC Channel Setup Register
0
82
0x00
0x52
ADC Fine Gain Adjust Register
0
83
0x00
0x53
Left ADC Channel Volume Control Register
0
84
0x00
0x54
Right ADC Channel Volume Control Register
0
85
0x00
0x55
ADC Phase Adjust Register
0
86
0x00
0x56
Left Channel AGC Control Register 1
0
87
0x00
0x57
Left Channel AGC Control Register 2
0
88
0x00
0x58
Left Channel AGC Control Register 3
0
89
0x00
0x59
Left Channel AGC Control Register 4
0
90
0x00
0x5A
Left Channel AGC Control Register 5
0
91
0x00
0x5B
Left Channel AGC Control Register 6
0
92
0x00
0x5C
Left Channel AGC Control Register 7
0
93
0x00
0x5D
Left Channel AGC Control Register 8
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Register Map (continued)
Table 4. Summary of Register Map (continued)
Decimal
Hex
DESCRIPTION
PAGE NO.
REG. NO.
PAGE NO.
REG. NO.
0
94
0x00
0x5E
Right Channel AGC Control Register 1
0
95
0x00
0x5F
Right Channel AGC Control Register 2
0
96
0x00
0x60
Right Channel AGC Control Register 3
0
97
0x00
0x61
Right Channel AGC Control Register 4
0
98
0x00
0x62
Right Channel AGC Control Register 5
0
99
0x00
0x63
Right Channel AGC Control Register 6
0
100
0x00
0x64
Right Channel AGC Control Register 7
0
101
0x00
0x65
Right Channel AGC Control Register 8
0
102
0x00
0x66
DC Measurement Register 1
0
103
0x00
0x67
DC Measurement Register 2
0
104
0x00
0x68
Left Channel DC Measurement Output Register 1
0
105
0x00
0x69
Left Channel DC Measurement Output Register 2
0
106
0x00
0x6A
Left Channel DC Measurement Output Register 3
0
107
0x00
0x6B
Right Channel DC Measurement Output Register 1
0
108
0x00
0x6C
Right Channel DC Measurement Output Register 2
0
109
0x00
0x6D
Right Channel DC Measurement Output Register 3
0
110-127
0x00
0x6E-0x7F
Reserved Register
1
0
0x01
0x00
Page Select Register
1
1
0x01
0x01
Power Configuration Register 1
1
2
0x01
0x02
Power Configuration Register 2
1
3
0x01
0x03
Playback Configuration Register 1
1
4
0x01
0x04
Playback Configuration Register 2
1
5-8
0x01
0x05-0x08
Reserved Register
1
9
0x01
0x09
Output Driver Power Control Register
1
10
0x01
0x0A
Common Mode Control Register
1
11
0x01
0x0B
Over Current Protection Configuration Register
1
12
0x01
0x0C
HPL Routing Selection Register
1
13
0x01
0x0D
HPR Routing Selection Register
1
14
0x01
0x0E
LOL Routing Selection Register
1
15
0x01
0x0F
LOR Routing Selection Register
1
16
0x01
0x10
HPL Driver Gain Setting Register
1
17
0x01
0x11
HPR Driver Gain Setting Register
1
18
0x01
0x12
LOL Driver Gain Setting Register
1
19
0x01
0x13
LOR Driver Gain Setting Register
1
20
0x01
0x14
Headphone Driver Startup Control Register
1
21
0x01
0x15
Reserved Register
1
22
0x01
0x16
IN1L to HPL Volume Control Register
1
23
0x01
0x17
IN1R to HPR Volume Control Register
1
24
0x01
0x18
Mixer Amplifier Left Volume Control Register
1
25
0x01
0x19
Mixer Amplifier Right Volume Control Register
1
26-50
0x01
0x1A-0x32
Reserved Register
1
51
0x01
0x33
MICBIAS Configuration Register
1
52
0x01
0x34
Left MICPGA Positive Terminal Input Routing Configuration Register
1
53
0x01
0x35
Reserved Register
1
54
0x01
0x36
Left MICPGA Negative Terminal Input Routing Configuration Register
34
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SLAS649C – DECEMBER 2010 – REVISED NOVEMBER 2014
Register Map (continued)
Table 4. Summary of Register Map (continued)
Decimal
Hex
DESCRIPTION
PAGE NO.
REG. NO.
PAGE NO.
REG. NO.
1
55
0x01
0x37
Right MICPGA Positive Terminal Input Routing Configuration Register
1
56
0x01
0x38
Reserved Register
1
57
0x01
0x39
Right MICPGA Negative Terminal Input Routing Configuration Register
1
58
0x01
0x3A
Floating Input Configuration Register
1
59
0x01
0x3B
Left MICPGA Volume Control Register
1
60
0x01
0x3C
Right MICPGA Volume Control Register
1
61
0x01
0x3D
ADC Power Tune Configuration Register
1
62
0x01
0x3E
ADC Analog Volume Control Flag Register
1
63
0x01
0x3F
DAC Analog Gain Control Flag Register
1
64-70
0x01
0x40-0x46
Reserved Register
1
71
0x01
0x47
Analog Input Quick Charging Configuration Register
1
72-122
0x01
0x48-0x7A
Reserved Register
1
123
0x01
0x7B
Reference Power-up Configuration Register
1
124
0x01
0x7C
Charge Pump Control
1
125
0x01
0x7D
Headphone Driver Configuration
1
126-127
0x01
0x7E-0x7F
Reserved Register
8
0
0x08
0x00
Page Select Register
8
1
0x08
0x01
ADC Adaptive Filter Configuration Register
8
2-7
0x08
0x02-0x07
Reserved
8
8-127
0x08
0x08-0x7F
ADC Coefficients Buffer-A C(0:29)
9-16
0
0x09-0x10
0x00
Page Select Register
9-16
1-7
0x09-0x10
0x01-0x07
Reserved
9-16
8-127
0x09-0x10
0x08-0x7F
ADC Coefficients Buffer-A C(30:255)
26-34
0
0x1A-0x22
0x00
Page Select Register
26-34
1-7
0x1A-0x22
0x01-0x07
Reserved.
26-34
8-127
0x1A-0x22
0x08-0x7F
ADC Coefficients Buffer-B C(0:255)
44
0
0x2C
0x00
Page Select Register
44
1
0x2C
0x01
DAC Adaptive Filter Configuration Register
44
2-7
0x2C
0x02-0x07
Reserved
44
8-127
0x2C
0x08-0x7F
DAC Coefficients Buffer-A C(0:29)
45-52
0
0x2D-0x34
0x00
Page Select Register
45-52
1-7
0x2D-0x34
0x01-0x07
Reserved.
45-52
8-127
0x2D-0x34
0x08-0x7F
DAC Coefficients Buffer-A C(30:255)
62-70
0
0x3E-0x46
0x00
Page Select Register
62-70
1-7
0x3E-0x46
0x01-0x07
Reserved.
62-70
8-127
0x3E-0x46
0x08-0x7F
DAC Coefficients Buffer-B C(0:255)
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11 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
11.1 Application Information
The TLV320AIC3206 is a highly integrated stereo audio codec with flexible digital audio interface options. It
enables many different types of audio platforms having a need for stereo audio record and playback and needing
to interface with other devices in the system over a digital audio interface.
11.2 Typical Application
Figure 21 shows a typical circuit configuration for a system using theTLV320AIC3206.
Figure 21. Typical Circuit Configuration
36
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Typical Application (continued)
11.2.1 Design Requirements
11.2.1.1 Charge Pump Flying and Holding Capacitor
The TLV320AIC3206 features a built in charge-pump to generate a negative supply rail, VNEG from DVDD_CP.
This negative voltage is used by the headphone amplifier to enable driving the output signal biased around
ground potential. For proper operation of the charge pump and headphone amplifier, it is recommended that the
flying capacitor connected between FLY_P and FLY_N terminals and the holding capacitor connected between
VNEG and ground be of X7R type. It is recommended to use 2.2μF as capacitor values. Failure to use X7R type
capacitor can result in degraded performance of charge pump and headphone amplifier.
11.2.1.2 Reference Filtering Capacitor
The TLV320AIC3206 has a built-in bandgap used to generate reference voltages and currents for the device. To
achieve high SNR, the reference voltage on REF should be filtered using a 10-μF capacitor from REF terminal to
ground.
11.2.1.3
MICBIAS
The TLV320AIC3206 has a built-in bias voltage output for biasing of microphones. No intentional capacitors
should be connected directly to the MICBIAS output for filtering.
11.2.2 Detailed Design Procedures
11.2.2.1 Analog Input Connection
The analog inputs to TLV320AIC3206 should be ac-coupled to the device terminals to allow decoupling of signal
source's common mode voltage with that of TLV320AIC3206's common mode voltage. The input coupling
capacitor in combination with the selected input impedance of TLV320AIC3206 forms a high-pass filter.
Fc = 1/(2 x π x ReqCc)
Cc = 1/(2 x π x ReqFc)
(1)
(2)
For high fidelity audio recording application it is desirable to keep the cutoff frequency of the high pass filter as
low as possible. For single-ended input mode, the equivalent input resistance Req can be calculated as
Req = Rin x (1 + 2g)/(1+g)
(3)
where g is the analog PGA gain calculated in linear terms.
g = 10000 x 2floor(G/6)/Rin
(4)
where G is the analog PGA gain programmed in P1_R59-R60 (in dB) and Rin is the value of the resistor
programmed in P1_R52-R57 and assumes Rin = Rcm (as defined in P1_R52-R57).
For differential input mode, Req of the half circuit can be calculated as:
Req = Rin
(5)
where Rin is the value of the resistor programmed in P1_R52-R57, assuming symmetrical inputs.
Signal Connector
Device Analog Input
Cc
Req
Rpd
Figure 22. Analog Input Connection With Pull-down Resistor
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Typical Application (continued)
When the analog signal is connected to the system through a connector such as audio jack, it is recommended
to put a pull-down resistor on the signal as shown in Figure 22. The pulldown resistor helps keep the signal
grounded and helps improve noise immunity when no source is connected to the connector. The pulldown
resistor value should be chosen large enough to avoid loading of signal source.
Each analog input of the TLV320AIC3206 is capable of handling signal amplitude of 0.5 Vrms. If the input signal
source can drive signals higher than the maximum value, an external resistor divider network as shown in
Figure 23 should be used to attenuate the signal to less than 0.5Vrms before connecting the signal to the device.
The resistor values of the network should be chosen to provide desired attenuation as well as Equation 6.
R1|| R2
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