TLV320AIC3254IRHBR

TLV320AIC3254 Ultra Low Power Stereo Audio Codec With Embedded miniDSP www.ti.com SLAS549A – SEPTEMBER 2008 – REVISED OCTOBER 2008 1 Introduction 1.1 Features 1.2 • • • • • • • • • • • • • • • • • • • • • • • • • Stereo Audio DAC with 100dB SNR 4.1mW Stereo 48ksps DAC Playback Stereo Audio ADC with 93dB SNR 6.1mW Stereo 48ksps ADC Record PowerTune™ Extensive Signal Processing Options Embedded miniDSP Six Single-Ended or 3 Fully-Differential Analog Inputs Stereo Analog and Digital Microphone Inputs Stereo Headphone Outputs Stereo Line Outputs Very Low-Noise PGA Low Power Analog Bypass Mode Programmable Microphone Bias Programmable PLL Integrated LDO 5 mm x 5 mm 32-pin QFN Package Applications Portable Navigation Devices (PND) Portable Media Player (PMP) Mobile Handsets Communication Portable Computing Acoustic Echo Cancellation (AEC) Active Noise Cancellation (ANC) Advanced DSP algorithms 1.3 Description The TLV320AIC3254 (sometimes referred to as the AIC3254) is a flexible, low-power, low-voltage stereo audio codec with programmable inputs and outputs, PowerTune capabilities, fully programmable miniDSP, fixed predefined and parameterizable signal processing blocks, integrated PLL, integrated LDOs and flexible digital interfaces. IN1_L IN2_L IN3_L 0…+47.5 dB + Left ADC tpl + ´ AGC DRC ADC Signal Proc. DAC Signal Proc. Vol . Ctrl -72...0dB Left DAC ´ -6...+29dB HPL + 1dB steps Gain Adj. 0.5 dB steps -6...+29dB -30...0 dB LOL + Data Interface miniDSP 1dB steps miniDSP -6...+29dB -30...0 dB LOR + 1dB steps 0… +47.5 dB + Gain Adj. Right ADC IN3_R + tpr ´ 0.5 dB steps IN2_R ADC Signal Proc. DAC Signal Proc. AGC DRC -6...+29dB Right DAC ´ Vol . Ctrl HPR + 1dB steps -72...0dB IN1_R SPI_Select SPI / I2C Control Block Reset Digital Interrupt Secondary Mic. Ctrl I2S IF PLL Primary I2S Interface HPVdd MicBias Mic Bias ALDO Ref Ref DLDO Supplies Pin Muxing/ Clock Routing BCLK WCLK DIN DOUT GPIO MCLK SCLK MISO SDA/MOSI SCL/SSZ IOVss DVss AVss IOVdd DVdd AVdd LDO Select LDO in Figure 1-1. Simplified Block Diagram Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this document. PowerTune is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008–2008, Texas Instruments Incorporated TLV320AIC3254 Ultra Low Power Stereo Audio Codec With Embedded miniDSP SLAS549A – SEPTEMBER 2008 – REVISED OCTOBER 2008 1.4 www.ti.com Detailed Description The TLV320AIC3254 features two fully programmable miniDSP cores that support application-specific algorithms in the record and/or the playback path of the device. The miniDSP cores are fully software controlled. Target algorithms, like active noise cancellation, acoustic echo cancellation or advanced DSP filtering are loaded into the device after power-up. Extensive Register based control of power, input/output channel configuration, gains, effects, pin-multiplexing and clocks is included, allowing the device to be precisely targeted to its application. Combined with the advanced PowerTune technology, the device can cover operations from 8 kHz mono voice playback to audio stereo 192kHz DAC playback, making it ideal for portable battery-powered audio and telephony applications. The record path of the TLV320AIC3254 covers operations from 8kHz mono to 192kHz stereo recording, and contains programmable input channel configurations covering single-ended and differential setups, as well as floating or mixing input signals. It also includes a digitally-controlled stereo microphone preamplifier and integrated microphone bias. Digital signal processing blocks can remove audible noise that may be introduced by mechanical coupling, e.g. optical zooming in a digital camera. The playback path offers signal-processing blocks for filtering and effects, and supports flexible mixing of DAC and analog input signals as well as programmable volume controls. The playback path contains two high-power output drivers as well as two fully-differential outputs. The high-power outputs can be configured in multiple ways, including stereo, mono BTL and Class D. The integrated PowerTune technology allows the device to be tuned to just the right power-performance trade-off. Mobile applications frequently have multiple use cases requiring very low power operation while being used in a mobile environment. When used in a docked environment power consumption typically is less of a concern, while minimizing noise is important. With PowerTune, the TLV320AIC3254 addresses both cases. The voltage supply range for the TLV320AIC3254 for analog is 1.5V–1.95V, and for digital it is 1.26V–1.95V. To ease system-level design, LDOs are integrated to generate the appropriate analog or digital supply from input voltages ranging from 1.8V to 3.6V. Digital I/O voltages are supported in the range of 1.1V–3.6V. The required internal clock of the TLV320AIC3254 can be derived from multiple sources, including the MCLK pin, the BCLK pin, the GPIO pin or the output of the internal PLL, where the input to the PLL again can be derived from the MCLK pin, the BCLK or GPIO pins. Although using the PLL ensures the availability of a suitable clock signal, it is not recommended for the lowest power settings. The PLL is highly programmable and can accept available input clocks in the range of 512kHz to 50MHz. The device is available in the 5-mm × 5-mm, 32-pin QFN package. 2 Introduction Submit Documentation Feedback TLV320AIC3254 Ultra Low Power Stereo Audio Codec With Embedded miniDSP www.ti.com SLAS549A – SEPTEMBER 2008 – REVISED OCTOBER 2008 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 2 Package and Signal Descriptions 2.1 Packaging/Ordering Information PRODUCT PACKAGE PACKAGE DESIGNATOR OPERATING TEMPERATURE RANGE TLV320AIC3254 QFN RHB –40°C to 85°C ORDERING NUMBER TRANSPORT MEDIA, QUANTITY TLV320AIC3254IRHBT Tape and Reel, 250 TLV320AIC3254IRHBR Tape and Reel, 3000 8 1 GPIO/MFP5 (32) SCLK/MFP3 IOVSS OVIDD DIN/MFP1 DOUT/MFP2 WCLK BCLK MCLK (1) 2.2 Pin Assignments 32 9 SCL/SSZ SDA/MOSI RESET LDO_SELECT MISO/MFP4 DVDD SPI_SELECT DVSS IN1_L HPR IN1_R LDOIN IN2_L HPL 25 16 24 IN2_R 17 AVSS MICBIAS REF IN3_L IN3_R LOR LOL AVDD Figure 2-1. QFN (RHB) Package, Bottom View Submit Documentation Feedback Package and Signal Descriptions 3 TLV320AIC3254 Ultra Low Power Stereo Audio Codec With Embedded miniDSP SLAS549A – SEPTEMBER 2008 – REVISED OCTOBER 2008 www.ti.com Table 2-1. TERMINAL FUNCTIONS TERMINAL NAME TYPE 1 MCLK I DESCRIPTION 2 BCLK IO Audio serial data bus (primary) bit clock 3 WCLK IO Audio serial data bus (primary) word clock 4 DIN I Master Clock Input Primary function Audio serial data bus data input MFP1 Secondary function Audio serial data bus (secondary) bit clock input Audio serial data bus (secondary) word clock input Digital Microphone Input Clock Input General Purpose Input 5 DOUT O Primary Audio serial data bus data output MFP2 Secondary General Purpose Output Clock Output INT1 Output INT2 Output Audio serial data bus (secondary) bit clock output Audio serial data bus (secondary) word clock output 6 IOVDD Power I/O voltage supply 1.1V – 3.6V 7 IOVSS Ground I/O ground supply 8 SCLK I Primary (SPI_Select = 1) SPI serial clock MFP3 Secondary: (SPI_Select = 0) Headset-detect input Digital microphone input Audio serial data bus (secondary) Audio serial data bus (secondary) Audio serial data bus (secondary) Audio serial data bus (secondary) General Purpose Input bit clock input DAC/common word clock input ADC word clock input data input 9 SCL/ SSZ I I2C interface serial clock (SPI_Select = 0) SPI interface mode chip-select signal (SPI_Select = 1) 10 SDA/ MOSI I I2C interface mode serial data input (SPI_Select = 0) SPI interface mode serial data input (SPI_Select = 1) 11 MISO O Primary (SPI_Select = 1) Serial data output MFP4 Secondary (SPI_Select = 0) General purpose output CLKOUT output INT1 output INT2 output Audio serial data bus (primary) ADC word clock output Digital microphone clock output Audio serial data bus (secondary) data output Audio serial data bus (secondary) bit clock output Audio serial data bus (secondary) word clock output 12 4 SPI_ SELECT Package and Signal Descriptions I Control mode select pin ( 1 = SPI, 0 = I2C ) Submit Documentation Feedback TLV320AIC3254 Ultra Low Power Stereo Audio Codec With Embedded miniDSP www.ti.com SLAS549A – SEPTEMBER 2008 – REVISED OCTOBER 2008 Table 2-1. TERMINAL FUNCTIONS (continued) TERMINAL NAME TYPE 13 IN1_L I Multifunction Analog Input, or Single-ended configuration: MIC 1 or Line 1 left or Differential configuration: MIC or Line right, negative 14 IN1_R I Multifunction Analog Input, or Single-ended configuration: MIC 1 or Line 1 right or Differential configuration: MIC or Line right, positive 15 IN2_L I Multifunction Analog Input, or Single-ended configuration: MIC 2 or Line 2 right or Differential configuration: MIC or Line left, positive 16 IN2_R I Multifunction Analog Input, or Single-ended configuration: MIC 2 or Line 2 right or Differential configuration: MIC or Line left, negative 17 AVss Ground 18 REF O Reference voltage output for filtering 19 MICBIAS O Microphone bias voltage output 20 IN3_L I Multifunction Analog Input, or Single-ended configuration: MIC3 or Line 3 left, or Differential configuration: MIC or Line left, positive, or Differential configuration: MIC or Line right, negative 21 IN3_R I Multifunction Analog Input, or Single-ended configuration: MIC3 or Line 3 right, or Differential configuration: MIC or Line left, negative, or Differential configuration: MIC or Line right, positive 22 LOL O Left line output Right line output 23 LOR O 24 AVdd Power DESCRIPTION Analog ground supply Analog voltage supply 1.5V–1.95V Input when A-LDO disabled, Filtering output when A-LDO enabled 25 HPL O 26 LDOIN/ HPVDD Power Left high power output driver 27 HPR O 28 DVss Ground Digital Ground and Chip-substrate 29 DVdd Power If LDO_SELECT Pin = 0 (D-LDO disabled) LDO Input supply and Headphone Power supply 1.9V– 3.6V Right high power output driver Digital voltage supply 1.26V – 1.95V If LDO_SELECT Pin = 1 (D-LDO enabled) Digital voltage supply filtering output 30 LDO_ SELECT I connect to DVss. 31 RESET I Reset (active low) 32 GPIO I Primary General Purpose digital IO MFP5 Secondary CLKOUT Output INT1 Output INT2 Output Audio serial data bus ADC word clock output Audio serial data bus (secondary) bit clock output Audio serial data bus (secondary) word clock output Digital microphone clock output Submit Documentation Feedback Package and Signal Descriptions 5 TLV320AIC3254 Ultra Low Power Stereo Audio Codec With Embedded miniDSP SLAS549A – SEPTEMBER 2008 – REVISED OCTOBER 2008 www.ti.com 3 Electrical Specifications 3.1 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) VALUE UNIT AVdd to AVss –0.3 to 2.2 V DVdd to DVss –0.3 to 2.2 V IOVDD to IOVSS –0.3 to 3.9 V LDOIN to AVss –0.3 to 3.9 V Digital Input voltage to ground –0.3 to IOVDD + 0.3 V Analog input voltage to ground –0.3 to AVdd + 0.3 V Operating temperature range –40 to 85 °C Storage temperature range –55 to 125 °C 105 °C Junction temperature (TJ Max) (TJ Max – TA)/ θJA W θJA Thermal impedance 35 C/W Infrared (15 sec) 260 °C QFN package (RHB) QFN package (RHB) Power dissipation (with thermal pad soldered to board) Lead Temperature (1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 3.2 RECOMMENDED OPERATING CONDITIONS MIN LDOIN Power Supply Voltage Range Referenced to AVss (1) AVdd 1.5 Referenced to IOVSS (1) IOVDD DVdd (2) Referenced to DVss PLL Input Frequency MCLK Master Clock Frequency SCL SCL Clock Frequency LOL, LOR Stereo line output load resistance HPL, HPR Stereo headphone output load resistance Headphone output load resistance CLout Digital output load capacitance TOPR Operating Temperature Range (1) (2) 6 (1) NOM 1.9 1.8 1.1 1.26 1.8 MAX UNIT 3.6 V 1.95 V 3.6 V 1.95 V Clock divider uses fractional divide (D > 0), P=1, DVdd ≥ 1.65V (Refer to Table 5-23) 10 20 MHz Clock divider uses integer divide (D = 0), P=1, DVdd ≥ 1.65V (Refer to Table 5-23) 0.512 20 MHz MCLK; Master Clock Frequency; DVdd ≥ 1.65V 50 MHz MCLK; Master Clock Frequency; DVdd ≥ 1.26V 25 400 kHz 0.6 10 kΩ Single-ended configuration 14.4 16 Ω Differential configuration 24.4 32 Ω 10 pF –40 85 °C All grounds on board are tied together, so they should not differ in voltage by more than 0.2V max, for any combination of ground signals. At DVdd values lower than 1.65V, the PLL does not function. Please see Table 5-23 for details on maximum clock frequencies. Electrical Specifications Submit Documentation Feedback TLV320AIC3254 Ultra Low Power Stereo Audio Codec With Embedded miniDSP www.ti.com 3.3 SLAS549A – SEPTEMBER 2008 – REVISED OCTOBER 2008 ELECTRICAL CHARACTERISTICS At 25°C, AVdd, DVdd, IOVDD = +1.8V, LDO_in = 3.3V, AVdd LDO disabled, fs (Audio) = 48kHz, Cref = 10 µF on REF PIN, PLL disabled unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT AUDIO ADC (1) (2) Input signal level (0dB) Single-ended, CM = 0.9V Device Setup 1kHz sine wave input Single-ended Configuration IN1R to Right ADC and IN1L to Left ADC, Rin = 20K, fs = 48kHz, AOSR = 128, MCLK = 256*fs, PLL Disabled; AGC = OFF, Channel Gain = 0dB, Processing Block = PRB_R1, Power Tune = PTM_R4 Inputs ac-shorted to ground SNR Signal-to-noise ratio, A-weighted (1) DR Dynamic range A-weighted (1) THD+N (2) (2) Total Harmonic Distortion plus Noise IN2R, IN3R routed to Right ADC and ac-shorted to ground IN2L, IN3L routed to Left ADC and ac-shorted to ground 0.5 80 VRMS 93 93 –60dB full-scale, 1-kHz input signal 92 –3 dB full-scale, 1-kHz input signal –85 IN2R,IN3R routed to Right ADC IN2L, IN3L routed to Left ADC –3dB full-scale, 1-kHz input signal –85 dB dB –70 dB AUDIO ADC SNR Input signal level (0dB) Single-ended, CM=0.75V, AVdd = 1.5V Device Setup 1kHz sine wave input Single-ended Configuration IN1R, IN2R, IN3R routed to Right ADC IN1L, IN2L, IN3L routed to Left ADC Rin = 20K, fs = 48kHz, AOSR=128, MCLK = 256* fs, PLL Disabled, AGC = OFF, Channel Gain = 0dB, Processing Block = PRB_R1 Power Tune = PTM_R4 Signal-to-noise ratio, A-weighted (1) (2) (1) (2) DR Dynamic range A-weighted THD+N Total Harmonic Distortion plus Noise 0.375 VRMS Inputs ac-shorted to ground 91 dB –60dB full-scale, 1-kHz input signal 90 dB –3dB full-scale, 1-kHz input signal –80 dB 10 mV 2 µVRMS AUDIO ADC ICN (1) (2) Input signal level (0dB) Differential Input, CM=0.9V Device Setup 1kHz sine wave input Differential configuration IN1L and IN1R routed to Right ADC IN2L and IN2R routed to Left ADC Rin =10K, fs =48kHz, AOSR=128 MCLK = 256* fs PLL Disabled AGC = OFF, Channel Gain=40dB Processing Block = PRB_R1, Power Tune = PTM_R4 Idle-Channel Noise, A-weighted (1) (2) Inputs ac-shorted to ground, input referred noise Ratio of output level with 1-kHz full-scale sine wave input, to the output level with the inputs short circuited, measured A-weighted over a 20-Hz to 20-kHz bandwidth using an audio analyzer. All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes out-of-band noise, which, although not audible, may affect dynamic specification values Submit Documentation Feedback Electrical Specifications 7 TLV320AIC3254 Ultra Low Power Stereo Audio Codec With Embedded miniDSP SLAS549A – SEPTEMBER 2008 – REVISED OCTOBER 2008 www.ti.com ELECTRICAL CHARACTERISTICS (continued) At 25°C, AVdd, DVdd, IOVDD = +1.8V, LDO_in = 3.3V, AVdd LDO disabled, fs (Audio) = 48kHz, Cref = 10 µF on REF PIN, PLL disabled unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT AUDIO ADC Gain Error 1kHz sine wave input Single-ended configuration Rin = 20K fs = 48kHz, AOSR=128, MCLK = 256* fs, PLL Disabled AGC = OFF, Channel Gain=0dB Processing Block = PRB_R1, Power Tune = PTM_R4, CM=0.9V –0.05 dB 108 dB Input Channel Separation 1kHz sine wave input at -3dBFS Single-ended configuration IN1L routed to Left ADC IN1R routed to Right ADC, Rin = 20K AGC = OFF, AOSR = 128, Channel Gain=0dB, CM=0.9V 1kHz sine wave input at –3dBFS on IN2L, IN2L internally not routed. IN1L routed to Left ADC ac-coupled to ground 115 dB Input Pin Crosstalk 55 dB 1kHz sine wave input at –3dBFS on IN2R, IN2R internally not routed. IN1R routed to Right ADC ac-coupled to ground Single-ended configuration Rin = 20K, AOSR=128 Channel, Gain=0dB, CM=0.9V PSRR 217Hz, 100mVpp signal on AVdd, Single-ended configuration, Rin=20K, Channel Gain=0dB; CM=0.9V Single-Ended, Rin = 10K, PGA gain set to 0dB 0 dB 47.5 dB –6 dB Single-Ended, Rin = 20K, PGA gain set to 47.5dB 41.5 dB Single-Ended, Rin = 40K, PGA gain set to 0dB –12 dB Single-Ended, Rin = 40K, PGA gain set to 47.5dB 35.5 dB 0.5 dB Single-Ended, Rin = 10K, PGA gain set to 47.5dB ADC programmable gain amplifier gain ADC programmable gain amplifier step size 8 Electrical Specifications Single-Ended, Rin = 20K, PGA gain set to 0dB 1-kHz tone Submit Documentation Feedback TLV320AIC3254 Ultra Low Power Stereo Audio Codec With Embedded miniDSP www.ti.com SLAS549A – SEPTEMBER 2008 – REVISED OCTOBER 2008 ELECTRICAL CHARACTERISTICS (continued) At 25°C, AVdd, DVdd, IOVDD = +1.8V, LDO_in = 3.3V, AVdd LDO disabled, fs (Audio) = 48kHz, Cref = 10 µF on REF PIN, PLL disabled unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG BYPASS TO HEADPHONE AMPLIFIER, DIRECT MODE Device Setup Load = 16Ω (single-ended), 50pF; Input and Output CM=0.9V; Headphone Output on LDOIN Supply; IN1L routed to HPL and IN1R routed to HPR; Channel Gain=0dB Gain Error THD –0.8 Noise, A-weighted (1) Idle Channel, IN1L and IN1R ac-shorted to ground Total Harmonic Distortion 446mVrms, 1-kHz input signal 3 dB µVRMS –89 dB ANALOG BYPASS TO LINE-OUT AMPLIFIER, PGA MODE Device Setup Load = 10KOhm (single-ended), 56pF; Input and Output CM=0.9V; LINE Output on LDOIN Supply; IN1L routed to ADCPGA_L and IN1R routed to ADCPGA_R; Rin = 20k ADCPGA_L routed to LOL and ADCPGA_R routed to LOR; Channel Gain = 0dB Gain Error 0.6 Idle Channel, IN1L and IN1R ac-shorted to ground Noise, A-weighted (1) Channel Gain=40dB, Input Signal (0dB) = 5mVrms Inputs ac-shorted to ground, Input Referred dB 7 µVRMS 3.4 µVRMS 1.25 V 1.7 V MICROPHONE BIAS Bias voltage Bias voltage CM=0.9V, LDOin = 3.3V Micbias Mode 0, Connect to AVdd or LDOin Micbias Mode 1, Connect to LDOin Micbias Mode 2, Connect to LDOin 2.5 V Micbias Mode 3, Connect to AVdd AVdd V Micbias Mode 3, Connect to LDOin LDOin V Micbias Mode 0, Connect to AVdd or LDOin 1.04 V Micbias Mode 1, Connect to AVdd or LDOin 1.425 V Micbias Mode 2, Connect to LDOin 2.075 V Micbias Mode 3, Connect to AVdd AVdd V Micbias Mode 3, Connect to LDOin LDOin V CM=0.75V, LDOin = 3.3V Output Noise CM=0.9V, Micbias Mode 2, A-weighted, 20Hz to 20kHz bandwidth, Current load = 0mA. Current Sourcing Micbias Mode 2, Connect to LDOin Inline Resistance (1) 10 µVRMS 3 Micbias Mode 3, Connect to AVdd 140 Micbias Mode 3, Connect to LDOin 87 mA Ω All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes out-of-band noise, which, although not audible, may affect dynamic specification values Submit Documentation Feedback Electrical Specifications 9 TLV320AIC3254 Ultra Low Power Stereo Audio Codec With Embedded miniDSP SLAS549A – SEPTEMBER 2008 – REVISED OCTOBER 2008 www.ti.com ELECTRICAL CHARACTERISTICS (continued) At 25°C, AVdd, DVdd, IOVDD = +1.8V, LDO_in = 3.3V, AVdd LDO disabled, fs (Audio) = 48kHz, Cref = 10 µF on REF PIN, PLL disabled unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 0.5 VRMS 87 100 dB –60dB 1kHz input full-scale signal, Word length=20 bits 100 dB AUDIO DAC – STEREO SINGLE-ENDED LINE OUTPUT Load = 10 kΩ (single-ended), 56pF Line Output on AVdd Supply Input & Output CM=0.9V DOSR = 128, MCLK=256* fs, Channel Gain = 0dB, word length = 16 bits, Processing Block = PRB_P1, Power Tune = PTM_P3 Device Setup Full scale output voltage (0dB) SNR Signal-to-noise ratio A-weighted (1) (2) DR Dynamic range, A-weighted THD+N Total Harmonic Distortion plus Noise –3dB full-scale, 1-kHz input signal –83 DAC Gain Error 0 dB, 1kHz input full scale signal 0.3 dB DAC Mute Attenuation Mute 119 dB DAC channel separation –1 dB, 1kHz signal, between left and right HP out 113 dB 100mVpp, 1kHz signal applied to AVdd 73 dB 100mVpp, 217Hz signal applied to AVdd 77 dB (1) (2) DAC PSRR All zeros fed to DAC input –70 dB AUDIO DAC – STEREO SINGLE-ENDED LINE OUTPUT Load = 10 kΩ (single-ended), 56pF Line Output on AVdd Supply Input & Output CM=0.75V; AVdd=1.5V DOSR = 128 MCLK=256* fs Channel Gain = –2dB word length = 20-bits Processing Block = PRB_P1 Power Tune = PTM_P4 Device Setup Full scale output voltage (0dB) 0.375 (1) (2) SNR Signal-to-noise ratio, A-weighted DR Dynamic range, A-weighted THD+N Total Harmonic Distortion plus Noise (1) (2) VRMS All zeros fed to DAC input 99 dB –60dB 1 kHz input full-scale signal 97 dB –1 dB full-scale, 1-kHz input signal –85 dB AUDIO DAC – STEREO SINGLE-ENDED HEADPHONE OUTPUT Load = 16Ω (single-ended), 50pF Headphone Output on AVdd Supply, Input & Output CM=0.9V, DOSR = 128, MCLK=256* fs, Channel Gain=0dB word length = 16 bits; Processing Block = PRB_P1 Power Tune = PTM_P3 Device Setup Full scale output voltage (0dB) 0.5 VRMS dB 99 dB Signal-to-noise ratio, A-weighted (1) DR Dynamic range, A-weighted THD+N Total Harmonic Distortion plus Noise –3dB full-scale, 1-kHz input signal –83 DAC Gain Error 0dB, 1kHz input full scale signal –0.3 dB DAC Mute Attenuation Mute 122 dB DAC channel separation –1dB, 1kHz signal, between left and right HP out 110 dB 100mVpp, 1kHz signal applied to AVdd 73 dB 100mVpp, 217Hz signal applied to AVdd 78 dB DAC PSRR (1) (2) 10 (2) 100 SNR (1) (2) All zeros fed to DAC input –60dB 1kHz input full-scale signal, Word Length = 20 bits, Power Tune = PTM_P4 87 –70 dB Ratio of output level with 1-kHz full-scale sine wave input, to the output level with the inputs short circuited, measured A-weighted over a 20-Hz to 20-kHz bandwidth using an audio analyzer. All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes out-of-band noise, which, although not audible, may affect dynamic specification values Electrical Specifications Submit Documentation Feedback TLV320AIC3254 Ultra Low Power Stereo Audio Codec With Embedded miniDSP www.ti.com SLAS549A – SEPTEMBER 2008 – REVISED OCTOBER 2008 ELECTRICAL CHARACTERISTICS (continued) At 25°C, AVdd, DVdd, IOVDD = +1.8V, LDO_in = 3.3V, AVdd LDO disabled, fs (Audio) = 48kHz, Cref = 10 µF on REF PIN, PLL disabled unless otherwise noted. PARAMETER TEST CONDITIONS Power Delivered MIN TYP RL=16Ω, Output Stage on AVdd = 1.8V THDN < 1%, Input CM=0.9V, Output CM=0.9V 15 RL=16 Ω Output Stage on LDOIN = 3.3V, THDN < 1% Input CM=0.9V, Output CM=1.65V 64 MAX UNIT mW AUDIO DAC – STEREO SINGLE-ENDED HEADPHONE OUTPUT Load = 16Ω (single-ended), 50pF, Headphone Output on AVdd Supply, Input & Output CM=0.75V; AVdd=1.5V, DOSR = 128, MCLK=256* fs, Channel Gain = –2dB, word length=20-bits; Processing Block = PRB_P1, Power Tune = PTM_P4 Device Setup Full scale output voltage (0dB) 0.375 SNR Signal-to-noise ratio, A-weighted (1) (2) DR Dynamic range, A-weighted THD+N Total Harmonic Distortion plus Noise (1) (2) VRMS All zeros fed to DAC input 99 dB -60dB 1 kHz input full-scale signal 98 dB –1dB full-scale, 1-kHz input signal –83 dB 1778 mVRMS AUDIO DAC – MONO DIFFERENTIAL HEADPHONE OUTPUT Load = 32 Ω (differential), 50pF, Headphone Output on LDOIN Supply Input CM = 0.75V, Output CM=1.5V, AVdd=1.8V, LDOIN=3.0V, DOSR = 128 MCLK=256* fs, Channel (headphone driver) Gain = 5dB for full scale output signal, word length=16-bits, Processing Block = PRB_P1, Power Tune = PTM_P3 Device Setup Full scale output voltage (0dB) SNR Signal-to-noise ratio, A-weighted (1) DR Dynamic range, A-weighted THD Total Harmonic Distortion (2) All zeros fed to DAC input 98 dB –60dB 1kHz input full-scale signal 96 dB –3dB full-scale, 1-kHz input signal –82 dB RL=32Ω, Output Stage on LDOIN = 3.3V, THDN < 1%, Input CM=0.9V, Output CM=1.65V 136 mW RL=32Ω Output Stage on LDOIN = 3.0V, THDN < 1% Input CM=0.9V, Output CM=1.5V 114 mW LDOMode = 1, LDOin > 1.95V 1.67 LDOMode = 0, LDOin > 2.0V 1.72 LDOMode = 2, LDOin > 2.05V 1.77 ±2 % Load Regulation Load current range 0 to 50mA 15 mV Line Regulation Input Supply Range 1.9V to 3.6V 5 mV 60 µA LDOMode = 1, LDOin > 1.95V 1.67 V LDOMode = 0, LDOin > 2.0V 1.72 LDOMode = 2, LDOin > 2.05V 1.77 ±2 % Load Regulation Load current range 0 to 50mA 15 mV Line Regulation Input Supply Range 1.9V to 3.6V 5 mV 60 µA (1) (2) Power Delivered LOW DROPOUT REGULATOR (AVdd) Output Voltage Output Voltage Accuracy Decoupling Capacitor µF 1 Bias Current V LOW DROPOUT REGULATOR (DVdd) Output Voltage Output Voltage Accuracy Decoupling Capacitor Bias Current Submit Documentation Feedback µF 1 Electrical Specifications 11 TLV320AIC3254 Ultra Low Power Stereo Audio Codec With Embedded miniDSP SLAS549A – SEPTEMBER 2008 – REVISED OCTOBER 2008 www.ti.com ELECTRICAL CHARACTERISTICS (continued) At 25°C, AVdd, DVdd, IOVDD = +1.8V, LDO_in = 3.3V, AVdd LDO disabled, fs (Audio) = 48kHz, Cref = 10 µF on REF PIN, PLL disabled unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT REFERENCE Reference Voltage Settings Reference Noise CMMode = 0 (0.9V) 0.9 CMMode = 1 (0.75V) 0.75 CM=0.9V, A-weighted, 20Hz to 20kHz bandwidth, Cref = 10µF Decoupling Capacitor V µVRMS 1 1 Bias Current 10 µF 120 µA miniDSP (3) Maximum miniDSP clock frequency - ADC DVdd = 1.65V 55.3 MHz Maximum miniDSP clock frequency - DAC DVdd = 1.65V 55.3 MHz I(DVdd) 0.9 µA I(AVdd) SDA Controlled by Master (S) => SDA Controlled by Slave Figure 5-54. I2C Write SCL DA(6) SDA Start (M) DA(0) 7-bit Device Address (M) RA(7) Write (M) Slave Ack (S) DA(6) RA(0) 8-bit Register Address (M) Slave Ack (S) Repeat Start (M) DA(0) 7-bit Device Address (M) D(7) Read (M) Slave Ack (S) 8-bit Register Data (S) D(0) Master No Ack (M) Stop (M) (M) => SDA Controlled by Master (S) => SDA Controlled by Slave Figure 5-55. I2C Read In the case of an I2C register write, if the master does not issue a STOP condition, then the device enters auto-increment mode. So in the next eight clocks, the data on SDA is treated as data for the next incremental register. Similarly, in the case of an I2C register read, after the device has sent out the 8-bit data from the addressed register, if the master issues a ACKNOWLEDGE, the slave takes over control of SDA bus and transmit for the next 8 clocks the data of the next incremental register. 5.18.2.2 SPI DIGITAL INTERFACE In the SPI control mode, the TLV320AIC3254 uses the pins SCL/SSZ=SSZ, SCLK=SCLK, MISO=MISO, SDA/MOSI=MOSI as a standard SPI port with clock polarity setting of 0 (typical microprocessor SPI control bit CPOL = 0). The SPI port allows full-duplex, synchronous, serial communication between a host processor (the master) and peripheral devices (slaves). The SPI master (in this case, the host processor) generates the synchronizing clock (driven onto SCLK) and initiates transmissions. The SPI slave devices (such as the TLV320AIC3254) depend on a master to start and synchronize transmissions. A transmission begins when initiated by an SPI master. The byte from the SPI master begins shifting in on the slave MOSI pin under the control of the master serial clock (driven onto SCLK). As the byte shifts in on the MOSI pin, a byte shifts out on the MISO pin to the master shift register. The TLV320AIC3254 interface is designed so that with a clock-phase bit setting of 1 (typical microprocessor SPI control bit CPHA = 1), the master begins driving its MOSI pin and the slave begins driving its MISO pin on the first serial clock edge. The SSZ pin can remain low between transmissions; however, the TLV320AIC3254 only interprets the first 8 bits transmitted after the falling edge of SSZ as a command byte, and the next 8 bits as a data byte only if writing to a register. Reserved register bits should be written to their default values. The TLV320AIC3254 is entirely controlled by registers. Reading and writing these registers is accomplished by an 8-bit command sent to the MOSI pin of the part prior to the data for that register. The command is structured as shown in Section 5.18.2.3. The first 7 bits specify the register address which is being written or read, from 0 to 127 (decimal). The command word ends with an R/W bit, which specifies the direction of data flow on the serial bus. In the case of a register write, the R/W bit should be set to 0. A second byte of data is sent to the MOSI pin and contains the data to be written to the register. Reading of registers is accomplished in similar fashion. The 8-bit command word sends the 7-bit register address, followed by R/W bit = 1 to signify a register read is occurring. The 8-bit register data is then clocked out of the part on the MISO pin during the second 8 SCLK clocks in the frame. Submit Documentation Feedback Application Information 93 TLV320AIC3254 Ultra Low Power Stereo Audio Codec With Embedded miniDSP SLAS549A – SEPTEMBER 2008 – REVISED OCTOBER 2008 www.ti.com Table 5.18.2.3. COMMAND WORD Bit 7 ADDR(6) Bit 6 ADDR(5) Bit 5 ADDR(4) Bit 4 ADDR(3) Bit 3 ADDR(2) Bit 2 ADDR(1) Bit 1 ADDR(0) Bit 0 R/WZ SSZ SCLK MOSI A6 A5 A0 D7 D6 D1 D0 MISO Figure 5-56. SPI Timing Diagram for Register Write SSZ SCLK MOSI MISO A6 A5 A0 D7 D6 D1 D0 D7 D6 D1 D0 Figure 5-57. SPI Timing Diagram for Register Read 5.19 POWER The TLV320AIC3254 has four power-supply connections which allow various optimizations for low system power. The four supply pins are LDOin, DVdd, AVdd and IOVDD. • IOVdd - The IOVdd pin supplies the digital IO cells of the device. The voltage of IOVdd can range from 1.1 to 3.6V and is determined by the digital IO voltage of the rest of the system. • DVdd - This pin is either a supply input to the device, or if the internal LDO is used it is used to connect an external capacitor. It supplies the digital core of the device. Lower DVdd voltages cause lower power dissipation. If efficient switched-mode power supplies are used in the system, system power can be optimized using low DVdd voltages. The device will offer full functionality up to the highest specified clock frequencies for DVdd values of 1.65 to 1.95V. • AVdd - This pin is either a supply input to the device, or if the internal LDO is used it is used to connect an external capacitor. It supplies the analog core of the device. The analog core voltage (AVdd) may be in the range of 1.5 to 1.95V for specified performance. For AVdd voltages above 1.8V, the internal common mode voltage can be set to 0.9V (Pg 1, Reg 10, D(6)=0, default) resulting in 500mVrms full-scale voltage internally. For AVdd voltages below 1.8V, the internal common mode voltage should be set to 0.75V (Pg 1, Reg 10, D(6)=1), resulting in 375mVrms internal full scale voltage. At powerup, AVDD is weakly connected to DVDD. This coarse AVDD generation must be turned off by writing Pg 1, Reg 1, D(3) = 1 at the time AVDD is applied, either from internal LDO or through external LDO. • LDOin - The LDOin pin serves two main functions. It serves as supply to internal LDOs as well as to the analog-output amplifiers of the device. The LDOin voltage can range from 1.9V to 3.6V. In conjunction with the two internal LDOs for AVdd and DVdd the device can run from a single supply. 94 Application Information Submit Documentation Feedback TLV320AIC3254 Ultra Low Power Stereo Audio Codec With Embedded miniDSP www.ti.com SLAS549A – SEPTEMBER 2008 – REVISED OCTOBER 2008 For cases where high output voltages from the line out amplifiers (1Vrms) or high output power from the headphone amplifier is required, the LDOin voltage is used as a supply. 5.19.1 System Level Considerations While there is flexibility in supplying the device through multiple options of power supplies, care must be taken to stay within safe areas when going to standby and shutdown modes. In summary, the lowest shutdown current is achieved when all supplies to the device are turned off, implying that all settings must be reapplied to the device after bringing the power back up. In order to retain settings in the device, the DVdd voltage and either internally or externally the AVdd voltage also must be maintained. In this case the TLV320AIC3254 exhibits shutdown currents of below 1µA.(If DVdd is generated by internal LDO, add 50µA) 5.19.1.1 Supply from single voltage rail (1.9 to 3.6V) The device can be powered directly from a single 3.3V rail through the LDOin pin. During operation the DVdd LDO is activated via the LDO_select pin, and the AVdd LDO is activated via control registers (Pg 1, Reg 2, D(0)=1). 5.19.1.1.1 Standby Mode (3.3V operation) To put the device in standby mode, the AVdd and DVdd LDOs as well as the Reference Block (Pg 1, Reg 123, D(2:0) = 101) must stay on, and all other blocks powered down. This results in a standby current of approximately 180µA. In standby mode, the device responds quickly to playback requests. 5.19.1.1.2 Sleep Mode (3.3V operation) In this mode all settings and memory content of the device are retained. To put the device into sleep mode, the DVdd LDO must remain powered up (LDO_select pin), the AVdd LDO must be powered down (Pg 1, Reg 2, D(0)=0), the crude AVdd generation must be turned on (Pg 1, Reg 1, D(3)=0) and the analog blocks must be powered down (Pg 1, Reg 2, D(3)=1). The sleep-mode power consumption is approximately 50µA 5.19.1.1.3 Shutdown Mode To shutdown the device, the external supply can be turned off completely. 5.19.1.2 Supply from single voltage rail (1.8V). If a single 1.8V rail is used, generating the 1.8V from a higher battery voltage via a DC-DC converter results in good system-level efficiency. In this setup, the line-output voltage is limited to 500mVrms, and the maximum headphone output power is 15mW into 16Ω. The 1.8V rail can be connected directly to the DVdd pin (LDO_select pin connected to ground) and also supply the digital core voltage. Connecting the 1.8V rail to the AVdd pin will make the device function, but the achievable performance is a function of the voltage ripple typically found on DC-DC converter outputs. To achieve specified performance, an external low-input-voltage 1.6V LDO must be connected between the 1.8V rail and the AVdd input. During operation, the DVdd and AVdd LDOs are deactivated (LDO_select pin and via control register Pg 1, Reg 2, D(0)=0). In this case the LDOin pin should be connected to DVdd. 5.19.1.2.1 Standby Mode (1.8V operation) To put the device in standby mode, both external voltages (AVdd and DVdd) and the reference block inside the TLV320AIC3254 must stay on (Pg 1, Reg 123, D(2:0) = 101), all other blocks should be powered down. This results in standby current of approximately 50µA. In standby mode the device responds very quickly to playback requests. Submit Documentation Feedback Application Information 95 TLV320AIC3254 Ultra Low Power Stereo Audio Codec With Embedded miniDSP SLAS549A – SEPTEMBER 2008 – REVISED OCTOBER 2008 www.ti.com 5.19.1.2.2 Sleep Mode (1.8V operation) In this mode, all settings and memory content of the device is retained. To put the device into sleep mode, the external DVdd must remain powered up, the external AVdd LDO must be powered down, the crude AVdd generation must be turned on (Pg 1, Reg 1, D(3)=0) and the analog blocks must be powered down (Pg 1, Reg 2, D(3)=1). The device's sleep mode power consumption in this case is < 1µA 5.19.1.2.3 Shutdown Mode To shut down the device, the external supplies can be turned off completely. If the 1.8V rail cannot be turned off, the crude AVdd generation must be turned on (Pg 1, Reg 1, D(3)=0) and the analog blocks must be powered down (Pg 1, Reg 2, D(3)=1). This results in a device shutdown current < 1µA. 5.19.1.3 Other Supply Options There are other options to power the device. Apply the following rules: • During normal operation all supply pins must be connected to a supply (via internal LDO or external) • Whenever the LDOin supply is present, – DVdd supply must be present as well – If AVdd supply is not present, then the crude internal AVdd generation must be turned on (Pg 1, Reg 1, D(3)=0) • Whenever the DVdd supply is on, and either AVdd or LDOin or both supplies are off, the analog blocks must be powered down (Pg 1, Reg 2, D(3)=1) 5.20 REFERENCE All data converters require a DC reference voltage. The TLV320AIC3254 achieves its low-noise performance by internally generating a low-noise reference voltage. This reference voltage is generated using a band-gap circuit with a good PSRR performance. This reference voltage must be filtered externally using a minimum 1µF capacitor connected from the REF pin to analog ground (AVss). To achieve low power consumption, this reference block is powered down when all analog blocks inside the device are powered down. In this condition, the REF pin is 3-stated. On powerup of any analog block, the reference block is also powered up and the REF pin settles to its steady-state voltage after the settling time (a function of the de-coupling capacitor on the REF pin). This time is approximately equal to 1 second when using a 1µF decoupling capacitor. In the event that a faster power-up is required, either the reference block can be kept powered up (even when no other analog block is powered up) by programming Page 1, Register 123, D(2) = 1. However, in this case, an additional 125µA of current from DVdd and 105µA of current from AVdd is consumed. Additionally, to achieve a faster powerup, a fast-charge option is also provided where the charging time can be controlled between 40ms and 120ms by programming Page 1, Register 123, D(1:0). By default, the fast charge option is disabled. 5.21 SETTING DEVICE COMMON MODE The TLV320AIC3254 allows the user to set the common mode voltage for analog inputs to 0.75V or 0.9V by programming Page 1, Register 10, D(6). The input common-mode voltage of 0.9V works best when the analog supply voltage is centered around 1.8V or above, and offers the highest possible performance. For analog supply voltages below 1.8V, a common mode voltage of 0.75V must be used. Table 5-26. Input Common Mode voltage and Input Signal Swing Input Common Mode Voltage (V) 96 AVdd (V) Channel Gain (dB) Single-Ended Input Swing for 0dBFS output signal (VRMS) Differential Input Swing for 0dBFS output signal (VRMS) 0.75 >1.5 0 0.375 0.75 0.90 1.8 … 1.95 0 0.5 1.0 Application Information Submit Documentation Feedback TLV320AIC3254 Ultra Low Power Stereo Audio Codec With Embedded miniDSP www.ti.com SLAS549A – SEPTEMBER 2008 – REVISED OCTOBER 2008 The choice of input common mode of 0.75V allows the use of PowerTune mode PTM_R1 which results in significantly lower power dissipation. (see Section 5.6) An input common-mode voltage of 0.9V allows the user to maximize the signal swings and SNR. NOTE The input common mode setting is common for ADC record, DAC playback and Analog Bypass path 5.22 DEVICE SPECIAL FUNCTIONS 5.22.1 Headset Detection The TLV320AIC3254 includes extensive capability to monitor a headphone, microphone, or headset jack, to determine if a plug has been inserted into the jack, and then determine what type of headset/headphone is wired to the plug. The device also includes the capability to detect a button press, even, for example, when starting calls on mobile phones with headsets. This feature is available while using I2C protocol for control interface. The figure shows the circuit configuration to enable this feature. 1 s g s 3 s HPR g HPL s Micpga m m SCLK MICBIAS Micbias Figure 5-58. Jack Connections for Headset Detection This feature is enabled by programming Page 0, Register 67, D(1). In order to avoid false detections due to mechanical vibrations in headset jacks or microphone buttons, a debounce function is provided for glitch rejection. For the case of headset insertion, a debounce function with a range of 32ms - 512ms is provided. This can be programmed via Page 0, Register 67, D(4:2). For improved button-press detection, the debounce function has a range of 8ms to 32ms by programming Page 0, Register 67, D(1:0). The TLV320AIC3254 also provides feedback to user when a button press, or a headset insertion/removal event is detected through register readable flags as well as an interrupt on the IO pins. The value in Page 0, Register 45, D(5:4) provides the instantaneous state of button press and headset insertion. Page 0, Register 44, D(5) is a sticky (latched) flag that is set when the button-press event is detected. Page 0, Register 44, D(4) is a sticky flag which is set when the headset insertion or removal event is detected. These sticky flags are set by the event occurrence, and are reset only when read. This requires polling Page 0, Register 44. To avoid polling and the associated overhead, the TLV320AIC3254 also provides an interrupt feature where the events can trigger the INT1 and/or INT2 interrupts. These interrupt events can be routed to one of the digital output pins. Please refer to Section 5.22.2 for details. Submit Documentation Feedback Application Information 97 TLV320AIC3254 Ultra Low Power Stereo Audio Codec With Embedded miniDSP SLAS549A – SEPTEMBER 2008 – REVISED OCTOBER 2008 www.ti.com The TLV320AIC3254 not only detects a headset insertion event, but also is able to distinguish between the different headsets inserted such as stereo headphones or cellular headphones. After the headset-detection event, the user can read Page 0, Register 67, D(6:5) to determine the type of headset inserted. Table 5-27. Headset Detection Block Registers Register Description Page 0, Register 67, D(1) Headset Detection Enable/Disable Page 0, Register 67, D(4:2) Debounce Programmability for Headset Detection Page 0, Register 67, D(1:0) Debounce Programmability for Button Press Page 0, Register 44, D(5) Sticky Flag for Button Press Event Page 0, Register 44, D(4) Sticky Flag for Headset Insertion or Removal Event Page 0, Register 45, D(5) Status Flag for Button Press Event Page 0, Register 45, D(4) Status Flag for Headset Insertion and Removal Page 0, Register 67, D(6:5) Flags for type of Headset Detected The headset detection block requires AVdd to be powered and Master Analog Power control in Page 1, Register 2, D(3) to be enabled. The headset detection feature in the TLV320AIC3254 is achieved with a very low power overhead, requiring less than 20µA of additional current from AVdd supply. 5.22.2 Interrupts Some specific events in the TLV320AIC3254 which may require host processor intervention, can be used to trigger interrupts to the host processor. This avoids polling the status-flag registers continuously. The TLV320AIC3254 has two defined interrupts; INT1 and INT2 that can be configured by programming Page 0, Register 48 and 49. A user can configure the interrupts INT1 and INT2 to be triggered by one or many events such as • Headset Detection • Button Press • DAC DRC Signal exceeding Threshold • Noise detected by AGC • Over-current condition in headphones • Data Overflow in ADC and DAC Processing Blocks and Filters and • DC Measurement Data Available Each of these INT1 and INT2 interrupts can be routed to output pins like GPIO, DOUT and MISO by configuring the respective output control registers in Page 0, Register 52, 53 and 55. These interrupt signals can either be configured as a single pulse or a series of pulses by programming Page 0, Register 48, D(0) and Page 0, Register 49, D(0). If the user configures the interrupts as a series of pulses, the events will trigger the start of pulses that will stop when the flag registers in Page 0, Register 42, 44 and 45 are read by the user to determine the cause of the interrupt. 5.23 EXAMPLE SETUPS The following example setups can be taken directly for the TLV320AIC3254 EVM setup. The # marks a comment line, w marks an I2C write command followed by the device address, the I2C register address and the value. 5.23.1 Stereo DAC Playback with 48ksps Sample Rate and High Performance. Assumption AVdd = 1.8V, DVdd = 1.8V MCLK = 12.288MHz Ext C = 47uF Based on C the wait time will change. Wait time = N*Rpop*C + 4* Offset ramp time 98 Application Information Submit Documentation Feedback TLV320AIC3254 Ultra Low Power Stereo Audio Codec With Embedded miniDSP www.ti.com SLAS549A – SEPTEMBER 2008 – REVISED OCTOBER 2008 Default settings used. PLL Disabled DOSR 128 # Initialize to Page 0 w 30 00 00 # Initialize the device through software reset w 30 01 01 # Power up the NDAC divider with value 1 w 30 0b 81 # Power up the MDAC divider with value 2 w 30 0c 82 # Program the OSR of DAC to 128 w 30 0d 00 w 30 0e 80 # Set the word length of Audio Interface to 20bits PTM_P4 w 30 1b 10 # Set the DAC Mode to PRB_P8 w 30 3c 08 # Select Page 1 w 30 00 01 # Disable Internal Crude AVdd in presence of external AVdd supply or before #powering up internal AVdd LDO w 30 01 08 # Enable Master Analog Power Control w 30 02 00 # Set the REF charging time to 40ms w 30 7b 01 # HP soft stepping settings for optimal pop performance at power up # Rpop used is 6k with N = 6 & soft step = 20usec. This should work with 47uF coupling # capacitor. Can try N=5,6 or 7 time constants as well. Trade-off delay vs “pop” sound. w 30 14 25 # Set the Input Common Mode to 0.9V and Output Common Mode for Headphone to # Input Common Mode w 30 0a 00 # Route Left DAC to HPL w 30 0c 08 # Route Right DAC to HPR w 30 0d 08 # Set the DAC PTM mode to PTM_P3/4 w 30 03 00 w 30 04 00 # Set the HPL gain to 0dB w 30 10 00 # Set the HPR gain to 0dB w 30 11 00 # Power up HPL and HPR drivers w 30 09 30 # Wait for 2.5 sec for soft stepping to take effect # Else read Page 1, Register 63d, D(7:6). When = “11” soft-stepping is complete # Select Page 0 w 30 00 00 # Power up the Left and Right DAC Channels with route the Left Audio digital data to # Left Channel DAC and Right Audio digital data to Right Channel DAC w 30 3f d6 # Unmute the DAC digital volume control w 30 40 00 5.23.2 Stereo DAC Playback with 48ksps Sample Rate and Low Power Mode Assumption AVdd = 1.8V, DVdd = 1.8V MCLK = 12.288MHz Ext C = 47µF Based on C the wait time will change. Wait time = N*Rpop*C + 4* Offset ramp time Default settings used. PLL Disabled # Initialize to Page 0 w 30 00 00 # Initialize the device through software reset w 30 01 01 # Power up the NDAC divide with value 1 w 30 0b 81 Submit Documentation Feedback Application Information 99 TLV320AIC3254 Ultra Low Power Stereo Audio Codec With Embedded miniDSP SLAS549A – SEPTEMBER 2008 – REVISED OCTOBER 2008 # w # w w # w # w # # w # w # w # # # w # # w # w # w # w w # w # w # w # # # w # # w # w www.ti.com Power up the MDAC divider with value 4 30 0c 84 Program the OSR of DAC to 64 30 0d 00 30 0e 40 Set the DAC Mode to PRB_P8 30 3c 08 Select Page 1 30 00 01 Disable Internal Crude AVdd in presence of external AVdd supply or before powering up internal AVdd LDO 30 01 08 Enable Master Analog Power Control 30 02 00 Set the REF charging time to 40ms 30 7b 01 HP soft stepping settings for optimal pop performance at power up Rpop used is 6k with N = 6 & soft step = 20usec. This should work with 47uF coupling capacitor. Can try N=5,6 or 7 time constants as well. Trade-off delay vs “pop” sound. 30 14 25 Set the Input Common Mode to 0.9V and Output Common Mode for Headphone to Input Common Mode 30 0a 00 Route Left DAC to HPL 30 0c 08 Route Right DAC to HPR 30 0d 08 Set the DAC PTM mode to PTM_P1 30 03 08 30 04 08 Set the HPL gain to 0dB 30 10 00 Set the HPR gain to 0dB 30 11 00 Power up HPL and HPR drivers 30 09 30 Wait for 2.5 sec for soft stepping to take effect Else read Page 1, Register 63d, D(7:6). When = “11” soft-stepping is complete Select Page 0 30 00 00 Power up the Left and Right DAC Channels with route the Left Audio digital data to Left Channel DAC and Right Audio digital data to Right Channel DAC 30 3f d6 Unmute the DAC digital volume control 30 40 00 5.23.3 DAC Playback Through Class-D Headphone Amplifiers Power Up # Assumption DAC_FS = 48000Hz # MCLK = 24.576MHz # I2S Interface in Slave Mode 100 # w # w # w # # w # w w # w Initialize to Page 0 30 00 00 Initialize the device through software reset 30 01 01 Power up the NDAC divider with value 1 30 0B 81 Power up the MDAC divider with value 4 For Class-D mode, MDAC = I*4 30 0C 84 Program the OSR of DAC to 128 30 0D 00 30 0E 80 Set the DAC Mode to PRB_P1v 30 3C 01 # w # # w Select Page 1 30 00 01 Disable Internal Crude AVdd in presence of external AVdd supply or before powering up internal AVdd LDO 30 01 08 Application Information Submit Documentation Feedback TLV320AIC3254 Ultra Low Power Stereo Audio Codec With Embedded miniDSP www.ti.com SLAS549A – SEPTEMBER 2008 – REVISED OCTOBER 2008 # w # w # # w # # w # w # w # w # w # w # w Enable Master Analog Power Control 30 02 00 Set the REF charging time to 40ms 30 7B 01 HP soft stepping settings for optimal pop performance at power up Rpop used is 6k with N = 6 & soft step = 0 30 14 25 Set the Input Common Mode to 0.9V and Output Common Mode for Headphone to Input Common Mode 30 0A 00 Route Left DAC to HPL 30 0C 08 Route Right DAC to HPR 30 0D 08 Unmute HPL driver 30 10 00 Unmute HPR driver 30 11 00 Power up HPL and HPR drivers 30 09 30 switch to Page 0 30 00 00 # # w # w Wait for soft stepping to take effect L&R DAC powerup Ldata-LDAC Rdata-RDAC 30 3F d4 Left and Right DAC unmuted with indep. vol. ctrl 30 40 00 # Wait for DAC vol ctrl soft-stepping to complete # Select Page 1 w # w # w # w 30 00 01 Enable Class-D mode for HPL output 30 03 C0 Enable Class-D mode for HPR output 30 04 C0 Power down HPL and HPR drivers 30 09 00 Power Down # Select Page 0 w 30 00 00 # Mute the DAC digital volume control w 30 40 0d # Power down the DAC W 30 3F C0 # Disable Class-D mode for HPL output w 30 03 00 # Disable Class-D mode for HPL output w 30 04 00 5.23.4 Stereo ADC with 48ksps Sample Rate and High Performance Assumption AVdd = 1.8V, DVdd = 1.8V MCLK = 12.288MHz Default settings used. PLL Disabled I2S Interface with 16bit Word Length. AOSR 128 PRB_R1 PTM_R4 # w # w # w # Initialize to Page 0 30 00 00 S/W Reset to initialize all registers 30 01 01 Power up NADC divider with value 1 30 12 81 Power up MADC divider with value 2 Submit Documentation Feedback Application Information 101 TLV320AIC3254 Ultra Low Power Stereo Audio Codec With Embedded miniDSP SLAS549A – SEPTEMBER 2008 – REVISED OCTOBER 2008 w # w # w # w # # w # w # w # w # w # w # w # w # w # w # # w # # w # w # w # w www.ti.com 30 13 82 Program OSR for ADC to 128 30 14 80 Select ADC PRB_R1 30 3d 01 Select Page 1 30 00 01 Disable Internal Crude AVdd in presence of external AVdd supply or before powering up internal AVdd LDO 30 01 08 Enable Master Analog Power Control 30 02 00 Set the input common mode to 0.9V 30 0a 00 Select ADC PTM_R4 30 3d 00 Set MicPGA startup delay to 3.1ms 30 47 32 Set the REF charging time to 40ms 30 7b 01 Route IN1L to LEFT_P with 20K input impedance 30 34 80 Route Common Mode to LEFT_M with impedance of 20K 30 36 80 Route IN1R to RIGHT_P with input impedance of 20K 30 37 80 Route Common Mode to RIGHT_M with impedance of 20K 30 39 80 Unmute Left MICPGA, Gain selection of 6dB to make channel gain 0dB Register of 6dB with input impedance of 20K => Channel Gain of 0dB 30 3b 0c Unmute Right MICPGA, Gain selection of 6dB to make channel gain 0dB Register of 6dB with input impedance of 20K => Channel Gain of 0dB 30 3c 0c Select Page 0 30 00 00 Power up Left and Right ADC Channels 30 51 c0 Unmute Left and Right ADC Digital Volume Control. 30 52 00 5.23.5 Stereo ADC with 48ksps Sample Rate and Low Power Assumption AVdd = 1.8V, DVdd = 1.8V MCLK = 12.288MHz Default settings used. PLL Disabled I2S Interface with 16bit Word Length. # Initialize to Page 0 w 30 00 00 # S/W Reset to initialize all registers w 30 01 01 # Power up NADC divider with value 1 w 30 12 81 # Power up MADC divider with value 4 w 30 13 84 # Program OSR for ADC to 64 w 30 14 40 # Select ADC PRB_R7 w 30 3d 07 # Select Page 1 w 30 00 01 # Disable Internal Crude AVdd in presence of external AVdd supply or before #powering up internal AVdd LDO w 30 01 08 # Enable Master Analog Power Control w 30 02 00 # Set the input common mode to 0.75V w 30 0a 40 # Select ADC PTM_R1 w 30 3d ff 102 Application Information Submit Documentation Feedback TLV320AIC3254 Ultra Low Power Stereo Audio Codec With Embedded miniDSP www.ti.com SLAS549A – SEPTEMBER 2008 – REVISED OCTOBER 2008 # w # w # w # w # w # w # # w Set MicPGA startup delay to 3.1ms 30 47 32 Set the REF charging time to 40ms 30 7b 01 Route IN1L to LEFT_P with 20K input impedance 30 34 80 Route Common Mode to LEFT_M with impedance of 20K 30 36 80 Route IN1R to RIGHT_P with input impedance of 20K 30 37 80 Route Common Mode to RIGHT_M with impedance of 20K 30 39 80 Unmute Left MICPGA, Gain selection of 6dB to make channel gain 0dB Register of 6dB with input impedance of 20K => Channel Gain of 0dB 30 3b 0c # # w # w # w # w Unmute Right MICPGA, Gain selection of 6dB to make channel gain 0dB Register of 6dB with input impedance of 20K => Channel Gain of 0dB 30 3c 0c Select Page 0 30 00 00 Power up Left and Right ADC Channels 30 51 c0 Unmute Left and Right ADC Digital Volume Control. 30 52 00 Submit Documentation Feedback Application Information 103 TLV320AIC3254 Ultra Low Power Stereo Audio Codec With Embedded miniDSP SLAS549A – SEPTEMBER 2008 – REVISED OCTOBER 2008 www.ti.com 6 REGISTER MAP TLV320AIC3254 contains 108 pages of 8-bit registers, each page can contain up to 128 registers. The register pages are divided up based on functional blocks for this device. Page 0 is the default “home” page after hardware reset. 6.1 Register Map Summary Table 6-1. Summary of Register Map PAGE NO. DESCRIPTION 0 Configuration for Serial Interface, Digital IO, Clocking, ADC and DAC miniDSP configuration etc. 1 Configuration for Analog PGA’s, ADC, DAC, Output.Drivers, Volume controls etc 2-7 Reserved 8 ADC miniDSP adaptive filtering control and ADC Coefficient Buffer-A (0:29). Refer to Table 6-2 for more details. 9-16 ADC Coefficient Buffer-A (30:255). Refer to Table 6-2 and Table 6-4 for more details. 17-25 Reserved. 26-34 ADC Coefficient Buffer-B (0:255). Refer to Table 6-3 and Table 6-4 for more details. 35-43 Reserved. 44 DAC miniDSP adaptive filtering control and DAC Coefficient Buffer-A (0:29). Refer to Table 6-5 for more details. 45-52 DAC Coefficient BufferA (30:255). Refer Table 6-5 and Table 6-7 for more details. 53-61 Reserved. 62-70 DAC Coefficient BufferB C(0:255). Refer Table 6-6 and Table 6-7 for more details. 71-79 Reserved. 80-114 ADC miniDSP Instructions (0:1023). Refer Table 6-8 for more details. 115-151 Reserved. 152-186 DAC miniDSP Instructions (0:1023). Refer Table 6-9 for more details. 187-255 Reserved. 6.2 Register Map Details 6.2.1 Page 0 / Register 0: BIT READ/ WRITE RESET VALUE D7–D0 R/W 0000 0000 6.2.2 Page 0 / Register 1: READ/ WRITE RESET VALUE D7–D1 R 0000 000 D0 W 0 BIT 6.2.3 Page 0 / Register 2: BIT READ/ WRITE D7–D0 R 104 REGISTER MAP Page Select Register DESCRIPTION Page Select Register 0-255: Selects the Register Page for next read or write command. Refer Table "Summary of Memory Map" for details. Software Reset Register DESCRIPTION Reserved, Write only default values Self clearing software reset bit 0: Don't care 1: Self clearing software reset Reserved Register RESET VALUE DESCRIPTION 0XXX 0XXX Reserved, Write only default values Submit Documentation Feedback TLV320AIC3254 Ultra Low Power Stereo Audio Codec With Embedded miniDSP www.ti.com 6.2.4 SLAS549A – SEPTEMBER 2008 – REVISED OCTOBER 2008 Page 0 / Register 3: BIT READ/ WRITE RESET VALUE D7–D0 R 0000 0000 6.2.5 Page 0 / Register 4: Reserved Register DESCRIPTION Reserved, Write only default values to this register Clock Setting Register 1, Multiplexers READ/ WRITE RESET VALUE D7 R 0 Reserved, Write only default values D6 R/W 0 Select PLL Range 0: Low PLL Clock Range 1: High PLL Clock Range D5–D4 R 00 Reserved, Write only default values any other value than reset value. D3–D2 R/W 00 Select PLL Input Clock 00: MCLK pin is input to PLL 01: BCLK pin is input to PLL 10: GPIO pin is input to PLL 11: DIN pin is input to PLL D1–D0 R/W 00 Select CODEC_CLKIN 00: MCLK pin is CODEC_CLKIN 01: BCLK pin is CODEC_CLKIN 10: GPIO pin is CODEC_CLKIN 11: PLL Clock is CODEC_CLKIN BIT 6.2.6 Page 0 / Register 5: DESCRIPTION Clock Setting Register 2, PLL P&R Values BIT READ/ WRITE RESET VALUE D7 R/W 0 D6–D4 R/W 001 PLL divider P Value 000: P=8 001: P=1 010: P=2 … 110: P=6 111: P=7 D3–D0 R/W 0001 PLL divider R Value 000: Reserved, do not use 001: R=1 010: R=2 011: R=3 100: R=4 101…111: Reserved, do not use 6.2.7 BIT Page 0 / Register 6: READ/ WRITE DESCRIPTION PLL Power Up 0: PLL is powered down 1: PLL is powered up Clock Setting Register 3, PLL J Values RESET VALUE D7–D6 R 00 D5–D0 R/W 00 0100 Submit Documentation Feedback DESCRIPTION Reserved. Write only default values any value other than default PLL divider J value 00 0000…00 0011: Do not use 00 0100: J=4 00 0101: J=5 … 11 1110: J=62 11 1111: J=63 REGISTER MAP 105 TLV320AIC3254 Ultra Low Power Stereo Audio Codec With Embedded miniDSP SLAS549A – SEPTEMBER 2008 – REVISED OCTOBER 2008 6.2.8 Page 0 / Register 7: BIT READ/ WRITE RESET VALUE D7–D6 R 00 D5–D0 R/W 00 0000 6.2.9 Clock Setting Register 4, PLL D Values (MSB) DESCRIPTION Reserved. Write only default values any value other than default PLL divider D value (MSB) PLL divider D value(MSB) & PLL divider D value(LSB) 00 0000 0000 0000: D=0000 00 0000 0000 0001: D=0001 … 10 0111 0000 1110: D=9998 10 0111 0000 1111: D=9999 10 0111 0001 0000…11 1111 1111 1111: Do not use Note: This register will be updated only when the Page-0, Reg-8 is written immediately after Page-0, Reg-7 Page 0 / Register 8: BIT READ/ WRITE RESET VALUE D7–D0 R/W 0000 0000 Clock Setting Register 5, PLL D Values (LSB) DESCRIPTION PLL divider D value (LSB) PLL divider D value(MSB) & PLL divider D value(LSB) 00 0000 0000 0000: D=0000 00 0000 0000 0001: D=0001 … 10 0111 0000 1110: D=9998 10 0111 0000 1111: D=9999 10 0111 0001 0000…11 1111 1111 1111: Do not use Note: Page-0, Reg-8 should be written immediately after Page-0, Reg-7 6.2.10 Page 0 / Register 9-10: BIT READ/ WRITE RESET VALUE D7–D0 R 0000 0000 READ/ WRITE RESET VALUE D7 R/W 0 D6–D0 R/W 000 0001 Reserved, Write only default values. READ/ WRITE RESET VALUE D7 R/W 0 D6–D0 R/W 000 0001 106 REGISTER MAP Clock Setting Register 6, NDAC Values DESCRIPTION NDAC Divider Power Control 0: NDAC divider powered down 1: NDAC divider powered up NDAC Value 000 0000: NDAC=128 000 0001: NDAC=1 000 0010: NDAC=2 … 111 1110: NDAC=126 111 1111: NDAC=127 Note: Please check the clock frequency requirements in the Overview section 6.2.12 Page 0 / Register 12: BIT Reserved Register DESCRIPTION 6.2.11 Page 0 / Register 11: BIT www.ti.com Clock Setting Register 7, MDAC Values DESCRIPTION MDAC Divider Power Control 0: MDAC divider powered down 1: MDAC divider powered up MDAC Value 000 0000: MDAC=128 000 0001: MDAC=1 000 0010: MDAC=2 … 111 1110: MDAC=126 111 1111: MDAC=127 Note: Please check the clock frequency requirements in the Overview section Submit Documentation Feedback TLV320AIC3254 Ultra Low Power Stereo Audio Codec With Embedded miniDSP www.ti.com SLAS549A – SEPTEMBER 2008 – REVISED OCTOBER 2008 6.2.13 Page 0 / Register 13: BIT READ/ WRITE RESET VALUE D7–D2 R 0000 00 D1–D0 R/W 00 DESCRIPTION Reserved. Write only default values DAC OSR (DOSR) Setting DAC OSR(MSB) & DAC OSR(LSB) 00 0000 0000: DOSR=1024 00 0000 0001: DOSR=1 00 0000 0010: DOSR=2 … 11 1111 1110: DOSR=1022 11 1111 1111: DOSR=1023 Note: This register is updated when Page-0, Reg-14 is written to immediately after Page-0, Reg-13 6.2.14 Page 0 / Register 14: BIT READ/ WRITE RESET VALUE D7–D0 R/W 1000 0000 READ/ WRITE RESET VALUE D7 R 0 D6–D0 R/W 000 0010 DAC OSR (DOSR) Setting DAC OSR(MSB) & DAC OSR(LSB) 00 0000 0000: DOSR=1024 00 0000 0001: DOSR=1 00 0000 0010: DOSR=2 … 11 1111 1110: DOSR=1022 11 1111 1111: DOSR=1023 Note: This register should be written immediately after Page-0, Reg-13 BIT RESET VALUE D7–D0 R/W 0000 0000 Submit Documentation Feedback DAC miniDSP instruction control Register 1 DESCRIPTION Reserved. Write only default value DAC miniDSP IDAC (14:8) setting. Use when DAC miniDSP is in use for signal processing (page 0,Reg 60) DAC miniDSP IDAC(14:0) 000 0000 0000 0000: DAC miniDSP IDAC = 32768 000 0000 0000 0001: DAC miniDSP IDAC = 1 000 0000 0000 0010: DAC miniDSP IDAC = 2 … … 111 1111 1111 1110: DAC miniDSP IDAC = 32766 111 1111 1111 1111: DAC miniDSP IDAC = 32767 Note: IDAC should be a integral multiple of INTERP ( Page-0, Reg-17, D3-D0 ) Note: Page-0, Reg-15 takes effect after programming Page-0, Reg-16 in the immediate next control command 6.2.16 Page 0 / Register 16: READ/ WRITE DAC OSR Setting Register 2, LSB Value DESCRIPTION 6.2.15 Page 0 / Register 15: BIT DAC OSR Setting Register 1, MSB Value DAC miniDSP instruction control Register 2 DESCRIPTION DAC miniDSP IDAC (7:0) setting. Use when DAC miniDSP is in use for signal processing (page 0,Reg 60) DAC miniDSP IDAC(14:0) 000 0000 0000 0000: DAC miniDSP IDAC = 32768 000 0000 0000 0001: DAC miniDSP IDAC = 1 000 0000 0000 0010: DAC miniDSP IDAC = 2 … … 111 1111 1111 1110: DAC miniDSP IDAC = 32766 111 1111 1111 1111: DAC miniDSP IDAC = 32767 Note: IDAC should be a integral multiple of INTERP ( Page-0, Reg-17, D3-D0 ) Note: Page-0, Reg-16 should be programmed immediately after Page-0, Reg-15 REGISTER MAP 107 TLV320AIC3254 Ultra Low Power Stereo Audio Codec With Embedded miniDSP SLAS549A – SEPTEMBER 2008 – REVISED OCTOBER 2008 6.2.17 Page 0 / Register 17: www.ti.com DAC miniDSP Interpolation Factor Setting Register BIT READ/ WRITE RESET VALUE D7–D4 R 0000 Reserved. Write only default values D3–D0 R/W 1000 DAC miniDSP interpolation factor setting. Used when DAC miniDSP is in use for signal processing (page 0,Reg 60) 0000 : Interpolation factor in DAC miniDSP(INTERP) = 16 0001: Interpolation factor in DAC miniDSP(INTERP)= 1 0010: Interpolation factor in DAC miniDSP(INTERP) = 2 … 1110: Interpolation factor in DAC miniDSP(INTERP) = 14 1111: Interpolation factor in DAC miniDSP(INTERP) = 15 DESCRIPTION 6.2.18 Page 0 / Register 18: BIT READ/ WRITE RESET VALUE D7 R/W 0 D6–D0 R/W 000 0001 DESCRIPTION NADC Clock Divider Power Control 0: NADC divider powered down, ADC_CLK is same as DAC_CLK 1: NADC divider powered up NADC Value 000 0000: NADC=128 000 0001: NADC=1 … 111 1110: NADC=126 111 1111: NADC=127 6.2.19 Page 0 / Register 19: BIT READ/ WRITE RESET VALUE D7 R/W 0 D6–D0 R/W 000 0001 READ/ WRITE RESET VALUE D7–D0 R/W 1000 0000 MADC Clock Divider Power Control 0: MADC divider powered down, ADC_MOD_CLK is same as DAC_MOD_CLK 1: MADC divider powered up MADC Value 000 0000: MADC=128 000 0001: MADC=1 … 111 1110: MADC=126 111 1111: MADC=127 108 READ/ WRITE RESET VALUE D7 R 0 REGISTER MAP ADC Oversampling (AOSR) Register DESCRIPTION ADC Oversampling Value 0000 0000: ADC AOSR = 256 0000 0001: ADC AOSR = 1 0000 0010: ADC AOSR = 2 ... 0010 0000: ADC AOSR=32 (Use with PRB_R13 to PRB_R18, ADC Filter Type C) ... 0100 0000: AOSR=64 (Use with PRB_R1 to PRB_R12, ADC Filter Type A or B) ... 1000 0000: AOSR=128 (Use with PRB_R1 to PRB_R6, ADC Filter Type A) ... 1111 1110: ADC AOSR = 254 1111 1111: ADC AOSR = 255 Note: If the ADC miniDSP will be used for signal processing ADC (Pg 0, Reg 61) AOSR should be an integral multiple of ADC DECIM factor. 6.2.21 Page 0 / Register 21: BIT Clock Setting Register 9, MADC Values DESCRIPTION 6.2.20 Page 0 / Register 20: BIT Clock Setting Register 8, NADC Values ADC miniDSP instruction control Register 1 DESCRIPTION Reserved. Write only default values Submit Documentation Feedback TLV320AIC3254 Ultra Low Power Stereo Audio Codec With Embedded miniDSP www.ti.com SLAS549A – SEPTEMBER 2008 – REVISED OCTOBER 2008 (continued) BIT READ/ WRITE RESET VALUE D6–D0 R/W 000 0001 DESCRIPTION ADC miniDSP IADC (14:8) setting. Use when ADC miniDSP is in use for signal processing (page 0,Reg 61) ADC miniDSP IADC(14:0) 000 0000 0000 0000: ADC miniDSP IADC=32768 000 0000 0000 0001: ADC miniDSP IADC = 1 000 0000 0000 0010: ADC miniDSP IADC = 2 … … 111 1111 1111 1110: ADC miniDSP IADC = 32766 111 1111 1111 1111: ADC miniDSP IADC = 32767 Note: IADC should be a integral multiple of DECIM ( Page-0, Reg-23, D3-D0 ) Note: Page-0, Reg-21 takes effect after programming Page-0, Reg-22 in the immediate next control command 6.2.22 Page 0 / Register 22: BIT READ/ WRITE RESET VALUE D7–D0 R/W 0000 0000 ADC miniDSP instruction control Register 2 DESCRIPTION ADC miniDSP IADC (14:8) setting. Use when ADC miniDSP is in use for signal processing (page 0,Reg 61) ADC miniDSP IADC(14:0) 000 0000 0000 0000: ADC miniDSP IADC=32768 000 0000 0000 0001: ADC miniDSP IADC = 1 000 0000 0000 0010: ADC miniDSP IADC = 2 … … 111 1111 1111 1110: ADC miniDSP IADC = 32766 111 1111 1111 1111: ADC miniDSP IADC = 32767 Note: IADC should be a integral multiple of DECIM ( Page-0, Reg-23, D3-D0 ) Note: Page-0, Reg-21 takes effect after programming Page-0, Reg-22 in the immediate next control command 6.2.23 Page 0 / Register 23: ADC miniDSP Decimation Factor Setting Register READ/ WRITE RESET VALUE D7–D4 R 0000 Reserved. Write only default values D3–D0 R/W 0100 ADC miniDSP Decimation factor setting. Use when ADC miniDSP is in use for signal processing (page 0,Reg 61) 0000: Decimation factor in ADC miniDSP = 16 0001: Decimation factor in ADC miniDSP = 1 0010: Decimation factor in ADC miniDSP = 2 … 1110: Decimation factor in ADC miniDSP = 14 1111: Decimation factor in ADC miniDSP = 15 BIT DESCRIPTION 6.2.24 Page 0 / Register 24: BIT READ/ WRITE RESET VALUE D7–D0 R 0000 0000 DESCRIPTION Reserved. Write only default values 6.2.25 Page 0 / Register 25: BIT READ/ WRITE RESET VALUE D7–D3 R 0000 0 Submit Documentation Feedback Reserved Register Clock Setting Register 9, Multiplexers DESCRIPTION Reserved. Write only default values REGISTER MAP 109 TLV320AIC3254 Ultra Low Power Stereo Audio Codec With Embedded miniDSP SLAS549A – SEPTEMBER 2008 – REVISED OCTOBER 2008 www.ti.com (continued) BIT READ/ WRITE RESET VALUE D2–D0 R/W 000 DESCRIPTION CDIV_CLKIN Clock Selection 000: CDIV_CLKIN= MCLK 001: CDIV_CLKIN= BCLK 010: CDIV_CLKIN=DIN 011: CDIV_CLKIN=PLL_CLK 100: CDIV_CLKIN=DAC_CLK 101: CDIV_CLKIN=DAC_MOD_CLK 110: CDIV_CLKIN=ADC_CLK 111: CDIV_CLKIN=ADC_MOD_CLK 6.2.26 Page 0 / Register 26: BIT READ/ WRITE RESET VALUE D7 R/W 0 D6–D0 R/W 000 0001 Clock Setting Register 10, CLKOUT M divider value DESCRIPTION CLKOUT M divider power control 0: CLKOUT M divider powered down 1: CLKOUT M divider powered up CLKOUT M divider value 000 0000: CLKOUT M divider 000 0001: CLKOUT M divider 000 0010: CLKOUT M divider … 111 1110: CLKOUT M divider 111 1111: CLKOUT M divider 6.2.27 Page 0 / Register 27: = 126 = 127 Audio Interface Setting Register 1 BIT READ/ WRITE RESET VALUE D7–D6 R/W 00 Audio Interface Selection 00: Audio Interface = I2S 01: Audio Interface = DSP 10: Audio Interface = RJF 11: Audio Interface = LJF D5–D4 R/W 00 Audio Data Word length 00: Data Word length = 16 01: Data Word length = 20 10: Data Word length = 24 11: Data Word length = 32 DESCRIPTION bits bits bits bits D3 R/W 0 BCLK Direction Control 0: BCLK is input to the device 1: BCLK is output from the device D2 R/W 0 WCLK Direction Control 0: WCLK is input to the device 1: WCLK is output from the device D1 R 0 Reserved. Write only default value D0 R/W 0 DOUT High Impendance Output Control 0: DOUT will not be high impedance while Audio Interface is active 1: DOUT will be high impedance after data has been transferred 6.2.28 Page 0 / Register 28: BIT READ/ WRITE RESET VALUE D7–D0 R/W 0000 0000 110 = 128 =1 =2 REGISTER MAP Audio Interface Setting Register 2, Data offset setting DESCRIPTION Data Offset Value 0000 0000: Data Offset 0000 0001: Data Offset … 1111 1110: Data Offset 1111 1111: Data Offset = 0 BCLK's = 1 BCLK's = 254 BCLK's = 255 BCLK's Submit Documentation Feedback TLV320AIC3254 Ultra Low Power Stereo Audio Codec With Embedded miniDSP www.ti.com SLAS549A – SEPTEMBER 2008 – REVISED OCTOBER 2008 6.2.29 Page 0 / Register 29: Audio Interface Setting Register 3 BIT READ/ WRITE RESET VALUE D7–D6 R/W 00 Reserved. Write only default values D5 R/W 0 Loopback control 0: No Loopback 1: Audio Data in is routed to Audio Data out D4 R/W 0 Loopback control 0: No Loopback 1: Stereo ADC output is routed to Stereo DAC input D3 R/W 0 Audio Bit Clock Polarity Control 0: Default Bit Clock polarity 1: Bit Clock is inverted w.r.t. default polarity D2 R/W 0 Primary BCLK and Primary WCLK Power control 0: Primary BCLK and Primary WCLK buffers are powered up when they are used in clock generation even when the codec is powered down 1: Priamry BCLK and Primary WCLK buffers are powered down when the codec is powered down D1–D0 R/W 00 BDIV_CLKIN Multiplexer Control 00: BDIV_CLKIN = DAC_CLK 01: BDIV_CLKIN = DAC_MOD_CLK 10: BDIV_CLKIN = ADC_CLK 11: BDIV_CLKIN = ADC_MOD_CLK DESCRIPTION 6.2.30 Page 0 / Register 30: BIT READ/ WRITE RESET VALUE D7 R/W 0 D6–D0 R/W 000 0001 DESCRIPTION BCLK N Divider Power Control 0: BCLK N divider powered down 1: BCLK N divider powered up BCLK N Divider value 0000 0000: BCLK N divider 0000 0001: BCLK N divider … 1111 1110: BCLK N divider 1111 1111: BCLK N divider 6.2.31 Page 0 / Register 31: BIT READ/ WRITE Clock Setting Register 11, BCLK N Divider = 128 =1 = 126 = 127 Audio Interface Setting Register 4, Secondary Audio Interface RESET VALUE DESCRIPTION D7 R 0 Reserved. Write only default values D6–D5 R/W 00 Secondary Bit Clock Multiplexer 00: Secondary Bit Clock = GPIO 01: Secondary Bit Clock = SCLK 10: Secondary Bit Clock = MISO 11: Secondary Bit Clock = DOUT D4–D3 R/W 00 Secondary Word Clock Multiplexer 00: Secondary Word Clock = GPIO 01: Secondary Word Clock = SCLK 10: Secondary Word Clock = MISO 11: Secondary Word Clock = DOUT D2–D1 R/W 00 ADC Word Clock Multiplexer 00: ADC Word Clock = GPIO 01: ADC Word Clock = SCLK 10: ADC Word Clock = MISO 11: Do not use D0 R/W 0 Secondary Data Input Multiplexer 0: Secondary Data Input = GPIO 1: Secondary Data Input = SCLK Submit Documentation Feedback REGISTER MAP 111 TLV320AIC3254 Ultra Low Power Stereo Audio Codec With Embedded miniDSP SLAS549A – SEPTEMBER 2008 – REVISED OCTOBER 2008 6.2.32 Page 0 / Register 32: www.ti.com Audio Interface Setting Register 5 BIT READ/ WRITE RESET VALUE D7–D4 R 0000 D3 R/W 0 Primary / Secondary Bit Clock Control 0: Primary Bit Clock(BCLK) is used for Audio Interface and Clocking 1: Secondary Bit Clock is used for Audio Interface and Clocking D2 R/W 0 Primary / Secondary Word Clock Control 0: Primary Word Clock(WCLK) is used for Audio Interface 1: Secondary Word Clock is used for Audio Interface D1 R/W 0 ADC Word Clock Control 0: ADC Word Clock is same as DAC Word Clock 1: ADC Word Clock is Secondary ADC Word Clock D0 R/W 0 Audio Data In Control 0: DIN is used for Audio Data In 1: Secondary Data In is used for Audio Data In DESCRIPTION Reserved. Write only default values 6.2.33 Page 0 / Register 33: Audio Interface Setting Register 6 BIT READ/ WRITE RESET VALUE D7 R/W 0 BCLK Output Control 0: BCLK Output = Generated Primary Bit Clock 1: BCLK Output = Secondary Bit Clock Input D6 R/W 0 Secondary Bit Clock Output Control 0: Secondary Bit Clock = BCLK input 1: Secondary Bit Clock = Generated Primary Bit Clock D5–D4 R/W 00 WCLK Output Control 00: WCLK Output = Generated DAC_FS 01: WCLK Output = Generated ADC_FS 10: WCLK Output = Secondary Word Clock Input 11: Do not use D3–D2 R/W 00 Secondary Word Clock Output Control 00: Secondary Word Clock output = WCLK input 01: Secondary Word Clock output = Generated DAC_FS 10: Secondary Word Clock output = Generated ADC_FS 11: Do not use D1 R/W 0 Primary Data Out output control 0: DOUT output = Data Output from Serial Interface 1: DOUT output = Secondary Data Input (Loopback) D0 R/W 0 Secondary Data Out output control 0: Secondary Data Output = DIN input (Loopback) 1: Secondary Data Output = Data output from Serial Interface DESCRIPTION 6.2.34 Page 0 / Register 34: Digital Interface Misc. Setting Register BIT READ/ WRITE RESET VALUE D7 R 0 Reserved. Write only default value D6 R 0 Reserved. Write only default value D5 R/W 0 I2C General Call Address Configuration 0: I2C General Call Address will be ignored 1: I2C General Call Address accepted D4–D0 R 0 0000 DESCRIPTION Reserved. Write only default values 6.2.35 Page 0 / Register 35: BIT READ/ WRITE RESET VALUE D7–D0 R 0000 0000 112 REGISTER MAP Reserved Register DESCRIPTION Reserved. Write only default value Submit Documentation Feedback TLV320AIC3254 Ultra Low Power Stereo Audio Codec With Embedded miniDSP www.ti.com SLAS549A – SEPTEMBER 2008 – REVISED OCTOBER 2008 6.2.36 Page 0 / Register 36: ADC Flag Register BIT READ/ WRITE RESET VALUE D7 R 0 Left ADC PGA Status Flag 0: Gain Applied in Left ADC PGA is not equal to Programmed Gain in Control Register 1: Gain Applied in Left ADC PGA is equal to Programmed Gain in Control Register D6 R 0 Left ADC Power Status Flag 0: Left ADC Powered Down 1: Left ADC Powered Up D5 R 0 Left AGC Gain Status. This sticky flag will self clear on reading 0: Gain in Left AGC is not saturated 1: Gain in Left ADC is equal to maximum allowed gain in Left AGC D4 R 0 Reserved. Write only default value D3 R 0 Right ADC PGA Status Flag 0: Gain Applied in Right ADC PGA is not equal to Programmed Gain in Control Register 1: Gain Applied in Right ADC PGA is equal to Programmed Gain in Control Register D2 R 0 Right ADC Power Status Flag 0: Right ADC Powered Down 1: Right ADC Powered Up D1 R 0 Right AGC Gain Status. This sticky flag will self clear on reading 0: Gain in Right AGC is not saturated 1: Gain in Right ADC is equal to maximum allowed gain in Right AGC D0 R 0 Reserved. Write only default value DESCRIPTION 6.2.37 Page 0 / Register 37: DAC Flag Register 1 BIT READ/ WRITE RESET VALUE D7 R 0 Left DAC Power Status Flag 0: Left DAC Powered Down 1: Left DAC Powered Up D6 R 0 Left Line Output Driver(LOL) Power Status Flag 0: LOL Powered Down 1: LOL Powered Up D5 R 0 Left Headphone Driver (HPL) Power Status Flag 0: HPL Powered Down 1: HPL Powered Up D4 R 0 Reserved. Write only default values D3 R 0 Right DAC Power Status Flag 0: Right DAC Powered Down 1: Right DAC Powered Up D2 R 0 Right Line Output Driver(LOR) Power Status Flag 0: LOR Powered Down 1: LOR Powered Up D1 R 0 Right Headphone Driver (HPR) Power Status Flag 0: HPR Powered Down 1: HPR Powered Up D0 R 0 Reserved. Write only default values DESCRIPTION 6.2.38 Page 0 / Register 38: BIT READ/ WRITE RESET VALUE D7–D5 R 000 D4 R 0 D3–D1 R 000 D0 R 0 Submit Documentation Feedback DAC Flag Register 2 DESCRIPTION Reserved. Write only default values Left DAC PGA Status Flag 0: Gain applied in Left DAC PGA is not equal to Gain programmed in Control Register 1: Gain applied in Left DAC PGA is equal to Gain programmed in Control Register Reserved. Write only default values Right DAC PGA Status Flag 0: Gain applied in Right DAC PGA is not equal to Gain programmed in Control Register 1: Gain applied in Right DAC PGA is equal to Gain programmed in Control Register REGISTER MAP 113 TLV320AIC3254 Ultra Low Power Stereo Audio Codec With Embedded miniDSP SLAS549A – SEPTEMBER 2008 – REVISED OCTOBER 2008 6.2.39 Page 0 / Register 39-41: BIT READ/ WRITE RESET VALUE D7–D0 R 0000 0000 Reserved Register DESCRIPTION Reserved. Write only default values 6.2.40 Page 0 / Register 42: Sticky Flag Register 1 BIT READ/ WRITE RESET VALUE D7 R 0 Left DAC Overflow Status. This sticky flag will self clear on read 0: No overflow in Left DAC 1: Overflow has happened in Left DAC since last read of this register D6 R 0 Right DAC Overflow Status. This sticky flag will self clear on read 0: No overflow in Right DAC 1: Overflow has happened in Right DAC since last read of this register D5 R 0 DAC miniDSP Barrel Shifter Output Overflow Sticky Flag. Flag is reset on register reading D4 R 0 Reserved. Write only default value D3 R 0 Left ADC Overflow Status. This sticky flag will self clear on read 0: No overflow in Left ADC 1: Overflow has happened in Left ADC since last read of this register D2 R 0 Right ADC Overflow Status. This sticky flag will self clear on read 0: No overflow in Right ADC 1: Overflow has happened in Right ADC since last read of this register D1 R 0 ADC miniDSP Barrel Shifter Output Overflow Sticky Flag. Flag is reset on register reading D0 R 0 Reserved. Write only default value DESCRIPTION 6.2.41 Page 0 / Register 43: Interrupt Flag Register 1 BIT READ/ WRITE RESET VALUE D7 R 0 Left DAC Overflow Status. 0: No overflow in Left DAC 1: Overflow condition is present in Left ADC at the time of reading the register D6 R 0 Right DAC Overflow Status. 0: No overflow in Right DAC 1: Overflow condition is present in Right DAC at the time of reading the register D5 R 0 DAC miniDSP Barrel Shifter Output Overflow Flag. Overflow condition is present at the time of reading the register D4 R 0 Reserved. Write only default value D3 R 0 Left ADC Overflow Status. 0: No overflow in Left ADC 1: Overflow condition is present in Left ADC at the time of reading the register D2 R 0 Right ADC Overflow Status. 0: No overflow in Right ADC 1: Overflow condition is present in Right ADC at the time of reading the register D1 R 0 ADC miniDSP Barrel Shifter Output Overflow Flag. Overflow condition is present at the time of reading the register D0 R 0 Reserved. Write only default value DESCRIPTION 6.2.42 Page 0 / Register 44: 114 www.ti.com Sticky Flag Register 2 BIT READ/ WRITE RESET VALUE D7 R 0 HPL Over Current Detect Flag 0: Over Current not detected on HPL 1: Over Current detected on HPL (will be cleared when the register is read) D6 R 0 HPR Over Current Detect Flag 0: Over Current not detected on HPR 1: Over Current detected on HPR (will be cleared when the register is read) REGISTER MAP DESCRIPTION Submit Documentation Feedback TLV320AIC3254 Ultra Low Power Stereo Audio Codec With Embedded miniDSP www.ti.com SLAS549A – SEPTEMBER 2008 – REVISED OCTOBER 2008 (continued) BIT READ/ WRITE RESET VALUE D5 R 0 Headset Button Press 0: Button Press not detected 1: Button Press detected (will be cleared when the register is read) D4 R 0 Headset Insertion/Removal Detect Flag 0: Insertion/Removal event not detected 1: Insertion/Removal event detected (will be cleared when the register is read) D3 R 0 Left Channel DRC, Signal Threshold Flag 0: Signal Power is below Signal Threshold 1: Signal Power exceeded Signal Threshold (will be cleared when the register is read) D2 R 0 Right Channel DRC, Signal Threshold Flag 0: Signal Power is below Signal Threshold 1: Signal Power exceeded Signal Threshold (will be cleared when the register is read) D1 R 0 DAC miniDSP Standard Interrupt Port Output. This is a sticky bit D0 R 0 DAC miniDSP Auxilliary Interrupt Port Output. This is a sticky bit DESCRIPTION 6.2.43 Page 0 / Register 45: Sticky Flag Register 3 BIT READ/ WRITE RESET VALUE D7 R 0 Reserved. D6 R 0 Left AGC Noise Threshold Flag 0: Signal Power is greater than Noise Threshold 1: Signal Power was lower than Noise Threshold (will be cleared when the register is read) D5 R 0 Right AGC Noise Threshold Flag 0: Signal Power is greater than Noise Threshold 1: Signal Power was lower than Noise Threshold (will be cleared when the register is read) D4 R 0 ADC miniDSP Standard Interrupt Port Output. This is a sticky bit D3 R 0 ADC miniDSP Auxilliary Interrupt Port Output. This is a sticky bit D2 R 0 Left ADC DC Measurement Data Available Flag 0: Data not available 1: Data available (will be cleared when the register is read) D1 R 0 Right ADC DC Measurement Data Available Flag 0: Data not available 1: Data available (will be cleared when the register is read) D0 R 0 Reserved DESCRIPTION 6.2.44 Page 0 / Register 46: Interrupt Flag Register 2 BIT READ/ WRITE RESET VALUE D7 R 0 HPL Over Current Detect Flag 0: Over Current not detected on HPL 1: Over Current detected on HPL D6 R 0 HPR Over Current Detect Flag 0: Over Current not detected on HPR 1: Over Current detected on HPR D5 R 0 Headset Button Press 0: Button Press not detected 1: Button Press detected D4 R 0 Headset Insertion/Removal Detect Flag 0: Headset removal detected 1: Headset insertion detected D3 R 0 Left Channel DRC, Signal Threshold Flag 0: Signal Power is below Signal Threshold 1: Signal Power exceeded Signal Threshold D2 R 0 Right Channel DRC, Signal Threshold Flag 0: Signal Power is below Signal Threshold 1: Signal Power exceeded Signal Threshold Submit Documentation Feedback DESCRIPTION REGISTER MAP 115 TLV320AIC3254 Ultra Low Power Stereo Audio Codec With Embedded miniDSP SLAS549A – SEPTEMBER 2008 – REVISED OCTOBER 2008 www.ti.com (continued) BIT READ/ WRITE RESET VALUE D1 R 0 DAC miniDSP Standard Interrupt Port Output. This bit shows the instantaneous value of miniDSP interrupt port at the time of reading the register D0 R 0 DAC miniDSP Auxilliary Interrupt Port Output. This bit shows the instantaneous value of miniDSP interrupt port at the time of reading the register DESCRIPTION 6.2.45 Page 0 / Register 47: BIT READ/ WRITE RESET VALUE D7 R 0 Reserved. D6 R 0 Left AGC Noise Threshold Flag 0: Signal Power is greater than Noise Threshold 1: Signal Power was lower than Noise Threshold D5 R 0 Right AGC Noise Threshold Flag 0: Signal Power is greater than Noise Threshold 1: Signal Power was lower than Noise Threshold D4 R 0 ADC miniDSP Standard Interrupt Port Output. This bit shows the instantaneous value of the interrupt port at the time of reading the register D3 R 0 ADC miniDSP Auxilliary Interrupt Port Output. This bit shows the instantaneous value of the interrupt port at the time of reading the register D2 R 0 Left ADC DC Measurement Data Available Flag 0: Data not available 1: Data available D1 R 0 Right ADC DC Measurement Data Available Flag 0: Data not available 1: Data available D0 R 0 Reserved DESCRIPTION 6.2.46 Page 0 / Register 48: 116 Interrupt Flag Register 3 INT1 Interrupt Control Register BIT READ/ WRITE RESET VALUE D7 R/W 0 INT1 Interrupt for Headset Insertion Event 0: Headset Insertion event will not generate a INT1 interrupt 1: Headset Insertion even will generate a INT1 interrupt D6 R/W 0 INT1 Interrupt for Button Press Event 0: Button Press event will not generate a INT1 interrupt 1: Button Press event will generate a INT1 interrupt D5 R/W 0 INT1 Interrupt for DAC DRC Signal Threshold 0: DAC DRC Signal Power exceeding Signal Threshold will not generate a INT1 interrupt 1: DAC DRC Signal Power exceeding Signal Threshold for either of Left or Right Channel will generate a INT1 interrupt. Read Page-0, Register-44 to distinguish between Left or Right Channel D4 R/W 0 INT1 Interrupt for AGC Noise Interrupt 0: Noise level detected by AGC will not generate a INT1 interrupt 1: Noise level detected by either off Left or Right Channel AGC will generate a INT1 interrupt. Read Page-0, Register-45 to distinguish between Left or Right Channel D3 R/W 0 INT1 Interrupt for Over Current Condition 0: Headphone Over Current condition will not generate a INT1 interrupt. 1: Headphone Over Current condition on either off Left or Right Channels will generate a INT1 interrupt. Read Page-0, Register-44 to distinguish between HPL and HPR D2 R/W 0 INT1 Interrupt for overflow event 0: ADC or DAC miniDSP generated interrupt does not result in a INT1 interrupt 1: ADC or DAC miniDSP generated interrupt will result in a INT1 interrupt. Read Page-0, Register-42 to distinguish between ADC or DAC.miniDSP interrupt D1 R/W 0 INT1 Interrupt for DC Measurement 0: DC Measurement data available will not generate INT1 interrupt 1: DC Measurement data available will generate INT1 interrupt REGISTER MAP DESCRIPTION Submit Documentation Feedback TLV320AIC3254 Ultra Low Power Stereo Audio Codec With Embedded miniDSP www.ti.com SLAS549A – SEPTEMBER 2008 – REVISED OCTOBER 2008 (continued) BIT READ/ WRITE RESET VALUE D0 R/W 0 DESCRIPTION INT1 pulse control 0: INT1 is active high interrupt of 1 pulse of approx. 2ms duration 1: INT1 is active high interrupt of multiple pulses, each of duration 2ms. To stop the pulse train, read Page-0, Reg-42d, 44d or 45d 6.2.47 Page 0 / Register 49: INT2 Interrupt Control Register BIT READ/ WRITE RESET VALUE D7 R/W 0 INT2 Interrupt for Headset Insertion Event 0: Headset Insertion event will not generate a INT2 interrupt 1: Headset Insertion even will generate a INT2 interrupt D6 R/W 0 INT2 Interrupt for Button Press Event 0: Button Press event will not generate a INT2 interrupt 1: Button Press event will generate a INT2 interrupt D5 R/W 0 INT2 Interrupt for DAC DRC Signal Threshold 0: DAC DRC Signal Power exceeding Signal Threshold will not generate a INT2 interrupt 1: DAC DRC Signal Power exceeding Signal Threshold for either of Left or Right Channel will generate a INT2 interrupt. Read Page-0, Register-44 to distinguish between Left or Right Channel D4 R/W 0 INT2 Interrupt for AGC Noise Interrupt 0: Noise level detected by AGC will not generate a INT2 interrupt 1: Noise level detected by either off Left or Right Channel AGC will generate a INT2 interrupt. Read Page-0, Register-45 to distinguish between Left or Right Channel D3 R/W 0 INT2 Interrupt for Over Current Condition 0: Headphone Over Current condition will not generate a INT2 interrupt. 1: Headphone Over Current condition on either off Left or Right Channels will generate a INT2 interrupt. Read Page-0, Register-44 to distinguish between HPL and HPR D2 R/W 0 INT2 Interrupt for overflow event 0: ADC or DAC miniDSP generated interrupt will not result in a INT2 interrupt 1: ADC or DAC miniDSP generated interrupt will result in a INT2 interrupt. Read Page-0, Register-42 to distinguish between ADC or DAC. D1 R/W 0 INT2 Interrupt for DC Measurement 0: DC Measurement data available will not generate INT2 interrupt 1: DC Measurement data available will generate INT2 interrupt D0 R/W 0 INT2 pulse control 0: INT2 is active high interrupt of 1 pulse of approx. 2ms duration 1: INT2 is active high interrupt of multiple pulses, each of duration 2ms. To stop the pulse train, read Page-0, Reg-42d, 44d and 45d DESCRIPTION 6.2.48 Page 0 / Register 50-51: BIT READ/ WRITE RESET VALUE D7–D0 R 0000 0000 DESCRIPTION Reserved. Write only default values 6.2.49 Page 0 / Register 52: BIT READ/ WRITE RESET VALUE D7–D6 R 00 Submit Documentation Feedback GPIO/MFP5 Control Register DESCRIPTION Reserved. Write only default values REGISTER MAP 117 TLV320AIC3254 Ultra Low Power Stereo Audio Codec With Embedded miniDSP SLAS549A – SEPTEMBER 2008 – REVISED OCTOBER 2008 www.ti.com (continued) BIT READ/ WRITE RESET VALUE D5–D2 R/W 0000 D1 R X GPIO Input Pin state, used along with GPIO as general purpose input D0 R/W 0 GPIO as general purpose output control 0: GPIO pin is driven to '0' in general purpose output mode 1: GPIO pin is driven to '1' in general purpose output mode DESCRIPTION GPIO Control 0000: GPIO input/output disabled. 0001: GPIO input is used for secondary audio interface, digital microphone input or clock input. Configure other registers to choose the functionality of GPIO input 0010: GPIO is general purpose input 0011: GPIO is general purpose output 0100: GPIO output is CLKOUT 0101: GPIO output is INT1 0110: GPIO output is INT2 0111: GPIO output is ADC_WCLK for Audio Interface 1000: GPIO output is secondary bit-clock for Audio Interface 1001: GPIO output is secondary word-clock for Audio Interface 1010: GPIO output is clock for digital microphone 1011-1111: Reserved. Do not use. 6.2.50 Page 0 / Register 53: DOUT/MFP2 Function Control Register READ/ WRITE RESET VALUE D7–D5 R 000 D4 R/W 1 D3–D1 R/W 001 DOUT MUX Control 000: DOUT disabled 001: DOUT is Primary DOUT 010: DOUT is General Purpose Output 011: DOUT is CLKOUT 100: DOUT is INT1 101: DOUT is INT2 110: DOUT is Secondary BCLK 111: DOUT is Secondary WCLK D0 R/W 0 DOUT as General Purpose Output 0: DOUT General Purpose Output is '0' 1: DOUT General Purpose Output is '1' BIT DESCRIPTION Reserved. Write only default values DOUT Bus Keeper Control 0: DOUT Bus Keeper Enabled 1: DOUT Bus Keeper Disabled 6.2.51 Page 0 / Register 54: DIN/MFP1 Function Control Register BIT READ/ WRITE RESET VALUE D7–D3 R 0 0000 D2–D1 R/W 01 DIN function control 00: DIN pin is disabled 01: DIN is enabled for Primary Data Input or Digital Microphone Input or General Purpose Clock input 10: DIN is used as General Purpose Input 11: Reserved. Do not use D0 R X Value of DIN input pin. To be used when for General Purpose Input DESCRIPTION Reserved. Write only reserved values 6.2.52 Page 0 / Register 55: BIT READ/ WRITE RESET VALUE D7–D5 R 000 118 REGISTER MAP MISO/MFP4 Function Control Register DESCRIPTION Reserved. Write only default values Submit Documentation Feedback TLV320AIC3254 Ultra Low Power Stereo Audio Codec With Embedded miniDSP www.ti.com SLAS549A – SEPTEMBER 2008 – REVISED OCTOBER 2008 (continued) BIT READ/ WRITE RESET VALUE D4–D1 R/W 0001 D0 R/W 0 DESCRIPTION MISO function control 0000: MISO buffer disabled 0001: MISO is used for data output in SPI interface, is disabled for I2C interface 0010: MISO is General Purpose Output 0011: MISO is CLKOUT output 0100: MISO is INT1 output 0101: MISO is INT2 output 0110: MISO is ADC Word Clock output 0111: MISO is clock output for Digital Microphone 1000: MISO is Secondary Data Output for Audio Interface 1001: MISO is Secondary Bit Clock for Audio Interface 1010: MISO is Secondary Word Clock for Audio Interface 1011-1111: Reserved. Do not use Value to be driven on MISO pin when used as General Purpose Output 6.2.53 Page 0 / Register 56: SCLK/MFP3 Function Control Register READ/ WRITE RESET VALUE D7–D3 R 0 0000 D2–D1 R/W 01 SCLK function control 00: SCLK pin is disabled 01: SCLK pin is enabled for SPI clock in SPI Interface mode or when in I2C Interface enabled for Secondary Data Input or Secondary Bit Clock Input or Secondary Word Clock or Secondary ADC Word Clock or Digital Microphone Input 10: SCLK is enabled as General Purpose Input 11: Reserved. Do not use D0 R X Value of SCLK input pin when used as General Purpose Input BIT DESCRIPTION Reserved. Write only default values 6.2.54 Page 0 / Register 57-59: BIT READ/ WRITE RESET VALUE D7–D0 R 0000 0000 Reserved Registers DESCRIPTION Reserved. Write only default values 6.2.55 Page 0 / Register 60: DAC Signal Processing Block Control Register BIT READ/ WRITE RESET VALUE D7 R/W 0 0: ADC and DAC miniDSP's are independently powered up 1: ADC and DAC miniDSP's are powered up together. Useful when there is data transfer between ADC and DAC miniDSP's D6 R/W 0 DAC miniDSP Power Configuration 0: DAC miniDSP is powered down with DAC Channel Power Down 1: DAC miniDSP is powered up if ADC Channel is powered up D5 R 0 Reserved. Write only default value D4–D0 R/W 0 0001 DESCRIPTION 0 0000: The DAC miniDSP will be used for signal processing 0 0001: DAC Signal Processing Block PRB_P1 0 0010: DAC Signal Processing Block PRB_P2 0 0011: DAC Signal Processing Block PRB_P3 0 0100: DAC Signal Processing Block PRB_P4 … 1 1000: DAC Signal Processing Block PRB_P24 1 1001: DAC Signal Processing Block PRB_P25 1 1010-1 1111: Reserved. Do not use 6.2.56 Page 0 / Register 61: BIT READ/ WRITE RESET VALUE D7–D5 R 000 Submit Documentation Feedback ADC Signal Processing Block Control Register DESCRIPTION Reserved. Write only default values REGISTER MAP 119 TLV320AIC3254 Ultra Low Power Stereo Audio Codec With Embedded miniDSP SLAS549A – SEPTEMBER 2008 – REVISED OCTOBER 2008 www.ti.com (continued) BIT READ/ WRITE RESET VALUE D4–D0 R/W 0 0001 DESCRIPTION 0 0000: The ADC miniDSP will be used for signal processing 0 0001: ADC Singal Processing Block PRB_R1 0 0010: ADC Signal Processing Block PRB_R2 0 0011: ADC Signal Processing Block PRB_R3 0 0100: ADC Signal Processing Block PRB_R4 … 1 0001: ADC Signal Processing Block PRB_R17 1 0010: ADC Signal Processing Block PRB_R18 1 0010-1 1111: Reserved. Do not use 6.2.57 Page 0 / Register 62: ADC and DAC miniDSP Configuration Register READ/ WRITE RESET VALUE D7 R 0 Reserved. Write only default values D6 R/W 0 ADC miniDSP Auxilliary Control Bit-A. Used for conditional instruction like JMP. D5 R/W 0 ADC miniDSP Auxilliary Control Bit-B. Used for conditional instruction like JMP. D4 R/W 0 0: Reset ADC miniDSP instruction counter at the start of new frame. 1: Do not reset ADC miniDSP instruction counter at the start of new frame. If ADC miniDSP is used for Signal Processing D3 R 0 Reserved. Write only default values D2 R/W 0 DAC miniDSP Auxilliary Control Bit-A. Used for conditional instruction like JMP. D1 R/W 0 DAC miniDSP Auxilliary Control Bit-B. Used for conditional instruction like JMP. D0 R/W 0 0: Reset DAC miniDSP instruction counter at the start of new frame. 1: Do not reset DAC miniDSP instruction counter at the start of new frame. If DAC miniDSP is used for Signal Processing BIT DESCRIPTION 6.2.58 Page 0 / Register 63: DAC Channel Setup Register 1 BIT READ/ WRITE RESET VALUE D7 R/W 0 Left DAC Channel Power Control 0: Left DAC Channel Powered Down 1: Left DAC Channel Powered Up D6 R/W 0 Right DAC Channel Power Control 0: Right DAC Channel Powered Down 1: Right DAC Channel Powered Up D5–D4 R/W 01 Left DAC Data path Control 00: Left DAC data is disabled 01: Left DAC data Left Channel Audio Interface Data 10: Left DAC data is Right Channel Audio Interface Data 11: Left DAC data is Mono Mix of Left and Right Channel Audio Interface Data D3–D2 R/W 01 Right DAC Data path Control 00: Right DAC data is disabled 01: Right DAC data Right Channel Audio Interface Data 10: Right DAC data is Left Channel Audio Interface Data 11: Right DAC data is Mono Mix of Left and Right Channel Audio Interface Data D1–D0 R/W 00 DAC Channel Volume Control's Soft-Step control 00: Soft-Stepping is 1 step per 1 DAC Word Clock 01: Soft-Stepping is 1 step per 2 DAC Word Clocks 10: Soft-Stepping is disabled 11: Reserved. Do not use 120 REGISTER MAP DESCRIPTION Submit Documentation Feedback TLV320AIC3254 Ultra Low Power Stereo Audio Codec With Embedded miniDSP www.ti.com SLAS549A – SEPTEMBER 2008 – REVISED OCTOBER 2008 6.2.59 Page 0 / Register 64: BIT READ/ WRITE RESET VALUE D7 R/W 0 D6–D4 R/W 000 DAC Channel Setup Register 2 DESCRIPTION Right Modulator Output Control 0: When Right DAC Channel is powered down, the data is zero. 1: When Right DAC Channel is powered down, the data is inverted version of Left DAC Modulator Output. Can be used when differential mono output is used DAC Auto Mute Control 000: Auto Mute disabled 001: DAC is auto muted if 010: DAC is auto muted if 011: DAC is auto muted if 100: DAC is auto muted if 101: DAC is auto muted if 110: DAC is auto muted if 111: DAC is auto muted if input data input data input data input data input data input data input data is is is is is is is DC for DC for DC for DC for DC for DC for DC for more more more more more more more than than than than than than than 100 consecutive inputs 200 consecutive inputs 400 consecutive inputs 800 consecutive inputs 1600 consecutive inputs 3200 consecutive inputs 6400 consecutive inputs D3 R/W 1 Left DAC Channel Mute Control 0: Left DAC Channel not muted 1: Left DAC Channel muted D2 R/W 1 Right DAC Channel Mute Control 0: Right DAC Channel not muted 1: Right DAC Channel muted D1–D0 R/W 00 DAC Master Volume Control 00: Left and Right Channel have independent volume control 01: Left Channel Volume is controlled by Right Channel Volume Control setting 10: Right Channel Volume is controlled by Left Channel Volume Control setting 11: Reserved. Do not use 6.2.60 Page 0 / Register 65: BIT READ/ WRITE RESET VALUE D7–D0 R/W 0000 0000 DESCRIPTION Left DAC Channel Digital Volume Control Setting 0111 1111-0011 0001: Reserved. Do not use 0011 0000: Digital Volume Control = +24dB 0010 1111: Digital Volume Control = +23.5dB … 0000 0001: Digital Volume Control = +0.5dB 0000 0000: Digital Volume Control = 0.0dB 1111 1111: Digital Volume Control = -0.5dB ... 1000 0010: Digital Volume Control = -63dB 1000 0001: Digital Volume Control = -63.5dB 1000 0000: Reserved. Do not use 6.2.61 Page 0 / Register 66: BIT READ/ WRITE RESET VALUE D7–D0 R/W 0000 0000 Submit Documentation Feedback Left DAC Channel Digital Volume Control Register Right DAC Channel Digital Volume Control Register DESCRIPTION Right DAC Channel Digital Volume Control Setting 0111 1111-0011 0001: Reserved. Do not use 0011 0000: Digital Volume Control = +24dB 0010 1111: Digital Volume Control = +23.5dB … 0000 0001: Digital Volume Control = +0.5dB 0000 0000: Digital Volume Control = 0.0dB 1111 1111: Digital Volume Control = -0.5dB ... 1000 0010: Digital Volume Control = -63dB 1000 0001: Digital Volume Control = -63.5dB 1000 0000: Reserved. Do not use REGISTER MAP 121 TLV320AIC3254 Ultra Low Power Stereo Audio Codec With Embedded miniDSP SLAS549A – SEPTEMBER 2008 – REVISED OCTOBER 2008 6.2.62 Page 0 / Register 67: www.ti.com Headset Detection Configuration Register BIT READ/ WRITE RESET VALUE D7 R/W 0 0: Headset Detection Disabled 1: Headset Detection Enabled D6–D5 R 00 Headset Type Flag 00: Headset not detected 01: Stereo Headset detected 10: Reserved 11: Stereo + Cellular Headset detected D4–D2 R/W 000 Headset Detection Debounce Programmability 000: Debounce Time = 16ms 001: Debounce Time = 32ms 010: Debounce Time = 64ms 011: Debounce Time = 128ms 100: Debounce Time = 256ms 101: Debounce Time = 512ms 110-111: Reserved. Do not use Note: All times are typical values D1–D0 R/W 00 Headset Button Press Debounce Programmability 00: Debounce disabled 01: Debounce Time = 8ms 10: Debounce Time = 16ms 11: Debounce Time = 32ms Note: All times are typical values DESCRIPTION 6.2.63 Page 0 / Register 68: DRC Control Register 1 READ/ WRITE RESET VALUE D7 R 0 Reserved. Write only default value D6 R/W 0 DRC Enable Control 0: Left Channel DRC disabled 1: Left Channel DRC enabled D5 R/W 0 DRC Enable Control 0: Right Channel DRC disabled 1: Right Channel DRC enabled D4–D2 R/W 011 DRC Threshold control 000: DRC Threshold = -3dBFS 001: DRC Threshold = -6dBFS 010: DRC Threshold = -9dBFS 011: DRC Threshold = -12dBFS 100: DRC Threshold = -15dBFS 101: DRC Threshold = -18dBFS 110: DRC Threshold = -21dBFS 111: DRC Threshold = -24dBFS D1–D0 R/W 11 DRC Hysteresis Control 00: DRC Hysteresis = 0dB 01: DRC Hysteresis = 1dB 10: DRC Hysteresis = 2dB 11: DRC Hysteresis = 3dB BIT DESCRIPTION 6.2.64 Page 0 / Register 69: 122 BIT READ/ WRITE RESET VALUE D7 R 0 REGISTER MAP DRC Control Register 2 DESCRIPTION Reserved. Write only default value. Submit Documentation Feedback TLV320AIC3254 Ultra Low Power Stereo Audio Codec With Embedded miniDSP www.ti.com SLAS549A – SEPTEMBER 2008 – REVISED OCTOBER 2008 (continued) BIT READ/ WRITE RESET VALUE D6–D3 R/W 0111 DRC Hold Programmability 0000: DRC Hold Disabled 0001: DRC Hold Time = 32 DAC Word Clocks 0010: DRC Hold Time = 64 DAC Word Clocks 0011: DRC Hold Time = 128 DAC Word Clocks 0100: DRC Hold Time = 256 DAC Word Clocks 0101: DRC Hold Time = 512 DAC Word Clocks ... 1110: DRC Hold Time = 4*32768 DAC Word Clocks 1111: DRC Hold Time = 5*32768 DAC Word Clocks D2–D0 R/W 000 Reserved. Write only default values DESCRIPTION 6.2.65 Page 0 / Register 70: DRC Control Register 3 BIT READ/ WRITE RESET VALUE D7–D4 R/W 0000 DRC Attack Rate control 0000: DRC Attack Rate = 4.0dB per DAC Word Clock 0001: DRC Attack Rate = 2.0dB per DAC Word Clock 0010: DRC Attack Rae = 1.0dB per DAC Word Clock … 1110: DRC Attack Rate = 2.4414e-4dB per DAC Word Clock 1111: DRC Attack Rate = 1.2207e-4dB per DAC Word Clock D3–D0 R/W 0000 DRC Decay Rate control 0000: DRC Decay Rate = 1.5625e-2dB per DAC Word Clock 0001: DRC Decay Rate = 7.8125e-3dB per DAC Word Clock 0010: DRC Decay Rae = 3.9062e-3dB per DAC Word Clock … 1110: DRC Decay Rate = 9.5367e-7dB per DAC Word Clock 1111: DRC Decay Rate = 4.7683e-7dB per DAC Word Clock DESCRIPTION 6.2.66 Page 0 / Register 71: Beep Generator Register 1 BIT READ/ WRITE RESET VALUE D7 R/W 0 0: Beep Generator Disabled 1: Beep Generator Enabled. This bit will self clear after the beep has been generated. D6 R 0 Reserved. Write only default value D5–D0 R/W 00 0000 DESCRIPTION Left Channel Beep Volume Control 00 0000: Left Channel Beep Volume 00 0001: Left Channel Beep Volume … 11 1110: Left Channel Beep Volume 11 1111: Left Channel Beep Volume 6.2.67 Page 0 / Register 72: BIT READ/ WRITE RESET VALUE D7–D6 R/W 00 D5–D0 R 00 0000 Submit Documentation Feedback = 0dB = -1dB = -62dB = -63dB Beep Generator Register 2 DESCRIPTION Beep Generator Master Volume Control Setting 00: Left and Right Channels have independent Volume Settings 01: Left Channel Beep Volume is the same as programmed for Right Channel 10: Right Channel Beep Volume is the same as programmed for Left Channel 11: Reserved. Do not use Right Channel Beep Volume Control 00 0000: Right Channel Beep Volume = 00 0001: Right Channel Beep Volume = … 11 1110: Right Channel Beep Volume = 11 1111: Right Channel Beep Volume = 0dB -1dB -62dB -63dB REGISTER MAP 123 TLV320AIC3254 Ultra Low Power Stereo Audio Codec With Embedded miniDSP SLAS549A – SEPTEMBER 2008 – REVISED OCTOBER 2008 6.2.68 Page 0 / Register 73: BIT READ/ WRITE RESET VALUE D7–D0 R/W 0000 0000 READ/ WRITE RESET VALUE D7–D0 R/W 0000 0000 Programmed value is Beep Sample Length(23:16) BIT RESET VALUE D7–D0 R/W 1110 1110 Programmed value is Beep Sample Length(15:8) READ/ WRITE RESET VALUE D7–D0 R/W 0001 0000 Programmed value is Beep Sample Length(7:0) READ/ WRITE RESET VALUE D7–D0 R/W 1101 1000 Programmed Value is Beep Sin(x)(15:8), where Sin(x) = sin(2*pi*Fin/Fs), where Fin is desired beep frequency and Fs is DAC sample rate READ/ WRITE RESET VALUE D7–D0 R/W 0111 1110 Programmed Value is Beep Sin(x)(7:0), where Sin(x) = sin(2*pi*Fin/Fs), where Fin is desired beep frequency and Fs is DAC sample rate READ/ WRITE RESET VALUE D7–D0 R/W 1110 0011 Programmed Value is Beep Cos(x)(15:8), where Cos(x) = cos(2*pi*Fin/Fs), where Fin is desired beep frequency and Fs is DAC sample rate READ/ WRITE RESET VALUE D7–D0 R 0000 0000 Programmed Value is Beep Cos(x)(7:0), where Cos(x) = cos(2*p*Fin/Fs), where Fin is desired beep frequency and Fs is DAC sample rate 124 READ/ WRITE RESET VALUE D7 R/W 0 REGISTER MAP Reserved DESCRIPTION Reserved. Write only default values 6.2.76 Page 0 / Register 81: BIT Beep Generator Register 9 DESCRIPTION 6.2.75 Page 0 / Register 80: BIT Beep Generator Register 8 DESCRIPTION 6.2.74 Page 0 / Register 79: BIT Beep Generator Register 7 DESCRIPTION 6.2.73 Page 0 / Register 78: BIT Beep Generator Register 6 DESCRIPTION 6.2.72 Page 0 / Register 77: BIT Beep Generator Register 5 DESCRIPTION 6.2.71 Page 0 / Register 76: BIT Beep Generator Register 4 DESCRIPTION 6.2.70 Page 0 / Register 75: READ/ WRITE Beep Generator Register 3 DESCRIPTION 6.2.69 Page 0 / Register 74: BIT www.ti.com ADC Channel Setup Register DESCRIPTION Left Channel ADC Power Control 0: Left Channel ADC is powered down 1: Left Channel ADC is powered up Submit Documentation Feedback TLV320AIC3254 Ultra Low Power Stereo Audio Codec With Embedded miniDSP www.ti.com SLAS549A – SEPTEMBER 2008 – REVISED OCTOBER 2008 (continued) BIT READ/ WRITE RESET VALUE D6 R/W 0 Right Channel ADC Power Control 0: Right Channel ADC is powered down 1: Right Channel ADC is powered up D5–D4 R/W 00 Digital Microphone Input Configuration 00: GPIO serves as Digital Microphone Input 01: SCLK serves as Digital Microphone Input 10: DIN serves as Digital Microphone Input 11: Reserved. Do not use D3 R/W 0 Left Channel Digital Microphone Power Control 0: Left Channel ADC not configured for Digital Microphone 1: Left Channel ADC configured for Digital Microphone D2 R/W 0 Right Channel Digital Microphone Power Control 0: Right Channel ADC not configured for Digital Microphone 1: Right Channel ADC configured for Digital Microphone D1–D0 R/W 00 ADC Volume Control Soft-Stepping Control 00: ADC Volume Control changes by 1 gain step per ADC Word Clock 01: ADC Volume Control changes by 1 gain step per two ADC Word Clocks 10: ADC Volume Control Soft-Stepping disabled 11: Reserved. Do not use DESCRIPTION 6.2.77 Page 0 / Register 82: BIT READ/ WRITE RESET VALUE D7 R/W 1 D6–D4 R/W 000 D3 R/W 1 D2–D0 R/W 000 DESCRIPTION Left ADC Channel Mute Control 0: Left ADC Channel Un-muted 1: Left ADC Channel Muted Left ADC Channel Fine Gain Adjust 000: Left ADC Channel Fine Gain = 0dB 001: Left ADC Channel Fine Gain = -0.1dB 010: Left ADC Channel Fine Gain = -0.2dB 011: Left ADC Channel Fine Gain = -0.3dB 100: Left ADC Channel Fine Gain = -0.4dB 101-111: Reserved. Do not use Right ADC Channel Mute Control 0: Right ADC Channel Un-muted 1: Right ADC Channel Muted Right ADC Channel Fine Gain Adjust 000: Right ADC Channel Fine Gain = 0dB 001: Right ADC Channel Fine Gain = -0.1dB 010: Right ADC Channel Fine Gain = -0.2dB 011: Right ADC Channel Fine Gain = -0.3dB 100: Right ADC Channel Fine Gain = -0.4dB 101-111: Reserved. Do not use 6.2.78 Page 0 / Register 83: BIT READ/ WRITE RESET VALUE D7 R 0 Submit Documentation Feedback ADC Fine Gain Adjust Register Left ADC Channel Volume Control Register DESCRIPTION Reserved. Write only default values REGISTER MAP 125 TLV320AIC3254 Ultra Low Power Stereo Audio Codec With Embedded miniDSP SLAS549A – SEPTEMBER 2008 – REVISED OCTOBER 2008 www.ti.com (continued) BIT READ/ WRITE RESET VALUE D6–D0 R/W 000 0000 DESCRIPTION Left ADC Channel Volume Control 100 0000-110 1000: Reserved. Do not use 110 0111: Left ADC Channel Volume = -12dB 110 0110: Left ADC Channel Volume = -11.5dB 110 0101: Left ADC Channel Volume = -11.0dB … 111 1111: Left ADC Channel Volume = -0.5dB 000 0000: Left ADC Channel Volume = 0.0dB 000 0001: Left ADC Channel Volume = 0.5dB ... 010 0110: Left ADC Channel Volume = 19.0dB 010 0111: Left ADC Channel Volume = 19.5dB 010 1000: Left ADC Channel Volume = 20.0dB 010 1001-011 1111: Reserved. Do not use 6.2.79 Page 0 / Register 84: READ/ WRITE BIT Right ADC Channel Volume Control Register RESET VALUE D7 R 0 D6–D0 R/W 000 0000 DESCRIPTION Reserved. Write only default values Right ADC Channel Volume Control 100 0000-110 1000: Reserved. Do not use 110 0111: Right ADC Channel Volume = -12dB 110 0110: Right ADC Channel Volume = -11.5dB 110 0101: Right ADC Channel Volume = -11.0dB … 111 1111: Right ADC Channel Volume = -0.5dB 000 0000: Right ADC Channel Volume = 0.0dB 000 0001: Right ADC Channel Volume = 0.5dB ... 010 0110: Right ADC Channel Volume = 19.0dB 010 0111: Right ADC Channel Volume = 19.5dB 010 1000: Right ADC Channel Volume = 20.0dB 010 1001-011 1111: Reserved. Do not use 6.2.80 Page 0 / Register 85: BIT READ/ WRITE RESET VALUE D7–D0 R/W 0000 0000 ADC Phase Adjust Register DESCRIPTION ADC Phase Compensation Control 1000 0000-1111 1111: Left ADC Channel Data is delayed with respect to Right ADC Channel Data. For details of delayed amount please refer to the description of Phase Compensation in the Overview section. 0000 0000: Left and Right ADC Channel data are not delayed with respect to each other 0000 0001-0111 1111: Right ADC Channel Data is delayed with respect to Left ADC Channel Data. For details of delayed amount please refer to the description of Phase Compensation in the Overview section. 6.2.81 Page 0 / Register 86: Left Channel AGC Control Register 1 BIT READ/ WRITE RESET VALUE D7 R/W 0 D6–D4 R/W 000 Left Channel AGC Target Level Setting 000: Left Channel AGC Target Level = -5.5dBFS 001: Left Channel AGC Target Level = -8.0dBFS 010: Left Channel AGC Target Level = -10.0dBFS 011: Left Channel AGC Target Level = -12.0dBFS 100: Left Channel AGC Target Level = -14.0dBFS 101: Left Channel AGC Target Level = -17.0dBFS 110: Left Channel AGC Target Level = -20.0dBFS 111: Left Channel AGC Target Level = -24.0dBFS D3–D2 R 00 Reserved. Write only default values 126 REGISTER MAP DESCRIPTION 0: Left Channel AGC Disabled 1: Left Channel AGC Enabled Submit Documentation Feedback TLV320AIC3254 Ultra Low Power Stereo Audio Codec With Embedded miniDSP www.ti.com SLAS549A – SEPTEMBER 2008 – REVISED OCTOBER 2008 (continued) BIT READ/ WRITE RESET VALUE D1–D0 R/W 00 DESCRIPTION Left Channel AGC Gain Hysteresis Control 00: Left Channel AGC Gain Hysteresis is disabled 01: Left Channel AGC Gain Hysteresis is 0.5dB 10: Left Channel AGC Gain Hysteresis is 1.0dB 11: Left Channel AGC Gain Hysteresis is 1.5dB 6.2.82 Page 0 / Register 87: BIT READ/ WRITE RESET VALUE D7–D6 R/W 00 D5–D1 R/W 0 0000 D0 R 0 DESCRIPTION Left Channel AGC Hysteresis Setting 00: Left Channel AGC Hysteresis is 1.0dB 01: Left Channel AGC Hysteresis is 2.0dB 10: Left Channel AGC Hysteresis is 4.0dB 11: Left Channel AGC Hysteresis is disabled Left Channel AGC Noise Threshold 0 0000: Left Channel AGC Noise Gate disabled 0 0001: Left Channel AGC Noise Threshold is -30dB 0 0010: Left Channel AGC Noise Threshold is -32dB 0 0011: Left Channel AGC Noise Threshold is -34dB … 1 1101: Left Channel AGC Noise Threshold is -86dB 1 1110: Left Channel AGC Noise Threshold is -88dB 1 1111: Left Channel AGC Noise Threshold is -90dB Reserved. Write only default value 6.2.83 Page 0 / Register 88: BIT READ/ WRITE D7 R 0 R/W 111 1111 DESCRIPTION Reserved. Write only default value Left Channel AGC Maximum Gain Setting 000 0000: Left Channel AGC Maximum Gain = 0.0dB 000 0001: Left Channel AGC Maximum Gain = 0.5dB 000 0010: Left Channel AGC Maximum Gain = 1.0dB … 111 0011: Left Channel AGC Maximum Gain = 57.5dB 111 0100-111 1111: Left Channel AGC Maximum Gain = 58.0dB 6.2.84 Page 0 / Register 89: BIT READ/ WRITE RESET VALUE D7–D3 R/W 0 0000 R/W Left Channel AGC Control Register 3 RESET VALUE D6–D0 D2–D0 Left Channel AGC Control Register 2 000 Submit Documentation Feedback Left Channel AGC Control Register 4 DESCRIPTION Left Channel AGC Attack Time Setting 0 0000: Left Channel AGC Attack Time 0 0001: Left Channel AGC Attack Time 0 0010: Left Channel AGC Attack Time … 1 1101: Left Channel AGC Attack Time 1 1110: Left Channel AGC Attack Time 1 1111: Left Channel AGC Attack Time = 1*32 ADC Word Clocks = 3*32 ADC Word Clocks = 5*32 ADC Word Clocks = 59*32 ADC Word Clocks = 61*32 ADC Word Clocks = 63*32 ADC Word Clocks Left Channel AGC Attack Time Scale Factor Setting 000: Scale Factor = 1 001: Scale Factor = 2 010: Scale Factor = 4 … 101: Scale Factor = 32 110: Scale Factor = 64 111: Scale Factor = 128 REGISTER MAP 127 TLV320AIC3254 Ultra Low Power Stereo Audio Codec With Embedded miniDSP SLAS549A – SEPTEMBER 2008 – REVISED OCTOBER 2008 6.2.85 Page 0 / Register 90: BIT READ/ WRITE RESET VALUE D7–D3 R/W 0 0000 D2–D0 R/W 000 READ/ WRITE RESET VALUE D7–D5 R 000 D4–D0 R/W 0 0000 Left Channel AGC Control Register 5 DESCRIPTION Left Channel AGC Decay Time Setting 0 0000: Left Channel AGC Decay Time 0 0001: Left Channel AGC Decay Time 0 0010: Left Channel AGC Decay Time … 1 1101: Left Channel AGC Decay Time 1 1110: Left Channel AGC Decay Time 1 1111: Left Channel AGC Decay Time = 1*512 ADC Word Clocks = 3*512 ADC Word Clocks = 5*512 ADC Word Clocks = 59*512 ADC Word Clocks = 61*512 ADC Word Clocks = 63*512 ADC Word Clocks Left Channel AGC Decay Time Scale Factor Setting 000: Scale Factor = 1 001: Scale Factor = 2 010: Scale Factor = 4 … 101: Scale Factor = 32 110: Scale Factor = 64 111: Scale Factor = 128 6.2.86 Page 0 / Register 91: BIT www.ti.com Left Channel AGC Control Register 6 DESCRIPTION Reserved. Write only default values Left Channel AGC Noise Debounce Time Setting 0 0001: Left Channel AGC Noise Debounce Time 0 0010: Left Channel AGC Noise Debounce Time 0 0011: Left Channel AGC Noise Debounce Time … 0 1010: Left Channel AGC Noise Debounce Time 0 1011: Left Channel AGC Noise Debounce Time 0 1100: Left Channel AGC Noise Debounce Time 0 1101: Left Channel AGC Noise Debounce Time ... 1 1101: Left Channel AGC Noise Debounce Time 1 1110: Left Channel AGC Noise Debounce Time 1 1111: Left Channel AGC Noise Debounce Time 6.2.87 Page 0 / Register 92: RESET VALUE D7–D4 R 0000 Reserved. Write only default values D3–D0 R/W 0000 Left Channel AGC Signal Debounce Time Setting 0001: Left Channel AGC Signal Debounce Time = 0010: Left Channel AGC Signal Debounce Time = 0011: Left Channel AGC Signal Debounce Time = … 1001: Left Channel AGC Signal Debounce Time = 1010: Left Channel AGC Signal Debounce Time = 1011: Left Channel AGC Signal Debounce Time = 1100: Left Channel AGC Signal Debounce Time = 1101: Left Channel AGC Signal Debounce Time = 1110: Left Channel AGC Signal Debounce Time = 1111: Left Channel AGC Signal Debounce Time = 128 REGISTER MAP = = = = 2048 ADC Word Clocks 4096 ADC Word Clocks 2*4096 ADC Word Clocks 3*4096 ADC Word Clocks = 19*4096 ADC Word Clocks = 20*4096 ADC Word Clocks = 21*4096 ADC Word Clocks Left Channel AGC Control Register 7 READ/ WRITE BIT =0 = 4 ADC Word Clocks = 8 ADC Word Clocks DESCRIPTION 0 4 ADC Word Clocks 8 ADC Word Clocks 1024 ADC Word Clocks 2048 ADC Word Clocks 2*2048 ADC Word Clocks 3*2048 ADC Word Clocks 4*2048 ADC Word Clocks 5*2048 ADC Word Clocks 6*2048 ADC Word Clocks Submit Documentation Feedback TLV320AIC3254 Ultra Low Power Stereo Audio Codec With Embedded miniDSP www.ti.com SLAS549A – SEPTEMBER 2008 – REVISED OCTOBER 2008 6.2.88 Page 0 / Register 93: BIT READ/ WRITE RESET VALUE D7–D0 R 0000 0000 Left Channel AGC Control Register 8 DESCRIPTION Left Channel AGC Gain Flag 1111 0100: Left Channel AGC Gain 1111 0101: Left Channel AGC Gain 1111 0110: Left Channel AGC Gain … 0000 0000: Left Channel AGC Gain … 0111 0010: Left Channel AGC Gain 0111 0011: Left Channel AGC Gain 0111 0100: Left Channel AGC Gain 6.2.89 Page 0 / Register 94: = -12.0dB = -11.5dB = -11.0dB = 0.0dB = 57.0dB = 57.5dB = 58.0dB Right Channel AGC Control Register 1 BIT READ/ WRITE RESET VALUE D7 R/W 0 D6–D4 R/W 000 Right Channel AGC Target Level Setting 000: Right Channel AGC Target Level = -5.5dBFS 001: Right Channel AGC Target Level = -8.0dBFS 010: Right Channel AGC Target Level = -10.0dBFS 011: Right Channel AGC Target Level = -12.0dBFS 100: Right Channel AGC Target Level = -14.0dBFS 101: Right Channel AGC Target Level = -17.0dBFS 110: Right Channel AGC Target Level = -20.0dBFS 111: Right Channel AGC Target Level = -24.0dBFS D3–D2 R 00 Reserved. Write only default values D1–D0 R/W 00 Right Channel AGC Gain Hysteresis Control 00: Right Channel AGC Gain Hysteresis is disabled 01: Right Channel AGC Gain Hysteresis is 0.5dB 10: Right Channel AGC Gain Hysteresis is 1.0dB 11: Right Channel AGC Gain Hysteresis is 1.5dB DESCRIPTION 0: Right Channel AGC Disabled 1: Right Channel AGC Enabled 6.2.90 Page 0 / Register 95: BIT READ/ WRITE RESET VALUE D7–D6 R/W 00 D5–D1 R/W 0 0000 D0 R 0 DESCRIPTION Right Channel AGC Hysteresis Setting 00: Right Channel AGC Hysteresis is 1.0dB 01: Right Channel AGC Hysteresis is 2.0dB 10: Right Channel AGC Hysteresis is 4.0dB 11: Right Channel AGC Hysteresis is disabled Right Channel AGC Noise Threshold 0 0000: Right Channel AGC Noise Gate disabled 0 0001: Right Channel AGC Noise Threshold is -30dB 0 0010: Right Channel AGC Noise Threshold is -32dB 0 0011: Right Channel AGC Noise Threshold is -34dB … 1 1101: Right Channel AGC Noise Threshold is -86dB 1 1110: Right Channel AGC Noise Threshold is -88dB 1 1111: Right Channel AGC Noise Threshold is -90dB Reserved. Write only default value 6.2.91 Page 0 / Register 96: BIT READ/ WRITE RESET VALUE D7 R 0 Submit Documentation Feedback Right Channel AGC Control Register 2 Right Channel AGC Control Register 3 DESCRIPTION Reserved. Write only default value REGISTER MAP 129 TLV320AIC3254 Ultra Low Power Stereo Audio Codec With Embedded miniDSP SLAS549A – SEPTEMBER 2008 – REVISED OCTOBER 2008 www.ti.com (continued) BIT READ/ WRITE RESET VALUE D6–D0 R/W 111 1111 DESCRIPTION Right Channel AGC Maximum Gain Setting 000 0000: Right Channel AGC Maximum Gain = 0.0dB 000 0001: Right Channel AGC Maximum Gain = 0.5dB 000 0010: Right Channel AGC Maximum Gain = 1.0dB … 111 0011: Right Channel AGC Maximum Gain = 57.5dB 111 0100-111 1111: Right Channel AGC Maximum Gain = 58.0dB 6.2.92 Page 0 / Register 97: BIT READ/ WRITE RESET VALUE D7–D3 R/W 0 0000 D2–D0 R/W 000 DESCRIPTION Right Channel AGC Attack Time Setting 0 0000: Right Channel AGC Attack Time 0 0001: Right Channel AGC Attack Time 0 0010: Right Channel AGC Attack Time … 1 1101: Right Channel AGC Attack Time 1 1110: Right Channel AGC Attack Time 1 1111: Right Channel AGC Attack Time READ/ WRITE RESET VALUE D7–D3 R/W 0 0000 D2–D0 R/W 000 READ/ WRITE RESET VALUE D7–D5 R 000 130 REGISTER MAP = 59*32 ADC Word Clocks = 61*32 ADC Word Clocks = 63*32 ADC Word Clocks Right Channel AGC Control Register 5 DESCRIPTION Right Channel AGC Decay Time Setting 0 0000: Right Channel AGC Decay Time 0 0001: Right Channel AGC Decay Time 0 0010: Right Channel AGC Decay Time … 1 1101: Right Channel AGC Decay Time 1 1110: Right Channel AGC Decay Time 1 1111: Right Channel AGC Decay Time = 1*512 ADC Word Clocks = 3*512 ADC Word Clocks = 5*512 ADC Word Clocks = 59*512 ADC Word Clocks = 61*512 ADC Word Clocks = 63*512 ADC Word Clocks Right Channel AGC Decay Time Scale Factor Setting 000: Scale Factor = 1 001: Scale Factor = 2 010: Scale Factor = 4 … 101: Scale Factor = 32 110: Scale Factor = 64 111: Scale Factor = 128 6.2.94 Page 0 / Register 99: BIT = 1*32 ADC Word Clocks = 3*32 ADC Word Clocks = 5*32 ADC Word Clocks Right Channel AGC Attack Time Scale Factor Setting 000: Scale Factor = 1 001: Scale Factor = 2 010: Scale Factor = 4 … 101: Scale Factor = 32 110: Scale Factor = 64 111: Scale Factor = 128 6.2.93 Page 0 / Register 98: BIT Right Channel AGC Control Register 4 Right Channel AGC Control Register 6 DESCRIPTION Reserved. Write only default values Submit Documentation Feedback TLV320AIC3254 Ultra Low Power Stereo Audio Codec With Embedded miniDSP www.ti.com SLAS549A – SEPTEMBER 2008 – REVISED OCTOBER 2008 (continued) BIT READ/ WRITE RESET VALUE D4–D0 R/W 0 0000 DESCRIPTION Right Channel AGC Noise Debounce Time Setting 0 0001: Right Channel AGC Noise Debounce Time 0 0010: Right Channel AGC Noise Debounce Time 0 0011: Right Channel AGC Noise Debounce Time … 0 1010: Right Channel AGC Noise Debounce Time 0 1011: Right Channel AGC Noise Debounce Time 0 1100: Right Channel AGC Noise Debounce Time 0 1101: Right Channel AGC Noise Debounce Time ... 1 1101: Right Channel AGC Noise Debounce Time 1 1110: Right Channel AGC Noise Debounce Time 1 1111: Right Channel AGC Noise Debounce Time 6.2.95 Page 0 / Register 100: RESET VALUE D7–D4 R 0000 Reserved. Write only default values D3–D0 R/W 0000 Right Channel AGC Signal Debounce Time Setting 0001: Right Channel AGC Signal Debounce Time = 0010: Right Channel AGC Signal Debounce Time = 0011: Right Channel AGC Signal Debounce Time = … 1001: Right Channel AGC Signal Debounce Time = 1010: Right Channel AGC Signal Debounce Time = 1011: Right Channel AGC Signal Debounce Time = 1100: Right Channel AGC Signal Debounce Time = 1101: Right Channel AGC Signal Debounce Time = 1110: Right Channel AGC Signal Debounce Time = 1111: Right Channel AGC Signal Debounce Time = READ/ WRITE RESET VALUE D7–D0 R 0000 0000 = 19*4096 ADC Word Clocks = 20*4096 ADC Word Clocks = 21*4096 ADC Word Clocks DESCRIPTION 6.2.96 Page 0 / Register 101: BIT = 2048 ADC Word Clocks = 4096 ADC Word Clocks = 2*4096 ADC Word Clocks = 3*4096 ADC Word Clocks Right Channel AGC Control Register 7 READ/ WRITE BIT =0 = 4 ADC Word Clocks = 8 ADC Word Clocks 0 4 ADC Word Clocks 8 ADC Word Clocks 1024 ADC Word Clocks 2048 ADC Word Clocks 2*2048 ADC Word Clocks 3*2048 ADC Word Clocks 4*2048 ADC Word Clocks 5*2048 ADC Word Clocks 6*2048 ADC Word Clocks Right Channel AGC Control Register 8 DESCRIPTION Right Channel AGC Gain Flag 1111 0100: Right Channel AGC 1111 0101: Right Channel AGC 1111 0110: Right Channel AGC … 0000 0000: Right Channel AGC … 0111 0010: Right Channel AGC 0111 0011: Right Channel AGC 0111 0100: Right Channel AGC 6.2.97 Page 0 / Register 102: Gain = -12.0dB Gain = -11.5dB Gain = -11.0dB Gain = 0.0dB Gain = 57.0dB Gain = 57.5dB Gain = 58.0dB DC Measurement Register 1 BIT READ/ WRITE RESET VALUE D7 R/W 0 0: DC Measurement Mode disabled for Left ADC Channel 1: DC Measurement Mode enabled for Left ADC Channel D6 R/W 0 0: DC Measurement Mode disabled for Right ADC Channel 1: DC Measurement Mode enabled for Right ADC Channel D5 R/W 0 0: DC Measurement is done using 1st order moving average filter with averaging of 2^D 1: DC Measurement is done with 1sr order Low-pass IIR filter with coefficients as a function of D Submit Documentation Feedback DESCRIPTION REGISTER MAP 131 TLV320AIC3254 Ultra Low Power Stereo Audio Codec With Embedded miniDSP SLAS549A – SEPTEMBER 2008 – REVISED OCTOBER 2008 www.ti.com (continued) BIT READ/ WRITE RESET VALUE D4–D0 R/W 0 0000 DESCRIPTION DC Measurement D setting 0 0000: Reserved. Do not use 0 0001: DC Measurement D parameter 0 0010: DC Measurement D parameter .. 1 0011: DC Measurement D parameter 1 0100: DC Measurement D parameter 1 0101-1 1111: Reserved. Do not use 6.2.98 Page 0 / Register 103: =1 =2 = 19 = 20 DC Measurement Register 2 BIT READ/ WRITE RESET VALUE D7 R 0 Reserved. Write only default values D6 R/W 0 0: Left and Right Channel DC measurement result update enabled 1: Left and Right Channel DC measurement result update disabled i.e. new results will be updated while old results are being read D5 R/W 0 0: For IIR based DC measurement, measurement value is the instantaneous output of IIR filter 1: For IIR based DC measurement, the measurement value is updated before periodic clearing of IIR filter D4–D0 R/W 0 0000 DESCRIPTION IIR based DC Measurement, averaging time setting 0 0000: Infinite average is used 0 0001: Averaging time is 2^1 ADC Modulator clocks 0 0010: Averaging time is 2^2 ADC Modulator clocks … 1 0011: Averaging time is 2^19 ADC Modulator clocks 1 0100: Averaging time is 2^20 ADC Modulator clocks 1 0101-1 1111: Reserved. Do not use 6.2.99 Page 0 / Register 104: BIT READ/ WRITE RESET VALUE D7–D0 R 0000 0000 DESCRIPTION Left Channel DC Measurement Output (23:16) 6.2.100 Page 0 / Register 105: BIT READ/ WRITE RESET VALUE D7–D0 R 0000 0000 READ/ WRITE RESET VALUE D7–D0 R 0000 0000 Left Channel DC Measurement Output (15:8) READ/ WRITE RESET VALUE D7–D0 R 0000 0000 Left Channel DC Measurement Output (7:0) READ/ WRITE RESET VALUE D7–D0 R 0000 0000 132 REGISTER MAP Right Channel DC Measurement Output Register 1 DESCRIPTION Right Channel DC Measurement Output (23:16) 6.2.103 Page 0 / Register 108: BIT Left Channel DC Measurement Output Register 3 DESCRIPTION 6.2.102 Page 0 / Register 107: BIT Left Channel DC Measurement Output Register 2 DESCRIPTION 6.2.101 Page 0 / Register 106: BIT Left Channel DC Measurement Output Register 1 Right Channel DC Measurement Output Register 2 DESCRIPTION Right Channel DC Measurement Output (15:8) Submit Documentation Feedback TLV320AIC3254 Ultra Low Power Stereo Audio Codec With Embedded miniDSP www.ti.com SLAS549A – SEPTEMBER 2008 – REVISED OCTOBER 2008 6.2.104 Page 0 / Register 109: BIT READ/ WRITE RESET VALUE D7–D0 R 0000 0000 Right Channel DC Measurement Output Register 3 DESCRIPTION Right Channel DC Measurement Output (7:0) 6.2.105 Page 0 / Register 110-127: BIT READ/ WRITE RESET VALUE D7–D0 R 0000 0000 DESCRIPTION Reserved. Write only default values 6.2.106 Page 1 / Register 0: BIT READ/ WRITE RESET VALUE D7–D0 R/W 0000 0000 READ/ WRITE RESET VALUE D7–D4 R 0000 D3 R/W 0 D2–D0 R 000 Page Select Register DESCRIPTION Page Select Register 0-255: Selects the Register Page for next read or write command. Refer Table "Summary of Memory Map" for details. 6.2.107 Page 1 / Register 1: BIT Reserved Register Power Configuration Register DESCRIPTION Reserved. Write only default values 0: AVDD will be weakly connected to DVDD. Use when DVDD is powered, but AVDD LDO is powered down and AVDD is not externally powered 1: Disabled weak connection of AVDD with DVDD Reserved. Write only default values 6.2.108 Page 1 / Register 2: LDO Control Register BIT READ/ WRITE RESET VALUE D7–D6 R/W 00 DVDD LDO Control 00: DVDD LDO output is nominally 1.72V 01: DVDD LDO output is nominally 1.67V 10: DVDD LDO output is nominally 1.77V 11: Do not use D5–D4 R/W 00 AVDD LDO Control 00: AVDD LDO output is nominally 1.72V 01: AVDD LDO output is nominally 1.67V 10: AVDD LDO output is nominally 1.77V 11: Do not use D3 R/W 1 Analog Block Power Control 0: Analog Blocks Enabled 1: Analog Blocks Disabled D2 R 0 DVDD LDO Over Current Detect 0: Over Current not detected for DVDD LDO 1: Over Current detected for DVDD LDO D1 R 0 AVDD LDO Over Current Detect 0: Over Current not detected for AVDD LDO 1: Over Current detected for AVDD LDO D0 R/W 0 AVDD LDO Power Control 0: AVDD LDO Powered down 1: AVDD LDO Powered up Submit Documentation Feedback DESCRIPTION REGISTER MAP 133 TLV320AIC3254 Ultra Low Power Stereo Audio Codec With Embedded miniDSP SLAS549A – SEPTEMBER 2008 – REVISED OCTOBER 2008 6.2.109 Page 1 / Register 3: www.ti.com Playback Configuration Register 1 BIT READ/ WRITE RESET VALUE D7–D6 R/W 00 00: Left DAC routing to HPL uses Class-AB driver 01-10: Reserved. Do not use 11: Left DAC routing to HPL uses Class-D driver Reserved. Write only default value DESCRIPTION D5 R 0 D4–D2 R/W 000 Left DAC PTM Control 000: Left DAC in mode PTM_P3, PTM_P4 001: Left DAC in mode PTM_P2 010: Left DAC in mode PTM_P1 011-111: Reserved. Do not use D1–D0 R 00 Reserved. Write only default value 6.2.110 Page 1 / Register 4: Playback Configuration Register 2 BIT READ/ WRITE RESET VALUE D7–D6 R/W 00 00: Right DAC routing to HPL uses Class-AB driver 01-10: Reserved. Do not use 11: Right DAC routing to HPL uses Class-D driver Reserved. Write only default value DESCRIPTION D5 R 0 D4–D2 R/W 000 Right DAC PTM Control 000: Right DAC in mode PTM_P3, PTM_P4 001: Right DAC in mode PTM_P2 010: Right DAC in mode PTM_P1 011-111: Reserved. Do not use D1–D0 R 00 Reserved. Write only default value 6.2.111 Page 1 / Register 5-8: BIT READ/ WRITE RESET VALUE D7–D0 R 0000 0000 Reserved Register DESCRIPTION Reserved. Write only default values 6.2.112 Page 1 / Register 9: Output Driver Power Control Register READ/ WRITE RESET VALUE D7–D6 R 00 Reserved. Write only default value D5 R/W 0 0: HPL is powered down 1: HPL is powered up D4 R/W 0 0: HPR is powered down 1: HPR is powered up D3 R/W 0 0: LOL is powered down 1: LOL is powered up D2 R/W 0 0: LOR is powered down 1: LOR is powered up D1 R/W 0 0: Left Mixer Amplifier(MAL) is powered down 1: Left Mixer Amplifier(MAL) is powered up D0 R/W 0 0: Right Mixer Amplifier(MAR) is powered down 1: Right Mixer Amplifier(MAR) is powered up BIT DESCRIPTION 6.2.113 Page 1 / Register 10: READ/ WRITE RESET VALUE D7 R 0 Reserved. Write only default value. D6 R/W 0 0: Full Chip Common Mode is 0.9V 1: Full Chip Common Mode is 0.75V BIT 134 Common Mode Control Register REGISTER MAP DESCRIPTION Submit Documentation Feedback TLV320AIC3254 Ultra Low Power Stereo Audio Codec With Embedded miniDSP www.ti.com SLAS549A – SEPTEMBER 2008 – REVISED OCTOBER 2008 (continued) BIT READ/ WRITE RESET VALUE D5–D4 R/W 00 00: 01: 10: 11: D3 R/W 0 0: Output Common Mode for LOL & LOR is same as full-chip common mode 1: Output Common Mode for LOL & LOR is 1.65V and output is powered by LDOIN D2 R 0 Reserved. Write only default value D1 R/W 0 0: Output of HPL & HPR is powered with AVDD supply 1: Output of HPL & HPR is powered with LDOIN supply D0 R/W 0 0: When Page-1, Reg-10, D1=1, then LDOIN input range is 1.5V to 1.95V 1: When Page-1, Reg-10, D1=1, then LDOIN input range is 1.8V to 3.6V DESCRIPTION Output Output Output Output 6.2.114 Page 1 / Register 11: BIT READ/ WRITE RESET VALUE D7–D5 R 000 D4 R/W 1 D3–D1 R/W 000 D0 R/W 0 Common Common Common Common Mode Mode Mode Mode for for for for HPL & HPR is HPL & HPR is HPL & HPR is HPL & HPR is same as full-chip common mode 1.25V 1.5V 1.65V Over Current Protection Configuration Register DESCRIPTION Reserved. Write only default values 0: Over Current detection is disabled for HPL & HPR 1: Over Current detection is enabled for HPL & HPR 000: 001: 010: 011: 100: 101: 110: 111: No debounce is used for Over Current detection Over Current detection is debounced by 8ms Over Current detection is debounce by 16ms Over Current detection is debounced by 32ms Over Current detection is debounced by 64ms Over Current detection is debounced by 128ms Over Current detection is debounced by 256ms Over Current detection is debounced by 512ms 0: Output current will be limited if over current condition is detected 1: Output driver will be powered down if over current condition is detected 6.2.115 Page 1 / Register 12: HPL Routing Selection Register READ/ WRITE RESET VALUE D7–D4 R 0000 D3 R/W 0 0: Left Channel DAC reconstruction filter's positive terminal is not routed to HPL 1: Left Channel DAC reconstruction filter's positive terminal is routed to HPL D2 R/W 0 0: IN1L is not routed to HPL 1: IN1L is routed to HPL D1 R/W 0 0: MAL output is not routed to HPL 1: MAL output is routed to HPL D0 R/W 0 0: MAR output is not routed to HPL 1: MAR output is routed to HPL BIT DESCRIPTION Reserved. Write only default values 6.2.116 Page 1 / Register 13: HPR Routing Selection Register BIT READ/ WRITE RESET VALUE D7–D5 R 000 D4 R/W 0 0: Left Channel DAC reconstruction filter's negative terminal is not routed to HPR 1: Left Channel DAC reconstruction filter's negative terminal is routed to HPR D3 R/W 0 0: Right Channel DAC reconstruction filter's positive terminal is not routed to HPR 1: Right Channel DAC reconstruction filter's positive terminal is routed to HPR D2 R/W 0 0: IN1R is not routed to HPR 1: IN1R is routed to HPR D1 R/W 0 0: MAR output is not routed to HPR 1: MAR output is routed to HPR Submit Documentation Feedback DESCRIPTION Reserved. Write only default values REGISTER MAP 135 TLV320AIC3254 Ultra Low Power Stereo Audio Codec With Embedded miniDSP SLAS549A – SEPTEMBER 2008 – REVISED OCTOBER 2008 www.ti.com (continued) BIT READ/ WRITE RESET VALUE D0 R/W 0 DESCRIPTION 0: HPL output is not routed to HPR 1: HPL output is routed to HPR (use when HPL&HPR output is powered by AVDD) 6.2.117 Page 1 / Register 14: LOL Routing Selection Register READ/ WRITE RESET VALUE D7–D5 R 000 D4 R/W 0 0: Right Channel DAC reconstruction filter's negative terminal is not routed to LOL 1: Right Channel DAC reconstruction filter's negative terminal is routed to LOL D3 R/W 0 0: Left Channel DAC reconstruction filter output is not routed to LOL 1: Left Channel DAC reconstruction filter output is routed to LOL D2 R 0 Reserved. Write only default value. D1 R/W 0 0: MAL output is not routed to LOL 1: MAL output is routed to LOL D0 R/W 0 0: LOR output is not routed to LOL 1: LOR output is routed to LOL(use when LOL&LOR output is powered by AVDD) BIT DESCRIPTION Reserved. Write only default values 6.2.118 Page 1 / Register 15: LOR Routing Selection Register READ/ WRITE RESET VALUE D7–D4 R 0000 D3 R/W 0 0: Right Channel DAC reconstruction filter output is not routed to LOR 1: Right Channel DAC reconstruction filter output is routed to LOR D2 R 0 Reserved. Write only default value. D1 R/W 0 0: MAR output is not routed to LOR 1: MAR output is routed to LOR D0 R 0 Reserved. Write only default value. BIT DESCRIPTION Reserved. Write only default values 6.2.119 Page 1 / Register 16: HPL Driver Gain Setting Register READ/ WRITE RESET VALUE D7 R 0 Reserved. Write only default value. D6 R/W 1 0: HPL driver is not muted 1: HPL driver is muted D5–D0 R/W 00 0000 BIT DESCRIPTION 10 0000-11 1001: Reserved. Do not use 11 1010: HPL driver gain is -6dB (Note: It is not possible to mute HPL while programmed to -6dB) 11 1011: HPL driver gain is -5dB 11 1100: HPL driver gain is -4dB … 00 0000: HPL driver gain is 0dB ... 01 1011: HPL driver gain is 27dB 01 1100: HPL driver gain is 28dB 01 1101: HPL driver gain is 29dB 01 1110-01 1111: Reserved. Do not use Note: These gains are not valid while using the driver in Class-D mode 6.2.120 Page 1 / Register 17: RESET VALUE D7 R 0 Reserved. Write only default value. D6 R/W 1 0: HPR driver is not muted 1: HPR driver is muted BIT 136 HPR Driver Gain Setting Register READ/ WRITE REGISTER MAP DESCRIPTION Submit Documentation Feedback TLV320AIC3254 Ultra Low Power Stereo Audio Codec With Embedded miniDSP www.ti.com SLAS549A – SEPTEMBER 2008 – REVISED OCTOBER 2008 (continued) BIT READ/ WRITE RESET VALUE D5–D0 R/W 00 0000 DESCRIPTION 10 0000-11 1001: Reserved. Do not use 11 1010: HPR driver gain is -6dB (Note: It is not possible to mute HPR while programmed to -6dB) 11 1011: HPR driver gain is -5dB 11 1100: HPR driver gain is -4dB … 00 0000: HPR driver gain is 0dB ... 01 1011: HPR driver gain is 27dB 01 1100: HPR driver gain is 28dB 01 1101: HPR driver gain is 29dB 01 1110-01 1111: Reserved. Do not use Note: These gains are not valid while using the driver in Class-D mode 6.2.121 Page 1 / Register 18: LOL Driver Gain Setting Register READ/ WRITE RESET VALUE D7 R 0 Reserved. Write only default value. D6 R/W 1 0: LOL driver is not muted 1: LOL driver is muted D5–D0 R/W 00 0000 BIT DESCRIPTION 10 11 11 11 … 00 ... 01 01 01 01 0000-11 1001: Reserved. Do not use 1010: LOL driver gain is -6dB 1011: LOL driver gain is -5dB 1100: LOL driver gain is -4dB 0000: LOL driver gain is 0dB 1011: LOL driver gain is 27dB 1100: LOL driver gain is 28dB 1101: LOL driver gain is 29dB 1110-01 1111: Reserved. Do not use 6.2.122 Page 1 / Register 19: LOR Driver Gain Setting Register BIT READ/ WRITE RESET VALUE D7 R 0 Reserved. Write only default value. D6 R/W 1 0: LOR driver is not muted 1: LOR driver is muted D5–D0 R/W 00 0000 DESCRIPTION 10 11 11 11 … 00 ... 01 01 01 01 0000-11 1001: Reserved. Do not use 1010: LOR driver gain is -6dB 1011: LOR driver gain is -5dB 1100: LOR driver gain is -4dB 0000: LOR driver gain is 0dB 1011: LOR driver gain is 27dB 1100: LOR driver gain is 28dB 1101: LOR driver gain is 29dB 1110-01 1111: Reserved. Do not use 6.2.123 Page 1 / Register 20: BIT READ/ WRITE RESET VALUE D7–D6 R/W 00 Submit Documentation Feedback Headphone Driver Startup Control Register DESCRIPTION 00: 01: 10: 11: Soft Soft Soft Soft routing step routing step routing step routing step time time time time is 0ms is 50ms is 100ms is 200ms REGISTER MAP 137 TLV320AIC3254 Ultra Low Power Stereo Audio Codec With Embedded miniDSP SLAS549A – SEPTEMBER 2008 – REVISED OCTOBER 2008 www.ti.com (continued) BIT READ/ WRITE RESET VALUE D5–D2 R/W 0000 D1–D0 R/W 00 DESCRIPTION 0000: Slow power up of headphone amp's is disabled 0001: Headphone amps power up slowly in 0.5 time constants 0010: Headphone amps power up slowly in 0.625 time constants 0011; Headphone amps power up slowly in 0.725 time constants 0100: Headphone amps power up slowly in 0.875 time constants 0101: Headphone amps power up slowly in 1.0 time constants 0110: Headphone amps power up slowly in 2.0 time constants 0111: Headphone amps power up slowly in 3.0 time constants 1000: Headphone amps power up slowly in 4.0 time constants 1001: Headphone amps power up slowly in 5.0 time constants 1010: Headphone amps power up slowly in 6.0 time constants 1011: Headphone amps power up slowly in 7.0 time constants 1100: Headphone amps power up slowly in 8.0 time constants 1101: Headphone amps power up slowly in 16.0 time constants ( do not use for Rchg=25K) 1110: Headphone amps power up slowly in 24.0 time constants (do not use for Rchg=25K) 1111: Headphone amps power up slowly in 32.0 time constants (do not use for Rchg=25K) Note: Time constants assume 47uF decoupling cap 00: 01: 10: 11: 6.2.124 Page 1 / Register 21: BIT READ/ WRITE RESET VALUE D7–D0 R 0000 0000 138 READ/ WRITE RESET VALUE D7 R 0 REGISTER MAP Reserved Register DESCRIPTION Reserved. Write only default values 6.2.125 Page 1 / Register 22: BIT Headphone amps power up time is determined with 25K resistance Headphone amps power up time is determined with 6K resistance Headphone amps power up time is determined with 2K resistance Reserved. Do not use IN1L to HPL Volume Control Register DESCRIPTION Reserved. Write only default value. Submit Documentation Feedback TLV320AIC3254 Ultra Low Power Stereo Audio Codec With Embedded miniDSP www.ti.com SLAS549A – SEPTEMBER 2008 – REVISED OCTOBER 2008 (continued) BIT READ/ WRITE RESET VALUE D6–D0 R/W 000 0000 Submit Documentation Feedback DESCRIPTION IN1L to HPL Volume Control 000 0000: Volume Control = 0.0dB 000 0001: Volume Control = -0.5dB 000 0010: Volume Control = -1.0dB 000 0011: Volume Control = -1.5dB 000 0100: Volume Control = -2.0dB 000 0101: Volume Control = -2.5dB 000 0110: Volume Control = -3.0dB 000 0111: Volume Control = -3.5dB 000 1000: Volume Control = -4.0dB 000 1001: Volume Control = -4.5dB 000 1010: Volume Control = -5.0dB 000 1011: Volume Control = -5.5dB 000 1100: Volume Control = -6.0dB 000 1101: Volume Control = -7.0dB 000 1110: Volume Control = -8.0dB 000 1111: Volume Control = -8.5dB 001 0000: Volume Control = -9.0dB 001 0001: Volume Control = -9.5dB 001 0010: Volume Control = -10.0dB 001 0011: Volume Control = -10.5dB 001 0100: Volume Control = -11.0dB 001 0101: Volume Control = -11.5dB 001 0110: Volume Control = -12.0dB 001 0111: Volume Control = -12.5dB 001 1000: Volume Control = -13.0dB 001 1001: Volume Control = -13.5dB 001 1010: Volume Control = -14.0dB 001 1011: Volume Control = -14.5dB 001 1100: Volume Control = -15.0dB 001 1101: Volume Control = -15.5dB 001 1110: Volume Control = -16.0dB 001 1111: Volume Control = -16.5dB 010 0000: Volume Control = -17.1dB 010 0001: Volume Control = -17.5dB 010 0010: Volume Control = -18.1dB 010 0011: Volume Control = -18.6dB 010 0100: Volume Control = -19.1dB 010 0101: Volume Control = -19.6dB 010 0110: Volume Control = -20.1dB 010 0111: Volume Control = -20.6dB 010 1000: Volume Control = -21.1dB 010 1001: Volume Control = -21.6dB 010 1010: Volume Control = -22.1dB 010 1011: Volume Control = -22.6dB 010 1100: Volume Control = -23.1dB 010 1101: Volume Control = -23.6dB 010 1110: Volume Control = -24.1dB 010 1111: Volume Control = -24.6dB 011 0000: Volume Control = -25.1dB 011 0001: Volume Control = -25.6dB 011 0010: Volume Control = -26.1dB 011 0011: Volume Control = -26.6dB 011 0100: Volume Control = -27.1dB 011 0101: Volume Control = -27.6dB 011 0110: Volume Control = -28.1dB 011 0111: Volume Control = -28.6dB 011 1000: Volume Control = -29.1dB 011 1001: Volume Control = -29.6dB 011 1010: Volume Control = -30.1dB 011 1011: Volume Control = -30.6dB 011 1100: Volume Control = -31.1dB 011 1100: Volume Control = -31.6dB 011 1101: Volume Control = -32.1dB 011 1110: Volume Control = -32.6dB 011 1111: Volume Control = -33.1dB 100 0000: Volume Control = -33.6dB 100 0001: Volume Control = -34.1dB REGISTER MAP 139 TLV320AIC3254 Ultra Low Power Stereo Audio Codec With Embedded miniDSP SLAS549A – SEPTEMBER 2008 – REVISED OCTOBER 2008 www.ti.com (continued) BIT READ/ WRITE RESET VALUE DESCRIPTION 100 0010: Volume Control = -34.6dB 100 0011: Volume Control = -35.2dB 100 0100: Volume Control = -35.7dB 100 0101: Volume Control = -36.2dB 100 0110: Volume Control = -36.7dB 100 0111: Volume Control = -37.2dB 100 1000: Volume Control = -37.7dB 100 1001: Volume Control = -38.2dB 100 1010: Volume Control = -38.7dB 100 1011: Volume Control = -39.2dB 100 1100: Volume Control = -39.7dB 100 1101: Volume Control = -40.2dB 100 1110: Volume Control = -40.7dB 100 1111: Volume Control = -41.2dB 101 0000: Volume Control = -41.7dB 101 0001: Volume Control = -42.1dB 101 0010: Volume Control = -42.7dB 101 0011: Volume Control = -43.2dB 101 0100: Volume Control = -43.8dB 101 0101: Volume Control = -44.3dB 101 0110: Volume Control = -44.8dB 101 0111: Volume Control = -45.2dB 101 1000: Volume Control = -45.8dB 101 1001: Volume Control = -46.2dB 101 1010: Volume Control = -46.7dB 101 1011: Volume Control = -47.4dB 101 1100: Volume Control = -47.9dB 101 1101: Volume Control = -48.2dB 101 1110: Volume Control = -48.7dB 101 1111: Volume Control = -49.3dB 110 0000: Volume Control = -50.0dB 110 0001: Volume Control = -50.3dB 110 0010: Volume Control = -51.0dB 110 0011: Volume Control = -51.42dB 110 0100: Volume Control = -51.82dB 110 0101: Volume Control = -52.3dB 110 0110: Volume Control = -52.7dB 110 0111: Volume Control = -53.7dB 110 1000: Volume Control = -54.2dB 110 1001: Volume Control = -55.4dB 110 1010: Volume Control = -56.7dB 110 1011: Volume Control = -58.3dB 110 1100: Volume Control = -60.2dB 110 1101: Volume Control = -62.7dB 110 1110: Volume Control = -64.3dB 110 1111: Volume Control = -66.2dB 111 0000: Volume Control = -68.7dB 111 0001: Volume Control = -72.3dB 111 0010: Volume Control = MUTE 111 0011-111 1111: Reserved. Do not use 6.2.126 Page 1 / Register 23: 140 BIT READ/ WRITE RESET VALUE D7 R 0 REGISTER MAP IN1R to HPR Volume Control Register DESCRIPTION Reserved. Write only default value Submit Documentation Feedback TLV320AIC3254 Ultra Low Power Stereo Audio Codec With Embedded miniDSP www.ti.com SLAS549A – SEPTEMBER 2008 – REVISED OCTOBER 2008 (continued) BIT READ/ WRITE RESET VALUE D6–D0 R/W 000 0000 Submit Documentation Feedback DESCRIPTION IN1R to HPR Volume Control 000 0000: Volume Control = 0.0dB 000 0001: Volume Control = -0.5dB 000 0010: Volume Control = -1.0dB 000 0011: Volume Control = -1.5dB 000 0100: Volume Control = -2.0dB 000 0101: Volume Control = -2.5dB 000 0110: Volume Control = -3.0dB 000 0111: Volume Control = -3.5dB 000 1000: Volume Control = -4.0dB 000 1001: Volume Control = -4.5dB 000 1010: Volume Control = -5.0dB 000 1011: Volume Control = -5.5dB 000 1100: Volume Control = -6.0dB 000 1101: Volume Control = -7.0dB 000 1110: Volume Control = -8.0dB 000 1111: Volume Control = -8.5dB 001 0000: Volume Control = -9.0dB 001 0001: Volume Control = -9.5dB 001 0010: Volume Control = -10.0dB 001 0011: Volume Control = -10.5dB 001 0100: Volume Control = -11.0dB 001 0101: Volume Control = -11.5dB 001 0110: Volume Control = -12.0dB 001 0111: Volume Control = -12.5dB 001 1000: Volume Control = -13.0dB 001 1001: Volume Control = -13.5dB 001 1010: Volume Control = -14.0dB 001 1011: Volume Control = -14.5dB 001 1100: Volume Control = -15.0dB 001 1101: Volume Control = -15.5dB 001 1110: Volume Control = -16.0dB 001 1111: Volume Control = -16.5dB 010 0000: Volume Control = -17.1dB 010 0001: Volume Control = -17.5dB 010 0010: Volume Control = -18.1dB 010 0011: Volume Control = -18.6dB 010 0100: Volume Control = -19.1dB 010 0101: Volume Control = -19.6dB 010 0110: Volume Control = -20.1dB 010 0111: Volume Control = -20.6dB 010 1000: Volume Control = -21.1dB 010 1001: Volume Control = -21.6dB 010 1010: Volume Control = -22.1dB 010 1011: Volume Control = -22.6dB 010 1100: Volume Control = -23.1dB 010 1101: Volume Control = -23.6dB 010 1110: Volume Control = -24.1dB 010 1111: Volume Control = -24.6dB 011 0000: Volume Control = -25.1dB 011 0001: Volume Control = -25.6dB 011 0010: Volume Control = -26.1dB 011 0011: Volume Control = -26.6dB 011 0100: Volume Control = -27.1dB 011 0101: Volume Control = -27.6dB 011 0110: Volume Control = -28.1dB 011 0111: Volume Control = -28.6dB 011 1000: Volume Control = -29.1dB 011 1001: Volume Control = -29.6dB 011 1010: Volume Control = -30.1dB 011 1011: Volume Control = -30.6dB 011 1100: Volume Control = -31.1dB 011 1100: Volume Control = -31.6dB 011 1101: Volume Control = -32.1dB 011 1110: Volume Control = -32.6dB 011 1111: Volume Control = -33.1dB 100 0000: Volume Control = -33.6dB 100 0001: Volume Control = -34.1dB REGISTER MAP 141 TLV320AIC3254 Ultra Low Power Stereo Audio Codec With Embedded miniDSP SLAS549A – SEPTEMBER 2008 – REVISED OCTOBER 2008 www.ti.com (continued) READ/ WRITE BIT RESET VALUE DESCRIPTION 100 0010: Volume Control = -34.6dB 100 0011: Volume Control = -35.2dB 100 0100: Volume Control = -35.7dB 100 0101: Volume Control = -36.2dB 100 0110: Volume Control = -36.7dB 100 0111: Volume Control = -37.2dB 100 1000: Volume Control = -37.7dB 100 1001: Volume Control = -38.2dB 100 1010: Volume Control = -38.7dB 100 1011: Volume Control = -39.2dB 100 1100: Volume Control = -39.7dB 100 1101: Volume Control = -40.2dB 100 1110: Volume Control = -40.7dB 100 1111: Volume Control = -41.2dB 101 0000: Volume Control = -41.7dB 101 0001: Volume Control = -42.1dB 101 0010: Volume Control = -42.7dB 101 0011: Volume Control = -43.2dB 101 0100: Volume Control = -43.8dB 101 0101: Volume Control = -44.3dB 101 0110: Volume Control = -44.8dB 101 0111: Volume Control = -45.2dB 101 1000: Volume Control = -45.8dB 101 1001: Volume Control = -46.2dB 101 1010: Volume Control = -46.7dB 101 1011: Volume Control = -47.4dB 101 1100: Volume Control = -47.9dB 101 1101: Volume Control = -48.2dB 101 1110: Volume Control = -48.7dB 101 1111: Volume Control = -49.3dB 110 0000: Volume Control = -50.0dB 110 0001: Volume Control = -50.3dB 110 0010: Volume Control = -51.0dB 110 0011: Volume Control = -51.42dB 110 0100: Volume Control = -51.82dB 110 0101: Volume Control = -52.3dB 110 0110: Volume Control = -52.7dB 110 0111: Volume Control = -53.7dB 110 1000: Volume Control = -54.2dB 110 1001: Volume Control = -55.4dB 110 1010: Volume Control = -56.7dB 110 1011: Volume Control = -58.3dB 110 1100: Volume Control = -60.2dB 110 1101: Volume Control = -62.7dB 110 1110: Volume Control = -64.3dB 110 1111: Volume Control = -66.2dB 111 0000: Volume Control = -68.7dB 111 0001: Volume Control = -72.3dB 111 0010: Volume Control = MUTE 111 0011-111 1111: Reserved. Do not use 6.2.127 Page 1 / Register 24: BIT READ/ WRITE RESET VALUE D7–D6 R 00 142 REGISTER MAP MAL Volume Control Register DESCRIPTION Reserved. Write only default values Submit Documentation Feedback TLV320AIC3254 Ultra Low Power Stereo Audio Codec With Embedded miniDSP www.ti.com SLAS549A – SEPTEMBER 2008 – REVISED OCTOBER 2008 (continued) BIT READ/ WRITE RESET VALUE D5–D0 R/W 00 0000 DESCRIPTION MAL Volume Control 00 0000: Volume Control = 0.0dB 00 0001: Volume Control = -0.4dB 00 0010: Volume Control = -0.9dB 00 0011: Volume Control = -1.3dB 00 0100: Volume Control = -1.8dB 00 0101: Volume Control = -2.3dB 00 0110: Volume Control = -2.9dB 00 0111: Volume Control = -3.3dB 00 1000: Volume Control = -3.9dB 00 1001: Volume Control = -4.3dB 00 1010: Volume Control = -4.8dB 00 1011: Volume Control = -5.2dB 00 1100: Volume Control = -5.8dB 00 1101: Volume Control = -6.3dB 00 1110: Volume Control = -6.6dB 00 1111: Volume Control = -7.2dB 01 0000: Volume Control = -7.8dB 01 0001: Volume Control = -8.2dB 01 0010: Volume Control = -8.5dB 01 0011: Volume Control = -9.3dB 01 0100: Volume Control = -9.7dB 01 0101: Volume Control = -10.1dB 01 0110: Volume Control = -10.6dB 01 0111: Volume Control = -11.0dB 01 1000: Volume Control = -11.5dB 01 1001: Volume Control = -12.0dB 01 1010: Volume Control = -12.6dB 01 1011: Volume Control = -13.2dB 01 1100: Volume Control = -13.8dB 01 1101: Volume Control = -14.5dB 01 1110: Volume Control = -15.3dB 01 1111: Volume Control = -16.1dB 10 0000: Volume Control = -17.0dB 10 0001: Volume Control = -18.1dB 10 0010: Volume Control = -19.2dB 10 0011: Volume Control = -20.6dB 10 0100: Volume Control = -22.1dB 10 0101: Volume Control = -24.1dB 10 0110: Volume Control = -26.6dB 10 0111: Volume Control = -30.1dB 10 1000: Volume Control = MUTE 10 1001-11 1111: Reserved. Do no use 6.2.128 Page 1 / Register 25: BIT READ/ WRITE RESET VALUE D7–D6 R 00 Submit Documentation Feedback MAR Volume Control Register DESCRIPTION Reserved. Write only default values REGISTER MAP 143 TLV320AIC3254 Ultra Low Power Stereo Audio Codec With Embedded miniDSP SLAS549A – SEPTEMBER 2008 – REVISED OCTOBER 2008 www.ti.com (continued) BIT READ/ WRITE RESET VALUE D5–D0 R/W 00 0000 DESCRIPTION MAR Volume Control 00 0000: Volume Control = 0.0dB 00 0001: Volume Control = -0.4dB 00 0010: Volume Control = -0.9dB 00 0011: Volume Control = -1.3dB 00 0100: Volume Control = -1.8dB 00 0101: Volume Control = -2.3dB 00 0110: Volume Control = -2.9dB 00 0111: Volume Control = -3.3dB 00 1000: Volume Control = -3.9dB 00 1001: Volume Control = -4.3dB 00 1010: Volume Control = -4.8dB 00 1011: Volume Control = -5.2dB 00 1100: Volume Control = -5.8dB 00 1101: Volume Control = -6.3dB 00 1110: Volume Control = -6.6dB 00 1111: Volume Control = -7.2dB 01 0000: Volume Control = -7.8dB 01 0001: Volume Control = -8.2dB 01 0010: Volume Control = -8.5dB 01 0011: Volume Control = -9.3dB 01 0100: Volume Control = -9.7dB 01 0101: Volume Control = -10.1dB 01 0110: Volume Control = -10.6dB 01 0111: Volume Control = -11.0dB 01 1000: Volume Control = -11.5dB 01 1001: Volume Control = -12.0dB 01 1010: Volume Control = -12.6dB 01 1011: Volume Control = -13.2dB 01 1100: Volume Control = -13.8dB 01 1101: Volume Control = -14.5dB 01 1110: Volume Control = -15.3dB 01 1111: Volume Control = -16.1dB 10 0000: Volume Control = -17.0dB 10 0001: Volume Control = -18.1dB 10 0010: Volume Control = -19.2dB 10 0011: Volume Control = -20.6dB 10 0100: Volume Control = -22.1dB 10 0101: Volume Control = -24.1dB 10 0110: Volume Control = -26.6dB 10 0111: Volume Control = -30.1dB 10 1000: Volume Control = MUTE 10 1001-11 1111: Reserved. Do no use 6.2.129 Page 1 / Register 26-50: BIT READ/ WRITE RESET VALUE D7–D0 R 0000 0000 Reserved Register DESCRIPTION Reserved. Write only default values 6.2.130 Page 1 / Register 51: MICBIAS Configuration Register READ/ WRITE RESET VALUE D7 R 0 Reserved. Write only default value. D6 R/W 0 0: MICBIAS powered down 1: MICBIAS powered up D5–D4 R/W 00 MICBIAS Output Voltage Configuration 00: MICBIAS = 1.04V (CM=0.75V) or MICBIAS = 1.25V(CM=0.9V) 01: MICBIAS = 1.425V(CM=0.75V) or MICBIAS = 1.7V(CM=0.9V) 10: MICBIAS = 2.075V(CM=0.75V) or MICBIAS = 2.5V(CM=0.9V) 11: MICBIAS is switch to power supply D3 R/W 0 0: MICBIAS voltage is generated from AVDD 1: MICBIAS voltage is generated from LDOIN BIT 144 REGISTER MAP DESCRIPTION Submit Documentation Feedback TLV320AIC3254 Ultra Low Power Stereo Audio Codec With Embedded miniDSP www.ti.com SLAS549A – SEPTEMBER 2008 – REVISED OCTOBER 2008 (continued) BIT READ/ WRITE RESET VALUE D2–D0 R 000 DESCRIPTION Reserved. Write only default value. 6.2.131 Page 1 / Register 52: Configuration Register Left MICPGA Positive Terminal Input Routing BIT READ/ WRITE RESET VALUE D7–D6 R/W 00 IN1L to Left MICPGA positive terminal selection 00: IN1L is not routed to Left MICPGA 01: IN1L is routed to Left MICPGA with 10K resistance 10: IN1L is routed to Left MICPGA with 20K resistance 11: IN1L is routed to Left MICPGA with 40K resistance D5–D4 R/W 00 IN2L to Left MICPGA positive terminal selection 00: IN2L is not routed to Left MICPGA 01: IN2L is routed to Left MICPGA with 10K resistance 10: IN2L is routed to Left MICPGA with 20K resistance 11: IN2L is routed to Left MICPGA with 40K resistance D3–D2 R/W 00 IN3L to Left MICPGA positive terminal selection 00: IN3L is not routed to Left MICPGA 01: IN3L is routed to Left MICPGA with 10K resistance 10: IN3L is routed to Left MICPGA with 20K resistance 11: IN3L is routed to Left MICPGA with 40K resistance D1–D0 R/W 00 IN1R to Left MICPGA positive terminal selection 00: IN1R is not routed to Left MICPGA 01: IN1R is routed to Left MICPGA with 10K resistance 10: IN1R is routed to Left MICPGA with 20K resistance 11: IN1R is routed to Left MICPGA with 40K resistance DESCRIPTION 6.2.132 Page 1 / Register 53: BIT READ/ WRITE RESET VALUE D7–D0 R 0000 0000 Reserved Register DESCRIPTION Reserved. Write only default values 6.2.133 Page 1 / Register 54: Configuration Register Left MICPGA Negative Terminal Input Routing BIT READ/ WRITE RESET VALUE D7–D6 R/W 00 CM to Left MICPGA (CM1L) positive terminal selection 00: CM is not routed to Left MICPGA 01: CM is routed to Left MICPGA via CM1L with 10K resistance 10: CM is routed to Left MICPGA via CM1L with 20K resistance 11: CM is routed to Left MICPGA via CM1L with 40K resistance D5–D4 R/W 00 IN2R to Left MICPGA positive terminal selection 00: IN2R is not routed to Left MICPGA 01: IN2R is routed to Left MICPGA with 10K resistance 10: IN2R is routed to Left MICPGA with 20K resistance 11: IN2R is routed to Left MICPGA with 40K resistance D3–D2 R/W 00 IN3R to Left MICPGA positive terminal selection 00: IN3R is not routed to Left MICPGA 01: IN3R is routed to Left MICPGA with 10K resistance 10: IN3R is routed to Left MICPGA with 20K resistance 11: IN3R is routed to Left MICPGA with 40K resistance D1–D0 R/W 00 CM to Left MICPGA (CM2L) positive terminal selection 00: CM is not routed to Left MICPGA 01: CM is routed to Left MICPGA via CM2L with 10K resistance 10: CM is routed to Left MICPGA via CM2L with 20K resistance 11: CM is routed to Left MICPGA via CM2L with 40K resistance Submit Documentation Feedback DESCRIPTION REGISTER MAP 145 TLV320AIC3254 Ultra Low Power Stereo Audio Codec With Embedded miniDSP SLAS549A – SEPTEMBER 2008 – REVISED OCTOBER 2008 6.2.134 Page 1 / Register 55: Configuration Register www.ti.com Right MICPGA Positive Terminal Input Routing BIT READ/ WRITE RESET VALUE D7–D6 R/W 00 IN1R to Right MICPGA positive terminal selection 00: IN1R is not routed to Right MICPGA 01: IN1R is routed to Right MICPGA with 10K resistance 10: IN1R is routed to Right MICPGA with 20K resistance 11: IN1R is routed to Right MICPGA with 40K resistance D5–D4 R/W 00 IN2R to Right MICPGA positive terminal selection 00: IN2R is not routed to Right MICPGA 01: IN2R is routed to Right MICPGA with 10K resistance 10: IN2R is routed to Right MICPGA with 20K resistance 11: IN2R is routed to Right MICPGA with 40K resistance D3–D2 R/W 00 IN3R to Right MICPGA positive terminal selection 00: IN3R is not routed to Right MICPGA 01: IN3R is routed to Right MICPGA with 10K resistance 10: IN3R is routed to Right MICPGA with 20K resistance 11: IN3R is routed to Right MICPGA with 40K resistance D1–D0 R/W 00 IN2L to Right MICPGA positive terminal selection 00: IN2L is not routed to Right MICPGA 01: IN2L is routed to Right MICPGA with 10K resistance 10: IN2L is routed to Right MICPGA with 20K resistance 11: IN2L is routed to Right MICPGA with 40K resistance DESCRIPTION 6.2.135 Page 1 / Register 56: BIT READ/ WRITE RESET VALUE D7–D0 R 0000 0000 Reserved Register DESCRIPTION Reserved. Write only default values 6.2.136 Page 1 / Register 57: Configuration Register Right MICPGA Negative Terminal Input Routing BIT READ/ WRITE RESET VALUE D7–D6 R/W 00 CM to Right MICPGA (CM1R) positive terminal selection 00: CM is not routed to Right MICPGA 01: CM is routed to Right MICPGA via CM1R with 10K resistance 10: CM is routed to Right MICPGA via CM1R with 20K resistance 11: CM is routed to Right MICPGA via CM1R with 40K resistance D5–D4 R/W 00 IN1L to Right MICPGA positive terminal selection 00: IN1L is not routed to Right MICPGA 01: IN1L is routed to Right MICPGA with 10K resistance 10: IN1L is routed to Right MICPGA with 20K resistance 11: IN1L is routed to Right MICPGA with 40K resistance D3–D2 R/W 00 IN3L to Right MICPGA positive terminal selection 00: IN3L is not routed to Right MICPGA 01: IN3L is routed to Right MICPGA with 10K resistance 10: IN3L is routed to Right MICPGA with 20K resistance 11: IN3L is routed to Right MICPGA with 40K resistance D1–D0 R/W 00 CM to Right MICPGA (CM2R) positive terminal selection 00: CM is not routed to Right MICPGA 01: CM is routed to Right MICPGA via CM2R with 10K resistance 10: CM is routed to Right MICPGA via CM2R with 20K resistance 11: CM is routed to Right MICPGA via CM2R with 40K resistance DESCRIPTION 6.2.137 Page 1 / Register 58: 146 BIT READ/ WRITE RESET VALUE D7 R/W 0 REGISTER MAP Floating Input Configuration Register DESCRIPTION 0: IN1L input is not weakly connected to common mode 1: IN1L input is weakly driven to common mode. Use when not routing IN1L to Left and Right MICPGA and HPL Submit Documentation Feedback TLV320AIC3254 Ultra Low Power Stereo Audio Codec With Embedded miniDSP www.ti.com SLAS549A – SEPTEMBER 2008 – REVISED OCTOBER 2008 (continued) BIT READ/ WRITE RESET VALUE D6 R/W 0 0: IN1R input is not weakly connected to common mode 1: IN1R input is weakly driven to common mode. Use when not routing IN1L to Left and Right MICPGA and HPR D5 R/W 0 0: IN2L input is not weakly connected to common mode 1: IN2L input is weakly driven to common mode. Use when not routing IN2L to Left and Right MICPGA D4 R/W 0 0: IN2R input is not weakly connected to common mode 1: IN2R input is weakly driven to common mode. Use when not routing IN2R to Left and Right MICPGA D3 R/W 0 0: IN3L input is not weakly connected to common mode 1: IN3L input is weakly driven to common mode. Use when not routing IN3L to Left and Right MICPGA D2 R/W 0 0: IN3R input is not weakly connected to common mode 1: IN3R input is weakly driven to common mode. Use when not routing IN3R to Left and Right MICPGA D1–D0 R 00 Reserved. Write only default values DESCRIPTION 6.2.138 Page 1 / Register 59: BIT READ/ WRITE RESET VALUE D7 R/W 1 D6–D0 R/W 000 0000 DESCRIPTION 0: Left MICPGA Gain is enabled 1: Left MICPGA Gain is set to 0dB Left MICPGA Volume Control 000 0000: Volume Control = 0.0dB 000 0001: Volume Control = 0.5dB 000 0010: Volume Control = 1.0dB … 101 1101: Volume Control = 46.5dB 101 1110: Volume Control = 47.0dB 101 1111: Volume Control = 47.5dB 110 0000-111 1111: Reserved. Do not use 6.2.139 Page 1 / Register 60: BIT READ/ WRITE RESET VALUE D7 R/W 1 D6–D0 R/W 000 0000 READ/ WRITE RESET VALUE D7–D0 R/W 0000 0000 Submit Documentation Feedback Right MICPGA Volume Control Register DESCRIPTION 0: Right MICPGA Gain is enabled 1: Right MICPGA Gain is set to 0dB Right MICPGA Volume Control 000 0000: Volume Control = 0.0dB 000 0001: Volume Control = 0.5dB 000 0010: Volume Control = 1.0dB … 101 1101: Volume Control = 46.5dB 101 1110: Volume Control = 47.0dB 101 1111: Volume Control = 47.5dB 110 0000-111 1111: Reserved. Do not use 6.2.140 Page 1 / Register 61: BIT Left MICPGA Volume Control Register ADC Power Tune Configuration Register DESCRIPTION 0000 0110 1011 1111 0000: PTM_R4 (Default) 0100: PTM_R3 0110: PTM_R2 1111: PTM_R1 REGISTER MAP 147 TLV320AIC3254 Ultra Low Power Stereo Audio Codec With Embedded miniDSP SLAS549A – SEPTEMBER 2008 – REVISED OCTOBER 2008 6.2.141 Page 1 / Register 62: www.ti.com ADC Analog Volume Control Flag Register BIT READ/ WRITE RESET VALUE D7–D2 R 00 0000 D1 R 0 Left Channel Analog Volume Control Flag 0: Applied Volume is not equal to Programmed Volume 1: Applied Volume is equal to Programmed Volume D0 R 0 Right Channel Analog Volume Control Flag 0: Applied Volume is not equal to Programmed Volume 1: Applied Volume is equal to Programmed Volume DESCRIPTION Reserved. Write only default values 6.2.142 Page 1 / Register 63: BIT READ/ WRITE RESET VALUE D7 R 0 HPL Gain Flag 0: Applied Gain is not equal to Programmed Gain 1: Applied Gain is equal to Programmed Gain D6 R 0 HPR Gain Flag 0: Applied Gain is not equal to Programmed Gain 1: Applied Gain is equal to Programmed Gain D5 R 0 LOL Gain Flag 0: Applied Gain is not equal to Programmed Gain 1: Applied Gain is equal to Programmed Gain D4 R 0 LOR Gain Flag 0: Applied Gain is not equal to Programmed Gain 1: Applied Gain is equal to Programmed Gain D3 R 0 IN1L to HPL Bypass Volume Flag 0: Applied Volume is not equal to Programmed Volume 1: Applied Volume is equal to Programmed Volume D2 R 0 IN1R to HPR Bypass Volume Flag 0: Applied Volume is not equal to Programmed Volume 1: Applied Volume is equal to Programmed Volume D1 R 0 MAL Volume Flag 0: Applied Volume is not equal to Programmed Volume 1: Applied Volume is equal to Programmed Volume D0 R 0 MAR Volume Flag 0: Applied Volume is not equal to Programmed Volume 1: Applied Volume is equal to Programmed Volume DESCRIPTION 6.2.143 Page 1 / Register 64-70: BIT READ/ WRITE RESET VALUE D7–D0 R 0000 0000 READ/ WRITE BIT Reserved. Write only default values Analog Input Quick Charging Configuration Register RESET VALUE D7–D6 R 00 D5–D0 R/W 00 0000 DESCRIPTION Reserved. Write only default values Analog inputs power up time 00 0000: Default. Use one of the values give below 11 0001: Analog inputs power up time is 3.1 ms 11 0010: Analog inputs power up time is 6.4 ms 11 0011: Analog inputs power up time is 1.6 ms Others: Do not use 6.2.145 Page 1 / Register 72-122: BIT READ/ WRITE RESET VALUE D7–D0 R 0000 0000 REGISTER MAP Reserved Register DESCRIPTION 6.2.144 Page 1 / Register 71: 148 DAC Analog Gain Control Flag Register Reserved Register DESCRIPTION Reserved. Write only default values Submit Documentation Feedback TLV320AIC3254 Ultra Low Power Stereo Audio Codec With Embedded miniDSP www.ti.com SLAS549A – SEPTEMBER 2008 – REVISED OCTOBER 2008 6.2.146 Page 1 / Register 123: BIT READ/ WRITE RESET VALUE D7–D3 R 0 0000 D2–D0 R/W 000 Reference Power-up Configuration Register DESCRIPTION Reserved. Write only default values Reference Power Up configuration 000: Reference will power up slowly when analog blocks are powered up 001: Reference will power up in 40ms when analog blocks are powered up 010: Reference will power up in 80ms when analog blocks are powered up 011: Reference will power up in 120ms when analog blocks are powered up 100: Force power up of reference. Power up will be slow 101: Force power up of reference. Power up time will be 40ms 110: Force power up of reference. Power up time will be 80ms 111: Force power up of reference. Power up time will be 120ms 6.2.147 Page 1 / Register 124-127: BIT READ/ WRITE RESET VALUE D7–D0 R 0000 0000 DESCRIPTION Reserved. Write only default values 6.2.148 Page 8 / Register 0: BIT READ/ WRITE RESET VALUE D7–D0 R/W 0000 0000 Reserved Register Page Select Register DESCRIPTION Page Select Register 0-255: Selects the Register Page for next read or write command. Refer Table "Summary of Memory Map" for details. 6.2.149 Page 8 / Register 1: ADC Adaptive Filter Configuration Register READ/ WRITE RESET VALUE D7–D3 R 0000 0 D2 R/W 0 ADC Adaptive Filtering Control 0: Adaptive Filtering disabled for ADC 1: Adaptive Filtering enabled for ADC D1 R 0 ADC Adaptive Filter Buffer Control Flag 0: In adaptive filter mode, ADC accesses ADC Coefficient Buffer-A and control interface accesses ADC Coefficient Buffer-B 1: In adaptive filter mode, ADC accesses ADC Coefficient Buffer-B and control interface accesses ADC Coefficient Buffer-A D0 R/W 0 ADC Adaptive Filter Buffer Switch control 0: ADC Coefficient Buffers will not be switched at next frame boundary 1: ADC Coefficient Buffers will be switched at next frame boundary, if in adaptive filtering mode. This will self clear on switching. BIT DESCRIPTION Reserved. Write only default values 6.2.150 Page 8 / Register 1-7: BIT READ/ WRITE RESET VALUE D7–D0 R 0000 0000 DESCRIPTION Reserved. Write only default values 6.2.151 Page 8 / Register 8-127: BIT READ/ WRITE RESET VALUE D7–D0 R/W xxxx xxxx Submit Documentation Feedback Reserved ADC Coefficients Buffer-A C(0:29) DESCRIPTION 24-bit coefficients C0 through C29 of ADC Coefficient Buffer-A. Refer Table ?? for details When Page-8, Reg-01d, D2='0' the read write access to these registers is allowed only when ADC channel is powered down REGISTER MAP 149 TLV320AIC3254 Ultra Low Power Stereo Audio Codec With Embedded miniDSP SLAS549A – SEPTEMBER 2008 – REVISED OCTOBER 2008 6.2.152 Page 9-16 / Register 0: BIT READ/ WRITE RESET VALUE D7–D0 R/W 0000 0000 Page Select Register DESCRIPTION Page Select Register 0-255: Selects the Register Page for next read or write command. Refer Table "Summary of Memory Map" for details. 6.2.153 Page 9-16 / Register 1-7: BIT READ/ WRITE RESET VALUE D7–D0 R 0000 0000 Reserved DESCRIPTION Reserved. Write only default values 6.2.154 Page 9-16 / Register 8-127: BIT READ/ WRITE RESET VALUE D7–D0 R/W xxxx xxxx READ/ WRITE RESET VALUE D7–D0 R/W 0000 0000 24-bit coefficients ADC Coefficient Buffer-A. Refer Table ?? for details When Page-8, Reg-01d, D2='0' (Adaptive filtering disabled) the read write access to these registers is allowed only when ADC channel is powered down Page Select Register DESCRIPTION Page Select Register 0-255: Selects the Register Page for next read or write command. Refer Table "Summary of Memory Map" for details. 6.2.156 Page 26-34 / Register 1-7: BIT READ/ WRITE RESET VALUE D7–D0 R 0000 0000 READ/ WRITE RESET VALUE D7–D0 R/W xxxx xxxx Reserved. Write only default values READ/ WRITE RESET VALUE D7–D0 R/W 0000 0000 ADC Coefficients Buffer-B C(0:255) DESCRIPTION 24-bit coefficients of ADC Coefficient Buffer-B. Refer Table ?? for details When Page-8, Reg-01d, D2='0' (Adaptive filtering disabled) the read write access to these registers is allowed only when ADC channel is powered down 6.2.158 Page 44 / Register 0: BIT Reserved. DESCRIPTION 6.2.157 Page 26-34 / Register 8-127: BIT ADC Coefficients Buffer-A C(30:255) DESCRIPTION 6.2.155 Page 26-34 / Register 0: BIT www.ti.com Page Select Register DESCRIPTION Page Select Register 0-255: Selects the Register Page for next read or write command. Refer Table "Summary of Memory Map" for details. 6.2.159 Page 44 / Register 1: DAC Adaptive Filter Configuration Register BIT READ/ WRITE RESET VALUE D7–D3 R 0000 0 D2 R/W 0 DAC Adaptive Filtering Control 0: Adaptive Filtering disabled for DAC 1: Adaptive Filtering enabled for DAC D1 R 0 DAC Adaptive Filter Buffer Control Flag 0: In adaptive filter mode, DAC accesses DAC Coefficient Buffer-A and control interface accesses DAC Coefficient Buffer-B 1: In adaptive filter mode, DAC accesses DAC Coefficient Buffer-B and control interface accesses DAC Coefficient Buffer-A 150 REGISTER MAP DESCRIPTION Reserved. Write only default values Submit Documentation Feedback TLV320AIC3254 Ultra Low Power Stereo Audio Codec With Embedded miniDSP www.ti.com SLAS549A – SEPTEMBER 2008 – REVISED OCTOBER 2008 (continued) BIT READ/ WRITE RESET VALUE D0 R/W 0 DESCRIPTION DAC Adaptive Filter Buffer Switch control 0: DAC Coefficient Buffers will not be switched at next frame boundary 1: DAC Coefficient Buffers will be switched at next frame boundary, if in adaptive filtering mode. This will self clear on switching. 6.2.160 Page 44 / Register 1-7: BIT READ/ WRITE RESET VALUE D7–D0 R 0000 0000 Reserved DESCRIPTION Reserved. Write only default values 6.2.161 Page 44 / Register 8-127: BIT READ/ WRITE RESET VALUE D7–D0 R/W xxxx xxxx DESCRIPTION 24-bit coefficients C0 through C29 of DAC Coefficient Buffer-A. Refer Table ?? for details When Page-44, Reg-01d, D2='0' the read write access to these registers is allowed only when DAC channel is powered down 6.2.162 Page 45-52 / Register 0: BIT READ/ WRITE RESET VALUE D7–D0 R/W 0000 0000 READ/ WRITE RESET VALUE D7–D0 R 0000 0000 Page Select Register 0-255: Selects the Register Page for next read or write command. Refer Table "Summary of Memory Map" for details. READ/ WRITE RESET VALUE D7–D0 R/W xxxx xxxx Reserved. Write only default values READ/ WRITE RESET VALUE D7–D0 R/W 0000 0000 24-bit coefficients DAC Coefficient Buffer-A. Refer Table ?? for details When Page-44, Reg-01d, D2='0' (Adaptive filtering disabled) the read write access to these registers is allowed only when DAC channel is powered down READ/ WRITE RESET VALUE D7–D0 R 0000 0000 Submit Documentation Feedback Page Select Register DESCRIPTION Page Select Register 0-255: Selects the Register Page for next read or write command. Refer Table "Summary of Memory Map" for details. 6.2.166 Page 62-70 / Register 1-7: BIT DAC Coefficients Buffer-A C(30:255) DESCRIPTION 6.2.165 Page 62-70 / Register 0: BIT Reserved. DESCRIPTION 6.2.164 Page 45-52 / Register 8-127: BIT Page Select Register DESCRIPTION 6.2.163 Page 45-52 / Register 1-7: BIT DAC Coefficients Buffer-A C(0:29) Reserved. DESCRIPTION Reserved. Write only default values REGISTER MAP 151 TLV320AIC3254 Ultra Low Power Stereo Audio Codec With Embedded miniDSP SLAS549A – SEPTEMBER 2008 – REVISED OCTOBER 2008 www.ti.com 6.2.167 Page 62-70 / Register 8-127: BIT READ/ WRITE RESET VALUE D7–D0 R/W xxxx xxxx DESCRIPTION 24-bit coefficients of DAC Coefficient Buffer-B. Refer Table ?? for details When Page-44, Reg-01d, D2='0' (Adaptive filtering disabled) the read write access to these registers is allowed only when DAC channel is powered down 6.2.168 Page 80-114 / Register 0: BIT READ/ WRITE RESET VALUE D7–D0 R/W 0000 0000 DAC Coefficients Buffer-B C(0:255) Page Select Register DESCRIPTION Page Select Register 0-255: Selects the Register Page for next read or write command. Refer Table "Summary of Memory Map" for details. 6.2.169 Page 80-114 / Register 1-7: BIT READ/ WRITE RESET VALUE D7–D0 R 0000 0000 Reserved. DESCRIPTION Reserved. Write only default values 6.2.170 Page 80-114 / Register 8-127: BIT READ/ WRITE RESET VALUE D7–D0 R/W xxxx xxxx DESCRIPTION 24 bit instructions for ADC miniDSP engine. For details refer Table ?? in the datasheet. These instructions control the operation of ADC miniDSP mode. When the fully programmable miniDSP mode is enabled and ADC channel is powered up, the read and write access to these registers is disabled. 6.2.171 Page 152-186 / Register 0: BIT READ/ WRITE RESET VALUE D7–D0 R/W 0000 0000 READ/ WRITE RESET VALUE D7–D0 R 0000 0000 Page Select Register DESCRIPTION Page Select Register 0-255: Selects the Register Page for next read or write command. Refer Table "Summary of Memory Map" for details. 6.2.172 Page 152-186 / Register 1-7: BIT ADC miniDSP Instructions Reserved. DESCRIPTION Reserved. Write only default values 6.2.173 Page 152-186 / Register 8-127: BIT READ/ WRITE RESET VALUE D7–D0 R/W xxxx xxxx DAC miniDSP Instructions DESCRIPTION 24 bit instructions for DAC miniDSP engine. For details refer Table ?? in the datasheet. These instructions control the operation of DAC miniDSP mode. When the fully programmable miniDSP mode is enabled and DAC channel is powered up, the read and write access to these registers is disabled. 6.3 ADC Coefficients A+B Table 6-2. ADC Coefficient Buffer-A Map Coef No Page No Base Register Base Register + 0 Base Register + 1 Base Register + 2 Base Register + 3 C0 8 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. C1 8 12 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. … .. .. .. .. .. .. C29 8 124 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. 152 REGISTER MAP Submit Documentation Feedback TLV320AIC3254 Ultra Low Power Stereo Audio Codec With Embedded miniDSP www.ti.com SLAS549A – SEPTEMBER 2008 – REVISED OCTOBER 2008 Table 6-2. ADC Coefficient Buffer-A Map (continued) Coef No Page No Base Register Base Register + 0 Base Register + 1 Base Register + 2 Base Register + 3 C30 9 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. … .. .. .. .. .. .. C59 9 124 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. C60 10 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. … .. .. .. .. .. .. C89 10 124 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. C90 11 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. … .. .. .. .. .. .. C119 11 124 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. C120 12 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. … .. .. .. .. .. .. C149 12 124 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. C150 13 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. … .. .. .. .. .. .. C179 13 124 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. C180 14 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. … .. .. .. .. .. .. C209 14 124 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. C210 15 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. … .. .. .. .. .. .. C239 15 124 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. C240 16 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. … .. .. .. .. .. .. C255 16 68 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. Table 6-3. ADC Coefficient Buffer-B Map Coef No Page No Base Register Base Register + 0 Base Register + 1 Base Register + 2 Base Register + 3 C0 26 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. C1 26 12 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. … .. .. .. .. .. .. C29 26 124 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. C30 27 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. … .. .. .. .. .. .. C59 27 124 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. C60 28 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. … .. .. .. .. .. .. C89 28 124 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. C90 29 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. … .. .. .. .. .. .. C119 29 124 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. C120 30 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. … .. .. .. .. .. .. C149 30 124 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. C150 31 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. … .. .. .. .. .. .. C179 31 124 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. C180 32 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. Submit Documentation Feedback REGISTER MAP 153 TLV320AIC3254 Ultra Low Power Stereo Audio Codec With Embedded miniDSP SLAS549A – SEPTEMBER 2008 – REVISED OCTOBER 2008 www.ti.com Table 6-3. ADC Coefficient Buffer-B Map (continued) Coef No Page No Base Register Base Register + 0 Base Register + 1 Base Register + 2 Base Register + 3 … .. .. .. .. .. .. C209 32 124 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. C210 33 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. … .. .. .. .. .. .. C239 33 124 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. C240 34 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. … .. .. .. .. .. .. C255 34 68 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. 6.4 ADC Defaults Table 6-4. Default values of ADC Coefficients in Buffers A and B ADC Buffer-A,B Coefficients 154 REGISTER MAP Default Value at reset C0 00000000H C1 00170000H C2 00170000H C3 7DD30000H C4 7FFFFF00H C5,C6 00000000H C7 7FFFFF00H C8,..,C11 00000000H C12 7FFFFF00H C13,..,C16 00000000H C17 7FFFFF00H C18,..,C21 00000000H C22 7FFFFF00H C23,..,C26 00000000H C27 7FFFFF00H C28,..,C35 00000000H C36 7FFFFF00H C37,C38 00000000H C39 7FFFFF00H C40,..,C43 00000000H C44 7FFFFF00H C45,..,C48 00000000H C49 7FFFFF00H C50,..,C53 00000000H C54 7FFFFF00H C55,..,C58 00000000H C59 7FFFFF00H C60,..,C255 00000000H Submit Documentation Feedback TLV320AIC3254 Ultra Low Power Stereo Audio Codec With Embedded miniDSP www.ti.com SLAS549A – SEPTEMBER 2008 – REVISED OCTOBER 2008 6.5 DAC Coefficients A+B Table 6-5. DAC Coefficient Buffer-A Map Coef No Page No Base Register Base Register + 0 Base Register + 1 Base Register + 2 Base Register + 3 C0 44 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. C1 44 12 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. … .. .. .. .. .. .. C29 44 124 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. C30 45 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. … .. .. .. .. .. .. C59 45 124 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. C60 46 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. … .. .. .. .. .. .. C89 46 124 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. C90 47 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. … .. .. .. .. .. .. C119 47 124 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. C120 48 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. … .. .. .. .. .. .. C149 48 124 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. C150 49 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. … .. .. .. .. .. .. C179 49 124 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. C180 50 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. … .. .. .. .. .. .. C209 50 124 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. C210 51 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. … .. .. .. .. .. .. C239 51 124 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. C240 52 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. … .. .. .. .. .. .. C255 52 68 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. Table 6-6. DAC Coefficient Buffer-B Map Coef No Page No Base Register Base Register + 0 Base Register + 1 Base Register + 2 Base Register + 3 C0 62 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. C1 62 12 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. … .. .. .. .. .. .. C29 62 124 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. C30 63 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. … .. .. .. .. .. .. C59 63 124 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. C60 64 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. … .. .. .. .. .. .. C89 64 124 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. C90 65 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. … .. .. .. .. .. .. C119 65 124 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. C120 66 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. Submit Documentation Feedback REGISTER MAP 155 TLV320AIC3254 Ultra Low Power Stereo Audio Codec With Embedded miniDSP SLAS549A – SEPTEMBER 2008 – REVISED OCTOBER 2008 www.ti.com Table 6-6. DAC Coefficient Buffer-B Map (continued) Coef No Page No Base Register Base Register + 0 Base Register + 1 Base Register + 2 Base Register + 3 … .. .. .. .. .. .. C149 66 124 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. C150 67 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. … .. .. .. .. .. .. C179 67 124 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. C180 68 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. … .. .. .. .. .. .. C209 68 124 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. C210 69 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. … .. .. .. .. .. .. C239 69 124 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. C240 70 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. … .. .. .. .. .. .. C255 70 68 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. 6.6 DAC Defaults Table 6-7. Default values of DAC Coefficients in Buffers A and B 156 DAC Buffer-A,B Coefficients Default Value at reset C0 00000000H C1 7FFFFF00H C2,..,C5 00000000H C6 7FFFFF00H C7,..,C10 00000000H C11 7FFFFF00H C12,..,C15 00000000H C16 7FFFFF00H C17,..,C20 00000000H C21 7FFFFF00H C22,..,C25 00000000H C26 7FFFFF00H C27,..,C30 00000000H C31,C32 00000000H C33 7FFFFF00H C34,..,C37 00000000H C38 7FFFFF00H C39,..,C42 00000000H C43 7FFFFF00H C44,..,C47 00000000H C48 7FFFFF00H C49,..,C52 00000000H C53 7FFFFF00H C54,..,C57 00000000H C58 7FFFFF00H C59,..,C64 00000000H C65 7FFFFF00H REGISTER MAP Submit Documentation Feedback TLV320AIC3254 Ultra Low Power Stereo Audio Codec With Embedded miniDSP www.ti.com SLAS549A – SEPTEMBER 2008 – REVISED OCTOBER 2008 Table 6-7. Default values of DAC Coefficients in Buffers A and B (continued) DAC Buffer-A,B Coefficients Default Value at reset C66,C67 00000000H C68 7FFFFF00H C69,C70 00000000H C71 7FF70000H C72 10090000H C73 7FEF0000H C74,C75 00110000H C76 7FDE0000H C77,..,C255 00000000H 6.7 ADC miniDSP Instructions Table 6-8. ADC miniDSP Instruction Map Coef No Page No Base Register Base Register + 0 Base Register + 1 Base Register + 2 Base Register + 3 I0 80 8 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. I1 80 12 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. … .. .. .. .. .. .. I29 80 124 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. I30 81 8 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. … .. .. .. .. .. .. I59 81 124 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. I60 82 8 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. … .. .. .. .. .. .. I89 82 124 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. I90 83 8 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. … .. .. .. .. .. .. I119 83 124 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. I120 84 8 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. … .. .. .. .. .. .. I149 84 124 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. I150 85 8 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. … .. .. .. .. .. .. I179 85 124 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. I180 86 8 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. … .. .. .. .. .. .. I209 86 124 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. I210 87 8 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. … .. .. .. .. .. .. I239 87 124 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. I240 88 8 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. … .. .. .. .. .. .. I269 88 124 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. I270 89 8 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. … .. .. .. .. .. .. I299 89 124 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. I300 90 8 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. … .. .. .. .. .. .. Submit Documentation Feedback REGISTER MAP 157 TLV320AIC3254 Ultra Low Power Stereo Audio Codec With Embedded miniDSP SLAS549A – SEPTEMBER 2008 – REVISED OCTOBER 2008 www.ti.com Table 6-8. ADC miniDSP Instruction Map (continued) Coef No Page No Base Register Base Register + 0 Base Register + 1 Base Register + 2 Base Register + 3 I329 90 124 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. I330 91 8 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. … .. .. .. .. .. .. I359 91 124 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. I360 92 8 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. … .. .. .. .. .. .. I389 92 124 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. I390 93 8 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. … .. .. .. .. .. .. I419 93 124 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. I420 94 8 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. … .. .. .. .. .. .. I449 94 124 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. I450 95 8 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. … .. .. .. .. .. .. I479 95 124 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. I480 96 8 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. … .. .. .. .. .. .. I509 96 124 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. I510 97 8 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. … .. .. .. .. .. .. I539 97 124 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. I540 98 8 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. … .. .. .. .. .. .. I569 98 124 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. I570 99 8 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. … .. .. .. .. .. .. I599 99 124 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. I600 100 8 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. … .. .. .. .. .. .. I629 100 124 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. I630 101 8 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. … .. .. .. .. .. .. I659 101 124 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. I660 102 8 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. … .. .. .. .. .. .. I689 102 124 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. I690 103 8 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. … .. .. .. .. .. .. I719 103 124 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. I720 104 8 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. … .. .. .. .. .. .. I749 104 124 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. I750 105 8 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. … .. .. .. .. .. .. I779 105 124 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. I780 106 8 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. 158 REGISTER MAP Submit Documentation Feedback TLV320AIC3254 Ultra Low Power Stereo Audio Codec With Embedded miniDSP www.ti.com SLAS549A – SEPTEMBER 2008 – REVISED OCTOBER 2008 Table 6-8. ADC miniDSP Instruction Map (continued) Coef No Page No Base Register Base Register + 0 Base Register + 1 Base Register + 2 Base Register + 3 … .. .. .. .. .. .. I809 106 124 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. I810 107 8 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. … .. .. .. .. .. .. I839 107 124 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. I840 108 8 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. … .. .. .. .. .. .. I869 108 124 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. I870 109 8 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. … .. .. .. .. .. .. I899 109 124 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. I900 110 8 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. … .. .. .. .. .. .. I929 110 124 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. I930 111 8 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. … .. .. .. .. .. .. I959 111 124 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. I960 112 8 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. … .. .. .. .. .. .. I989 112 124 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. I990 113 8 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. … .. .. .. .. .. .. I1019 113 124 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. I1020 114 8 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. … .. .. .. .. .. .. I1023 114 20 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. 6.8 DAC miniDSP Instructions Table 6-9. DAC miniDSP Instruction Map Coef No Page No Base Register Base Register + 0 Base Register + 1 Base Register + 2 Base Register + 3 I0 152 8 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. I1 152 12 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. … … .. .. .. .. .. I29 152 124 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. I30 153 8 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. … … .. .. .. .. .. I59 153 124 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. I60 154 8 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. … … .. .. .. .. .. I89 154 124 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. I90 155 8 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. … … .. .. .. .. .. I119 155 124 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. I120 156 8 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. … … .. .. .. .. .. I149 156 124 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. Submit Documentation Feedback REGISTER MAP 159 TLV320AIC3254 Ultra Low Power Stereo Audio Codec With Embedded miniDSP SLAS549A – SEPTEMBER 2008 – REVISED OCTOBER 2008 www.ti.com Table 6-9. DAC miniDSP Instruction Map (continued) Coef No Page No Base Register Base Register + 0 Base Register + 1 Base Register + 2 Base Register + 3 I150 157 8 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. … … .. .. .. .. .. I179 157 124 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. I180 158 8 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. … … .. .. .. .. .. I209 158 124 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. I210 159 8 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. … … .. .. .. .. .. I239 159 124 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. I240 160 8 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. … … .. .. .. .. .. I269 160 124 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. I270 161 8 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. … … .. .. .. .. .. I299 161 124 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. I300 162 8 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. … … .. .. .. .. .. I329 162 124 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. I330 163 8 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. … … .. .. .. .. .. I359 163 124 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. I360 164 8 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. … … .. .. .. .. .. I389 164 124 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. I390 165 8 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. … … .. .. .. .. .. I419 165 124 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. I420 166 8 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. … … .. .. .. .. .. I449 166 124 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. I450 167 8 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. … … .. .. .. .. .. I479 167 124 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. I480 168 8 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. … … .. .. .. .. .. I509 168 124 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. I510 169 8 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. … … .. .. .. .. .. I539 169 124 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. I540 170 8 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. … … .. .. .. .. .. I569 170 124 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. I570 171 8 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. … … .. .. .. .. .. I599 171 124 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. I600 172 8 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. … … .. .. .. .. .. 160 REGISTER MAP Submit Documentation Feedback TLV320AIC3254 Ultra Low Power Stereo Audio Codec With Embedded miniDSP www.ti.com SLAS549A – SEPTEMBER 2008 – REVISED OCTOBER 2008 Table 6-9. DAC miniDSP Instruction Map (continued) Coef No Page No Base Register Base Register + 0 Base Register + 1 Base Register + 2 Base Register + 3 I629 172 124 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. I630 173 8 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. … … .. .. .. .. .. I659 173 124 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. I660 174 8 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. … … .. .. .. .. .. I689 174 124 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. I690 175 8 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. … … .. .. .. .. .. I719 175 124 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. I720 176 8 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. … … .. .. .. .. .. I749 176 124 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. I750 177 8 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. … … .. .. .. .. .. I779 177 124 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. I780 178 8 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. … … .. .. .. .. .. I809 178 124 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. I810 179 8 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. … … .. .. .. .. .. I839 179 124 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. I840 180 8 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. … … .. .. .. .. .. I869 180 124 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. I870 181 8 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. … … .. .. .. .. .. I899 181 124 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. I900 182 8 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. … … .. .. .. .. .. I929 182 124 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. I930 183 8 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. … … .. .. .. .. .. I959 183 124 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. I960 184 8 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. … … .. .. .. .. .. I989 184 124 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. I990 185 8 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. … … .. .. .. .. .. I1019 185 124 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. I1020 186 8 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. … … .. .. .. .. .. I1023 186 20 Instr(23:16) Instr(15:8) Instr(7:0) Reserved. Submit Documentation Feedback REGISTER MAP 161 PACKAGE OPTION ADDENDUM www.ti.com 23-Oct-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TLV320AIC3254IRHBR ACTIVE QFN RHB 32 3000 Green (RoHS & no Sb/Br) TLV320AIC3254IRHBT ACTIVE QFN RHB 32 250 TBD Lead/Ball Finish CU NIPDAU Call TI MSL Peak Temp (3) Level-3-260C-168 HR Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 23-Oct-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device TLV320AIC3254IRHBR Package Package Pins Type Drawing QFN RHB 32 SPQ Reel Reel Diameter Width (mm) W1 (mm) 3000 330.0 12.4 Pack Materials-Page 1 A0 (mm) B0 (mm) K0 (mm) P1 (mm) 5.3 5.3 1.5 8.0 W Pin1 (mm) Quadrant 12.0 Q2 PACKAGE MATERIALS INFORMATION www.ti.com 23-Oct-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV320AIC3254IRHBR QFN RHB 32 3000 346.0 346.0 29.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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