TLV320AIC3268EVM-U

User's Guide SLAU564A – February 2014 – Revised February 2014 TLV320AIC3268EVM-U Evaluation Module This User’s Guide describes the operation, use, and features of the TLV320AIC3268EVM-U. For questions and support go to the E2E forums (e2e.ti.com). The main contents of this document are: • Hardware descriptions and implementation • Start up procedure using PurePath™ Console 2 (PPC2) software with the AIC3268 plug-in Table 1. Related Documents Document Title 1 2 3 4 5 6 7 8 9 Literature Number TLV320AIC3268 Data Sheet SLAS953 PurePath Graphic Development Suite PurePath Console Contents Features ...................................................................................................................... 2 Introduction .................................................................................................................. 2 2.1 Electrostatic Discharge Warning ................................................................................. 2 2.2 Unpacking the EVM ................................................................................................ 3 Getting Started .............................................................................................................. 4 PurePath Console 2 Software ............................................................................................. 4 4.1 Installation ........................................................................................................... 4 4.2 Graphical User Interface (GUI) ................................................................................... 5 TLV320AIC3268EVM-U Default Jumper Locations .................................................................... 7 TLV320AIC3268EVM-U EVM Schematics .............................................................................. 8 TLV320AIC3268EVM-U EVM Board Layout ........................................................................... 17 TLV320AIC3268EVM-U Bill of Materials ............................................................................... 19 Writing Scripts .............................................................................................................. 22 List of Figures 1 TLV320AIC3268EVM-U Top Board Photo .............................................................................. 3 2 TLV320AIC3268EVM-U Bottom Board Photo ........................................................................... 3 3 Main Panel ................................................................................................................... 5 4 Register Inspector Window ................................................................................................ 6 5 TLV320AIC3268RGC Block Diagram .................................................................................... 8 6 TAS1020BPFB USB Controller ........................................................................................... 9 7 Sample Rate Converters for ASIs ....................................................................................... 10 8 GPIO and MCLK for AIC3268 ........................................................................................... 11 9 LDO Supplies and Analog Outputs ..................................................................................... TLV320AIC3268 Schematic .............................................................................................. Audio Connectors ......................................................................................................... I2C Translation and Selection ............................................................................................ Breakout Board Connections ............................................................................................ Top Xray View ............................................................................................................. 12 10 11 12 13 14 13 14 15 16 17 PurePath is a trademark of Texas Instruments. Windows is a registered trademark of Microsoft Corporation. SLAU564A – February 2014 – Revised February 2014 Submit Documentation Feedback TLV320AIC3268EVM-U Evaluation Module Copyright © 2014, Texas Instruments Incorporated 1 Features 1 15 Silkscreen Top ............................................................................................................. 17 16 Silkscreen Bottom ......................................................................................................... 18 Features • • • 2 www.ti.com Full featured EVM with the TLV320AIC3268 Audio Codec USB connection to PC provides power, control and streaming audio for quick evaluation Easy-to-use PurePath Console 2 software provides graphical user interface to configure and control AIC3268 Introduction This specific evaluation module (EVM) is a programmable USB audio device that features the TLV320AIC3268 Audio Codec with miniDSP. 2.1 Electrostatic Discharge Warning Many of the components on the EVM are susceptible to damage by electrostatic discharge (ESD). Users are advised to observe proper ESD handling precautions when unpacking and handling the EVM, including the use of a grounded wrist strap at an approved ESD workstation. CAUTION Failure to observe ESD handling procedures can result in damage to EVM components. 2 TLV320AIC3268EVM-U Evaluation Module SLAU564A – February 2014 – Revised February 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Introduction www.ti.com 2.2 Unpacking the EVM On opening the TLV320AIC3268EVM-U package, ensure that the following item is included: • One TLV320AIC3268EVM-U board using one TLV320AIC3268 (Figure 1 and Figure 2) If either of the board or the TLV320AIC3268 device is missing, contact the Texas Instruments Product Information Center to inquire about a replacement. Figure 1. TLV320AIC3268EVM-U Top Board Photo Figure 2. TLV320AIC3268EVM-U Bottom Board Photo SLAU564A – February 2014 – Revised February 2014 Submit Documentation Feedback TLV320AIC3268EVM-U Evaluation Module Copyright © 2014, Texas Instruments Incorporated 3 Getting Started 3 www.ti.com Getting Started 1. Request and download the PPC2 software located in the EVM product folder on the web. 2. Connect the EVM to USB port, LED lights LED1 and LED2 should illuminate once the EVM is detected by Windows® PC. Also, in the Windows Device Manager, the EVM should be recognized as a USB composite device, a USB audio device and an HID-compliant device. 3. Connect headphones to jack J7, labeled HP OUT. 4. Open PPC2 and in the Command Buffer Interface select Open. 5. Download the most up-to-date scripts from the product folder. Navigate to that folder and select script 1.1 and click Execute. 6. Play audio through any media tool. Make sure that the playback (and recording) device is USBAudioEVM in the Windows control panel. • To adjust playback volume, open Sound in control panel, select the USB-AudioEVM device and click Properties. • Similarly, the other example configurations can be tried and sound can be recorded using the microphone available on the board. 7. Install jumpers on the EVM as per the requirements to make the right signal connections. 4 PurePath Console 2 Software 4.1 Installation 1. 2. 3. 4. 4 Request and download the PPC2 software located in the TLV320AIC3268 product folder. Open the self-extracting installation file, and extract contents to a known folder. Install the software by double clicking the setup executable and follow the directions. Connect the EVM to a USB port using a micro-USB cable and open PurePath Console 2. If prompted, select the appropriate EVM name. TLV320AIC3268EVM-U Evaluation Module SLAU564A – February 2014 – Revised February 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated PurePath Console 2 Software www.ti.com 4.2 4.2.1 Graphical User Interface (GUI) Main panel window The main panel, shown in Figure 3, provides direct access to the I2C settings of the AIC3268. On the main panel, users can configure the registers through the single byte write and read or through the Command Buffer Interface. The analog setup, digital setup, audio inputs, audio outputs, DRC, AGC, SAR and headset detection can be configured through this interface. The EVM status, which reflects the hardware connection of the EVM, is shown on the bottom left of the main panel. Figure 3. Main Panel 4.2.2 Typical Configuration In the product folder there are example scripts for typical playback and record applications. These configurations are used through the Command Buffer Interface. 4.2.3 I2C Logger The Command Buffer Interface communicates with the TLV320AIC3268 using a simple scripting language (described in Section 9). The TAS1020B USB controller handles all communication between the PC and the codec. A script is loaded into the command buffer, either by loading a script file using the Open button or by pasting text from the clipboard. Click Run to execute the command buffer. To record the I2C communication between the PC and the device, there is an I2C Logger in the bottom right of the GUI. The I2C Logger records all register writes sent to the codec when the Logging box is checked. The recorded register values along with their page numbers are displayed in the I2C Logger Window. Pressing the Clear button clears the content of the logger. SLAU564A – February 2014 – Revised February 2014 Submit Documentation Feedback TLV320AIC3268EVM-U Evaluation Module Copyright © 2014, Texas Instruments Incorporated 5 PurePath Console 2 Software 4.2.4 www.ti.com Register Inspector Figure 4. Register Inspector Window The contents of the TLV320AIC3268 register map can be accessed through the Registers tab in PPC2. The Page number control selects the page to be displayed in the register table. The register table contains information such as register name, current register value and the bit field of the current register value. Specify the page number when using the register inspector table. Once the page is specified, the register value can then be inspected or changed by either entering the hex value of the register or changing the corresponding bits for that register. 6 TLV320AIC3268EVM-U Evaluation Module SLAU564A – February 2014 – Revised February 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated TLV320AIC3268EVM-U Default Jumper Locations www.ti.com 5 TLV320AIC3268EVM-U Default Jumper Locations Table 2 displays the default jumper location information. Table 2. Default Jumper Locations Jumper Position Jumper Position JP1 Shorted JP31 Shorted JP2 Shorted JP32 Shorted JP3 Open JP33 1-2 JP4 2-3 JP34 1-2 JP5 2-3 JP35 Shorted JP6 2-3 JP36 Shorted JP7 2-3 JP37 1-2 JP8 2-3 JP38 2-3 JP9 2-3 JP39 Shorted JP10 2-3 JP40 2-3 JP11 2-3 JP41 Shorted JP12 2-3 JP42 Open JP13 2-3 JP43 Open JP14 2-3 JP44 2-3 JP15 2-3 JP45 Shorted JP16 2-3 JP46 Open JP17 2-3 JP47 Open JP18 2-3 JP48 Shorted JP19 2-3 JP49 Shorted JP20 1-2 JP50 1-2 JP21 1-2 JP51 1-2 JP22 1-2 JP52 Open JP23 1-2 JP53 Open JP24 Shorted JP54 Open JP25 Shorted JP55 Open JP26 Shorted JP56 Open JP27 Open JP57 Open JP28 Open JP58 Open JP29 Shorted JP59 Open JP30 Shorted SLAU564A – February 2014 – Revised February 2014 Submit Documentation Feedback TLV320AIC3268EVM-U Evaluation Module Copyright © 2014, Texas Instruments Incorporated 7 TLV320AIC3268EVM-U EVM Schematics 6 www.ti.com TLV320AIC3268EVM-U EVM Schematics The schematics for the TLV320AIC3268EVM-U are shown in Figure 5 through Figure 12. TLV320AIC3268RGC EVALUATION BOARD TAS1020B USB CONTROLLER AUDIO TLV320AIC3268 TI MICBIAS MICBIAS_EXT 37 RECVDD_33 38 RECP 39 AVDD2_18 40 RECM 41 HVDD_18 42 I2C & SPI HPR 43 HPVSS_SENSE 44 HPL 45 CPFCM 46 VNEG 47 CPVDD_18 48 CPFCP LOR LOL QFN, Top View 36 35 34 33 I2C & SPI CONTROL INTERFACE I2S #1 AUDIO INTERFACE ASI#1 AVDD4_18 49 32 MICBIAS_VDD SPKP 50 31 MICDET SVDD 51 30 AVDD1_18 SPKM 52 29 IN4L SPK_V 53 28 IN4R I2S #2 AUDIO INTERFACE B VBAT 54 27 VREF_SAR DVDD_18 55 26 VREF_AUDIO DVSS 56 25 IN1L_AUX1 DVSS 57 24 IN1R_AUX2 DOUT2 58 23 IN3L BCLK2 59 22 IN3R GPIO4 60 21 IN2R 5 6 7 8 9 10 11 12 13 14 15 16 DIN1 4 GPIO1 3 GPIO2 2 DOUT1 1 WCLK1 BCLK1 RESETZ 17 DVDD_18 64 IOVDD1_33 MCLK WCLK2 SCL_SSZ AVDD_18 18 I2C_ADDR/SCLK 19 63 GPIO5 62 DIN2 SDA_MOSI IOVDD2_33 MISO IN2L SPI_SELECT 20 GPIO3 61 IOVDD1_33 DVDD_18 I2C OPTICAL AUDIO INPUT SRC4392 A ASI#2 VSS CONTROL I2S #3 AUDIO INTERFACE B SRC #1 OPTICAL AUDIO OUTPUT I2C OPTICAL AUDIO INPUT SRC4392 ASI#3 A SRC #2 OPTICAL AUDIO OUTPUT 6 WIRE AUDIO I/F ANALOG OUTPUTS ANALOG INPUTS BLOCK DIAGRAM PAGE INFO: DESIGN LEAD JOHN FEDAK IV DATE JANUARY 31, 2014 FILENAME AIP013C_Schematic.sbk SCH REV C PCB REV C SHEET 1 OF 11 DRAWN BY L;DN Figure 5. TLV320AIC3268RGC Block Diagram 8 TLV320AIC3268EVM-U Evaluation Module SLAU564A – February 2014 – Revised February 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated TLV320AIC3268EVM-U EVM Schematics www.ti.com TLV320AIC3268RGC EVALUATION BOARD TAS1020B +3.3VIO 1 U5 1 JP1 2 3 1 4 R16 4.7k 8 2 +3.3VIO +3.3VIO R13 2.7k C6 0.1uF/16V 6.0MHz GND EE Program JP2 1 R17 4.7k GND 0.1uF/16V +3.3VIO GND R14 2.7k TAS_SCL 2 C12 +3.3VIO Y1 4 OE Vcc GNDOUT 3 2 +3.3VIO USB HOST ADAPTER TAS_SDA 7 +3.3VIO GND 6 +3.3VIO 5 24FC512-I/MF GND GND 1 2 U5 24FC512-I/MF PowerPAD 3 GND C14 GND +3.3VIO +5V 5v DataData+ ID_NC GND 1 2 FB5 1.50k R2 3 36 2 35 3 GND 4 5 34 33 32 31 TAS_MISO FB6 47pF/50V 47pF/50V GND +3.3VIO C4 GND GND 30 TAS_MOSI 8 9 29 28 TAS_SSz 10 27 TAS_SCLK 11 26 GND JP3 R8 649 R5 10k R6 10k 2 1 10 9 8 R15 10k GND CBTLV3253DBQ GND GND R7 10k DUT_RESETz 0.1uF/16V RESETz C3 S4 11 7 GND C10 USB RESET 12 6 2 +3.3VIO +3.3VIO R4 100k 13 5 I2S1_DOUT I2S_ENABLE 1 +3.3VIO 4 I2S2_DOUT_SRC GND ASI_S0 R10 10k LED1 Yellow R9 649 I2S3_DOUT_SRC 14 GND GND LED2 Yellow 15 3 0.1uF/16V 13 14 15 16 17 18 19 20 21 22 23 24 GND 2 R12 10k C8 0.1uF/16V 16 ASI_S1 LVC1G126DBVR 25 GND 12 0.1uF/16V C13 U4 1 TAS_MCLK GND U2 220ohms/2A GND +3.3VIO TAS1020BPFB C2 4 TAS_WCLK 7 C1 Y (ADC Data) 6 4 5 3.09k 1 R3 27.4 GND 0.1uF/16V TAS_DOUT 27.4 220ohms/2A A 48 47 46 45 44 43 42 41 40 39 38 37 0.1uF/16V C5 R1 J1 C7 5 TAS_BCLK GND 100pF/50V R11 USB INPUT U3 VCC (DAC Data) TAS_DIN C15 1000pF/50V OE PATCH 1 2 S1 GND 1.0uF/16V APP 1 S2 GND 2 DUT RESET 1 2 S3 C11 C9 C16 0.1uF/50V 0.1uF/50V 0.1uF/50V GND GND GND GND SCH REV TI C PCB REV C PAGE INFO: USB CONTROLLER DATE JANUARY 31, 2014 SHEET 2 DESIGN LEAD JOHN FEDAK IV FILENAME AIP013C_Schematic.sbk DRAWN BY OF 11 L;DN Figure 6. TAS1020BPFB USB Controller SLAU564A – February 2014 – Revised February 2014 Submit Documentation Feedback TLV320AIC3268EVM-U Evaluation Module Copyright © 2014, Texas Instruments Incorporated 9 TLV320AIC3268EVM-U EVM Schematics www.ti.com TLV320AIC3268RGC EVALUATION BOARD +3.3VIO IOVD1 C43 U14 14 0.1uF/16V GND 13 12 I2S1_DOUT 11 10 9 R29 8 +3.3VIO VCCB B1 A1 B2 A2 B3 A3 B4 A4 NC NC GND OE DATA, SAMPLE RATE CONVERTER 0.1uF/16V 1 VCCA C44 GND 2 DOUT1 3 DIN1 4 WCLK1 5 BCLK1 6 7 10k Use same IOVD for IOVD1 and IOVD2. BCLK3 -> GPIO2 (IOVD1) WCLK3 -> GPIO1 (IOVD1) DIN3 -> GPIO3 (IOVD2) DOUT3 -> GPIO4 (IOVD2) TXS0104EPWR GND I2S3_DOUT_SRC +3.3VIO IOVD2 C27 C28 U9 9 +3.3VIO +3.3VIO R18 C41 8 A3 B4 A4 NC NC OE DIN2 13 3 DOUT2 12 4 WCLK2 11 5 10 BCLK2 +3.3VIO GND C42 1 2 C30 VCC 0.1uF/16V 36 TXS0104EPWR 46 44 45 1 36 C29 35 34 33 4 33 32 C25 5 32 31 0.1uF/16V +3.3VIO 9 28 27 SRC1_LOCKz 11 26 SRC1_RXCXO 12 25 GND 1 INPUT 2 10uF/6.3V C24 23 24 21 22 19 20 17 18 15 16 14 13 +3.3VIO 0.1uF/16V GND GND GND GND 4.7k 9 28 10 27 SRC2_LOCKz 11 26 SRC2_RXCXO 12 25 GND 0.1uF/16V VCC GND 1 GND SRC1_MCLK INPUT 2 3 SHIELD GND GND GND C35 10uF/6.3V GND SRC2_RDYz C36 0.1uF/16V PLT133/T10W GND GND R23 0 SPDIF-OUT2 GND 29 GND GND SRC2_MCLK +3.3VIO R26 4.7k R25 R27 +1.8VIO 1.00k +1.8VIO +3.3VIO 0.1uF/16V 30 8 R24 SRC1_RDYz C37 31 SRC #2 SRC4392IPFBR i2c: 1110 001 GND GND GND SRC2_MCLK U10 7 C23 SHIELD 10uF/6.3V SRC1_MCLK C32 3 PLT133/T10W GND C33 23 GND 10 GND VCC 29 +3.3VIO 6 SPDIF-OUT1 GND SRC4392IPFBR i2c: 1110 000 8 +3.3VIO R20 0 24 0.1uF/16V 30 21 U6 SRC #1 7 22 6 19 +3.3VIO C20 +3.3VIO GND 20 GND 17 5 35 Connect Pin44 to Pin10, pin 10 to ground plane 3 18 4 2 0.1uF/16V 15 34 16 Connect Pin44 to Pin10, pin 10 to ground plane 3 14 2 GND BCLK3 7 GND C17 0.1uF/16V 10uF/6.3V 5 6 GND PLR135/T10 48 38 GND C21 A4 NC OE WCLK3 0.1uF/16V GND 37 40 39 42 41 44 43 46 48 45 10uF/6.3V 1 B4 DIN3 DOUT3 4 3 OUT 13 OUT PLR135/T10 GND A3 3 GND Case 3 GND GND B3 GND 2 GND 0.1uF/16V C31 Case 0.1uF/16V 10uF/6.3V A2 SPDIF-IN2 VCC GND 47 2 A1 B2 C38 47 SPDIF-IN1 1 C18 B1 0.1uF/16V 1 VCCA 10uF/6.3V R22 0 C19 10k U13 VCCB NC 8 +3.3VIO GND C26 R19 0 R21 7 TXS0104EPWR 10uF/6.3V 9 +3.3VIO 6 10k +3.3VIO C40 14 2 38 TAS_BCLK A2 B3 10 TAS_WCLK A1 B2 0.1uF/16V 37 11 (DAC Data) B1 40 TAS_DIN VCCB VCCA 39 12 GND 42 13 I2S2_DOUT_SRC GND IOVD1 +3.3VIO C39 0.1uF/16V 1 41 14 43 0.1uF/16V GND 10k R28 C34 1.00k C22 0.1uF/16V 0.1uF/16V GND GND TAS_SCL TAS_SDA RESETz C SCH REV TI C PCB REV PAGE INFO: SAMPLE RATE CONVERTERS FOR ASIs DATE JANUARY 31, 2014 SHEET DESIGN LEAD JOHN FEDAK IV FILENAME AIP013C_Schematic.sbk DRAWN BY 3 OF 11 L;DN Figure 7. Sample Rate Converters for ASIs 10 TLV320AIC3268EVM-U Evaluation Module SLAU564A – February 2014 – Revised February 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated TLV320AIC3268EVM-U EVM Schematics www.ti.com DATA CLOCKS TLV320AIC3268RGC EVALUATION BOARD U19 1 SRC1_MCLK_S1 TAS_MCLK +3.3VIO 16 2 15 3 14 4 13 5 12 6 11 7 10 R42 10k 8 R43 10k R39 +3.3VIO 357 U15 6 SRC1_LOCKz 1 1A 1Y 2 5 GND VCC 3 SRC1_RDYz 2A 2Y GND LVC2G17DBV +3.3VIO R30 4 +3.3VIO SRC2_LOCKz 1 2 +3.3VIO LED3 R31 SRC2_RDYz 357 C51 Green 10k 1Y LVC2G17DBV OE 2 GND Vcc GND OUT GND 4 5 LED5 ICLK 2 0.1uF/16V +3.3VIO R33 GND CLK VDD CLK/2 3 4 GND OE CBTLV3253DBQ GND GND S0 S1 +3.3VIO Green GND 8 7 6 +3.3VIO SRC1_MCLK R38 5 10k ICS542MLFT CLK1_DIV_S1 GND 357 C52 U18 1 3 22.5792MHz C47 Green 6 GND VCC 3 4 2A 2Y GND 0.1uF/16V 1A +3.3VIO OSC2 1 R32 357 U16 Green LED4 9 +3.3VIO +3.3VIO LED6 C48 GND 0.1uF16V SRC1_MCLK_S0 R37 10k CLK1_DIV_S0 0.1uF/16V +3.3VIO GND GND +3.3VIO +3.3VIO R36 1 10k 2 OSC1 OE Vcc GND OUT 4 3 U17 24.576MHz 1 GND 2 C45 3 0.1uF/16V 4 GND ICLK CLK VDD CLK/2 GND OE S0 S1 8 7 6 +3.3VIO R44 10k R35 5 10k ICS542MLFT C46 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 GND 0.1uF/16V SRC2_MCLK_S0 R45 10k GND CBTLV3253DBQ GND GND GND CLK2_DIV_S1 GND U20 1 SRC2_MCLK_S1 CLK2_DIV_S0 C53 GND SRC2_MCLK +3.3VIO +3.3VIO 24 U22 0.1uF/16V R34 20 CLK2_DIV_S1 19 CLK2_DIV_S0 CLK1_DIV_S1 18 10k 17 CLK1_DIV_S0 i2c: 1110 100 16 I2C_ADDR_SEL 15 MCLK_SEL TAS_SCL 22 14 MCLK_S1 TAS_SDA 23 13 MCLK_S0 11 SPI_SELECT 1 RESETz 3 10 6Wire1_EN +3.3VIO 1 SPI_SELECT is only information, Never drive this pin. Use Jumper JP51 instead MCLK_S1 U21 C49 16 2 15 3 14 9 ASI_S1 SRC2_MCLK 4 13 8 ASI_S0 SRC1_MCLK 5 TAS_MCLK 6 12 GND 11 21 6 SRC2_MCLK_S0 7 10 2 5 SRC1_MCLK_S1 8 9 12 4 SRC1_MCLK_S0 7 SRC2_MCLK_S1 R41 10k GND 0.1uF/16V MCLK_S0 SRC2_RXCXO SRC1_RXCXO R40 10k TCA9539PW GND GND GND U11 GND 1 2 7 MCLK_SEL 6 IOVD1 8 C50 GND 5 MCLK 0.1uF/16V 3 4 R46 10k GND GND GND C SCH REV TI C PCB REV PAGE INFO: BOARD GPIO & MCLK FOR AIC3268 DATE JANUARY 31, 2014 SHEET DESIGN LEAD JOHN FEDAK IV FILENAME AIP013C_Schematic.sbk DRAWN BY 4 OF 11 L;DN Figure 8. GPIO and MCLK for AIC3268 SLAU564A – February 2014 – Revised February 2014 Submit Documentation Feedback TLV320AIC3268EVM-U Evaluation Module Copyright © 2014, Texas Instruments Incorporated 11 TLV320AIC3268EVM-U EVM Schematics www.ti.com JP4 1 TP6 2 LDO SUPPLIES TLV320AIC3268RGC EVALUATION BOARD 3 MCLK GND JP7 3 JP8 1 JP6 3 3 3 2 TP9 TP10 1 TP8 2 TP7 1 JP5 +1.8VA 2 GND JP9 +3.3VA 3 C70 TP4 VR2 1 GND DOUT2_DUT GND R54 +1.8V_CP 3 4 47uF/6.3V TPS73618DBV 1.8V/400mA AV_ENABLE 0 2 J2 TEST1 1 2 3 TEST2 3 4 4 5 6 5 GND 6 DNP TP69 VR1 1 +1.8VD GND 4 TPS73618DBV 1.8V/400mA C71 47uF/6.3V GND DV_ENABLE 6 C90 MIC3 0.1uF/16V IOVD1 1 GND 1 2 2 3 1 +3.3VIO 1 GND 0.1uF/16V IOVD1 1 GND C74 GND MIC4 GND 1 2 4 2 B2 A2 3 GND GND TAS_BCLK GPIO3 +3.3VIO 6Wire1_EN GPIO4 R55 10k GND GND C72 0.1uF/16V GND VDD 2 SELECT 4 CLOCK 5 DATA 3 GND 6 1 TP63 TP64 TP65 TP66 TP67 TP68 U23 TXB0102DCU JP21 JP20 3 GND 0.1uF/16V TP62 GND 3 GND 6 C75 GND VDD 2 SELECT 4 CLOCK 5 DATA GND MIC5 3 SELECT CLOCK DATA GND MIC2 0.1uF/16V +1.8VIO IOVD2 JP23 +1.8VIO IOVD1 +3.3VIO 2 4 5 GND 6 C91 GND VDD B1 3 A1 10k TAS_WCLK 5 R51 GND GND GND JP22 1 3 5 2 C62 0.1uF/16V GND JP19 1 C63 10uF/6.3V JP18 0.1uF/16V +1.8VIO 2 VR4 IOVD2 C73 JP17 1 1 GND GPIO4 GPIO5 GND TP2 +5V DIN3 DOUT3 GND GPIO3 8 DV_ENABLE GND GND C69 47uF/6.3V WCLK3 GND GND 4 TPS73633DBV 3.3V/400mA BCLK3 GND GPIO2 Use same IOVD for IOVD1 and IOVD2. BCLK3 -> GPIO2 (IOVD1) WCLK3 -> GPIO1 (IOVD1) DIN3 -> GPIO3 (IOVD2) DOUT3 -> GPIO4 (IOVD2) 3 VCCA 3 gpio1/bclk3 OE 10k gpio2/wclk3 JP16 3 VCCB R50 GND gpio3/din3 JP15 3 6 C60 0.1uF/16V gpio4/dout3 JP14 3 1 C61 10uF/6.3V TP17 1 2 TP18 3 5 TP19 7 1 TP20 GPIO1 TP1 +3.3VIO VR5 JP13 IOVD1: GPIO1: Dig_Mic 1,2 Data and BCLK3 GPIO2: ADC_MOD_CLK and WCLK3 GPIO5: Dig_Mic 3,4 Data IOVD2: GPIO3: DIN3 GPIO4: DOUT3 GND 1 TPS73618DBV 1.8V/400mA +5V GND 47uF/6.3V DV_ENABLE GND GND B- DNP C67 3 10k 4 2 0.1uF/16V 3 1 R48 GND GND B+ GND 2 10uF/6.3V C56 A- Case 5 2 C57 7 A+ 2 +5V GND GND 1 GND GND 1 2 10k TP15 2 0.1uF/16V TP16 C68 1 R49 GND J3 R53 3 10uF/6.3V C58 SLIMbus SATA 0 5 2 C59 DOUT2 GND DIN2_DUT AV_ENABLE +5V BCLK2 DIN2 GND WCLK2_DUT 47ufd/6.3V TPS73633DBV 3.3V/400mA GND GND 3 2 10k 4 GND BCLK2_DUT 2 0.1uF/16V JP12 3 3 10uF/6.3V R52 GND JP11 3 WCLK2 2 C64 JP10 3 TP14 TP13 TP12 TP11 5 1 VR6 1 DOUT1_DUT 1 C65 DOUT1 GND DIN1_DUT GND TP5 +5V DIN1 GND WCLK1_DUT 1 TPS73618DBV 1.8V/400mA AV_ENABLE GND GND BCLK1 WCLK1 GND BCLK1_DUT C66 47ufd/6.3V 2 10k 4 2 3 1 R47 GND C54 0.1uF/16V 2 C55 10uF/6.3V 2 5 1 VR3 1 2 TP3 +5V 2 MCLK_DUT VDD 2 SELECT 4 CLOCK 5 DATA 3 GND GND GND TI LDOs & AIC3268 ANALOG OUTPUTS PAGE INFO: DESIGN LEAD JOHN FEDAK IV DATE JANUARY 31, 2014 FILENAME AIP013C_Schematic.sbk C SCH REV C PCB REV SHEET 5 OF 11 L;DN DRAWN BY Figure 9. LDO Supplies and Analog Outputs 12 TLV320AIC3268EVM-U Evaluation Module SLAU564A – February 2014 – Revised February 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated TLV320AIC3268EVM-U EVM Schematics www.ti.com JP47 JP44 VSYS_EXT 2 1 1 +1.8VD 3 C110 R65 200 10uF/10V + GND GND 1 2 SPKM GND 6A/125V SPKP GND TP41 C114 0.1uF/16V J6 C99 2 1 0.1uF/16V GND 0.1uF/16V C113 C111 C116 1.0uF/16V GND GND IOVD2 C112 220ohms/2A 1.0uF/16V 1 C115 1 2 JP46 2 0.1uF/16V +5V FB4 VSYS_EXT JP48 3 2 +1.8VIO TLV320AIC3268RGC EVALUATION BOARD spkp FB1 1.0uF/16V J5 1 GND TP40 GND +1.8VD 2 JP43 U1 JP25 GND 1 52 51 50 49 AIC_SPI_SELECT 4 45 SDA_MOSI 5 44 GPIO5 6 43 C105 C100 7 SCL_SSZ 8 41 9 40 10 39 AIC_RESETZ 11 38 WCLK1_DUT 12 37 GPIO2 13 36 DOUT1_DUT 14 35 DIN1_DUT 15 34 MICBIAS_DUT GPIO1 16 33 42 BCLK1_DUT 27 28 29 30 31 C102 JP39 2 C77 RECM +1.8VA 0.1uF/16V C103 10uF/10V 1 0.1uF/16V GND GND RECP GND JP38 MICBIAS_EXT_DUT +1.8VA +3.3VA 2 3 32 C117 10uF/10V C98 1.0uF/16V 0.1uF/16V GND C95 in2l C94 TP28 in4l 1.0ufd/10V R64 2.10k CP91 TP33 TP29 IN2R in4r 1.0ufd/10V JP28 TP32 1 2 C93 0.1uF/16V in3r 1 1.0uF/16V TP22 in3l micdet C92 2 1 1 2 TP21 1.0uF/16V VSYS_EXT R58 TP36 MICBIAS_EXT_DUT 100 JP36 2 1 1 2 JP33 JP34 JP35 R60 1.10k IN3L TP25 vref JP30 in1l C85 GND GND MICBIAS_EXT TP31 IN1L R59 2.10k 3 1 1 2 1 C78 IN3R JP31 +3.3VA IN4R JP29 2 JP37 IN4L in2r 1.0uF/10V R63 2.10k GND CP90 GND 1.0uF/16V 1 GND 2 GND 2 MIC1 JP40 +1.8VA GND 1 Shield 26 TP34 0.1uF/16V 100 R62 1.00k GND 2.2uF/10V HPL HPR 2 1 JP26 1.0uF/16V 3 JP27 MICBIAS 25 +1.8V_CP vref_sar 6 GND R61 24 C97 1 TP30 23 GND TP35 4 MICBIAS_DUT 22 GND IN2L 2 5 RIGHT 21 10uF/10V GND Vneg C118 C96 J4 20 MCLK_DUT +1.8VA LEFT 19 TP39 C109 C104 0.1uF/16V TP37 C101 3 U1 6A/125V GND 2.2ufd/10V HPVSS_SENSE DNP JP41 GND LLOUT ADDR_SCLK C107 DNP 2200pfd/50V 2 47 C106 1.00K C108 2200pfd/50V GND 48 RLOUT 2 R67 0.1uF/16V 1 53 2 TP38 1.00k 54 46 18 R66 C79 55 3 17 2 1 1 56 2 TEST1 TEST2 57 1 GND 58 3 0.1uF/16V 59 2 1.0uF/16V 60 2 2 1 C80 61 2 IOVD1 C81 62 JP42 2 0.1uF/16V GND 63 1 MISO_GPO1 C140 GPIO4 64 GPIO3 BCLK2_DUT GND DOUT2_DUT GND DIN2_DUT PowerPAD GND 1 1 WCLK2_DUT 1 C83 0.1uF/16V 120 OHMS/1.5A +1.8VA JP45 C84 10uF/10V + 2 1 JP24 2 120 OHMS/1.5A FB2 spkm 3 C89 TP27 1.0uF/16V C86 1.0uF/16V 1.0uF/16V R57 HS_MIC GND TP26 in1r IN1R 200 Ext_In1R TP24 Ext_Aux2 R56 JP32 200 2 1 +1.8VA C76 0.1uF/16V TI GND TLV320AIC3268 PAGE INFO: DESIGN LEAD JOHN FEDAK IV C87 0.1uF/16V GND TP23 Ext_Aux1 C88 0.1uF/16V GND DATE JANUARY 31, 2014 FILENAME AIP013C_Schematic.sbk C SCH REV C PCB REV SHEET 6 OF 11 L;DN DRAWN BY Figure 10. TLV320AIC3268 Schematic SLAU564A – February 2014 – Revised February 2014 Submit Documentation Feedback TLV320AIC3268EVM-U Evaluation Module Copyright © 2014, Texas Instruments Incorporated 13 TLV320AIC3268EVM-U EVM Schematics www.ti.com TLV320AIC3268RGC EVALUATION BOARD Shield 5 3 2 4 1 J8 GND TP42 hpl HPL 2 TP43 LEFT Shield 5 hpr 6 HPR 3 JP49 RIGHT 4 1 R73 J7 1 FB3 2 1 3 1 2 HS_MIC DNP 3 2 vss_sns 1 TP44 HPVSS_SENSE 2 Configuration JP50 220ohms/2A R68 1.00k TP45 1 3 R70 16.0 2 2200pF/50V GND C121 R71 32.4 2200pF/50V R90 16.0 JP52 GND 1-2 L-R-G-M 2-3 2-3 1.00k C122 GND GND 1 HPL 3 HPR JP51 1-2 R69 2 TP46 JP50 L-R-M-G JP51 GND JP53 GND R72 32.4 GND J9 TP53 1 2 recp RECP R78 1 JP56 2 32.4 GND TP54 RECM 3 recm 6A/125V RECP R76 R77 TP51 RECM TP52 1.00k C127 C128 2 1 2 1 1.00k 2200pF/50V 2200pF/50V JP54 JP55 GND GND TP47 llout C123 LLOUT 2 1.0ufF16V RLOUT rlout 6 1.0uF/16V TP50 JP57 2200pF/50V GND TI 2 C126 RIGHT 4 1.00k 1 2 1 1.00k C125 LLOUT 3 R75 R74 TP49 RLOUT LEFT 5 C124 Shield TP48 1 GND J10 2200pF/50V JP58 GND AUDIO CONNECTORS PAGE INFO: DESIGN LEAD JOHN FEDAK IV DATE JANUARY 31, 2014 FILENAME AIP013C_Schematic.sbk C SCH REV C PCB REV SHEET 7 OF 11 L;DN DRAWN BY Figure 11. Audio Connectors 14 TLV320AIC3268EVM-U Evaluation Module SLAU564A – February 2014 – Revised February 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated TLV320AIC3268EVM-U EVM Schematics www.ti.com TLV320AIC3268RGC EVALUATION BOARD TP55 TP56 TP57 ad/sclk scl/ssz sda/mosi C129 IOVD1 U24 8 0.1uF/16V GND ADDR_SCLK 1 AIC_ADDRESS 5 2 AIC_SCLK SCL_SSZ 7 SDA_MOSI 3 GND 6 IOVD1 4 +3.3VIO GND LVC2G157DCT C130 C131 7 0.1uF/16V GND GND 5 TAS_SSz 9 4 TAS_MOSI 10 3 2 8 1 GND 6 0.1uF/16V U25 GND AVC2T245RSW GND +3.3VIO C134 Install this jumper to use DUT in SPI mode 2 4 3 LVC2G04DBV R85 357 +3.3VIO +5V U27 C135 1 LED7 Green GND 2 0.1uF/16V 3 GND VCCA GND A VCCB OE B TXB0101DBV 5 4 GND 0.1uF/16V R84 7 TAS_SCL 6 TAS_SDA R82 806k GND 5 C132 EN VREF2 VREF1 SCL1 SDA2 SDA1 1 R79 2.7k 2 12 11 9 R87 10k 8 VCCB R80 2.7k 1 VCCA B1 A1 B2 A2 B3 A3 B4 A4 NC NC OE GND 0.1uF/16V GND 2 AIC_RESETZ AIC_ADDRESS 4 5 R88 6 10k 7 TXS0104EPW TP60 TP59 TP58 reset~ spi_sel gpo1/miso AIC_SPI_SELECT AIC_RESETZ MISO_GPO1 GND GND 3 LVC1G126DBV GND +3.3VIO 4 C139 GND AIC_SPI_SELECT 3 3 PCA9306DCT GND GND 13 10 TP61 +3.3VIO 1 4 GND SCL2 0.1uF/16V C120 14 2 U26 8 R89 1.00k U28 5 0.1uF/16V GND R81 200k GND 10k GND 10k DUT_RESETz I2C_ADDR_SEL IOVD1 C133 R83 IOVD1 U8 GND 0.1uF/16V R86 1.00k C136 6 +3.3VIO C119 SPI_SELECT C137 0.1uF/16V GND IOVD1 C138 6 1 5 1 7 6 2 0.1uF/16V GND 0.1uF/16V GND TAS_MISO 5 TAS_SCLK 4 9 3 10 GND 8 2 U7 GND +3.3VIO JP59 1 0.1uF/16V AIC_SCLK +3.3VIO U12 AVC2T245RSW GND TI I2C TRANSLATION AND SELECTION PAGE INFO: DESIGN LEAD JOHN FEDAK IV DATE JANUARY 31, 2014 FILENAME AIP013C_Schematic.sbk C SCH REV C PCB REV SHEET 8 OF 11 L;DN DRAWN BY Figure 12. I2C Translation and Selection SLAU564A – February 2014 – Revised February 2014 Submit Documentation Feedback TLV320AIC3268EVM-U Evaluation Module Copyright © 2014, Texas Instruments Incorporated 15 TLV320AIC3268EVM-U EVM Schematics www.ti.com TLV320AIC3268RGC EVALUATION BOARD STANDOFFS S03 S02 S05 S04 S07 S01 S06 DIGITAL INTERFACE CONNECTOR ANALOG INTERFACE CONNECTOR S08 mfg: JST p/n: 100P-JMDSS-G-1-TF(LF)(SN) BREAK-OUT CONNECTIONS BREAK-OUT CONNECTIONS BREAK-OUT CONNECTIONS mfg: JST p/n: 100P-JMDSS-G-1-TF(LF)(SN) J11 0.5in 0.5in 0.5in 0.5in 0.5in 0.5in 0.5in 0.5in 0.5in 0.5in 0.5in 0.5in 0.5in 0.5in 0.5in 0.5in GND CLASS-D SPEAKER OUTPUT LINE OUTPUTS HEADSET GROUND IN1+ AGND IN2+ AGND IN3+ AGND IN4+ AGND IN5+ AGND IN6+ AGND IN7+ AGND IN8+ AGND MICBIAS AGND SPK1+ SPK1SPK2+ SPK2OUT1+ OUT1GND OUT2+ OUT2GND OUT3+ OUT3GND OUT4+ OUT4GND AGND HPGND HPGND HPGND HPGND IN1L IN2L 2 3 4 5 6 IN2R 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 SPKP 37 38 SPKP SPKM 39 40 SPKM 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 HPL 65 66 HPR IN4L MICBIAS MICBIAS_EXT RECP LLOUT RLOUT 67 SPKVDD AV_ENABLE +1.8V_CP IN3R IN4R HS_MIC RECM 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 98 99 100 IN1AGND IN2AGND IN3AGND IN4AGND IN5AGND IN6AGND IN7AGND IN8AGND MICDET AGND SPK1+ SPK1SPK2+ SPK2OUT1OUT1GND OUT2OUT2GND OUT3OUT3GND OUT4OUT4GND AGND HP1L HP1R HP2L HP2R +5VD DGND +3.3IO DGND +1.8VD DGND VARVD DGND DV_ENABLE +3.3VD +1.8V VARVD DV_ENABLE RESERVED DGND MCLK CLASS-D SPEAKER OUTPUT DGND LINE OUTPUTS GND HEADSET OUTPUTS SPKGND RESERVED +3.3VD HPGND HPVDD RESERVED AGND VARVA AGND +1.8VA AGND +3.3VA AGND +5VA GPIO J12 BREAK-OUT CONNECTIONS +5V 1 2 3 4 5 6 +5VD DGND +3.0IO DGND +1.8IO DGND VARVD DGND +3.3VD +1.8V 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 TAS_SCL 27 28 TAS_SDA 29 30 MCLK 31 32 BCLK1 33 34 WCLK1 35 36 DIN1 37 38 DOUT1 39 40 TAS_MISO 41 42 43 44 TAS_SSz 45 46 TAS_SCLK 47 48 I2S_ENABLE 49 50 RESETz 51 52 53 54 55 56 57 58 BCLK2 59 60 WCLK2 61 62 DIN2 63 64 DOUT2 65 66 67 68 69 70 71 72 BCLK2 73 74 WCLK2 VARVD RESERVED I2C MCLK I2S1 TAS_MOSI SPI I2S_ENABLE RESET DGND GND I2S_2 RESERVED 75 76 DIN2 77 78 DOUT2 79 80 81 82 83 84 85 86 TAS_BCLK 87 88 TAS_WCLK GPIO1 89 90 TAS_DIN GPIO2 91 92 TAS_DOUT GPIO3 93 94 GPIO4 95 GPIO5 97 98 99 100 SPKVDD 96 97 GND TI IN1R 7 IN3L SPKGND HPGND HPVDD AV_ENABLE AGND VARVA AGND +1.8V_CP AGND +3.3VA AGND +5VA +5V 1 I2S_3 RESERVED I2S_4 96 RESERVED GND J12 J11 Anchor Anchor GND GND BREAKOUT BOARD CONNECTIONS PAGE INFO: DESIGN LEAD JOHN FEDAK IV DATE JANUARY 31, 2014 FILENAME AIP013C_Schematic.sbk C SCH REV C PCB REV SHEET 9 OF 11 L;DN DRAWN BY Figure 13. Breakout Board Connections 16 TLV320AIC3268EVM-U Evaluation Module SLAU564A – February 2014 – Revised February 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated TLV320AIC3268EVM-U EVM Board Layout www.ti.com 7 TLV320AIC3268EVM-U EVM Board Layout Figure 14 through Figure 16 illustrate the TLV320AIC3268EVM-U EVM board layouts. Figure 14. Top Xray View Figure 15. Silkscreen Top SLAU564A – February 2014 – Revised February 2014 Submit Documentation Feedback TLV320AIC3268EVM-U Evaluation Module Copyright © 2014, Texas Instruments Incorporated 17 TLV320AIC3268EVM-U EVM Board Layout www.ti.com Figure 16. Silkscreen Bottom 18 TLV320AIC3268EVM-U Evaluation Module SLAU564A – February 2014 – Revised February 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated TLV320AIC3268EVM-U Bill of Materials www.ti.com 8 TLV320AIC3268EVM-U Bill of Materials Table 3 contains the BOM for the TLV320AIC3268EVM-U. Table 3. TLV320AIC3268EVM-U Bill of Materials Item MANU PART NUM MFG QTY REF DESIGNATORS DESCRIPTION 1 TLV320AIC3268IRGC TEXAS INSTRUMENTS 1 U1 STEREO AUDIO CODEC WITH DIRECT PATH HEADPHONE AND CLASS-D 2 TAS1020BPFB TEXAS INSTRUMENTS 1 U2 USB STREAMING CONTROLLER TQFP48-PFB ROHS 3 SN74LVC1G126DBVR TEXAS INSTRUMENTS 2 U3, U28 SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT SOT23-DBV5 ROHS 4 SN74CBTLV3253DBQR TEXAS INSTRUMENTS 4 U4, U19, U20, U21 LO VOLT DUAL 1OF4 FET MUX/DEMUX SSOP16-DB ROHS 5 24FC512-I/MF MICROCHIP 1 U5 512K I2C SERIAL EEPROM DFN8-MF ROHS 6 SRC4392IPFBR BURR-BROWN 2 U6, U10 2 CHAN,ASYNC,SAMPLE RATE CONV W/DIG AUDIO REC/XMTR ROHS 7 SN74LVC2G04DBVR TEXAS INSTRUMENTS 1 U7 DUAL INVERTER GATE SOT23-DBV6 ROHS 8 TXS0104EPWR TEXAS INSTRUMENTS 4 U8, U9, U13, U14 4-BIT BIDIR LEVEL TRANSLATOR TSSOP14-PW ROHS 9 SN74LVC2G157DCTR TEXAS INSTRUMENTS 2 U11, U24, MUX/DATA SELECTOR 2 TO 1 SSOP8-DCT ROHS 10 SN74AVC2T245RSWR TEXAS INSTRUMENTS 2 U12, U25 2BIT XCVR CONFIGURABLE TRANSLATION 3-STATE OUTS QFN10-RSW ROHS 11 SN74LVC2G17DBVR TEXAS INSTRUMENTS 2 U15, U16 DUAL SCHMITT-TRIGGER BUFFER SOT23-DBV6 ROHS 12 ICS542MLFT IDT 2 U17, U18 CLOCK DIVIDER,SOP8-D,ROHS 13 TCA9539PWR TEXAS INSTRUMENTS 1 U22 REMOTE 16B I2C SMBUS LO PWR IO EXPNDR INT OUT TSSOP24-PW ROHS 14 TXB0102DCUR TEXAS INSTRUMENTS 1 U23 2-BIT BIDIR LEVEL TRANSLATOR VSSOP8-DCU ROHS 15 PCA9306DCTR TEXAS INSTRUMENTS 1 U26 DUAL BIDIR I2C BUS AND SMBUS VOLT LEVEL TRANS SSOP8-DCT ROHS 16 TXB0101DBVR TEXAS INSTRUMENTS 1 U27 1-BIT BIDIR LEVEL TRANSLATOR SOT23-DBV6 ROHS 17 TPS73618DBVT TEXAS INSTRUMENTS 4 VR1, VR2, VR3, VR4 VOLT REG 1.8V 400MA LDO CAP FREE NMOS SOT23-DBV5 ROHS 18 TPS73633DBVT TEXAS INSTRUMENTS 2 VR5, VR6 VOLT REG 3.3V 400MA LDO CAP FREE NMOS SOT23-DBV5 ROHS 19 PLR135/T10 EVERLIGHT ELECTRONICS 2 SPDIF-IN1, SPDIF-IN2 PHOTOLINK FIBER OPTIC RECEIVER 2.4-5.5V 15MB PCB-RA SHUTTER ROHS 20 PLT133/T10W EVERLIGHT ELECTRONICS 2 SPDIF-OUT1, SPDIF-OUT2 PHOTOLINK FIBER OPTIC TRANSMITTER 2.4-5.5V 15MB PCB-RA SHUTTER ROHS 21 SML-LXT0805YW-TR LUMEX OPTO 2 LED1, LED2 LED, YELLOW 2.0V SMD0805 ROHS 22 SML-LXT0805GW-TR LUMEX OPTO 5 LED3, LED4, LED5, LED6, LED7 LED, GREEN 2.0V SMD0805 ROHS 23 FXO-HC736R-22.5792 FOX ELECTRONICS 1 OSC1 OSCILLATOR SMT 3.3V 24.576MHz ROHS 24 625L3C024M57600 CTS FREQUENCY CONTROLS 1 OSC2 OSCILLATOR SMT 3.3V 22.5792MHz ROHS 25 625L3I006M00000 CTS FREQUENCY CONTROLS 1 Y1 OSCILLATOR SMT 6.0MHz 3.3V OUT-ENABLE ROHS 26 GRM1885C1H470JA01D MURATA 2 C1, C2 CAP SMD0603 CERM 47PFD 50V 5% COG ROHS 27 C1608X7R1C105K TDK 3 C3, C123, C124 CAP SMD0603 CERM 1.0UFD 16V 10% X7R ROHS 28 GRM155R71C104KA88D MURATA 77 C4, C5, C6, C7, C8, C10, C12, C13, C17, C18, C20, C22, C23, C25, C26, C27, C28, C29, C30, C32, C34, C35, C37, C38, C39, C40, C43, C44, C45, C46, C47, C48, C49, C50, C51, C52, C53, C54, C56, C58, C60, C62, C64, C72, C73, C74, C75, C76, C77, C79, C80, C83, C87, C88, C90, C91, C97, C99, C102, C112, C113, C115, C117, C119, C120, C129, C130, C131, C132, C133, C134, C135, C136, C137, C138, C139, C140 CAP SMD0402 CERM 0.1UFD 16V X7R 10% ROHS 29 C1608X7R1H104K TDK 3 C9, C11, C16 CAP SMD0603 CERM 0.1UFD 50V 10% X7R ROHS 30 C1608C0G1H102J TDK CORP. 1 C14 CAP SMD0603 CERM 1000PFD 50V 5% COG ROHS 31 GRM1885C1H101JA01D MURATA 1 C15 CAP SMD0603 CERM 100PFD 50V 5% COG ROHS 32 GRM188R60J106ME47D MURATA 14 C19, C21, C24, C31, C33, C36, C41, C42, C55, C57, C59, C61, C63, C65 CAP SMD0603 CERM 10UFD 6.3V 20% X5R ROHS 33 JMK212BJ476MG-T TAIYO YUDEN 6 C66, C67, C68, C69, C70, C71 CAP SMD0805 CERM 47UFD 6.3V 20% X5R ROHS SLAU564A – February 2014 – Revised February 2014 Submit Documentation Feedback TLV320AIC3268EVM-U Evaluation Module Copyright © 2014, Texas Instruments Incorporated 19 TLV320AIC3268EVM-U Bill of Materials www.ti.com Table 3. TLV320AIC3268EVM-U Bill of Materials (continued) Item MANU PART NUM MFG QTY REF DESIGNATORS DESCRIPTION 34 GRM188R71C104KA01D MURATA 2 C78, C105 CAP SMD0603 CERM 0.1UFD 16V 10% X7R ROHS 35 EMK107B7105KA-T TAIYO YUDEN 6 C81, C96, C98, C110, C114, C116 CAP SMD0603 CERM 1.0UFD 16V 10% X7R ROHS 36 GRM21BR71A106KE51L MURATA 5 C84, C103, C104, C111, C118 CAP SMD0805 CERM 10UFD 10V10% X7R ROHS 37 GRM188R71A105KA61D MURATA 9 C85, C86, C89, C92, C93, C94, C95, CP90, CP91 CAP SMD0603 CERM 1.0UFD 10V 10% X7R ROHS 38 GRM188R71A225KE15D MURATA 2 C100, C101 CAP SMD0603 CERM 2.2UFD 10V 10% X7R ROHS 39 NA NA 0 C106, C107 CAP SMD1206 VALUE TBD 40 GRM188R71H222KA01D MURATA 8 C108, C109, C121, C122, C125, C126, C127, C128 CAP SMD0603 CERM 2200PFD 50V 10% X7R ROHS 41 ERJ-3EKF1501V PANASONIC 1 R1 RESISTOR SMD0603 1.50K OHM 1% THICK FILM 1/10W ROHS 42 ERJ-3EKF27R4V PANASONIC 2 R2, R3 RESISTOR SMD0603 27.4 OHMS 1% 1/10W ROHS 43 ERJ-3EKF1003V PANASONIC 1 R4 RESISTOR SMD0603 100K OHM 1% THICK FILM 1/10W ROHS 44 ERJ-3GEYJ103V PANASONIC 34 R5, R6, R7, R10, R12, R15, R18, R21, R25, R29, R34, R35, R36, R37, R38, R39, R40, R41, R42, R43, R44, R45, R46, R47, R48, R49, R50, R51, R52, R55, R83, R84, R87, R88 RESISTOR SMD0603 10K 5% 1/10W ROHS 45 RC0603FR-07649RL YAGEO 2 R8, R9 RESISTOR SMD0603 THICK FILM 649 OHMS 1% 1/10W ROHS 46 ERJ-3EKF3091V PANASONIC 1 R11 RESISTOR SMD0603 3.09K OHM 1% THICK FILM 1/10W ROHS 47 ERJ-3GEYJ272V PANASONIC 4 R13, R14, R79, R80 RESISTOR SMD0603 2.7K OHMS 5% 1/10W ROHS 48 ERJ-3GEYJ472V PANASONIC 4 R16, R17, R24, R26 RESISTOR SMD0603 4.7K OHMS 5% 1/10W ROHS 49 ERJ-3GEY0R00V PANASONIC 6 R19, R20, R22, R23, R53, R54 RESISTOR,SMT,0603,ZERO OHM,5%,,1/10W,ROHS 50 RC0603FR-071KL YAGEO 13 R27, R28, R62, R66, R67, R68, R69, R74, R75, R76, R77, R86, R89 RESISTOR SMD0603 THICK FILM 1.00K OHM 1% 1/10W ROHS 51 ERJ-3EKF3570V PANASONIC 5 R30, R31, R32, R33, R85 RESISTOR SMD0603 357 OHM 1% THICK FILM 1/10W ROHS 52 CRCW0603200RFKEA VISHAY 3 R56, R57, R65 RESISTOR SMD0603 200 OHMS 1% 1/10W ROHS 53 ERJ-3EKF1000V PANASONIC 2 R58, R61 RESISTOR SMD0603 100 1% THICK FILM 1/10W ROHS 54 ERJ-3EKF2101V PANASONIC 3 R59, R63, R64 RESISTOR SMD0603 2.10K OHMS 1% THICK FILM 1/10W ROHS 55 ERJ-3EKF1101V PANASONIC 1 R60 RESISTOR SMD0603 1.10K OHMS 1% THICK FILM 1/10W ROHS 56 CRCW120616R0JNEA VISHAY 2 R70, R90 RESISTOR,SMT,1206,16.0 OHM,5%,1/4W,ROHS 57 RC1206FR-0732R4L YAGEO 3 R71, R72, R78 RESISTOR SMD1206 32.4 OHMS 1% 1/4W ROHS 58 ERJ-3GEY0R00V PANASONIC 0 R73 RESISTOR,SMT,0603,ZERO OHM,5%,,1/10W,ROHS 59 ERJ-3GEYJ204V PANASONIC 1 R81 RESISTOR SMD0603 200K OHMS 5% 1/10W ROHS 60 ERJ-2RKF8063X PANASONIC 1 R82 RESISTOR SMD0402 THICK FILM 806K OHMS 1/10W 1% ROHS 61 BLM15EG121SN1D MURATA 2 FB1, FB2 FERRITE BEAD SMD0402 120 OHMS 1.5A ROHS 62 MPZ1608S221A TDK 4 FB3, FB4, FB5, FB6 FERRITE CHIP, 220 OHMS 2A 100MHZ SMD 0603 ROHS 63 ZX62WD1-B-5PC HIROSE 1 J1 JACK USB FEMALE TYPEB MICRO SMT-RA 5PIN ROHS 64 75869-131LF FCI 0 J2 HEADER SHROUDED 100LS MALE GOLD 2x3 PINS ROHS 65 5607-4200-SH 3M 0 J3 CONNECTOR-SATA 7 PIN SMT-RA SERIES 5607 ROHS 66 SJ-43516-SMT CUI STACK 3 J4, J7, J10 JACK AUDIO-STEREO MINI(3.5MM ,4-COND SMT-RA ROHS 67 ED555/2DS ON SHORE TECHNOLOGY 2 J5, J6 TERMINAL BLOCK 2PIN 6A/125V GRAY 3.5mm PITCH 16-28AWG ROHS 68 SJ-435105 CUI STACK 1 J8 JACK AUDIO MINI(3.5MM ,4-COND SMT-RA ROHS 69 ED555/3DS ON SHORE TECHNOLOGY 1 J9 TERMINAL BLOCK 3PIN 6A/125V GRAY 3.5mm PITCH 16-28AWG ROHS 70 100P-JMDSS-G-1TF(LF)(SN) JST 2 J11, J12 PLUG SMD 2x50 FEMALE JMDSERIES 0.5MM LS GOLD ROHS 20 TLV320AIC3268EVM-U Evaluation Module SLAU564A – February 2014 – Revised February 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated TLV320AIC3268EVM-U Bill of Materials www.ti.com Table 3. TLV320AIC3268EVM-U Bill of Materials (continued) Item MANU PART NUM MFG QTY REF DESIGNATORS DESCRIPTION 71 PBC02SAAN SULLINS 28 JP1, JP2, JP3, JP24, JP25, JP26, JP27, JP28, JP29, JP30, JP31, JP32, JP35, JP36, JP39, JP41, JP42, JP43, JP45, JP46, JP48, JP49, JP54, JP55, JP56, JP57, JP58, JP59 HEADER THRU MALE 2 PIN 100LS 120 TAIL GOLD ROHS 72 PBC03SAAN SULLINS 31 JP4, JP5, JP6, JP7, JP8, JP9, JP10, JP11, JP12, JP13, JP14, JP15, JP16, JP17, JP18, JP19, JP20, JP21, JP22, JP23, JP33, JP34, JP37, JP38, JP40, JP44, JP47, JP50, JP51, JP52, JP53 HEADER THRU MALE 3 PIN 100LS 120 TAIL GOLD ROHS 73 WM-63PRT PANASONIC 1 MIC1 MICROPHONE ELECTRET OMNIDIRECTIONAL DUAL BAND 2PIN ROHS 74 SPM0423HD4H-WB KNOWLES 4 MIC2, MIC3, MIC4, MIC5 MIC DIGITAL MIMI-SISONIC HALOGEN FREE 6PIN ROHS 75 5000 KEYSTONE ELECTRONICS 11 TP1, TP2, TP3, TP4, TP5, TP21, TP30, TP35, TP36, TP37, TP69 PC TESTPOINT, RED, ROHS 76 5002 KEYSTONE ELECTRONICS 30 TP22, TP23, TP24, TP25, TP26, TP27, TP28, TP29, TP31, TP32, TP33, TP34, TP38, TP39, TP40, TP41, TP42, TP43, TP44, TP45, TP46, TP47, TP48, TP49, TP50, TP51, TP52, TP53, TP54, TP61 PC TESTPOINT, WHITE, ROHS 77 5004 KEYSTONE ELECTRONICS 21 TP6, TP7, TP8, TP9, TP10, TP11, TP12, TP13, TP14, TP15, TP16, TP17, TP18, TP19, TP20, TP55, TP56, TP57, TP58, TP59, TP60 PC TESTPOINT, YELLOW, ROHS 78 5011 KEYSTONE ELECTRONICS 7 TP62, TP63, TP64, TP65, TP66, TP67, TP68 PC TESTPOINT BLACK 063 HOLE ROHS 79 TL1015AF160QG E-SWITCH 4 S1, S2, S3, S4 SWITCH, MOM, 160G SMT 4X3MM ROHS 80 3480 KEYSTONE ELECTRONICS 8 STANDOFFS STANDOFF 4-40 0.5IN 0.220 DIA ALUM RND F-F ROHS 81 4862 KEYSTONE ELECTRONICS 8 STANDOFF SCREWS MACHINE SCREW 4-40 PHILIPS 0.25 LENGTH ROHS 82 INTLWSS 004 KEYSTONE ELECTRONICS 8 STANDOFF WASHERS WASHER INTERNAL TOOTH #4 STAINLESS STEEL ROHS 83 969102-0000-DA 3M 38 JP1, JP2, JP4, JP5, JP6, JP7, JP8, JP17, JP18, JP19, JP22, JP23, JP24, JP25, JP26, JP29, JP30, JP31, JP32, JP33, JP34, JP35, JP36, JP37, JP38, JP39, JP40, JP41, JP44, JP45, JP46, JP47, JP48, JP49, JP50, JP51, JP52, JP53 SHUNT BLACK AU FLASH 0.100LS OPEN TOP ROHS TOTAL 491 SPECIAL NOTES TO THIS BILL OF MATERIALS SN1 These assemblies are ESD sensitive, ESD precautions shall be observed. SN2 These assemblies must be clean and free from flux and all contaminants. Use of no clean flux is not acceptable. SN3 These assemblies must comply with workmanship standards IPC-A-610 Class 2. SN4 Ref designators marked with an asterisk ('**') cannot be substituted. All other components can be substituted with equivalent MFG's components. SLAU564A – February 2014 – Revised February 2014 Submit Documentation Feedback TLV320AIC3268EVM-U Evaluation Module Copyright © 2014, Texas Instruments Incorporated 21 Writing Scripts 9 www.ti.com Writing Scripts A script is simply a text file that contains data to send to the serial control buses. Each line in a script file is one command. No provision is made for extending lines beyond one line, except for the > command. A line is terminated by a carriage return. The first character of a line is the command. Commands are: I— Set interface bus to use r— Read from the serial control bus w— Write to the serial control bus >— Extend repeated write commands to lines below a w #— Comment b— Break d— Delay f— Wait for Flag The first command, I, sets the interface to use for the commands to follow. This command must be followed by one of the following parameters: i2cstd— Standard mode I2C bus i2cfast— Fast mode I2C bus spi8— SPI bus with 8-bit register addressing spi16— SPI bus with 16-bit register addressing For example, if a fast mode I2C bus is to be used, the script begins with: I i2cfast— A double-quoted string of characters following the b command can be added to provide information to the user about each breakpoint. When the script is executed, the software's command handler halts as soon as a breakpoint is detected and displays the string of characters within the double quotes. The Wait for Flag command, f, reads a specified register and verifies if the bitmap provided with the command matches the data being read. If the data does not match, the command handler retries for up to 200 times. This feature is useful when switching buffers in parts that support the adaptive filtering mode. The command f syntax follows: f [i2c address] [register] [D7][D6][D5][D4][D3][D2][D1][D0] where 'i2c address' and 'register' are in hexadecimal format and 'D7' through 'D0' are in binary format with values of 0, 1 or X for don't care.8 Anything following a comment command # is ignored by the parser, provided that it is on the same line. The delay command d allows the user to specify a time, in milliseconds, that the script pauses before proceeding. Note: The delay time is entered in decimal format. A series of byte values follows either a read or write command. Each byte value is expressed in hexadecimal, and each byte must be separated by a space. Commands are interpreted and sent to the TAS1020B by the program. 22 TLV320AIC3268EVM-U Evaluation Module SLAU564A – February 2014 – Revised February 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Writing Scripts www.ti.com The first byte following an r (read) or w (write) command is the I2C slave address of the device (if I2C is used) or the first data byte to write. (If SPI is used, note that SPI interfaces are not standardized on protocols, so the meaning of this byte varies with the device being addressed on the SPI bus.) The second byte is the starting register address that data will be written to (again, with I2C; SPI varies). Following these two bytes are data, if writing; if reading, the third byte value is the number of bytes to read, (expressed in hexadecimal). For example, to write the values 0xAA 0x55 to an I2C device with a slave address of 0x30, starting at a register address of 0x03, the user writes: #example script I i2cfast w 30 03 AA 55 r 30 03 02e This script begins with a comment, specifies that a fast I2C bus is used, then writes 0xAA 0x55 to the I2C slave device at address 0x30, writing the values into registers 0x03 and 0x04. The script then reads back two bytes from the same device starting at register address 0x03. Note that the slave device value does not change. It is unnecessary to set the R/W bit for I2C devices in the script; the read or write commands does that. If extensive repeated write commands are sent and commenting is desired for a group of bytes, the > command can be used to extend the bytes to other lines that follow. A usage example for the > command follows: #example script for '>' command I i2cfast # Write AA and BB to registers 3 and 4, respectively w 30 03 AA BB # Write CC, DD, EE and FF to registers 5, 6, 7 and 8, respectively > CC DD EE FF # Place a commented breakpoint b "AA BB CC DD EE FF was written, starting at register 3" # Read back all six registers, starting at register 3 r 30 03 06b The following example demonstrates usage of the Wait for Flag command, f: #example script for 'wait for flag' command I i2cfast # Switch to Page 44 w 30 00 2C # Switch buffer w 30 01 05 # Wait for bit D0 to clear. 'x' denotes a don't care. f 30 01 xxxxxxx0 Any text editor can be used to write these scripts; jEdit is an editor that is highly recommended for general usage. For more information, go to: www.jedit.org. SLAU564A – February 2014 – Revised February 2014 Submit Documentation Feedback TLV320AIC3268EVM-U Evaluation Module Copyright © 2014, Texas Instruments Incorporated 23 Writing Scripts www.ti.com Once the script is written, it can be used in the command window by running the program, and then selecting Open Script File... from the File menu. Locate the script and open it. The script then is displayed in the command buffer. The user also can edit the script once it is in the buffer and save it by selecting Save Script File... from the File menu. Once the script is in the command buffer, it can be executed by pressing the Execute Command Buffer button. If breakpoints are in the script, the script executes to that point, and the user is presented with a dialog box with a button to press to continue executing the script. When ready to proceed, the user pushes that button and the script continues. 24 TLV320AIC3268EVM-U Evaluation Module SLAU564A – February 2014 – Revised February 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Revision History www.ti.com Revision History Changes from Original (February 2014) to A Revision .................................................................................................. Page • • Deleted link to the Application Reference Guide from the Related Documents table. .......................................... 1 Deleted section titled Operation. ....................................................................................................... 4 NOTE: Page numbers for previous revisions may differ from page numbers in the current version. SLAU564A – February 2014 – Revised February 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Revision History 25 STANDARD TERMS AND CONDITIONS FOR EVALUATION MODULES 1. Delivery: TI delivers TI evaluation boards, kits, or modules, including any accompanying demonstration software, components, or documentation (collectively, an “EVM” or “EVMs”) to the User (“User”) in accordance with the terms and conditions set forth herein. Acceptance of the EVM is expressly subject to the following terms and conditions. 1.1 EVMs are intended solely for product or software developers for use in a research and development setting to facilitate feasibility evaluation, experimentation, or scientific analysis of TI semiconductors products. EVMs have no direct function and are not finished products. EVMs shall not be directly or indirectly assembled as a part or subassembly in any finished product. For clarification, any software or software tools provided with the EVM (“Software”) shall not be subject to the terms and conditions set forth herein but rather shall be subject to the applicable terms and conditions that accompany such Software 1.2 EVMs are not intended for consumer or household use. EVMs may not be sold, sublicensed, leased, rented, loaned, assigned, or otherwise distributed for commercial purposes by Users, in whole or in part, or used in any finished product or production system. 2 Limited Warranty and Related Remedies/Disclaimers: 2.1 These terms and conditions do not apply to Software. The warranty, if any, for Software is covered in the applicable Software License Agreement. 2.2 TI warrants that the TI EVM will conform to TI's published specifications for ninety (90) days after the date TI delivers such EVM to User. Notwithstanding the foregoing, TI shall not be liable for any defects that are caused by neglect, misuse or mistreatment by an entity other than TI, including improper installation or testing, or for any EVMs that have been altered or modified in any way by an entity other than TI. Moreover, TI shall not be liable for any defects that result from User's design, specifications or instructions for such EVMs. Testing and other quality control techniques are used to the extent TI deems necessary or as mandated by government requirements. TI does not test all parameters of each EVM. 2.3 If any EVM fails to conform to the warranty set forth above, TI's sole liability shall be at its option to repair or replace such EVM, or credit User's account for such EVM. TI's liability under this warranty shall be limited to EVMs that are returned during the warranty period to the address designated by TI and that are determined by TI not to conform to such warranty. If TI elects to repair or replace such EVM, TI shall have a reasonable time to repair such EVM or provide replacements. Repaired EVMs shall be warranted for the remainder of the original warranty period. Replaced EVMs shall be warranted for a new full ninety (90) day warranty period. 3 Regulatory Notices: 3.1 United States 3.1.1 Notice applicable to EVMs not FCC-Approved: This kit is designed to allow product developers to evaluate electronic components, circuitry, or software associated with the kit to determine whether to incorporate such items in a finished product and software developers to write software applications for use with the end product. This kit is not a finished product and when assembled may not be resold or otherwise marketed unless all required FCC equipment authorizations are first obtained. Operation is subject to the condition that this product not cause harmful interference to licensed radio stations and that this product accept harmful interference. Unless the assembled kit is designed to operate under part 15, part 18 or part 95 of this chapter, the operator of the kit must operate under the authority of an FCC license holder or must secure an experimental authorization under part 5 of this chapter. 3.1.2 For EVMs annotated as FCC – FEDERAL COMMUNICATIONS COMMISSION Part 15 Compliant: CAUTION This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate the equipment. FCC Interference Statement for Class A EVM devices NOTE: This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial environment. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the instruction manual, may cause harmful interference to radio communications. Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to correct the interference at his own expense. SPACER SPACER SPACER SPACER SPACER SPACER SPACER SPACER FCC Interference Statement for Class B EVM devices NOTE: This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures: • • • • Reorient or relocate the receiving antenna. Increase the separation between the equipment and receiver. Connect the equipment into an outlet on a circuit different from that to which the receiver is connected. Consult the dealer or an experienced radio/TV technician for help. 3.2 Canada 3.2.1 For EVMs issued with an Industry Canada Certificate of Conformance to RSS-210 Concerning EVMs Including Radio Transmitters: This device complies with Industry Canada license-exempt RSS standard(s). Operation is subject to the following two conditions: (1) this device may not cause interference, and (2) this device must accept any interference, including interference that may cause undesired operation of the device. Concernant les EVMs avec appareils radio: Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation est autorisée aux deux conditions suivantes: (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit accepter tout brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement. Concerning EVMs Including Detachable Antennas: Under Industry Canada regulations, this radio transmitter may only operate using an antenna of a type and maximum (or lesser) gain approved for the transmitter by Industry Canada. To reduce potential radio interference to other users, the antenna type and its gain should be so chosen that the equivalent isotropically radiated power (e.i.r.p.) is not more than that necessary for successful communication. This radio transmitter has been approved by Industry Canada to operate with the antenna types listed in the user guide with the maximum permissible gain and required antenna impedance for each antenna type indicated. Antenna types not included in this list, having a gain greater than the maximum gain indicated for that type, are strictly prohibited for use with this device. Concernant les EVMs avec antennes détachables Conformément à la réglementation d'Industrie Canada, le présent émetteur radio peut fonctionner avec une antenne d'un type et d'un gain maximal (ou inférieur) approuvé pour l'émetteur par Industrie Canada. Dans le but de réduire les risques de brouillage radioélectrique à l'intention des autres utilisateurs, il faut choisir le type d'antenne et son gain de sorte que la puissance isotrope rayonnée équivalente (p.i.r.e.) ne dépasse pas l'intensité nécessaire à l'établissement d'une communication satisfaisante. Le présent émetteur radio a été approuvé par Industrie Canada pour fonctionner avec les types d'antenne énumérés dans le manuel d’usage et ayant un gain admissible maximal et l'impédance requise pour chaque type d'antenne. Les types d'antenne non inclus dans cette liste, ou dont le gain est supérieur au gain maximal indiqué, sont strictement interdits pour l'exploitation de l'émetteur 3.3 Japan 3.3.1 Notice for EVMs delivered in Japan: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page 日本国内に 輸入される評価用キット、ボードについては、次のところをご覧ください。 http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page 3.3.2 Notice for Users of EVMs Considered “Radio Frequency Products” in Japan: EVMs entering Japan may not be certified by TI as conforming to Technical Regulations of Radio Law of Japan. If User uses EVMs in Japan, not certified to Technical Regulations of Radio Law of Japan, User is required by Radio Law of Japan to follow the instructions below with respect to EVMs: 1. 2. 3. Use EVMs in a shielded room or any other test facility as defined in the notification #173 issued by Ministry of Internal Affairs and Communications on March 28, 2006, based on Sub-section 1.1 of Article 6 of the Ministry’s Rule for Enforcement of Radio Law of Japan, Use EVMs only after User obtains the license of Test Radio Station as provided in Radio Law of Japan with respect to EVMs, or Use of EVMs only after User obtains the Technical Regulations Conformity Certification as provided in Radio Law of Japan with respect to EVMs. Also, do not transfer EVMs, unless User gives the same notice above to the transferee. Please note that if User does not follow the instructions above, User will be subject to penalties of Radio Law of Japan. SPACER SPACER SPACER SPACER SPACER 【無線電波を送信する製品の開発キットをお使いになる際の注意事項】 開発キットの中には技術基準適合証明を受けて いないものがあります。 技術適合証明を受けていないもののご使用に際しては、電波法遵守のため、以下のいずれかの 措置を取っていただく必要がありますのでご注意ください。 1. 2. 3. 電波法施行規則第6条第1項第1号に基づく平成18年3月28日総務省告示第173号で定められた電波暗室等の試験設備でご使用 いただく。 実験局の免許を取得後ご使用いただく。 技術基準適合証明を取得後ご使用いただく。 なお、本製品は、上記の「ご使用にあたっての注意」を譲渡先、移転先に通知しない限り、譲渡、移転できないものとします。 上記を遵守頂けない場合は、電波法の罰則が適用される可能性があることをご留意ください。 日本テキサス・イ ンスツルメンツ株式会社 東京都新宿区西新宿６丁目２４番１号 西新宿三井ビル 3.3.3 Notice for EVMs for Power Line Communication: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page 電力線搬送波通信についての開発キットをお使いになる際の注意事項については、次のところをご覧くださ い。http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page SPACER 4 EVM Use Restrictions and Warnings: 4.1 EVMS ARE NOT FOR USE IN FUNCTIONAL SAFETY AND/OR SAFETY CRITICAL EVALUATIONS, INCLUDING BUT NOT LIMITED TO EVALUATIONS OF LIFE SUPPORT APPLICATIONS. 4.2 User must read and apply the user guide and other available documentation provided by TI regarding the EVM prior to handling or using the EVM, including without limitation any warning or restriction notices. The notices contain important safety information related to, for example, temperatures and voltages. 4.3 Safety-Related Warnings and Restrictions: 4.3.1 User shall operate the EVM within TI’s recommended specifications and environmental considerations stated in the user guide, other available documentation provided by TI, and any other applicable requirements and employ reasonable and customary safeguards. Exceeding the specified performance ratings and specifications (including but not limited to input and output voltage, current, power, and environmental ranges) for the EVM may cause personal injury or death, or property damage. If there are questions concerning performance ratings and specifications, User should contact a TI field representative prior to connecting interface electronics including input power and intended loads. Any loads applied outside of the specified output range may also result in unintended and/or inaccurate operation and/or possible permanent damage to the EVM and/or interface electronics. Please consult the EVM user guide prior to connecting any load to the EVM output. If there is uncertainty as to the load specification, please contact a TI field representative. During normal operation, even with the inputs and outputs kept within the specified allowable ranges, some circuit components may have elevated case temperatures. These components include but are not limited to linear regulators, switching transistors, pass transistors, current sense resistors, and heat sinks, which can be identified using the information in the associated documentation. When working with the EVM, please be aware that the EVM may become very warm. 4.3.2 EVMs are intended solely for use by technically qualified, professional electronics experts who are familiar with the dangers and application risks associated with handling electrical mechanical components, systems, and subsystems. User assumes all responsibility and liability for proper and safe handling and use of the EVM by User or its employees, affiliates, contractors or designees. User assumes all responsibility and liability to ensure that any interfaces (electronic and/or mechanical) between the EVM and any human body are designed with suitable isolation and means to safely limit accessible leakage currents to minimize the risk of electrical shock hazard. User assumes all responsibility and liability for any improper or unsafe handling or use of the EVM by User or its employees, affiliates, contractors or designees. 4.4 User assumes all responsibility and liability to determine whether the EVM is subject to any applicable international, federal, state, or local laws and regulations related to User’s handling and use of the EVM and, if applicable, User assumes all responsibility and liability for compliance in all respects with such laws and regulations. User assumes all responsibility and liability for proper disposal and recycling of the EVM consistent with all applicable international, federal, state, and local requirements. 5. Accuracy of Information: To the extent TI provides information on the availability and function of EVMs, TI attempts to be as accurate as possible. However, TI does not warrant the accuracy of EVM descriptions, EVM availability or other information on its websites as accurate, complete, reliable, current, or error-free. SPACER SPACER SPACER SPACER SPACER SPACER SPACER 6. Disclaimers: 6.1 EXCEPT AS SET FORTH ABOVE, EVMS AND ANY WRITTEN DESIGN MATERIALS PROVIDED WITH THE EVM (AND THE DESIGN OF THE EVM ITSELF) ARE PROVIDED "AS IS" AND "WITH ALL FAULTS." TI DISCLAIMS ALL OTHER WARRANTIES, EXPRESS OR IMPLIED, REGARDING SUCH ITEMS, INCLUDING BUT NOT LIMITED TO ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF ANY THIRD PARTY PATENTS, COPYRIGHTS, TRADE SECRETS OR OTHER INTELLECTUAL PROPERTY RIGHTS. 6.2 EXCEPT FOR THE LIMITED RIGHT TO USE THE EVM SET FORTH HEREIN, NOTHING IN THESE TERMS AND CONDITIONS SHALL BE CONSTRUED AS GRANTING OR CONFERRING ANY RIGHTS BY LICENSE, PATENT, OR ANY OTHER INDUSTRIAL OR INTELLECTUAL PROPERTY RIGHT OF TI, ITS SUPPLIERS/LICENSORS OR ANY OTHER THIRD PARTY, TO USE THE EVM IN ANY FINISHED END-USER OR READY-TO-USE FINAL PRODUCT, OR FOR ANY INVENTION, DISCOVERY OR IMPROVEMENT MADE, CONCEIVED OR ACQUIRED PRIOR TO OR AFTER DELIVERY OF THE EVM. 7. USER'S INDEMNITY OBLIGATIONS AND REPRESENTATIONS. USER WILL DEFEND, INDEMNIFY AND HOLD TI, ITS LICENSORS AND THEIR REPRESENTATIVES HARMLESS FROM AND AGAINST ANY AND ALL CLAIMS, DAMAGES, LOSSES, EXPENSES, COSTS AND LIABILITIES (COLLECTIVELY, "CLAIMS") ARISING OUT OF OR IN CONNECTION WITH ANY HANDLING OR USE OF THE EVM THAT IS NOT IN ACCORDANCE WITH THESE TERMS AND CONDITIONS. THIS OBLIGATION SHALL APPLY WHETHER CLAIMS ARISE UNDER STATUTE, REGULATION, OR THE LAW OF TORT, CONTRACT OR ANY OTHER LEGAL THEORY, AND EVEN IF THE EVM FAILS TO PERFORM AS DESCRIBED OR EXPECTED. 8. Limitations on Damages and Liability: 8.1 General Limitations. IN NO EVENT SHALL TI BE LIABLE FOR ANY SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL, OR EXEMPLARY DAMAGES IN CONNECTION WITH OR ARISING OUT OF THESE TERMS ANDCONDITIONS OR THE USE OF THE EVMS PROVIDED HEREUNDER, REGARDLESS OF WHETHER TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED TO, COST OF REMOVAL OR REINSTALLATION, ANCILLARY COSTS TO THE PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES, RETESTING, OUTSIDE COMPUTER TIME, LABOR COSTS, LOSS OF GOODWILL, LOSS OF PROFITS, LOSS OF SAVINGS, LOSS OF USE, LOSS OF DATA, OR BUSINESS INTERRUPTION. NO CLAIM, SUIT OR ACTION SHALL BE BROUGHT AGAINST TI MORE THAN ONE YEAR AFTER THE RELATED CAUSE OF ACTION HAS OCCURRED. 8.2 Specific Limitations. IN NO EVENT SHALL TI'S AGGREGATE LIABILITY FROM ANY WARRANTY OR OTHER OBLIGATION ARISING OUT OF OR IN CONNECTION WITH THESE TERMS AND CONDITIONS, OR ANY USE OF ANY TI EVM PROVIDED HEREUNDER, EXCEED THE TOTAL AMOUNT PAID TO TI FOR THE PARTICULAR UNITS SOLD UNDER THESE TERMS AND CONDITIONS WITH RESPECT TO WHICH LOSSES OR DAMAGES ARE CLAIMED. THE EXISTENCE OF MORE THAN ONE CLAIM AGAINST THE PARTICULAR UNITS SOLD TO USER UNDER THESE TERMS AND CONDITIONS SHALL NOT ENLARGE OR EXTEND THIS LIMIT. 9. Return Policy. Except as otherwise provided, TI does not offer any refunds, returns, or exchanges. Furthermore, no return of EVM(s) will be accepted if the package has been opened and no return of the EVM(s) will be accepted if they are damaged or otherwise not in a resalable condition. If User feels it has been incorrectly charged for the EVM(s) it ordered or that delivery violates the applicable order, User should contact TI. All refunds will be made in full within thirty (30) working days from the return of the components(s), excluding any postage or packaging costs. 10. Governing Law: These terms and conditions shall be governed by and interpreted in accordance with the laws of the State of Texas, without reference to conflict-of-laws principles. User agrees that non-exclusive jurisdiction for any dispute arising out of or relating to these terms and conditions lies within courts located in the State of Texas and consents to venue in Dallas County, Texas. Notwithstanding the foregoing, any judgment may be enforced in any United States or foreign court, and TI may seek injunctive relief in any United States or foreign court. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2015, Texas Instruments Incorporated spacer IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. 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