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TLV3502-Q1
SBOS507A – FEBRUARY 2010 – REVISED DECEMBER 2014
TLV3502-Q1, 4.5-ns Rail-to-Rail High-Speed Comparator
1 Features
2 Applications
•
•
•
1
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: –40°C to
+125°C Ambient Operating Temperature
Range
– Device HBM ESD Classification Level 2
– Device CDM ESD Classification Level C4B
High Speed: 4.5 ns
Rail-To-Rail I/O
Supply Voltage: 2.7 V To 5.5 V
Push-Pull CMOS Output Stage
Shutdown
Micro Package: SOT23-8
Low Supply Current: 3.2 mA
HEV/EV, Powertrain, and Passive Safety:
– Threshold Detector
– Zero-Crossing Detector
– Window Comparator
– Oscillator
3 Description
The TLV3502-Q1 push-pull output comparators
feature a fast 4.5-ns propagation delay and operation
from 2.7 V to 5.5 V. Beyond-the-rails input commonmode range makes the device an ideal choice for
low-voltage applications. The rail-to-rail output directly
drives either CMOS or TTL logic.
A microsize package provides options for portable
and space-restricted applications. The TLV3502-Q1
device is available in the SOT23-8 (DCN) package.
Device Information(1)
PART NUMBER
TLV3502-Q1
PACKAGE
SOT-23 (8)
BODY SIZE (NOM)
2.90 mm × 1.60 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Propagation Delay vs Overdrive Voltage
9
VCM = 1 V
VS = 5 V
CLOAD = 17 pF
Propagation Delay (ns)
8
Rise
7
6
Fall
5
4
3
0
20
40
60
80
100
Overdrive Voltage (mV)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLV3502-Q1
SBOS507A – FEBRUARY 2010 – REVISED DECEMBER 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
4
5
5
6
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information .................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 9
7.1 Overview ................................................................... 9
7.2 Functional Block Diagram ......................................... 9
7.3 Feature Description................................................... 9
7.4 Device Functional Modes........................................ 11
8
Application and Implementation ........................ 12
8.1 Application Information............................................ 12
8.2 Typical Application ................................................. 12
9 Power Supply Recommendations...................... 13
10 Layout................................................................... 13
10.1 Layout Guidelines ................................................. 13
10.2 Layout Example .................................................... 14
11 Device and Documentation Support ................. 16
11.1 Trademarks ........................................................... 16
11.2 Electrostatic Discharge Caution ............................ 16
11.3 Glossary ................................................................ 16
12 Mechanical, Packaging, and Orderable
Information ........................................................... 16
4 Revision History
Changes from Original (February 2010) to Revision A
Page
•
Deleted references to the TLV3501 device and changed the TLV3502 device name to TLV3502-Q1 ................................ 1
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 4
2
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5 Pin Configuration and Functions
8-Pin SOT-23
DCN Package
(Top View)
+IN A
1
8
V+
7
OUT A
6
OUT B
5
V−
A
−IN A
2
+IN B
3
B
−IN B
4
Pin Functions
PIN
TYPE
DESCRIPTION
NO.
NAME
1
+IN A
I
Non inverting input, channel A
2
–IN A
I
Inverting input, channel A
3
+IN B
I
Non inverting input, channel B
4
–IN B
I
Inverting input, channel B
5
V–
Supply
6
OUT B
O
Output, channel B
7
OUT A
O
Output, channel A
8
V+
Supply
Negative (lowest) power supply
Positive (highest) power supply
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
Supply voltage
Signal input terminal voltage
(2)
(V−) − 0.3
MAX
UNIT
5.5
V
(V+) + 0.3
V
Signal input terminal current (2)
10
mA
Output short-circuit current (3)
74
mA
Thermal impedance, junction to free air
200
200
°C/W
Operating temperature
−40
125
°C
150
°C
150
°C
Junction temperature
−65
Storage temperature, Tstg
(1)
(2)
(3)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.3 V beyond the supply rails should
be current limited to 10mA or less.
Short circuit to ground, one comparator per package
6.2 ESD Ratings
VALUE
Human body model (HBM), per AEC Q100-002 (1)
V(ESD)
(1)
Electrostatic discharge
Charged device model (CDM), per AEC
Q100-011
UNIT
±2000
Corner pins (+IN A, –IN B, V+, and
V–)
±750
Other pins
±500
V
AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VS
Supply voltage
VIL
Low-level input voltage, shutdown (comparator is enabled) (1)
VIH
High-level input voltage, shutdown (comparator is disabled)
TA
Operating temperature
(1)
(1)
MIN
NOM
MAX
2.2
2.7
5.5
UNIT
V
(V+) 1.7
V
125
°C
(V+) – 0.9
–40
V
When the shutdown pin is within 0.9 V of the most positive supply, the part is disabled. When it is more than 1.7 V below the most
positive supply, the part is enabled.
6.4 Thermal Information
TLV3502-Q1
THERMAL METRIC (1)
SOT-23
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
43.9
RθJB
Junction-to-board thermal resistance
120.3
ψJT
Junction-to-top characterization parameter
14.4
ψJB
Junction-to-board characterization parameter
118.6
(1)
4
191.6
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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6.5 Electrical Characteristics
TA = 25°C and VS = 2.7 V to 5.5 V (unless otherwise noted)
PARAMETER
(1)
TEST CONDITIONS
MIN
TYP
MAX
±6.5
VOS
Input offset voltage
VCM = 0 V, IO = 0 mA
±1
ΔVOS/ΔT
Offset voltage vs temperature
TA = –40°C to 125°C
±5
PSRR
Offset voltage vs power supply
VS = 2.7 V to 5.5 V
mV
µV/°C
100
Input hysteresis
UNIT
400
µV/V
6
mV
IB
Input bias current
VCM = VCC/2, ΔVIN = ±5.5 V
±2
±10
pA
IOS
Input offset current (2)
VCM = VCC/2, ΔVIN = ±5.5 V
±2
±10
pA
VCM
Common-mode voltage range
(V+) + 0.2
V
CMRR
Common-mode rejection
(V–) - 0.2
VCM = –0.2 V to (V+) + 0.2 V
57
TA = −40°C to 125°C
VCM = –0.2 V to (V+) + 0.2 V
55
70
dB
1013 || 2
Common-mode input impedance
13
Differential input impedance
10
Ω || pF
Ω || pF
|| 4
VOH
High-level voltage output from rail
IOUT = ±1 mA
30
50
mV
VOL
Low-level voltage output from rail
IOUT = ±1 mA
30
50
mV
VS = 5 V, VO = High
3.2
5
mA
Input bias current of shutdown pin
IQ
Quiescent current per comparator
IQ(SD)
Quiescent current in shutdown
(1)
(2)
2
pA
2
µA
VOS is defined as the average of the positive and the negative switching thresholds.
The difference between IB+ and IB−.
6.6 Switching Characteristics
TA = 25°C and VS = 2.7 V to 5.5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
ΔVIN = 100 mV, Overdrive = 20 mV
Propagation delay time (1) (2)
tpd
MIN
TYP
MAX
4.5
6.4
ns
7
ns
10
ns
12
ns
TA = −40°C to 125°C
ΔVIN = 100 mV, Overdrive = 20 mV
ΔVIN = 100 mV, Overdrive = 5 mV
7.5
TA = −40°C to 125°C
ΔVIN = 100 mV, Overdrive = 5 mV
UNIT
Δt(SKEW)
Propagation delay skew (3)
ΔVIN = 100 mV, Overdrive = 20 mV
fMAX
Maximum toggle frequency
Overdrive = 50 mV, VS = 5 V
tR
Rise time (4)
tF
Fall time (4)
1.5
ns
tOFF
Shutdown turn-off time
30
ns
tON
Shutdown turn-on time
100
ns
(1)
(2)
(3)
(4)
0.5
ns
80
MHz
1.5
ns
Propagation delay cannot be accurately measured with low overdrive on automatic test equipment. This parameter is ensured by
characterization at 100-mV overdrive.
Not production tested
The difference between the propagation delay going high and the propagation delay going low.
Measured between 10% of VS and 90% of VS.
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6.7 Typical Characteristics
Input
5
4
Output Voltage (V)
Input Voltage (V)
0
VOD = 50 mV
VOD = 100 mV
3
Output Voltage (V)
Input Voltage (V)
TA = 25°C, VS = 5 V, Input Overdrive = 100 mV (unless otherwise noted)
VOD = 20 mV
2
VOD = 5 mV
1
0
−1
−10
0
10
20
30
Input
0
VOD = 50 mV
5
4
VOD = 5 mV
2
1
0
−1
−10
40
VOD = 20 mV
VOD = 100 mV
3
0
10
20
30
40
Time (ns)
Time (ns)
Figure 1. Output Response for Various Overdrive Voltages
(rising)
Figure 2. Output Response for Various Overdrive Voltages
(falling)
5.0
5.0
Propagation Delay (ns)
Propagation Delay (ns)
Fall
4.5
Rise
4.0
3.5
4.5
4.0
Fall
3.5
Rise
3.0
−40 −25
0
25
50
75
100
3.0
−40 −25
125
0
25
Temperature ( °C )
VOD = 20 mV
75
100
125
VOD = 50 mV
Figure 3. Propagation Delay vs Temperature
Figure 4. Propagation Delay vs Temperature
9
9
8
8
Propagation Delay (ns)
Propagation Delay (ns)
50
Temperature ( °C )
7
6
Fall
5
Rise
7
6
5
Fall
4
4
3
3
Rise
0
20
40
60
80
100
0
20
VOD = 20 mV
60
80
100
VOD = 50 mV
Figure 5. Propagation Delay vs Capacitive Load
6
40
Capacitive Load (pF)
Capacitive Load (pF)
Figure 6. Propagation Delay vs Capacitive Load
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Typical Characteristics (continued)
TA = 25°C, VS = 5 V, Input Overdrive = 100 mV (unless otherwise noted)
9
WAKE−UP DELAY vs TEMPERATURE
110
Wake−Up Delay (ns)
Propagation Delay (ns)
8
7
6
5
Fall
90
70
4
Rise
3
2
3
4
5
50
−40 −25
6
0
25
Supply Voltage (V)
VDD = 5 V
Input Voltage (V)
Input Voltage (V)
100
125
Figure 8. Wake-Up Delay vs Temperature
10
0
−10
5
500
0
−500
2
Output Voltage (V)
4
Output Voltage (V)
75
VIN = 20 mVpp
Figure 7. Propagation Delay vs Supply Voltage
3
2
1
0
−1
0
20
40
60
80
1
0
−1
−2
0
100
2
4
6
8
VDD = 5 V
10
12
14
16
18
20
Time (ns)
Time (ns)
±2.5-V dual supply into 50-Ω oscilloscope input
VIN = 20 mVpp
Figure 10. Response to 100 MHz Sine Wave
Figure 9. Response to 50-MHz Sine Wave
4.0
4.0
3.8
3.8
3.6
3.6
Quiescent Current (mA)
Quiescent Current (mA)
50
Temperature (°C )
3.4
3.2
3.0
2.8
2.6
2.4
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.2
2.0
2.0
2
3
4
5
6
−40 −25
0
25
50
75
100
125
Temperature (°C )
Supply Voltage (V)
Figure 11. Quiescent Current vs Supply Voltage
Figure 12. Quiescent Current vs Temperature
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Typical Characteristics (continued)
TA = 25°C, VS = 5 V, Input Overdrive = 100 mV (unless otherwise noted)
25
3.5
CLOAD = 50 pF
Quiescent Current (mA)
Quiescent Current (mA)
3.0
2.5
2.0
5V
(from off to on)
2.7 V
(from off to on)
1.5
5V
(from on to off)
1.0
2.7 V
(from on to off)
0.5
20
CLOAD = 20 pF
15
10
CLOAD = 10 pF
5
CLOAD = 0.5 pF
0
0
0
1
2
3
4
5
0
20
Figure 13. Quiescent Current vs Shutdown Voltage
8
40
60
80
100
Frequency (MHz)
Shutdown Voltage (V)
Figure 14. Quiescent Current vs Frequency
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7 Detailed Description
7.1 Overview
The TLV3502-Q1 push-pull output comparator features a fast 4.5-ns propagation delay and operation from
2.7 V to 5.5 V. Beyond-the-rails input common-mode range makes it an ideal choice for low-voltage
applications. The rail-to-rail output directly drives either CMOS or TTL logic.
7.2 Functional Block Diagram
V+
+IN A
+
A
±IN A
OUT A
±
V±
V+
+IN B
+
B
±IN B
OUT B
±
V±
7.3 Feature Description
The TLV3502-Q1 device feature fast 4.5-ns propagation delay with a push-pull output. The device operates from
2.7 V to 5.5 V. It has beyond-the-rails input common-mode range and rail-to-rail output directly drives either
CMOS or TTL logic.
7.3.1 Input Over-Voltage Protection
Device inputs are protected by ESD diodes that will conduct if the input voltages exceed the power supplies by
more than approximately 300 mV. Momentary voltages greater than 300 mV beyond the power supply can be
tolerated if the input current is limited to 10 mA. This limiting is easily accomplished with a small input resistor in
series with the comparator, as shown in Figure 15.
VS
R
0.1 µF
2.2 µF
VIN
VOUT
Vref
Figure 15. Input Current Protection for Voltages Exceeding the Supply Voltage
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Feature Description (continued)
7.3.2 Relaxation Oscillator
The TLV350x can easily be configured as a simple and inexpensive relaxation oscillator. In Figure 16, the R2
network sets the trip threshold at 1/3 and 2/3 of the supply. Since this is a high-speed circuit, the resistor values
are rather low to minimize the effect of parasitic capacitance. The positive input alternates between 1/3 of V+ and
2/3 of V+ depending on whether the output is low or high. The time to charge (or discharge) is 0.69R1C.
Therefore, the period is 1.38R1C. For 62 pF and 1 kΩ as shown in Figure 16, the output is calculated to be
10.9MHz. An implementation of this circuit oscillated at 9.6 MHz. Parasitic capacitance and component
tolerances explain the difference between theory and actual performance.
VC
2/3 (V+)
t
1/3 (V+)
V+
C
62 pF
1.38R1C
VS = 5 V R1
1 kΩ
VOUT
R2
5 kΩ
R2
5 kΩ
t
f = 10 MHz
V+
R2
5 kΩ
Figure 16. Relaxation Oscillator
7.3.3 High-Speed Window Comparator
A window comparator circuit is used to determine when a signal is between two voltages. The TLV3502-Q1
device can readily be used to create a high-speed window comparator. VHI is the upper voltage threshold, and
VLO is the lower voltage threshold. When VIN is between these two thresholds, the output in Figure 17 is high.
Figure 18 shows a simple means of obtaining an active low output. Note that the reference levels are connected
differently between Figure 17 and Figure 18. The operating voltage range of either circuit is 2.7 V to 5.5 V.
10
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Feature Description (continued)
VHI
a
VIN
VOUT
SN74LVC1G02
b
VLO
V
VOUT
VIN
VHI
VLO
Time
Figure 17. Window Comparator—Active High
VLO
a
VIN
VOUT
SN74AHC00
b
VHI
V
VOUT
VIN
VHI
VLO
Time
Figure 18. Window Comparator—Active Low
7.4 Device Functional Modes
This device has no special operating modes outside of the normally powered dual comparator function.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TLV3502-Q1 device features high-speed response and includes 6 mV of internal hysteresis for improved
noise immunity with an input common-mode range that extends 0.2 V beyond the power-supply rails.
8.2 Typical Application
In this example, we will show how can we add external hysteresis to TLV3502-Q1 device to achieve greater
noise immunity. First, let's understand when and why external hysteresis may be required.
The TLV3502-Q1 device has a robust performance when used with a good layout. However, comparator inputs
have little noise immunity within the range of specified offset voltage (±5 mV). For slow moving or noisy input
signals, the comparator output may display multiple switching as input signals move through the switching
threshold. In such applications, the 6mV of internal hysteresis of the TLV3502-Q1 device might not be sufficient.
In cases where greater noise immunity is desired, external hysteresis may be added by connecting a small
amount of feedback to the positive input.
VS = 5 V
0.1 µF
2.2 µF
VIN
VOUT
R1 = 51 Ω
R2 = 10 kΩ
Vref
Figure 19. Application Adding Hysteresis to the TLV350x
8.2.1 Design Requirements
Figure 19 shows a typical topology used to introduce 25 mV of additional hysteresis, for a total of 31-mV
hysteresis when operating from a single 5-V supply.
8.2.2 Detailed Design Procedure
Use Equation 1 to calculate the total hysteresis.
(V + ) ´ R1
+ 6 mV
VHYST =
R1 + R2
(1)
VHYST sets the value of the transition voltage required to switch the comparator output by enlarging the threshold
region, thereby reducing sensitivity to noise.
12
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Typical Application (continued)
8.2.3 Application Curve
Input
Output
Figure 20. TLV3502 With Upper and Lower Threshold With 1-V Hysteresis
9 Power Supply Recommendations
The TLV3505-Q1 comparator is specified for use on a single supply from 2.7 V to 5.5 V (or a dual supply from
±1.35 V to ±2.75 V) over a temperature range of −40°C to 125°C. The device continues to function below this
range, but performance is not specified.
Place bypass capacitors close to the power supply pins to reduce noise coupling in from noisy or highimpedance power supplies. For more detailed information on bypass capacitor placement, see the Layout
Guidelines section.
10 Layout
10.1 Layout Guidelines
•
•
•
•
•
For any high-speed comparator or amplifier, proper design and printed circuit board (PCB) layout are
necessary for optimal performance. Excess stray capacitance on the active input, or improper grounding, can
limit the maximum performance of high-speed circuitry.
Minimizing resistance from the signal source to the comparator input is necessary in order to minimize the
propagation delay of the complete circuit. The source resistance along with input and stray capacitance
creates an RC filter that delays voltage transitions at the input, and reduces the amplitude of high-frequency
signals. The input capacitance of the TLV3502-Q1 device along with stray capacitance from an input pin to
ground results in several picofarads of capacitance.
The location and type of capacitors used for power-supply bypassing are critical to high-speed comparators.
The suggested 2.2-μF tantalum capacitor do not need to be as close to the device as the 0.1-μF capacitor,
and may be shared with other devices. The 2.2-μF capacitor buffers the power-supply line against ripple, and
the 0.1-μF capacitor provides a charge for the comparator during high frequency switching.
In a high-speed circuit, fast rising and falling switching transients create voltage differences across lines that
would be at the same potential at DC. To reduce this effect, a ground plane is often used to reduce difference
in voltage potential within the circuit board. A ground plane has the advantage of minimizing the effect of stray
capacitances on the circuit board by providing a more desirable path for the current to flow. With a signal
trace over a ground plane, at high-frequency the return current (in the ground plane) tends to flow right under
the signal trace. Breaks in the ground plane (as simple as through-hole leads and vias) increase the
inductance of the plane, making it less effective at higher frequencies. Breaks in the ground plane for
necessary vias should be spaced randomly.
Figure 21 shows an evaluation layout for the TLV3502-Q1 SOT23-8 package. The device is shown with SMA
connectors bringing signals on and off the board. RT1, RT2, RT3 and RT4 are termination resistors for + IN
A, + IN B, –IN A, and –IN B respectively. C1 and C2 are power-supply bypass capacitors. Place the 0.1-μF
capacitor closest to the comparator. The ground plane is not shown, but the pads that the resistors and
capacitors connect to are shown. Figure 22 shows a schematic of this circuit.
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10.2 Layout Example
+IN A
±IN A
OUT A
GND
C2
C1
RT1
GND
RT2
GND
RT3
GND
GND
RT4
OUT B
V+
+IN B
GND (V±)
±IN B
Figure 21. TLV3502-Q1 Sample Layout
14
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TLV3502-Q1
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SBOS507A – FEBRUARY 2010 – REVISED DECEMBER 2014
Layout Example (continued)
C1
100 nF
+IN A
V+
C2
2.2 µF
+
RT1
50
±IN A
A
OUT A
B
OUT B
RT2
50
+IN B
+
RT3
50
±IN B
RT4
50
Figure 22. Schematic for Figure 21
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Product Folder Links: TLV3502-Q1
15
TLV3502-Q1
SBOS507A – FEBRUARY 2010 – REVISED DECEMBER 2014
www.ti.com
11 Device and Documentation Support
11.1 Trademarks
All trademarks are the property of their respective owners.
11.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
16
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Product Folder Links: TLV3502-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TLV3502AQDCNRQ1
ACTIVE
SOT-23
DCN
8
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
3502
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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