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TLV3541, TLV3542, TLV3544
SBOS756 – OCTOBER 2016
TLV354x 200-MHz, Rail-to-Rail I/O,
CMOS Operational Amplifiers for Cost-Sensitive Systems
1 Features
•
1
•
•
•
•
•
•
•
•
•
•
Wide-Bandwidth Amplifier for Cost-Sensitive
Systems
Unity-Gain Bandwidth: 200 MHz
High Slew Rate: 150 V/μs
Low Noise: 7.5 nV/√Hz
Rail-to-Rail I/O
High Output Current: > 100 mA
Excellent Video Performance:
– Diff Gain: 0.02%, Diff Phase: 0.09°
– 0.1-dB Gain Flatness: 40 MHz
Low Input Bias Current: 3 pA
Quiescent Current: 5.2 mA
Thermal Shutdown
Supply Range: 2.5 V to 5.5 V
2 Applications
•
•
•
•
•
•
•
•
•
•
High-Resolution ADC Driver Amplifiers
IR Touch
Low-Voltage, High-Frequency Signal Processing
Video Processing
Base Transceiver Stations
Optical Networking, Tunable Lasers
Photodiode Transimpedance Amplifiers
Barcode Scanners
Fast Current-Sensing Amplifiers
Ultrasound Imaging
V+
3 Description
The TLV3541, TLV3542 and TLV3544 are single-,
dual-, and quad-channel, low-power (5.2-mA per
channel), high-speed, unity-gain stable, rail-to-rail
input/output operational amplifiers (op amps)
designed for video and other applications that require
wide bandwidth.
Consuming only 6.5 mA (maximum) of supply current,
these devices feature 200-MHz gain-bandwidth
product, 150-V/μs slew rate, and a low 7.5 nV/√Hz of
input noise at f = 1 MHz. The combination of high
bandwidth, high slew rate, and low noise make the
TLV354x family suitable for low voltage, high-speed
signal conditioning systems.
The TLV354x series of op amps are optimized for
operation on single or dual supplies as low as 2.5 V
(±1.25 V) and up to 5.5 V (±2.75 V). Common-mode
input range extends beyond the supplies. The output
swing is within 100 mV of the rails, and supports a
wide dynamic range.
The TLV354x devices are specified from –40°C to
+125°C. The TLV354x family can be used as a plugin replacement for many commercially available wide
bandwidth op amps.
Device Information(1)
PART NUMBER
TLV3541
TLV3542
TLV3544
PACKAGE
BODY SIZE (NOM)
SOIC (8)
3.91 mm × 4.90 mm
SOT-23 (5)
2.90 mm × 1.60 mm
SOIC (8)
3.91 mm × 4.90 mm
VSSOP (8)
3.00 mm × 3.00 mm
SOIC (14)
8.65 mm × 3.91 mm
TSSOP (14)
5.00 mm × 4.40 mm
-In
TLV3541
VOUT
+In
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
V-
Figure 1. Simplified Schematic
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLV3541, TLV3542, TLV3544
SBOS756 – OCTOBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
5
8
8.1 Application Information............................................ 19
8.2 Typical Application ................................................. 19
8.3 System Examples ................................................... 20
9
9.1 Input and ESD Protection ....................................... 21
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 5
Thermal Information: TLV3541 ................................. 6
Thermal Information: TLV3542 ................................. 6
Thermal Information: TLV3544 ................................. 6
Electrical Characteristics: VS = 2.7 V to 5.5 V SingleSupply ........................................................................ 7
6.8 Typical Characteristics .............................................. 9
10.1 Layout Guidelines ................................................. 22
10.2 Layout Example .................................................... 22
11 Device and Documentation Support ................. 23
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Detailed Description ............................................ 13
7.1
7.2
7.3
7.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Power Supply Recommendations...................... 21
10 Layout................................................................... 22
6.1
6.2
6.3
6.4
6.5
6.6
6.7
7
Application and Implementation ........................ 19
13
13
14
18
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
23
23
23
23
23
23
23
12 Mechanical, Packaging, and Orderable
Information ........................................................... 24
4 Revision History
2
DATE
REVISION
NOTES
October 2016
*
Initial release.
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SBOS756 – OCTOBER 2016
5 Pin Configuration and Functions
TLV3541: DBV Package
5-Pin SOT-23
Top View
OUT 1
5
TLV3541: D Package
8-Pin SOIC
Top View
V+
2
+IN
3
4
-IN
(1)
(1)
(1)
1
8
NC
-IN
2
7
V+
+IN
3
6
OUT
V-
4
5
NC
NC
V-
(1)
NC means no internal connection.
Pin Functions: TLV3541
PIN
NAME
DBV (SOT-23)
D (SOIC)
4
2
–IN
I/O
DESCRIPTION
I
Inverting input
Noninverting input
+IN
3
3
I
NC
—
1, 5, 8
—
No internal connection (can be left floating)
OUT
1
6
O
Output
V–
2
4
—
Negative (lowest) supply
V+
5
7
—
Positive (highest) supply
TLV3542: DGK and D Packages
8-Pin VSSOP, SOIC
Top View
OUT A
1
-IN A
2
8
V+
7
OUT B
6
-IN B
5
+IN B
A
+IN A
3
B
V-
4
Pin Functions: TLV3542
PIN
I/O
DESCRIPTION
NAME
NO.
–IN A
2
I
Inverting input, channel A
+IN A
3
I
Noninverting input, channel A
–IN B
6
I
Inverting input, channel B
+IN B
5
I
Noninverting input, channel B
OUT A
1
O
Output, channel A
OUT B
7
O
Output, channel B
V–
4
—
Negative (lowest) supply
V+
8
—
Positive (highest) supply
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TLV3544: D and PW Packages
14-Pin SOIC, TSSOP
Top View
OUT A
1
14
OUT D
-IN A
2
13
-IN D
+IN A
3
12
+IN D
V+
4
11
V-
+IN B
5
10
+IN C
A
B
D
C
-IN B
6
9
-IN C
OUT B
7
8
OUT C
Pin Functions: TLV3544
PIN
TLV3544
NAME
I/O
DESCRIPTION
D (SOIC)
PW
(TSSOP)
–IN A
2
2
I
Inverting input, channel A
–IN B
6
6
I
Inverting input, channel B
–IN C
9
9
I
Inverting input, channel C
–IN D
13
13
I
Inverting input, channel D
+IN A
3
3
I
Noninverting input, channel A
+IN B
5
5
I
Noninverting input, channel B
+IN C
10
10
I
Noninverting input, channel C
+IN D
12
12
I
Noninverting input, channel D
OUT A
1
1
O
Output, channel A
OUT B
7
7
O
Output, channel B
OUT C
8
8
O
Output, channel C
OUT D
14
14
O
Output, channel D
V–
11
11
—
Negative (lowest) supply
V+
4
4
—
Positive (highest) supply
4
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SBOS756 – OCTOBER 2016
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
Supply voltage, V+ to V−
Voltage
Signal input terminals
(2)
Signal input terminals (2)
Current
(2)
(3)
V
(V+) + 0.5
V
–10
10
mA
Continuous
Operating, TA
–55
150
°C
Junction, TJ
–65
150
°C
150
°C
Storage, Tstg
(1)
UNIT
7.5
(V–) – (0.5)
Output short circuit (3)
Temperature
MAX
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Input pins are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5 V beyond the supply rails must be
current limited to 10 mA or less.
Short-circuit to ground, one amplifier per package.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
1000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
250
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VS
NOM
MAX
UNIT
Supply voltage, V– to V+
2.5
5.5
V
Specified temperature range
–40
125
°C
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6.4 Thermal Information: TLV3541
TLV3541
THERMAL METRIC (1)
D (SOIC)
DBV (SOT-23)
8 PINS
5 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
123.8
216.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
68.7
84.3
°C/W
RθJB
Junction-to-board thermal resistance
64.5
43.1
°C/W
ψJT
Junction-to-top characterization parameter
23.0
3.8
°C/W
ψJB
Junction-to-board characterization parameter
64.0
42.3
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics (SPRA953).
6.5 Thermal Information: TLV3542
TLV3542
THERMAL METRIC (1)
D (SOIC)
DGK (VSSOP)
UNIT
8 PINS
8 PINS
RθJA
Junction-to-ambient thermal resistance
113.9
175.9
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
60.4
67.8
°C/W
RθJB
Junction-to-board thermal resistance
54.1
97.1
°C/W
ψJT
Junction-to-top characterization parameter
17.1
9.3
°C/W
ψJB
Junction-to-board characterization parameter
53.6
95.5
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics (SPRA953).
6.6 Thermal Information: TLV3544
TLV3544
THERMAL METRIC (1)
D (SOIC)
PW (TSSOP)
14 PINS
14 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
83.8
92.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
70.7
27.5
°C/W
RθJB
Junction-to-board thermal resistance
59.5
33.6
°C/W
ψJT
Junction-to-top characterization parameter
11.6
1.9
°C/W
ψJB
Junction-to-board characterization parameter
37.7
33.1
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
°C/W
(1)
6
For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics (SPRA953).
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6.7 Electrical Characteristics: VS = 2.7 V to 5.5 V Single-Supply
at TA = 25°C, RF = 0 Ω, RL = 1 kΩ, and connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
±2
±10
UNIT
OFFSET VOLTAGE
VOS
Input offset voltage
VS = 5 V, at TA = 25°C
dVOS/dT
Input offset voltage vs temperature
VS = 5 V, at TA = −40°C to +125°C
PSRR
Input offset voltage vs power supply
VS = 2.7 V to 5.5 V,
VCM = (VS / 2) − 0.55 V
±4.5
60
mV
μV/°C
70
dB
3
pA
±1
pA
INPUT BIAS CURRENT
IB
Input bias current
IOS
Input offset current
NOISE
en
Input voltage noise density
f = 1 MHz
7.5
nV/√Hz
in
Current noise density
f = 1 MHz
50
fA/√Hz
INPUT VOLTAGE RANGE
VCM
CMRR
(V−) − 0.1
Common-mode voltage range
Common-mode rejection ratio
(V+) + 0.1
V
VS = 5.5 V, –0.1 V < VCM < 3.5 V,
at TA = 25°C
66
80
dB
VS = 5.5 V, –0.1 V < VCM < 5.6 V,
at TA = 25°C
56
68
dB
INPUT IMPEDANCE
Differential
1013 || 2
Ω || pF
Common-mode
1013 || 2
Ω || pF
OPEN-LOOP GAIN
AOL
VS = 5 V, 0.3 V < VO < 4.7 V,
at TA = 25°C
Open-loop gain
92
108
dB
200
MHz
90
MHz
100
MHz
FREQUENCY RESPONSE
At G = +1, VO = 10 mV
RF = 25 Ω
f−3dB
Small-signal bandwidth
GBW
Gain-bandwidth product
G = +10
f0.1dB
Bandwidth for 0.1-dB gain flatness
At G = +2, VO = 10 mV
At G = +2, VO = 10 mV
SR
Slew rate
Rise-and-fall time
Settling time
Overload recovery time
40
MHz
VS = 5 V, G = +1, 4-V step
150
V / μs
VS = 5 V, G = +1, 2-V step
130
V / μs
At G = +1, VO = 200 mVPP,
10% to 90%
2
ns
At G = +1, VO = 2 VPP, 10% to 90%
11
ns
0.1%, VS = 5 V, G = +1,
2-V output step
30
ns
0.01%, VS = 5 V, G = +1,
2-V output step
60
ns
5
ns
VIN × Gain = VS
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Electrical Characteristics: VS = 2.7 V to 5.5 V Single-Supply (continued)
at TA = 25°C, RF = 0 Ω, RL = 1 kΩ, and connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
FREQUENCY RESPONSE, continued
Harmonic
distortion
Second
harmonic
At G = +1, f = 1 MHz, VO = 2 VPP,
RL = 200 Ω, VCM = 1.5 V
–75
dBc
Third harmonic
At G = +1, f = 1 MHz, VO = 2 VPP,
RL = 200 Ω, VCM = 1.5 V
–83
dBc
Differential gain error
NTSC, RL = 150 Ω
0.02%
Differential phase error
NTSC, RL = 150 Ω
0.09
°
TLV3542
Channel-tochannel crosstalk TLV3544
f = 5 MHz
–100
dB
–84
dB
Voltage output swing from rail
VS = 5 V, RL = 1 kΩ at TA = 25°C
Output current, single, dual,
quad (1) (2)
VS = 5 V
OUTPUT
IO
0.1
100
VS = 3 V
Closed-loop output impedance
RO
0.3
mA
50
f < 100 kHz
Open-loop output resistance
V
mA
0.05
Ω
35
Ω
POWER SUPPLY
VS
IQ
Specified voltage range
2.7
5.5
V
Operating voltage range
2.5
5.5
V
6.5
mA
–40
125
°C
–55
150
°C
–65
150
°C
Quiescent current (per amplifier)
At TA = 25°C, VS = 5 V,
IO = 0
5.2
TEMPERATURE RANGE
Specified range
Operating range
(3)
Storage range
THERMAL SHUTDOWN
(1)
(2)
(3)
8
Shutdown temperature
160
°C
Reset from shutdown
140
°C
See typical characteristic curves, Output Voltage Swing vs Output Current (Figure 14 and Figure 15).
Specified by design.
Operating in this temperature range will not damage the part. However, degraded performance may be observed.
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6.8 Typical Characteristics
at TA = 25°C, VS = 5 V, G = +1, RF = 0 Ω, RL = 1 kΩ, and connected to VS / 2, unless otherwise noted.
3
3
VO = 10 mVpp, RF = 604W
G = +1
0
Gain (dB)
G = +2
G = +5
-3
Normalized Gain (dB)
0
G = +10
-6
-9
-3
G = -1
-6
G = -5
G = -10
-12
-12
-15
100k
1M
10M
100M
1000M
Frequency (Hz)
RF = 604 Ω
-15
100k
1M
C004
10M
Frequency (Hz)
100M
1G
VO = 10 mVpp
Figure 3. Inverting Small-Signal Frequency Response
Output Voltage (40mV/div)
Output Voltage (500mV/div)
Figure 2. Noninverting Small-Signal Frequency Response
Time (20ns/div)
Time (20ns/div)
Figure 4. Noninverting Small-Signal Step Response
Figure 5. Noninverting Large-Signal Step Response
3
9
RL = 10 kŸ
6
0
CL = 100 pF
3
-3
RL = 1 kŸ
Gain (dB)
Gain (dB)
G = -2
-9
-6
RL = 100 Ÿ
-9
0
CL = 47 pF
-3
-6
CL = 5 pF
-9
-12
RL = 50 Ÿ
-15
100k
1M
10M
-12
100M
1000M
Frequency (Hz)
G = +1, RF = 0 Ω
VO = 10 mVpp
-15
100k
1M
CL = 0 pF
Figure 6. Frequency Response for Various RL
10M
100M
1000M
Frequency (Hz)
C004
G = +1, RS = 0 Ω
C004
VO = 10 mVpp
Figure 7. Frequency Response for Various CL
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Typical Characteristics (continued)
at TA = 25°C, VS = 5 V, G = +1, RF = 0 Ω, RL = 1 kΩ, and connected to VS / 2, unless otherwise noted.
160
9
For 0.1dB
Flatness
CL = 5.6 pF, RS = 0 Ÿ
6
120
3
100
0
Gain (dB)
RS (W)
140
80
60
VIN
RS
40
VO
TLV3541
CL
CL = 47 pF, RS = 140 Ÿ
-3
-6
CL = 100 pF, RS = 120 Ÿ
-9
1kW
20
-12
0
1
-15
100k
1k
10
100
Capacitive Load (pF)
1M
10M
100M
1000M
Frequency (Hz)
C004
G = +1, VO = 10
mVpp
Figure 8. Recommended RS vs Capacitive Load
Figure 9. Frequency Response vs Capacitive Load
100
180
160
Open-Loop Phase (degrees)
Open-Loop Gain (dB)
CMRR
CMRR, PSRR (dB)
80
PSRR+
60
PSRR40
20
140
120
Phase
100
80
60
40
Gain
20
0
-20
0
-40
10k
100k
1M
10M
Frequency (Hz)
100M
1G
10
Figure 10. Common-Mode Rejection Ratio and PowerSupply Rejection Ratio vs Frequency
100
1k
10k 100k
1M
Frequency (Hz)
10M
100M
1G
Figure 11. Open-Loop Gain and Phase
10k
0.8
Input Bias Current (pA)
dG/dP (%/degrees)
0.7
0.6
0.5
dP
0.4
0.3
0.2
0.1
100
10
dG
1
0
1
2
3
Number of 150W Loads
4
Figure 12. Composite Video Differential Gain and Phase
10
1k
-55
-35
-15
5
25
45
65
Temperature (°C)
85
105 125 135
Figure 13. Input Bias Current vs Temperature
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Typical Characteristics (continued)
at TA = 25°C, VS = 5 V, G = +1, RF = 0 Ω, RL = 1 kΩ, and connected to VS / 2, unless otherwise noted.
5
3
Output Voltage (V)
Output Voltage (V)
4
2
+25°C
+125°C
-55°C
1
3
+125°C
+25°C
-55°C
2
1
0
0
0
20
40
60
80
Output Current (mA)
100
0
120
Figure 14. Output Voltage Swing vs Output Current
for VS = 3 V
25
50
75
100
125
Output Current (mA)
150
175
200
Figure 15. Output Voltage Swing vs Output Current
for VS = 5 V
6
100
VS = 5.5V
10
Output Voltage (VPP)
Output Impedance (W)
5
1
0.1
Maximum Output
Voltage without
Slew RateInduced Distortion
4
3
VS = 2.7V
2
TLV3541
1
ZO
0
0.01
100k
1M
10M
Frequency (Hz)
100M
1
1G
Figure 16. Closed-Loop Output Impedance vs Frequency
10
Frequency (MHz)
100
Figure 17. Maximum Output Voltage vs Frequency
0.5
0.4
VO = 2VPP
0.2
Population
Output Error (%)
0.3
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
0
10
20
30
40
50
60
Time (ns)
70
80
90
Figure 18. Output Settling Time to 0.1%
100
-8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3
Offset Voltage (mV)
4 5 6
7 8
Figure 19. Offset Voltage Production Distribution
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Typical Characteristics (continued)
at TA = 25°C, VS = 5 V, G = +1, RF = 0 Ω, RL = 1 kΩ, and connected to VS / 2, unless otherwise noted.
Crosstalk, Input-Referred (dB)
0
-20
-40
TLV4354
-60
TLV2354
-80
-100
-120
100k
1M
10M
100M
1G
Frequency (Hz)
Figure 20. Channel-to-Channel Crosstalk
12
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7 Detailed Description
7.1 Overview
The TLV354x is a CMOS, rail-to-rail I/O, high-speed, voltage-feedback operational amplifier designed for video,
high-speed, and other applications. The device is available as a single, dual, or quad op amp.
The amplifier features a 100-MHz gain bandwidth and a 150-V/μs slew rate, but the amplifier is unity-gain stable
and operates as a +1-V/V voltage follower.
7.2 Functional Block Diagram
V+
Reference
Current
VIN+
VINVBIAS1
Class AB
Control
Circuitry
VO
VBIAS2
V(Ground)
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7.3 Feature Description
7.3.1 Operating Voltage
The TLV354x is specified over a power-supply range of 2.7 V to 5.5 V (±1.35 V to ±2.75 V). However, the supply
voltage may range from 2.5 V to 5.5 V (±1.25 V to ±2.75 V). Supply voltages higher than 7.5 V (absolute
maximum) can permanently damage the amplifier.
Parameters that vary over supply voltage or temperature are shown in the Typical Characteristics section.
7.3.2 Rail-to-Rail Input
The specified input common-mode voltage range of the TLV354x extends 100 mV beyond the supply rails. This
extended range is achieved with a complementary input stage: an N-channel input differential pair in parallel with
a P-channel differential pair, as shown in the Functional Block Diagram. The N-channel pair is active for input
voltages close to the positive rail, typically (V+) − 1.2 V to 100 mV above the positive supply, while the P-channel
pair is on for inputs from 100 mV below the negative supply to approximately (V+) − 1.2 V. There is a small
transition region, typically (V+) − 1.5 V to (V+) − 0.9 V, in which both pairs are on. This 600-mV transition region
can vary ±500 mV with process variation. Thus, the transition region ( with both input stages on) can range from
(V+) − 2.0 V to (V+) − 1.5 V on the low end, up to (V+) − 0.9 V to (V+) − 0.4 V on the high end.
A double-folded cascode adds the signal from the two input pairs and presents a differential signal to the class
AB output stage.
7.3.3 Rail-to-Rail Output
A class AB output stage with common-source transistors is used to achieve rail-to-rail output. For highimpedance loads (> 200 Ω), the output voltage swing is typically 100 mV from the supply rails. With 10-Ω loads,
a useful output swing can be achieved while maintaining high open-loop gain. See the typical characteristic
curves, Output Voltage Swing vs Output Current (Figure 14 and Figure 15).
7.3.4 Output Drive
The TLV354x output stage can supply a continuous output current of ±100 mA and yet provide approximately 2.7
V of output swing on a 5-V supply, as shown in Figure 21. For maximum reliability, it is not recommended to run
a continuous DC current in excess of ±100 mA. Refer to the typical characteristic curves, Output Voltage Swing
vs Output Current (Figure 14 and Figure 15). For supplying continuous output currents greater than ±100 mA, the
TLV354x may be operated in parallel, as shown in Figure 22.
R2
1kW
+
V1
5V
-
C1
50pF
1mF
R1
10kW
V+
TLV3541
+
R3
VIN 10kW
-
1V In = 100mA
Out, as Shown
VR4
1kW
RSHUNT
1W
Laser Diode
Figure 21. Laser Diode Driver
14
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Feature Description (continued)
The TLV354x provides peak currents up to 200 mA, which corresponds to the typical short-circuit current.
Therefore, an on-chip thermal shutdown circuit is provided to protect the TLV354x from dangerously high junction
temperatures. At 160°C, the protection circuit shuts down the amplifier. Normal operation resumes when the
junction temperature cools to below +140°C.
R2
10kW
C1
200pF
+5V
1mF
R1
100kW
R5
1W
TLV3542
R3
100kW
+
-
R6
1W
2V In = 200mA
Out, as Shown
RSHUNT
1W
TLV3542
R4
10kW
Laser Diode
Figure 22. Parallel Operation
7.3.5 Video
The TLV354x output stage is capable of driving standard back-terminated 75-Ω video cables, as shown in
Figure 23. By back-terminating a transmission line, the device does not exhibit a capacitive load to its driver. A
properly back-terminated 75-Ω cable does not appear as capacitance; the device presents a 150-Ω resistive load
to the TLV354x output.
+5V
Video
In
75W
75W
TLV3541
Video
Output
+2.5V
604W
604W
+2.5V
Figure 23. Single-Supply Video Line Driver
The TLV3542 can be used as an amplifier for RGB graphic signals, which have a voltage of zero at the video
black level, by offsetting and AC-coupling the signal. See Figure 24.
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Feature Description (continued)
604W
+3V
+
V+
Red
10nF
604W
75W
1/2
TLV3542
R1
(1)
1mF
Red
75W
R2
V+
Green
R1
(1)
R2
604W
75W
1/2
TLV3542
Green
75W
604W
604W
+3V
+
V+
Blue
(1)
1 mF
10nF
604W
R1
75W
TLV3541
Blue
75W
R2
(1)
Source video signal offsets 300 mV above ground to accommodate op amp swing−to−ground capability.
Figure 24. RGB Cable Driver
16
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Feature Description (continued)
7.3.6 Driving Analog-to-Digital Converters
The TLV354x series op amps offer 60 ns of settling time to 0.01%, making them a good choice for driving highand medium-speed sampling A/D converters and buffering reference circuits. The TLV354x series provide an
effective means of buffering the A/D converter input capacitance and resulting charge injection while providing
signal gain. For applications requiring high DC accuracy, TI recommends using the OPA350 series.
Figure 25 illustrates the TLV3541 driving an A/D converter. With the TLV3541 in an inverting configuration, a
capacitor across the feedback resistor can filter high-frequency noise in the signal.
+5 V
1 kW
10 kW
VIN
VREF
V+
ADS7816, ADS7861,
or ADS7864
12-Bit A/D Converter
+In
TLV3541
+2.5 V
-In
GND
VIN = 2.3 V to 2.7 V signal (2.5 V DC + 400 mVpp AC)
NOTE: A/D converter input = 0 V to VREF
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Figure 25. The TLV3541 in Inverting Configuration Driving the ADS7816
7.3.7 Capacitive Load and Stability
The TLV354x series op amps can drive a wide range of capacitive loads. However, all op amps under certain
conditions may become unstable. Op amp configuration, gain, and load value are just a few of the factors to
consider when determining stability. An op amp in unity-gain configuration is most susceptible to the effects of
capacitive loading. The capacitive load reacts with the device output resistance, along with any additional load
resistance, to create a pole in the small-signal response that degrades the phase margin. Refer to the typical
characteristic curve, Frequency Response for Various CL (Figure 7) for details.
The TLV354x topology enhances the ability to drive capacitive loads. In unity gain, these op amps perform well
with large capacitive loads. Refer to the typical characteristic curves, Recommended RS vs Capacitive Load
(Figure 8) and Frequency Response vs Capacitive Load (Figure 9) for details.
One method of improving capacitive load drive in the unity-gain configuration is to insert a 10-Ω to 20-Ω resistor
in series with the output, as shown in Figure 26. This configuration significantly reduces ringing with large
capacitive loads. See the typical characteristic curve, Frequency Response vs Capacitive Load (Figure 9).
However, if there is a resistive load in parallel with the capacitive load, RS creates a voltage divider. This voltage
division introduces a DC error at the output and slightly reduces output swing. This error may be insignificant. For
instance, with RL = 10 kΩ and RS = 20 Ω, there is an error of approximately 0.2% at the output.
V+
RS
VOUT
TLV3541
VIN
RL
CL
Figure 26. Series Resistor in Unity-Gain Configuration Improves Capacitive Load Drive
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Feature Description (continued)
7.3.8 Wideband Transimpedance Amplifier
Wide bandwidth, low input bias current, and low input voltage and current noise make the TLV354x a suitable
wideband photodiode transimpedance amplifier for low-voltage, single-supply applications. Low-voltage noise is
important because photodiode capacitance causes the effective noise gain of the circuit to increase at high
frequency.
The key elements to a transimpedance design, as shown in Figure 27, are the expected diode capacitance
(including the parasitic input common-mode and differential-mode input capacitance (2 + 2) pF for the TLV354x),
the desired transimpedance gain (RF), and the Gain-Bandwidth Product (GBW) for the TLV354x (100 MHz,
typical). With these three variables set, the feedback capacitor value (CF) may be set to control the frequency
response.
CF
< 1pF
(prevents gain peaking)
RF
10MW
+V
l
CD TLV3541
VOUT
Figure 27. Transimpedance Amplifier
To achieve a flat, second-order, Butterworth frequency response, the feedback pole must be set as shown in
Equation 1:
1 =
2pRFCF
GBP
4pRFCD
(1)
Typical surface-mount resistors have a parasitic capacitance of approximately 0.2 pF that must be deducted from
the calculated feedback capacitance value. Bandwidth is calculated by Equation 2:
f-3dB =
GBP Hz
2pRFCD
(2)
For even higher transimpedance bandwidth, the high-speed CMOS OPA355 (200-MHz GBW) or the OPA655
(400-MHz GBW) may be used.
7.4 Device Functional Modes
The TLV354x has dual functional modes and is operational when the power-supply voltage is greater than 2.5 V
(±1.25 V). The maximum power-supply voltage for the TLV354x is 5.5 V (±2.75 V). At +160°C, the protection
circuit shuts down the amplifier. Normal operation resumes when the junction temperature cools to below
+140°C.
18
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TLV354x are wide bandwidth, low-noise, rail-to-rail input and output amplifiers. These devices operate from
2.5 V to 5.5 V, are unity-gain stable, and suitable for a wide range of general-purpose applications The input
common-mode voltage range includes both rails, and allows the TLV354x device to be used in any single-supply
application. Rail-to-rail input and output swing significantly increases dynamic range, especially in low-supply
applications, and makes the device ideal for driving analog-to-digital converters (ADCs).
The TLV354x family of devices features a 200-MHz bandwidth and 150-V/μs slew rate with only 7.5 nV/√Hz of
broadband noise.
8.2 Typical Application
A typical application for an operational amplifier is an inverting amplifier, as shown in Figure 28. An inverting
amplifier takes a positive voltage on the input and outputs a signal inverted to the input, making a negative
voltage of the same magnitude. In the same manner, the amplifier makes negative input voltages positive on the
output. In addition, amplification can be added by selecting the input resistor RI and the feedback resistor RF.
RF
VSUP+
RI
VOUT
+
VIN
VSUP
Figure 28. Application Schematic
8.2.1 Design Requirements
The supply voltage must be chosen to be larger than the input voltage range and the desired output range. The
limits of the input common-mode range (VCM) and the output voltage swing to the rails (VO) must be considered.
For instance, this application scales a signal of ±0.5 V (1 V) to ±1.8 V (3.6 V). Setting the supply at ±2.5 V is
sufficient to accommodate this application.
8.2.2 Detailed Design Procedure
Determine the gain required by the inverting amplifier using Equation 3 and Equation 4:
VOUT
AV
VIN
AV
1.8
0.5
3.6
(3)
(4)
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Typical Application (continued)
When the desired gain is determined, select a value for RI or RF. Selecting a value in the kilo ohm range is
desirable for general-purpose applications because the amplifier circuit uses currents in the milliamp range. This
milliamp current range ensures the device does not draw too much current. The trade-off is that large resistors
(100s of kilo ohms) draw the smallest current but generate the highest noise. Small resistors (100s of ohms)
generate low noise but draw high current. This example uses 10 kΩ for RI, meaning 36 kΩ is used for RF. These
values are determined by Equation 5:
RF
AV
RI
(5)
8.2.3 Application Curve
2
Input
Output
1.5
Voltage (V)
1
0.5
0
-0.5
-1
-1.5
-2
Time
Figure 29. Inverting Amplifier Input and Output
8.3 System Examples
When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often required.
The simplest way to establish this limited bandwidth is to place an RC filter at the noninverting terminal of the
amplifier, as shown in Figure 30.
RG
RF
R1
VOUT
VIN
C1
f-3 dB =
(
RF
VOUT
= 1+
RG
VIN
((
1
1 + sR1C1
1
2pR1C1
(
Figure 30. Single-Pole, Low-Pass Filter
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System Examples (continued)
If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter can be used for this
task, as shown in Figure 31. For best results, the amplifier must have a bandwidth that is eight to ten times the
filter frequency bandwidth. Failure to follow this guideline can result in phase shift of the amplifier.
C1
R1
R1 = R2 = R
C1 = C2 = C
Q = Peaking factor
(Butterworth Q = 0.707)
R2
VIN
VOUT
C2
1
2pRC
f-3 dB =
RF
RF
RG =
RG
(
2-
1
Q
(
Figure 31. Two-Pole, Low-Pass, Sallen-Key Filter
9 Power Supply Recommendations
The TLV354x family is specified from 2.7 V to 5.5 V (±1.35 V to ±2.75 V), although the devices can operate from
2.5 V to 5.5 V (±1.25 V to ±2.75 V); many specifications apply from –40°C to +125°C. Typical Characteristics
presents parameters that can exhibit significant variance with regard to operating voltage or temperature.
CAUTION
Supply voltages larger than 7.5 V can permanently damage the device. (See the
Absolute Maximum Ratings table).
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or highimpedance power supplies. For more detailed information on bypass capacitor placement, see Layout
Guidelines.
9.1 Input and ESD Protection
The TLV354x family incorporates internal electrostatic discharge (ESD) protection circuits on all pins. In the case
of input and output pins, this protection primarily consists of current-steering diodes connected between the input
and power-supply pins. These ESD protection diodes also provide in-circuit, input overdrive protection, as long
as the current is limited to 10 mA, as stated in the Absolute Maximum Ratings table. Figure 32 shows how a
series input resistor can be added to the driven input to limit the input current. The added resistor contributes
thermal noise at the amplifier input, which must be kept to a minimum in noise-sensitive applications.
V+
IOVERLOAD
10-mA max
Device
VOUT
VIN
5 kW
Figure 32. Input Current Protection
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10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:
• Noise propagates into analog circuitry through the power pins of the circuit as a whole and the
operational amplifier. Use bypass capacitors to reduce the coupled noise by providing low-impedance
power sources local to the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for singlesupply applications.
• Separate grounding for analog and digital portions of the circuitry is one of the simplest and most
effective methods of noise suppression. One or more layers on multilayer PCBs are typically devoted to
ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to
physically separate digital and analog grounds, paying attention to the flow of the ground current.
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicularly is much
better than crossing in parallel with the noisy trace.
• Place the external components as close to the device as possible. Keep RF and RG close to the inverting
input to minimize parasitic capacitance, as shown in Figure 33.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly
reduce leakage currents from nearby traces that are at different potentials.
10.2 Layout Example
+
VIN
VOUT
RG
RF
(Schematic Representation)
Place components
Run the input traces close to the device and
to each other to reduce
as far away from
parasitic errors.
the supply lines
as possible.
VS+
RF
N/C
N/C
GND
±IN
V+
VIN
+IN
OUTPUT
V±
N/C
RG
Use a low-ESR,
ceramic bypass
capacitor.
GND
VS±
GND
Use a low-ESR, ceramic
bypass capacitor.
VOUT
Ground (GND) plane on another layer.
Figure 33. Operational Amplifier Board Layout for Noninverting Configuration
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
TI recommends using the following reference documents for the TLV354x device. All are available for download
at www.ti.com unless otherwise noted.
• Handbook of Operational Amplifier Applications (SBOA092).
• Analog Engineer's Pocket Reference (SLYW038).
11.2 Related Links
Table 1 lists quick access links. Categories include technical documents, support and community resources,
tools and software, and quick access to sample or buy.
Table 1. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TLV3541
Click here
Click here
Click here
Click here
Click here
TLV3542
Click here
Click here
Click here
Click here
Click here
TLV3544
Click here
Click here
Click here
Click here
Click here
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
24
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TLV3541IDBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
17MD
TLV3541IDBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
17MD
TLV3541IDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TL3541
TLV3542IDGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
18TE
TLV3542IDGKT
ACTIVE
VSSOP
DGK
8
250
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
18TE
TLV3542IDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TL3542
TLV3544IDR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TLV3544A
TLV3544IPWR
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TLV
3544
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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