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TLV170, TLV2170, TLV4170
SBOS782A – NOVEMBER 2016 – REVISED MAY 2018
TLVx170 36-V, Single-Supply, EMI-Hardened, Low-Power Operational Amplifiers for
Cost-Sensitive Systems
1 Features
3 Description
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The TLVx170 family of electromagnetic interference
(EMI)-hardened, 36-V, single-supply, low-noise
operational amplifiers (op amps) have a THD+N of
0.0002% at 1 kHz and can operate on supplies that
range from 2.7 V (±1.35 V) to 36 V (±18V). These
features, along with low noise and very high powersupply rejection ratio (PSRR), make the singlechannel TLV170, dual-channel TLV2170, and quadchannel TLV4170 suitable for use in microvolt-level
signal amplification. The TLVx170 family of devices
also gives good offset, drift, and bandwidth with low
quiescent current.
1
Supply Range: 2.7 V to 36 V, ±1.35 V to ±18 V
Low Noise: 22 nV/√Hz
EMI-Hardened with RFI-Filtered Inputs
Input Range Includes the Negative Supply
Unity-Gain Stable: 200-pF Capacitive Load
Rail-to-Rail Output
Gain Bandwidth: 1.2 MHz
Low Quiescent Current: 125 µA per Amplifier
High Common-Mode Rejection: 110 dB
Low Bias Current: 10 pA (typical)
2 Applications
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Currency Counters
AC-DC Converters
Tracking Amplifiers in Power Modules
Server Power Supplies
Inverters
Test Equipment
Battery-Powered Instruments
Transducer Amplifiers
Line Drivers or Line Receivers
Smallest Packaging for 36-V Operational
Amplifiers
Package Footprint Comparison (to Scale)
Unlike most op amps that are specified at only one
supply voltage, the TLVx170 family of op amps is
specified from 2.7 V to 36 V with the ability to swing
input signals beyond the supply rails without phase
reversal. The TLVx170 family is also unity-gain stable
with a 200-pF capacitive load with a 1.2-MHz
bandwidth and a 0.4-V/μs slew rate for use in currentto-voltage converters.
The device inputs can operate 100 mV below the
negative rail and within 2 V of the positive rail for
normal operation, and with full rail-to-rail input with
reduced performance. The TLVx170 devices are
specified from –40°C to +125°C.
Device Information(1)
PART NUMBER
TLV170
TLV2170
TLV4170
PACKAGE
BODY SIZE (NOM)
SOIC (8)
4.90 mm × 3.91 mm
SOT-23 (5)
2.90 mm × 1.60 mm
SOIC (8)
4.90 mm × 3.91 mm
VSSOP (8)
3.00 mm × 3.00 mm
SOIC (14)
8.65 mm × 3.91 mm
TSSOP (14)
5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Package Height Comparison (to Scale)
D (SO-8)
DBV (SOT23-5)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLV170, TLV2170, TLV4170
SBOS782A – NOVEMBER 2016 – REVISED MAY 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
7
1
1
1
2
4
7
Absolute Maximum Ratings ...................................... 7
ESD Ratings.............................................................. 7
Recommended Operating Conditions....................... 7
Thermal Information: TLV170 ................................... 8
Thermal Information: TLV2170 ................................. 8
Thermal Information: TLV4170 ................................. 8
Electrical Characteristics........................................... 9
Typical Characteristics: Table of Graphs ................ 10
Typical Characteristics ............................................ 11
Detailed Description ............................................ 16
7.1 Overview ................................................................. 16
7.2 Functional Block Diagram ...................................... 16
7.3 Feature Description................................................. 17
7.4 Device Functional Modes........................................ 20
8
Application and Implementation ........................ 21
8.1 Application Information............................................ 21
8.2 Typical Application .................................................. 21
9 Power Supply Recommendations...................... 23
10 Layout................................................................... 23
10.1 Layout Guidelines ................................................. 23
10.2 Layout Example .................................................... 24
11 Device and Documentation Support ................. 25
11.1
11.2
11.3
11.4
11.5
11.6
11.7
11.8
Device Support......................................................
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
25
26
26
26
26
26
26
26
12 Mechanical, Packaging, and Orderable
Information ........................................................... 26
4 Revision History
Changes from Original (November 2016) to Revision A
•
2
Page
Updated the Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application figure........................................... 18
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SBOS782A – NOVEMBER 2016 – REVISED MAY 2018
Table 1. Device Comparison
PART NUMBER
NO OF
CHANNELS
PACKAGE-LEAD
SOT23-5
D
VSSOP
(micro size)
TSSOP
—
TLV170
1
5
8
—
TLV2170
2
—
8
8
—
TLV4170
4
—
14
—
14
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TLV170, TLV2170, TLV4170
SBOS782A – NOVEMBER 2016 – REVISED MAY 2018
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5 Pin Configuration and Functions
TLV170: DBV Package
5-Pin SOT-23
Top View
V±
2
+IN
3
5
V+
±
1
+
OUT
TLV170: D Package
8-Pin SOIC
Top View
4
NC
1
±IN
2
+IN
3
V±
4
8
NC
±
7
V+
+
6
OUT
5
NC
±IN
Not to scale
Not to scale
Pin Functions: TLV170
PIN
NAME
TLV170
I/O
DESCRIPTION
SOT-23
D
–IN
4
2
I
Negative (inverting) input
+IN
3
3
I
Positive (noninverting) input
NC
(1)
—
1, 5, 8
—
No internal connection (can be left floating)
OUT
1
6
O
Output
V–
2
4
—
Negative (lowest) power supply
V+
5
7
—
Positive (highest) power supply
(1)
4
NC indicates no internal connection.
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SBOS782A – NOVEMBER 2016 – REVISED MAY 2018
TLV2170: D and DGK Packages
8-Pin SOIC and VSSOP
Top View
OUT A
1
8
V+
±IN A
2
7
OUT B
+IN A
3
6
±IN B
V±
4
5
+IN B
Not to scale
Pin Functions: TLV2170
PIN
TLV2170
NAME
I/O
DESCRIPTION
SOIC
VSSOP
(micro size)
–IN A
2
2
I
Inverting input, channel A
–IN B
6
6
I
Inverting input, channel B
+IN A
3
3
I
Noninverting input, channel A
+IN B
5
5
I
Noninverting input, channel B
OUT A
1
1
O
Output, channel A
OUT B
7
7
O
Output, channel B
V–
4
4
—
Negative (lowest) power supply
V+
8
8
—
Positive (highest) power supply
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SBOS782A – NOVEMBER 2016 – REVISED MAY 2018
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TLV4170: D and PW Packages
14-Pin SOIC and TSSOP
Top View
OUT A
1
14
OUT D
±IN A
2
13
±IN D
+IN A
3
12
+IN D
V+
4
11
V±
+IN B
5
10
+IN C
±IN B
6
9
±IN C
OUT B
7
8
OUT C
Not to scale
Pin Functions: TLV4170
PIN
I/O
DESCRIPTION
NAME
SOIC
TSSOP
–IN A
2
2
I
Inverting input, channel A
–IN B
6
6
I
Inverting input, channel B
–IN C
9
9
I
Inverting input, channel C
–IN D
13
13
I
Inverting input, channel D
+IN A
3
3
I
Noninverting input, channel A
+IN B
5
5
I
Noninverting input, channel B
+IN C
10
10
I
Noninverting input, channel C
+IN D
12
12
I
Noninverting input, channel D
OUT A
1
1
O
Output, channel A
OUT B
7
7
O
Output, channel B
OUT C
8
8
O
Output, channel C
OUT D
14
14
O
Output, channel D
V–
11
11
—
Negative (lowest) power supply
V+
4
4
—
Positive (highest) power supply
6
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SBOS782A – NOVEMBER 2016 – REVISED MAY 2018
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
Supply voltage, [(V+) – (V−)]
Voltage
Single-supply voltage
Signal input pin
Signal input pin
Current
Output short-circuit
Temperature
(2)
V
(V+) + 0.5
–10
10
mA
Continuous
–55
150
Junction, TJ
150
Storage, Tstg
(1)
40
(V−) − 0.5
(2)
Operating, TA
UNIT
40
–65
°C
150
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Short-circuit to ground, one amplifier per package.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±4000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±750
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
Voltage
Supply, VS = (V+) – (V–)
2.7
36
V
TA
Specified temperature
–40
125
°C
TA
Operating temperature
–55
150
°C
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UNIT
7
TLV170, TLV2170, TLV4170
SBOS782A – NOVEMBER 2016 – REVISED MAY 2018
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6.4 Thermal Information: TLV170
TLV170
THERMAL METRIC (1)
D (SOIC)
DBV (SOT-23)
8 PINS
5 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
149.5
245.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
97.9
133.9
°C/W
RθJB
Junction-to-board thermal resistance
87.7
83.6
°C/W
ψJT
Junction-to-top characterization parameter
35.5
18.2
°C/W
ψJB
Junction-to-board characterization parameter
89.5
83.1
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
—
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Thermal Information: TLV2170
TLV2170
THERMAL METRIC (1)
D (SOIC)
DGK (VSSOP)
8 PINS
8 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
134.3
180
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
72.1
55
°C/W
RθJB
Junction-to-board thermal resistance
60.6
130
°C/W
ψJT
Junction-to-top characterization parameter
18.2
5.3
°C/W
ψJB
Junction-to-board characterization parameter
53.8
120
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
—
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.6 Thermal Information: TLV4170
TLV4170
THERMAL METRIC
(1)
D (SOIC)
PW (TSSOP)
14 PINS
14 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
93.2
106.9
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
51.8
24.4
°C/W
RθJB
Junction-to-board thermal resistance
49.4
59.3
°C/W
ψJT
Junction-to-top characterization parameter
13.5
0.6
°C/W
ψJB
Junction-to-board characterization parameter
42.2
54.3
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
—
°C/W
(1)
8
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SBOS782A – NOVEMBER 2016 – REVISED MAY 2018
6.7 Electrical Characteristics
at TA = 25°C, VCM = VOUT = VS / 2, and RL = 10 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
0.5
±2.5
UNIT
OFFSET VOLTAGE
TA = 25°C
VOS
Input offset voltage
dVOS/dT
Input offset voltage drift
TA = –40°C to +125°C
PSRR
Power-supply rejection ratio
VS = 4 V to 36 V, TA = –40°C to +125°C
TA = –40°C to +125°C
mV
±2.7
±2
90
Channel separation, dc
µV/°C
105
dB
5
µV/V
INPUT BIAS CURRENT
IB
Input bias current
IOS
Input offset current
TA = 25°C
TA = –40°C to +125°C
±10
pA
±1
nA
TA = 25°C
±10
TA = –40°C to +125°C
±50
pA
NOISE
Input voltage noise
en
Input voltage noise density
f = 0.1 Hz to 10 Hz
2
f = 100 Hz
27
f = 1 kHz
22
µVPP
nV/√Hz
INPUT VOLTAGE
Common-mode voltage range (1)
VCM
CMRR
Common-mode rejection ratio
(V–) – 0.1
VS = ±2 V, (V–) – 0.1 V < VCM < (V+) – 2 V,
TA = –40°C to +125°C
(V+) – 2
V
100
dB
VS = ±18 V, (V–) – 0.1 V < VCM < (V+) – 2 V,
TA = –40°C to +125°C
95
110
INPUT IMPEDANCE
Differential
100 || 3
Common-mode
MΩ || pF
6 || 3
1012 Ω || pF
130
dB
OPEN-LOOP GAIN
AOL
Open-loop voltage gain
VS = 36 V,
(V–) + 0.35 V < VO < (V+) – 0.35 V,
TA = –40°C to +125°C
94
FREQUENCY RESPONSE
GBP
Gain bandwidth product
SR
Slew rate
1.2
MHz
G = +1
0.4
V/µs
To 0.1%, VS = ±18 V, G = +1, 10-V step
20
28
tS
Settling time
To 0.01% (12-bit), VS = ±18 V, G = +1,
10-V step
THD+N
Total harmonic distortion + noise
G = +1, f = 1 kHz, VO = 3 VRMS
µs
0.0002%
OUTPUT
VS = ±18 V, RL = 10 kΩ; TA = –40°C to +125°C
VO
Voltage output swing from rail
ISC
Short-circuit current
CLOAD
Capacitive load drive
RO
Open-loop output resistance
RL = 10 kΩ, AOL ≥ 94 dB,
TA = –40°C to +125°C
(V–) + 0.2
(V+) – 0.3
(V–) + 0.35
(V+) – 0.35
–20
17
See Typical Characteristics: Table of
Graphs
f = 1 MHz, IO = 0 A
900
V
mA
pF
Ω
POWER SUPPLY
VS
Specified voltage range
IQ
Quiescent current per amplifier
(1)
2.7
IO = 0 A, TA = –40°C to +125°C
125
36
V
175
µA
The input range can be extended beyond (V+) – 2 V up to V+. See the Typical Characteristics: Table of Graphs and Application and
Implementation sections for additional information.
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6.8 Typical Characteristics: Table of Graphs
at VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
Table 2. Characteristic Performance Measurements
DESCRIPTION
FIGURE
Offset Voltage Production Distribution
Figure 1
Offset Voltage vs Common-Mode Voltage
Figure 2
Offset Voltage vs Common-Mode Voltage (Upper Stage)
Figure 3
Input Bias Current vs Temperature
Figure 4
Output Voltage Swing vs Output Current (Maximum Supply)
Figure 5
CMRR and PSRR vs Frequency (Referred-to-Input)
Figure 6
0.1-Hz to 10-Hz Noise
Figure 7
Input Voltage Noise Spectral Density vs Frequency
Figure 8
Quiescent Current vs Supply Voltage
Figure 9
Open-Loop Gain and Phase vs Frequency
Figure 10
Closed-Loop Gain vs Frequency
Figure 11
Open-Loop Gain vs Temperature
Figure 12
Open-Loop Output Impedance vs Frequency
Figure 13
Small-Signal Overshoot vs Capacitive Load
Figure 14, Figure 15
No Phase Reversal
Figure 16
Small-Signal Step Response (100 mV)
Figure 17, Figure 18
Large-Signal Step Response
Figure 19, Figure 20
Large-Signal Settling Time
Figure 21, Figure 22
Short-Circuit Current vs Temperature
Figure 23
Maximum Output Voltage vs Frequency
Figure 24
EMIRR IN+ vs Frequency
Figure 25
10
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6.9 Typical Characteristics
20
16
14
Offset Voltage (mV)
Percentage of Amplifiers (%)
18
12
10
8
6
4
VCM = - 18.1 V
2
−1200
−1100
−1000
−900
−800
−700
−600
−500
−400
−300
−200
−100
0
100
200
300
400
500
600
700
800
900
1000
1100
1200
0
Offset Voltage (µV)
Common-Mode Voltage (V)
G001
5 typical units shown
Distribution taken from 400 amplifiers
Figure 2. Offset Voltage vs Common-Mode Voltage
Figure 1. Offset Voltage Production Distribution
2000
IB+
IBIOS
Input Bias Current (pA)
Offset Voltage (mV)
1500
Normal
Operation
1000
500
0
-500
-1000
-75
-50
-25
0
25
50
75
100
125
150
Temperature (°C)
Common-Mode Voltage (V)
5 typical units shown
Figure 4. Input Bias Current vs Temperature
Figure 3. Offset Voltage vs Common-Mode Voltage
(Upper Stage)
140
Common-Mode Rejection Ratio (dB),
Power-Supply Rejection Ratio (dB)
18
Output Voltage (V)
17
16
15
14.5
-14.5
-15
-40°C
+25°C
+125°C
-16
-17
120
100
80
60
40
+PSRR
-PSRR
CMRR
20
0
-18
0
1
2
3
4
5
6
7
8
9
10
1
10
Figure 5. Output Voltage Swing vs Output Current
(Maximum Supply)
100
1k
10k
100k
1M
Frequency (Hz)
Output Current (mA)
Figure 6. CMRR and PSRR vs Frequency
(Referred-to Input)
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Typical Characteristics (continued)
1 mV/div
Voltage Noise Density (nV/ Hz)
1000
100
10
1
1
10
100
1k
10k
Frequency (Hz)
100k
1M
G014
Figure 8. Input Voltage Noise Spectral Density vs Frequency
Figure 7. 0.1-Hz to 10-Hz Noise
140
135
120
90
Gain
45
Gain (dB)
80
0
Phase
60
-45
40
-90
20
-135
0
-180
-20
-225
-40
0.1
1
10
100
1k
10k
100k
1M
Phase (°)
Quiescent Current (mA)
100
-270
10M
Frequency (Hz)
Figure 10. Open-Loop Gain and Phase vs Frequency
Figure 9. Quiescent Current vs Supply Voltage
3
50
VS = 2.7 V
40
Open-Loop Gain (mV/V)
2.5
Gain (dB)
30
20
10
0
1k
10k
1.5
1
0
100k
1M
Frequency (Hz)
10M
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100M
-75
-50
-25
0
25
50
75
100
125
150
Temperature (°C)
G020
Figure 11. Closed-Loop Gain vs Frequency
12
VS = 36 V
2
0.5
G = −1
G=1
G = 100
−10
−20
VS = 4 V
Figure 12. Open-Loop Gain vs Temperature
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Typical Characteristics (continued)
Open-Loop Output Impedance (W)
10k
1k
100
10
18 V
ROUT
1
W
W
W
1m
1
10
100
1k
10k
100k
1M
RL
-18 V
CL
10M
Frequency (Hz)
100-mV output step, RL = 10 kΩ, G = +1
Figure 13. Open-Loop Output Impedance vs Frequency
Figure 14. Small-Signal Overshoot vs Capacitive Load
18 V
5 V/div
-18 V
37-VPP
Sine Wave
(±18.5 V)
RI = 10 kW
RF = 10 kW
18 V
ROUT
W
W
W
CL
-18 V
Time (100 ms/div)
100-mV output step, RL = 10 kΩ, G = –1
Figure 16. No Phase Reversal
20 mV/div
20 mV/div
Figure 15. Small-Signal Overshoot vs Capacitive Load
+18 V
-18 V
RL
RI
= 2 kW
RF
= 2 kW
18 V
CL
CL
-18 V
Time (5 ms/div)
Time (5 ms/div)
RL = 10 kΩ, CL = 10 pF, G = +1
RL = 10 kΩ, CL = 10 pF, G = –1
Figure 17. Small-Signal Step Response (100 mV)
Figure 18. Small-Signal Step Response (100 mV)
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2 V/div
2 V/div
Typical Characteristics (continued)
Time (50 μs/div)
Time (50 ms/div)
G = +1, RL = 10 kΩ, CL = 10 pF
G = –1, RL = 10 kΩ, CL = 10 pF
Figure 20. Large-Signal Step Response
10
10
8
8
6
6
4
D From Final Value (mV)
D From Final Value (mV)
Figure 19. Large-Signal Step Response
12-Bit Settling
2
0
-2
(±1/2LSB = ±0.012%)
-4
-6
4
0
-2
-6
-8
-10
-10
10
20
30
40
50
60
70
80
90
(±1/2 LSB = ±0.012%)
-4
-8
0
12-Bit Settling
2
0
100
10
20
40
50
60
10-V negative step, G = –1
10-V positive step, G = +1
Figure 22. Large-Signal Settling Time
Figure 21. Large-Signal Settling Time
15
30
Short-Circuit Current, Source
Short-Circuit Current, Sink
24
VS = ±15 V
12.5
18
Output Voltage (VPP )
Short-Circuit Current (mA)
30
Time (ms)
Time (ms)
12
6
0
-6
-12
-18
Maximum output range without
slew−rate induced distortion
10
7.5
VS = ±5 V
5
2.5
VS = ±1.35 V
-24
-30
-50
0
-30
-10
10
30
50
70
90
Temperature (q C)
110
130
150
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10k
100k
Frequency (Hz)
1M
10M
D002
Figure 23. Short-Circuit Current vs Temperature
14
1k
G035
Figure 24. Maximum Output Voltage vs Frequency
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Typical Characteristics (continued)
140
EMIRR IN+ (dB)
120
100
80
60
40
20
0
10M
100M
1G
10G
Frequency (Hz)
PRP = –10 dBm, VS = ±18 V, VCM = 0 V
Figure 25. EMIRR IN+ vs Frequency
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7 Detailed Description
7.1 Overview
The TLVx170 family of op amps provides high overall performance, making the devices ideal for many generalpurpose applications. The excellent offset drift of only 2 μV/°C provides excellent stability over the entire
temperature range. In addition, the family offers very good overall performance with high CMRR, PSRR, and AOL.
7.2 Functional Block Diagram
PCH
FF Stage
Ca
Cb
+IN
PCH
Input Stage
Output
Stage
2nd Stage
OUT
-IN
NCH
Input Stage
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7.3 Feature Description
7.3.1 Operating Characteristics
The TLVx170 family of amplifiers is specified for operation from 2.7 V to 36 V (±1.35 V to ±18 V). Many of the
specifications apply from –40°C to +125°C. Parameters that can exhibit significant variance with regard to
operating voltage or temperature are presented in the Typical Characteristics: Table of Graphs section.
7.3.2 Phase-Reversal Protection
The TLVx170 family has an internal phase-reversal protection. Many op amps exhibit a phase reversal when the
input is driven beyond the linear common-mode range. This condition is most often encountered in noninverting
circuits when the input is driven beyond the specified common-mode voltage range, causing the output to
reverse into the opposite rail. The input of the TLVx170 prevents phase reversal with excessive common-mode
voltage. Instead, the output limits into the appropriate rail. This performance is shown in Figure 26.
18 V
5 V/div
-18 V
37-VPP
Sine Wave
(±18.5 V)
Time (100 ms/div)
Figure 26. No Phase Reversal
7.3.3 Electrical Overstress
Designers often ask questions about the capability of an op amp to withstand electrical overstress. These
questions tend to focus on the device inputs, but can involve the supply voltage pins or even the output pin. Each
of these different pin functions have electrical stress limits determined by the voltage breakdown characteristics
of the particular semiconductor fabrication process and specific circuits connected to the pin. Additionally, internal
electrostatic discharge (ESD) protection is built into these circuits for protection from accidental ESD events both
before and during product assembly.
A good understanding of this basic ESD circuitry and the relevance to an electrical overstress event is helpful.
Figure 27 illustrates the ESD circuits contained in the TLVx170 (indicated by the dashed line area). The ESD
protection circuitry involves several current-steering diodes connected from the input and output pins and routed
back to the internal power-supply lines, where the diodes meet at an absorption device internal to the op amp.
This protection circuitry is intended to remain inactive during normal circuit operation.
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Feature Description (continued)
TVS
+
±
RF
+VS
R1
IN±
RS
IN+
2.5 NŸ
2.5 NŸ
+
Power-Supply
ESD Cell
ID
VIN
RL
+
±
+
±
±VS
TVS
Figure 27. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application
An ESD event produces a short-duration, high-voltage pulse that is transformed into a short-duration, highcurrent pulse when discharging through a semiconductor device. The ESD protection circuits are designed to
provide a current path around the op amp core to prevent damage. The energy absorbed by the protection
circuitry is then dissipated as heat.
When an ESD voltage develops across two or more amplifier device pins, current flows through one or more
steering diodes. Depending on the path that the current takes, the absorption device can activate. The absorption
device has a trigger, or threshold voltage, that is above the normal operating voltage of the TLVx170 but below
the device breakdown voltage level. When this threshold is exceeded, the absorption device quickly activates
and clamps the voltage across the supply rails to a safe level.
When the op amp connects into a circuit, as shown in Figure 27, the ESD protection components are intended to
remain inactive and do not become involved in the application circuit operation. However, circumstances can
arise where an applied voltage exceeds the operating voltage range of a given pin. If this condition occurs, there
is a risk that some internal ESD protection circuits can turn on and conduct current. Any such current flow occurs
through steering-diode paths and rarely involves the absorption device.
Figure 27 shows a specific example where the input voltage (VIN) exceeds the positive supply voltage (V+) by
500 mV or more. Much of what happens in the circuit depends on the supply characteristics. If V+ can sink the
current, then one of the upper input steering diodes conducts and directs current to V+. Excessively high current
levels can flow with increasingly higher VIN. As a result, the data sheet specifications recommend that
applications limit the input current to 10 mA.
If the supply is not capable of sinking the current, VIN can begin sourcing current to the op amp and then take
over as the source of positive supply voltage. The danger in this case is that the voltage can rise to levels that
exceed the op amp absolute maximum ratings.
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Feature Description (continued)
Another common question involves what happens to the amplifier if an input signal is applied to the input when
the power supplies (V+ or V–) are at 0 V. Again, this question depends on the supply characteristic when at 0 V,
or at a level below the input signal amplitude. If the supplies appear as high impedance, then the input source
supplies the op amp current through the current-steering diodes. This state is not a normal bias condition; most
likely, the amplifier does not operate normally. If the supplies are low impedance, then the current through the
steering diodes can become quite high. The current level depends on the ability of the input source to deliver
current, and any resistance in the input path.
If there is any uncertainty about the ability of the supply to absorb this current, add external Zener diodes to the
supply pins; see Figure 27. Select the Zener voltage so that the diode does not turn on during normal operation.
However, the Zener voltage must be low enough so that the Zener diode conducts if the supply pin begins to rise
above the safe-operating, supply-voltage level.
The TLVx170 input pins are protected from excessive differential voltage with back-to-back diodes; see
Figure 27. In most circuit applications, the input protection circuitry has no effect. However, in low-gain or G = 1
circuits, fast-ramping input signals can forward-bias these diodes because the output of the amplifier cannot
respond rapidly enough to the input ramp. If the input signal is fast enough to create this forward-bias condition,
limit the input signal current to 10 mA or less. If the input signal current is not inherently limited, an input series
resistor can be used to limit the input signal current. This input series resistor degrades the low-noise
performance of the TLVx170. Figure 27 illustrates an example configuration that implements a current-limiting
feedback resistor.
7.3.4 Capacitive Load and Stability
The dynamic characteristics of the TLVx170 are optimized for common operating conditions. The combination of
low closed-loop gain and high capacitive loads decreases the phase margin of the amplifier and can lead to gain
peaking or oscillations. As a result, heavier capacitive loads must be isolated from the output. The simplest way
to achieve this isolation is to add a small resistor (for example, ROUT equal to 50 Ω) in series with the output.
Figure 28 and Figure 29 show graphs of small-signal overshoot versus capacitive load for several values of
ROUT. Also, see the Feedback Plots Define Op Amp AC Performance application report for details of analysis
techniques and application circuits.
18 V
RI = 10 kW
RF = 10 kW
ROUT
18 V
W
W
W
-18 V
RL
W
W
W
CL
100-mV output step, RL = 10 kΩ, G = +1
Figure 28. Small-Signal Overshoot vs Capacitive Load
ROUT
CL
-18 V
100-mV output step, RL = 10 kΩ, G = –1
Figure 29. Small-Signal Overshoot vs Capacitive Load
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7.4 Device Functional Modes
7.4.1 Common-Mode Voltage Range
The input common-mode voltage range of the TLVx170 family extends 100 mV below the negative rail and within
2 V of the top rail for normal operation.
This device can operate with full rail-to-rail input 100 mV beyond the top rail, but with reduced performance within
2 V of the top rail. The typical performance in this range is summarized in Table 3.
Table 3. Typical Performance for Common-Mode Voltages Within 2 V of the Positive Supply
PARAMETER
Input common-mode voltage
MIN
TYP
(V+) – 2
MAX
(V+) + 0.1
Offset voltage
UNIT
V
7
mV
Offset voltage vs temperature
12
µV/°C
Common-mode rejection ratio
65
dB
Open-loop gain
60
dB
Gain-bandwidth product
0.3
MHz
Slew rate
0.3
V/µs
7.4.2 Overload Recovery
Overload recovery is defined as the time required for the op amp output to recover from the saturated state to
the linear state. The output devices of the op amp enter the saturation region when the output voltage exceeds
the rated operating voltage, either resulting from the high input voltage or the high gain. After the device enters
the saturation region, the charge carriers in the output devices need time to return back to the normal state. After
the charge carriers return back to the equilibrium state, the device begins to slew at the normal slew rate. Thus,
the propagation delay in case of an overload condition is the sum of the overload recovery time and the slew
time. The overload recovery time for the TLVx170 is approximately 2 µs.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TLVx170 family of op amps provides high overall performance in a large number of general-purpose
applications. As with all amplifiers, applications with noisy or high-impedance power supplies require decoupling
capacitors placed close to the device pins. In most cases, 0.1-µF capacitors are adequate. Follow the additional
recommendations in the Layout Guidelines section in order to achieve the maximum performance from this
device. Many applications can introduce capacitive loading to the output of the amplifier (potentially causing
instability). One method of stabilizing the amplifier in such applications is to add an isolation resistor between the
amplifier output and the capacitive load. The design process for selecting this resistor is given in the Typical
Application section.
8.2 Typical Application
This circuit can be used to drive capacitive loads (such as cable shields, reference buffers, MOSFET gates, and
diodes). The circuit uses an isolation resistor (RISO) to stabilize the output of an op amp. RISO modifies the openloop gain of the system to ensure the circuit has sufficient phase margin.
+VS
VOUT
RISO
+
VIN
+
±
CLOAD
-VS
Copyright © 2016, Texas Instruments Incorporated
Figure 30. Unity-Gain Buffer With RISO Stability Compensation
8.2.1 Design Requirements
The design requirements are:
• Supply voltage: 30 V (±15 V)
• Capacitive loads: 100 pF, 1000 pF, 0.01 μF, 0.1 μF, and 1 μF
• Phase margin: 45° and 60°
8.2.2 Detailed Design Procedure
Figure 30 shows a unity-gain buffer driving a capacitive load. Equation 1 shows the transfer function for the
circuit in Figure 30. Not shown in Figure 30 is the open-loop output resistance of the op amp, Ro.
1 + CLOAD × RISO × s
T(s) =
1 + Ro + RISO × CLOAD × s
(1)
The transfer function in Equation 1 has a pole and a zero. The frequency of the pole (fp) is determined by (Ro +
RISO) and CLOAD. Components RISO and CLOAD determine the frequency of the zero (fz). A stable system is
obtained by selecting RISO such that the rate of closure (ROC) between the open-loop gain (AOL) and 1/β is
20 dB per decade; see Figure 31. The 1/β curve for a unity-gain buffer is 0 dB.
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Typical Application (continued)
120
AOL
100
1
fp
2 u Πu RISO
Gain (dB)
80
60
Ro
u CLOAD
40 dB
fz
40
1
2 u Πu RISO u CLOAD
1 dec
1/
20
ROC
20 dB
dec
0
10
100
1k
10k
100k
1M
10M
100M
Frequency (Hz)
Figure 31. TIPD128 Unity-Gain Amplifier With RISO Compensation
ROC stability analysis is typically simulated. The validity of the analysis depends on multiple factors, especially
the accurate modeling of Ro. In addition to simulating the ROC, a robust stability analysis includes a
measurement of overshoot percentage and ac gain peaking of the circuit using a function generator,
oscilloscope, and gain and phase analyzer. Phase margin is then calculated from these measurements. Table 4
shows the overshoot percentage and ac gain peaking that correspond to phase margins of 45° and 60°. For
more details on this design and other alternative devices that can be used in place of the TLV170, see the
Capacitive Load Drive Solution Using an Isolation Resistor precision design.
Table 4. Phase Margin versus Overshoot and AC Gain
Peaking
PHASE
MARGIN
OVERSHOOT
AC GAIN PEAKING
45°
23.3%
2.35 dB
60°
8.8%
0.28 dB
8.2.3 Application Curve
Using the described methodology, the values of RISO that yield phase margins of 45º and 60º for various
capacitive loads were determined. The results are shown in Figure 32.
10000
45° Phase Margin
Isolation Resistor (RISO,
)
60° Phase Margin
1000
100
10
0.1
1
10
100
Capacitive Load (nF)
1000
C002
Figure 32. Isolation Resistor Required for Various Capacitive Loads to Achieve a Target Phase Margin
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9 Power Supply Recommendations
The TLVx170 is specified for operation from 2.7 V to 36 V (±1.35 V to ±18 V); many specifications apply from
–40°C to +125°C. Parameters that can exhibit significant variance with regard to operating voltage or
temperature are presented in the Typical Characteristics: Table of Graphs section.
CAUTION
Supply voltages larger than 40 V can permanently damage the device; see the
Absolute Maximum Ratings.
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or highimpedance power supplies. For more detailed information on bypass capacitor placement, see the Layout
section.
10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good printed-circuit board (PCB) layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and the op amp
itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power
sources local to the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for singlesupply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground
planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically
separate digital and analog grounds, paying attention to the flow of the ground current.
• In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicularly is much
better than in parallel with the noisy trace.
• Place the external components as close to the device as possible. As illustrated in Figure 34, keeping RF
and RG close to the inverting input minimizes parasitic capacitance.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly
reduce leakage currents from nearby traces that are at different potentials.
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10.2 Layout Example
+
VIN
VOUT
RG
±
RF
Figure 33. Schematic Representation
Run the input traces
as far away from
the supply lines
as possible
Place components close
to device and to each
other to reduce parasitic
errors
VS+
RF
NC
NC
GND
±IN
V+
VIN
+IN
OUTPUT
V±
NC
Use a low-ESR,
ceramic bypass
capacitor
RG
VS±
GND
GND
VOUT
Ground (GND) plane on another layer
Use low-ESR,
ceramic bypass
capacitor
Figure 34. Op Amp Board Layout for a Noninverting Configuration
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 TINA-TI™ (Free Software Download)
TINA-TI™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINATI™ is a free, fully-functional version of the TINA-TI™ software, preloaded with a library of macromodels in
addition to a range of both passive and active models. TINA-TI™ provides all the conventional dc, transient, and
frequency domain analysis of SPICE, as well as additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI™ offers extensive post-processing
capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select
input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool.
NOTE
These files require that either the TINA software (from DesignSoft™) or the TINA-TI™
software be installed. Download the free TINA-TI™ software from the TINA-TI™ folder.
11.1.1.2 DIP Adapter EVM
The DIP Adapter EVM tool provides an easy, low-cost way to prototype small surface-mount devices. The
evaluation tool uses these TI packages: D or U (SOIC-8), PW (TSSOP-8), DGK (VSSOP-8), DBV (SOT23-6,
SOT23-5, and SOT23-3), DCK (SC70-6 and SC70-5), and DRL (SOT563-6). The DIP adapter EVM can also be
used with terminal strips or can be wired directly to existing circuits.
11.1.1.3 Universal Op Amp EVM
The Universal Op Amp EVM is a series of general-purpose, blank circuit boards that simplify prototyping circuits
for a variety of device package types. The evaluation module board design allows many different circuits to be
constructed easily and quickly. Five models are offered, with each model intended for a specific package type.
PDIP, SOIC, VSSOP, TSSOP, and SOT23 packages are all supported.
NOTE
These boards are unpopulated, so users must provide their own devices. TI recommends
requesting several op amp device samples when ordering the universal op amp EVM.
11.1.1.4 TI Precision Designs
TI precision designs are analog solutions created by TI’s precision analog applications experts and offer the
theory of operation, component selection, simulation, a complete PCB schematic and layout, bill of materials, and
measured performance of many useful circuits. TI precision designs are available online at
www.ti.com/ww/en/analog/precision-designs/.
11.1.1.5 WEBENCH® Filter Designer
The WEBENCH® Filter Designer is a simple, powerful, and easy-to-use active filter design program. The
WEBENCH® Filter Designer lets you create optimized filter designs using a selection of TI op amps and passive
components from TI's vendor partners.
Available as a web-based tool from the WEBENCH® design center, the WEBENCH® filter designer allows
complete multistage active filter solutions to be designed, optimized, and simulated within minutes.
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11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
Feedback Plots Define Op Amp AC Performance (SBOA015)
11.3 Related Links
Table 5 lists quick access links. Categories include technical documents, support and community resources,
tools and software, and quick access to sample or buy.
Table 5. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TLV170
Click here
Click here
Click here
Click here
Click here
TLV2170
Click here
Click here
Click here
Click here
Click here
TLV4170
Click here
Click here
Click here
Click here
Click here
11.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.5 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.6 Trademarks
TINA-TI, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
DesignSoft is a trademark of DesignSoft, Inc.
11.7 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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26-Mar-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TLV170IDBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
14QT
TLV170IDBVT
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
14QT
TLV170IDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TLV170
TLV2170IDGKR
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
14NV
TLV2170IDGKT
ACTIVE
VSSOP
DGK
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
14NV
TLV2170IDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TL2170
TLV4170ID
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
TLV4170
TLV4170IDR
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
TLV4170
TLV4170IPWR
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TLV4170
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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