TLV5604
2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS176B – DECEMBER 1997 – REVISED JULY 2002
D
D
D
D
D
D
D
D
D
Four 10-Bit D/A Converters
Programmable Settling Time
of 3 µs or 9 µs Typ
TMS320, (Q)SPI, and Microwire
Compatible Serial Interface
Internal Power-On Reset
Low Power Consumption:
5.5 mW, Slow Mode – 5-V Supply
3.3 mW, Slow Mode – 3-V Supply
Reference Input Buffers
Voltage Output Range . . . 2 × the Reference
Input Voltage
Monotonic Over Temperature
Dual 2.7-V to 5.5-V Supply (Separate Digital
and Analog Supplies)
D
D
D
Hardware Power Down (10 nA)
Software Power Down (10 nA)
Simultaneous Update
applications
D
D
D
D
D
D
Battery Powered Test Instruments
Digital Offset and Gain Adjustment
Industrial Process Controls
Machine and Motion Control Devices
Communications
Arbitrary Waveform Generation
D OR PW PACKAGE
(TOP VIEW)
DVDD
PD
LDAC
DIN
SCLK
CS
FS
DGND
description
The TLV5604 is a quadruple 10-bit voltage output
digital-to-analog converter (DAC) with a flexible
4-wire serial interface. The 4-wire serial interface
allows glueless interface to TMS320, SPI, QSPI,
and Microwire serial ports. The TLV5604 is
programmed with a 16-bit serial word comprised
of a DAC address, individual DAC control bits, and
a 10-bit DAC value.
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
AVDD
REFINAB
OUTA
OUTB
OUTC
OUTD
REFINCD
AGND
The device has provision for two supplies: one digital supply for the serial interface (via pins DVDD and DGND),
and one for the DACs, reference buffers and output buffers (via pins AVDD and AGND). Each supply is
independent of the other, and can be any value between 2.7 V and 5.5 V. The dual supplies allow a typical
application where the DAC will be controlled via a microprocessor operating on a 3-V supply (also used on pins
DVDD and DGND), with the DACs operating on a 5-V supply. Of course, the digital and analog supplies can be
tied together.
The resistor string output voltage is buffered by a x2 gain rail-to-rail output buffer. The buffer features a Class AB
output stage to improve stability and reduce settling time. A rail-to-rail output stage and a power-down mode
makes it ideal for single voltage, battery based applications. The settling time of the DAC is programmable to
allow the designer to optimize speed versus power dissipation. The settling time is chosen by the control bits
within the 16-bit serial input string. A high-impedance buffer is integrated on the REFINAB and REFINCD
terminals to reduce the need for a low source impedance drive to the terminal. REFINAB and REFINCD allow
DACs A and B to have a different reference voltage then DACs C and D.
The device, implemented with a CMOS process, is available in 16-terminal SOIC and TSSOP packages. The
TLV5604C is characterized for operation from 0°C to 70°C. The TLV5604I is characterized for operation from
– 40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SPI and QSPI are trademarks of Motorola, Inc.
Microwire is a trademark of National Semiconductor Corporation.
Copyright 2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
TLV5604
2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS176B – DECEMBER 1997 – REVISED JULY 2002
AVAILABLE OPTIONS
PACKAGE
TA
SOIC
(D)
TSSOP
(PW)
0°C to 70°C
TLV5604CD
TLV5604CPW
– 40°C to 85°C
TLV5604ID
TLV5604IPW
functional block diagram
AVDD
15
REFINAB
DVDD
16
1
DAC A
+
_
Power-On
Reset
DIN
4
Serial
Input
Register
14
2
14-Bit
Data
and
Control
Register
7
FS
5
SCLK
CS
6
14
x2
10
10-Bit
DAC
Latch
2
2-Bit
Control
Data
Latch
DAC
Select/
Control
Logic
OUTA
10
2
Power Down/
Speed Control
13
DAC B
OUTB
DAC C
12
OUTC
DAC D
11
OUTD
REFINCD
3
9
AGND
2
2
8
DGND
LDAC
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PD
TLV5604
2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS176B – DECEMBER 1997 – REVISED JULY 2002
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
AGND
9
AVDD
CS
16
DGND
8
DIN
4
DVDD
1
FS
7
I
Frame sync input. The falling edge of the frame sync pulse indicates the start of a serial data frame shifted out
to the TLV5604.
PD
2
I
Power-down pin. Powers down all DACs (overriding their individual power down settings), and all output stages.
This terminal is active low.
LDAC
3
I
Load DAC. When the LDAC signal is high, no DAC output updates occur when the input digital data is read into
the serial interface. The DAC outputs are only updated when LDAC is low.
REFINAB
15
I
Voltage reference input for DACs A and B.
REFINCD
10
I
Voltage reference input for DACs C and D.
SCLK
5
I
Serial Clock input
OUTA
14
O
DAC A output
OUTB
13
O
DAC B output
OUTC
12
O
DAC C output
OUTD
11
O
DAC D output
6
Analog ground
Analog supply
I
Chip select. This terminal is active low.
Digital ground
I
Serial data input
Digital supply
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, (DVDD, AVDD to GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Supply voltage difference, (AVDD to DVDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –2.8 V to 2.8 V
Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to DVDD + 0.3 V
Reference input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to AVDD + 0.3 V
Operating free-air temperature range, TA: TLV5604C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
TLV5604I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
TLV5604
2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS176B – DECEMBER 1997 – REVISED JULY 2002
recommended operating conditions
Supply voltage
voltage, AVDD, DVDD
High level digital input voltage
High-level
voltage, VIH
Low level digital input voltage,
Low-level
voltage VIL
Reference voltage,
voltage Vreff to REFINAB
REFINAB, REFINCD terminal
MIN
NOM
5-V supply
4.5
5
5.5
3-V supply
2.7
3
3.3
DVDD = 2.7 V
2
DVDD = 5.5 V
2.4
MAX
UNIT
V
V
DVDD = 2.7 V
0.6
DVDD = 5.5 V
1
5-V supply (see Note 1)
0
2.048
3-V supply (see Note 1)
0
1.024
2
10
Load resistance, RL
AVDD–1.5
AVDD–1.5
V
V
kΩ
Load capacitance, CL
100
pF
Serial clock rate, SCLK
20
MHz
air temperature
Operating free
free-air
TLV5604C
0
70
TLV5604I
–40
85
°C
NOTE 1: Voltages greater than AVDD/2 will cause output saturation for large DAC codes.
electrical characteristics over recommended operating free-air temperature range
(unless otherwise noted)
static DAC specifications
PARAMETER
TEST CONDITIONS
Resolution
EZS
EG
Integral nonlinearity (INL), end point adjusted
See Note 2
Differential nonlinearity (DNL)
See Note 3
Zero scale error (offset error at zero scale)
See Note 4
Zero scale error temperature coefficient
See Note 5
Gain error
See Note 6
Power supply rejection ratio
TYP
MAX
10
Gain error temperature coefficient
PSRR
MIN
See Note 7
Zero scale gain
Gain
See Notes 8 and 9
UNIT
bits
±0.1
±1
LSB
±1
LSB
±12
10
±0.6
10
– 80
– 80
mV
ppm/°C
%of FS
voltage
ppm/°C
dB
NOTES: 2. The relative accuracy or integral nonlinearity (INL) sometimes referred to as linearity error, is the maximum deviation of the output
from the line between zero and full scale excluding the effects of zero code and full-scale errors.
3. The differential nonlinearity (DNL) sometimes referred to as differential error, is the difference between the measured and ideal
1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains
constant) as a change in the digital input code.
4. Zero-scale error is the deviation from zero voltage output when the digital input code is zero.
5. Zero-scale-error temperature coefficient is given by: EZS TC = [EZS (Tmax) – EZS (Tmin)]/Vref × 106/(Tmax – Tmin).
6. Gain error is the deviation from the ideal output (2Vref – 1 LSB) with an output load of 10 kΩ excluding the effects of the zero-error.
7. Gain temperature coefficient is given by: EG TC = [EG(Tmax) – EG (Tmin)]/Vref × 106/(Tmax – Tmin).
8. Zero-scale-error rejection ratio (EZS–RR) is measured by varying the AVDD from 5 ±0.5 V and 3 ±0.3 V dc, and measuring the
proportion of this signal imposed on the zero-code output voltage.
9. Gain-error rejection ratio (EG-RR) is measured by varying the AVDD from 5 ±0.5 V and 3 ±0.3 V dc and measuring the proportion
of this signal imposed on the full-scale output voltage after subtracting the zero scale change.
4
POST OFFICE BOX 655303
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TLV5604
2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS176B – DECEMBER 1997 – REVISED JULY 2002
electrical characteristics over recommended operating free-air temperature range
(unless otherwise noted) (continued)
individual DAC output specifications
PARAMETER
VO
TEST CONDITIONS
Voltage output
MIN
RL = 10 kΩ
Output load regulation accuracy
TYP
0
MAX
AVDD–0.4
UNIT
V
0.1
0.25
% of FS
voltage
TYP
MAX
UNIT
RL = 2 kΩ vs 10 kΩ
reference input (REFINAB, REFINCD)
PARAMETER
VI
RI
Input voltage range
CI
Input capacitance
TEST CONDITIONS
MIN
See Note 10
0
AVDD–1.5
Input resistance
Reference feed through
REFIN = 1 Vpp at 1 kHz + 1.024 V dc
(see Note 11)
Reference input bandwidth
REFIN = 0.2
0 2 Vpp + 1.024
1 024 V dc
V
10
MΩ
5
pF
–75
dB
Slow
0.5
Fast
1
MHz
NOTES: 10. Reference input voltages greater than VDD/2 will cause output saturation for large DAC codes.
11. Reference feedthrough is measured at the DAC output with an input code = 000 hex and a Vref(REFINAB or REFINCD)
input = 1.024 Vdc + 1 Vpp at 1 kHz.
digital inputs (D0–D11, CS, WEB, LDAC, PD)
PARAMETER
IIH
IIL
High-level digital input current
CI
Input capacitance
TEST CONDITIONS
MIN
TYP
VI = DVDD
VI = 0 V
Low-level digital input current
MAX
UNIT
±1
µA
±1
µA
3
pF
power supply
PARAMETER
TEST CONDITIONS
5 V supply,
5-V
supply No load,
load Clock running
IDD
Power supply current
3 V supply,
supply No load,
load Clock running
3-V
Power down supply current,
See Figure 12
MIN
TYP
MAX
Slow
1.4
2.2
Fast
3.5
5.5
Slow
1
1.5
Fast
3
4.5
10
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
UNIT
mA
mA
nA
5
TLV5604
2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS176B – DECEMBER 1997 – REVISED JULY 2002
electrical characteristics over recommended operating free-air temperature range
(unless otherwise noted) (continued)
analog output dynamic performance
PARAMETER
SR
Output slew rate
TEST CONDITIONS
CL = 100 pF, RL = 10 kΩ,
VO = 10% to 90%
90%,
Vref = 2.048 V, 1024 V
MIN
TYP
MAX
UNIT
Fast
5
V/µs
Slow
1
V/µs
ts
Output settling time
To ± 0.5 LSB,, CL = 100 pF,,
RL = 10 kΩ, See Notes 12 and 14
Fast
2.5
4
Slow
8.5
18
ts(c)
( )
Output settling time,
time code to code
To ± 0.5 LSB,, CL = 100 pF,,
RL = 10 kΩ, See Note 13
Fast
1
Slow
2
Glitch energy
Code transition from 7FF to 800
10
SNR
Signal-to-noise ratio
68
S/(N+D)
Signal to noise + distortion
THD
Total harmonic Distortion
SFDR
Spurious free dynamic range
Sinewave generated by DAC,
R f
Reference
voltage
l
=1
1.024
024 at 3 V and
d2
2.048
048 at 5 V
V,
fs = 400 KSPS,
fOUT = 1.1 kHz sinewave,
CL = 100 pF,
pF
RL = 10 kΩ,
kΩ
BW = 20 kHz
µs
µs
nV-sec
65
–68
dB
70
NOTES: 12. Settling time is the time for the output signal to remain within ± 0.5LSB of the final measured value for a digital input code change
of 020 hex to 3FF hex or 3FF hex to 020 hex.
13. Settling time is the time for the output signal to remain within ± 0.5LSB of the final measured value for a digital input code change
of one count, 1FF hex to 200 hex.
14. Limits are ensured by design and characterization, but are not production tested.
6
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TLV5604
2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS176B – DECEMBER 1997 – REVISED JULY 2002
electrical characteristics over recommended operating free-air temperature range
(unless otherwise noted) (continued)
digital input timing requirements
MIN
tsu(CS–FS)
tsu(FS–CK)
Setup time, CS low before FS↓
Setup time, FS low before first negative SCLK edge
NOM
MAX
UNIT
10
ns
8
ns
tsu(C16–FS)
Setup time, sixteenth negative SCLK edge after FS low on which bit D0 is sampled before
rising edge of FS
10
ns
tsu(C16–CS)
Setup time. The first positive SCLK edge after D0 is sampled before CS rising edge. If FS
is used instead of the SCLK positive edge to update the DAC, then the setup time is between
the FS rising edge and CS rising edge.
10
ns
twH
twL
Pulse duration, SCLK high
25
ns
Pulse duration, SCLK low
25
ns
tsu(D)
Setup time, data ready before SCLK falling edge
8
ns
th(D)
twH(FS)
Hold time, data held valid after SCLK falling edge
5
ns
20
ns
Pulse duration, FS high
PARAMETER MEASUREMENT INFORMATION
SCLK
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
1
2
tsu(D)
DIN
twH
twL
3
4
5
15
16
th(D)
D15
D14
D13
D12
tsu(FS-CK)
D1
D0
ÎÎ
ÎÎ
ÎÎ
ÎÎÎ
ÎÎÎ
tsu(C16-CS)
tsu(CS-FS)
CS
twH(FS)
tsu(C16-FS)
FS
Figure 1. Timing Diagram
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7
TLV5604
2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS176B – DECEMBER 1997 – REVISED JULY 2002
TYPICAL CHARACTERISTICS
LOAD REGULATION
LOAD REGULATION
0.35
0.20
VDD = 5 V,
VREF = 2 V,
VO = Full Scale
0.16
VO – Output Voltage – V
VO – Output Voltage – V
0.30
VDD = 3 V,
VREF = 1 V,
VO = Full Scale
0.18
0.25
5 V Slow Mode, Sink
0.20
5 V Fast Mode, Sink
0.15
0.10
0.14
3 V Slow Mode, Sink
0.12
0.10
3 V Fast Mode, Sink
0.08
0.06
0.04
0.05
0.02
0
0
0
0.02 0.04 0.1
0.2
0.8
0.4
1
2
4
0
Load Current – mA
0.01 0.02 0.05 0.1 0.2 0.5
Load Current – mA
Figure 2
0.8
1
2
Figure 3
LOAD REGULATION
LOAD REGULATION
4.002
2.003
4.00
2.0025
5 V Slow Mode, Source
3 V Fast Mode, Source
VO – Output Voltage – V
VO – Output Voltage – V
3.998
3.996
3.994
5 V Fast Mode, Source
3.992
3.99
3.988
VDD = 5 V,
VREF = 2 V,
VO = Full Scale
3.986
2.002
2.0015
3 V Slow Mode, Source
2.001
2.0005
2
VDD = 3 V,
VREF = 1 V,
VO = Full Scale
1.9995
3.984
1.999
0
0.02 0.04 0.1 0.2 0.4 0.8
Load Current – mA
1
2
4
0
0.01 0.02 0.05 0.1 0.2 0.5
Load Current – mA
Figure 4
8
Figure 5
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
0.8
1
2
TLV5604
2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS176B – DECEMBER 1997 – REVISED JULY 2002
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
TEMPERATURE
SUPPLY CURRENT
vs
TEMPERATURE
4
4
VDD = 3 V,
VREF = 1.024 V,
VO = Full Scale
3.5
Fast Mode
Fast Mode
I DD – Supply Current – mA
I DD – Supply Current – mA
3.5
3
2.5
2
1.5
3
2.5
2
Slow Mode
1.5
Slow Mode
1
VDD = 5 V,
VREF = 1.024 V,
VO = Full Scale
1
0.5
–40
–20
0
20
40
60
T – Temperature – °C
80
0.5
–40
100
–20
Figure 6
80
100
Figure 7
TOTAL HARMONIC DISTORTION
vs
FREQUENCY
TOTAL HARMONIC DISTORTION
vs
FREQUENCY
0
0
Vref = 1 V dc + 1 V p/p Sinewave,
Output Full Scale
–10
THD – Total Harmonic Distortion – dB
THD – Total Harmonic Distortion – dB
0
20
40
60
T – Temperature – °C
–20
–30
––40
–50
–60
Fast Mode
–70
–80
0
5
10
20
30
50
100
Vref = 1 V dc + 1 V p/p Sinewave,
Output Full Scale
–10
–20
–30
––40
–50
–60
Slow Mode
–70
–80
0
5
f – Frequency – kHz
10
20
30
50
100
f – Frequency – kHz
Figure 8
Figure 9
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
9
TLV5604
2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS176B – DECEMBER 1997 – REVISED JULY 2002
TYPICAL CHARACTERISTICS
0
Vref = 1 V dc + 1 V p/p Sinewave,
Output Full Scale
–10
TOTAL HARMONIC DISTORTION AND NOISE
vs
FREQUENCY
THD – Total Harmonic Distortion And Noise – dB
THD – Total Harmonic Distortion And Noise – dB
TOTAL HARMONIC DISTORTION AND NOISE
vs
FREQUENCY
–20
–30
––40
–50
Fast Mode
–60
–70
–80
0
Vref = 1 V dc + 1 V p/p Sinewave,
Output Full Scale
–10
–20
–30
––40
–50
Slow Mode
–60
–70
–80
0
5
10
30
20
50
100
0
5
10
f – Frequency – kHz
Figure 10
Figure 11
SUPPLY CURRENT
vs
TIME
(WHEN ENTERING POWER-DOWN MODE)
4000
I DD – Supply Current – µ A
3500
3000
2500
2000
1500
1000
500
0
0
200
400
600
800
t – Time – ns
Figure 12
10
20
30
f – Frequency – kHz
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1000
50
100
TLV5604
2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS176B – DECEMBER 1997 – REVISED JULY 2002
TYPICAL CHARACTERISTICS
INL – Integral Nonlinearity – LSB
INTEGRAL NONLINEARITY
0.2
VDD = 5 V, Vref = 2 V,
CLK = 1 MHz
0
–0.2
–0.4
–0.6
0
64
128
192 256
320 384 448 512
576 640
704
768 832 896 960 1024
Digital Code
DNL – Differential Nonlinearity – LSB
Figure 13
DIFFERENTIAL NONLINEARITY
0.15
VDD = 5 V, Vref = 2 V,
CLK = 1 MHz
0.1
0.05
0
–0.05
–0.1
0
64
128 192 256 320 384 448
512
576 640 704
768 832
896 960
1024
Digital Code
Figure 14
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11
TLV5604
2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS176B – DECEMBER 1997 – REVISED JULY 2002
APPLICATION INFORMATION
general function
The TLV5604 is a 10-bit single supply DAC based on a resistor string architecture. The device consists of a serial
interface, speed and power-down control logic, a reference input buffer, a resistor string, and a rail-to-rail output
buffer.
The output voltage (full scale determined by external reference) is given by:
[V]
2 REF CODE
2n
Where REF is the reference voltage and CODE is the digital input value within the range of 010 to 2n–1, where
n=10 (bits). The 16-bit data word, consisting of control bits and the new DAC value, is illustrated in the data
format section. A power-on reset initially resets the internal latches to a defined state (all bits zero).
serial interface
Explanation of data transfer: First, the device has to be enabled with CS set to low. Then, a falling edge of FS
starts shifting the data bit-per-bit (starting with the MSB) to the internal register on the falling edges of SCLK.
After 16 bits have been transferred or FS rises, the content of the shift register is moved to the DAC latch, which
updates the voltage output to the new level.
The serial interface of the TLV5604 can be used in two basic modes:
D
D
Four wire (with chip select)
Three wire (without chip select)
Using chip select (four wire mode), it is possible to have more than one device connected to the serial port of
the data source (DSP or microcontroller). The interface is compatible with the TMS320 family. Figure 15 shows
an example with two TLV5604s connected directly to a TMS320 DSP.
TLV5604
TLV5604
CS FS DIN SCLK
CS FS DIN SCLK
TMS320
DSP
XF0
XF1
FSX
DX
CLKX
Figure 15. TMS320 Interface
12
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TLV5604
2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS176B – DECEMBER 1997 – REVISED JULY 2002
APPLICATION INFORMATION
serial interface (continued)
If there is no need to have more than one device on the serial bus, then CS can be tied low. Figure 16 shows
an example of how to connect the TLV5604 to a TMS320, SPI, or Microwire port using only three pins.
TMS320
DSP
TLV5604
FSX
SPI
FS
DIN
DX
CLKX
TLV5604
FS
DIN
SS
MOSI
SCLK
SCLK
Microwire
FS
DIN
I/O
SO
SK
SCLK
CS
TLV5604
SCLK
CS
CS
Figure 16. Three-Wire Interface
Notes on SPI and Microwire: Before the controller starts the data transfer, the software has to generate a falling
edge on the I/O pin connected to FS. If the word width is 8 bits (SPI and Microwire), two write operations must
be performed to program the TLV5604. After the write operation(s), the DAC output is updated automatically
on the next positive clock edge following the sixteenth falling clock edge.
serial clock frequency and update rate
The maximum serial clock frequency is given by:
f
SCLKmax
+t
) twL(min) + 20 MHz
wH(min)
1
The maximum update rate is:
f
UPDATEmax
+
16
ǒ
t
1
wH(min)
) twL(min)
Ǔ
+ 1.25 MHz
Note that the maximum update rate is a theoretical value for the serial interface since the settling time of the
TLV5604 has to be considered also.
data format
The 16-bit data word for the TLV5604 consists of two parts:
D
D
Control bits
(D15 . . . D12)
New DAC value
(D11 . . . D0)
D15
D14
D13
D12
A1
A0
PWR
SPD
X: don’t care
SPD: Speed control bit.
PWR: Power control bit.
D11
1 → fast mode
1 → power down
D10
D9
D8
D7
D6
D5
New DAC value (10 bits)
D4
D3
D2
D1
D0
X
X
0 → slow mode
0 → normal operation
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13
TLV5604
2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS176B – DECEMBER 1997 – REVISED JULY 2002
APPLICATION INFORMATION
In power down mode, all amplifiers within the TLV5604 are disabled. A particular DAC (A, B, C, D) of the
TLV5604 is selected by A1 and A0 within the input word.
A1
A0
DAC
0
0
A
0
1
B
1
0
C
1
1
D
TLV5604 interfaced to TMS320C203 DSP
Hardware interfacing
Figure 17 shows an example of how to connect the TLV5604 to a TMS320C203 DSP. The serial port is
configured in burst mode, with FSX generated by the TMS320C203 to provide the Frame Sync (FS) input to
the TLV5604. Data is transmitted on the DX line, with the serial clock input on the CLKX line. The
general-purpose input/output port bits IO0 and IO1 are used to generate the Chip Select ( CS) and DAC Latch
Update ( LDAC) inputs to the TLV5604. The active low Power Down ( PD) is pulled high all the time to ensure
the DACs are enabled.
TMS320C203
TLV5604
SDIN
DX
VDD
SCLK
CLKX
FSX
FS
I/O 0
CS
I/O 1
LDAC
PD
VOUTA
VOUTB
REF
REFINAB
VOUTC
REFINCD
VOUTD
VSS
Figure 17. TLV5604 Interfaced with TMS320C203
Software
The application example generates a differential in-phase (sine) signal between the VOUTA and VOUTB pins,
and it is quadrature (cosine) signal as the differential signal between VOUTC and VOUTD.
The on-chip timer is used to generate interrupts at a fixed frequency. The related interrupt service routine pulses
LDAC low to update all 4 DACs simultaneously, then fetches and writes the next sample to all 4 DACs. The
samples are stored in a look-up table, which describes two full periods of a sine wave.
The synchronous serial port of the DSP is used in burst mode. In this mode, the processor generates an FS
pulse preceding the MSB of every data word. If multiple, contiguous words are transmitted, a violation of the
tsu(C16-FS) timing requirement will occur. To avoid this, the program waits until the transmission of the previous
word has been completed.
14
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TLV5604
2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS176B – DECEMBER 1997 – REVISED JULY 2002
APPLICATION INFORMATION
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––;
; Processor: TMS320C203 runnning at 40 MHz;
; Description:
;
; This program generates a differential in-phase (sine) on (OUTA–OUTB) and it’s
; quadrature (cosine) as a differential signal on (OUTC–OUTD).
;
; The DAC codes for the signal samples are stored as a table of 64 12–bit values,
; describing 2 periods of a sine function. A rolling pointer is used to address the
; table location in the first period of this waveform, from which the DAC A samples are
; read. The samples for the other 3 DACs are read at an offset to this rolling pointer:
; DAC
Function
Offset from rolling pointer;
; A
sine
0
; B
inverse sine
16
; C
cosine
8
; D
inverse cosine
24
;
; The on-chip timer is used to generate interrupts at a fixed rate. The interrupt
; service routine first pulses LDAC low to update all DACs simultaneously with the
; values which were written to them in the previous interrupt. Then all 4 DAC values are
; fetched and written out through the synchronous serial interface. Finally, the
; rolling pointer is incremented to address the next sample, ready for the next
; interrupt.
;
; 1998, Texas Instruments Incorporated
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––;
; ––––––––––I/O and memory mapped regs –––––––––––––––––––––––––––––––––––––––––––
.include ”regs.asm”
; ––––––––––––––jump vectors––––––––––––––––––––––––––––––––––––––––––––––––––––––
.ps
0h
b
start
b
int1
b
int23
b
timer_isr
;–––––––––––––––––––––– variables ––––––––––––––––––––––––––––––––––––––––––––––––
temp
.equ
0060h
r_ptr
.equ
0061
iosr_stat
.equ
0062h
DACa_ptr
.equ
0063h
DACb_ptr
.equ
0064h
DACc_ptr
.equ
0065h
DACd_ptr
.equ
0066h
;––––––––– constants –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; DAC control bits to be OR’ed onto data
; all fast mode
DACa_control
.equ
01000h
DACb_control
.equ
05000h
DACc_control
.equ
09000h
DACd_control
.equ
0d000h
;––––––––––– tables –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
.ds
02000h
sinevals
.word
00800h
.word
0097Ch
.word
00AE9h
.word
00C3Ah
.word
00D61h
.word
00E53h
.word
00F07h
.word
00F76h
.word
00F9Ch
.word
00F76h
.word
00F07h
.word
00E53h
.word
00D61h
.word
00C3Ah
POST OFFICE BOX 655303
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15
TLV5604
2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS176B – DECEMBER 1997 – REVISED JULY 2002
APPLICATION INFORMATION
.word
00AE9h
.word
0097Ch
.word
00800h
.word
00684h
.word
00517h
.word
003C6h
.word
0029Fh
.word
001ADh
.word
000F9h
.word
0008Ah
.word
00064h
.word
0008Ah
.word
000F9h
.word
001ADh
.word
0029Fh
.word
003C6h
.word
00517h
.word
00684h
.word
00800h
.word
0097Ch
.word
00AE9h
.word
00C3Ah
.word
00D61h
.word
00E53h
.word
00F07h
.word
00F76h
.word
00F9Ch
.word
00F76h
.word
00F07h
.word
00E53h
.word
00D61h
.word
00C3Ah
.word
00AE9h
.word
0097Ch
.word
00800h
.word
00684h
.word
00517h
.word
003C6h
.word
0029Fh
.word
001ADh
.word
000F9h
.word
0008Ah
.word
00064h
.word
0008Ah
.word
000F9h
.word
001ADh
.word
0029Fh
.word
003C6h
.word
00517h
.word
00684h
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; Main Program
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
.ps
1000h
.entry
start
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; disable interrupts
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
setc
INTM
; disable maskable interrupts
splk
#0ffffh, IFR ; clear all interrupts
splk
#0004h, IMR
; timer interrupts unmasked
16
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TLV5604
2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS176B – DECEMBER 1997 – REVISED JULY 2002
APPLICATION INFORMATION
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; set up the timer
; timer period set by values in PRD and TDDR
; period = (CLKOUT1 period) × (1+PRD) × (1+TDDR)
; examples for TMS320C203 with 40 MHz main clock
; Timer rate
TDDR
PRD
;
80 kHz
9
24 (18h)
;
50 kHz
9
39 (27h)
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
prd_val.equ
tcr_val.equ
0018h
0029h
splk
#0000h, temp
; clear timer
out
temp, TIM
splk
#prd_val, temp
; set PRD
out
temp, PRD
splk
#tcr_val, temp
; set TDDR, and TRB=1 for auto-reload
out
temp, TCR
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; Configure IO0/1 as outputs to be :
; IO0 CS
– and set high
; IO1 LDAC
– and set high
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
in
temp, ASPCR
; configure as output
lacl
temp
or
#0003h
sacl
temp
out
temp, ASPCR
in
temp, IOSR
; set them high
lacl
temp
or
#0003h
sacl
temp
out
temp, IOSR
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; set up serial port for
; SSPCR.TXM=1
Transmit mode – generate FSX
; SSPCR.MCM=1
Clock mode – internal clock source
; SSPCR.FSM=1
Burst mode
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
splk
#0000Eh, temp
out
temp, SSPCR
; reset transmitter
splk
#0002Eh, temp
out
temp, SSPCR
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; reset the rolling pointer
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
lacl
#000h
sacl r_ptr
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; enable interrupts
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
clrc
INTM
; enable maskable interrupts
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; loop forever!
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
next
idle
;wait for interrupt
b
next
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; all else fails stop here
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
done
b
done
;hang there
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17
TLV5604
2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS176B – DECEMBER 1997 – REVISED JULY 2002
APPLICATION INFORMATION
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; Interrupt Service Routines
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
int1
ret
; do nothing and return
int23
ret
; do nothing and return
timer_isr:
in
iosr_stat, IOSR ; store IOSR value into variable space
lacl
iosr_stat
; load acc with iosr status
and
#0FFFDh
; reset IO1 – LDAC low
sacl
temp
;
out
temp, IOSR ;
or
sacl
out
and
sacl
out
lacl
add
sacl
add
sacl
add
sacl
add
sacl
mar
#0002h
temp
temp, IOSR
#0FFFEh
temp
temp, IOSR
r_ptr
#sinevals
DACa_ptr
#08h
DACc_ptr
#08h
DACb_ptr
#08h
DACd_ptr
*,ar0
; set IO1 – LDAC high
;
;
; reset IO0 – CS low
;
;
; load rolling pointer to accumulator
; add pointer to table start
; to get a pointer for next DAC a sample
; add 8 to get to DAC C pointer
; add 8 to get to DAC B pointer
; add 8 to get to DAC D pointer
; set ar0 as current AR
; DAC A
lar
ar0, DACa_ptr ; ar0 points to DAC a sample
lacl
*
; get DAC a sample into accumulator
or
#DACa_control ; OR in DAC A control bits
sacl
temp
;
out
temp, SDTR
; send data
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; We must wait for transmission to complete before writing next word to the SDTR.
; TLV5604 interface does not allow the use of burst mode with the full packet rate, as
; we need a CLKX –ve edge to clock in last bit before FS goes high again, to allow SPI
; compatibility.
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
rpt
#016h
; wait long enough for this configuration
nop
; of MCLK/CLKOUT1 rate
; DAC B
lar
lacl
or
sacl
out
rpt
nop
18
ar0, DACb_ptr ;
*
;
#DACb_control ;
temp
;
temp, SDTR
;
#016h
;
;
ar0 points to DAC a sample
get DAC a sample into accumulator
OR in DAC B control bits
send data
wait long enough for this configuration
of MCLK/CLKOUT1 rate
POST OFFICE BOX 655303
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TLV5604
2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS176B – DECEMBER 1997 – REVISED JULY 2002
APPLICATION INFORMATION
; DAC C
lar
lacl
or
sacl
out
rpt
nop
ar0, DACc_ptr ;
*
;
#DACc_control ;
temp
;
temp, SDTR
;
#016h
;
;
ar0 points to DAC a sample
get DAC a sample into accumulator
OR in DAC C control bits
send data
wait long enough for this configuration
of MCLK/CLKOUT1 rate
; DAC D
lar
ar0, DACd_ptr ; ar0 points to DAC a sample
lacl
*
; get DAC a sample into accumulator
or
#DACd_control ; OR in DAC D control bits
sacl
temp
;
out
temp, SDTR
; send data
lacl
r_ptr
; load rolling pointer to accumulator
add
#1h
; increment rolling pointer
and
#001Fh
; count 0–31 then wrap back round
sacl
r_ptr
; store rolling pointer
rpt
#016h
; wait long enough for this configuration
nop
; of MCLK/CLKOUT1 rate
; now take CS high again
lacl
iosr_stat
; load acc with iosr status
or
#0001h
; set IO0 – CS high
sacl
temp
;
out
temp, IOSR
;
clrc
intm
; re-enable interrupts
ret
; return from interrupt
.end
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19
TLV5604
2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS176B – DECEMBER 1997 – REVISED JULY 2002
APPLICATION INFORMATION
TLV5604 interfaced to MCS51 microcontroller
hardware interfacing
Figure 18 shows an example of how to connect the TLV5604 to an MCS51 Microcontroller. The serial DAC
input data and external control signals are sent via I/O Port 3 of the controller. The serial data is sent on the RxD
line, with the serial clock output on the TxD line. Port 3 bits 3, 4, and 5 are configured as outputs to provide the
DAC latch update (LDAC), chip select (CS) and frame sync (FS) signals for the TLV5604. The active low power
down pin (PD) of the TLV5604 is pulled high to ensure that the DACs are enabled.
MCS®51
TLV5604
RxD
SDIN
TxD
SCLK
P3.3
LDAC
P3.4
CS
P3.4
FS
VDD
PD
VOUTA
VOUTB
REF
REFINAB
VOUTC
REFINCD
VOUTD
VSS
Figure 18. TLV5604 Interfaced with MCS51
software
The example is the same as for the TMS320C203 in this datasheet, but adapted for a MCS51 controller. It
generates a differential in-phase (sine) signal between the VOUTA and VOUTB pins, and it’s quadrature
(cosine) signal as the differential signal between VOUTC and VOUTD.
The on-chip timer is used to generate interrupts at a fixed frequency. The related interrupt service routine pulses
LDAC low to update all 4 DACs simultaneously, then fetches and writes the next sample to all 4 DACs. The
samples are stored as a look-up table, which describes one full period of a sine wave.
The serial port of the controller is used in Mode 0, which transmits 8 bits of data on RxD, accompanied by a
synchronous clock on TxD. Two writes concatenated together are required to write a complete word to the
TLV5604. The CS and FS signals are provided in the required fashion through control of IO port 3, which has
bit addressable outputs.
MCS is a registered trademark of Intel Corporation.
20
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• DALLAS, TEXAS 75265
TLV5604
2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS176B – DECEMBER 1997 – REVISED JULY 2002
APPLICATION INFORMATION
;––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; Processor: 80C51
;
; Description:
;
; This program generates a differential in–phase (sine) on (OUTA–OUTB) and it’s
; quadrature (cosine) as a differential signal on (OUTC–OUTD).
; 1998, Texas Instruments Incorporated
;––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
NAME
GENIQ
MAIN
SEGMENT
CODE
ISR
SEGMENT
CODE
SINTBL
SEGMENT
CODE
VAR1
SEGMENT
DATA
STACK
SEGMENT
IDATA
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; Code start at address 0, jump to start
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
CSEG
AT 0
LJMP
start
; Execution starts at address 0 on power–up.
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; Code in the timer0 interrupt vector
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
CSEG
AT 0BH
LJMP
timer0isr ; Jump vector for timer 0 interrupt is 000Bh
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; Global variables need space allocated
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
RSEG
VAR1
Temp_ptr:
DS
1
rolling_ptr:
DS
1
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; Interrupt service routine for timer 0 interrupts
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
RSEG
ISR
timer0isr:
PUSH
PSW
PUSH
ACC
CLR
SETB
;
;
;
;
;
INT1
INT1
; pulse LDAC low
; to latch all 4 previous values at the same time
; 1st thing done in timer isr => fixed period
CLR
T0
; set CS low
The signal to be output on each DAC is a sine function.
One cycle of a sine wave is held in a table @ sinevals as 32 samples of msb,
lsb pairs (64 bytes). We have one pointer which rolls round this table,
rolling_ptr, incrementing by 2 bytes (1 sample) on each interrupt (at the end of
this routine).
; The
; DAC
; A
; B
; C
; D
MOV
MOV
MOV
MOVC
CLR
MOV
INC
MOV
MOVC
DAC samples are read at an offset to this rolling pointer:
Function Offset from rolling_ptr
sine
0
inverse sine
32
cosine
16
inverse cosine
48
DPTR,#sinevals
; set DPTR to the start of the table of sine signal values
R7,rolling_ptr
; R7 holds the pointer into the sine table
A,R7
; get DAC A msb
A,@A+DPTR
; msb of DAC A is in the ACC
T1
; transmit it – set FS low
SBUF,A
; send it out the serial port
R7
; increment the pointer in R7
A,R7
; to get the next byte from the table
A,@A+DPTR
; which is the lsb of this sample, now in ACC
POST OFFICE BOX 655303
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21
TLV5604
2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS176B – DECEMBER 1997 – REVISED JULY 2002
APPLICATION INFORMATION
A_MSB_TX:
JNB
TI,A_MSB_TX
CLR
TI
MOV
SBUF,A
; wait for transmit to complete
; clear for new transmit
; and send out the lsb of DAC A
; DAC C next
; DAC C codes should be taken from 16 bytes (8 samples) further on in the sine table
; – this gives a cosine function
MOV
A,R7
; pointer in R7
ADD
A,#0FH
; add 15 – already done one INC
ANL
A,#03FH
; wrap back round to 0 if > 64
MOV
R7,A
; pointer back in R7
MOVC
ORL
A_LSB_TX:
JNB
SETB
CLR
CLR
MOV
INC
MOV
MOVC
A,@A+DPTR
A,#01H
; get DAC C msb from the table
; set control bits to DAC C address
TI,A_LSB_TX
T1
T1
TI
SBUF,A
; wait for DAC A lsb transmit to complete
; toggle FS
; clear for new transmit
; and send out the msb of DAC C
R7
A,R7
A,@A+DPTR
; increment the pointer in R7
; to get the next byte from the table
; which is the lsb of this sample, now in ACC
C_MSB_TX:
JNB
TI,C_MSB_TX
CLR
TI
MOV
SBUF,A
; wait for transmit to complete
; clear for new transmit
; and send out the lsb of DAC C
; DAC B next
; DAC B codes should be taken from 16 bytes (8 samples) further on
; in the sine table – this gives an inverted sine function
MOV
A,R7
; pointer in R7
ADD
A,#0FH
; add 15 – already done one INC
ANL
A,#03FH
; wrap back round to 0 if > 64
MOV
R7,A
; pointer back in R7
MOVC
ORL
C_LSB_TX:
JNB
SETB
CLR
CLR
MOV
INC
MOV
MOVC
A,@A+DPTR
A,#02H
TI,C_LSB_TX
T1
T1
TI
SBUF,A
R7
A,R7
A,@A+DPTR
B_MSB_TX:
JNB
TI,B_MSB_TX
CLR
TI
MOV
SBUF,A
22
; get DAC B msb from the table
; set control bits to DAC B address
; wait for DAC C lsb transmit to complete
; toggle FS
;
;
;
;
;
;
clear for new transmit
and send out the msb of DAC B
get DAC B LSB
increment the pointer in R7
to get the next byte from the table
which is the lsb of this sample, now in ACC
; wait for transmit to complete
; clear for new transmit
; and send out the lsb of DAC B
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TLV5604
2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS176B – DECEMBER 1997 – REVISED JULY 2002
APPLICATION INFORMATION
; DAC D next
; DAC D codes should be taken from 16 bytes (8 samples) further on in the sine table
; – this gives an inverted cosine function
MOV
A,R7
; pointer in R7
ADD
A,#0FH
; add 15 – already done one INC
ANL
A,#03FH
; wrap back round to 0 if > 64
MOV
R7,A
; pointer back in R7
MOVC
ORL
B_LSB_TX:
JNB
SETB
CLR
CLR
MOV
INC
MOV
MOVC
A,@A+DPTR
A,#03H
; get DAC D msb from the table
; set control bits to DAC D address
TI,B_LSB_TX
T1
T1
TI
SBUF,A
; wait for DAC B lsb transmit to complete
; toggle FS
R7
A,R7
A,@A+DPTR
; increment the pointer in R7
; to get the next byte from the table
; which is the lsb of this sample, now in ACC
D_MSB_TX:
JNB
TI,D_MSB_TX
CLR
TI
MOV
SBUF,A
; clear for new transmit
; and send out the msb of DAC D
; wait for transmit to complete
; clear for new transmit
; and send out the lsb of DAC D
; increment the rolling pointer to point to the next sample
; ready for the next interrupt
MOV
A,rolling_ptr
ADD
A,#02H
; add 2 to the rolling pointer
ANL
A,#03FH
; wrap back round to 0 if > 64
MOV
rolling_ptr,A
; store in memory again
D_LSB_TX:
JNB TI,D_LSB_TX
CLR
TI
SETB
SETB
POP
POP
T1
T0
ACC
PSW
; wait for DAC D lsb transmit to complete
; clear for next transmit
; FS high
; CS high
RETI
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; Stack needs definition
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
RSEG
STACK
DS
10h
; 16 Byte Stack!
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
23
TLV5604
2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS176B – DECEMBER 1997 – REVISED JULY 2002
APPLICATION INFORMATION
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; Main program code
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
RSEG
MAIN
start:
MOV
SP,#STACK–1
; first set Stack Pointer
CLR
MOV
MOV
MOV
A
SCON,A
TMOD,#02H
TH0,#038H
; set serial port 0 to mode 0
; set timer 0 to mode 2 – auto-reload
; set TH0 for 5 kHs interrupts
SETB
SETB
SETB
INT1
T1
T0
; set LDAC = 1
; set FS = 1
; set CS = 1
SETB
SETB
ET0
EA
; enable timer 0 interrupts
; enable all interrupts
MOV
SETB
rolling_ptr,A
TR0
; set rolling pointer to 0
; start timer 0
always:
JMP always
; while(1) !
RET
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; Table of 32 sine wave samples used as DAC data
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
RSEG
SINTBL
sinevals:
DW
01000H
DW
0903EH
DW
05097H
DW
0305CH
DW
0B086H
DW
070CAH
DW
0F0E0H
DW
0F06EH
DW
0F039H
DW
0F06EH
DW
0F0E0H
DW
070CAH
DW
0B086H
DW
0305CH
DW
05097H
DW
0903EH
DW
01000H
DW
06021H
DW
0A0E8H
DW
0C063H
DW
040F9H
DW
080B5H
DW
0009FH
DW
00051H
DW
00026H
DW
00051H
DW
0009FH
DW
080B5H
DW
040F9H
DW
0C063H
DW
0A0E8H
DW
06021H
END
24
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TLV5604
2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS176B – DECEMBER 1997 – REVISED JULY 2002
MECHANICAL DATA
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
0.050 (1,27)
0.020 (0,51)
0.014 (0,35)
14
0.010 (0,25) M
8
0.008 (0,20) NOM
0.244 (6,20)
0.228 (5,80)
0.157 (4,00)
0.150 (3,81)
Gage Plane
0.010 (0,25)
1
7
0°– 8°
A
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.069 (1,75) MAX
0.010 (0,25)
0.004 (0,10)
PINS **
0.004 (0,10)
8
14
16
A MAX
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
A MIN
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
DIM
4040047 / D 10/96
NOTES: A.
B.
C.
D.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
Falls within JEDEC MS-012
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
25
TLV5604
2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS176B – DECEMBER 1997 – REVISED JULY 2002
MECHANICAL DATA
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
0,75
0,50
A
Seating Plane
0,15
0,05
1,20 MAX
0,10
PINS **
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064 / E 08/96
NOTES: A.
B.
C.
D.
26
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
13-Aug-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TLV5604CD
ACTIVE
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TLV5604C
TLV5604CDG4
ACTIVE
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TLV5604C
TLV5604CDR
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TLV5604C
TLV5604CPW
ACTIVE
TSSOP
PW
16
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TV5604
TLV5604CPWR
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TV5604
TLV5604CPWRG4
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TV5604
TLV5604ID
ACTIVE
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TLV5604I
TLV5604IPW
ACTIVE
TSSOP
PW
16
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TY5604
TLV5604IPWR
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TY5604
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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