TLV5626IDG4

TLV5626 2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN SLAS236A –JUNE 1999 – REVISED JUNE 2000 features D D D D D D D PACKAGE (TOP VIEW) Dual 8-Bit Voltage Output DAC Programmable Internal Reference Programmable Settling Time: 0.8 µs in Fast Mode , 2.8 µs in Slow Mode Compatible With TMS320 and SPI Serial Ports Differential Nonlinearity 4.75 V MIN TYP MAX UNIT 1.003 1.024 1.045 V 2.027 2.048 2.069 1 Output sink current –1 mA Load capacitance PSRR 100 Power supply rejection ratio V mA –65 pF dB reference pin configured as input (REF) PARAMETER VI RI Input voltage CI Input capacitance TEST CONDITIONS MIN TYP 0 VDD–1.5 Input resistance Reference input bandwidth REF = 0 0.2 2 Vpp + 1.024 1 024 V dc Reference feedthrough REF = 1 Vpp at 1 kHz + 1.024 V dc (see Note 10) MAX UNIT V 10 MΩ 5 pF Fast 1.3 MHz Slow 525 kHz – 80 dB NOTE 10: Reference feedthrough is measured at the DAC output with an input code = 0x000. digital inputs PARAMETER IIH IIL High-level digital input current Ci Input capacitance TEST CONDITIONS VI = VDD VI = 0 V Low-level digital input current MIN TYP MAX 1 UNIT µA µA –1 8 pF analog output dynamic performance PARAMETER TEST CONDITIONS CL = 100 pF,, TYP MAX Fast MIN 0.8 2.4 Slow 2.8 5.5 Fast 0.4 1.2 Slow 0.8 1.6 Fast 12 Slow 1.8 ts(FS) (FS) time full scale Output settling time, RL = 10 kΩ,, See Note 11 ts(CC) (CC) Output settling time, time code to code RL = 10 kΩ,, See Note 12 CL = 100 pF,, SR Slew rate RL = 10 kΩ,, See Note 13 CL = 100 pF,, Glitch energy DIN = 0 to 1, CS = VDD fCLK = 100 kHz, Signal-to-noise ratio 53 57 S/(N+D) Signal-to-noise + distortion 48 47 THD Total harmonic distortion SFDR Spurious free dynamic range fs = 480 kSPS,, fout = 1 kHz,, RL = 10 kΩ, CL = 100 pF –50 50 µs µs V/µs 5 SNR UNIT nV–S –48 dB 62 NOTES: 11. Settling time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code change of 0x020 to 0xFD0 or 0xFD0 to 0x020 respectively. Not tested, assured by design. 12. Settling time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code change of one count. Not tested, assured by design. 13. Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 TLV5626 2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN SLAS236A –JUNE 1999 – REVISED JUNE 2000 digital input timing requirements MIN NOM MAX UNIT tsu(CS–CK) tsu(C16-CS) Setup time, CS low before first negative SCLK edge Setup time, 16th negative SCLK edge (when D0 is sampled) before CS rising edge 10 ns 10 ns twH twL SCLK pulse width high 25 ns SCLK pulse width low 25 ns tsu(D) th(D) Setup time, data ready before SCLK falling edge 10 ns Hold time, data held valid after SCLK falling edge 5 ns PARAMETER MEASUREMENT INFORMATION twL SCLK X 1 2 tsu(D) DIN X twH 3 4 5 15 X 16 th(D) D15 D14 D13 D12 D1 D0 X tsu(C16-CS) tsu(CS-CK) CS Figure 1. Timing Diagram 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLV5626 2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN SLAS236A –JUNE 1999 – REVISED JUNE 2000 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs FREE-AIR TEMPERATURE SUPPLY CURRENT vs FREE-AIR TEMPERATURE 4.5 4.5 4 Fast Mode I DD – Supply Current – mA I DD – Supply Current – mA 4 3.5 3 2.5 2 Slow Mode 1.5 Fast Mode 3.5 3 2.5 2 Slow Mode 1.5 VDD = 5 V Vref = Int. 2 V Input Code = 1023 (Both DACs) 1 VDD = 3 V Vref = Int. 1 V Input Code = 1023 (Both DACs) 1 0.5 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 TA – Free-Air Temperature – °C 0.5 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 TA – Free-Air Temperature – °C Figure 2 Figure 3 POWER DOWN SUPPLY CURRENT vs TIME OUTPUT VOLTAGE vs LOAD CURRENT 2.064 2.4 VDD = 3 V Vref = Int. 1 V Input Code = 4095 Fast Mode 2.2 2.062 2 VO – Output Voltage – V I DD – Power Down Supply Current – mA 2.6 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 2.06 Slow Mode 2.058 2.056 2.054 2.052 0.2 0 0 10 20 50 30 40 t – Time – µs 60 70 80 2.05 0 0.5 1 1.5 2 2.5 3 3.5 4 Source Current – mA Figure 4 Figure 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 TLV5626 2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN SLAS236A –JUNE 1999 – REVISED JUNE 2000 TYPICAL CHARACTERISTICS OUTPUT VOLTAGE vs LOAD CURRENT OUTPUT VOLTAGE vs LOAD CURRENT 3 4.128 VDD = 5 V Vref = Int. 2 V Input Code = 4095 Fast Mode 2.5 VO – Output Voltage – V VO – Output Voltage – V 4.126 VDD = 3 V Vref = Int. 1 V Input Code = 0 4.124 Slow Mode 4.122 4.12 4.118 Fast Mode 2 1.5 1 0.5 4.116 Slow Mode 0 4.114 0 0.5 1 1.5 2 2.5 3 3.5 0 4 0.5 Figure 6 THD+N – Total Harmonic Distortion and Noise – dB VDD = 5 V Vref = Int. 2 V Input Code = 0 VO – Output Voltage – V 4 3.5 Fast Mode 3 2.5 2 1.5 1 Slow Mode 0 0.5 1 3 3.5 4 1.5 2 2.5 Sink Current – mA 3 3.5 4 0 –10 VDD = 5 V Vref = 1 V dc + 1 V p/p Sinewave Output Full Scale –20 –30 –40 –50 –60 Slow Mode –70 Fast Mode –80 –90 –100 100 1000 10000 f – Frequency – Hz Figure 8 8 2.5 TOTAL HARMONIC DISTORTION AND NOISE vs FREQUENCY 5 0 2 Figure 7 OUTPUT VOLTAGE vs LOAD CURRENT 0.5 1.5 Sink Current – mA Source Current – mA 4.5 1 Figure 9 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 100000 TLV5626 2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN SLAS236A –JUNE 1999 – REVISED JUNE 2000 TYPICAL CHARACTERISTICS TOTAL HARMONIC DISTORTION vs FREQUENCY THD – Total Harmonic Distortion – dB 0 –10 VDD = 5 V Vref = 1 V dc + 1 V p/p Sinewave Output Full Scale –20 –30 –40 –50 –60 –70 Slow Mode –80 Fast Mode –90 –100 100 10000 1000 100000 f – Frequency – Hz Figure 10 DNL – Differential Nonlinearity – LSB DIFFERENTIAL NONLINEARITY vs DIGITAL OUTPUT CODE 0.20 0.15 0.10 0.05 –0.00 –0.05 –0.10 –0.15 –0.2 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 Digital Output Code Figure 11 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 TLV5626 2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN SLAS236A –JUNE 1999 – REVISED JUNE 2000 TYPICAL CHARACTERISTICS INL – Integral Nonlinearity – LSB INTEGRAL NONLINEARITY vs DIGITAL OUTPUT CODE 1.0 0.8 0.6 0.4 0.2 –0.0 –0.2 –0.4 –0.6 –0.8 –1.0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 Digital Output Code Figure 12 APPLICATION INFORMATION general function The TLV5626 is a dual 8-bit, single supply DAC, based on a resistor string architecture. It consists of a serial interface, a speed and power-down control logic, a programmable internal reference, a resistor string, and a rail-to-rail output buffer. The output voltage (full scale determined by reference) is given by: 2 REF CODE [V] 0x1000 Where REF is the reference voltage and CODE is the digital input value in the range 0x000 to 0xFF0.Bits 3 to 0 must be set to zero. A power-on reset initially puts the internal latches to a defined state (all bits zero). serial interface A falling edge of CS starts shifting the data bit-per-bit (starting with the MSB) to the internal register on the falling edges of SCLK. After 16 bits have been transferred or CS rises, the content of the shift register is moved to the target latches (DAC A, DAC B, BUFFER, CONTROL), depending on the control bits within the data word. Figure 13 shows examples of how to connect the TLV5626 to TMS320, SPI, and Microwire. TMS320 DSP FSX DX CLKX TLV5626 CS DIN SCLK SPI I/O MOSI SCK TLV5626 CS DIN SCLK Figure 13. Three-Wire Interface 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Microwire I/O SO SK TLV5626 CS DIN SCLK TLV5626 2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN SLAS236A –JUNE 1999 – REVISED JUNE 2000 APPLICATION INFORMATION Notes on SPI and Microwire: Before the controller starts the data transfer, the software has to generate a falling edge on the I/O pin connected to CS. If the word width is 8 bits (SPI and Microwire), two write operations must be performed to program the TLV5626. After the write operation(s), the holding registers or the control register are updated automatically on the 16th positive clock edge. serial clock frequency and update rate The maximum serial clock frequency is given by: f sclkmax +t )t 1 whmin wlmin + 20 MHz The maximum update rate is: f updatemax + 16 ǒt 1 whmin )t Ǔ+ 1.25 MHz wlmin The maximum update rate is just a theoretical value for the serial interface, as the settling time of the TLV5626 has to be considered, too. data format The 16-bit data word for the TLV5626 consists of two parts: D D Program bits (D15..D12) New data (D11..D0) D15 D14 D13 D12 R1 SPD PWR R0 SPD: Speed control bit PWR: Power control bit D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 12 Data bits 1 → fast mode 1 → power down 0 → slow mode 0 → normal operation The following table lists the possible combination of the register select bits: register select bits R1 R0 REGISTER 0 0 Write data to DAC B and BUFFER 0 1 Write data to BUFFER 1 0 Write data to DAC A and update DAC B with BUFFER content 1 1 Write data to control register The meaning of the 12 data bits depends on the register. If one of the DAC registers or the BUFFER is selected, then the 12 data bits determine the new DAC value: data bits: DAC A, DAC B and BUFFER D11 D10 D9 D8 D7 D6 D5 D4 New DAC Value D3 D2 D1 D0 0 0 0 0 If control is selected, then D1, D0 of the 12 data bits are used to program the reference voltage: POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 TLV5626 2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN SLAS236A –JUNE 1999 – REVISED JUNE 2000 APPLICATION INFORMATION data bits: CONTROL D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X X X X X REF1 REF0 X: don’t care REF1 and REF0 determine the reference source and, if internal reference is selected, the reference voltage. reference bits REF1 REF0 REFERENCE 0 0 External 0 1 1.024 V 1 0 2.048 V 1 1 External CAUTION: If external reference voltage is applied to the REF pin, external reference MUST be selected. examples of operation: D Set DAC A output, select fast mode, select internal reference at 2.048 V: 1. Set reference voltage to 2.048 V (CONTROL register): D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 2. Write new DAC A value and update DAC A output: D15 D14 D13 D12 1 1 0 0 D11 D10 D9 D8 D7 New DAC A output value The DAC A output is updated on the rising clock edge after D0 is sampled. To output data consecutively using the same DAC configuration, it is not necessary to program the CONTROL register again. D Set DAC B output, select fast mode, select external reference: 3. Select external reference (CONTROL register): D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 D4 D3 D2 D1 D0 0 0 0 0 4. Write new DAC B value to BUFFER and update DAC B output: D15 D14 D13 D12 0 1 0 0 D11 D10 D9 D8 D7 D6 D5 New BUFFER content and DAC B output value X = Don’t care The DAC A output is updated on the rising clock edge after D0 is sampled. To output data consecutively using the same DAC configuration, it is not necessary to program the CONTROL register again. 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLV5626 2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN SLAS236A –JUNE 1999 – REVISED JUNE 2000 APPLICATION INFORMATION examples of operation: (continued) D Set DAC A value, set DAC B value, update both simultaneously, select slow mode, select internal reference at 1.024 V: 1. Set reference voltage to 1.024 V (CONTROL register): D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 D3 D2 D1 D0 0 0 0 0 2. Write data for DAC B to BUFFER: D15 D14 D13 D12 0 0 0 1 D11 D10 D9 New DAC B value X = Don’t care 3. Write new DAC A value and update DAC A and B simultaneously: D15 D14 D13 D12 1 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 New DAC A value X = Don’t care Both outputs are updated on the rising clock edge after D0 from the DAC A data word is sampled. D Set power-down mode: D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X 1 X X X X X X X X X X X X X X = Don’t care linearity, offset, and gain error using single ended supplies When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. With a positive offset, the output voltage changes on the first code change. With a negative offset, the output voltage may not change with the first code, depending on the magnitude of the offset voltage. The output amplifier attempts to drive the output to a negative voltage. However, because the most negative supply rail is ground, the output cannot drive below ground and clamps the output at 0 V. The output voltage then remains at zero until the input code value produces a sufficient positive output voltage to overcome the negative offset voltage, resulting in the transfer function shown in Figure 14. Output Voltage 0V DAC Code Negative Offset Figure 14. Effect of Negative Offset (single supply) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 TLV5626 2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN SLAS236A –JUNE 1999 – REVISED JUNE 2000 APPLICATION INFORMATION This offset error, not the linearity error, produces this breakpoint. The transfer function would have followed the dotted line if the output buffer could drive below the ground rail. For a DAC, linearity is measured between zero-input code (all inputs 0) and full-scale code (all inputs 1) after offset and full scale are adjusted out or accounted for in some way. However, single supply operation does not allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity is measured between full-scale code and the lowest code that produces a positive output voltage. definitions of specifications and terminology integral nonlinearity (INL) The relative accuracy or integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale errors. differential nonlinearity (DNL) The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code. zero-scale error (EZS) Zero-scale error is defined as the deviation of the output from 0 V at a digital input value of 0. gain error (EG) Gain error is the error in slope of the DAC transfer function. signal-to-noise ratio + distortion (S/N+D) S/N+D is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for S/N+D is expressed in decibels. spurious free dynamic range (SFDR) Spurious free dynamic range is the difference between the rms value of the output signal and the rms value of the spurious signal within a specified bandwidth. The value for SFDR is expressed in decibels. 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLV5626 2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN SLAS236A –JUNE 1999 – REVISED JUNE 2000 MECHANICAL DATA D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0.050 (1,27) 0.020 (0,51) 0.014 (0,35) 14 0.010 (0,25) M 8 0.008 (0,20) NOM 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81) Gage Plane 0.010 (0,25) 1 7 0°– 8° A 0.044 (1,12) 0.016 (0,40) Seating Plane 0.069 (1,75) MAX 0.010 (0,25) 0.004 (0,10) PINS ** 0.004 (0,10) 8 14 16 A MAX 0.197 (5,00) 0.344 (8,75) 0.394 (10,00) A MIN 0.189 (4,80) 0.337 (8,55) 0.386 (9,80) DIM 4040047 / D 10/96 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). Falls within JEDEC MS-012 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) TLV5626CD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TV5626 Samples TLV5626CDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TV5626 Samples TLV5626ID ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TY5626 Samples TLV5626IDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TY5626 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of