TLV5627CPWR


 
 
  

   
 
     SLAS232A − JUNE1999 − REVISED JULY 2002 D Four 8-Bit D/A Converters D Programmable Settling Time of 2.5 µs or 8.5 µs Typ D TMS320, (Q)SPI, and Microwire D D D D Compatible Serial Interface Low Power Consumption: 7 mW, Slow Mode − 5-V Supply 3 mW, Slow Mode − 3-V Supply Reference Input Buffers Monotonic Over Temperature Dual 2.7-V to 5.5-V Supply (Separate Digital and Analog Supplies) D Hardware Power Down D Software Power Down D Simultaneous Update applications D D D D D Battery Powered Test Instruments Digital Offset and Gain Adjustment Industrial Process Controls Machine and Motion Control Devices Arbitrary Waveform Generation D OR PW PACKAGE (TOP VIEW) description The TLV5627 is a four channel, 8-bit voltage output digital-to-analog converter (DAC) with a flexible 4-wire serial interface. The 4-wire serial interface allows glueless interface to TMS320, SPI, QSPI, and Microwire serial ports. The TLV5627 is programmed with a 16-bit serial word comprised of a DAC address, individual DAC control bits, and an 8-bit DAC value. DVDD PD LDAC DIN SCLK CS FS DGND 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 AVDD REFINAB OUTA OUTB OUTC OUTD REFINCD AGND The device has provision for two supplies: one digital supply for the serial interface (via pins DVDD and DGND), and one for the DACs, reference buffers and output buffers (via pins AVDD and AGND). Each supply is independent of the other, and can be any value between 2.7 V and 5.5 V. The dual supplies allow a typical application where the DAC will be controlled via a microprocessor operating on a 3-V supply (also used on pins DVDD and DGND), with the DACs operating on a 5-V supply. The digital and analog supplies can be tied together. The resistor string output voltage is buffered by an x2 gain rail-to-rail output buffer. The buffer features a Class AB output stage to improve stability and reduce settling time. A rail-to-rail output stage and a power-down mode make it ideal for single voltage, battery based applications. The settling time of the DAC is programmable to allow the designer to optimize speed versus power dissipation. The settling time is chosen by the control bits within the 16-bit serial input string. A high-impedance buffer is integrated on the REFINAB and REFINCD terminals to reduce the need for a low source impedance drive to the terminal. REFINAB and REFINCD allow DACs A and B to have a different reference voltage than DACs C and D. The device, implemented with a CMOS process, is available in 16-terminal SOIC and TSSOP packages. The TLV5627C is characterized for operation from 0°C to 70°C. The TLV5627I is characterized for operation from −40°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SPI and QSPI are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor Corporation. Copyright  2002, Texas Instruments Incorporated  
 
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     SLAS232A − JUNE1999 − REVISED JULY 2002 AVAILABLE OPTIONS PACKAGE TA SOIC (D) TSSOP (PW) 0°C to 70°C TLV5627CD TLV5627CPW −40°C to 85°C TLV5627ID TLV5627IPW functional block diagram AVDD 15 REFINAB DVDD 16 1 DAC A + _ Power-On Reset DIN 4 Serial Input Register 10 2 10-Bit Data and Control Register 7 FS 5 SCLK CS 6 14 x2 8 8-Bit DAC Latch 2 2-Bit Control Data Latch DAC Select/ Control Logic OUTA 8 2 Power Down/ Speed Control 13 DAC B OUTB DAC C 12 OUTC DAC D 11 OUTD REFINCD 3 9 AGND 2 2 8 DGND LDAC POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PD 

 
 
  

   
 
     SLAS232A − JUNE1999 − REVISED JULY 2002 Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION AGND 9 AVDD CS 16 DGND 8 DIN 4 DVDD 1 FS 7 I Frame sync input. The falling edge of the frame sync pulse indicates the start of a serial data frame shifted out to the TLV5627. PD 2 I Power-down pin. Powers down all DACs (overriding their individual power down settings), and all output stages. This terminal is active low. LDAC 3 I Load DAC. When the LDAC signal is high, no DAC output updates occur when the input digital data is read into the serial interface. The DAC outputs are only updated when LDAC is low. REFINAB 15 I Voltage reference input for DACs A and B. REFINCD 10 I Voltage reference input for DACs C and D. 6 Analog ground Analog supply I Chip select. This terminal is active low. Digital ground I Serial data input Digital supply SCLK 5 I Serial clock input OUTA 14 O DAC A output OUTB 13 O DAC B output OUTC 12 O DAC C output OUTD 11 O DAC D output absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, (DVDD, AVDD to GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Supply voltage difference, (AVDD to DVDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −2.8 V to 2.8 V Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to DVDD + 0.3 V Reference input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to AVDD + 0.3 V Operating free-air temperature range, TA: TLV5627C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C TLV5627I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 

 
 
  

   
 
     SLAS232A − JUNE1999 − REVISED JULY 2002 recommended operating conditions Supply voltage, AVDD, DVDD High-level digital input voltage, VIH Low-level digital input voltage, VIL Reference voltage, Vref to REFINAB, REFINCD terminal MIN NOM 5-V supply 4.5 5 5.5 3-V supply 2.7 3 3.3 DVDD = 2.7 V 2 DVDD = 5.5 V 2.4 MAX UNIT V V DVDD = 2.7 V 0.6 DVDD = 5.5 V 1 5-V supply (see Note 1) 0 2.048 3-V supply (see Note 1) 0 1.024 2 10 Load resistance, RL AVDD−1.5 AVDD−1.5 V V kΩ Load capacitance, CL 100 pF Serial clock rate, SCLK 20 MHz Operating free-air temperature TLV5627C 0 70 TLV5627I −40 85 °C NOTE 1: Voltages greater than AVDD/2 will cause output saturation for large DAC codes. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) static DAC specifications PARAMETER TEST CONDITIONS Resolution EZS EG MIN TYP MAX 8 UNIT bits Integral nonlinearity (INL), end point adjusted See Note 2 ±0.3 ±0.5 LSB Differential nonlinearity (DNL) See Note 3 ±0.03 ±0.5 LSB Zero scale error (offset error at zero scale) See Note 4 Zero scale error temperature coefficient See Note 5 Gain error See Note 6 Gain error temperature coefficient See Note 7 ±10 10 ±0.6 10 mV ppm/°C %of FS voltage ppm/°C NOTES: 2. The relative accuracy or integral nonlinearity (INL) sometimes referred to as linearity error, is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale errors. 3. The differential nonlinearity (DNL) sometimes referred to as differential error, is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code. 4. Zero-scale error is the deviation from zero voltage output when the digital input code is zero. 5. Zero-scale-error temperature coefficient is given by: EZS TC = [EZS (Tmax) − EZS (Tmin)]/Vref × 106/(Tmax − Tmin). 6. Gain error is the deviation from the ideal output (2Vref − 1 LSB) with an output load of 10 kΩ excluding the effects of the zero-error. 7. Gain temperature coefficient is given by: EG TC = [EG(Tmax) − EG (Tmin)]/Vref × 106/(Tmax − Tmin). 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 

 
 
  

   
 
     SLAS232A − JUNE1999 − REVISED JULY 2002 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued) individual DAC output specifications PARAMETER VO TEST CONDITIONS Voltage output RL = 10 kΩ Output load regulation accuracy RL = 2 kΩ vs 10 kΩ MIN TYP 0 MAX AVDD−0.4 0.1 UNIT V 0.25 % of FS voltage MAX UNIT reference input (REFINAB, REFINCD) PARAMETER VI RI Input voltage range CI Input capacitance TEST CONDITIONS MIN See Note 8 TYP 0 AVDD−1.5 Input resistance Reference feed through REFIN = 1 Vpp at 1 kHz + 1.024 V dc (see Note 9) Reference input bandwidth REFIN = 0.2 Vpp + 1.024 V dc V 10 MΩ 5 pF −75 dB Slow 0.5 Fast 1 MHz NOTES: 8. Reference input voltages greater than VDD/2 will cause output saturation for large DAC codes. 9. Reference feedthrough is measured at the DAC output with an input code = 000 hex and a Vref(REFINAB or REFINCD) input = 1.024 Vdc + 1 Vpp at 1 kHz. digital inputs (D0−D11, CS, WEB, LDAC, PD) PARAMETER IIH IIL High-level digital input current CI Input capacitance TEST CONDITIONS MIN TYP VI = DVDD VI = 0 V Low-level digital input current MAX UNIT ±1 µA ±1 µA 3 pF power supply PARAMETER TEST CONDITIONS 5-V supply, No load, Clock running IDD Power supply current 3-V supply, No load, Clock running Power down supply current, See Figure 12 Power supply rejection ratio Gain MIN MAX 1.4 2.2 Fast 3.5 5.5 Slow 1 1.5 Fast 3 4.5 1 Zero scale gain PSRR TYP Slow UNIT mA mA µA −68 See Notes 10 and 11 −68 dB 10. Zero-scale-error rejection ratio (EZS−RR) is measured by varying the AVDD from 5 ±0.5 V and 3 ±0.3 V dc, and measuring the proportion of this signal imposed on the zero-code output voltage. 11. Gain-error rejection ratio (EG-RR) is measured by varying the AVDD from 5 ±0.5 V and 3 ±0.3 V dc and measuring the proportion of this signal imposed on the full-scale output voltage after subtracting the zero scale change. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 

 
 
  

   
 
     SLAS232A − JUNE1999 − REVISED JULY 2002 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued) analog output dynamic performance PARAMETER SR TEST CONDITIONS CL = 100 pF, RL = 10 kΩ, VO = 10% to 90%, Vref = 2.048 V, 1024 V Output slew rate ts Output settling time To ± 0.1 LSB, CL = 100 pF, RL = 10 kΩ, See Notes 12 and 14 ts(c) Output settling time, code to code To ± 0.1 LSB, CL = 100 pF, RL = 10 kΩ, See Notes 13 and 14 Glitch energy Code transition from 7F0 to 800 SNR Signal-to-noise ratio S/(N+D) Signal to noise + distortion THD Total harmonic distortion SFDR Spurious free dynamic range MIN Fast TYP MAX 5 UNIT V/µs Slow 1 Fast 2.5 4 V/µs Slow 8.5 18 Fast 1 Slow 2 µss µss 10 nV-sec 57 Sinewave generated by DAC, Reference voltage = 1.024 at 3 V and 2.048 at 5 V, fs = 400 KSPS, fOUT = 1.1 kHz sinewave, CL = 100 pF, RL = 10 kΩ, BW = 20 kHz 49 dB −50 60 NOTES: 12. Settling time is the time for the output signal to remain within ± 0.1 LSB of the final measured value for a digital input code change of 0x020 to 0xFF0 or 0xFF0 to 0x020. 13. Settling time is the time for the output signal to remain within ± 0.1 LSB of the final measured value for a digital input code change of one count. 14. Limits are ensured by design and characterization, but are not production tested. digital input timing requirements MIN tsu(CS−FS) tsu(FS−CK) Setup time, CS low before FS↓ MAX UNIT ns 8 ns tsu(C16−FS) Setup time, sixteenth negative SCLK edge after FS low on which bit D0 is sampled before rising edge of FS 10 ns tsu(C16−CS) Setup time. The first positive SCLK edge after D0 is sampled before CS rising edge. If FS is used instead of the SCLK positive edge to update the DAC, then the setup time is between the FS rising edge and CS rising edge. 10 ns twH twL Pulse duration, SCLK high 25 ns Pulse duration, SCLK low 25 ns tsu(D) Setup time, data ready before SCLK falling edge 8 ns th(D) twH(FS) Hold time, data held valid after SCLK falling edge 5 ns 20 ns 6 Setup time, FS low before first negative SCLK edge NOM 10 Pulse duration, FS high POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 

 
 
  

   
 
     SLAS232A − JUNE1999 − REVISED JULY 2002 PARAMETER MEASUREMENT INFORMATION SCLK ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 1 2 tsu(D) DIN twH twL 3 4 5 15 16 th(D) D15 D14 D13 D12 tsu(FS-CK) D1 D0 ÎÎ ÎÎ ÎÎÎ ÎÎÎ tsu(C16-CS) tsu(CS-FS) CS twH(FS) tsu(C16-FS) FS Figure 1. Timing Diagram POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 

 
 
  

   
 
     SLAS232A − JUNE1999 − REVISED JULY 2002 TYPICAL CHARACTERISTICS LOAD REGULATION LOAD REGULATION 0.35 0.20 VDD = 5 V, VREF = 2 V, VO = Full Scale 0.16 VO − Output Voltage − V VO − Output Voltage − V 0.30 VDD = 3 V, VREF = 1 V, VO = Full Scale 0.18 0.25 5 V Slow Mode, Sink 0.20 5 V Fast Mode, Sink 0.15 0.10 0.14 3 V Slow Mode, Sink 0.12 0.10 3 V Fast Mode, Sink 0.08 0.06 0.04 0.05 0.02 0 0 0 0.02 0.04 0.1 0.2 0.4 0.8 1 2 4 0 Load Current − mA 0.01 0.02 0.05 0.1 0.2 0.5 Load Current − mA Figure 2 0.8 1 2 Figure 3 LOAD REGULATION LOAD REGULATION 4.002 2.003 4.00 2.0025 5 V Slow Mode, Source 3 V Fast Mode, Source VO − Output Voltage − V VO − Output Voltage − V 3.998 3.996 3.994 5 V Fast Mode, Source 3.992 3.99 3.988 VDD = 5 V, VREF = 2 V, VO = Full Scale 3.986 0.02 0.04 0.1 0.2 0.4 0.8 Load Current − mA 1 2 2.0015 3 V Slow Mode, Source 2.001 2.0005 2 VDD = 3 V, VREF = 1 V, VO = Full Scale 1.9995 3.984 0 2.002 4 1.999 0 0.01 0.02 0.05 0.1 0.2 0.5 Load Current − mA Figure 4 8 Figure 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 0.8 1 2 

 
 
  

   
 
     SLAS232A − JUNE1999 − REVISED JULY 2002 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs TEMPERATURE SUPPLY CURRENT vs TEMPERATURE 4 4 VDD = 3 V, VREF = 1.024 V, VO = Full Scale 3.5 Fast Mode Fast Mode I DD − Supply Current − mA I DD − Supply Current − mA 3.5 3 2.5 2 1.5 3 2.5 2 Slow Mode 1.5 Slow Mode 1 VDD = 5 V, VREF = 1.024 V, VO = Full Scale 1 0.5 −40 −20 0 20 40 60 80 0.5 −40 100 −20 T − Temperature − °C 20 40 60 80 100 T − Temperature − °C Figure 6 Figure 7 TOTAL HARMONIC DISTORTION vs FREQUENCY TOTAL HARMONIC DISTORTION vs FREQUENCY 0 0 Vref = 1 V dc + 1 V p/p Sinewave, Output Full Scale −10 THD − Total Harmonic Distortion − dB THD − Total Harmonic Distortion − dB 0 −20 −30 −−40 −50 −60 Fast Mode −70 −80 0 5 10 20 30 50 100 Vref = 1 V dc + 1 V p/p Sinewave, Output Full Scale −10 −20 −30 −−40 −50 −60 Slow Mode −70 −80 0 5 f − Frequency − kHz 10 20 30 50 100 f − Frequency − kHz Figure 8 Figure 9 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 

 
 
  

   
 
     SLAS232A − JUNE1999 − REVISED JULY 2002 TYPICAL CHARACTERISTICS 0 Vref = 1 V dc + 1 V p/p Sinewave, Output Full Scale −10 TOTAL HARMONIC DISTORTION AND NOISE vs FREQUENCY THD − Total Harmonic Distortion And Noise − dB THD − Total Harmonic Distortion And Noise − dB TOTAL HARMONIC DISTORTION AND NOISE vs FREQUENCY −20 −30 −−40 −50 Fast Mode −60 −70 −80 0 Vref = 1 V dc + 1 V p/p Sinewave, Output Full Scale −10 −20 −30 −−40 −50 Slow Mode −60 −70 −80 0 5 10 30 20 50 100 0 5 10 f − Frequency − kHz Figure 10 Figure 11 SUPPLY CURRENT vs TIME (WHEN ENTERING POWER-DOWN MODE) 4000 I DD − Supply Current − µ A 3500 3000 2500 2000 1500 1000 500 0 0 200 400 600 800 t − Time − ns Figure 12 10 20 30 f − Frequency − kHz POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1000 50 100 

 
 
  

   
 
     SLAS232A − JUNE1999 − REVISED JULY 2002 TYPICAL CHARACTERISTICS DNL − Differential Nonlinearity − LSB DIFFERENTIAL NONLINEARITY vs DIGITAL OUTPUT CODE 0.20 0.15 0.10 0.05 −0.00 −0.05 −0.10 −0.15 −0.20 0 64 128 192 255 Digital Output Code Figure 13 INL − Integral Nonlinearity − LSB INTEGRAL NONLINEARITY vs DIGITAL OUTPUT CODE 0.4 0.3 0.2 0.1 −0.0 −0.1 −0.2 −0.3 −0.4 0 64 128 192 255 Digital Output Code Figure 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 

 
 
  

   
 
     SLAS232A − JUNE1999 − REVISED JULY 2002 APPLICATION INFORMATION general function The TLV5627 is an 8-bit single supply DAC based on a resistor string architecture. The device consists of a serial interface, speed and power-down control logic, a reference input buffer, a resistor string, and a rail-to-rail output buffer. The output voltage (full scale determined by external reference) is given by: 2 REF CODE [V] 2n Where REF is the reference voltage and CODE is the digital input value within the range of 010 to 2n−1, where n=8 (bits). The 16-bit data word, consisting of control bits and the new DAC value, is illustrated in the data format section. A power-on reset initially resets the internal latches to a defined state (all bits zero). serial interface The device has to be enabled with CS set to low. A falling edge of FS starts shifting the data bit-per-bit (starting with the MSB) to the internal register on the falling edges of SCLK. After 16 bits have been transferred or FS rises, the content of the shift register is moved to the DAC latch, which updates the voltage output to the new level. The serial interface of the TLV5627 can be used in two basic modes: D Four wire (with chip select) D Three wire (without chip select) Using chip select (four-wire mode), it is possible to have more than one device connected to the serial port of the data source (DSP or microcontroller). The interface is compatible with the TMS320 family. Figure 15 shows an example with two TLV5627s connected directly to a TMS320 DSP. TLV5627 TLV5627 CS FS DIN SCLK CS FS DIN SCLK TMS320 DSP XF0 XF1 FSX DX CLKX Figure 15. TMS320 Interface 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 

 
 
  

   
 
     SLAS232A − JUNE1999 − REVISED JULY 2002 APPLICATION INFORMATION serial interface (continued) If there is no need to have more than one device on the serial bus, then CS can be tied low. Figure 16 shows an example of how to connect the TLV5627 to a TMS320, SPI, or Microwire port using only three pins. TMS320 DSP TLV5627 FSX SPI FS DIN DX CLKX TLV5627 FS DIN SS MOSI SCLK SCLK Microwire FS DIN I/O SO SK SCLK CS TLV5627 SCLK CS CS Figure 16. Three-Wire Interface Notes on SPI and Microwire: Before the controller starts the data transfer, the software has to generate a falling edge on the I/O pin connected to FS. If the word width is 8 bits (SPI and Microwire), two write operations must be performed to program the TLV5627. After the write operation(s), the DAC output is updated automatically on the next positive clock edge following the sixteenth falling clock edge. serial clock frequency and update rate The maximum serial clock frequency is given by: f SCLKmax + t wH(min) 1 )t + 20 MHz wL(min) The maximum update rate is: f UPDATEmax + 1 ǒ wH(min) ) twL(min)Ǔ + 1.25 MHz 16 t The maximum update rate is a theoretical value for the serial interface since the settling time of the TLV5627 has to be considered also. data format The 16-bit data word for the TLV5627 consists of two parts: D Control bits D New DAC value D15 D14 D13 D12 A1 A0 PWR SPD SPD: Speed control bit. PWR: Power control bit. (D15 . . . D12) (D11 . . . D0) D11 1 → fast mode 1 → power down D10 D9 D8 D7 D6 D5 New DAC value (8 bits) D4 D3 D2 D1 D0 0 0 0 0 0 → slow mode 0 → normal operation POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 

 
 
  

   
 
     SLAS232A − JUNE1999 − REVISED JULY 2002 APPLICATION INFORMATION In power-down mode, all amplifiers within the TLV5627 are disabled. A particular DAC (A, B, C, D) of the TLV5627 is selected by A1 and A0 within the input word. A1 A0 DAC 0 0 A 0 1 B 1 0 C 1 1 D TLV5627 interfaced to TMS320C203 DSP hardware interfacing Figure 17 shows an example of how to connect the TLV5627 to a TMS320C203 DSP. The serial port is configured in burst mode, with FSX generated by the TMS320C203 to provide the frame sync (FS) input to the TLV5627. Data is transmitted on the DX line, with the serial clock input on the CLKX line. The general-purpose input/output port bits IO0 and IO1 are used to generate the chip select ( CS) and DAC latch update ( LDAC) inputs to the TLV5627. The active low power down ( PD) is pulled high all the time to ensure the DACs are enabled. TMS320C203 TLV5627 SDIN DX VDD SCLK CLKX FSX FS I/O 0 CS I/O 1 LDAC PD VOUTA VOUTB REF REFINAB VOUTC REFINCD VOUTD VSS Figure 17. TLV5627 Interfaced with TMS320C203 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 

 
 
  

   
 
     SLAS232A − JUNE1999 − REVISED JULY 2002 APPLICATION INFORMATION TLV5627 interfaced to MCS51 microcontroller hardware interfacing Figure 18 shows an example of how to connect the TLV5627 to an MCS51 Microcontroller. The serial DAC input data and external control signals are sent via I/O Port 3 of the controller. The serial data is sent on the RxD line, with the serial clock output on the TxD line. Port 3 bits 3, 4, and 5 are configured as outputs to provide the DAC latch update (LDAC), chip select (CS) and frame sync (FS) signals for the TLV5627. The active low power down pin (PD) of the TLV5627 is pulled high to ensure that the DACs are enabled. MCS®51 TLV5627 RxD SDIN TxD SCLK P3.3 LDAC P3.4 CS P3.4 FS VDD PD VOUTA VOUTB REF REFINAB VOUTC REFINCD VOUTD VSS Figure 18. TLV5627 Interfaced with MCS51 linearity, offset, and gain error using single ended supplies When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. With a positive offset, the output voltage changes on the first code change. With a negative offset, the output voltage may not change with the first code, depending on the magnitude of the offset voltage. The output amplifier attempts to drive the output to a negative voltage. However, because the most negative supply rail is ground, the output cannot drive below ground and clamps the output at 0 V. The output voltage then remains at zero until the input code value produces a sufficient positive output voltage to overcome the negative offset voltage, resulting in the transfer function shown in Figure 19. Output Voltage 0V DAC Code Negative Offset Figure 19. Effect of Negative Offset (single supply) MCS is a registered trademark of Intel Corporation. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 

 
 
  

   
 
     SLAS232A − JUNE1999 − REVISED JULY 2002 APPLICATION INFORMATION linearity, offset, and gain error using single ended supplies (continued) The offset error, not the linearity error, produces this breakpoint. The transfer function would have followed the dotted line if the output buffer could drive below the ground rail. For a DAC, linearity is measured between zero-input code (all inputs 0) and full-scale code (all inputs 1) after offset and full scale are adjusted out or accounted for in some way. However, single supply operation does not allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity is measured between full-scale code and the lowest code that produces a positive output voltage. power-supply bypassing and ground management Printed-circuit boards that use separate analog and digital ground planes offer the best system performance. Wire-wrap boards do not perform well and should not be used. The two ground planes should be connected together at the low-impedance power-supply source. The best ground connection may be achieved by connecting the DAC AGND terminal to the system analog ground plane, making sure that analog ground currents are well-managed and there are negligible voltage drops across the ground plane. A 0.1-µF ceramic-capacitor bypass should be connected between VDD and AGND and mounted with short leads as close as possible to the device. Use of ferrite beads may further isolate the system analog supply from the digital power supply. Figure 20 shows the ground plane layout and bypassing technique. Analog Ground Plane 1 8 2 7 3 6 4 5 0.1 µF Figure 20. Power-Supply Bypassing 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 

 
 
  

   
 
     SLAS232A − JUNE1999 − REVISED JULY 2002 MECHANICAL DATA D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PIN SHOWN 0.050 (1,27) 0.020 (0,51) 0.014 (0,35) 14 0.010 (0,25) M 8 0.008 (0,20) NOM 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81) Gage Plane 0.010 (0,25) 1 7 0°−ā 8° A 0.044 (1,12) 0.016 (0,40) Seating Plane 0.069 (1,75) MAX 0.010 (0,25) 0.004 (0,10) PINS ** 0.004 (0,10) 8 14 16 A MAX 0.197 (5,00) 0.344 (8,75) 0.394 (10,00) A MIN 0.189 (4,80) 0.337 (8,55) 0.386 (9,80) DIM 4040047 / D 10/96 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). Falls within JEDEC MS-012 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 

 
 
  

   
 
     SLAS232A − JUNE1999 − REVISED JULY 2002 MECHANICAL DATA PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PIN SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°−ā 8° 0,75 0,50 A Seating Plane 0,15 0,05 1,20 MAX 0,10 PINS ** 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064 / E 08/96 NOTES: A. B. C. D. 18 All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) TLV5627CD ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TLV5627C Samples TLV5627CDG4 ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TLV5627C Samples TLV5627CDR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TLV5627C Samples TLV5627CPW ACTIVE TSSOP PW 16 90 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TV5627 Samples TLV5627CPWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TV5627 Samples TLV5627ID ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TLV5627I Samples TLV5627IPW ACTIVE TSSOP PW 16 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TY5627 Samples TLV5627IPWG4 ACTIVE TSSOP PW 16 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TY5627 Samples TLV5627IPWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TY5627 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of