D−8
DGK−8
TLV5636
www.ti.com
SLAS223C – JUNE 1999 – REVISED APRIL 2004
2.7-V TO 5.5-V, LOW POWER, 12-BIT, DIGITAL-TO-ANALOG CONVERTER
WITH INTERNAL REFERENCE AND POWER DOWN
FEATURES
APPLICATIONS
•
•
•
•
•
•
•
•
•
•
•
12-Bit Voltage Output DAC
Programmable Internal Reference
Programmable Settling Time:
– 1 µs in Fast Mode
– 3.5 µs in Slow Mode
Compatible With TMS320 and SPI™ Serial
Ports
Differential Nonlinearity . . . 4.75 V
MIN
TYP
MAX
UNIT
1.003
1.024
1.045
V
2.027
2.048
2.068
V
1
-1
mA
Load capacitance
PSRR
mA
100
Power supply rejection ratio
-65
pF
dB
REFERENCE INPUT CONFIGURED AS INPUT (REF)
PARAMETER
VI
Input voltage
Ri
Input resistance
Ci
Input capacitance
(1)
TEST CONDITIONS
MIN
TYP
0
Reference input bandwidth
REF = 0.2 Vpp + 1.024 V dc
Reference feed through
REF = 1 Vpp at 1 kHz + 1.024 V dc (1)
MAX
VDD - 1.5
UNIT
V
10
kΩ
5
pF
Fast
1.3
Slow
525
MHz
-80
dB
Reference feedthrough is measured at the DAC output with an input code = 0x000.
DIGITAL INPUT
PARAMETER
TEST CONDITIONS
IIH
High-level digital input current
VI = VDD
IIL
Low-level digital input current
VI = 0 V
Ci
Input capacitance
4
MIN
TYP
MAX
1
-1
UNIT
µA
µA
8
pF
TLV5636
www.ti.com
SLAS223C – JUNE 1999 – REVISED APRIL 2004
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range, supply voltages, and reference voltages (unless otherwise noted)
ANALOG OUTPUT DYNAMIC PERFORMANCE
PARAMETER
TEST CONDITIONS
ts(FS)
Output settling time (full scale)
RL = 10 kΩ,
see note (1)
CL = 100 pF,
ts(CC)
Output settling time, code to code
RL = 10 kΩ,
see note (2)
CL = 100 pF,
SR
Slew rate
RL = 10 kΩ,
see note (3)
CL = 100 pF,
Glitch energy
DIN = 0 to 1,
CS = VDD
TYP
MAX
Fast
MIN
1
3
Slow
3.5
7
Fast
0.5
1.5
Slow
1
2
Fast
8
Slow
1.5
fout = 1 kHz,
Signal-to-noise ratio
71
S/(N+D)
Signal-to-noise + distortion
59
THD
Total harmonic distortion
fs = 480 kSPS,
RL = 10 kΩ,
fout = 1 kHz,
CL = 100 pF
Spurious free dynamic range
(1)
(2)
(3)
µs
µs
V/µs
5
SNR
UNIT
nV-s
75
66
-67
59
-59
dB
69
Settling time is the time for the output signal to remain within +0.5 LSB of the final measured value for a digital input code change of
0x20 to 0xFDF and 0xFDF to 0x020 respectively. Assured by design; not tested.
Settling time is the time for the output signal to remain within +0.5 LSB of the final measured value for a digital input code change of one
count. Assured by design; not tested.
Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage.
TIMING REQUIREMENTS
DIGITAL INPUTS
MIN
tsu(CS-FS)
Setup time, CS low before FS falling edge
tsu(FS-CK)
Setup time, FS low before first negative SCLK edge
16th
NOM
MAX
UNIT
10
ns
8
ns
tsu(C16-FS)
Setup time,
negative edge after FS low on which bit D0 is sampled before
rising edge of FS.
10
ns
tsu(C16-CS)
Setup time, 16th positive SCLK edge (first positive after D0 is sampled) before CS
rising edge. If FS is used instead of 16th positive edge to update DAC, then setup
time between FS rising edge and CS rising edge.
10
ns
twH
SCLK pulse duration high
25
ns
twL
SCLK pulse duration low
25
ns
tsu(D)
Setup time, data ready before SCLK falling edge
8
ns
th(D)
Hold time, data held valid after SCLK falling edge
5
ns
twH(FS)
FS duration high
25
ns
5
TLV5636
www.ti.com
SLAS223C – JUNE 1999 – REVISED APRIL 2004
PARAMETER MEASUREMENT INFORMATION
twL
SCLK
X
1
2
tsu(D)
DIN
X
twH
3
4
5 15
X
16
th(D)
D15
D14
D13
D12
D1
D0
X
tsu(C16-CS)
tsu(CS-FS)
CS
twH(FS)
tsu(FS-CK)
tsu(C16-FS)
FS
Figure 1. Timing Diagram
6
TLV5636
www.ti.com
SLAS223C – JUNE 1999 – REVISED APRIL 2004
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE
vs
LOAD CURRENT
OUTPUT VOLTAGE
vs
LOAD CURRENT
2.071
4.135
VDD = 3 V, REF = Int. 1 V, Input Code = 4095
VDD = 5 V, REF = Int. 2 V, Input Code = 4095
2.0705
4.134
Fast
2.0695
Output Voltage − V
Output Voltage − V
2.07
Fast
2.0698
Slow
2.0685
2.068
4.133
Slow
4.132
4.131
2.0675
2.067
4.13
2.0665
4.129
2.066
0
0.5
1
1.5
2
2.5
3
3.5
4
0
0.5
1
Source Current − mA
1.5
2
2.5
3
3.5
4
Source Current − mA
Figure 2.
Figure 3.
OUTPUT VOLTAGE
vs
LOAD CURRENT
OUTPUT VOLTAGE
vs
LOAD CURRENT
3
5
VDD = 3 V, REF = Int. 1 V,
Input Code = 0
VDD = 5 V, REF = Int. 2 V,
Input Code = 0
4.5
2.5
2
Output Voltage − V
Output Voltage − V
4
Fast
1.5
1
3.5
3
Fast
2.5
2
1.5
1
0.5
0.5
Slow
0
Slow
0
0
0.5
1
1.5
2
2.5
Sink Current − mA
Figure 4.
3
3.5
4
0
0.5
1
1.5
2
2.5
3
3.5
4
Sink Current − mA
Figure 5.
7
TLV5636
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SLAS223C – JUNE 1999 – REVISED APRIL 2004
TYPICAL CHARACTERISTICS (continued)
SUPPLY CURRENT
vs
TEMPERATURE
SUPPLY CURRENT
vs
TEMPERATURE
3
3
VDD = 5 V, REF = 2 V,
Input Code = 4095
VDD = 3 V, REF = 1 V,
Input Code = 4095
2.5
2.5
Supply Current − mA
Supply Current − mA
Fast Mode
2
Slow Mode
1.5
1
Slow Mode
0.5
−40 −30 −20 −10 0 10 20 30 40 50 60 70 80 90
T − Temperature − °C
0.5
−40−30−20 −10 0 10 20 30 40 50 60 70 80 90
T − Temperature − °C
Figure 6.
Figure 7.
POWER DOWN SUPPLY CURRENT
vs
TIME
TOTAL HARMONIC DISTORTION AND NOISE
vs
FREQUENCY
THD+N − Total Harmonic Distortion and Noise − dB
I DD − Power Down Supply Current − mA
1.5
1
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
0
10
20
30
40
50
t − Time − µs
Figure 8.
8
Fast Mode
2
60
70
80
0
−10
VDD = 5 V
Vref = 1 V dc + 1 V p/p Sine Wave
Output Full Scale
−20
−30
−40
−50
−60
Slow Mode
−70
Fast Mode
−80
−90
−100
100
1000
10000
f − Frequency − Hz
Figure 9.
100000
TLV5636
www.ti.com
SLAS223C – JUNE 1999 – REVISED APRIL 2004
TYPICAL CHARACTERISTICS (continued)
TOTAL HARMONIC DISTORTION
vs
FREQUENCY
0
VDD = 5 V
Vref = 1 V dc + 1 V p/p Sine Wave
Output Full Scale
THD − Total Harmonic Distortion − dB
−10
−20
−30
−40
−50
−60
−70
Slow Mode
−80
Fast Mode
−90
−100
100
1000
10000
100000
f − Frequency − Hz
Figure 10.
DNL − Differential Nonlinearity − LSB
DIFFERENTIAL NONLINEARITY
vs
DIGITAL INPUT CODE
1
0.5
0
−0.5
−1
0
1024
2048
Digital Input Code
3072
4096
Figure 11.
9
TLV5636
www.ti.com
SLAS223C – JUNE 1999 – REVISED APRIL 2004
TYPICAL CHARACTERISTICS (continued)
INL − Integral Nonlinearity − LSB
INTEGRAL NONLINEARITY
vs
DIGITAL INPUT CODE
4
3
2
1
0
−1
−2
−3
−4
0
1024
2048
Digital Input Code
Figure 12.
10
3072
4096
TLV5636
www.ti.com
SLAS223C – JUNE 1999 – REVISED APRIL 2004
APPLICATION INFORMATION
GENERAL FUNCTION
The TLV5636 is a 12-bit, single supply DAC, based on a resistor string architecture. It consists of a serial
interface, a speed and power-down control logic, a programmable internal reference, a resistor string, and a
rail-to-rail output buffer.
The output voltage (full scale determined by external reference) for each channel is given by:
2 REF CODE
[V]
2n
where REF is the reference voltage and CODE is the digital input value within the range of 010 to 2n-1, where
n = 12 (bits). The 16-bit data word, consisting of control bits and the new DAC value, is illustrated in the data
format section. A power-on reset initially resets the internal latches to a defined state (all bits zero).
SERIAL INTERFACE
The device has to be enabled with CS set to low. A falling edge of FS starts shifting the data bit-per-bit (starting
with the MSB) to the internal register on high-low transitions of SCLK. After 16 bits have been transferred or FS
rises, the content of the shift register is moved to the DAC latch, which updates the voltage output to the new
level.
The serial interface of the TLV5636 can be used in two basic modes:
• Four wire (with chip select)
• Three wire (without chip select)
Using chip select (four-wire mode), it is possible to have more than one device connected to the serial port of the
data source (DSP or microcontroller). Figure 13 shows an example with two TLV5636s connected directly to a
TMS320 DSP.
TLV5636
CS
TMS320
DSP
FS
DIN SCLK
TLV5636
CS
FS
DIN
SCLK
XF0
XF1
FSX
DX
CLKX
Figure 13. TMS320 Interface
If there is no need to have more than one device on the serial bus, then CS can be tied low. Figure 14 shows an
example of how to connect the TLV5636 to TMS320, SPI™ or Microwire™ using only three pins.
11
TLV5636
www.ti.com
SLAS223C – JUNE 1999 – REVISED APRIL 2004
APPLICATION INFORMATION (continued)
TMS320
DSP FSX
DX
CLKX
TLV5636
FS
DIN
SCLK
SPI
TLV5636
FS
DIN
SCLK
I/O
MOSI
SCK
CS
Microwire
I/O
SO
SK
TLV5636
FS
DIN
SCLK
CS
CS
Figure 14. Three Wire Interface
Notes on SPI and Microwire: Before the controller starts the data transfer, the software has to generate a falling
edge on the I/O pin connected to FS. If the word width is 8 bits (SPI and Microwire), two write operations must be
performed to program the TLV5636. After the write operation(s), the DAC output is updated automatically on the
next positive clock edge following the sixteenth falling clock edge.
SERIAL CLOCK AND UPDATE RATE
The maximum serial clock frequency is given by:
1
f sclkmax
20 MHz
t whmin t wlmin
(1)
The maximum update rate is:
1
f updatemax
1.25 MHz
16 t whmin t wlmin
(2)
Note that the maximum update rate is just a theoretical value for the serial interface, as the settling time of the
TLV5636 has to be considered, too.
DATA FORMAT
The 16-bit data word for the TLV5636 consists of two parts:
• Program bits (D15..D12)
• New data (D11..D0)
D15
D14
D13
D12
R1
SPD
PWR
R0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
12 Data bits
SPD
: Speed control bit
1 = fast mode
0 = slow mode
PWR
: Power control bit
1 = power down
0 = normal operation
The following table lists the possible combination of the register select bits:
Register Select Bits
12
R1
R0
REGISTER
0
0
Write data to DAC
0
1
Reserved
1
0
Reserved
1
1
Write data to control register
D1
D0
TLV5636
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SLAS223C – JUNE 1999 – REVISED APRIL 2004
The meaning of the 12 data bits depends on the selected register. For the DAC register, the 12 data bits
determine the new DAC output value:
Data Bits: DAC
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
New DAC value
If the control register is selected, then D1, D0 of the 12 data bits are used to program the reference voltage:
Data Bits: CONTROL
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X (1)
X
X
X
X
X
X
X
X
X
REF1
REF0
(1)
X = don't care
REF1 and REF0 determine the reference source. If internal reference is selected, REF1 and REF0 determine the
reference voltage.
Reference Bits
REF1
REF0
REFERENCE
0
0
External
0
1
1.024 V
1
0
2.048 V
1
1
External
CAUTION:
If external reference voltage is applied to the REF pin, external reference MUST
be selected.
EXAMPLE:
•
Set DAC output, select fast mode, select internal reference at 2.048 V:
Set reference voltage to 2.048 V (CONTROL register):
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
1
0
D2
D1
D0
Write new DAC value and update DAC output:
D15
D14
D13
D12
0
1
0
0
D11
D10
D9
D8
D7
D6
D5
D4
D3
New DAC output value
The DAC output is updated on the rising clock edge after D0 is sampled.
To output data consecutively using the same DAC configuration, it is not necessary to program the CONTROL
register again.
13
TLV5636
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SLAS223C – JUNE 1999 – REVISED APRIL 2004
LINEARITY, OFFSET, AND GAIN ERROR USING SINGLE END SUPPLIES
When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. With
a positive offset, the output voltage changes on the first code change. With a negative offset, the output voltage
may not change with the first code, depending on the magnitude of the offset voltage.
The output amplifier attempts to drive the output to a negative voltage. However, because the most negative
supply rail is ground, the output cannot drive below ground and clamps the output at 0 V.
The output voltage then remains at zero until the input code value produces a sufficient positive output voltage to
overcome the negative offset voltage, resulting in the transfer function shown in Figure 15.
Output
Voltage
0V
DAC Code
Negative
Offset
Figure 15. Effect of Negative Offset (Single Supply)
This offset error, not the linearity error, produces this breakpoint. The transfer function would have followed the
dotted line if the output buffer could drive below the ground rail.
For a DAC, linearity is measured between zero-input code (all inputs 0) and full-scale code (all inputs 1) after
offset and full scale are adjusted out or accounted for in some way. However, single supply operation does not
allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity is
measured between full-scale code and the lowest code that produces a positive output voltage.
POWER-SUPPLY BYPASSING AND GROUND MANAGEMENT
Printed-circuit boards that use separate analog and digital ground planes offer the best system performance.
Wire-wrap boards do not perform well and should not be used. The two ground planes should be connected
together at the low-impedance power-supply source. The best ground connection may be achieved by
connecting the DAC AGND terminal to the system analog ground plane, making sure that analog ground currents
are well managed and there are negligible voltage drops across the ground plane.
A 0.1-µF ceramic-capacitor bypass should be connected between VDD and AGND and mounted with short leads
as close as possible to the device. Use of ferrite beads may further isolate the system analog supply from the
digital power supply.
Figure 16 shows the ground plane layout and bypassing technique.
Analog Ground Plane
1
8
2
7
3
6
4
5
0.1 µF
Figure 16. Power-Supply Bypassing
14
TLV5636
www.ti.com
SLAS223C – JUNE 1999 – REVISED APRIL 2004
DEFINITIONS OF SPECIFICATIONS AND TERMINOLOGY
Integral Nonlinearity (INL)
The relative accuracy or integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum
deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale
errors.
Differential Nonlinearity (DNL)
The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the
measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage
changes in the same direction (or remains constant) as a change in the digital input code.
Zero-Scale Error (EZS)
Zero-scale error is defined as the deviation of the output from 0 V at a digital input value of 0.
Gain Error (EG)
Gain error is the error in slope of the DAC transfer function.
Total Harmonic Distortion (THD)
THD is the ratio of the rms value of the first six harmonic components to the value of the fundamental signal. The
value for THD is expressed in decibels.
Signal-To-Noise Ratio + Distortion (S/N+D)
S/N+D is the ratio of the rms value of the output signal to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc. The value for S/N+D is expressed in decibels.
Spurious Free Dynamic Range (SFDR)
Spurious free dynamic range is the difference between the rms value of the output signal and the rms value of
the largest spurious signal within a specified bandwidth. The value for SFDR is expressed in decibels.
15
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TLV5636CD
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
5636C
TLV5636CDGK
ACTIVE
VSSOP
DGK
8
80
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
0 to 70
AJF
TLV5636CDGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
0 to 70
AJF
TLV5636ID
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
5636I
TLV5636IDGK
ACTIVE
VSSOP
DGK
8
80
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
AJG
TLV5636IDGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
AJG
TLV5636IDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
5636I
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of