TLV5637
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SLAS224C – JUNE 1999 – REVISED JUNE 2007
2.7V TO 5.5V LOW-POWER DUAL 10-BIT DIGITAL-TO-ANALOG CONVERTER WITH
INTERNAL REFERENCE AND POWER DOWN
FEATURES
•
•
•
•
•
•
Dual 10-Bit Voltage Output DAC
Programmable Internal Reference
Programmable Settling Time:
– 0.8µs in Fast Mode
– 2.8µs in Slow Mode
Compatible With TMS320 and SPI™ Serial
Ports
Differential Nonlinearity 4.75V
MIN
TYP
MAX
UNIT
1.003
1.024
1.045
V
2.027
2.048
2.069
1
1
mA
Load capacitance
PSRR
V
mA
100
Power supply rejection ratio
65
pF
dB
REFERENCE PIN CONFIGURED AS INPUT (REF)
PARAMETER
VI
Input voltage
RI
Input resistance
CI
Input capacitance
(1)
TEST CONDITIONS
MIN
TYP
MAX
VDD–1.
5
0
10
REF = 0.2VPP + 1.024V dc
Reference feedthrough
REF = 1VPP at 1 kHz + 1.024V dc, See
V
MΩ
5
Reference input bandwidth
UNIT
pF
Fast
1.3
MHz
Slow
525
kHz
80
dB
(1)
Reference feedthrough is measured at the DAC output with an input code = 0x000.
DIGITAL INPUTS
PARAMETER
TEST CONDITIONS
IIH
High-level digital input current
VI = VDD
IIL
Low-level digital input current
VI = 0V
Ci
Input capacitance
MIN
TYP MAX
1
1
µA
µA
8
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UNIT
pF
5
TLV5637
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SLAS224C – JUNE 1999 – REVISED JUNE 2007
ELECTRICAL CHARACTAERISTICS (CONTINUED)
over recommended operating conditions (unless otherwise noted)
ANALOG OUTPUT DYNAMIC PERFORMANCE
PARAMETER
TEST CONDITIONS
MIN
ts(FS)
Output settling time, full scale
RL = 10kΩ, CL = 100pF,
See
(1)
ts(CC)
Output settling time, code to code
RL = 10kΩ, CL = 100pF,
See
(2)
SR
Slew rate
RL = 10kΩ, CL = 100pF,
See
(3)
Glitch energy
DIN = 0 to 1, fCLK = 100kHz,
CS = VDD
TYP MAX
Fast
0.8
2.4
Slow
2.8
5.5
Fast
0.4
1.2
Slow
0.8
1.6
Fast
12
Slow
1.8
Signal-to-noise ratio
53
56
S/(N+D)
Signal-to-noise + distortion
50
54
THD
Total harmonic distortion
SFDR
Spurious free dynamic range
(2)
(3)
µs
µs
V/µs
5
SNR
(1)
UNIT
fs = 480kSPS, fout = 1kHz, RL = 10kΩ, CL = 100pF
61
51
nV-S
dB
50
62
Settling time is the time for the output signal to remain within ±0.5LSB of the final measured value for a digital input code change of
0x020 to 0xFDF or 0xFDF to 0x020 respectively. Not tested, assured by design.
Settling time is the time for the output signal to remain within ± 0.5LSB of the final measured value for a digital input code change of one
count. Not tested, assured by design.
Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage.
DIGITAL INPUT TIMING REQUIREMENTS
MIN
NOM
MAX
UNIT
tsu(CS-CK)
Setup time, CS low before first negative SCLK edge
10
ns
tsu(C16-CS)
Setup time, 16th negative SCLK edge (when D0 is sampled) before CS rising edge
10
ns
twH
SCLK pulse width high
25
ns
twL
SCLK pulse width low
25
ns
tsu(D)
Setup time, data ready before SCLK falling edge
10
ns
th(D)
Hold time, data held valid after SCLK falling edge
5
ns
PARAMETER MEASUREMENT INFORMATION
twL
SCLK
X
1
2
tsu(D)
DIN
X
D15
twH
3
4
5 15
X
16
th(D)
D14
D13
D12
D1
D0
X
tsu(C16-CS)
tsu(CS-CK)
CS
Figure 1. Timing Diagram
6
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SLAS224C – JUNE 1999 – REVISED JUNE 2007
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
4.5
4.5
4
I DD – Supply Current – mA
I DD – Supply Current – mA
4
Fast Mode
3.5
3
2.5
2
Slow Mode
1.5
Fast Mode
3.5
3
2.5
2
Slow Mode
1.5
VDD = 5 V
Vref = Int. 2 V
Input Code = 1023 (Both DACs)
1
VDD = 3 V
Vref = Int. 1 V
Input Code = 1023 (Both DACs)
1
0.5
–40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90
TA – Free-Air Temperature – °C
0.5
–40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90
TA – Free-Air Temperature – °C
Figure 2.
Figure 3.
POWER DOWN SUPPLY CURRENT
vs
TIME
OUTPUT VOLTAGE
vs
LOAD CURRENT
2.064
2.4
VDD = 3 V
Vref = Int. 1 V
Input Code = 4095
Fast Mode
2.062
2.2
2
VO – Output Voltage – V
I DD – Power Down Supply Current – mA
2.6
1.8
1.6
1.4
1.2
1
0.8
2.06
Slow Mode
2.058
2.056
2.054
0.6
0.4
2.052
0.2
0
2.05
0
10
20
30
40
50
t – Time – µs
60
70
80
0
0.5
1
1.5
2
2.5
3
3.5
4
Source Current – mA
Figure 4.
Figure 5.
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TLV5637
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SLAS224C – JUNE 1999 – REVISED JUNE 2007
TYPICAL CHARACTERISTICS (continued)
OUTPUT VOLTAGE
vs
LOAD CURRENT
OUTPUT VOLTAGE
vs
LOAD CURRENT
3
4.128
VDD = 5 V
Vref = Int. 2 V
Input Code = 4095
Fast Mode
2.5
VO – Output Voltage – V
VO – Output Voltage – V
4.126
VDD = 3 V
Vref = Int. 1 V
Input Code = 0
4.124
Slow Mode
4.122
4.12
4.118
Fast Mode
2
1.5
1
0.5
4.116
Slow Mode
0
4.114
0
0.5
1
1.5
2
2.5
3
3.5
0
4
Source Current – mA
THD+N – Total Harmonic Distortion and Noise – dB
VO – Output Voltage – V
3
3.5
TOTAL HARMONIC DISTORTION AND NOISE
vs
FREQUENCY
Fast Mode
3
2.5
2
1.5
1
0.5
Slow Mode
0
1.5
2
2.5
4
3
3.5
4
0
–10
VDD = 5 V
Vref = 1 V dc + 1 V p/p Sinewave
Output Full Scale
–20
–30
–40
–50
–60
Slow Mode
–70
Fast Mode
–80
–90
–100
100
Sink Current – mA
1000
10000
f – Frequency – Hz
Figure 8.
8
2.5
OUTPUT VOLTAGE
vs
LOAD CURRENT
3.5
1
2
Figure 7.
4
0.5
1.5
Figure 6.
VDD = 5 V
Vref = Int. 2 V
Input Code = 0
0
1
Sink Current – mA
5
4.5
0.5
Figure 9.
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TLV5637
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SLAS224C – JUNE 1999 – REVISED JUNE 2007
TYPICAL CHARACTERISTICS (continued)
TOTAL HARMONIC DISTORTION
vs
FREQUENCY
0
VDD = 5 V
Vref = 1 V dc + 1 V p/p Sinewave
Output Full Scale
THD – Total Harmonic Distortion – dB
–10
–20
–30
–40
–50
–60
–70
Slow Mode
–80
Fast Mode
–90
–100
100
1000
10000
100000
f – Frequency – Hz
INL – Integral Nonlinearity Error – LSB
Figure 10.
INTEGRAL NONLINEARITY ERROR
1
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1
0
256
512
768
1024
DNL – Differential Nonlinearity Error – LSB
Digital Code
Figure 11.
DIFFERENTIAL NONLINEARITY ERROR
0.2
0.15
0.1
0.05
0
–0.05
–0.1
–0.15
–0.2
0
256
512
768
1024
Digital Code
Figure 12.
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TLV5637
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SLAS224C – JUNE 1999 – REVISED JUNE 2007
APPLICATION INFORMATION
GENERAL FUNCTION
The TLV5637 is a dual 10-bit, single supply DAC, based on a resistor string architecture. It consists of a serial
interface, a speed and power-down control logic, a programmable internal reference, a resistor string, and a
rail-to-rail output buffer.
The output voltage (full scale determined by reference) is given by:
2 REF CODE [V]
0x1000
Where REF is the reference voltage and CODE is the digital input value in the range 0x000 to 0xFFF. Because
it is a 10-bit DAC, only D11 to D2 are used. D0 and D1 are ignored. A power-on reset initially puts the internal
latches to a defined state (all bits zero).
SERIAL INTERFACE
A falling edge of CS starts shifting the data bit-per-bit (starting with the MSB) to the internal register on the falling
edges of SCLK. After 16 bits have been transferred or CS rises, the content of the shift register is moved to the
target latches (DAC A, DAC B, BUFFER, CONTROL), depending on the control bits within the data word.
Figure 13 shows examples of how to connect the TLV5637 to TMS320, SPI, and Microwire.
TMS320
DSP FSX
DX
CLKX
TLV5637
CS
DIN
SCLK
SPI
I/O
MOSI
SCK
TLV5637
CS
DIN
SCLK
Microwire
I/O
SO
SK
TLV5637
CS
DIN
SCLK
Figure 13. Three-Wire Interface
Notes on SPI and Microwire: Before the controller starts the data transfer, the software has to generate a falling
edge on the I/O pin connected to CS. If the word width is 8 bits (SPI and Microwire), two write operations must
be performed to program the TLV5637. After the write operation(s), the holding registers or the control register
are updated automatically on the 16th positive clock edge.
SERIAL CLOCK FREQUENCY AND UPDATE RATE
The maximum serial clock frequency is given by:
fsclkmax =
1
= 20MHz
(twhmin + twlmin)
The maximum update rate is:
fupdatemax =
1
= 1.25MHz
16 (twhmin + twlmin)
Note that the maximum update rate is just a theoretical value for the serial interface, as the settling time of the
TLV5637 has to be considered as well.
10
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SLAS224C – JUNE 1999 – REVISED JUNE 2007
APPLICATION INFORMATION (continued)
DATA FORMAT
The 16-bit data word for the TLV5637 consists of two parts:
• Program bits (D15..D12)
• New data (D11..D0)
D15
D14
D13
D12
R1
SPD
PWR
R0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
12 Data bits
SPD: Speed control bit
1→ fast mode
0 → slow mode
PWR: Power control bit
1 → power down
0 → normal operation
The following table lists the possible combination of the register select bits:
Register Select Bits
R1
R0
0
0
REGISTER
Write data to DAC B and BUFFER
0
1
Write data to BUFFER
1
0
Write data to DAC A and update DAC B with BUFFER content
1
1
Write data to control register
The meaning of the 12 data bits depends on the register. If one of the DAC registers or the BUFFER is selected,
then the 12 data bits determine the new DAC value:
Data Bits: DAC A, DAC B and BUFFER
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
New DAC Value
D1
D0
0
0
If control is selected, then D1, D0 of the 12 data bits are used to program the reference voltage:
Data Bits: CONTROL
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
X
X
X
X
X
REF1
REF0
X: don't care
REF1 and REF0 determine the reference source and, if internal reference is selected, the reference voltage.
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TLV5637
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SLAS224C – JUNE 1999 – REVISED JUNE 2007
APPLICATION INFORMATION
REFERENCE BITS
REF1
REF0
REFERENCE
0
0
External
0
1
1.024V
1
0
2.048V
1
1
External
CAUTION:
If external refeence voltage is applied to the REF pin, external reference MUST
be selected.
EXAMPLES OF OPERATION:
1. Set DAC A output, select fast mode, select internal reference at 2.048V:
a. Set reference voltage to 2.048V (CONTROL register)
D15
1
D14
1
D13
0
D12
1
D11
0
D10
0
D9
0
D8
0
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
1
D0
0
D8
D7
D6
D5
New DAC A output value
D4
D3
D2
D1
0
D0
0
b. Write new DAC A value and update DAC A output:
D15
1
D14
1
D13
0
D12
0
D11
D10
D9
The DAC A output is updated on the rising clock edge after D0 is sampled.
To output data consecutively using the same DAC configuration, it is not necessary to program the
CONTROL register again.
2. Set DAC B output, select fast mode, select external reference:
a. Select external reference (CONTROL register):
D15
1
D14
1
D13
0
D12
1
D11
0
D10
0
D9
0
D8
0
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
D5
D4
D3
D2
D1
D0
0
0
b. Write new DAC B value to BUFFER and update DAC B output:
D15
D14
D13
D12
0
1
0
0
D11
D10
D9
D8
D7
D6
New BUFFER content and DAC B output value
The DAC A output is updated on the rising clock edge after D0 is sampled.
To output data consecutively using the same DAC configuration, it is not necessary to program the
CONTROL register again.
1. Set DAC A value, set DAC B value, update both simultaneously, select slow mode, select internal
reference at 1.024V:
a. Set reference voltage to 1.024V (CONTROL register):
D15
1
D14
0
D13
0
D12
1
D11
0
D10
0
D9
0
D8
0
D9
D8
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
1
D5
D4
D3
D2
D1
0
D0
0
D5
D4
D3
D2
D1
0
D0
0
b. Write data for DAC B to BUFFER:
D15
0
c.
D15
1
D14
0
D13
0
D12
1
D11
D10
D7
D6
New DAC B value
Write new DAC A value and update DAC A and B simultaneously:
D14
0
D13
0
D12
0
D11
D10
D9
D8
D7
D6
New DAC A value
Both outputs are updated on the rising clock edge after D0 from the DAC A data word is sampled.
2. Set power down mode:
D15
D14
X
X
X = Don't care
12
D13
1
D12
X
D11
X
D10
X
D9
X
D8
X
D7
X
D6
X
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D5
X
D4
X
D3
X
D2
X
D1
X
D0
X
TLV5637
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SLAS224C – JUNE 1999 – REVISED JUNE 2007
LINEARITY, OFFSET, AND GAIN ERROR USING SINGLE ENDED SUPPLIES
When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative.
With a positive offset, the output voltage changes on the first code change. With a negative offset, the output
voltage may not change with the first code, depending on the magnitude of the offset voltage.
The output amplifier attempts to drive the output to a negative voltage. However, because the most negative
supply rail is ground, the output cannot drive below ground and clamps the output at 0V.
The output voltage then remains at zero until the input code value produces a sufficiently positive output voltage
to overcome the negative offset voltage, resulting in the transfer function shown in Figure 14.
Output
Voltage
0V
Negative
Offset
DAC Code
Figure 14. Effect of Negative Offset (Single Supply)
This offset error, not the linearity error, produces this breakpoint. The transfer function would have followed the
dotted line if the output buffer could drive below the ground rail.
For a DAC, linearity is measured between zero-input code (all inputs 0) and full-scale code (all inputs 1) after
offset and full scale are adjusted out or accounted for in some way. However, single supply operation does not
allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity is
measured between full-scale code and the lowest code that produces a positive output voltage.
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TLV5637
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SLAS224C – JUNE 1999 – REVISED JUNE 2007
DEFINITIONS OF SPECIFICATIONS AND TERMINOLOGY
Integral Nonlinearity (INL)
The relative accuracy or integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum
deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale
errors.
Differential Nonlinearity (DNL)
The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the
measured and ideal 1LSB amplitude change of any two adjacent codes. Monotonic means the output voltage
changes in the same direction (or remains constant) as a change in the digital input code.
Zero-Scale Error (EZS)
Zero-scale error is defined as the deviation of the output from 0V at a digital input value of 0.
GAIN ERROR (EG)
Gain error is the error in slope of the DAC transfer function.
SIGNAL-TO-NOISE RATIO + DISTORTION (S/N+D)
S/N+D is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components
below the Nyquist frequency, including harmonics but excluding dc. The value for S/N+D is expressed in
decibels.
SPURIOUS FREE DYNAMIC RANGE (SFDR)
Spurious free dynamic range is the difference between the rms value of the output signal and the rms value of
the spurious signal within a specified bandwidth. The value for SFDR is expressed in decibels.
14
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Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from B Revision (January 2004) to C Revision .............................................................................................. Page
•
Changed —moved package option table from front page. ................................................................................................... 3
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TLV5637CD
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
5637C
TLV5637CDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
5637C
TLV5637ID
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
5637I
TLV5637IDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
5637I
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of