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TLV6001-Q1, TLV6002-Q1
SBOS934A – AUGUST 2018 – REVISED DECEMBER 2018
TLV600x-Q1 Low-Power, Rail-to-Rail In/Out, 1-MHz Operational Amplifier for CostSensitive Systems
1 Features
•
1
•
•
•
•
•
•
•
•
•
•
AEC-Q100 Qualified for Automotive Applications
– Device Temperature Grade 1: –40°C to
+125°C, TA
– Device HBM ESD Classification Level 3A
– Device CDM ESD Classification Level C6
General-Purpose Amplifiers for Cost-Sensitive
Systems
Supply Range: 1.8 V to 5.5 V
Gain Bandwidth: 1 MHz
Low Quiescent Current: 75 µA/ch
Rail-to-Rail Input and Output
Low Offset Voltage: 0.75 mV
Unity-Gain Stable
Input Voltage Noise Density: 28 nV/√Hz at 1 kHz
Internal RF and EMI Filter
Extended Temperature Range:
–40°C to 125°C
The robust design of the TLV600x-Q1 provides easeof use to the circuit designer: unity-gain stability with
capacitive loads of up to 150 pF, integrated RF/EMI
rejection filter, no phase reversal in overdrive
conditions, and high electrostatic discharge (ESD)
protection (4-kV HBM).
The devices are optimized for operation at voltages
as low as 1.8 V (±0.9 V) and up to 5.5 V (±2.75 V),
and are specified over the extended temperature
range of –40°C to +125°C.
The single-channel TLV6001-Q1 is available in the
SC70-5 package, and the dual-channel TLV6002-Q1
is available in both SOIC and VSSOP packages.
Device Information(1)
PART NUMBER
TLV6002-Q1
3 Description
The TLV600x-Q1 family of single and dual-channel
operational amplifiers is specifically designed for
general-purpose automotive applications. Featuring
rail-to-rail input and output (RRIO) swings, low
quiescent current (75 µA, typical), wide bandwidth (1
MHz) and low noise (28 nV/√Hz at 1 kHz), this family
is attractive for a variety of automotive applications
that require a good balance between cost and
performance, such as infotainment, engine control
units, and automotive lighting. The low-input-bias
current (±1 pA, typical) enables the TLV600x-Q1 to
be used in applications with megaohm source
impedances.
2.00 mm × 1.25 mm
SOIC (8)
3.91 mm × 4.90 mm
VSSOP (8)
3.00 mm × 3.00 mm
CMRR and PSRR vs Temperature
110
Common-Mode Rejection Ratio (dB),
Power-Supply Rejection Ratio (dB)
Optimized for AEC-Q100 Grade 1 Applications
Electric Vehicle Inverters
Infotainment
Passive Safety
Body Electronics and Lighting
BODY SIZE (NOM)
SC70 (5)
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
•
•
•
•
•
PACKAGE
TLV6001-Q1
105
PSRR
100
95
90
CMRR
85
80
75
70
65
60
-50
-25
0
25
50
75
Temperature (oC)
100
125
C001
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLV6001-Q1, TLV6002-Q1
SBOS934A – AUGUST 2018 – REVISED DECEMBER 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
5
6.1
6.2
6.3
6.4
6.5
6.6
5
5
5
6
6
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information: TLV6001-Q1 ...........................
Thermal Information: TLV6002-Q1 ...........................
Electrical Characteristics: VS = 1.8 V to 5 V (±0.9 V
to ±2.75 V) .................................................................
6.7 Typical Characteristics: Table of Graphs ..................
6.8 Typical Characteristics ..............................................
7
7
8
9
Detailed Description ............................................ 12
7.1
7.2
7.3
7.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
12
12
13
14
7.5 Input and ESD Protection ....................................... 14
8
Application and Implementation ........................ 15
8.1 Application Information............................................ 15
8.2 Typical Application ................................................. 15
8.3 System Examples .................................................. 16
9 Power Supply Recommendations...................... 17
10 Layout................................................................... 18
10.1 Layout Guidelines ................................................. 18
10.2 Layout Example: Single Channel.......................... 18
10.3 Layout Example: Dual Channel ............................ 19
11 Device and Documentation Support ................. 20
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
20
20
20
20
20
20
20
12 Mechanical, Packaging, and Orderable
Information ........................................................... 21
4 Revision History
Changes from Original (August 2018) to Revision A
Page
•
Added TLV6002-Q1 device to data sheet .............................................................................................................................. 1
•
Added dual channel information for TLV6002-Q1 device throughout data sheet .................................................................. 1
•
Added ESD classification levels for TLV600x-Q1 family ........................................................................................................ 1
2
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SBOS934A – AUGUST 2018 – REVISED DECEMBER 2018
5 Pin Configuration and Functions
TLV6001-Q1 DCK Package
5-Pin SC70
Top View
+IN
1
V±
2
±IN
3
5
V+
4
OUT
+
±
Not to scale
Pin Functions: TLV6001-Q1
PIN
NAME
NO.
I/O
DESCRIPTION
–IN
3
I
Inverting input
+IN
1
I
Noninverting input
OUT
4
O
Output
V–
2
—
Negative (lowest) power supply
V+
5
—
Positive (highest) power supply
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SBOS934A – AUGUST 2018 – REVISED DECEMBER 2018
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TLV6002-Q1 D, DGK Packages
8-Pin SOIC, VSSOP
Top View
OUT A
1
8
V+
±IN A
2
7
OUT B
+IN A
3
6
±IN B
V±
4
5
+IN B
Not to scale
Pin Functions: TLV6002-Q1
PIN
I/O
DESCRIPTION
NAME
NO.
–IN A
2
I
Inverting input, channel A
–IN B
6
I
Inverting input, channel B
+IN A
3
I
Noninverting input, channel A
+IN B
5
I
Noninverting input, channel B
OUT A
1
O
Output, channel A
OUT B
7
O
Output, channel B
V–
4
—
Negative (lowest) power supply
V+
8
—
Positive (highest) power supply
4
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SBOS934A – AUGUST 2018 – REVISED DECEMBER 2018
6 Specifications
6.1 Absolute Maximum Ratings
over recommended operating free-air temperature range (unless otherwise noted) (1)
MIN
Voltage
Signal input pins, voltage (2)
(V–) – 0.5
(V+) + 0.5
–10
10
Output short-circuit (3)
–40
(3)
mA
150
Junction, TJ
150
Storage, Tstg
(2)
V
Continuous
Operating, TA
Temperature
UNIT
7
Signal input pins, current (2)
Current
(1)
MAX
Supply voltage (V+) – (V–)
–65
°C
150
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Input pins are diode-clamped to the power-supply rails. Input signals that may swing more than 0.5 V beyond the supply rails must be
current limited to 10 mA or less.
Short-circuit to ground, one amplifier per package.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002 (1)
HBM ESD Classification Level 3A
±4000
Charged-device model (CDM), per AEC Q100-011
CDM ESD Classification Level C4B
±1000
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VS
Supply voltage
1.8
5.5
UNIT
V
TA
Specified temperature
–40
125
°C
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SBOS934A – AUGUST 2018 – REVISED DECEMBER 2018
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6.4 Thermal Information: TLV6001-Q1
TLV6001-Q1
THERMAL METRIC (1)
DCK (SC70)
UNIT
5 PINS
RθJA
Junction-to-ambient thermal resistance
281.4
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
91.6
°C/W
RθJB
Junction-to-board thermal resistance
59.6
°C/W
ψJT
Junction-to-top characterization parameter
1.5
°C/W
ψJB
Junction-to-board characterization parameter
58.8
°C/W
(1)
For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
6.5 Thermal Information: TLV6002-Q1
TLV6002-Q1
THERMAL METRIC (1)
D (SOIC)
DGK (VSSOP)
8 PINS
8 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
131.6
186.0
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
71.4
73.2
°C/W
RθJB
Junction-to-board thermal resistance
75.4
107.3
°C/W
ψJT
Junction-to-top characterization parameter
22.7
14.4
°C/W
ψJB
Junction-to-board characterization parameter
74.6
105.6
°C/W
(1)
6
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SBOS934A – AUGUST 2018 – REVISED DECEMBER 2018
6.6 Electrical Characteristics: VS = 1.8 V to 5 V (±0.9 V to ±2.75 V) (1)
at TA = 25°C, RL = 10 kΩ connected to VS / 2, and VCM = VOUT = VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
0.75
4.5
UNIT
OFFSET VOLTAGE
VOS
Input offset voltage
dVOS/dT
VOS vs temperature
PSRR
Power-supply rejection ratio
TA = –40°C to +125°C
mV
2
µV/°C
86
dB
±1
pA
±1
pA
INPUT BIAS CURRENT
IB
Input bias current
IOS
Input offset current
TA = 25°C
INPUT IMPEDANCE
ZID
Differential
ZIC
Common-mode
100 || 1
MΩ || pF
1013Ω || pF
1 || 5
INPUT VOLTAGE RANGE
VCM
Common-mode voltage range
No phase reversal, rail-to-rail input
CMRR
Common-mode rejection ratio
VCM = –0.2 V to 5.7 V
(V–) – 0.2
60
76
(V+) + 0.2
Open-loop voltage gain
0.3 V < VO < (V+) – 0.3 V, RL = 2 kΩ
90
110
Phase margin
VS = 5 V, G = 1
V
dB
OPEN-LOOP GAIN
AOL
65
°
OUTPUT
VO
Voltage output swing from supply rails
ISC
Short-circuit current
RO
Open-loop output impedance
RL = 100 kΩ
5
RL = 2 kΩ
75
mV
100
±15
mA
2300
Ω
FREQUENCY RESPONSE
GBW
Gain-bandwidth product
SR
Slew rate
tS
Settling time
To 0.1%, VS = 5 V, 2-V step , G = +1
1
MHz
0.5
V/µs
5
µs
NOISE
Input voltage noise (peak-to-peak)
f = 0.1 Hz to 10 Hz
6
µVPP
en
Input voltage noise density
f = 1 kHz
28
nV/√Hz
in
Input current noise density
f = 1 kHz
5
fA/√Hz
POWER SUPPLY
VS
Specified voltage range
IQ
Quiescent current per amplifier
IO = 0 mA, VS = 5 V
75
Power-on time
VS = 0 V to 5 V, to 90% IQ level
10
(1)
1.8 (±0.9)
5.5 (±2.75)
V
100
µA
µs
Parameters with minimum or maximum specification limits are 100% production tested at 25°C, unless otherwise noted.
Overtemperature limits are based on characterization and statistical analysis.
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6.7 Typical Characteristics: Table of Graphs
Table 1. Table of Graphs
8
TITLE
FIGURE
Open-Loop Gain and Phase vs Frequency
Figure 1
Quiescent Current vs Supply Voltage
Figure 2
Offset Voltage Production Distribution
Figure 3
Offset Voltage vs Common-Mode Voltage (Maximum Supply)
Figure 4
CMRR and PSRR vs Frequency (RTI)
Figure 5
0.1-Hz to 10-Hz Input Voltage Noise (5.5 V)
Figure 6
Input Voltage Noise Spectral Density vs Frequency (1.8 V, 5.5 V)
Figure 7
Input Bias and Offset Current vs Temperature
Figure 8
Open-Loop Output Impedance vs Frequency
Figure 9
Maximum Output Voltage vs Frequency and Supply Voltage
Figure 10
Output Voltage Swing vs Output Current
Figure 11
Closed-Loop Gain vs Frequency, G = 1, –1, 10 (1.8 V)
Figure 12
Small-Signal Step Response, Noninverting (1.8 V)
Figure 13
Small-Signal Step Response, Noninverting (5.5 V)
Figure 14
Large-Signal Step Response, Noninverting (1.8 V)
Figure 15
Large-Signal Step Response, Noninverting (5.5 V)
Figure 16
No Phase Reversal
Figure 17
EMIRR IN+ vs Frequency
Figure 18
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SBOS934A – AUGUST 2018 – REVISED DECEMBER 2018
6.8 Typical Characteristics
at TA = 25°C, VS = 5 V, RL = 10 kΩ connected to VS / 2, and VCM = VOUT = VS / 2 (unless otherwise noted)
140
180
Gain
58
Phase
135
CL=10pF
C
L = 10 pF
80
60
Phase (o)
Gain (dB)
100
Quiescent Current (µA/ch)
120
60
90
40
20
45
C
L = 100 pF
CL=100pF
0
56
54
52
50
48
46
44
42
-20
1
10
100
1k
10k 100k
Frequency (Hz)
1M
10M
0
100M
40
1.5
2.5
3
3.5
4
4.5
Supply Voltage (V)
5
5.5
6
C003
Figure 2. Quiescent Current vs Supply
9
1500
8
1200
900
Offset Voltage (µV)
7
6
5
4
3
600
300
0
-300
-600
Offset Voltage (mV)
2.5
2
1.5
1
0.5
0
-1500
-0.5
0
-1
-1200
-1.5
-900
1
-2
2
-2.5
Percent of Amplifiers (%)
Figure 1. Open-Loop Gain and Phase vs Frequency
2
0
0.5
1
C005
Figure 3. Offset Voltage Production Distribution
1.5 2 2.5 3 3.5 4
Common-Mode Voltage (V)
4.5
5
5.5
C007
Figure 4. Offset Voltage vs Common-Mode Voltage
100
Voltage Noise (1 µV/div)
Common-Mode Rejection Ratio (dB),
Power-Supply Rejection Ratio (dB)
120
80
+PSRR
60
CMRR
40
20
-PSRR
0
10
100
1k
10k
Frequency (Hz)
100k
Time (1 s/div)
1M
C009
Figure 5. CMRR and PSRR vs Frequency (Referred-to-Input)
C011
Figure 6. 0.1-Hz to 10-Hz Input Voltage Noise
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Typical Characteristics (continued)
at TA = 25°C, VS = 5 V, RL = 10 kΩ connected to VS / 2, and VCM = VOUT = VS / 2 (unless otherwise noted)
1000
200
150
Input Bias Current (pA)
9ROWDJH 1RLVH Q9 ¥+]
VS = 1.8 V
100
10
VS = 5.5 V
IBN
100
IBP
50
0
IOS
-50
1
-100
1
10
100
1k
Frequency (Hz)
10k
100k
-50
-25
0
25
50
Temperature (oC)
C012
Figure 7. Input Voltage Noise Spectral Density vs Frequency
75
100
125
C014
Figure 8. Input Bias and Offset Current vs Temperature
6
100k
VS = 5.5 V
Output Voltage (V)
Output Impedance ( )
5
VS = 1.8 V
10k
4
VS = 1.8 V
3
2
1
VS = 5.5 V
0
1000
1000
1
10
100
1k
Frequency (Hz)
10k
100k
1M
C016
Figure 10. Maximum Output Voltage vs Frequency and
Supply Voltage
3
40
G = +10 V/V
2
20
oC
+125
+125oC
0
+25oC
+25 oC
Gain (dB)
1
-40 oC
-40oC
G = +1 V/V
0
-1
-2
G = -1 V/V
-20
-3
0
5
10
Output Current (mA)
15
20
10
100
C017
Figure 11. Output Voltage Swing vs Output Current
10
100k
Frequency (Hz)
Figure 9. Open-Loop Output Impedance vs Frequency
Output Voltage Swing (V)
10k
C015
1k
10k
100k
Frequency (Hz)
1M
10M
100M
C018
Figure 12. Closed-Loop Gain vs Frequency
(Minimum Supply)
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Typical Characteristics (continued)
at TA = 25°C, VS = 5 V, RL = 10 kΩ connected to VS / 2, and VCM = VOUT = VS / 2 (unless otherwise noted)
CL = 100 pF
CL = 100 pF
VIN
Voltage (25 mV/div)
Voltage (25 mV/div)
VIN
CL = 10 pF
CL = 10 pF
Time (1 µs/div)
Time (1 µs/div)
C004
C023
Figure 14. Small-Signal Pulse Response (Maximum Supply)
Voltage (250 mV/div)
Voltage (250 mV/div)
Figure 13. Small-Signal Pulse Response (Minimum Supply)
VOUT
VIN
VOUT
VIN
Time (2.5 µs/div)
Time (2.5 µs/div)
C024
C025
Figure 15. Large-Signal Pulse Response (Minimum Supply)
Figure 16. Large-Signal Pulse Response (Maximum Supply)
120
EMIRR IN+ (dB)
Voltage (1 V/div)
100
VOUT
80
60
40
20
VIN
0
Time (125 µs/div)
10
100
1000
Frequency (MHz)
C028
Figure 17. No Phase Reversal
10000
C033
Figure 18. EMIRR IN+ vs Frequency
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7 Detailed Description
7.1 Overview
The TLV600x-Q1 family of operational amplifiers is a general-purpose, low-cost family that is designed for a wide
range of portable applications. Rail-to-rail input and output swings, low quiescent current, and wide dynamic
range make the operational amplifier designed to drive sampling analog-to-digital converters (ADCs) and other
single-supply applications.
7.2 Functional Block Diagram
V+
Reference
Current
VIN+
VINVBIAS1
Class AB
Control
Circuitry
VO
VBIAS2
V(Ground)
12
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7.3 Feature Description
7.3.1 Operating Voltage
The TLV600x-Q1 family is fully specified and tested from 1.8 V to 5.5 V (±0.9 V to ±2.75 V).The Typical
Characteristics section shows parameters that vary with supply voltage.
7.3.2 Rail-to-Rail Input
The input common-mode voltage range of the TLV600x-Q1 family extends 200 mV beyond the supply rails. This
performance is achieved with a complementary input stage: an N-channel input differential pair in parallel with a
P-channel differential pair, as the Functional Block Diagram section shows. The N-channel pair is active for input
voltages close to the positive rail, typically (V+) – 1.3 V to 200 mV above the positive supply, while the P-channel
pair is on for inputs from 200 mV below the negative supply to approximately (V+) – 1.3 V. There is a small
transition region, typically (V+) – 1.4 V to (V+) – 1.2 V, in which both pairs are on. This 200-mV transition region
can vary up to 300 mV with process variation. As a result, the transition region (both stages on) can range from
(V+) – 1.7 V to (V+) – 1.5 V on the low end, and up to (V+) – 1.1 V to (V+) – 0.9 V on the high end. Within this
transition region, PSRR, CMRR, offset voltage, offset drift, and THD can degrade compared to device operation
outside this region.
7.3.3 Rail-to-Rail Output
Designed as a micro-power, low-noise operational amplifier, the TLV600x-Q1 family delivers a robust output
drive capability. A class AB output stage with common source transistors achieve full rail-to-rail output swing
capability. For resistive loads up to 100 kΩ, the output swings typically to within 5 mV of either supply rail
regardless of the power supply voltage that is applied. Figure 11 shows that different load conditions change the
ability of the amplifier to swing close to the rails.
7.3.4 Common-Mode Rejection Ratio (CMRR)
CMRR for the TLV600x-Q1 family is specified in several ways so the best match for a given application can be
used; see the Electrical Characteristics. First, the CMRR of the device in the common-mode range below the
transition region (VCM < (V+) – 1.3 V) is shown. This specification is the best indicator of the capability of the
device when the application requires the use of one of the differential input pairs. Second, the CMRR over the
entire common-mode range is specified at (VCM = –0.2 V to 5.7 V). This last value includes the variations seen
through the transition region, as Figure 4 shows.
7.3.5 Capacitive Load and Stability
The TLV600x-Q1 family is designed to be used in applications where driving a capacitive load is required. As
with all operational amplifiers, there can be specific instances where the TLV600x-Q1 family can become
unstable. The particular op amp circuit configuration, layout, gain, and output loading are some of the factors to
consider when establishing if an amplifier is stable in operation. An operational amplifier in the unity-gain (1-V/V)
buffer configuration that drives a capacitive load exhibits a greater tendency for instability than an amplifier that is
operated at a higher noise gain. The capacitive load in conjunction with the op amp output resistance creates a
pole within the feedback loop that degrades the phase margin. The degradation of the phase margin increases
as the capacitive loading increases. When operating in the unity-gain configuration, the TLV600x-Q1 family
remains stable with a pure capacitive load up to approximately 1 nF. The equivalent series resistance (ESR) of
some capacitors (CL greater than 1 µF) is sufficient to alter the phase characteristics in the feedback loop such
that the amplifier remains stable. Increasing the amplifier closed-loop gain allows the amplifier to drive
increasingly larger capacitance. This increased capability is evident when observing the overshoot response of
the amplifier at higher voltage gains.
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Feature Description (continued)
One technique for increasing the capacitive load drive capability of the amplifier when the device operates in a
unity-gain configuration is to insert a small resistor, typically 10 Ω to 20 Ω, in series with the output, as Figure 19
shows. This resistor reduces the overshoot and ringing associated with large capacitive loads. One possible
problem with this technique is that a voltage divider is created with the added series resistor and any resistor
connected in parallel with the capacitive load. The voltage divider introduces a gain error at the output that
reduces the output swing.
V+
RS
VOUT
Device
10 W to
20 W
VIN
RL
CL
Figure 19. Improving Capacitive Load Drive
7.3.6 EMI Susceptibility and Input Filtering
Operational amplifiers vary with regard to the susceptibility of the device to electromagnetic interference (EMI). If
conducted EMI enters the op amp, the dc offset observed at the amplifier output can shift from the nominal value
while EMI is present. This shift is a result of signal rectification associated with the internal semiconductor
junctions. While all op amp pin functions can be affected by EMI, the signal input pins are likely to be the most
susceptible. The TLV600x-Q1 family incorporates an internal input low-pass filter that reduces the amplifiers
response to EMI. This filter provides common-mode and differential mode filtering. The filter is designed for a
cutoff frequency of approximately 35 MHz (–3 dB) with a rolloff of 20 dB per decade.
Texas Instruments developed the ability to accurately measure and quantify the immunity of an operational
amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz. The EMI rejection ratio (EMIRR)
metric allows op amps to be directly compared by the EMI immunity. Figure 18 shows the results of this testing
on the TLV600x-Q1 family. EMI Rejection Ratio of Operational Amplifiers shows detailed information, and is
available for download from www.ti.com.
7.4 Device Functional Modes
The TLV600x-Q1 family has a single functional mode. The device is powered on if the power-supply voltage is
between 1.8 V (±0.9 V) and 5.5 V (±2.75 V).
7.5 Input and ESD Protection
The TLV600x-Q1 family incorporates internal electrostatic discharge (ESD) protection circuits on all pins. In the
case of input and output pins, this protection primarily consists of current-steering diodes connected between the
input and power supply pins. The ESD protection diodes provide in-circuit, input overdrive protection if the
current is limited to 10 mA, as the Absolute Maximum Ratings lists. Figure 20 shows how a series input resistor
can be added to the driven input to limit the input current. The added resistor contributes thermal noise at the
amplifier input and the value must be kept to a minimum in noise-sensitive applications.
V+
IOVERLOAD
10-mA max
Device
VOUT
VIN
5 kW
Figure 20. Input Current Protection
14
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TLV600x-Q1 is a low-power, rail-to-rail input and output operational amplifier specifically designed for
portable applications. The device operates from 1.8 V to 5.5 V, is unity-gain stable, and is designed for a wide
range of general-purpose applications. The class AB output stage can drive ≤ 10-kΩ loads connected to any
point between V+ and ground. The input common-mode voltage range includes both rails and allows the
TLV600x-Q1 family to be used in any single-supply application.
8.2 Typical Application
A typical application for an operational amplifier is an inverting amplifier, as Figure 21 shows. An inverting
amplifier takes a positive voltage on the input and outputs a signal inverted to the input, making a negative
voltage of the same magnitude. In the same manner, the amplifier makes negative input voltages positive on the
output. To add amplification, select an input resistor (RI) and a feedback resistor (RF.)
RF
VSUP+
RI
VOUT
+
VIN
VSUP±
Figure 21. Application Schematic
8.2.1 Design Requirements
Select a supply voltage value that is larger than the input voltage range and the desired output range. Users
must consider the limits of the input common-mode range (VCM) and the output voltage swing to the rails (VO) .
For example, this application scales a signal of ±0.5 V (1 V) to ±1.8 V (3.6 V). Setting the supply at ±2.5 V is
sufficient to accommodate this application.
8.2.2 Detailed Design Procedure
Use Equation 1 and Equation 2 to calculate the required gain for the inverting amplifier:
VOUT
AV
VIN
AV
1.8
0.5
3.6
(1)
(2)
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Typical Application (continued)
When the desired gain is determined, select a value for RI or RF. Selecting a value in the kilohm range is
desirable for general-purpose applications because the amplifier circuit uses currents in the milliamp range. This
milliamp current range ensures the device does not draw too much current. The trade-off is that large resistors
(hundreds of kilohms) draw the smallest current but generate the highest noise. Small resistors (hundreds of
ohms) generate low noise but draw high current. In this example, RI equals 10 kΩ, and RF equals 36 V.
Equation 3 determines these values:
RF
AV
RI
(3)
8.2.3 Application Curve
2
Input
Output
1.5
Voltage (V)
1
0.5
0
-0.5
-1
-1.5
-2
Time
Figure 22. Inverting Amplifier Input and Output
8.3 System Examples
When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often required.
To establish this minimum bandwidth, place an RC filter at the noninverting pin of the amplifier, as Figure 23
shows.
RG
RF
R1
VOUT
VIN
C1
f-3 dB =
(
RF
VOUT
= 1+
RG
VIN
((
1
1 + sR1C1
1
2pR1C1
(
Figure 23. Single-Pole Low-Pass Filter
16
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System Examples (continued)
If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter can be used for this
task, as Figure 24 shows. For best results, the amplifier must have a bandwidth that is 8 to 10 times larger than
the filter frequency bandwidth. Failure to follow this guideline can result in phase shift of the amplifier.
C1
R1
R1 = R2 = R
C1 = C2 = C
Q = Peaking factor
(Butterworth Q = 0.707)
R2
VIN
VOUT
C2
1
2pRC
f-3 dB =
RF
RF
RG =
RG
(
2-
1
Q
(
Figure 24. Two-Pole, Low-Pass, Sallen-Key Filter
9 Power Supply Recommendations
The TLV600x-Q1 family is specified for operation from 1.8 V to 5.5 V (±0.9 V to ±2.75 V). The Typical
Characteristics section presents parameters that can exhibit significant variance with regard to operating voltage
or temperature.
CAUTION
Supply voltages larger than 7 V may permanently damage the device. (See the
Absolute Maximum Ratings ).
Place 0.1-µF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or highimpedance power supplies. For more detailed information on bypass capacitor placement, see the Layout
Guidelines section.
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10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit and the operational
amplifier. Use bypass capacitors to reduce the coupled noise by providing low-impedance power sources
local to the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for singlesupply applications.
• Separate grounding for analog and digital portions of the circuitry is one of the simplest and most
effective methods of noise suppression. One or more layers on multilayer PCBs are typically devoted to
ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Take care to
physically separate digital and analog grounds, paying attention to the flow of the ground current. For
more detailed information, see Circuit Board Layout Techniques (available for download from
www.ti.com).
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If the traces cannot be kept separate, crossing the sensitive trace perpendicularly is much better
than crossing in parallel with the noisy trace.
• Place the external components as close to the device as possible. Keep RF and RG close to the inverting
input in order to minimize parasitic capacitance, as shown in Figure 25.
• Keep the length of input traces as short as possible. Remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly
reduce leakage currents from nearby traces that are at different potentials.
10.2 Layout Example: Single Channel
Run the input traces
as far away from
the supply lines V
IN
as possible.
VS+
VS±
V+
+IN
Use a low-ESR,
ceramic bypass
capacitor.
V±
Use a low-ESR,
ceramic bypass
capacitor.
GND
RG
OUT
±IN
VOUT
GND
RF
Place components
close to the device
and to each other to
reduce parasitic
errors.
Figure 25. Operational Amplifier Board Layout for Noninverting Configuration
+
VIN
VOUT
RG
RF
Figure 26. Schematic Representation of Figure 25
18
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10.3 Layout Example: Dual Channel
+
VIN 1
+
VIN 2
VOUT 1
RG
VOUT 2
RG
RF
RF
Figure 27. Schematic Representation for Figure 25
Place components
close to device and to
each other to reduce
parasitic errors .
OUT 1
VS+
OUT1
Use low-ESR,
ceramic bypass
capacitor . Place as
close to the device
as possible .
GND
V+
RF
OUT 2
GND
IN1 ±
OUT2
IN1 +
IN2 ±
RF
RG
VIN 1
GND
RG
V±
Use low-ESR,
ceramic bypass
capacitor . Place as
close to the device
as possible .
GND
VS±
IN2 +
Ground (GND) plane on another layer
VIN 2
Keep input traces short
and run the input traces
as far away from
the supply lines
as possible .
Figure 28. Layout Example
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, EMI Rejection Ratio of Operational Amplifiers
• Texas Instruments, Circuit Board Layout Techniques
11.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 2. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TLV6001-Q1
Click here
Click here
Click here
Click here
Click here
TLV6002-Q1
Click here
Click here
Click here
Click here
Click here
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
20
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TLV6001QDCKRQ1
ACTIVE
SC70
DCK
5
3000
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
1B1
TLV6002QDGKRQ1
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
1NX6
TLV6002QDRQ1
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
V6002Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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