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TLV6003
SLOS981 – OCTOBER 2019
TLV6003 980-nA, 16-V, Precision, Rail-to-Rail Input and Output, Operational Amplifier
1 Features
3 Description
•
•
•
•
•
•
The TLV6003 is a nanopower operational amplifier
consuming only 980 nA per channel, while offering
very low maximum offset. Reverse battery protection
guards the amplifier from an overcurrent condition
due to improper battery installation. For harsh
environments, the inputs can be taken 5 V greater
than the positive supply rail without damage to the
device.
1
•
•
•
•
Micro-power operation: 1.2 µA (maximum)
Low input offset voltage: 550 µV (maximum)
Reverse battery protection up to 18 V
Rail-to-rail input/output
Gain bandwidth product: 5.5 kHz
Specified temperature range:
TA = –40°C to +125°C
Operating temperature range:
TA = –55°C to +125°C
Input common-mode range exceeds the rails:
–0.1 V to VCC + 5 V
Supply voltage range: 2.5 V to 16 V
Small package:
– 5-pin SOT-23
The low supply current is coupled with a low input
bias current, enabling the device to be used with high
series resistance input sources, such as PIR motion
detectors and carbon monoxide sensors. DC
accuracy is maintained with a low max offset voltage
of 550 μV (25°C), a typical CMRR of 120 dB, and a
minimum open-loop gain of 112 dB at 2.7 V.
The maximum operating supply voltage is specified
from 2.5 V to 16 V, with electrical characteristics
specified at 2.7 V, 5 V, and 15 V. The 2.5-V operation
makes this device compatible with Li-Ion batterypowered systems, making the TLV6003 a good
choice for input signal gain and buffering into lowpower microcontrollers, such as TI’s MSP430.
2 Applications
•
•
•
•
•
Flow transmitter
Pressure transmitter
Motion detector (PIR, uWave, and more)
Blood glucose monitor
Gas detector
The TLV6003 is available in a small SOT-23
package.
Device Information(1)
PART NUMBER
TLV6003
PACKAGE
SOT-23 (5)
BODY SIZE (NOM)
2.90 mm x 1.60 mm
(1) For all available packages, see the package option addendum
at the end of the data sheet.
+
IR
TLV6003
Offset Voltage vs Temperature
VOUT
Offset Voltage (PV)
PIR Motion Detector Buffer
800
700 5 Typical Units Shown
600
500
400
300
200
100
0
-100
-200
-300
-400
-500
-600
-700
-800
-55
-35
-15
5
25
45
65
Temperature (qC)
85
105
125
C001
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLV6003
SLOS981 – OCTOBER 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information – TLV6003 ...............................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
8
8.1 Application Information............................................ 14
8.2 Typical Application .................................................. 15
9 Power Supply Recommendations...................... 18
10 Layout................................................................... 18
10.1 Layout Guidelines ................................................. 18
10.2 Layout Example .................................................... 18
11 Device and Documentation Support ................. 19
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Detailed Description ............................................ 12
7.1
7.2
7.3
7.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Application and Implementation ........................ 14
12
12
13
13
Device Support......................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
19
19
19
19
19
19
19
12 Mechanical, Packaging, and Orderable
Information ........................................................... 19
4 Revision History
2
DATE
REVISION
NOTES
October 2019
*
Initial release.
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5 Pin Configuration and Functions
DBV Package
5-pin SOT-23
Top View
OUT
1
GND
5
VCC
4
±IN
2
3
±
+
+IN
Not to scale
Pin Functions
PIN
NAME
DBV
I/O
DESCRIPTION
OUT
1
O
Output
GND
2
–
Negative (lowest) power supply
+IN
3
I
Noninverting input
–IN
4
I
Inverting input
VCC
5
–
Positive (highest) power supply
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
VCC
Supply voltage (2)
VIN+, VIN–
Input voltage
Singe-ended and common-mode input
voltage, VICR
MAX
17
–0.3
VCC + 5
Differential, VID
IO
UNIT
–18
V
V
±20
Input current (any input)
±10
mA
Output current
±10
mA
Continuous total power dissipation
See Dissipation Rating
TJ
Maximum junction temperature
–55
150
°C
Tstg
Storage temperature
–65
150
°C
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential voltages, are with respect to GND
6.2 ESD Ratings
VALUE
Electrostatic
discharge
V(ESD)
(1)
(2)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±450
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
Single Supply
VCC
Supply Voltage
TA
Operating free-air temperature
Split Supply
NOM
MAX
2.5
16
±1.25
±8
–55
125
UNIT
V
°C
6.4 Thermal Information – TLV6003
TLV6003
THERMAL METRIC
(1)
DBV
UNIT
5 PINS
RθJA
Junction-to-ambient thermal resistance
166.0
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
89.9
°C/W
RθJB
Junction-to-board thermal resistance
36.5
°C/W
ψJT
Junction-to-top characterization parameter
14.0
°C/W
ψJB
Junction-to-board characterization parameter
36.3
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
at TA = 25°C, VCC = 2.7 V, 5 V, and 15 V, VICR = VO = VCC/2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DC PERFORMANCE
VIO
Input offset voltage (1)
dVIO/dT
Offset voltage drift
CMRR
AOL
Common-mode
rejection ratio
Open-loop gain
390
TA = –55°C to +125°C
±550
1500
TA = –55°C to +125°C
2
VICR = 0 V to VCC
VCC = 2.7 V
63
VCC = 2.7 V,
TA = –40°C to +125°C
60
VCC = 5 V
66
VCC = 5 V,
TA = –40°C to +125°C
63
VCC = 15 V
76
VCC = 15 V,
TA = –40°C to +125°C
75
µV
µV/°C
120
120
dB
120
VCC = 2.7 V, 0.2 V < VO < VCC – 0.2 V, RL = 500 kΩ
112
dB
VCC = 15 V, 0.2 V < VO < VCC – 0.2 V, RL = 500 kΩ
123
dB
INPUT
IIO
Input offset current
IIB
Input bias current
ri(d)
Differential input
resistance
Ci(c)
Common-mode input
capacitance
25
TA = –40°C to +125°C
250
pA
1200
100
TA = –40°C to +125°C
250
pA
2000
f = 100 kHz
300
MΩ
3
pF
DYNAMIC PERFORMANCE
UGBW
Unity gain bandwidth
RL = 500 kΩ, CL = 100 pF
5.5
kHz
SR
Slew rate at unity gain
VO(pp) = 0.8 V, RL = 500 kΩ, CL = 100 pF
2.5
V/ms
PM
Phase margin
RL = 500 kΩ, CL = 100 pF
60
°
Gain margin
RL = 500 kΩ, CL = 100 pF
15
dB
VCC = 2.7 or 5 V, V(STEP)PP = 1 V,
AV = –1, CL = 100 pF, RL = 100 kΩ
ts
Settling time
VCC = 15 V, V(STEP)PP = 1 V,
AV = –1, CL = 100 pF, RL = 100 kΩ
0.1%
1.84
0.1%
6.1
0.01%
32
ms
NOISE PERFORMANCE
Vn
Equivalent input noise
voltage
In
Equivalent input noise
current
f = 10 Hz
800
f = 100 Hz
500
f = 100 Hz
8
nV/√Hz
fA/√Hz
OUTPUT
IOL = 2 µA (sourcing)
VOL
Voltage output swing
from the positive rail
IOL = 50 µA (sourcing)
IOH = 2 µA (sinking)
VOH
Voltage output swing
from the negative rail
IOH = 50 µA (sinking)
IO
(1)
Output current
VCC – 0.05
TA = –40°C to +125°C
VCC – 0.08
TA = –40°C to +125°C
VCC – 0.02
VCC – 0.07
VCC – 0.05
VCC – 0.1
0.090
TA = –40°C to +125°C
V
0.180
0.180
TA = –40°C to +125°C
VO = 0.5 V from rail
0.150
0.230
0.260
±200
μA
Input offset voltage and offset voltage drift are specified by characterization from TA = –55°C to +125°C. All other temperature
specifications cover the range of TA = –40°C to +125°C, as listed in the test conditions column.
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Electrical Characteristics (continued)
at TA = 25°C, VCC = 2.7 V, 5 V, and 15 V, VICR = VO = VCC/2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
980
1200
UNIT
POWER SUPPLY
VCC = 2.7 V and 5 V
ICC
Supply current
VCC = 15 V
Reverse supply current
Power supply rejection
ratio (ΔVCC/ΔVOS)
VCC = 5 to 15 V, no load
6
1350
1000
TA = –40°C to +125°C
50
90
TA = –40°C to 125°C
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nA
nA
100
85
100
TA = –40°C to 125°C
1250
1400
VCC = –18 V, VIN = 0 V, VO = open current
VCC = 2.7 to 5 V, no load
PSRR
TA = –40°C to +125°C
110
dB
95
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6.6 Typical Characteristics
at TA = 25°C and VCC = 5 V (unless otherwise noted)
6
1400
V IO – Input Offset Voltage – mV
Frequency - %
5
4
3
2
1
-600
-400
-200
0
200
400
1200
1000
800
600
400
200
0
–200
–0.20
–0.1 0.20 0.60 1.00 1.40 1.80 2.20 2.60 2.9
600
C002
VIO - Input Offset Voltage - PV
VICR – Common-Mode Input Voltage – V
VCC = 2.7 V
Figure 1. Input Offset Voltage Histogram
Figure 2. Input Offset Voltage vs Common-Mode Input
Voltage
400
V IO – Input Offset Voltage – mV
V IO – Input Offset Voltage – mV
100
0
–100
–200
–300
–400
–0.2
–0.1 0.4 1.0 1.6 2.2 2.8 3.4 4.0 4.6 5.2
300
200
100
0
–100
–200
–300
–400
–0.2
–0.1
VICR – Common-Mode Input Voltage – V
VCC = 5 V
4.2
6.4
8.6
10.8 13.0 15.2
VCC = 15 V
Figure 3. Input Offset Voltage vs Common-Mode Input
Voltage
Figure 4. Input Offset Voltage vs Common-Mode Input
Voltage
600
I IB / I IO – Input Bias / Offset Current – pA
600
I IB / I IO – Input Bias / Offset Current – pA
2.0
VICR – Common-Mode Input Voltage – V
500
400
300
200
100
IIO
0
IIB
–100
–200
–40 –25 –10 5
20 35 50 65 80 95 110 125
500
400
300
200
100
IIO
0
IIB
–100
–200
–40 –25 –10 5
20 35 50 65 80 95 110 125
TA – Free-Air Temperature – °C
TA – Free-Air Temperature – °C
VCC = 2.7 V
VCC = 5.0 V
Figure 5. Input Bias Current and Offset Current vs Free-Air
Temperature
Figure 6. Input Bias Current and Offset Current vs CommonMode Input Voltage
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Typical Characteristics (continued)
at TA = 25°C and VCC = 5 V (unless otherwise noted)
400
I IB / I IO – Input Bias / Offset Current – pA
I IB / I IO – Input Bias / Offset Current – pA
700
600
500
400
300
200
100
IIO
0
–100
–200
–40 –25 –10 5
IIB
20 35 50 65 80 95 110 125
350
300
250
200
150
100
50
IIO
0
–50
IIB
–100
–150
–0.2
–0.1 0.2
VCC = 15 V
1.8
2.2
2.6 2.9
250
150
100
50
IIO
0
–50
IIB
–100
–150
–0.2 0.4 1.0 1.6 2.2 2.8 3.4 4.0 4.6 5.2
–0.1
I IB / I IO – Input Bias / Offset Current – pA
I IB / I IO – Input Bias / Offset Current – pA
1.4
Figure 8. Input Bias Current and Offset Current vs CommonMode Input Voltage
200
200
150
100
50
IIO
0
–50
IIB
–100
–150
–0.2
–0.1
2.0
4.2
6.4
8.6
10.8 13.0 15.2
VICR – Common-Mode Input Voltage –V
VICR – Common Mode Input Voltage – V
VCC = 5.0 V
VCC = 15.0 V
Figure 9. Input Bias Current and Offset Current vs CommonMode Input Voltage
Figure 10. Input Bias Current and Offset Current vs
Common-Mode Input Voltage
2.7
120
VCC=2.7, 5, 15 V
100
V OH – High-Level Output Voltage – V
CMRR – Common-Mode Rejection Ratio – dB
1.0
VCC = 2.7 V
Figure 7. Input Bias Current and Offset Current vs Free-Air
Temperature
RF=100 kW
RI=1 kW
80
60
40
20
2.4
TA = –40°C
2.1
TA = –0°C
TA = 25 °C
TA = 70 °C
TA = 125 °C
1.8
1.5
1.2
0
1
10
100
1k
f – Frequency – Hz
0
10k
50
100
150
200
IOH – High-Level Output Current – mA
Figure 11. Common-Mode Rejection Ratio vs Frequency
8
0.6
VICR – Common Mode Input Voltage – V
TA – Free-Air Temperature – °C
Figure 12. High-Level Output Voltage vs High-Level Output
Current
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Typical Characteristics (continued)
at TA = 25°C and VCC = 5 V (unless otherwise noted)
5.0
1.25
V OH – High-Level Output Voltage – V
VOL – Low-Level Output Voltage – V
1.50
TA = 25 °C
TA = 0 °C
TA = –40°C
1.00
0.75
TA = 70 °C
TA = 125 °C
0.50
0.25
0
TA = –40°C
4.5
TA = –0°C
TA = 25 °C
TA = 70 °C
TA = 125 °C
4.0
3.5
3.0
0
50
100
150
200
0
50
100
150
200
IOL – Low-Level Output Current – mA
IOH – High-Level Output Current – mA
Figure 13. Low-Level Output Voltage vs Low-Level Output
Current
Figure 14. High-Level Output Voltage vs High-Level Output
Current
15.0
V OH – High-Level Output Voltage – V
VOL – Low-Level Output Voltage – V
1.50
1.25
TA = 0 °C
TA = –40°C
1.00
0.75
TA = 25 °C
TA = 70 °C
TA = 125 °C
0.50
0.25
14.5
TA = –0°C
TA = 25 °C
TA = 70 °C
TA = 125 °C
14.0
13.5
TA = –40°C
13
0
0
50
100
150
0
200
50
100
150
200
IOL – Low-Level Output Current – mA
IOH – High-Level Output Current – mA
Figure 15. Low-Level Output Voltage vs Low-Level Output
Current
Figure 16. High-Level Output Voltage vs High-Level Output
Current
V O(PP) – Output voltage Peak–to–Peak – V
VOL – Low-Level Output Voltage – V
1.50
1.25
TA = –40°C
1.00
TA = –0°C
TA = 25 °C
TA = 70 °C
TA = 125 °C
0.75
0.50
0.25
0
0
50
100
150
200
14
12
10
8
6
4
VCC = 5 V
2
VCC = 2.7 V
0
–2
10
IOL – Low-Level Output Current – mA
Figure 17. Low-Level Output Voltage vs Low-Level Output
Current
16
100
f – Frequency – Hz
1k
Figure 18. Output Voltage Peak-to-Peak vs Frequency
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Typical Characteristics (continued)
at TA = 25°C and VCC = 5 V (unless otherwise noted)
1.4
I CC – Supply Current – m A/Ch
AV = 10
1k
AV = 1
100
1.2
1.0
0.8
0.6
TA = 125°C
TA = 70 °C
TA = 25 °C
TA = 0 °C
TA = –40°C
0.4
0.2
10
100
0
1k
f – Frequency – Hz
0
10k
60
110
50
AOL – Open-Loop Gain – dB
PSRR – Power Supply Rejection Ratio – dB
100
8
10
12
14
16
90
80
70
60
135
40
90
30
20
45
10
0
0
–10
50
–20
40
100
1k
f – Frequency – Hz
10
10k
3.5
6
3.0
5
4
3
2
100
1k
f – Frequency – Hz
–45
10k
Figure 22. Open-Loop Gain and Phase vs Frequency
7
SR – Slew Rate – V/ ms
GBWP –Gain Bandwidth Product – kHz
6
Figure 20. Supply Current vs Supply Voltage
120
Figure 21. Power Supply Rejection Ratio vs Frequency
2.5
SR+
VCC = 5, 15 V
VCC = 2.7 V
2.0
1.5
SR–
1.0
VCC = 2.7, 5, & 15 V
0.5
1
0
–40 –25 –10 5
0
2.5 4.0 5.5 7.0 8.5 10.0 11.5 13.0 14.5 16.0
VCC – Supply Voltage –V
20 35 50 65 80 95 110 125
TA – Free-Air Temperature – °C
Figure 23. Gain Bandwidth Product vs Supply Voltage
10
4
VCC – Supply Voltage – V
Figure 19. Output Impedance vs Frequency
10
2
Phase – °
Z o – Output Impedance – W
10k
Figure 24. Slew Rate vs Free-Air Temperature
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Typical Characteristics (continued)
at TA = 25°C and VCC = 5 V (unless otherwise noted)
4
70
3
Input Referred Voltage Noise – mV
80
Phase Margin – °
60
50
40
30
20
10
2
1
0
–1
–2
–3
0
–4
10
100
1k
CL – Capacitive Load – pF
0
10k
2
3
5
7
6
8
9
10
Figure 26. Voltage Noise Over a 10-Second Period
8
4
7
3
1.5
2
1.0
2.0
3
VIN
2
–1
2
IN
VO
V
1
–1
–0.5
–1.0
VO
–1.5
0
– Input Voltage – V
3
0
0.0
IN
0
4
1
0.5
V
1
– Input Voltage – V
5
V – Output Voltage – V
O
VIN
6
–2
–1
1
2
3
4
5
–1
6
0
1
2
AV = 1
120
–150
60
VO
40
20
VO – Output Voltage – mV
0
V IN – Input Voltage – mV
140
80
7
200
VIN
150
100
6
150
100
100
0
50
–100
0
–50
IN
VIN
5
Figure 28. Large-Signal Step Response
200
300
160
4
AV = –1
Figure 27. Large-Signal Step Response
180
3
t – Time – ms
t – Time – ms
– Input Voltage – mV
0
VO
V
–1
V – Output Voltage – mV
O
4
t – Time – s
Figure 25. Phase Margin vs Capacitive Load
V – Output Voltage – V
O
1
–100
0
–20
–50 0
–150
–200
50 100 150 200 250 300 350 400 450 500
0
200
400
600
t – Time – ms
t – Time – ms
AV = 1
AV = –1
Figure 29. Small-Signal Step Response
800 1000 1200
Figure 30. Small-Signal Step Response
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7 Detailed Description
7.1 Overview
The TLV6003 is a nanopower operational amplifier consuming only 980 nA per channel, while offering very low
maximum offset. Reverse battery protection guards the amplifier from overcurrent conditions due to improper
battery installation. The TLV6003 is based on a rail-to-rail bipolar technology that is specifically designed to allow
high common-mode-range functionality. For harsh environments, the inputs can be taken 5 V greater than the
positive supply rail without damage to the device. Offset is specified by characterization to an ambient
temperature of –55°C, making the TLV6003 a good choice for low-temperature industrial automation.
7.2 Functional Block Diagram
VCC
VBIAS1
IN+
IN±
VBIAS2
Class AB
Control
Circuitry
OUT
GND
12
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7.3 Feature Description
7.3.1 Reverse-Battery Protection
The TLV6003 is protected against reverse-battery voltage up to 18 V. When subjected to reverse-battery
conditions, the supply current is typically 50 nA at 25°C (inputs grounded and outputs open). This current is
determined by the leakage of internal Schottky diodes, and therefore increases as the ambient temperature
increases.
When subjected to reverse-battery conditions, and negative voltages are applied to the inputs or outputs, the
input ESD structure conducts current; limit this current to less than 10 mA. If the inputs or outputs are referred to
ground rather than midrail, no extra precautions are required.
7.3.2 Common-Mode Input Range
The TLV6003 has rail-to-rail inputs and outputs. For common-mode inputs from –0.1 V to VCC – 0.8 V, a PNP
differential pair provides the gain.
For inputs between VCC – 0.8 V and VCC, two NPN emitter followers buffering a second PNP differential pair
provide the gain.
This special combination of a NPN and PNP differential pair enables the inputs to be taken 5 V greater than VCC.
As the inputs rise to greater than VCC, the NPNs change from functioning as transistors to functioning as diodes.
This change leads to an increase in input bias current. The second PNP differential pair continues to function
normally as the inputs exceed VCC.
The TLV6003 has a negative common-mode input voltage range that can fall to less than VGND by 100 mV. If the
inputs are taken to less than VGND – 0.1, reduced open-loop gain will be observed.
7.4 Device Functional Modes
The TLV6003 has a single functional mode and is operational when the power-supply voltage is greater than 2.5
V. The maximum specified power-supply voltage for the TLV6003 is 16 V.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Drive a Capacitive Load
The TLV6003 is internally compensated for stable unity-gain operation, with a 5.5-kHz typical gain bandwidth.
However, the unity gain follower is the most sensitive configuration to capacitive load. The combination of a
capacitive load placed directly on the output of an amplifier along with the amplifier output impedance creates a
phase lag, which reduces the phase margin of the amplifier. If the phase margin is significantly reduced, the
response will be underdamped, which causes peaking in the transfer function. This condition creates very low
phase margin, and leads to excessive ringing or oscillations.
In order to drive heavy (> 50 pF) capacitive loads, an isolation resistor (RISO) must be used, as shown in
Figure 31. By using this isolation resistor, the capacitive load is isolated from the amplifier output. The higher the
value of RISO, the more stable the amplifier. If the value of RISO is sufficiently high, the feedback loop is stable,
independent of the value of CL. However, larger values of RISO result in reduced output swing and reduced
output current drive. The recommended value for RISO is 30 kΩ to 50 kΩ.
-
RISO
VOUT
VIN
+
CL
Figure 31. Resistive Isolation of Capacitive Load
14
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8.2 Typical Application
Figure 32 shows a simple micropower potentiostat circuit for use with three-terminal unbiased CO sensors;
although, the design is applicable to many other type of three-terminal gas sensors or electrochemical cells.
The basic sensor has three electrodes: the sense or working electrode (WE), counter electrode (CE) and
reference electrode (RE). A current flows between the CE and WE proportional to the detected concentration.
The RE monitors the potential of the internal reference point. For an unbiased sensor, the WE and RE electrodes
must be maintained at the same potential by adjusting the bias on CE. Through the potentiostat circuit formed by
U1, the servo feedback action maintains the RE pin at a potential set by VREF.
R1 maintains stability due to the large capacitance of the sensor.
C1 and R2 form the potentiostat integrator and set the feedback time constant.
U2 forms a transimpedance amplifier (TIA) to convert the resulting sensor current into a proportional voltage. The
transimpedance gain, and resulting sensitivity, is set by RF according to Equation 1.
VTIA = (–I * RF) + VREF
(1)
RL is a load resistor with a value that is normally specified by the sensor manufacturer (typically, 10 Ω). The
potential at WE is set by the applied VREF.
Riso provides capacitive isolation and, combined with C2, form the output filter and ADC reservoir capacitor to
drive the ADC.
R1
10 k
C1
0.1µF
Potentiostat (Bias Loop)
CE
RE
CO Sensor
R2
10 NŸ
2.5V
U1
+
VREF
WE
Transimpedance Amplifier (I to V conversion)
ISENS
RF
Riso
49.9 k
RL
VREF
+
U2
VTIA
C2
1µF
Figure 32. Three Terminal CO Gas Sensor
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Typical Application (continued)
8.2.1 Design Requirements
For this example, an electrical model of a CO sensor is used to simulate the sensor performance, as shown in
Figure 33. The simulation is designed to model a CO sensor with a sensitivity of 69 nA/ppm. The supply voltage
and maximum ADC input voltage is 2.5 V, and the maximum concentration is 300 ppm.
CO Sensor
Model
VCE
10 NŸ
CE
300 Ÿ
260 mF
10 µF
2Ÿ
RE
±
2Ÿ
130 mF
2.5 V
10 NŸ
VREF
+
TLV6003
300 Ÿ
ISENS
VTIA
110 NŸ
0 - 20 µA
WE
2.5 V
10 Ÿ
±
VREF
+
TLV6003
Figure 33. CO Sensor Simulation Schematic
Table 1. Design Parameters
DESIGN PARAMETER
16
EXAMPLE VALUE
Supply voltage
2.5 V
Amplifier quiescent current
< 2 µA
Transimpedance amplifier
sensitivity
110 mV/µA
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8.2.2 Detailed Design Procedure
First, determine the VREF voltage. This voltage is a compromise between maximum headroom and resolution, as
well as allowance for the minimum swing on the CE terminal because the CE terminal generally goes negative in
relation to the RE potential as the concentration (sensor current) increases. Bench measurements found the
difference between CE and RE to be 180 mV at 300 ppm for this particular sensor.
To allow for negative CE swing, footroom, and voltage drop across the 10-kΩ resistor, 300 mV is chosen for
VREF.
Therefore, 300 mV is used as the minimum VZERO to add some headroom.
VZERO = VREF = 300 mV
where
•
•
VZERO is the zero concentration voltage.
VREF is the reference voltage (300 mV).
(2)
Next, calculate the maximum sensor current at highest expected concentration:
ISENSMAX = IPERPPM * ppmMAX = 69 nA * 300 ppm = 20.7 µA
where
•
•
•
ISENSMAX is the maximum expected sensor current.
IPERPPM is the manufacturer specified sensor current in Amps per ppm.
ppmMAX is the maximum required ppm reading.
(3)
Then, find the available output swing range greater than the reference voltage available for the measurement:
VSWING = VOUTMAX – VZERO = 2.5 V – 0.3 V = 2.2 V
where
•
•
VSWING is the expected change in output voltage
VOUTMAX is the maximum amplifer output swing (usually near VCC)
(4)
Finally, calculate the transimpedance resistor (RF) value using the maximum swing and the maximum sensor
current:
RF = VSWING / ISENSMAX = 2.2 V / 20.7 µA = 106.28 kΩ (use 110 kΩ for a common value)
(5)
8.2.3 Application Curve
0.3 V
20 PA
Current (10 P$/div)
Voltage (1 V/div)
2.5 V
VTIA
VCE
ISENS
Time (10 ms/div)
C012
Figure 34. Sensor Transient Response to Simulated 300-ppm CO Exposure
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9 Power Supply Recommendations
The TLV6003 is specified for operation from 2.5 V to 16 V (±1.25 V to ±8 V) over a –40°C to +125°C temperature
range.
CAUTION
Supply voltages larger than 17 V can permanently damage the device.
For proper operation, the power supplies must be properly decoupled. For decoupling the supply lines, place 100
nF capacitors as close as possible to the operational amplifier power supply pins. For single-supply operation,
place a capacitor between VCC and GND supply leads. For dual supplies, place one capacitor between VCC and
ground, and one capacitor between GND and ground.
Low-bandwidth nanopower devices do not have good high-frequency (> 1 kHz) AC PSRR rejection against highfrequency switching supplies and other 1-kHz and greater noise sources. Therefore, use extra supply filtering if
kilohertz or greater noise is expected on the power supply lines.
10 Layout
10.1 Layout Guidelines
•
•
•
•
•
Bypass the VCC pin to ground with a low ESR capacitor.
The best placement is closest to the VCC and ground pins.
Take care to minimize the loop area formed by the bypass capacitor connection between VCC and ground.
Connect the ground pin to the PCB ground plane at the pin of the device.
Place the feedback components as close as possible to the device to minimize strays.
10.2 Layout Example
VCC
CBYPASS
VOUT
OUT
Minimize parasitic
inductance by placing
bypass capacitor
close to VCC.
VCC
GND
+IN
Keep high
impedance input
signal away from
noisy traces.
-IN
VIN
RF
Route trace under
package for output to
feedback resistor
connection.
Figure 35. SOT-23 Layout Example (Top View)
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
• TINA-TI SPICE-Based Analog Simulation Program
• DIP Adapter Evaluation Module
• TI Universal Operational Amplifier Evaluation Module
• TI Filter Design Tool
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
• Single-supply, low-side, unidirectional current-sensing circuit application report
• Simplifying Environmental Measurements in Power Conscious Factory and Building Automation Systems With
Nanopower Op Amps application note
• GPIO Pins Power Signal Chain in Personal Electronics Running on Li-Ion Batteries application brief
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TLV6003DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
1NE9
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
