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TLV62065-Q1
SLVSB92C – JANUARY 2012 – REVISED SEPTEMBER 2016
TLV62065-Q1 3-MHz 2-A Step-Down Converter in 2-mm × 2-mm WSON Package
1 Features
3 Description
•
•
The TLV62065-Q1 device is a highly-efficient
synchronous step-down DC-DC converter with
adjustable output voltage. The device operates at a
switching frequency of 3 MHz and provides up to 2 A
of output current.
1
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Test Guidance With the Following
Results:
– Device Temperature Grade 2: –40°C to
+105°C Ambient Operating Temperature
Range
– Device HBM ESD Classification Level 2
– Device CDM ESD Classification Level C4B
VIN Range from 2.9 to 5.5 V
Up to 97% Efficiency
Power-Save Mode or Fixed Frequency PWM
Mode
Output Voltage Accuracy in PWM Mode ±2%
Output Capacitor Discharge Function
Typical 18-µA Quiescent Current
100% Duty Cycle for Lowest Dropout
Clock Dithering
Available in a 2-mm × 2-mm × 0.75-mm WSON
In the shutdown mode, the current consumption is
reduced to less than 1 µA and an internal circuit
discharges the output capacitor.
The TLV62065-Q1 device operates with a 1-µH
inductor and 10-µF output capacitor.
The TLV62065-Q1 device is available in a small
2-mm × 2-mm × 0.75-mm 8-pin WSON package.
Device Information(1)
2 Applications
•
•
•
With an input voltage range of 2.9 to 5.5 V, the
device is a perfect fit for power conversion from a 5-V
or 3.3-V system supply rail. The TLV62065-Q1 device
enters power-save mode operation at light-load
currents to maintain high efficiency over the entire
load current range. For low-noise applications, the
TLV62065-Q1 device can be forced into fixedfrequency PWM mode by pulling the MODE pin high.
Automotive Infotainment and Cluster
Advanced Driver Assistance System (ADAS)
Automotive Display
PART NUMBER
TLV62065-Q1
EN
MODE
AGND
PGND
L
1 µH
SW
R1
360 kΩ
FB
R2
180 kΩ
2.00 mm × 2.00 mm
Efficiency vs Load Current
100
VOUT
1.8 V 2 A
95
90
Cff
COUT
22 pF 10 µF
Copyright © 2016, Texas Instruments Incorporated
85
Efficiency (%)
CIN
10 µF
PVIN
AVIN
WSON (8)
BODY SIZE (NOM)
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Typical Application Circuit
VIN = 2.9 to 5.5 V
PACKAGE
80
75
70
65
60
L = 1.2 µH (NRG4026T 1R2)
COUT = 22 µF (0603 size)
VOUT = 3.3 V
Mode: Auto PFM/PWM
55
50
0
0.25
0.5
0.75
1
1.25
Load Current (A)
VIN = 3.7 V
VIN = 4.2 V
VIN = 5 V
1.5
1.75
2
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLV62065-Q1
SLVSB92C – JANUARY 2012 – REVISED SEPTEMBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
4
5
5
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 11
7.1 Overview ................................................................. 11
7.2 Functional Block Diagram ....................................... 11
7.3 Feature Description................................................. 12
7.4 Device Functional Modes........................................ 13
8
Application and Implementation ........................ 15
8.1 Application Information............................................ 15
8.2 Typical Application ................................................. 15
9 Power Supply Recommendations...................... 18
10 Layout................................................................... 18
10.1 Layout Guidelines ................................................. 18
10.2 Layout Example .................................................... 19
11 Device and Documentation Support ................. 19
11.1
11.2
11.3
11.4
11.5
11.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resource............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
19
19
19
19
19
20
12 Mechanical, Packaging, and Orderable
Information ........................................................... 20
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (June 2015) to Revision C
Page
•
Deleted the junction temperature from the Recommended Operating Conditions table ....................................................... 4
•
Added a description of the clock dithering feature to the Feature Description section ....................................................... 13
•
Added the Receiving Notification of Documentation Updates section ................................................................................ 19
Changes from Revision A (March 2012) to Revision B
Page
•
Changed the Description section to state that the TLV62065-Q1 device has an adjustable output voltage. ........................ 1
•
Added the Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device
Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information
section ................................................................................................................................................................................... 1
•
Changed the Thermal Information values ............................................................................................................................. 4
•
Deleted the Parameter Measurement Information section because the circuit is similar to the application circuit in
the Typical Application section ............................................................................................................................................. 11
•
Changed fc to fz and R2 to R1 in the feed-forward capacitor equations in the Output Voltage Setting section .................... 16
•
Deleted the List of Inductors and List of Capacitors tables .................................................................................................. 16
Changes from Original (January 2012) to Revision A
Page
•
Update automotive qualitifcation description and add temperature grade ............................................................................. 1
•
Update Absolute Maximum Ratings ....................................................................................................................................... 4
•
Update Electrical Characteristics - Shutdown current max rating ......................................................................................... 5
2
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SLVSB92C – JANUARY 2012 – REVISED SEPTEMBER 2016
5 Pin Configuration and Functions
DSG Package
8-Pin WSON With Exposed Thermal Pad
Top View
PGND
1
SW
2
AGND
3
FB
4
Thermal
Pad
8
PVIN
7
AVIN
6
MODE
5
EN
Pin Functions
PIN
TYPE
DESCRIPTION
NAME
NO.
AGND
3
IN
Analog GND supply pin for the control circuit.
AVIN
7
IN
Analog VIN power supply for the control circuit. This pin must be connected to the PVIN pin and the
input capacitor.
EN
5
IN
EN is the enable pin of the device. Pulling this pin low forces the device into shutdown mode.
Pulling this pin high enables the device. This pin must be terminated.
FB
4
IN
Feedback pin for the internal regulation loop. Connect the external resistor divider to this pin. In the
case of fixed output voltage option, connect this pin directly to the output capacitor.
MODE
6
IN
When the MODE pin is high, the device is forced to operate in fixed-frequency PWM mode. When
the MODE pin is low , the device enters the power-save mode with automatic transition from PFM
mode to fixed-frequency PWM mode. This pin must be terminated.
PGND
1
PWR
GND supply pin for the output stage
PVIN
8
PWR
VIN power-supply pin for the output stage
SW
2
OUT
SW is the switch pin and is connected to the internal MOSFET switches. Connect the external
inductor between this pin and the output capacitor.
Thermal pad
—
For good thermal performance, this pad must be soldered to the land pattern on the PCB. This pad
should be used as device GND.
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SLVSB92C – JANUARY 2012 – REVISED SEPTEMBER 2016
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Voltage (2)
Current (source)
MIN
MAX
AVIN, PVIN
–0.3
7
EN, MODE, FB
–0.3
(VIN + 0.3) < 7
SW
–0.3
7
Peak output
UNIT
V
Internally limited
A
Junction temperature, TJ
–40
140
°C
Storage temperature, Tstg
–65
150
°C
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to the network ground pin.
6.2 ESD Ratings
VALUE
Human body model (HBM), per AEC Q100-002 (1)
V(ESD)
(1)
Electrostatic discharge
Charged device model (CDM), per
AEC Q100-011
UNIT
±2000
Corner pins (1, 4, 5, and 8)
±750
Other pins
±500
V
AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
MIN
AVIN , PVIN
Supply voltage
NOM
2.9
5.5
Output current capability
2000
Output voltage for adjustable voltage
0.8
L
Effective inductance
0.7
COUT
Effective output-capacitance
4.5
TA
(1)
Operating ambient temperature
MAX
(1)
UNIT
V
mA
VIN
V
1
1.6
µH
10
22
µF
105
°C
–40
In applications where high power dissipation, poor package thermal resistance, or both are present, the maximum ambient temperature
may have to be derated. Maximum ambient temperature (TA(max)) is dependent on the maximum operating junction temperature
(TJ(max)), the maximum power dissipation of the device in the application (PD(max)), and the junction-to-ambient thermal resistance of the
device or package in the application (RθJA), as given by the following equation: TA(max)= TJ(max) – (RθJA × PD(max))
6.4 Thermal Information
TLV62065-Q1
THERMAL METRIC (1)
DSG (WSON)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
58.1
°C/W
RθJC(top)
Junction-to-case(top) thermal resistance
67.4
°C/W
RθJB
Junction-to-board thermal resistance
29.2
°C/W
ψJT
Junction-to-top characterization parameter
1.1
°C/W
ψJB
Junction-to-board characterization parameter
29.8
°C/W
RθJC(bot)
Junction-to-case(bottom) thermal resistance
7.2
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SLVSB92C – JANUARY 2012 – REVISED SEPTEMBER 2016
6.5 Electrical Characteristics
Over full operating ambient temperature range, typical values are at TA = 25°C. Unless otherwise noted, specifications apply
for condition VIN = EN = 3.6 V. External components CIN = 10 μF 0603, COUT = 10 μF 0603, L = 1 μH
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
VIN
Input voltage range
2.9
IQ
Operating quiescent current
IOUT = 0 mA, device operating in PFM mode
and not device not switching
ISD
Shutdown current
EN = GND, current into AVIN and PVIN combined
VUVLO
Undervoltage lockout threshold
5.5
18
0.1
5
V
μA
Falling
1.73
1.78
1.83
Rising
1.9
1.95
1.99
μA
V
ENABLE, MODE
VIH
High-level input voltage
2.9 V ≤ VIN ≤ 5.5 V
1
5.5
VIL
Low-level input voltage
2.9 V ≤ VIN ≤ 5.5 V
0
0.4
V
IIN
Input bias current
EN, MODE tied to GND or AVIN
0.01
1
μA
120
180
95
150
90
130
75
100
V
POWER SWITCH
VIN = 3.6 V
(1)
rDS(on)
High-side MOSFET on-resistance
rDS(on)
Low-side MOSFET on-resistance
ILIMF
Forward current limit MOSFET
high-side and low-side
3 V ≤ VIN ≤ 3.6 V
Thermal shutdown
Increasing junction temperature
150
Thermal shutdown hysteresis
Decreasing junction temperature
10
TSD
VIN = 5 V
(1)
VIN = 3.6 V (1)
VIN = 5 V
(1)
2300
mΩ
mΩ
2750
mA
°C
OUTPUT
Vref
Reference voltage
VFB(PWM)
Feedback voltage, PWM mode
PWM operation, MODE = VIN ,
2.9 V ≤ VIN ≤ 5.5 V, 0-mA load
VFB(PFM)
Feedback voltage, PFM mode,
voltage positioning
Device in PFM mode, voltage positioning active (2)
–2%
0%
Line regulation
R(Discharge)
Internal discharge resistor
mV
2%
1%
Load regulation
VFB
(1)
(2)
600
Activated with EN = GND, 2.9 V ≤ VIN≤ 5.5 V, 0.8
V ≤ VOUT≤ 3.6 V
–0.5
%/A
0
%/V
200
Ω
Maximum value applies for TJ = 85°C.
In PFM mode, the internal reference voltage is set to typ. 1.01 × Vref. See the Application and Implementation section.
6.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
2.6
3
3.4
MHz
OSCILLATOR
fSW
Oscillator frequency
2.9 V ≤ VIN ≤ 5.5 V
Startup time
Time from active EN to reach 95%
of VOUT
OUTPUT
tSTART
500
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6.7 Typical Characteristics
Table 1. Table of Graphs
FIGURE
η
Efficiency
Output Voltage Accuracy
Load Current, VOUT = 1.2 V, Auto PF//PWM Mode, Linear Scale
Figure 1
Load Current, VOUT = 1.8 V, Auto PFM/PWM Mode, Linear Scale
Figure 2
Load Current, VOUT = 3.3 V, PFM/PWM Mode, Linear Scale
Figure 3
Load Current, VOUT = 1.8 V, Auto PFM/PWM Mode vs. Forced PWM
Mode, Logarithmic Scale
Figure 4
Load Current, VOUT = 1.8 V, Auto PFM/PWM Mode
Figure 5
Load Current, VOUT = 1.8 V, Forced PWM Mode
Figure 6
Shutdown Current
Input Voltage and Ambient Temperature
Figure 7
Quiescent Current
Input Voltage
Figure 8
Oscillator Frequency
Input Voltage
Figure 9
Static Drain-Source On-State
Resistance
Input Voltage, Low-Side Switch
Figure 10
Input Voltage, High-Side Switch
Figure 11
RDISCHARGE
Input Voltage vs. VOUT
Figure 12
PWM Mode, VIN = 3.6 V, VOUT = 1.8 V, 500 mA, L = 1.2 μH, COUT = 10 μF
Figure 13
PFM Mode, VIN = 3.6 V, VOUT = 1.8 V, 20 mA, L = 1.2 μH, COUT = 10 μF
Figure 14
PWM Mode, VIN = 3.6 V, VOUT = 1.2 V, 0.2 mA to 1 A
Figure 15
PFM Mode, VIN = 3.6 V, VOUT = 1.2 V, 20 mA to 250 mA
Figure 16
VIN = 3.6 V, VOUT = 1.8 V, 200 mA to 1500 mA
Figure 17
PWM Mode, VIN = 3.6 V to 4.2 V, VOUT = 1.8 V, 500 mA
Figure 18
Typical Operation
Load Transient
Line Transient
Figure 19
VIN = 3.6 V, VOUT = 1.8 V, Load = 2.2-Ω
Figure 20
Output Discharge
VIN = 3.6 V, VOUT = 1.8 V, No Load
Figure 21
100
100
95
95
90
90
85
85
Efficiency (%)
Efficiency (%)
PFM Mode, VIN = 3.6 V to 4.2 V, VOUT = 1.8 V, 500 mA
Startup into Load
80
75
70
65
55
50
0
0.25
0.5
0.75
1
1.25
Load Current (A)
VOUT = 1.2 V
L = 1.2 µH (NRG4026T 1R2)
1.5
1.75
75
70
65
VIN = 3 V
VIN = 3.3 V
VIN = 3.6 V
VIN = 4.2 V
VIN = 5 V
60
80
55
2
Linear Scale
COUT = 10 µF (0603 size)
50
0
0.25
0.5
0.75
1
1.25
Load Current (A)
VOUT = 1.8 V
L = 1.2 µH (NRG4026T 1R2)
Figure 1. Efficiency vs Load Current
Auto PFM and PWM MODE
6
VIN = 3 V
VIN = 3.3 V
VIN = 3.6 V
VIN = 4.2 V
VIN = 5 V
60
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1.5
1.75
2
Linear Scale
COUT = 10 µF (0603 size)
Figure 2. Efficiency vs Load Current
Auto PFM and PWM MODE
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100
100
95
90
90
80
85
70
Efficiency (%)
Efficiency (%)
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80
75
70
50
40
Auto PFM/
PWM Mode
Forced
PWM Mode
VIN = 3.3 V
VIN = 3.6 V
VIN = 4.2 V
VIN = 5 V
20
60
VIN = 3.7 V
VIN = 4.2 V
VIN = 5 V
55
0
0.25
0.5
0.75
1
1.25
Load Current (A)
VOUT = 3.3 V
L = 1.2 µH (NRG4026T 1R2)
1.5
1.75
10
0
0.001
2
Linear Scale
COUT = 22 µF (0603 size)
Figure 3. Efficiency vs Load Current
Auto PFM and PWM MODE
1.890
1.872
1.872
1.854 Voltage Positioning PFM Mode
1.854
1.836
1.836
1.818
PWM Mode
1.800
1.782
1.764
VIN = 3.3 V
VIN = 3.6 V
VIN = 4.2 V
VIN = 5 V
1.728
1.710
0.001
0.01
L = 1 µH
0.1
Load Current (A)
1
VOUT = 1.8 V
1
10
Logarithmic Scale
COUT = 10 µF (0603 size)
1.818
1.800
1.782
1.764
VIN = 3.3 V
VIN = 3.6 V
VIN = 4.2 V
VIN = 5 V
1.746
1.728
1.710
0.001
10
0.01
L = 1 µH
COUT = 10 µF
Figure 5. Output Voltage Accuracy vs Load Current
Auto PFM and PWM MODE
1
0.1
Load Current (A)
Figure 4. Efficiency vs Load Current
Auto PFM and PWM Mode vs. Forced PWM Mode
1.890
1.746
0.01
VOUT = 1.8 V
L = 1.2 µH (NRG4026T 1R2)
Output Voltage DC (V)
Output Voltage DC (V)
Forced
PWM Mode
60
30
65
50
Auto PFM/
PWM Mode
0.1
Load Current (A)
1
10
VOUT = 1.8 V
COUT = 10 µF
Figure 6. Output Voltage Accuracy vs Load Current
Forced PWM MODE
25
TA = –40°C
TA = 25°C
TA = 85°C
20
Quiescent Current (µA)
Shutdown Current (µA)
0.75
0.50
15
10
0.25
5
0
2.5
3
3.5
4
4.5
Input Voltage (V)
5
5.5
6
Figure 7. Shutdown Current vs Input Voltage and Ambient
Temperature
0
2.5
TA = –40°C
TA = 25°C
TA = 85°C
3
3.5
4
4.5
Input Voltage (V)
5
5.5
6
Figure 8. Quiescent Current vs Input Voltage
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3.1
0.12
3.05
0.1
3
0.08
RDSON (Ω)
Oscillator Frequency (MHz)
SLVSB92C – JANUARY 2012 – REVISED SEPTEMBER 2016
2.95
2.9
0.04
2.85
2.8
2.5
0.06
TA = –40°C
TA = 25°C
TA = 85°C
3
3.5
4
4.5
Input Voltage (V)
5
5.5
TJ = –40°C
TJ = 25°C
TJ = 85°C
0.02
0
2.5
6
3
3.5
4
4.5
Input Voltage (V)
5
5.5
6
Low-Side Switch
Figure 9. Oscillator Frequency vs Input Voltage
Figure 10. Static Drain-Source On-State Resistance vs Input
Voltage
600
0.2
VO = 1.2 V
VO = 1.8 V
VO = 3.3 V
0.18
500
0.16
400
Rdischarge (Ω)
RDSON (Ω)
0.14
0.12
0.1
0.08
200
0.06
0.04
100
TJ = –40°C
TJ = 25°C
TJ = 85°C
0.02
0
2.5
300
3
3.5
4
4.5
Input Voltage (V)
5
5.5
6
0
2.5
3
3.5
4
4.5
Input Voltage (V)
5
5.5
6
High-Side Switch
Figure 11. Static Drain-Source On-State Resistance vs Input
Voltage
Figure 12. RDISCHARGE vs Input Voltage
VOUT 50 mV/Div
VOUT 50 mV/Div
SW 2 V/Div
SW 2 V/Div
ICOIL 500 mA/Div
ICOIL 200 mA/Div
Time Base - 4 µs/Div
Time Base - 100 ns/Div
VIN = 3.6 V
COUT = 10 µF
VOUT = 1.8 V
L = 1.2 µH
MODE = GND
IOUT = 500 mA
Figure 13. Typical Operation (PWM Mode)
8
VIN = 3.6 V
COUT = 10 µF
VOUT = 1.8 V
L = 1.2 µH
MODE = GND
IOUT = 20 mA
Figure 14. Typical Operation (PFM Mode)
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VOUT 100 mV/Div
VOUT 100 mV/Div
SW 2 V/Div
SW 2 V/Div
ICOIL1 A/Div
ICOIL1 A/Div
ILOAD 500 mA/Div
ILOAD 500 mA/Div
Time Base - 10 µs/Div
VIN = 3.6 V
Time Base - 10 µs/Div
VOUT = 1.2 V
IOUT = 0.2 to 1 A
VIN = 3.6 V
Figure 15. Load Transient Response, MODE = VIN
PWM Mode 0.2 A To 1 A
VOUT
200 mV/Div
VOUT = 1.2 V
IOUT = 20 to 250 mA
Figure 16. Load Transient
PFM Mode 20 mA to 250 mA
VIN
500 mV/Div
ILOAD
2 A/Div
VOUT
50 mV/Div
IINDUCTOR
1 A/Div
Time Base - 100 µs/Div
Time Base - 100 µs/Div
VIN = 3.6 V
COUT = 10 µF
VOUT = 1.8 V
L = 1.2 µH
IOUT = 200 to 1500 mA
Figure 17. Load Transient Response
200 mA To 1500 mA
VIN = 3.6 to 4.2 V
COUT = 10 µF
VOUT = 1.8 V
L = 1.2 µH
IOUT = 500 mA
Figure 18. Line Transient Response PWM Mode
EN
2 V/Div
VIN
500 mV/Div
VOUT
1 V/Div
2 A/Div
ICOIL
500 mA/Div
VOUT
50 mV/Div
ILOAD
500 mA/Div
Time Base - 100 µs/Div
Time Base - 100 µs/Div
VIN = 3.6 to 4.2 V
COUT = 10 µF
VOUT = 1.8 V
L = 1.2 µH
IOUT = 500 mA
VIN = 3.6 V
COUT = 10 µF
Figure 19. Line Transient PFM Mode
VOUT = 1.8 V
L = 1.2 µH
Load = 2.2 Ω
Figure 20. Startup Into Load
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EN
1 V/Div
SW
2 V/Div
VOUT
1 V/Div
Time Base - 2 ms/Div
VIN = 3.6 V
COUT = 10 µF
VOUT = 1.8 V
No load
Figure 21. Output Discharge
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7 Detailed Description
7.1 Overview
The TLV62065-Q1 step-down converter operates with a typical 3-MHz fixed-frequency pulse-width modulation
(PWM) at moderate to heavy load currents. At light load currents, the converter can automatically enter powersave mode, and then operates in pulse-frequency mode (PFM).
During PWM operation, the converter uses a unique fast-response voltage-mode controller scheme with input
voltage feed-forward to achieve good line and load regulation, allowing the use of small ceramic input and output
capacitors. At the beginning of each clock cycle, the high-side MOSFET switch is turned on. The current now
flows from the input capacitor through the high-side MOSFET switch through the inductor to the output capacitor
and load. During this phase, the current ramps up until the PWM comparator trips and the control logic turns off
the switch. The current-limit comparator also turns off the switch in case the current-limit of the high-side
MOSFET switch is exceeded. After a dead time preventing shoot-through current, the low-side MOSFET rectifier
is turned on and the inductor current ramps down. The current now flows from the inductor to the output
capacitor and to the load. The current returns back to the inductor through the low-side MOSFET rectifier.
The next cycle is initiated by the clock signal again turning off the low-side MOSFET rectifier and turning on the
high-side MOSFET switch.
7.2 Functional Block Diagram
AVIN
PVIN
Current
Limit Comparator
Thermal
Shutdown
Undervoltage
Lockout 1.8 V
Limit
High Side
PFM Comparator
Reference
0.6-V VREF
FB
VREF
Soft-start
VOUT Ramp
Control
Gate Driver
Anti
Shoot-Through
Error Amplifier
Control Stage
VREF
SW
Integrator
FB
Zero-Pole
AMP.
PWM
Comp.
Limit
Low Side
MODE
Sawtooth
Generator
3-MHz
Clock
Current
Limit Comparator
RDischarge
AGND
EN
PGND
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7.3 Feature Description
7.3.1 Enable
The device is enabled by setting the EN pin high. At first, the internal reference is activated and the internal
analog circuits are settled. Afterwards, the soft start is activated and the output voltage is ramped up. The output
voltages reaches 95% of the nominal value within tSTART of typically 500 µs after the device has been enabled.
The EN input can be used to control power sequencing in a system with various DC-DC converters. To drive the
EN pin high and get a sequencing of supply rails, connect the EN pin to the output of another converter. With EN
= GND, the device enters shutdown mode. In this mode, all circuits are disabled and the SW pin is connected to
PGND through an internal resistor to discharge the output.
7.3.2 Mode Selection
The MODE pin allows mode selection between forced PWM mode and power-save mode.
Connecting this pin to GND enables the power-save mode with automatic transition between PWM and PFM
mode. Pulling the MODE pin high forces the converter to operate in fixed-frequency PWM mode even at light
load currents which allows simple filtering of the switching frequency for noise-sensitive applications. In this
mode, the efficiency is lower compared to the power-save mode during light loads.
The condition of the MODE pin can be changed during operation and allows efficient power management by
adjusting the operation mode of the converter to the specific system requirements.
7.3.3 Soft-Start Functionality
The TLV62065-Q1 device has an internal soft-start circuit that controls the ramp-up of the output voltage. When
the converter is enabled and the input voltage is above the undervoltage lockout threshold, VUVLO, the output
voltage ramps up from 5% to 95% of the nominal value within a tRamp of 250 µs (typical).
This ramping limits the inrush current in the converter during startup and prevents possible input-voltage drops
when a battery or high-impedance power source is used.
During soft start, the switch current limit is reduced to 1/3 of the nominal value, ILIMF, until the output voltage
reaches 1/3 of the nominal value. When the output voltage trips this threshold, the device operates with the
nominal current-limit, ILIMF.
7.3.4 Internal Current-Limit and Foldback Current-Limit For Short-Circuit Protection
During normal operation, the high-side and low-side MOSFET switches are protected by the current limits, ILIMF.
When the high-side MOSFET switch reaches the current limit, it is turned off and the low-side MOSFET switch is
turned on. The high-side MOSFET switch can only turn on again when the current in the low-side MOSFET
switch decreases below the current-limit, ILIMF. The device is capable of providing peak inductor currents up to
the internal-current limit ILIMF..
As soon as the switch-current limits are hit and the output voltage falls below 1/3 of the nominal output voltage
because of an overload or short-circuit condition, the foldback current limit is enabled. In this case, the switchcurrent limit is reduced to 1/3 of the nominal value, ILIMF.
Because the short-circuit protection is enabled during startup, the device does not deliver more than 1/3 of the
nominal current-limit, ILIMF, until the output voltage exceeds 1/3 of the nominal output voltage. This must be
considered when a load which acts as a current sink is connected to the output of the converter.
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Feature Description (continued)
7.3.5 100% Duty Cycle Low-Dropout Operation
The device begins to enter 100% duty cycle mode as the input voltage comes close to the nominal output
voltage. In order to maintain the output voltage, the high-side MOSFET switch is turned on 100% for one or more
cycles.
With further decreasing VIN, the high-side MOSFET switch is turned on completely. In this case, the converter
offers a low input-to-output voltage differential. This differential voltage is particularly useful in battery-powered
applications to achieve longest operation time by taking full advantage of the whole battery voltage range.
The minimum input voltage to maintain regulation depends on the load current and output voltage, and is
calculated using Equation 1.
VINmin = VOmax + IOmax × (RDS(on)max + RL)
where
•
•
•
•
IOmax = maximum output current
RDS(on)max = maximum P-channel switch RDS(on)
RL = DC resistance of the inductor
VOmax = nominal output voltage plus maximum output voltage tolerance
(1)
7.3.6 Clock Dithering
To reduce the noise level of switch-frequency harmonics in the higher RF bands, the TLV62065-Q1 device has a
built-in clock-dithering circuit. The oscillator frequency is slightly modulated with a sub clock which causes a clock
dither of ±3 ns (typical).
7.3.7 Undervoltage Lockout
The undervoltage lockout (UVLO) circuit prevents the device from malfunctioning at low input voltages and from
excessive discharge of the battery. The UVLO circuit disables the output stage of the converter once the falling
VIN trips the undervoltage lockout threshold VUVLO. The undervoltage lockout threshold VUVLO for falling VIN is
typically 1.78 V. The device begins operation when the rising VIN trips the undervoltage lockout threshold VUVLO
again at 1.95 V (typical).
7.3.8 Output Capacitor Discharge
With EN = GND, the device enters shutdown mode and disables all internal circuits. An internal resistor connects
the SW pin is to PGND to discharge the output capacitor. This feature ensures startup with a discharged output
capacitor when the converter is enabled again and prevents a floating charge on the output capacitor. The output
voltage ramps up monotonic, starting from 0 V.
7.3.9 Thermal Shutdown
As soon as the junction temperature, TJ, exceeds 150°C (typical) the device goes into thermal shutdown. In this
mode, the high-side and low-side MOSFETs are turned off. The device continues operation with a soft-start when
the junction temperature falls below the thermal shutdown hysteresis.
7.4 Device Functional Modes
7.4.1 Power Save Mode
Pulling the TLV62065-Q1 MODE pin low enables power-save mode. If the load current decreases, the converter
enters power-save mode operation automatically. In power-save mode, the converter skips switching and
operates with reduced frequency in the PFM mode with a minimum quiescent current to maintain high efficiency.
The converter positions the output voltage 1% (typical) above the nominal output voltage. This voltagepositioning feature minimizes voltage drops caused by a sudden load step.
The transition from PWM mode to PFM mode occurs when the inductor current in the low-side MOSFET switch
becomes zero, which indicates discontinuous conduction mode.
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Device Functional Modes (continued)
In power-save mode, a PFM comparator monitors the output voltage. As the output voltage falls below the PFM
comparator threshold of VOUTnominal + 1%, the device begins a PFM current pulse. For this pulse, the high-side
MOSFET switch turns on and the inductor current ramps up. After the on-time expires, the switch is turned off
and the low-side MOSFET switch is turned on until the inductor current becomes zero.
The converter effectively delivers a current to the output capacitor and the load. If the load is below the delivered
current, the output voltage rises. If the output voltage is equal to or higher than the PFM comparator threshold,
the device stops switching and enters a sleep mode with 18-µA current consumption (typical).
In case the output voltage is still below the PFM comparator threshold, further PFM current pulses are generated
until the PFM comparator threshold is reached. The converter begins switching again when the output voltage
drops below the PFM comparator threshold because of the load current.
The device leaves PFM mode and goes to PWM mode in case the output current can no longer be supported in
PFM mode.
Output voltage
Voltage Positioning
VOUT + 1%
PFM Comparator
threshold
Light load
PFM Mode
VOUT (PWM)
Moderate to heavy load
PWM Mode
Figure 22. Power Save Mode Operation With Automatic Mode Transition
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TLV62065-Q1 device is a highly efficient, synchronous step-down, DC-DC converter with an adjustable
output voltage and an output current of up to 2 A. The device can be used in buck converter applications with an
input range from 2.9 to 5.5 V.
8.2 Typical Application
The typical application circuit (see Figure 23) is optimized for an output voltage of 1.8 V and a load current of 2 A
maximum for an input voltage from 2.9 to 5.5 V.
VIN = 2.9 to 5.5 V
CIN
10 µF
PVIN
AVIN
EN
MODE
AGND
PGND
L
1 µH
VOUT
1.8 V 2 A
SW
R1
360 kΩ
FB
R2
180 kΩ
Cff
COUT
22 pF 10 µF
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Figure 23. TLV62065-Q1 1.8-V Adjustable Output Voltage Configuration
8.2.1 Design Requirements
The input voltage for this device must be from 2.9 V to 5.5 V. The output voltage must be set using an external
voltage divider. The internal compensation network of the device is optimized for an LC output filter that is
composed of a 1-μH inductor and a 10-μF ceramic capacitor with a suitable external feed-forward capacitor
calculated based on the voltage divider resistor. The Recommended Operating Conditions table specifies the
allowed range for input voltages, output voltages, output current, inductance, and capacitance. The values listed
in this table must be followed when designing the regulator. Low-ESR ceramic capacitors should be used at the
input and output for better filtering and ripple performance. The Detailed Design Procedure section provides the
necessary equations and guidelines for selecting external components for this regulator.
8.2.2 Detailed Design Procedure
8.2.2.1 Output Voltage Setting
Use Equation 2 to calculate the output voltage.
VOUT
§
R1 ·
VREF u ¨ 1
¸
R
©
2¹
where
•
•
•
VREF is the internal reference voltage at 0.6 V (typical).
R1 is the feedback divider resistor connected between the VOUT and FB pins.
R2 is the feedback divider resistor connected between the FB pin and GND.
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Typical Application (continued)
To minimize the current through the feedback divider network, R2, should be within the range of 120 kΩ to 360
kΩ. To keep the network robust against noise the sum of R1 and R2 should not exceed approximately 1 MΩ.
However, lower resistor values can be used. An external feed-forward capacitor, Cff, is required for optimum
regulation performance. R1 and Cff place a zero in the loop. Use Equation 4 to calculate the value of Cff .
1
fZ
25 kHz
2 u S u R1 u Cff
(3)
1
Cff
2 u S u R1 u 25 kHz
(4)
8.2.2.2 Output Filter Design (inductor And Output Capacitor)
The internal compensation network of the TLV62065-Q1 device is optimized for an LC output filter with a corner
frequency that is calculated with Equation 5
1
fc
50 kHz
2 u S u 1 µH u 10 µF
(5)
The device operates with nominal inductors of 1 µH to 1.2 µH and with 10 µF to 22 µF small X5R and X7R
ceramic capacitors. The device is optimized for a 1-µH inductor and 10-µF output capacitor.
8.2.2.2.1 Inductor Selection
The inductor value has a direct effect on the ripple current. The selected inductor must be rated for the DC
resistance and saturation current. The inductor ripple current (ΔIL) decreases with higher inductance and
increases with higher VIN or VOUT.
Use Equation 6 to calculate the maximum inductor current in PWM mode under static load conditions. The
saturation current of the inductor should be rated higher than the maximum inductor current as calculated with
Equation 7. This value is recommended because during heavy load transients the inductor current rises above
the calculated value.
V
1 OUT
VIN
'IL VOUT u
/u¦
where
•
•
•
IL max
ΔIL = Peak-to-peak inductor ripple current
L = Inductor value
ƒ = Switching frequency (3 MHz typical)
IOUT max
(6)
'IL
2
where
•
ILmax = Maximum inductor current
(7)
A more conservative approach is to select the inductor current rating just for the switch-current limit ILIMF of the
converter.
The total losses of the coil have a strong impact on the efficiency of the DC-DC conversion and consist of both
the losses in the DC resistance R(DC) and the following frequency-dependent components:
• The losses in the core material (magnetic hysteresis loss, especially at high switching frequencies)
• Additional losses in the conductor from the skin effect (current displacement at high frequencies)
• Magnetic field losses of the neighboring windings (proximity effect)
• Radiation losses
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Typical Application (continued)
8.2.2.2.2 Output Capacitor Selection
The advanced fast-response voltage-mode control scheme of the TLV62065-Q1 device allows the use of tiny
ceramic capacitors. Ceramic capacitors with low ESR values provide the lowest output-voltage ripple and are
recommended. The output capacitor requires either an X7R or X5R dielectric. Y5V- and Z5U-dielectric
capacitors, aside from a wide variation in capacitance over temperature, become resistive at high frequencies
and may not be used. For most applications, a nominal 10-µF or 22-µF capacitor is suitable. In small ceramic
capacitors, the DC-bias effect decreases the effective capacitance. Therefore a 22-µF capacitor can be used for
output voltages higher than 2 V.
In case additional ceramic capacitors in the supplied system are connected to the output of the DC-DC converter,
the output capacitor COUT must be decreased in order not to exceed the recommended effective capacitance
range. In this case, a loop-stability analysis must be performed as described in the Checking Loop Stability
section.
Use Equation 8 to calculate the RMS ripple current at the nominal load current and while the device is in PWM
mode.
VOUT
1
VIN
1
IRMSCout VOUT u
u
/u¦
2u 3
(8)
8.2.2.2.3 Input Capacitor Selection
Because of the nature of the buck converter having a pulsating input current, a low-ESR input capacitor is
required for best input voltage filtering and minimizing interference with other circuits caused by high input
voltage spikes. For most applications a 10-µF ceramic capacitor is recommended. The input capacitor can be
increased without any limit for better input voltage filtering.
Take care when using only small ceramic input capacitors. When a ceramic capacitor is used at the input and the
power is being supplied through long wires, such as from a wall adapter, a load step at the output or VIN step on
the input can induce ringing at the VIN pin. This ringing can couple to the output and be mistaken as loop
instability, or could even damage the part by exceeding the maximum ratings.
8.2.2.3 Checking Loop Stability
The first step of circuit and stability evaluation is to look at the following signals from a steady-state perspective:
• Switching node, SW
• Inductor current, IL
• Output ripple voltage, VOUT(AC)
These signals are the basic signals that must be measured when evaluating a switching converter. When the
switching waveform shows large duty cycle jitter, or the output voltage or inductor current shows oscillations, the
regulation loop may be unstable. This instability is often a result of board layout, wrong L-C output filter
combinations, or both. As a next step in the evaluation of the regulation loop, the transient response of the load
is tested. During the time between the application of the load transient and the turnon of the P-channel MOSFET,
the output capacitor must supply all of the current required by the load. VOUT immediately shifts by an amount
equal to ΔI(LOAD) × ESR, where ESR is the effective series resistance of COUT. ΔI(LOAD) begins to charge or
discharge CO, generating a feedback error signal used by the regulator to return VOUT to its steady-state value.
The results are most easily interpreted when the device operates in PWM mode at medium-to-high load currents.
During this recovery time, VOUT can be monitored for settling time, overshoot, or ringing; that helps evaluate
stability of the converter. Without any ringing, the loop has usually more than 45° of phase margin.
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Typical Application (continued)
8.2.3 Application Curves
For the application curves, see the graphs listed in Table 2.
Table 2. Table of Graphs
FIGURE
Output Voltage Accuracy
Load Current, VOUT = 1.8 V, Auto PFM/PWM Mode
Figure 5
Load Current, VOUT = 1.8 V, Forced PWM Mode
Figure 6
9 Power Supply Recommendations
The TLV62065-Q1 device is designed to operate from an input voltage up to 5.5 V. For the input pins (PVIN and
AVIN), a small ceramic capacitor with a typical value of 10 μF is recommended for most applications.
Capacitance derating for aging, temperature, and DC bias must be taken into account while determining the
capacitor value.
10 Layout
10.1 Layout Guidelines
As for all switching power supplies, the layout is an important step in the design. Proper function of the device
demands careful attention to PCB layout. Care must be taken in board layout to get the specified performance. If
the layout is not carefully done, the regulator could show poor line regulation, load regulation or both and may
have stability issues as well as EMI and thermal problems. Providing a low-inductance, low-impedance ground
path is critical. Therefore, use wide and short traces for the main current paths. The input capacitor as well as
the inductor and output capacitor should be placed as close as possible to the IC pins.
Large parasitic inductance in ground path or large parasitic inductance between input capacitor and VIN pin can
cause significant overshoot or undershoot voltage on SW pin exceeding the specifications in the Absolute
Maximum Ratings table.
Connect the AGND and PGND pins of the device to the thermal pad land of the PCB and use this pad as a star
point. To minimize the effects of ground noise use a common power node (PGND), and a different node (AGND)
for the signal. The FB divider network should be connected directly to the output capacitor and the FB line must
be routed away from noisy components and traces (for example, the SW line).
Because of the small package of this converter and the overall small solution size, the thermal performance of
the PCB layout is important. For good thermal performance, PCB design of at least four layers is recommended.
The thermal pad of the IC must be soldered on the thermal pad area on the PCB to achieve proper thermal
connection. Additionally, for good thermal performance, the thermal pad on the PCB must have sufficient number
of thermal vias connected to the GND planes on the PCB.
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Mode/PG
Enable
10.2 Layout Example
VIN
GND
CIN
COUT
R2
R1
CFF
GND
L
VOUT
Figure 24. PCB Layout
11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
TLV62065EVM-719 User's Guide (SLVU424)
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resource
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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19-Apr-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
TLV62065TDSGRQ1
ACTIVE
Package Type Package Pins Package
Drawing
Qty
WSON
DSG
8
3000
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
Op Temp (°C)
Device Marking
(4/5)
-40 to 105
SCD
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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19-Apr-2016
OTHER QUALIFIED VERSIONS OF TLV62065-Q1 :
• Catalog: TLV62065
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Aug-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TLV62065TDSGRQ1
Package Package Pins
Type Drawing
WSON
DSG
8
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
3000
179.0
8.4
Pack Materials-Page 1
2.2
B0
(mm)
K0
(mm)
P1
(mm)
2.2
1.2
4.0
W
Pin1
(mm) Quadrant
8.0
Q2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Aug-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TLV62065TDSGRQ1
WSON
DSG
8
3000
195.0
200.0
45.0
Pack Materials-Page 2
PACKAGE OUTLINE
DSG0008A
WSON - 0.8 mm max height
SCALE 5.500
PLASTIC SMALL OUTLINE - NO LEAD
2.1
1.9
A
B
PIN 1 INDEX AREA
2.1
1.9
0.3
0.2
0.4
0.2
OPTIONAL TERMINAL
TYPICAL
C
0.8 MAX
SEATING PLANE
0.05
0.00
0.08 C
EXPOSED
THERMAL PAD
(0.2) TYP
0.9 0.1
5
4
6X 0.5
2X
1.5
SEE OPTIONAL
TERMINAL
9
8
1
PIN 1 ID
1.6 0.1
8X
0.4
8X
0.2
0.3
0.2
0.1
0.05
C A B
C
4218900/B 09/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
DSG0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.9)
8X (0.5)
( 0.2) VIA
TYP
1
8
8X (0.25)
(0.55)
SYMM
9
(1.6)
6X (0.5)
5
4
SYMM
(R0.05) TYP
(1.9)
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4218900/B 09/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
DSG0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
8X (0.5)
SYMM
METAL
1
8
8X (0.25)
(0.45)
SYMM
9
(0.7)
6X (0.5)
5
4
(R0.05) TYP
(0.9)
(1.9)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 9:
87% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4218900/B 09/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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