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TLV62569, TLV62569P
ZHCSFR4C – DECEMBER 2016 – REVISED OCTOBER 2017
TLV62569 采用 SOT 封装的 2A 高效同步降压转换器
1 特性
•
•
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•
•
•
•
•
•
•
•
•
•
•
•
1
3 说明
效率高达 95%
低 RDS(ON)，可在 100mΩ 和 60mΩ 之间切换
输入电压范围：2.5V 至 5.5V
可调输出电压：0.6V 至 VIN
针对轻载效率的省电模式
针对最低压降的 100% 占空比
35µA 静态工作电流
1.5MHz 典型开关频率
电源正常输出
过流保护
内部软启动
热关断保护
采用小外形尺寸晶体管 (SOT) 封装
与 TLV62568 引脚兼容
使用 TLV62569 并借助 WEBENCH® Power
Designer 创建定制设计方案
2 应用
•
•
•
•
•
通用负载点 (POL) 电源
机顶盒
网络视频摄像头
无线路由器
硬盘
TLV62569 器件是一款同步降压 DC-DC 转换器，专门
针对高效和紧凑型解决方案进行了优化。该器件集成的
开关能够提供高达 2A 的输出电流。
在中等负载或重载条件下，该器件运行在脉宽调制
(PWM) 模式下，开关频率为 1.5MHz。在轻载情况
下，该器件自动进入节能模式 (PSM)，从而在整个负
载电流范围内保持高效率。关断时，流耗减少至 2μA
以下。
TLV62569 的输出电压可通过一个外部电阻分压器进行
调节。内部软启动电路可限制启动期间的浪涌电流。此
外， 还内置了 诸如输出过流保护、热关断保护和电源
正常输出等其他特性。该器件提供 SOT23 和 SOT563
两种封装。
器件信息(1)
器件型号
封装
TLV62569DBV
SOT23 (5)
TLV62569PDDC
SOT23 (6)
TLV62569DRL
SOT563 (6)
TLV62569PDRL
SOT563 (6)
TLV62569PDDC
功能
标记符号
-
16AF
电源正常
7G
-
19D
电源正常
19E
TLV62569DRL
TLV62569PDRL
简化电路原理图
VIN
R3
499 k
C1
4.7 µF
5V 输入电压下的效率
VOUT
1.8 V / 2.0 A
L1
2.2 µH
100
SW
EN
C2
10 µF
C3*
95
R1
200 k
90
PG GND FB
Copyright Ú 2016, Texas Instruments Incorporated
R2
100 k
Efficiency (%)
VPG
C3: Optional
1.60mm x 1.60mm
器件比较
器件编号
TLV62569P
2.90mm x 2.80mm
(1) 要了解所有可用封装，请参阅数据表末尾的可订购产品附录。
TLV62569DBV
VIN
2.5 V to 5.5 V
封装尺寸（标称值）
85
80
75
70
VOUT = 1.2 V
VOUT = 1.8 V
VOUT = 2.5 V
VOUT = 3.3 V
65
60
0
0.2
0.4
0.6
0.8
1
1.2
Load (A)
1.4
1.6
1.8
2
D008
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
English Data Sheet: SLVSDG1
TLV62569, TLV62569P
ZHCSFR4C – DECEMBER 2016 – REVISED OCTOBER 2017
www.ti.com.cn
目录
1
2
3
4
5
6
7
特性 ..........................................................................
应用 ..........................................................................
说明 ..........................................................................
修订历史记录 ...........................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
6.1
6.2
6.3
6.4
6.5
6.6
3
4
4
4
4
5
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions ......................
Thermal Information ..................................................
Electrical Characteristics..........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 6
7.1
7.2
7.3
7.4
Overview ...................................................................
Functional Block Diagrams .......................................
Feature Description...................................................
Device Functional Modes..........................................
6
6
6
7
8
Application and Implementation .......................... 8
8.1 Application Information.............................................. 8
8.2 Typical Application .................................................... 8
9 Power Supply Recommendations...................... 12
10 Layout................................................................... 13
10.1 Layout Guidelines ................................................. 13
10.2 Layout Example .................................................... 13
10.3 Thermal Considerations ........................................ 13
11 器件和文档支持 ..................................................... 14
11.1
11.2
11.3
11.4
11.5
11.6
11.7
器件支持 ...............................................................
文档支持 ...............................................................
接收文档更新通知 .................................................
社区资源................................................................
商标 .......................................................................
静电放电警告.........................................................
Glossary ................................................................
14
14
14
14
14
14
15
12 机械、封装和可订购信息 ....................................... 15
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision B (July 2017) to Revision C
Page
•
已更改 TLV62569DRL 和 TLV62569PDRL 更改为生产状态。 .............................................................................................. 1
•
已添加 在器件比较表中添加了 TLV62569DRL 和 TLV62569PDRL 的标记符号 .................................................................... 1
•
Added DRL package thermal information ............................................................................................................................. 4
•
Corrected editorial error of EN pin threshold voltage ............................................................................................................. 4
•
Added current limit for TLV62569DRL and TLV62569PDRL ................................................................................................ 5
•
已添加 TLV62569PDRL layout example .............................................................................................................................. 13
Changes from Revision A (March 2017) to Revision B
Page
•
已更改 TLV62569PDDC 更改为生产状态 ............................................................................................................................... 1
•
器件比较表移至第 1 页 ........................................................................................................................................................... 1
•
Added DDC package thermal information .............................................................................................................................. 4
•
Added startup time of TLV62569PDDC.................................................................................................................................. 4
Changes from Original (December 2016) to Revision A
Page
•
已添加 WEBENCH® 模型 ...................................................................................................................................................... 1
2
Copyright © 2016–2017, Texas Instruments Incorporated
TLV62569, TLV62569P
www.ti.com.cn
ZHCSFR4C – DECEMBER 2016 – REVISED OCTOBER 2017
5 Pin Configuration and Functions
SOT23-5
DBV Package
(Top View)
SOT23-6
DDC Package
(Top View)
SOT563-6
DRL Package
(Top View)
FB
VIN
FB
PG
VIN
5
4
6
5
4
NC/PG EN
1
2
3
1
2
SW
6
5
4
1
2
3
3
FB GND VIN
EN
GND
SW
EN
GND
SW
Pin Functions
PIN NUMBER
NAME
I/O/PWR
DESCRIPTION
SOT23-5
SOT23-6
SOT563-6
EN
1
1
5
I
GND
2
2
2
PWR
Ground pin.
SW
3
3
4
PWR
Switch pin connected to the internal FET switches and inductor
terminal. Connect the inductor of the output filter to this pin.
VIN
4
4
3
PWR
Power supply voltage input.
PG
-
5
6
O
Power good open drain output pin for TLV62569P. The pull-up
resistor should not be connected to any voltage higher than 5.5V. If
it's not used, leave the pin floating.
FB
5
6
1
I
Feedback pin for the internal control loop. Connect this pin to an
external feedback divider.
NC
-
-
6
O
No connection pin for TLV62569DRL. The pin can be connected to
the output or the ground. Or leave it floating.
Device enable logic input. Logic high enables the device, logic low
disables the device and turns it into shutdown. Do not leave floating.
6 Specifications
6.1 Absolute Maximum Ratings
Over operating temperature range (unless otherwise noted) (1)
VIN, EN, PG
Voltage SW (DC)
(2)
SW (AC, less than 10ns) (3)
FB
MIN
MAX
UNIT
–0.3
6
V
–0.3
VIN+0.3
V
–3.0
9
V
–0.3
5.5
V
Operating junction temperature, TJ
–40
150
°C
Storage temperature, Tstg
–65
150
°C
(1)
(2)
(3)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and the device is not switching. Functional operation of the device at these or any other conditions beyond those indicated under
recommended operating conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect
device reliability.
All voltage values are with respect to network ground terminal.
While switching
Copyright © 2016–2017, Texas Instruments Incorporated
3
TLV62569, TLV62569P
ZHCSFR4C – DECEMBER 2016 – REVISED OCTOBER 2017
www.ti.com.cn
6.2 ESD Ratings
V(ESD)
(1)
(2)
Electrostatic discharge
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
V
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±500
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions (1)
MAX
UNIT
VIN
Input voltage
MIN
2.5
TYP
5.5
V
VOUT
Output voltage
0.6
VIN
V
IOUT
Output current
0
2
A
TJ
Operating junction temperature
–40
125
°C
1
mA
ISINK_PG Sink current at PG pin
(1)
Refer to the Application and Implementation section for further information.
6.4 Thermal Information
THERMAL METRIC (1)
RθJA
DBV
(5 Pins)
DDC
(6 Pins)
DRL
(6 Pins)
UNIT
188.2
106.2
146.3
°C/W
RθJC(top) Junction-to-case (top) thermal resistance
137.5
52.9
51.0
°C/W
RθJB
Junction-to-board thermal resistance
41.2
31.2
27.0
°C/W
ψJT
Junction-to-top characterization parameter
31.4
11.3
2.2
°C/W
ψJB
Junction-to-board characterization parameter
40.6
31.6
27.6
°C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance
n/a
n/a
n/a
°C/W
(1)
Junction-to-ambient thermal resistance
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6.5
Electrical Characteristics
VIN = 5.0 V, TJ = 25°C, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
IQ
Quiescent current into VIN pin
Not switching
35
ISD
Shutdown current into VIN pin
EN = 0 V
0.1
2
µA
Under voltage lock out
VIN falling
2.3
2.45
V
VUVLO
TJSD
Under voltage lock out hysteresis
Thermal shutdown
uA
100
Junction temperature rising
150
Junction temperature falling
130
mV
°C
LOGIC INTERFACE
VIH
High-level threshold at EN pin
2.5 V ≤ VIN ≤ 5.5 V
VIL
Low-level threshold at EN pin
2.5 V ≤ VIN ≤ 5.5 V
0.95
0.4
TLV62569DBV
800
TLV62569PDDC, TLV62569DRL,
TLV62569PDRL
900
VFB rising, referenced to VFB nominal
95%
VFB falling, referenced to VFB nominal
90%
tSS
Soft startup time
VPG
Power good threshold
VPG,OL
Power good low-level output voltage
ISINK = 1 mA
IPG,LKG
Input leakage current into PG pin
VPG = 5.0 V
tPG,DLY
Power good delay time
VFB falling
1.2
0.85
V
V
µs
0.4
V
0.01
µA
40
µs
OUTPUT
VFB
4
Feedback regulation voltage
0.588
0.6
0.612
V
Copyright © 2016–2017, Texas Instruments Incorporated
TLV62569, TLV62569P
www.ti.com.cn
ZHCSFR4C – DECEMBER 2016 – REVISED OCTOBER 2017
Electrical Characteristics (continued)
VIN = 5.0 V, TJ = 25°C, unless otherwise noted
PARAMETER
RDS(on)
TEST CONDITIONS
MIN
TYP
High-side FET on resistance
100
Low-side FET on resistance
60
ILIM
High-side FET current limit
fSW
Switching frequency
TLV62569DBV, TLV62569PDDC
3
TLV62569DRL, TLV62569PDRL
2.5
VOUT = 2.5 V
MAX
UNIT
mΩ
A
1.5
MHz
6.6 Typical Characteristics
50
20
45
18
VIN = 2.5V
VIN = 3.6V
VIN = 5.0V
$
35
6KXWGRZQ &XUUHQW
$
4XLHVFHQW &XUUHQW
16
40
30
25
20
TJ = -40°C
TJ = 25°C
TJ = 85°C
TJ = 125°C
15
10
2.5
3.0
3.5
4.0
4.5
Input Voltage (V)
5.0
14
12
10
8
6
4
2
0
-40
5.5
-10
D001
图 1. Quiescent Current vs Input Voltage
20
50
80
Junction Temperature (°C)
110
140
D002
图 2. Shutdown Current vs Junction Temperature
0.3
FB Voltage Accuracy (%)
0.2
TJ = -40°C
TJ = 25°C
TJ = 85°C
TJ = 125°C
0.1
0.0
-0.1
-0.2
-0.3
2.5
3.0
3.5
4.0
4.5
Input Voltage (V)
5.0
5.5
D003
图 3. FB Voltage Accuracy
版权 © 2016–2017, Texas Instruments Incorporated
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TLV62569, TLV62569P
ZHCSFR4C – DECEMBER 2016 – REVISED OCTOBER 2017
www.ti.com.cn
7 Detailed Description
7.1 Overview
The TLV62569 is a high-efficiency synchronous step-down converter. The device operates with an adaptive off
time with peak current control scheme. The device operates at typically 1.5-MHz frequency pulse width
modulation (PWM) at moderate to heavy load currents. Based on the VIN/VOUT ratio, a simple circuit sets the
required off time for the low-side MOSFET. It makes the switching frequency relatively constant regardless of the
variation of input voltage, output voltage, and load current.
7.2 Functional Block Diagrams
PG
Soft Start
Thermal
Shutdown
UVLO
Control Logic
EN
VPG
+
VFB
±
VIN
GND
Peak Current Detect
VREF
+
_
FB
Modulator
SW
Gate
Drive
VSW
VIN
TOFF
Zero Current Detect
GND
Power Good feature is only available in TLV62569P
GND
Copyright Ú 2016, Texas Instruments Incorporated
图 4. TLV62569 Functional Block Diagram
7.3 Feature Description
7.3.1 Power Save Mode
The device automatically enters Power Save Mode to improve efficiency at light load when the inductor current
becomes discontinuous. In Power Save Mode, the converter reduces switching frequency and minimizes current
consumption. In Power Save Mode, the output voltage rises slightly above the nominal output voltage. This effect
is minimized by increasing the output capacitor.
7.3.2 100% Duty Cycle Low Dropout Operation
The device offers a low input-to-output voltage differential by entering 100% duty cycle mode. In this mode, the
high-side MOSFET switch is constantly turned on and the low-side MOSFET is switched off. The minimum input
voltage to maintain output regulation, depending on the load current and output voltage, is calculated as:
VIN(MIN) = VOUT + IOUT x (RDS(ON) + RL)
where
•
•
6
RDS(ON) = High side FET on-resistance
RL = Inductor ohmic resistance (DCR)
(1)
版权 © 2016–2017, Texas Instruments Incorporated
TLV62569, TLV62569P
www.ti.com.cn
ZHCSFR4C – DECEMBER 2016 – REVISED OCTOBER 2017
Feature Description (接
接下页)
7.3.3 Soft Startup
After enabling the device, internal soft startup circuitry ramps up the output voltage which reaches nominal output
voltage during a startup time. This avoids excessive inrush current and creates a smooth output voltage rise
slope. It also prevents excessive voltage drops of primary cells and rechargeable batteries with high internal
impedance.
The TLV62569 is able to start into a pre-biased output capacitor. The converter starts with the applied bias
voltage and ramps the output voltage to its nominal value.
7.3.4 Switch Current Limit
The switch current limit prevents the device from high inductor current and drawing excessive current from a
battery or input voltage rail. Excessive current might occur with a heavy load or shorted output circuit condition.
The TLV62569 adopts the peak current control by sensing the current of the high-side switch. Once the high-side
switch current limit is reached, the high-side switch is turned off and low-side switch is turned on to ramp down
the inductor current with an adaptive off-time.
7.3.5 Under Voltage Lockout
To avoid mis-operation of the device at low input voltages, under voltage lockout is implemented that shuts down
the device at voltages lower than VUVLO with VHYS_UVLO hysteresis.
7.3.6 Thermal Shutdown
The device enters thermal shutdown once the junction temperature exceeds the thermal shutdown rising
threshold, TJSD. Once the junction temperature falls below the falling threshold, the device returns to normal
operation automatically.
7.4 Device Functional Modes
7.4.1 Enabling/Disabling the Device
The device is enabled by setting the EN input to a logic High. Accordingly, a logic Low disables the device. If the
device is enabled, the internal power stage starts switching and regulates the output voltage to the set point
voltage. The EN input must be terminated and should not be left floating.
7.4.2 Power Good
The TLV62569P has a power good output. The PG pin goes high impedance once the output is above 95% of
the nominal voltage, and is driven low once the output voltage falls below typically 90% of the nominal voltage.
The PG pin is an open-drain output and is specified to sink up to 1 mA. The power good output requires a pull-up
resistor connecting to any voltage rail less than 5.5 V. The PG signal can be used for sequencing of multiple rails
by connecting it to the EN pin of other converters. Leave the PG pin unconnected when not used.
表 1. PG Pin Logic
DEVICE CONDITIONS
Enable
EN = High, VFB ≥ VPG
LOGIC STATUS
HIGH Z
LOW
√
EN = High, VFB ≤ VPG
√
Shutdown
EN = Low
√
Thermal Shutdown
TJ > TJSD
√
UVLO
1.4 V < VIN < VUVLO
√
Power Supply Removal
VIN ≤ 1.4 V
版权 © 2016–2017, Texas Instruments Incorporated
√
7
TLV62569, TLV62569P
ZHCSFR4C – DECEMBER 2016 – REVISED OCTOBER 2017
www.ti.com.cn
8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The following section discusses the design of the external components to complete the power supply design for
several input and output voltage options by using typical applications as a reference.
8.2 Typical Application
VIN
2.5 V to 5.5 V
TLV62569P
VIN
C1
4.7 µF
R3
499 k
VOUT
1.8 V / 2.0 A
L1
2.2 µH
SW
C2
10 µF
EN
C3*
R1
200 k
VPG
PG GND FB
R2
100 k
C3: Optional
Copyright Ú 2016, Texas Instruments Incorporated
图 5. TLV62569 1.8-V Output Application
8.2.1 Design Requirements
For this design example, use the parameters listed in 表 2 as the input parameters.
表 2. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage
2.5 V to 5.5 V
Output voltage
1.8 V
Maximum output current
2.0 A
表 3 lists the components used for the example.
表 3. List of Components
REFERENCE
C1
4.7 µF, Ceramic Capacitor, 10 V, X7R, size 0805, GRM21BR71A475KA73L
C2
10 µF, Ceramic Capacitor, 10 V, X7R, size 0805, GRM21BR71A106KE51L
Murata
L1
2.2 µH, Power Inductor, size 4mmx4mm, XAL4020-222ME
Coilcraft
R1,R2,R3
C3
(1)
MANUFACTURER (1)
DESCRIPTION
Murata
Chip resistor,1%,size 0603
Std.
Optional, 6.8 pF if it is needed
Std.
See Third-party Products Disclaimer
8.2.2 Detailed Design Procedure
8.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TLV62569 device with the WEBENCH® Power Designer.
8
版权 © 2016–2017, Texas Instruments Incorporated
TLV62569, TLV62569P
www.ti.com.cn
ZHCSFR4C – DECEMBER 2016 – REVISED OCTOBER 2017
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.2.2 Setting the Output Voltage
An external resistor divider is used to set output voltage according to 公式 2.
When sizing R2, in order to achieve low current consumption and acceptable noise sensitivity, use a maximum of
200 kΩ for R2. Larger currents through R2 improve noise sensitivity and output voltage accuracy but increase
current consumption.
R1 ö
R1 ö
æ
æ
VOUT = VFB ´ ç 1 +
÷
÷ = 0.6V ´ ç 1 +
R2 ø
R2 ø
è
è
(2)
A feed forward capacitor, C3 improves the loop bandwidth to make a fast transient response (shown in 图 19).
6.8-pF capacitance is recommended for R2 of 100-kΩ resistance. A more detailed discussion on the optimization
for stability vs. transient response can be found in SLVA289.
8.2.2.3 Output Filter Design
The inductor and output capacitor together provide a low-pass filter. To simplify this process, 表 4 outlines
possible inductor and capacitor value combinations. Checked cells represent combinations that are proven for
stability by simulation and lab test. Further combinations should be checked for each individual application.
表 4. Matrix of Output Capacitor and Inductor Combinations
L [µH] (1)
0.6 ≤ VOUT < 1.2
1
+
2.2
++ (3)
1.2 ≤ VOUT < 1.8
1.8 ≤ VOUT
(1)
(2)
(3)
COUT [µF] (2)
VOUT [V]
4.7
10
22
2 x 22
1
+
+
2.2
++ (3)
+
1
+
+
+
2.2
++ (3)
+
+
100
Inductor tolerance and current de-rating is anticipated. The effective inductance can vary by +20% and -30%.
Capacitance tolerance and bias voltage de-rating is anticipated. The effective capacitance can vary by +20% and -50%.
This LC combination is the standard value and recommended for most applications.
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TLV62569, TLV62569P
ZHCSFR4C – DECEMBER 2016 – REVISED OCTOBER 2017
www.ti.com.cn
8.2.2.4 Inductor Selection
The main parameters for inductor selection is inductor value and then saturation current of the inductor. To
calculate the maximum inductor current under static load conditions, 公式 3 is given:
DI
IL,MAX = IOUT,MAX + L
2
VOUT
VIN
DIL = VOUT ´
L ´ fSW
1-
where:
•
•
•
•
IOUT,MAX is the maximum output current
ΔIL is the inductor current ripple
fSW is the switching frequency
L is the inductor value
(3)
It is recommended to choose a saturation current for the inductor that is approximately 20% to 30% higher than
IL,MAX. In addition, DC resistance and size should also be taken into account when selecting an appropriate
inductor.
8.2.2.5 Input and Output Capacitor Selection
The architecture of the TLV62569 allows use of tiny ceramic-type output capacitors with low equivalent series
resistance (ESR). These capacitors provide low output voltage ripple and are thus recommended. To keep its
resistance up to high frequencies and to achieve narrow capacitance variation with temperature, it is
recommended to use X7R or X5R dielectric.
The input capacitor is the low impedance energy source for the converter that helps provide stable operation. A
low ESR multilayer ceramic capacitor is recommended for best filtering. For most applications, 4.7-μF input
capacitance is sufficient; a larger value reduces input voltage ripple.
The TLV62569 is designed to operate with an output capacitor of 10 µF to 47 µF, as outlined in 表 4.
8.2.3 Application Performance Curves
100
100
95
95
90
90
Efficiency (%)
Efficiency (%)
VIN = 5 V, VOUT = 1.8 V, L = 2.2 μH, TA = 25 °C, unless otherwise noted.
85
80
75
60
1m
VIN = 2.5 V
VIN = 3.3 V
VIN = 5.0 V
75
10m
65
100m
Load (A)
图 6. 1.2-V Output Efficiency
10
80
70
70
65
85
1
2
D004
60
1m
VIN = 2.5 V
VIN = 3.3 V
VIN = 5.0 V
10m
100m
Load (A)
1
2
D005
图 7. 1.8-V Output Efficiency
版权 © 2016–2017, Texas Instruments Incorporated
TLV62569, TLV62569P
ZHCSFR4C – DECEMBER 2016 – REVISED OCTOBER 2017
100
100
95
95
90
90
Efficiency (%)
Efficiency (%)
www.ti.com.cn
85
80
75
85
80
75
70
70
65
65
VIN = 3.3 V
VIN = 5.0 V
60
1m
VIN = 5.0 V
10m
100m
Load (A)
1
60
1m
2
10m
3
2
D007
1.0
VOUT = 1.8 V
VOUT = 3.3 V
2.5
2
Line Regulation (%)
Load Regulation (%)
1
图 9. 3.3-V Output Efficiency
图 8. 2.5-V Output Efficiency
1.5
1
0.5
0
0.5
0.0
-0.5
IOUT = 0.5A
IOUT = 1.0A
IOUT = 2.0A
-0.5
-1
0
0.2
0.4
0.6
0.8
1
1.2
Load (A)
1.4
1.6
1.8
-1.0
2.5
2
3.0
D009
VIN = 5 V
2000
2000
Switching Frequency (kHz)
2500
1500
1000
VOUT = 1.2 V
VOUT = 1.8 V
VOUT = 2.5 V
VOUT = 3.3 V
500
0
0.2
0.4
4.0
4.5
Input Voltage (V)
5.0
5.5
D010
图 11. Line Regulation
2500
0
3.5
VOUT = 1.8 V
图 10. Load Regulation
Switching Frequency (kHz)
100m
Load (A)
D006
0.6
0.8
1
1.2
Load (A)
1.4
1.6
VIN = 5 V
图 12. Switching Frequency vs Load
版权 © 2016–2017, Texas Instruments Incorporated
1.8
2
1500
1000
VOUT = 1.2 V
VOUT = 1.8 V
VOUT = 2.5 V
VOUT = 3.3 V
500
0
2.5
3
D011
3.5
4
4.5
Input Voltage (V)
5
5.5
D012
IOUT = 1 A
图 13. Switching Frequency vs Input Voltage
11
TLV62569, TLV62569P
ZHCSFR4C – DECEMBER 2016 – REVISED OCTOBER 2017
www.ti.com.cn
VSW
2V/DIV
VSW
2V/DIV
VOUT
10mV/DIV
AC
VOUT
0.1V/DIV
AC
ICOIL
0.5A/DIV
ICOIL
0.5A/DIV
7LPH
Time - 500ns/DIV
V ',9
D014
D013
IOUT = 1 A
IOUT = 0.1 A
图 14. PWM Operation
图 15. Power Save Mode Operation
VEN
3V/DIV
VEN
3V/DIV
VOUT
1V/DIV
VOUT
1V/DIV
ICOIL
2A/DIV
ICOIL
0.5A/DIV
7LPH
V ',9
7LPH
V ',9
D015
IOUT = 2 A
D016
IOUT = 0.1 A
图 16. Startup and Shutdown with Load
图 17. Startup and Shutdown with Load
VOUT
0.2V/DIV
VOUT
0.2V/DIV
ICOIL
1A/DIV
ICOIL
1A/DIV
7LPH
V ',9
7LPH
V ',9
D017
Load Step 0.8 A to 2 A, 1A/μs slew rate
图 18. Load Transient
D018
Load Step 0.8 A to 2 A, 1A/μs slew rate
C3 = 6.8 pF
图 19. Load Transient
9 Power Supply Recommendations
The power supply to the TLV62569 must have a current rating according to the supply voltage, output voltage
and output current.
12
版权 © 2016–2017, Texas Instruments Incorporated
TLV62569, TLV62569P
www.ti.com.cn
ZHCSFR4C – DECEMBER 2016 – REVISED OCTOBER 2017
10 Layout
10.1 Layout Guidelines
The PCB layout is an important step to maintain the high performance of the TLV62569 device.
• The input/output capacitors and the inductor should be placed as close as possible to the IC. This keeps the
power traces short. Routing these power traces direct and wide results in low trace resistance and low
parasitic inductance.
• The low side of the input and output capacitors must be connected properly to the power GND to avoid a
GND potential shift.
• The sense traces connected to FB are signal traces. Special care should be taken to avoid noise being
induced. Keep these traces away from SW nodes.
• GND layers might be used for shielding.
10.2 Layout Example
GND
L1
VIN
PAC101
C1
VOUT
VIN
GND
FB
R2 PAR202
R1
EN
R1
R2
PAC601
SW
C2
C1
PAR201
VIN
FB
GND
VIN
L1
PG
EN
SW
C2
VOUT
GND
图 20. TLV62569DBV Layout
图 21. TLV62569PDRL Layout
10.3 Thermal Considerations
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow,
convection surfaces, and the presence of other heat-generating components affect the power dissipation limits of
a given component.
Two basic approaches for enhancing thermal performance are listed below:
• Improving the power dissipation capability of the PCB design
• Introducing airflow in the system
For more details on how to use the thermal parameters, see the application notes: Thermal Characteristics
Application Notes SZZA017 and SPRA953.
版权 © 2016–2017, Texas Instruments Incorporated
13
TLV62569, TLV62569P
ZHCSFR4C – DECEMBER 2016 – REVISED OCTOBER 2017
www.ti.com.cn
11 器件和文档支持
11.1 器件支持
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.1.2 开发支持
11.1.2.1 使用 WEBENCH® 工具创建定制设计
请单击此处，借助 WEBENCH® Power Designer 并使用 TLV62569 器件定制设计方案
1. 在开始阶段键入输出电压 (VIN)、输出电压 (VOUT) 和输出电流 (IOUT) 要求。
2. 使用优化器拨盘优化关键设计参数，如效率、封装和成本。
3. 将生成的设计与德州仪器 (TI) 的其他解决方案进行比较。
WEBENCH Power Designer 提供一份定制原理图以及罗列实时价格和组件可用性的物料清单。
在多数情况下，可执行以下操作：
• 运行电气仿真，观察重要波形以及电路性能
• 运行热性能仿真，了解电路板热性能
• 将定制原理图和布局方案导出至常用 CAD 格式
• 打印设计方案的 PDF 报告并与同事共享
有关 WEBENCH 工具的详细信息，请访问 www.ti.com/WEBENCH。
11.2 文档支持
11.2.1 相关文档
应用报告《半导体和 IC 封装热指标》（文件编号：SPRA953）
应用报告《采用 JEDEC PCB 设计的线性和逻辑封装散热特性》（文件编号：SZZA017）
11.3 接收文档更新通知
要接收文档更新通知，请转至 TI.com 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产品信
息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.4 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.5 商标
E2E is a trademark of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
14
版权 © 2016–2017, Texas Instruments Incorporated
TLV62569, TLV62569P
www.ti.com.cn
ZHCSFR4C – DECEMBER 2016 – REVISED OCTOBER 2017
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据如有变更，恕不另行通知
和修订此文档。如欲获取此产品说明书的浏览器版本，请参阅左侧的导航。
版权 © 2016–2017, Texas Instruments Incorporated
15
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TLV62569DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
16AF
TLV62569DBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
16AF
TLV62569DRLR
ACTIVE
SOT-5X3
DRL
6
3000
RoHS & Green
Call TI | SN
Level-1-260C-UNLIM
-40 to 125
19D
TLV62569DRLT
ACTIVE
SOT-5X3
DRL
6
250
RoHS & Green
Call TI | SN
Level-1-260C-UNLIM
-40 to 125
19D
TLV62569PDDCR
ACTIVE
SOT-23-THIN
DDC
6
3000
RoHS & Green
Call TI | SN
Level-1-260C-UNLIM
-40 to 125
(6D9, 6DW)
TLV62569PDDCT
ACTIVE
SOT-23-THIN
DDC
6
250
RoHS & Green
Call TI | SN
Level-1-260C-UNLIM
-40 to 125
(6D9, 6DW)
TLV62569PDRLR
ACTIVE
SOT-5X3
DRL
6
3000
RoHS & Green
Call TI | SN
Level-1-260C-UNLIM
-40 to 125
19E
TLV62569PDRLT
ACTIVE
SOT-5X3
DRL
6
250
RoHS & Green
Call TI | SN
Level-1-260C-UNLIM
-40 to 125
19E
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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