TLV62595
TLV62595
SLUSDR2 – DECEMBER
2020
SLUSDR2 – DECEMBER 2020
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TLV62595, 2.5-V to 5.5-V Input, 4-A Step-Down Converter with 1% Output Accuracy in
1.5-mm × 1.5-mm QFN Package
1 Features
3 Description
•
•
•
•
•
The TLV62595 is a high-frequency synchronous stepdown converter optimized for compact solution size
and high efficiency. The device integrates switches
capable of delivering an output current up to 4 A. At
medium to heavy loads, the converter operates in
pulse width modulation (PWM) mode with typical 2.2MHz switching frequency. At light load, the device
automatically enters Power Save Mode (PSM) to
maintain high efficiency over the entire load current
range with a quiescent current as low as 10-µA.
•
•
•
•
•
•
•
•
•
•
Up to 97% efficiency
Low RDS(ON) power switches 26 mΩ / 25 mΩ
2.5-V to 5.5-V input voltage range
Adjustable output voltage from 0.6 V to 4 V
1% feedback voltage accuracy (full temperature
range)
DCS-control topology
Power save mode for light load efficiency
100% duty cycle for lowest dropout
10-μA operating quiescent current
2.2-MHz typical switching frequency
Short circuit protection (HICCUP)
Active output discharge
Power good output
Thermal shutdown protection
Create a custom design using the TLV62595 with
the WEBENCH® Power Designer
The device is available in a 6-pin 1.5-mm x 1.5-mm
QFN package, offering a high power density solution.
2 Applications
•
•
•
•
•
Solid state drive
Portable electronics
IP network camera
Industrial PC
Multifunction printers
VIN
2.5 V to 5.5 V
R3
100 k
Device Information
(1)
TLV62595
VIN
C1
4.7 µF
Based on the DCS Control topology, it provides a fast
transient response. The internal reference regulates
the output voltage down to 0.6 V with a high feedback
voltage accuracy of 1% over the junction temperature
range of –40°C to 125°C. The entire solution requires
a small 470-nH inductor, a single 4.7-μF input
capacitor and three 10-μF or single 47-μF output
capacitor.
L1
0.47 µH
PACKAGE(1)
BODY SIZE (NOM)
TLV62595
6-Pin VSON-HR
1.5 mm x 1.5 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
100
VOUT
1.8 V
SW
EN
PART NUMBER
95
C2
3x10 µF
R1
200 k
C3
120 pF
90
85
PG GND FB
R2
100 k
Typical Application Schematic
Efficiency (%)
VPG
80
75
70
65
VOUT = 0.6V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
60
55
50
100P
1m
10m
Load (A)
100m
1
4
D007
Efficiency at VIN = 5 V
An©IMPORTANT
NOTICEIncorporated
at the end of this data sheet addresses availability, warranty, changes, use in
safety-critical
applications,
Copyright
2020 Texas Instruments
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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics.............................................5
6.6 Typical Characteristics................................................ 6
7 Detailed Description........................................................7
7.1 Overview..................................................................... 7
7.2 Functional Block Diagram........................................... 7
7.3 Feature Description.....................................................8
7.4 Device Functional Modes............................................9
8 Application and Implementation.................................. 10
8.1 Application Information............................................. 10
8.2 Typical Application.................................................... 10
9 Power Supply Recommendations................................18
10 Layout...........................................................................19
10.1 Layout Guidelines................................................... 19
10.2 Layout Example...................................................... 19
11 Device and Documentation Support..........................20
11.1 Device Support........................................................20
11.2 Documentation Support.......................................... 20
11.3 Receiving Notification of Documentation Updates.. 20
11.4 Support Resources................................................. 20
11.5 Trademarks............................................................. 20
11.6 Electrostatic Discharge Caution.............................. 21
11.7 Glossary.................................................................. 21
12 Mechanical, Packaging, and Orderable
Information.................................................................... 21
4 Revision History
2
DATE
REVISION
NOTES
December 2020
*
Initial release
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5 Pin Configuration and Functions
FB
3
4
GND
PG
2
5
SW
EN
1
6
VIN
Figure 5-1. 6-Pin VSON-HR DMQ Package (Bottom View)
Table 5-1. Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
EN
1
I
Device enable pin. To enable the device, this pin needs to be pulled high. Pulling this pin low
disables the device. Do not leave floating.
PG
2
O
Power-good open-drain output pin. The pullup resistor can be connected to voltages up to
5.5 V. If unused, leave it floating.
FB
3
I
Feedback pin. For the fixed output voltage versions, this pin must be connected to the
output.
GND
4
SW
5
PWR
Switch pin of the power stage
VIN
6
PWR
Input voltage pin
Ground pin
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6 Specifications
6.1 Absolute Maximum Ratings
over operating temperature range (unless otherwise noted)(1)
MIN
Pin
voltage(2)
Pin voltage(2)
Pin
voltage(2)
UNIT
VIN, FB, EN, PG
– 0.3
6
V
SW (DC)
– 0.3
VIN + 0.3
V
SW (DC, in current limit)
Pin voltage(2)
MAX
SW (AC, less than 10ns)(3)
–1
VIN + 0.3
– 2.5
10
V
Temperature
Operating Junction, TJ
–40
150
°C
Temperature
Storage, TSTG
–65
150
°C
(1)
(2)
(3)
Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
All voltage values are with respect to the network ground terminal
While switching
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC
JS-001(1)
±2000
Charged device model (CDM), per JEDEC
specificationJESD22-C101(2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
Over operating temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VIN
Input voltage range
2.5
5.5
V
VOUT
Output voltage range
0.6
4.0
V
IOUT
Output curent range
VPG
Pull-up resistor voltage
0
ISINK_PG
Sink current at PG pin
TJ
Operating junction temperature
–40
4
A
5.5
V
1
mA
125
°C
6.4 Thermal Information
THERMAL
TLV62595
TLV62595EVM-794
DMQ (JEDEC)
DMQ (EVM)
6 PINS
6 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
129.5
71.4
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
103.9
n/a
°C/W
RθJB
Junction-to-board thermal resistance
33.1
n/a
°C/W
ΨJT
Junction-to-top characterization parameter
3.8
3.9
°C/W
YJB
Junction-to-board characterization parameter
33.1
38.6
°C/W
(1)
4
METRIC(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
TJ = 25 °C and VIN = 5 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
IQ
Quiescent current
EN = High, no load, device not switching
ISD
Shutdown current
EN = Low, TJ = -40℃ to 85℃
Undervoltage lock out threshold
VIN falling
Undervoltage lock out hysteresis
VIN rising
160
mV
Thermal shutdown threshold
TJ rising
150
°C
Thermal shutdown hysteresis
TJ falling
20
°C
VUVLO
TJSD
2.1
10
µA
0.05
µA
2.2
2.3
V
LOGIC INTERFACE EN
VIH
High-level threshold voltage
VIN = 2.5 V to 5.5 V
VIL
Low-level threshold voltage
VIN = 2.5 V to 5.5 V
1.0
V
0.4
V
SOFT START, POWER GOOD
tSS
Soft start time
Power good lower threshold
VPG
Power good upper threshold
Time from EN high to 95% of VOUT nominal
VPG rising, VFB referenced to VFB nominal
1.75
ms
96
%
VPG falling, VFB referenced to VFB nominal
92
%
VPG rising, VFB referenced to VFB nominal
105
%
VPG falling, VFB referenced to VFB nominal
110
VPG,OL
Low-level output voltage
Isink = 1 mA
IPG,LKG
Input leakage current into PG pin
VPG = 5.0 V
0.01
PG rising edge
100
PG falling edge
20
tPG,DLY
Power good deglitch delay
%
0.4
V
µA
µs
OUTPUT
VFB
Feedback regulation voltage
PWM mode, 2.5 V ≤ VIN ≤ 5.5 V, TJ = -40°C to
125°C
IFB,LKG
Feedback input leakage current for
adjustable output voltage
VFB = 0.6 V
0.01
µA
IDIS
Output discharge current
VSW = 0.4V; EN = LOW
400
mA
Load regulation
IOUT = 0.5 A to 3 A, VOUT = 1.8 V
0.1
%/A
High-side FET on-resistance
26
mΩ
Low-side FET on-resistance
25
mΩ
594
600
606
mV
POWER SWITCH
RDS(on)
ILIM
High-side FET switch current limit, DC
fSW
PWM switching frequency
4.8
IOUT = 1 A, VOUT = 1.8 V
5.6
A
2.2
MHz
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70.0
70.0
60.0
60.0
50.0
50.0
RDS(on) (mOhm)
RDS(on) (mOhm)
6.6 Typical Characteristics
40.0
30.0
20.0
10.0
0.0
2.5
3.5
4.0
4.5
Input Voltage (V)
5.0
0.0
2.5
5.5
3.5
4.0
4.5
Input Voltage (V)
5.0
5.5
D011
Figure 6-2. Low-Side FET On-Resistance
8.0
$
TJ = -40 °C
TJ = 25 °C
TJ = 85 °C
TJ = 125 °C
4XLHVFHQW &XUUHQW
$
6KXWGRZQ &XUUHQW
3.0
D010
0.5
0.3
0.2
0.1
0.0
2.5
TJ = 0 °C
TJ = 25 °C
TJ = 85 °C
TJ = 125 °C
10.0
Figure 6-1. High-Side FET On-Resistance
0.4
30.0
20.0
TJ = 0 °C
TJ = 25 °C
TJ = 85 °C
TJ = 125 °C
3.0
40.0
3.0
3.5
4.0
4.5
Input Voltage (V)
5.0
6.0
4.0
2.0
TJ = -40 °C
TJ = 25 °C
TJ = 85 °C
TJ = 125 °C
0.0
2.5
5.5
3.0
3.5
D000
Figure 6-3. Shutdown Current
4.0
4.5
Input Voltage (V)
5.0
5.5
D001
Figure 6-4. Quiescent Current
500
Output Discharge Current (mA)
450
400
350
300
250
200
150
TJ = 0 °C
TJ = 25 °C
TJ = 85 °C
TJ = 125 °C
100
50
0
2.5
3.0
3.5
4.0
4.5
Input Voltage (V)
5.0
5.5
D012
Figure 6-5. Output Discharge Current
6
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7 Detailed Description
7.1 Overview
The TLV62595 are synchronous step-down converters based on the DCS-Control topology with an adaptive
constant on-time control and a stabilized switching frequency. It operates in PWM (pulse width modulation) mode
for medium to heavy loads and in PSM (power save mode) at light load conditions, keeping the output voltage
ripple small. The nominal switching frequency is about 2.2 MHz with a small and controlled variation over the
input voltage range. As the load current decreases, the converter enters PSM, reducing the switching frequency
to keep efficiency high over the entire load current range. Since combining both PWM and PSM within a single
building block, the transition between modes is seamless and without effect on the output voltage. The devices
offer both excellent dc voltage and fast load transient regulation, combined with a very low output voltage ripple.
7.2 Functional Block Diagram
PG
Control Logic
EN
VFB
VREF
Soft-Start
UVLO
Thermal
Shutdown
VIN
VFB
FB
Ramp
VSW
VIN
Peak Current Detect
VREF
EA
HICCUP
Comp
VSW
Modulator
SW
Gate Drive
Ton
Output
Discharge
VIN
VSW
Zero Current Detect
0.6 V
Or
Fixed Output Voltages
VREF
GND
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7.3 Feature Description
7.3.1 Pulse Width Modulation (PWM) Operation
At load currents larger than half the inductor ripple current, the device operates in pulse width modulation in
continuous conduction mode (CCM). The PWM operation is based on an adaptive constant on-time control with
stabilized switching frequency. To achieve a stable switching frequency in a steady state condition, the on-time is
calculated as:
TON =
VOUT
× 450ns
VIN
(1)
7.3.2 Power Save Mode (PSM) Operation
To maintain high efficiency at light loads, the device enters power save mode (PSM) at the boundary to
discontinuous conduction mode (DCM). This happens when the output current becomes smaller than half of the
ripple current of the inductor. The device operates now with a fixed on-time and the switching frequency further
decreases proportionally to the load current. It can be calculated as:
fPSM =
2 × IOUT
V éV - VOUT ù
2
× IN ê IN
TON
ú
VOUT ë
L
û
(2)
In PSM, the output voltage rises slightly above the nominal target, which can be minimized using larger output
capacitance. At duty cycles larger than 90%, the device may not enter PSM. The device maintains output
regulation in PWM mode.
7.3.3 Minimum Duty Cycle and 100% Mode Operation
There is no limitation for small duty cycles, since even at very low duty cycles, the switching frequency is
reduced as needed to always ensure a proper regulation.
If the output voltage level comes close to the input voltage, the device enters 100% mode. While the high-side
switch is constantly turned on, the low-side switch is switched off. The difference between VIN and VOUT is
determined by the voltage drop across the high-side FET and the dc resistance of the inductor. The minimum
VIN that is needed to maintain a specific VOUT value is estimated as:
VIN,MIN = VOUT + IOUT,MAX ´ (RDS(on) + RL )
(3)
where
•
•
•
•
VIN,MIN = Minimum input voltage to maintain an output voltage
IOUT,MAX = Maximum output current
RDS(on) = High-side FET ON-resistance
RL = Inductor ohmic resistance (DCR)
7.3.4 Soft Start
About 250 μs after EN goes high, the internal soft-start circuitry controls the output voltage during start-up. This
avoids excessive inrush current and ensures a controlled output voltage ramp. It also prevents unwanted voltage
drops from high-impedance power sources or batteries. The TLV62595 can start into a pre-biased output.
7.3.5 Switch Current Limit and HICCUP Short-Circuit Protection
The switch current limit prevents the device from drawing excessive current in case of externally-caused
overcurrent or short circuit condition. Due to an internal propagation delay (typically 60 ns), the actual ac peak
current can exceed the static current limit during that time.
8
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If the current limit threshold is reached, the device delivers its maximum output current. Detecting this condition
for 32 switching cycles (about 13 μs), the device turns off the high-side MOSFET for about 100 μs which allows
the inductor current to decrease through the low-side MOSFET's body diode and then restart again with a soft
start cycle. As long as the overload condition is present, the device hiccups that way, limiting the output power.
7.3.6 Undervoltage Lockout
The undervoltage lockout (UVLO) function prevents misoperation of the device, if the input voltage drops below
the UVLO threshold. It is set to about 2.2 V with a hysteresis of typically 160 mV.
7.3.7 Thermal Shutdown
The junction temperature (TJ) of the device is monitored by an internal temperature sensor. If TJ exceeds 150°C
(typ.), the device goes in thermal shutdown with a hysteresis of typically 20°C. Once the TJ has decreased
enough, the device resumes normal operation.
7.4 Device Functional Modes
7.4.1 Enable, Disable and Output Discharge
The device starts operation, when Enable (EN) is set High. The input threshold levels are typically 0.9 V for
rising and 0.7 V for falling signals. Do not leave EN floating. Shutdown is forced if EN is pulled low with a
shutdown current of typically 50 nA. During shutdown, the internal power MOSFETs as well as the entire control
circuitry, are turned off and the output voltage is actively discharged through the SW pin by a current sink.
Therefore VIN must remain present for the discharge to function.
7.4.2 Power Good
The TLV62595 has a built-in power good (PG) function. The PG pin goes high impedance, when the output
voltage has reached its nominal value. Otherwise, including when disabled, in UVLO or in thermal shutdown, PG
is low (see Table 7-1). The PG function is formed with a window comparator, which has an upper and lower
voltage threshold. The PG pin is an open-drain output and is specified to sink up to 1 mA. The power good
output requires a pullup resistor connecting to any voltage rail less than 5.5 V.
The PG signal can be used for sequencing of multiple rails by connecting it to the EN pin of other converters.
Leave the PG pin unconnected when not used. The PG rising edge has a 100-µs blanking time and the PG
falling edge has a deglitch delay of 20 µs.
Table 7-1. PG Pin Logic
LOGIC STATUS
DEVICE CONDITIONS
HIGH Z
EN = High, VFB ≥ 0.576 V
Enable
√
EN = High, VFB ≤ 0.552 V
EN = High, VFB ≤ 0.63 V
LOW
√
√
EN = High, VFB ≥ 0.66 V
√
Shutdown
EN = Low
√
Thermal Shutdown
TJ > TJSD
√
UVLO
0.7 V < VIN < VUVLO
Power Supply Removal
VIN < 0.7 V
√
√
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The following section discusses the design of the external components to complete the power supply design for
several input and output voltage options by using typical applications as a reference.
8.2 Typical Application
VIN
2.5 V to 5.5 V
TLV62595
VIN
C1
4.7 µF
R3
100 k
L1
0.47 µH
VOUT
1.8 V
SW
C2
3x10 µF
EN
R1
200 k
C3
120 pF
VPG
PG GND FB
R2
100 k
Figure 8-1. Typical Application of TLV62595
8.2.1 Design Requirements
For this design example, use the parameters listed in Table 8-1 as the input parameters.
Table 8-1. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage, TLV62595
2.5 V to 5.5 V
Output voltage
1.8 V
Output ripple voltage
