TLV6700QDSERQ1

TLV6700-Q1 TLV6700-Q1 SNVSBG5 – NOVEMBER 2020 SNVSBG5 – NOVEMBER 2020 www.ti.com TLV6700-Q1 Micropower, 18-V Window Comparator With 400-mV Reference 1 Features 3 Description • • The TLV6700-Q1 is a high voltage window comparator that operates over a 1.8 V to 18 V range. The device has two high-accuracy comparators with an internal 400-mV reference and two open-drain outputs rated to 18 V. The TLV6700-Q1 can be used as a window comparator or as two independent comparators; the monitored voltage can be set with the use of external resistors. • • • • • 2 Applications • • • • OUTA is driven low when the voltage at INA+ drops below (V ITP – V HYS), and goes high when the voltage returns above the respective threshold (V ITP). OUTB is driven low when the voltage at INB– rises above V ITP, and goes high when the voltage drops below the respective threshold (V ITP – V HYS). Both comparators in the TLV6700-Q1 include built-in hysteresis to reject brief glitches, thereby ensuring stable output operation without false triggering. The TLV6700-Q1 is available in a Thin SOT-23-6 and leadless WSON-6; the comparators are specified over the junction temperature range of –40°C to 125°C. Device Information (1) Emergency call (eCall) Automotive head unit Instrument cluster On-board (OBC) & wireless charger PART NUMBER TLV6700-Q1 (1) PACKAGE 2.90 mm × 1.60 mm WSON (6) 1.50 mm × 1.50 mm For all available packages, see the orderable addendum at the end of the datasheet. VPULL-UP (Up To 18 V) OUTA 1.8 V to 18 V VDD OUTA INA+ BODY SIZE (NOM) SOT-23 (6) INA+ OUTB INB– VIT+ OUTB • • • Qualified for automotive applications AEC-Q100 qualified with the following results: – Device temperature Grade 1: –40°C to 125°C ambient operating temperature range – Device HBM ESD classification level H2 – Device CDM ESD classification level C6 Wide supply voltage range: 1.8 V to 18 V Adjustable threshold: down to 400 mV High threshold accuracy: – 0.5% Max at 25°C – 1.0% Max over temperature Low quiescent current: 5.5 µA (Typ) Open-drain outputs Internal hysteresis: 5.5 mV (Typ) Temperature range: –40°C to 125°C Package: – thin SOT-23-6 – Leadless WSON-6 INB± VIT+ Output Response Reference GND Simplified Block Diagram An©IMPORTANT NOTICEIncorporated at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, Copyright 2020 Texas Instruments Submit Document Feedback intellectual property matters and other important disclaimers. PRODUCTION DATA. Product Folder Links: TLV6700-Q1 1 TLV6700-Q1 www.ti.com SNVSBG5 – NOVEMBER 2020 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Device Comparison Table...............................................3 6 Pin Configuration and Functions...................................4 7 Specifications.................................................................. 5 7.1 Absolute Maximum Ratings........................................ 5 7.2 ESD Ratings............................................................... 5 7.3 Recommended Operating Conditions.........................5 7.4 Thermal Information....................................................5 7.5 Electrical Characteristics.............................................6 7.6 Timing Requirements.................................................. 7 7.7 Switching Characteristics............................................7 7.8 Timing Diagrams ........................................................ 7 7.9 Typical Characteristics................................................ 8 8 Detailed Description......................................................10 8.1 Overview................................................................... 10 8.2 Functional Block Diagram......................................... 10 8.3 Feature Description...................................................10 8.4 Device Functional Modes..........................................12 9 Application and Implementation.................................. 13 9.1 Application Information............................................. 13 9.2 Typical Application.................................................... 16 9.3 Do's and Don'ts.........................................................18 10 Power Supply Recommendations..............................19 11 Layout........................................................................... 20 11.1 Layout Guidelines................................................... 20 11.2 Layout Example...................................................... 20 12 Device and Documentation Support..........................21 12.1 Device Support....................................................... 21 12.2 Receiving Notification of Documentation Updates..21 12.3 Support Resources................................................. 21 12.4 Trademarks............................................................. 21 12.5 Electrostatic Discharge Caution..............................21 12.6 Glossary..................................................................21 13 Mechanical, Packaging, and Orderable Information.................................................................... 21 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE November 2020 2 REVISION NOTES * Initial Release Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TLV6700-Q1 TLV6700-Q1 www.ti.com SNVSBG5 – NOVEMBER 2020 5 Device Comparison Table Table 5-1. Industrial TLV67xx Comparator Family PART NUMBER CONFIGURATION OPERATING VOLTAGE RANGE THRESHOLD ACCURACY OVER TEMPERATURE TLV6700 Window 1.8 V to 18 V 1% TLV6703 Non-Inverting Single Channel 1.8 V to 18 V 1% TLV6710 Window 1.8 V to 36 V 0.75% TLV6713 Non-Inverting Single Channel 1.8 V to 36 V 0.75% Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TLV6700-Q1 3 TLV6700-Q1 www.ti.com SNVSBG5 – NOVEMBER 2020 6 Pin Configuration and Functions OUTA 1 6 OUTB GND 2 5 VDD INA+ 3 4 INB- Figure 6-1. DDC Package, SOT-23-6, Top View OUTB 1 6 OUTA VDD 2 5 GND INB- 3 4 INA+ Figure 6-2. DSE Package, WSON-6, Top View Table 6-1. Pin Functions PIN 4 I/O DESCRIPTION NAME DDC DSE GND 2 5 — INA+ 3 4 I This pin is connected to the voltage to be monitored with the use of an external resistor divider. When the voltage at this terminal drops below the threshold voltage (VITP – V HYS), OUTA is driven low. INB– 4 3 I This pin is connected to the voltage to be monitored with the use of an external resistor divider. When the voltage at this terminal exceeds the threshold voltage (VITP), OUTB is driven low. OUTA 1 6 O INA+ comparator open-drain output. OUTA is driven low when the voltage at this comparator is below (VITP – VHYS). The output goes high when the sense voltage returns above the respective threshold (VITP). OUTB 6 1 O INB– comparator open-drain output. OUTB is driven low when the voltage at this comparator exceeds VITP. The output goes high when the sense voltage returns below the respective threshold (VITP – VHYS). VDD 5 2 I Supply voltage input. Connect a 1.8-V to 18-V supply to VDD to power the device. Good analog design practice is to place a 0.1-µF ceramic capacitor close to this pin. Ground Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TLV6700-Q1 TLV6700-Q1 www.ti.com SNVSBG5 – NOVEMBER 2020 7 Specifications 7.1 Absolute Maximum Ratings over operating temperature range (unless otherwise noted)(1) MIN MAX UNIT VDD –0.3 20 V OUTA, OUTB –0.3 20 V INA+, INB– –0.3 7 V 40 mA Operating junction temperature, TJ –40 125 °C Storage temperature, Tstg –65 150 °C Voltage(2) Current (1) (2) Output terminal current Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to network ground terminal. 7.2 ESD Ratings VALUE V(ESD) (1) Electrostatic discharge Human body model (HBM), per AEC Q100-002 (1) ±2500 Charged-device model (CDM), per AEC Q100-011 ±1000 UNIT V JEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification. 7.3 Recommended Operating Conditions over operating temperature range (unless otherwise noted) MIN NOM MAX UNIT VDD Supply voltage 1.8 18 V VI Input voltage INA+, INB– 0 6.5 V VO Output voltage OUTA, OUTB 0 18 V 7.4 Thermal Information THERMAL METRIC(1) DDC (SOT) DSE (WSON) 6 PINS 6 PINS UNIT RθJA Junction-to-ambient thermal resistance 204.6 194.9 °C/W RθJC(top) Junction-to-case (top) thermal resistance 50.5 128.9 °C/W RθJB Junction-to-board thermal resistance 54.3 153.8 °C/W ψJT Junction-to-top characterization parameter 0.8 11.9 °C/W ψJB Junction-to-board characterization parameter 52.8 157.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TLV6700-Q1 5 TLV6700-Q1 www.ti.com SNVSBG5 – NOVEMBER 2020 7.5 Electrical Characteristics Over the operating temperature range of TJ = –40°C to 125°C, and 1.8 V < VDD < 18 V, unless otherwise noted. Typical values are at TJ = 25°C and VDD = 5 V. PARAMETER V(POR) Power-on reset voltage(1) VIT+ Positive-going input threshold voltage VIT– Negative-going input threshold voltage Vhys Hysteresis voltage (hys = VIT+ – VIT–) I(INA+) Input current (at the INA+ terminal) I(INB–) Input current (at the INB– terminal) VOL Low-level output voltage Ilkg(OD) Open-drain output leakage-current TEST CONDITIONS MIN VDD = 1.8V and 18 V, TJ = 25°C 398 VDD = 1.8V and 18 V, TJ = –40°C to 125°C 396 VDD = 1.8V and 18 V, TJ = 25°C Supply current 391.6 (1) (2) (3) 6 Undervoltage 402.5 404 394.5 397.5 400 V mV mV 387 5.5 12 mV VDD = 1.8 V and 18 V, VI = 6.5 V –25 1 25 nA VDD = 1.8 V and 18 V, VI = 0.1 V –15 1 15 nA VDD = 1.8 V, IO = 3 mA 250 VDD = 5 V, IO = 5 mA 250 VDD = 1.8 V and 18 V, VO = VDD 300 VDD = 1.8 V, VO = 18 V 300 5.5 11 VDD = 5 V 6 13 VDD = 12 V 6 13 VDD = 18 V UVLO 400 UNIT VDD = 1.8V and 18 V, TJ = –40°C to 125°C Start-up delay(2) lockout(3) MAX 0.8 VDD = 1.8 V, no load IDD TYP VOLmax = 0.2 V, I(OUTA/B) = 15 µA VDD falling 1.3 mV nA µA 7 13 150 450 µs 1.7 V The lowest supply voltage (VDD) at which output is active; tr(VDD) > 15 µs/V. Below V(POR), the output cannot be determined. During power on, VDD must exceed 1.8 V for 450 µs (max) before the output is in a correct state. When VDD falls below UVLO, OUTA is driven low and OUTB goes to high impedance. The outputs cannot be determined below V(POR). Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TLV6700-Q1 TLV6700-Q1 www.ti.com SNVSBG5 – NOVEMBER 2020 7.6 Timing Requirements over operating temperature range (unless otherwise noted) MIN NOM MAX UNIT tPHL High-to-low propagation delay(1) VDD = 5 V, 10-mV input overdrive, RP = 10 kΩ, VOH = 0.9 × VDD, VOL = 400 mV, see Figure 7-1 18 µs tPLH Low-to-high propagation delay(1) VDD = 5 V, 10-mV input overdrive, RP = 10 kΩ, VOH = 0.9 × VDD, VOL = 400 mV, see Figure 7-1 29 µs (1) High-to-low and low-to-high refers to the transition at the input terminals (INA+ and INB–). 7.7 Switching Characteristics Over operating temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN tr Output rise time VDD = 5 V, 10-mV input overdrive, RP = 10 kΩ, VO = (0.1 to 0.9) × VDD tf Output fall time VDD = 5 V, 10-mV input overdrive, RP = 10 kΩ, VO = (0.1 to 0.9) × VDD TYP MAX UNIT 2.2 µs 0.22 µs 7.8 Timing Diagrams VDD VIT+ Vhys INA+ OUTA tPHL tPLH tPLH VIT+ Vhys INB– OUTB tPLH tPHL Figure 7-1. Timing Diagram Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TLV6700-Q1 7 TLV6700-Q1 www.ti.com SNVSBG5 – NOVEMBER 2020 7.9 Typical Characteristics at TJ = 25°C and VDD = 5 V (unless otherwise noted) 10 Positive-Going Input Threshold (mV) 401 9 Supply Current (µA) 8 7 6 5 4 3 40qC 0qC 25qC 85qC 125qC 2 1 2 4 6 8 10 12 Supply Voltage (V) 14 16 D001 1.8 V 5V 1.2 V 18 V 399.8 399.4 -25 -10 5 20 35 50 65 Temperature (qC) 80 95 110 125 D003 Figure 7-3. Rising Input Threshold Voltage (VIT+) vs Temperature 9 Low-to-High Propagation Delay (µs) 31 8 Hysteresis Voltage (mV) = = = = 400.2 18 Figure 7-2. Supply Current (IDD) vs Supply Voltage (VDD) 7 6 5 VDD VDD VDD VDD 4 3 -40 -25 -10 5 20 35 50 65 Temperature (qC) 80 95 = = = = 1.8 V 5V 12 V 18 V 18 26 16 Input Pulse Duration (µs) 20 24 22 20 18 16 VDD = 1.8 V, INB to OUTB VDD = 18 V, INB to OUTB VDD = 1.8 V, INA+ to OUTA VDD = 18 V, INA+ to OUTA 10 8 -40 -25 -10 5 20 35 50 65 Temperature (qC) 25 23 21 19 17 15 13 11 -25 80 95 -10 5 20 35 50 65 Temperature (qC) 80 95 110 125 D005 Figure 7-5. Propagation Delay vs Temperature (High-to-Low Transition at the Inputs) 28 12 27 D004 30 14 VDD = 1.8 V, INB to OUTB VDD = 18 V, INB to OUTB VDD = 1.8 V, INA+ to OUTA VDD = 18 V, INA+ to OUTA 29 9 -40 110 125 Figure 7-4. Hysteresis (Vhys) vs Temperature Low-to-High Propagation Delay (µs) 400.6 399 -40 0 0 VDD VDD VDD VDD INA+ INB– 14 12 10 8 6 4 2 110 125 D006 0 2.5 4 5.5 7 8.5 10 11.5 13 14.5 Positive-Going Input Threshold Overdrive (%) 16 D007 INA+ = negative spike below VIT– INB– = positive spike above VIT+ Figure 7-6. Propagation Delay vs Temperature (Low-to-High Transition at the Inputs) 8 Figure 7-7. Minimum Pulse Duration vs Threshold Overdrive Voltage Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TLV6700-Q1 TLV6700-Q1 www.ti.com SNVSBG5 – NOVEMBER 2020 7.9 Typical Characteristics (continued) at TJ = 25°C and VDD = 5 V (unless otherwise noted) 2000 10 1750 Low-Level Output Voltage(mV) 11 Supply Current (µA) 9 8 7 6 5 4 40qC 0qC 25qC 85qC 125qC 3 2 4 8 12 16 20 24 28 Output Sink Current (mA) 32 36 1000 750 500 250 0 5 10 15 20 25 30 Output Sink Current (mA) 35 40 D009 D008 Figure 7-9. Output Voltage Low (VOL) vs Output Sink Current (– 40°C) 2000 2000 VDD = 1.8 V VDD = 5 V VDD = 18 V 1750 Low-Level Output Voltage (mV) Low-Level Output Voltage(mV) 1250 40 Figure 7-8. Supply Current (IDD) vs Output Sink Current 1500 1250 1000 750 500 250 0 VDD = 1.8 V VDD = 5 V VDD = 18 V 1750 1500 1250 1000 750 500 250 0 0 5 10 15 20 25 30 Output Sink Current (mA) 35 40 0 5 10 D010 Figure 7-10. Output Voltage Low (VOL) vs Output Sink Current (0°C) 15 20 25 30 Output Sink Current (mA) 35 40 D011 Figure 7-11. Output Voltage Low (VOL) vs Output Sink Current (25°C) 2000 2000 VDD = 1.8 V VDD = 5 V VDD = 18 V VDD = 1.8 V VDD = 5 V VDD = 18 V 1750 Low-level output voltage (mV) 1750 Low-level output voltage (mV) 1500 0 1 0 VDD = 1.8 V VDD = 5 V VDD = 18 V 1500 1250 1000 750 500 250 1500 1250 1000 750 500 250 0 0 0 5 10 15 20 25 30 Output Sink Current (mA) 35 40 0 D012 Figure 7-12. Output Voltage Low (VOL) vs Output Sink Current (85°C) 5 10 15 20 25 30 Output Sink Current (mA) 35 40 D013 Figure 7-13. Output Voltage Low (VOL) vs Output Sink Current (125°C) Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TLV6700-Q1 9 TLV6700-Q1 www.ti.com SNVSBG5 – NOVEMBER 2020 8 Detailed Description 8.1 Overview The TLV6700-Q1 device combines two comparators for overvoltage and undervoltage detection. The TLV6700Q1 has a wide-supply voltage range (1.8 V to 18 V) with a high-accuracy rising-input threshold of 400 mV (1% over temperature) and built-in hysteresis. The outputs are also rated to 18 V, independant of supply voltage, and can sink up to 40 mA. The TLV6700-Q1 is designed to assert the output signals, as shown in Table 8-1. Each input terminal can be set to monitor any voltage above 0.4 V using an external resistor divider network. Each input pin has very low input leakage current, allowing the use of large resistor dividers without sacrificing system accuracy. With the use of two input terminals of different polarities, the TLV6700-Q1 forms a window comparator. The relationship between the inputs and the outputs is shown in Table 8-1. Broad voltage thresholds can be supported that allow the device to be used in a wide array of applications. Table 8-1. TLV6700 Truth Table CONDITION OUTPUT INA+ > VIT+ OUTA high Output A high impedance OUTPUT STATE INA+ < VIT– OUTA low Output A sinking INB– > VIT+ OUTB low Output B sinking INB– < VIT– OUTB high Output B high impedance 8.2 Functional Block Diagram VDD INA+ OUTA OUTB INB– Reference GND 8.3 Feature Description 8.3.1 Inputs (INA+, INB–) The TLV6700-Q1 device combines two comparators. Each comparator has one external input (inverting and noninverting); the other input is connected to the internal reference. The comparator rising threshold is designed and trimmed to be equal to the reference voltage (400 mV). Both comparators also have a built-in falling hysteresis that makes the device less sensitive to supply rail noise and ensures stable operation. The comparator inputs can swing from ground to 6.5 V, regardless of the device supply voltage used. Although not required in most cases, good analog design practice is to place a 1-nF to 10-nF bypass capacitor at the comparator input for extremely noisy applications to reduce sensitivity to transients and layout parasitics. For comparator A, the corresponding output (OUTA) is driven to logic low when the input INA+ voltage drops below (V IT+ – V hys). When the voltage exceeds V IT+, the output (OUTA) goes to a high-impedance state; see Figure 7-1. 10 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TLV6700-Q1 TLV6700-Q1 www.ti.com SNVSBG5 – NOVEMBER 2020 For comparator B, the corresponding output (OUTB) is driven to logic low when the voltage at input INB– exceeds VIT+. When the voltage drops below VIT+ – Vhys the output (OUTB) goes to a high-impedance state; see Figure 7-1. Together, these comparators form a window-detection function as discussed in the Section 8.3.3 section. 8.3.2 Outputs (OUTA, OUTB) In a typical TLV6700-Q1 application, the outputs are connected to a GPIO input of the processor (such as a digital signal processor [DSP], central processing unit [CPU], field-programmable gate array [FPGA], or application-specific integrated circuit [ASIC]). The TLV6700-Q1 device provides two open-drain outputs (OUTA and OUTB). Pullup resistors must be used to hold these lines high when the output goes to high impedance (not asserted). By connecting pullup resistors to the proper voltage rails, the outputs can be connected to other devices at the correct interface-voltage levels. The TLV6700-Q1 outputs can be pulled up to 18 V, independent of the device supply voltage. By using wired-OR logic, OUTA and OUTB can merge into one logic signal that goes low if either outputs are asserted because of a fault condition. Table 8-1 and the Section 8.3.1 section describe how the outputs are asserted or deasserted. See Figure 7-1 for a timing diagram that describes the relationship between threshold voltages and the respective output. 8.3.3 Window Comparator The inverting and noninverting configuration of the comparators forms a window-comparator detection circuit using a resistor divider network, as illustrated in Figure 8-1 and Figure 8-2. The input terminals can monitor any system voltage above 400 mV with the use of a resistor divider network. The INA+ and INB– terminals monitor for undervoltage and overvoltage conditions, respectively. Figure 8-1. Window Comparator Block Diagram Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TLV6700-Q1 11 TLV6700-Q1 www.ti.com SNVSBG5 – NOVEMBER 2020 Overvoltage Limit VMON Undervoltage Limit OUTB OUTA Figure 8-2. Window Comparator Timing Diagram 8.3.4 Immunity to Input Terminal Voltage Transients The TLV6700-Q1 device is relatively immune to short voltage transient spikes on the input terminals. Sensitivity to transients depends on both transient duration and amplitude; see the Minimum Pulse Duration vs Threshold Overdrive Voltage curve (Figure 7-7) in the Section 7.9 section. 8.4 Device Functional Modes 8.4.1 Normal Operation (VDD > UVLO) When the voltage on V DD is greater than 1.8 V for at least 150 µs, the OUTA and OUTB signals correspond to the voltage on INA+ and INB– as listed in Table 8-1. 8.4.2 Undervoltage Lockout (V(POR) < VDD < UVLO) When the voltage on V DD is less than the device UVLO voltage, and greater than the power-on reset voltage, V (POR), the OUTA and OUTB signals are asserted and high impedance, respectively, regardless of the voltage on INA+ and INB–. 8.4.3 Power-On Reset (VDD < V(POR)) When the voltage on V DD is lower than the required voltage to internally pull the asserted output to GND (V (POR)), both outputs are in a high-impedance state. 12 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TLV6700-Q1 TLV6700-Q1 www.ti.com SNVSBG5 – NOVEMBER 2020 9 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The TLV6700-Q1 device is a wide-supply voltage window comparator that operates over a VDD range of 1.8 V to 18 V. The device has two high-accuracy comparators with an internal 400-mV reference and two open-drain outputs rated to 18 V for overvoltage and undervoltage detection. The device can be used either as a window comparator or as two independent voltage monitors. The monitored voltages are set with the use of external resistors. 9.1.1 VPULLUP to a Voltage Other Than VDD The outputs are often tied to V DD through a resistor. However, some applications may require the outputs to be pulled up to a higher or lower voltage than VDD to correctly interface with the input terminals of other devices. Figure 9-1. Interfacing to Voltages Other Than VDD Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TLV6700-Q1 13 TLV6700-Q1 www.ti.com SNVSBG5 – NOVEMBER 2020 9.1.2 Monitoring VDD Many applications monitor the same rail that is powering V DD. In these applications the resistor divider is simply connected to the VDD rail. Figure 9-2. Monitoring the Same Voltage as VDD 9.1.3 Monitoring a Voltage Other Than VDD Some applications monitor rails other than the one that is powering V DD. In these types of applications the resistor divider used to set the desired thresholds is connected to the rail that is being monitored. 14 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TLV6700-Q1 TLV6700-Q1 www.ti.com SNVSBG5 – NOVEMBER 2020 The inputs can monitor a voltage higher than VDDmax with the use of an external resistor divider network. Figure 9-3. Monitoring a Voltage Other Than VDD Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TLV6700-Q1 15 TLV6700-Q1 www.ti.com SNVSBG5 – NOVEMBER 2020 9.2 Typical Application The TLV6700-Q1 device is a wide-supply voltage window comparator that operates over a V DD range of 1.8 to 18 V. The monitored voltages are set with the use of external resistors, so the device can be used either as a window comparator or as two independent overvoltage and undervoltage monitors. VDD C1 0.1 µF VPULLUP R4 49.9 k U1 TLV670 0DDC R1 2.21 M VDD INA+ INB± R2 13.7 k 5 1 3 6 4 2 R5 49.9 k OUTA OUTB GND R3 69.8 k Figure 9-4. Typical Application Schematic 9.2.1 Design Requirements For this design example, use the values summarized in Table 9-1 as the input parameters. Table 9-1. Design Parameters PARAMETER DESIGN REQUIREMENT DESIGN RESULT Monitored voltage 12-V nominal rail with maximum rising and falling thresholds of ±10% VMON(UV)= 10.99 V (8.33%) ±2.94%, VMON(OV)= 13.14 V (8.33%) ±2.94% 9.2.2 Detailed Design Procedure 9.2.2.1 Resistor Divider Selection Use Equation 1 through Equation 4 to calculate the resistor divider values and target threshold voltages. RT = R1 + R2 + R3 (1) Select a value for R T such that the current through the divider is approximately 100 times higher than the input current at the INA+ and INB– terminals. The resistors can have high values to minimize current consumption as a result of low-input bias current without adding significant error to the resistive divider. See the application note Optimizing Resistor Dividers at a Comparator Input (SLVA450) for details on sizing input resistors. Use Equation 2 to calculate the value of R3. R3 = RT VMON(OV) ´ VIT+ (2) where: VMON(OV) is the target voltage at which an overvoltage condition is detected 16 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TLV6700-Q1 TLV6700-Q1 www.ti.com SNVSBG5 – NOVEMBER 2020 Use Equation 3 or Equation 4 to calculate the value of R2. R2 = RT VMON (no UV) ´ VIT+ - R3 (3) where: VMON(no UV) is the target voltage at which an undervoltage condition is removed as VMON rises R2 = RT VMON(UV) ´ (VIT+ - Vhys) - R3 (4) where: VMON(UV) is the target voltage at which an undervoltage condition is detected The worst-case tolerance can be calculated by referring to Equation 13 in application report SLVA450, Optimizing Resistor Dividers at a Comparator Input (available for download at www.ti.com). An example of the rising threshold error, VMON(OV), is given in Equation 5. V % ACC = % TOL(VIT+(INB)) + 2 ´ 1- IT+(INB) ´ % TOLR = 1% + 2 ´ 1- 0.4 ´ 1% = 2.94% VMON(OV) 13.2 (5) 9.2.2.2 Pullup Resistor Selection To ensure proper voltage levels, the pullup resistor value is selected by ensuring that the pullup voltage divided by the resistor does not exceed the sink-current capability of the device. This confirmation is calculated by verifying that the pullup voltage minus the output-leakage current (Ilkg(OD)) multiplied by the resistor is greater the desired logic-high voltage. These values are specified in the Section 7.5 table. Use Equation 6 to calculate the value of the pullup resistor. VPU (VHI - VPU) ³ RPU ³ IO Ilkg(OD) (6) 9.2.2.3 Input Supply Capacitor Although an input capacitor is not required for stability, connecting a 0.1-μF low equivalent series resistance (ESR) capacitor across the V DD terminal and GND terminal is good analog design practice. A higher-value capacitor may be necessary if large, fast rise-time load transients are anticipated, or if the device is not located close to the power source. 9.2.2.4 Input Capacitors Although not required in most cases, for extremely noisy applications, placing a 1-nF to 10-nF bypass capacitor from the comparator inputs (INA+, INB–) to the GND terminal is good analog design practice. This capacitor placement reduces device sensitivity to transients. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TLV6700-Q1 17 TLV6700-Q1 www.ti.com SNVSBG5 – NOVEMBER 2020 9.2.3 Application Curves At TJ = 25°C OUTB C2 (2 V/div) C1 (2 V/div) C2 (2 V/div) OUTB OUTA C3 (2 V/div) C1 (2 V/div) C3 (2 V/div) VDD Time (100 µs/div) VDD = 5 V OUTA V(INA+) = 390 mV VDD Time (100 µs/div) G013 V(INB–) = 410 mV Figure 9-5. Start-Up Delay (OUT Pulled Up to VDD) VDD = 5 V V(INA+) = 410 mV G014 V(INB–) = 390 mV Figure 9-6. Start-Up Delay (OUT Pulled Up to VDD) 9.3 Do's and Don'ts It is good analog design practice to have a 0.1-µF decoupling capacitor from VDD to GND. If the monitored rail is noisy, connect decoupling capacitors from the comparator inputs to GND. Do not use resistors for the voltage divider that cause the current through them to be less than 100 times the input current of the comparators without also accounting for the effect to the accuracy. Do not use pullup resistors that are too small, because the larger current sunk by the output then exceeds the desired low-level output voltage (VOL). 18 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TLV6700-Q1 TLV6700-Q1 www.ti.com SNVSBG5 – NOVEMBER 2020 10 Power Supply Recommendations The TLV6700-Q1 has a 20 V absolute maximum rating on the VDD pin, with a recommended operating condition of 18V. If the voltage supply that is providing power to VDD is susceptible to any large voltage transient that may exceed 20 V, or if the supply exhibits high voltage slew rates greater than 1 V/µs, take additional precautions. Place an RC filter between the supply and VDD to filter any high-frequency transient surges on the VDD pin. A 100-Ω resistor and 0.01-µF capacitor is required in these cases, as shown in Figure 10-1. 100 Ÿ 0.01 F + ± VPULLUP R1 VDD INA OUTA INB OUTB R2 R3 GND Figure 10-1. Using an RC Filter to Remove High-Frequency Disturbances on VDD Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TLV6700-Q1 19 TLV6700-Q1 www.ti.com SNVSBG5 – NOVEMBER 2020 11 Layout 11.1 Layout Guidelines Placing a 0.1-µF capacitor close to the VDD terminal to reduce the input impedance to the device is good analog design practice. The pullup resistors can be separated if separate logic functions are needed (as shown in Figure 11-1) or both resistors can be tied to a single pullup resistor if a logical AND function is desired. VPULLUP VPULLUP 11.2 Layout Example Figure 11-1. TLV6700 Layout Schematic 20 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TLV6700-Q1 TLV6700-Q1 www.ti.com SNVSBG5 – NOVEMBER 2020 12 Device and Documentation Support 12.1 Device Support 12.1.1 Development Support The DIP Adapter Evaluation Module allows conversion of the SOT-23-6 package to a standard DIP-6 pinout for ease of prototyping and bench evaluation. 12.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.3 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 12.4 Trademarks TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners. 12.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.6 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TLV6700-Q1 21 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TLV6700QDDCRQ1 ACTIVE SOT-23-THIN DDC 6 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 2DI1 TLV6700QDSERQ1 ACTIVE WSON DSE 6 3000 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 K6 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of