TLV70033DDCR

Sample & Buy Product Folder Support & Community Tools & Software Technical Documents TLV700 SLVSA00E – SEPTEMBER 2009 – REVISED APRIL 2015 TLV700 200-mA, Low-IQ, Low-Dropout Regulator for Portable Devices 1 Features 3 Description • The TLV700 series of low-dropout (LDO) linear regulators are low quiescent current devices with excellent line and load transient performance. These LDOs are designed for power-sensitive applications. A precision bandgap and error amplifier provides overall 2% accuracy. Low output noise, very high power-supply rejection ratio (PSRR), and low dropout voltage make this series of devices ideal for most battery-operated handheld equipment. All device versions have thermal shutdown and current limit for safety. 1 • • • • • • • (1) Very Low Dropout: – 43 mV at IOUT = 50 mA, VOUT = 2.8 V – 85 mV at IOUT = 100 mA, VOUT = 2.8 V – 175 mV at IOUT = 200 mA, VOUT = 2.35 V 2% Accuracy Low IQ: 31 μA Available in Fixed-Output Voltages from 1.2 V to 4.8 V High PSRR: 68 dB at 1 kHz Stable With Effective Capacitance of 0.1 μF(1) Thermal Shutdown and Overcurrent Protection Available in 1.5-mm × 1.5-mm SON-6, SOT23-5, and SC-70 Packages Furthermore, these devices are stable with an effective output capacitance of only 0.1 μF. This feature enables the use of cost-effective capacitors that have higher bias voltages and temperature derating. The devices regulate to specified accuracy with no output load. See the Input and Output Capacitor Requirements. The TLV700 series of LDOs are available in 1.5-mm × 1.5-mm SON-6, SOT-5, and SC70 packages. 2 Applications • • • • • • Wireless Handsets Smart Phones, PDAs ZigBee® Networks Bluetooth® Devices Li-Ion Operated Handheld Products WLAN and Other PC Add-on Cards Device Information(1) PART NUMBER TL700xx PACKAGE BODY SIZE (NOM) SC70 (5) 2.00 mm × 1.25 mm SOT (5) 2.90 mm × 1.60 mm WSON (6) 1.50 mm × 1.50 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Typical Application Circuit VIN IN OUT CIN COUT VOUT 1 mF Ceramic TLV700xx On Off EN GND 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TLV700 SLVSA00E – SEPTEMBER 2009 – REVISED APRIL 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 4 5 6.1 6.2 6.3 6.4 6.5 6.6 5 5 5 5 6 7 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description ............................................ 11 7.1 7.2 7.3 7.4 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ 11 11 11 12 8 Application and Implementation ........................ 13 8.1 Application Information............................................ 13 8.2 Typical Application .................................................. 13 9 Power Supply Recommendations...................... 14 10 Layout................................................................... 15 10.1 10.2 10.3 10.4 Layout Guidelines ................................................. Layout Examples................................................... Thermal Protection................................................ Power Dissipation ................................................. 15 15 15 16 11 Device and Documentation Support ................. 17 11.1 11.2 11.3 11.4 11.5 Device Support .................................................... Documentation Support ........................................ Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 17 17 17 17 17 12 Mechanical, Packaging, and Orderable Information ........................................................... 18 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision D (October 2012) to Revision E Page • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ................................................................................................. 1 • Deleted Applications bullet for MP3 Players .......................................................................................................................... 1 • Changed front-page graphic .................................................................................................................................................. 1 • Changed Pin Configuration and Functions section; updated table format ............................................................................ 4 • Changed "free-air temperature" to "junction temperature" in Absolute Maximum Ratings condition statement .................... 5 • Deleted Dissipation Ratings table .......................................................................................................................................... 5 • Changed Thermal Information table; updated thermal resistance values for all packages ................................................... 5 Changes from Revision C (July 2011) to Revision D • Page Updated Figure 5.................................................................................................................................................................... 7 Changes from Revision B (December, 2010) to Revision C Page • Added footnote 2 to Absolute Maximum Ratings table .......................................................................................................... 5 • Changed output current limit typical and maximum specifications......................................................................................... 6 • Deleted previous Figure 12, Current Limit vs Input Voltage typical characteristic ................................................................. 7 Changes from Revision A (April, 2010) to Revision B Page • Removed TLV701xx device references throughout document .............................................................................................. 1 • Changed minimum output voltage available from 0.7 V to 1.2 V ........................................................................................... 1 • Added footnote (1) .................................................................................................................................................................. 1 • Deleted VOUT < 1 V specification ............................................................................................................................................ 6 • Deleted Active pulldown resistance parameter ...................................................................................................................... 6 2 Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: TLV700 TLV700 www.ti.com SLVSA00E – SEPTEMBER 2009 – REVISED APRIL 2015 • Changed Figure 4 title ............................................................................................................................................................ 7 • Changed Figure 5 title ............................................................................................................................................................ 7 • Removed TLV701xx block diagram...................................................................................................................................... 11 • Revised Shutdown section ................................................................................................................................................... 11 • Updated Application Information section to reflect minimum output voltage availability of 1.2 V ........................................ 13 • Deleted references to TLV701xx throughout Application Information .................................................................................. 13 • Changed footnote 2 for Ordering Information table to reflect minimum output voltage of 1.2 V ......................................... 17 Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: TLV700 3 TLV700 SLVSA00E – SEPTEMBER 2009 – REVISED APRIL 2015 www.ti.com 5 Pin Configuration and Functions DSE Package 6-Pin WSON Top View DCK Package 5-Pin SC70 Top View IN 1 6 EN GND 2 5 N/C OUT 3 4 N/C (1) (1) IN 1 GND 2 EN 3 5 OUT 4 N/C (1) DDC Package 5-Pin SOT Top View (1) IN 1 GND 2 EN 3 5 OUT 4 N/C (1) No connection. Pin Functions PIN 4 I/O DESCRIPTION 1 I Input pin. A small, 1-μF ceramic capacitor is recommended from this pin to ground to assure stability and good transient performance. See Input and Output Capacitor Requirements for more details. 2 2 — 6 3 3 I NC 4, 5 4 4 — No connection. This pin can be tied to ground to improve thermal dissipation. OUT 3 5 5 O Regulated output voltage pin. A small, 1-μF ceramic capacitor is needed from this pin to ground to assure stability. See Input and Output Capacitor Requirements for more details. NAME WSON SC70 SOT IN 1 1 GND 2 EN Ground pin Enable pin. Driving EN over 0.9 V turns on the regulator. Driving EN below 0.4 V puts the regulator into shutdown mode and reduces operating current to 1 μA, nominal. Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: TLV700 TLV700 www.ti.com SLVSA00E – SEPTEMBER 2009 – REVISED APRIL 2015 6 Specifications 6.1 Absolute Maximum Ratings over operating junction temperature range (unless otherwise noted) Voltage (1) MIN MAX VIN –0.3 6 VEN –0.3 6 (2) VOUT –0.3 6 Maximum output current IOUT (1) (2) V Internally limited Output short-circuit duration Temperature UNIT Indefinite Operating junction, TJ –55 150 Storage, Tstg –55 150 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. VEN absolute maximum rating is VIN + 0.3 V or 6 V, whichever is less. 6.2 ESD Ratings VALUE Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins V(ESD) (1) (2) Electrostatic discharge (1) Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) UNIT ±2000 V ±500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN VIN NOM MAX 2 VOUT IOUT UNIT 5.5 V 1.2 4.8 V 0 200 mA 6.4 Thermal Information TLV700 THERMAL METRIC (1) DCK [SC70] DDC [SOT] DSE [WSON] 5 PINS 5 PINS 6 PINS RθJA Junction-to-ambient thermal resistance 307.6 235.9 321.3 RθJC(top) Junction-to-case (top) thermal resistance 79.1 61.9 207.9 RθJB Junction-to-board thermal resistance 93.7 54 281.5 ψJT Junction-to-top characterization parameter 1.3 0.8 42.4 ψJB Junction-to-board characterization parameter 92.8 53.4 284.8 RθJC(bot) Junction-to-case (bottom) thermal resistance n/a n/a 142.3 (1) UNIT °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: TLV700 5 TLV700 SLVSA00E – SEPTEMBER 2009 – REVISED APRIL 2015 www.ti.com 6.5 Electrical Characteristics At VIN = VOUT(nom) + 0.3 V or 2 V (whichever is greater); IOUT = 10 mA, VEN = 0.9 V, COUT = 1 μF, and TJ = –40°C to +125°C, unless otherwise noted. Typical values are at TJ = 25°C. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIN Input voltage range VOUT DC output accuracy –40°C ≤ TJ ≤ +125°C ΔVOUT(ΔVIN) Line regulation VOUT(nom) + 0.3 V ≤ VIN ≤ 5.5 V, IOUT = 10 mA 1 5 mV ΔVOUT(ΔIOUT) Load regulation 0 mA ≤ IOUT ≤ 200 mA 1 15 mV Dropout voltage (1) VDO ICL Output current limit IGND Ground pin current ISHDN Ground pin current (shutdown) 5.5 –2% 2% VIN = 0.98 × VOUT(nom), IOUT = 50 mA, VOUT = 2.8 V 43 VIN = 0.98 × VOUT(nom), IOUT = 100 mA, VOUT = 2.8 V 85 VIN = 0.98 × VOUT(nom), IOUT = 200 mA, VOUT = 2.35 V 175 VOUT = 0.9 × VOUT(nom) 220 IOUT = 0 mA 31 270 VEN ≤ 0.4 V, VIN = 2 V 400 VEN ≤ 0.4 V, 2 V ≤ VIN ≤ 4.5 V 1 PSRR Power-supply rejection ratio Vn Output noise voltage BW = 100 Hz to 100 kHz, VIN = 2.3 V, VOUT = 1.8 V, IOUT = 10 mA COUT = 1 μF, IOUT = 200 mA VEN(low) Enable pin low (disabled) IEN Enable pin current VIN = VEN = 5.5 V UVLO Undervoltage lockout VIN rising 1.9 Shutdown, temperature increasing 160 Reset, temperature decreasing 140 (1) (2) 6 nA 2 μs 100 0.9 VIN 0 0.04 –40 μA μVRMS Enable pin high (enabled) Operating junction temperature μA 48 Start-up time TJ 55 mA dB VEN(high) Thermal shutdown temperature 250 68 tSTR Tsd V mV 860 IOUT = 200 mA, VIN = VOUT + 0.5 V VIN = 2.3 V, VOUT = 1.8 V, IOUT = 10 mA, f = 1 kHz (2) 2 V 0.4 V 0.5 μA V °C 125 °C VDO is measured for devices with VOUT(nom) ≥ 2.35 V. Start-up time = time from EN assertion to 0.98 × VOUT(nom). Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: TLV700 TLV700 www.ti.com SLVSA00E – SEPTEMBER 2009 – REVISED APRIL 2015 6.6 Typical Characteristics Over operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(nom) + 0.5 V or 2 V, whichever is greater; IOUT = 10 mA, VEN = VIN, COUT = 1 μF, unless otherwise noted. Typical values are at TJ = 25°C. 1.90 1.90 IOUT = 10 mA 1.88 1.88 1.86 1.84 1.82 1.80 1.78 1.76 +125°C +85°C +25°C -40°C 1.74 1.72 Output Voltage (V) Output Voltage (V) 1.86 IOUT = 200 mA 1.84 1.82 1.80 1.78 1.76 +125°C +85°C +25°C -40°C 1.74 1.72 1.70 1.70 2.1 2.6 3.1 3.6 4.1 4.6 5.1 5.6 2.1 2.6 3.1 Input Voltage (V) Figure 1. TLV70018 Line Regulation 250 Output Voltage (V) 1.86 1.84 1.82 1.80 1.78 1.76 +125°C +85°C +25°C -40°C 1.74 1.72 Dropout Voltage (mV) 1.88 40 60 80 5.1 5.6 100 120 140 160 IOUT = 200 mA 200 150 100 +125°C +85°C +25°C -40°C 0 2.25 180 200 2.75 3.25 3.75 4.75 4.25 Input Voltage (V) Output Current (mA) Figure 3. TLV70018 Load Regulation Figure 4. Dropout Voltage vs Input Voltage 180 1.90 160 1.88 140 1.86 120 100 80 60 +125°C +85°C +25°C -40°C 40 20 Output Voltage (V) Dropout Voltage (mV) 4.6 50 1.70 20 4.1 Figure 2. TLV70018 Line Regulation 1.90 0 3.6 Input Voltage (V) 1.84 1.82 1.80 1.78 1.76 IOUT = 200 mA IOUT = 10 mA IOUT = 150 mA 1.74 1.72 1.70 0 0 30 60 90 120 150 180 210 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature (°C) Output Current (mA) Figure 5. Dropout Voltage vs Output Current, VOUT = 4.8 V Figure 6. TLV70018 Output Voltage vs Temperature Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: TLV700 7 TLV700 SLVSA00E – SEPTEMBER 2009 – REVISED APRIL 2015 www.ti.com Typical Characteristics (continued) Over operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(nom) + 0.5 V or 2 V, whichever is greater; IOUT = 10 mA, VEN = VIN, COUT = 1 μF, unless otherwise noted. Typical values are at TJ = 25°C. Ground Pin Current (mA) 45 300 IOUT = 0 mA 40 35 30 25 20 15 +125°C +85°C +25°C -40°C 10 5 Ground Pin Current (mA) 50 250 200 150 100 +125°C +85°C +25°C -40°C 50 0 0 2.1 2.6 3.1 3.6 4.1 4.6 5.1 0 5.6 20 40 60 2.0 35 1.8 Shutdown Current (mA) Ground Pin Current (mA) 40 30 25 20 15 10 5 1.6 1.4 1.2 1.0 0.8 0.6 +125°C +85°C +25°C 0.4 0.2 IOUT = 0 mA 0 0 -40 -25 -10 5 20 35 50 65 80 95 110 125 2.1 2.6 3.1 3.6 4.1 4.6 5.1 5.6 Temperature (°C) Input Voltage (V) Figure 9. TLV70018 Ground Pin Current vs Temperature Figure 10. TLV70018 Shutdown Current vs Input Voltage 100 80 IOUT = 10 mA 90 80 1 kHz 70 IOUT = 150 mA 60 PSRR (dB) 70 PSRR (dB) 100 120 140 160 180 200 Figure 8. TLV70018 Ground Pin Current vs Load Figure 7. TLV70018 Ground Pin Current vs Input Voltage 60 50 40 30 10 kHz 50 100 kHz 40 30 20 20 10 10 VIN - VOUT = 0.5 V 0 0 10 8 80 Output Current (mA) Input Voltage (V) 100 1k 10 k 100 k 1M 10 M 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 Frequency (Hz) Input Voltage (V) Figure 11. TLV70018 Power-Supply Ripple Rejection vs Frequency Figure 12. TLV70018 Power-Supply Ripple Rejection vs Input Voltage Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: TLV700 TLV700 www.ti.com SLVSA00E – SEPTEMBER 2009 – REVISED APRIL 2015 Typical Characteristics (continued) 10 100 mA/div tR = tF = 1 ms 1 200 mA IOUT 0 mA 0.1 50 mV/div Output Spectral Noise Density (mV/ÖHz) Over operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(nom) + 0.5 V or 2 V, whichever is greater; IOUT = 10 mA, VEN = VIN, COUT = 1 μF, unless otherwise noted. Typical values are at TJ = 25°C. 0.01 IOUT = 10 mA CIN = COUT = 1 mF VOUT VIN = 2.1 V 0 10 100 1k 10 k 100 k 1M 10 ms/div 10 M Frequency (Hz) Figure 14. TLV70018 Load Transient Response Figure 13. TLV70018 Output Spectral Noise Density vs Output Voltage tR = tF = 1 ms 0 mA IOUT 50 mA/div 10 mA IOUT VOUT 50 mA 0 mA 20 mV/div 5 mV/div 20 mA/div tR = tF = 1 ms VOUT VIN = 2.3 V VIN = 2.3 V 10 ms/div 10 ms/div Figure 15. TLV70018 Load Transient Response Figure 16. TLV70018 Load Transient Response 1 V/div VIN 2.9 V VIN Slew Rate = 1 V/ms 2.7 V 2.3 V VOUT IOUT = 200 mA 5 mV/div 2.3 V 5 mV/div 1 V/div Slew Rate = 1 V/ms VOUT IOUT = 1 mA 1 ms/div 1 ms/div Figure 17. TLV70018 Line Transient Response Figure 18. TLV70018 Line Transient Response Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: TLV700 9 TLV700 SLVSA00E – SEPTEMBER 2009 – REVISED APRIL 2015 www.ti.com Typical Characteristics (continued) Over operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(nom) + 0.5 V or 2 V, whichever is greater; IOUT = 10 mA, VEN = VIN, COUT = 1 μF, unless otherwise noted. Typical values are at TJ = 25°C. IOUT = 1 mA 1 V/div Slew Rate = 1 V/ms VIN 5.5 V 10 mV/div 1 V/div 2.1 V VIN VOUT IOUT = 200 mA VOUT 1 ms/div 200 ms/div Figure 19. TLV70018 Line Transient Response 10 Figure 20. TLV70018 VIN Ramp-Up, Ramp-Down Response Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: TLV700 TLV700 www.ti.com SLVSA00E – SEPTEMBER 2009 – REVISED APRIL 2015 7 Detailed Description 7.1 Overview The TLV700 series of LDO linear regulators are low quiescent current devices with excellent line and load transient performance. These LDOs are designed for power-sensitive applications. A precision bandgap and error amplifier provides overall 2% accuracy. Low output noise, very high PSRR, and low dropout voltage make this series of devices ideal for most battery-operated handheld equipment. All device versions have integrated thermal shutdown, current limit, and undervoltage lockout (UVLO). 7.2 Functional Block Diagram IN OUT Current Limit Thermal Shutdown UVLO EN Bandgap LOGIC TLV700xx Series GND 7.3 Feature Description 7.3.1 Internal Current Limit The TLV700 internal current limit helps to protect the regulator during fault conditions. During current limit, the output sources a fixed amount of current that is largely independent of the output voltage. In such a case, the output voltage is not regulated, and is VOUT = ICL × RLOAD. The PMOS pass transistor dissipates (VIN – VOUT) × ICL until thermal shutdown is triggered and the device turns off. As the device cools down, it is turned on by the internal thermal shutdown circuit. If the fault condition continues, the device cycles between current limit and thermal shutdown. See Thermal Protection for more details. The PMOS pass element in the TLV700 has a built-in body diode that conducts current when the voltage at OUT exceeds the voltage at IN. This current is not limited, so if extended reverse voltage operation is anticipated, external limiting to 5% of the rated output current is recommended. 7.3.2 Shutdown The enable pin (EN) is active high. The device is enabled when voltage at EN pin goes above 0.9 V. The device is turned off when the EN pin is held at less than 0.4 V. When shutdown capability is not required, EN can be connected to the IN pin. Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: TLV700 11 TLV700 SLVSA00E – SEPTEMBER 2009 – REVISED APRIL 2015 www.ti.com Feature Description (continued) 7.3.3 Dropout Voltage The TLV700 uses a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the dropout voltage (VDO), the PMOS pass device is in the linear region of operation and the input-to-output resistance is the RDS(on) of the PMOS pass element. VDO scales approximately with output current because the PMOS device behaves as a resistor in dropout. As with any linear regulator, PSRR and transient response are degraded as (VIN – VOUT) approaches dropout. This effect is shown in Figure 12 in Typical Characteristics. 7.3.4 Undervoltage Lockout (UVLO) The TLV700 uses a UVLO circuit to keep the output shut off until internal circuitry is operating properly. 7.4 Device Functional Modes 7.4.1 Normal Operation The device regulates to the nominal output voltage under the following conditions: • • • The input voltage is greater than the nominal output voltage added to the dropout voltage. The output current is less than the current limit. The input voltage is greater than the UVLO voltage. 7.4.2 Dropout Operation If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other conditions are met for normal operation, the device operates in dropout mode. In this condition, the output voltage is the same the input voltage minus the dropout voltage. The transient performance of the device is significantly degraded because the pass device is in a triode state and no longer regulates the output voltage of the LDO. Line or load transients in dropout may result in large output voltage deviations. Table 1 lists the conditions that lead to the different modes of operation. Table 1. Device Functional Mode Comparison OPERATING MODE 12 PARAMETER VIN IOUT Normal mode VIN > VOUT(nom) + VDO IOUT < ICL Dropout mode VIN < VOUT(nom) + VDO IOUT < ICL Current limit VIN > UVLO IOUT > ICL Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: TLV700 TLV700 www.ti.com SLVSA00E – SEPTEMBER 2009 – REVISED APRIL 2015 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The TLV700 belongs to a new family of next-generation value LDO regulators. These devices consume low quiescent current and deliver excellent line and load transient performance. These characteristics, combined with low noise, very good PSRR with little (VIN – VOUT) headroom, make this family of devices ideal for RF portable applications. This family of regulators offers current limit and thermal protection, and is specified from –40°C to +125°C. 8.2 Typical Application Figure 21 shows a typical application circuit. VIN IN OUT CIN COUT VOUT 1 mF Ceramic TLV700xx On Off EN GND Figure 21. Typical Application Circuit 8.2.1 Design Requirements Table 2 lists the design parameters. Table 2. Design Parameters PARAMETER DESIGN REQUIREMENT Input voltage 2.5 V to 3.3 V Output voltage 1.8 V Output current 100 mA 8.2.2 Detailed Design Procedure 8.2.2.1 Input and Output Capacitor Requirements TI recommends using 1-μF X5R- and X7R-type ceramic capacitors because these capacitors have minimal variation in value and equivalent series resistance (ESR) over temperature. However, the TLV700 is designed to be stable with an effective capacitance of 0.1 μF or larger at the output. Thus, the device is stable with capacitors of other dielectric types as well, as long as the effective capacitance under operating bias voltage and temperature is greater than 0.1 μF. This effective capacitance refers to the capacitance that the LDO sees under operating bias voltage and temperature conditions; that is, the capacitance after taking both bias voltage and temperature derating into consideration. In addition to allowing the use of cheaper dielectrics, this capability of being stable with 0.1-μF effective capacitance also enables the use of smaller footprint capacitors that have higher derating in size- and space-constrained applications. Using a 0.1-μF rated capacitor at the output of the LDO does not ensure stability because the effective capacitance under the specified operating conditions must not be less than 0.1 μF. Maximum ESR should be less than 200 mΩ. Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: TLV700 13 TLV700 SLVSA00E – SEPTEMBER 2009 – REVISED APRIL 2015 www.ti.com Although an input capacitor is not required for stability, it is good analog design practice to connect a 0.1-μF to 1μF, low ESR capacitor across the IN pin and GND in of the regulator. This capacitor counteracts reactive input sources and improves transient response, noise rejection, and ripple rejection. A higher-value capacitor may be necessary if large, fast rise-time load transients are anticipated, or if the device is not located close to the power source. If source impedance is more than 2 Ω, a 0.1-μF input capacitor may be necessary to ensure stability. 8.2.2.2 Transient Response As with any regulator, increasing the size of the output capacitor reduces overshoot and undershoot magnitude but increases the duration of the transient response. 8.2.3 Application Curves Slew Rate = 1 V/ms IOUT 50 mA 1 V/div 0 mA VIN 2.9 V 2.3 V 5 mV/div 20 mV/div 50 mA/div tR = tF = 1 ms VOUT VIN = 2.3 V VOUT IOUT = 200 mA 1 ms/div 10 ms/div Figure 22. TLV70018 Load Transient Response Figure 23. TLV70018 Line Transient Response 9 Power Supply Recommendations Connect a low output impedance power supply directly to the INPUT pin of the TLV700. Inductive impedances between the input supply and the INPUT pin can create significant voltage excursions at the INPUT pin during start-up or load transient events. 14 Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: TLV700 TLV700 www.ti.com SLVSA00E – SEPTEMBER 2009 – REVISED APRIL 2015 10 Layout 10.1 Layout Guidelines Input and output capacitors should be placed as close to the device pins as possible. To improve AC performance such as PSRR, output noise, and transient response, TI recommends designing the printed-circuitboards with separate ground planes for VIN and VOUT, with the ground plane connected only at the GND pin of the device. In addition, the ground connection for the output capacitor should be connected directly to the GND pin of the device. High ESR capacitors may degrade PSRR performance. 10.2 Layout Examples VOUT VIN OUT IN CIN COUT GND NC EN GND PLANE Represents via used for application specific connections Figure 24. Layout Example for the DCK and DDC Package VIN CIN IN EN GND NC OUT NC VOUT GND PLANE COUT Represents via used for application specific connections Figure 25. Layout Example for the DSE Package 10.3 Thermal Protection Thermal protection disables the output when the junction temperature rises to approximately 160°C, allowing the device to cool. When the junction temperature cools to approximately 140°C, the output circuitry is again enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage as a result of overheating. Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate heatsink. For reliable operation, junction temperature should be limited to 125°C maximum. To estimate the margin of safety in a complete design (including heatsink), increase the ambient temperature until the thermal protection is triggered; use worst-case loads and signal conditions. For good reliability, thermal protection should trigger at least 35°C above the maximum expected ambient condition of the particular application. This configuration produces a worst-case junction temperature of 125°C at the highest expected ambient temperature and worst-case load. Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: TLV700 15 TLV700 SLVSA00E – SEPTEMBER 2009 – REVISED APRIL 2015 www.ti.com Thermal Protection (continued) The internal protection circuitry of the TLV700 has been designed to protect against overload conditions. The protection circuitry was not intended to replace proper heatsinking. Continuously running the TLV700 into thermal shutdown degrades device reliability. 10.4 Power Dissipation The ability to remove heat from the die is different for each package type, presenting different considerations in the PCB layout. The PCB area around the device that is free of other components moves the heat from the device to the ambient air. Performance data for JEDEC low and high-K boards are given in Thermal Information. Using heavier copper increases the effectiveness in removing heat from the device. The addition of plated through-holes to heat-dissipating layers also improves heatsink effectiveness. Power dissipation depends on input voltage and load conditions. Power dissipation (PD) is equal to the product of the output current and the voltage drop across the output pass element, as shown in Equation 1. PD = (VIN - VOUT) ´ IOUT (1) 16 Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: TLV700 TLV700 www.ti.com SLVSA00E – SEPTEMBER 2009 – REVISED APRIL 2015 11 Device and Documentation Support 11.1 Device Support 11.1.1 Development Support 11.1.1.1 Evaluation Modules Three evaluation modules (EVMs) are available to assist in the initial circuit performance evaluation using the TLV700: • TLV70033EVM-503 • TLV70018EVM-503 • TLV70028EVM-463 These EVMs can be requested at the Texas Instruments website through the product folders or purchased directly from the TI eStore. 11.1.1.2 Spice Models Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of analog circuits and systems. A SPICE model for the TLV700 is available through the product folders under Tools & Software. 11.1.2 Device Nomenclature Table 3. Ordering Information (1) PRODUCT TLV700xx yyyz (1) (2) VOUT (2) XX is nominal output voltage (for example, 28 = 2.8 V). YYY is the package designator. Z is tape and reel quantity (R = 3000, T = 250). For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the device product folder at www.ti.com. Output voltages from 1.2 V to 4.8 V in 50-mV increments are available. Contact factory for details and availability. 11.2 Documentation Support 11.2.1 Related Documentation • Using the TLV700xxEVM-463 Evaluation Module, SLUU390 • Using the TLV700xxEVM-503 Evaluation Module, SLUU391 11.3 Trademarks Bluetooth is a registered trademark of Bluetooth SIG. ZigBee is a registered trademark of the ZigBee Alliance. All other trademarks are the property of their respective owners. 11.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: TLV700 17 TLV700 SLVSA00E – SEPTEMBER 2009 – REVISED APRIL 2015 www.ti.com 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 18 Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: TLV700 PACKAGE OPTION ADDENDUM www.ti.com 28-Feb-2017 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) TLV70012DCKR ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 ODT TLV70012DCKT ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 ODT TLV70012DDCR ACTIVE SOT-23-THIN DDC 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ODO TLV70012DDCT ACTIVE SOT-23-THIN DDC 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ODO TLV70012DSER ACTIVE WSON DSE 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 NH TLV70012DSET ACTIVE WSON DSE 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 NH TLV70013DDCR ACTIVE SOT-23-THIN DDC 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 SAH TLV70013DDCT ACTIVE SOT-23-THIN DDC 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 SAH TLV70015DCKR ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 ODU TLV70015DCKT ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 ODU TLV70015DDCR ACTIVE SOT-23-THIN DDC 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ODP TLV70015DDCT ACTIVE SOT-23-THIN DDC 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ODP TLV70015DSER ACTIVE WSON DSE 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 NJ TLV70015DSET ACTIVE WSON DSE 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 NJ TLV70018DCKR ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 ODV TLV70018DCKT ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 ODV TLV70018DDCR ACTIVE SOT-23-THIN DDC 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ODK Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 28-Feb-2017 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) TLV70018DDCT ACTIVE SOT-23-THIN DDC 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ODK TLV70018DSER ACTIVE WSON DSE 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 NK TLV70018DSET ACTIVE WSON DSE 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 NK TLV70019DDCR ACTIVE SOT-23-THIN DDC 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 SCJ TLV70019DDCT ACTIVE SOT-23-THIN DDC 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 SCJ TLV70022DDCR ACTIVE SOT-23-THIN DDC 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 SCI TLV70022DDCT ACTIVE SOT-23-THIN DDC 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 SCI TLV70025DCKR ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 QTP TLV70025DCKT ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 QTP TLV70025DDCR ACTIVE SOT-23-THIN DDC 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 DAU TLV70025DDCT ACTIVE SOT-23-THIN DDC 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 DAU TLV70025DSER ACTIVE WSON DSE 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 QY TLV70025DSET ACTIVE WSON DSE 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 QY TLV70028DCKR ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 ODW TLV70028DCKT ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 ODW TLV70028DDCR ACTIVE SOT-23-THIN DDC 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ODL TLV70028DDCT ACTIVE SOT-23-THIN DDC 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ODL TLV70028DSER ACTIVE WSON DSE 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 NL Addendum-Page 2 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 28-Feb-2017 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) TLV70028DSET ACTIVE WSON DSE 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 NL TLV70029DSER ACTIVE WSON DSE 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 QJ TLV70029DSET ACTIVE WSON DSE 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 QJ TLV70030DCKR ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 ODR TLV70030DCKT ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 ODR TLV70030DDCR ACTIVE SOT-23-THIN DDC 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ODM TLV70030DDCT ACTIVE SOT-23-THIN DDC 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ODM TLV70030DSER ACTIVE WSON DSE 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 NP TLV70030DSET ACTIVE WSON DSE 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 NP TLV70031DSER ACTIVE WSON DSE 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 C4 TLV70031DSET ACTIVE WSON DSE 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 C4 TLV70032DDCR ACTIVE SOT-23-THIN DDC 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 SCH TLV70032DDCT ACTIVE SOT-23-THIN DDC 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 SCH TLV70033DCKR ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 ODS TLV70033DCKT ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 ODS TLV70033DDCR ACTIVE SOT-23-THIN DDC 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ODN TLV70033DDCT ACTIVE SOT-23-THIN DDC 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ODN TLV70033DSER ACTIVE WSON DSE 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 NR Addendum-Page 3 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 28-Feb-2017 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) TLV70033DSET ACTIVE WSON DSE 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 NR TLV70036DDCR ACTIVE SOT-23-THIN DDC 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 SCG TLV70036DDCT ACTIVE SOT-23-THIN DDC 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 SCG TLV70036DSER ACTIVE WSON DSE 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 UG TLV70036DSET ACTIVE WSON DSE 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 UG (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 4 Samples PACKAGE OPTION ADDENDUM www.ti.com 28-Feb-2017 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TLV700 : • Automotive: TLV700-Q1 NOTE: Qualified Version Definitions: • Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 5 PACKAGE MATERIALS INFORMATION www.ti.com 8-May-2018 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TLV70012DCKR SC70 DCK 5 3000 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3 TLV70012DCKR SC70 DCK 5 3000 180.0 8.4 2.47 2.3 1.25 4.0 8.0 Q3 TLV70012DCKT SC70 DCK 5 250 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3 TLV70012DCKT SC70 DCK 5 250 180.0 8.4 2.47 2.3 1.25 4.0 8.0 Q3 TLV70012DDCR SOT23-THIN DDC 5 3000 180.0 8.4 3.1 3.05 1.1 4.0 8.0 Q3 TLV70012DDCR SOT23-THIN DDC 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 TLV70012DDCT SOT23-THIN DDC 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 TLV70012DDCT SOT23-THIN DDC 5 250 180.0 8.4 3.1 3.05 1.1 4.0 8.0 Q3 TLV70012DSER WSON DSE 6 3000 180.0 8.4 1.83 1.83 0.89 4.0 8.0 Q2 TLV70012DSET WSON DSE 6 250 180.0 8.4 1.83 1.83 0.89 4.0 8.0 Q2 TLV70013DDCR SOT23-THIN DDC 5 3000 180.0 8.4 3.1 3.05 1.1 4.0 8.0 Q3 TLV70013DDCT SOT23-THIN DDC 5 250 180.0 8.4 3.1 3.05 1.1 4.0 8.0 Q3 TLV70015DCKR SC70 DCK 5 3000 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3 TLV70015DCKR SC70 DCK 5 3000 180.0 8.4 2.47 2.3 1.25 4.0 8.0 Q3 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 8-May-2018 Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TLV70015DCKT SC70 DCK 5 250 180.0 8.4 2.47 2.3 1.25 4.0 8.0 Q3 TLV70015DCKT SC70 DCK 5 250 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3 TLV70015DDCR SOT23-THIN DDC 5 3000 180.0 8.4 3.1 3.05 1.1 4.0 8.0 Q3 TLV70015DDCR SOT23-THIN DDC 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 TLV70015DDCT SOT23-THIN DDC 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 TLV70015DDCT SOT23-THIN DDC 5 250 180.0 8.4 3.1 3.05 1.1 4.0 8.0 Q3 TLV70015DSER WSON DSE 6 3000 180.0 8.4 1.83 1.83 0.89 4.0 8.0 Q2 TLV70015DSET WSON DSE 6 250 180.0 8.4 1.83 1.83 0.89 4.0 8.0 Q2 TLV70018DCKR SC70 DCK 5 3000 179.0 8.4 2.2 2.5 1.2 4.0 8.0 Q3 TLV70018DCKR SC70 DCK 5 3000 180.0 8.4 2.47 2.3 1.25 4.0 8.0 Q3 TLV70018DCKR SC70 DCK 5 3000 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3 TLV70018DCKT SC70 DCK 5 250 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3 TLV70018DCKT SC70 DCK 5 250 179.0 8.4 2.2 2.5 1.2 4.0 8.0 Q3 TLV70018DCKT SC70 DCK 5 250 180.0 8.4 2.47 2.3 1.25 4.0 8.0 Q3 TLV70018DDCR SOT23-THIN DDC 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 TLV70018DDCR SOT23-THIN DDC 5 3000 180.0 8.4 3.1 3.05 1.1 4.0 8.0 Q3 TLV70018DDCT SOT23-THIN DDC 5 250 180.0 8.4 3.1 3.05 1.1 4.0 8.0 Q3 TLV70018DDCT SOT23-THIN DDC 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 TLV70018DSER WSON DSE 6 3000 180.0 8.4 1.83 1.83 0.89 4.0 8.0 Q2 TLV70018DSER WSON DSE 6 3000 179.0 8.4 1.8 1.8 1.0 4.0 8.0 Q2 TLV70018DSET WSON DSE 6 250 180.0 8.4 1.83 1.83 0.89 4.0 8.0 Q2 TLV70019DDCR SOT23-THIN DDC 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 TLV70019DDCT SOT23-THIN DDC 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 TLV70022DDCR SOT23-THIN DDC 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 TLV70022DDCT SOT23-THIN DDC 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 TLV70025DCKR SC70 DCK 5 3000 179.0 8.4 2.2 2.5 1.2 4.0 8.0 Q3 TLV70025DCKR SC70 DCK 5 3000 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3 TLV70025DCKT SC70 DCK 5 250 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3 TLV70025DCKT SC70 DCK 5 250 179.0 8.4 2.2 2.5 1.2 4.0 8.0 Q3 TLV70025DDCR SOT23-THIN DDC 5 3000 180.0 8.4 3.1 3.05 1.1 4.0 8.0 Q3 TLV70025DDCR SOT23-THIN DDC 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 TLV70025DDCT SOT23-THIN DDC 5 250 180.0 8.4 3.1 3.05 1.1 4.0 8.0 Q3 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 8-May-2018 Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) TLV70025DDCT SOT23-THIN DDC 5 250 179.0 8.4 TLV70025DSER WSON DSE 6 3000 179.0 8.4 1.8 TLV70025DSER WSON DSE 6 3000 180.0 8.4 1.83 TLV70025DSET WSON DSE 6 250 179.0 8.4 1.8 3.2 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3.2 1.4 4.0 8.0 Q3 1.8 1.0 4.0 8.0 Q2 1.83 0.89 4.0 8.0 Q2 1.8 1.0 4.0 8.0 Q2 TLV70025DSET WSON DSE 6 250 180.0 8.4 1.83 1.83 0.89 4.0 8.0 Q2 TLV70028DCKR SC70 DCK 5 3000 180.0 8.4 2.47 2.3 1.25 4.0 8.0 Q3 TLV70028DCKR SC70 DCK 5 3000 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3 TLV70028DCKT SC70 DCK 5 250 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3 TLV70028DCKT SC70 DCK 5 250 180.0 8.4 2.47 2.3 1.25 4.0 8.0 Q3 TLV70028DDCR SOT23-THIN DDC 5 3000 180.0 8.4 3.1 3.05 1.1 4.0 8.0 Q3 TLV70028DDCR SOT23-THIN DDC 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 TLV70028DDCT SOT23-THIN DDC 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 TLV70028DDCT SOT23-THIN DDC 5 250 180.0 8.4 3.1 3.05 1.1 4.0 8.0 Q3 TLV70028DSER WSON DSE 6 3000 180.0 8.4 1.83 1.83 0.89 4.0 8.0 Q2 TLV70028DSER WSON DSE 6 3000 178.0 8.4 1.7 1.7 0.95 4.0 8.0 Q2 TLV70028DSET WSON DSE 6 250 178.0 8.4 1.7 1.7 0.95 4.0 8.0 Q2 TLV70028DSET WSON DSE 6 250 180.0 8.4 1.83 1.83 0.89 4.0 8.0 Q2 TLV70029DSER WSON DSE 6 3000 180.0 8.4 1.83 1.83 0.89 4.0 8.0 Q2 TLV70029DSET WSON DSE 6 250 180.0 8.4 1.83 1.83 0.89 4.0 8.0 Q2 TLV70030DCKR SC70 DCK 5 3000 180.0 8.4 2.47 2.3 1.25 4.0 8.0 Q3 TLV70030DCKR SC70 DCK 5 3000 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3 TLV70030DCKR SC70 DCK 5 3000 179.0 8.4 2.2 2.5 1.2 4.0 8.0 Q3 TLV70030DCKT SC70 DCK 5 250 180.0 8.4 2.47 2.3 1.25 4.0 8.0 Q3 TLV70030DCKT SC70 DCK 5 250 179.0 8.4 2.2 2.5 1.2 4.0 8.0 Q3 TLV70030DCKT SC70 DCK 5 250 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3 TLV70030DDCR SOT23-THIN DDC 5 3000 180.0 8.4 3.1 3.05 1.1 4.0 8.0 Q3 TLV70030DDCR SOT23-THIN DDC 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 TLV70030DDCT SOT23-THIN DDC 5 250 180.0 8.4 3.1 3.05 1.1 4.0 8.0 Q3 TLV70030DDCT SOT23-THIN DDC 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 TLV70030DSER WSON DSE 6 3000 180.0 8.4 1.83 1.83 0.89 4.0 8.0 Q2 TLV70030DSET WSON DSE 6 250 180.0 8.4 1.83 1.83 0.89 4.0 8.0 Q2 TLV70031DSER WSON DSE 6 3000 180.0 8.4 1.83 1.83 0.89 4.0 8.0 Q2 TLV70031DSET WSON DSE 6 250 180.0 8.4 1.83 1.83 0.89 4.0 8.0 Q2 TLV70032DDCR SOT23-THIN DDC 5 3000 180.0 8.4 3.1 3.05 1.1 4.0 8.0 Q3 TLV70032DDCT SOT23-THIN DDC 5 250 180.0 8.4 3.1 3.05 1.1 4.0 8.0 Q3 Pack Materials-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 8-May-2018 Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TLV70033DCKR SC70 DCK 5 3000 180.0 8.4 2.47 2.3 1.25 4.0 8.0 Q3 TLV70033DCKR SC70 DCK 5 3000 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3 TLV70033DCKT SC70 DCK 5 250 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3 TLV70033DCKT SC70 DCK 5 250 180.0 8.4 2.47 2.3 1.25 4.0 8.0 Q3 TLV70033DDCR SOT23-THIN DDC 5 3000 180.0 8.4 3.1 3.05 1.1 4.0 8.0 Q3 TLV70033DDCR SOT23-THIN DDC 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 TLV70033DDCT SOT23-THIN DDC 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 TLV70033DDCT SOT23-THIN DDC 5 250 180.0 8.4 3.1 3.05 1.1 4.0 8.0 Q3 TLV70033DSER WSON DSE 6 3000 180.0 8.4 1.83 1.83 0.89 4.0 8.0 Q2 TLV70033DSER WSON DSE 6 3000 178.0 8.4 1.7 1.7 0.95 4.0 8.0 Q2 TLV70033DSET WSON DSE 6 250 180.0 8.4 1.83 1.83 0.89 4.0 8.0 Q2 TLV70033DSET WSON DSE 6 250 178.0 8.4 1.7 1.7 0.95 4.0 8.0 Q2 TLV70036DDCR SOT23-THIN DDC 5 3000 180.0 8.4 3.1 3.05 1.1 4.0 8.0 Q3 TLV70036DDCT SOT23-THIN DDC 5 250 180.0 8.4 3.1 3.05 1.1 4.0 8.0 Q3 TLV70036DSER WSON DSE 6 3000 180.0 8.4 1.83 1.83 0.89 4.0 8.0 Q2 TLV70036DSET WSON DSE 6 250 180.0 8.4 1.83 1.83 0.89 4.0 8.0 Q2 Pack Materials-Page 4 PACKAGE MATERIALS INFORMATION www.ti.com 8-May-2018 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV70012DCKR SC70 DCK 5 3000 180.0 180.0 18.0 TLV70012DCKR SC70 DCK 5 3000 183.0 183.0 20.0 TLV70012DCKT SC70 DCK 5 250 180.0 180.0 18.0 TLV70012DCKT SC70 DCK 5 250 183.0 183.0 20.0 TLV70012DDCR SOT-23-THIN DDC 5 3000 406.0 348.0 63.0 TLV70012DDCR SOT-23-THIN DDC 5 3000 195.0 200.0 45.0 TLV70012DDCT SOT-23-THIN DDC 5 250 195.0 200.0 45.0 TLV70012DDCT SOT-23-THIN DDC 5 250 202.0 201.0 28.0 TLV70012DSER WSON DSE 6 3000 183.0 183.0 20.0 TLV70012DSET WSON DSE 6 250 183.0 183.0 20.0 TLV70013DDCR SOT-23-THIN DDC 5 3000 202.0 201.0 28.0 TLV70013DDCT SOT-23-THIN DDC 5 250 213.0 191.0 35.0 TLV70015DCKR SC70 DCK 5 3000 180.0 180.0 18.0 TLV70015DCKR SC70 DCK 5 3000 183.0 183.0 20.0 TLV70015DCKT SC70 DCK 5 250 183.0 183.0 20.0 TLV70015DCKT SC70 DCK 5 250 180.0 180.0 18.0 TLV70015DDCR SOT-23-THIN DDC 5 3000 213.0 191.0 35.0 TLV70015DDCR SOT-23-THIN DDC 5 3000 195.0 200.0 45.0 TLV70015DDCT SOT-23-THIN DDC 5 250 195.0 200.0 45.0 TLV70015DDCT SOT-23-THIN DDC 5 250 213.0 191.0 35.0 TLV70015DSER WSON DSE 6 3000 183.0 183.0 20.0 TLV70015DSET WSON DSE 6 250 183.0 183.0 20.0 TLV70018DCKR SC70 DCK 5 3000 203.0 203.0 35.0 TLV70018DCKR SC70 DCK 5 3000 183.0 183.0 20.0 TLV70018DCKR SC70 DCK 5 3000 180.0 180.0 18.0 TLV70018DCKT SC70 DCK 5 250 180.0 180.0 18.0 TLV70018DCKT SC70 DCK 5 250 203.0 203.0 35.0 TLV70018DCKT SC70 DCK 5 250 183.0 183.0 20.0 TLV70018DDCR SOT-23-THIN DDC 5 3000 195.0 200.0 45.0 TLV70018DDCR SOT-23-THIN DDC 5 3000 213.0 191.0 35.0 TLV70018DDCT SOT-23-THIN DDC 5 250 213.0 191.0 35.0 TLV70018DDCT SOT-23-THIN DDC 5 250 195.0 200.0 45.0 TLV70018DSER WSON DSE 6 3000 183.0 183.0 20.0 TLV70018DSER WSON DSE 6 3000 203.0 203.0 35.0 TLV70018DSET WSON DSE 6 250 183.0 183.0 20.0 TLV70019DDCR SOT-23-THIN DDC 5 3000 195.0 200.0 45.0 TLV70019DDCT SOT-23-THIN DDC 5 250 195.0 200.0 45.0 TLV70022DDCR SOT-23-THIN DDC 5 3000 195.0 200.0 45.0 TLV70022DDCT SOT-23-THIN DDC 5 250 195.0 200.0 45.0 TLV70025DCKR SC70 DCK 5 3000 203.0 203.0 35.0 TLV70025DCKR SC70 DCK 5 3000 180.0 180.0 18.0 TLV70025DCKT SC70 DCK 5 250 180.0 180.0 18.0 Pack Materials-Page 5 PACKAGE MATERIALS INFORMATION www.ti.com 8-May-2018 Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV70025DCKT SC70 DCK 5 250 203.0 203.0 35.0 TLV70025DDCR SOT-23-THIN DDC 5 3000 213.0 191.0 35.0 TLV70025DDCR SOT-23-THIN DDC 5 3000 195.0 200.0 45.0 TLV70025DDCT SOT-23-THIN DDC 5 250 213.0 191.0 35.0 TLV70025DDCT SOT-23-THIN DDC 5 250 195.0 200.0 45.0 TLV70025DSER WSON DSE 6 3000 203.0 203.0 35.0 TLV70025DSER WSON DSE 6 3000 183.0 183.0 20.0 TLV70025DSET WSON DSE 6 250 203.0 203.0 35.0 TLV70025DSET WSON DSE 6 250 183.0 183.0 20.0 TLV70028DCKR SC70 DCK 5 3000 183.0 183.0 20.0 TLV70028DCKR SC70 DCK 5 3000 180.0 180.0 18.0 TLV70028DCKT SC70 DCK 5 250 180.0 180.0 18.0 TLV70028DCKT SC70 DCK 5 250 183.0 183.0 20.0 TLV70028DDCR SOT-23-THIN DDC 5 3000 213.0 191.0 35.0 TLV70028DDCR SOT-23-THIN DDC 5 3000 195.0 200.0 45.0 TLV70028DDCT SOT-23-THIN DDC 5 250 195.0 200.0 45.0 TLV70028DDCT SOT-23-THIN DDC 5 250 213.0 191.0 35.0 TLV70028DSER WSON DSE 6 3000 183.0 183.0 20.0 TLV70028DSER WSON DSE 6 3000 205.0 200.0 33.0 TLV70028DSET WSON DSE 6 250 205.0 200.0 33.0 TLV70028DSET WSON DSE 6 250 183.0 183.0 20.0 TLV70029DSER WSON DSE 6 3000 183.0 183.0 20.0 TLV70029DSET WSON DSE 6 250 183.0 183.0 20.0 TLV70030DCKR SC70 DCK 5 3000 183.0 183.0 20.0 TLV70030DCKR SC70 DCK 5 3000 180.0 180.0 18.0 TLV70030DCKR SC70 DCK 5 3000 203.0 203.0 35.0 TLV70030DCKT SC70 DCK 5 250 183.0 183.0 20.0 TLV70030DCKT SC70 DCK 5 250 203.0 203.0 35.0 TLV70030DCKT SC70 DCK 5 250 180.0 180.0 18.0 TLV70030DDCR SOT-23-THIN DDC 5 3000 213.0 191.0 35.0 TLV70030DDCR SOT-23-THIN DDC 5 3000 195.0 200.0 45.0 TLV70030DDCT SOT-23-THIN DDC 5 250 213.0 191.0 35.0 TLV70030DDCT SOT-23-THIN DDC 5 250 195.0 200.0 45.0 TLV70030DSER WSON DSE 6 3000 183.0 183.0 20.0 TLV70030DSET WSON DSE 6 250 183.0 183.0 20.0 TLV70031DSER WSON DSE 6 3000 183.0 183.0 20.0 TLV70031DSET WSON DSE 6 250 183.0 183.0 20.0 TLV70032DDCR SOT-23-THIN DDC 5 3000 202.0 201.0 28.0 TLV70032DDCT SOT-23-THIN DDC 5 250 213.0 191.0 35.0 TLV70033DCKR SC70 DCK 5 3000 183.0 183.0 20.0 TLV70033DCKR SC70 DCK 5 3000 180.0 180.0 18.0 TLV70033DCKT SC70 DCK 5 250 180.0 180.0 18.0 TLV70033DCKT SC70 DCK 5 250 183.0 183.0 20.0 TLV70033DDCR SOT-23-THIN DDC 5 3000 213.0 191.0 35.0 Pack Materials-Page 6 PACKAGE MATERIALS INFORMATION www.ti.com 8-May-2018 Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV70033DDCR SOT-23-THIN DDC 5 3000 195.0 200.0 45.0 TLV70033DDCT SOT-23-THIN DDC 5 250 195.0 200.0 45.0 TLV70033DDCT SOT-23-THIN DDC 5 250 213.0 191.0 35.0 TLV70033DSER WSON DSE 6 3000 183.0 183.0 20.0 TLV70033DSER WSON DSE 6 3000 205.0 200.0 33.0 TLV70033DSET WSON DSE 6 250 183.0 183.0 20.0 TLV70033DSET WSON DSE 6 250 205.0 200.0 33.0 TLV70036DDCR SOT-23-THIN DDC 5 3000 202.0 201.0 28.0 TLV70036DDCT SOT-23-THIN DDC 5 250 213.0 191.0 35.0 TLV70036DSER WSON DSE 6 3000 183.0 183.0 20.0 TLV70036DSET WSON DSE 6 250 183.0 183.0 20.0 Pack Materials-Page 7 IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF 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