TLV704
SBVS148F – SEPTEMBER 2010 – REVISED MARCH 2023
TLV704 24-V, 150-mA, 3.2-μA Quiescent Current, Low-Dropout Linear Regulator
1 Features
3 Description
•
The TLV704 low-dropout (LDO) linear voltage
regulator is a low quiescent current device that
offers the benefits of a wide input voltage range
and low-power operation in miniaturized packaging.
Thus, the TLV704 is designed for battery-powered
applications and as a power-management attachment
to low-power microcontrollers.
2 Applications
Home and building automation
Retail automation and payment
Grid infrastructure
Medical applications
Lighting applications
The TLV704 is available in a 2.90-mm × 1.60-mm
SOT23-5 package, which is useful for cost-effective
board manufacturing.
Package Information
PART NUMBER
TLV704
(1)
PACKAGE(1)
BODY SIZE (nom)
DBV (SOT-23, 5)
2.90 mm × 1.60 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
4.5
TLV70433
4
IN
3.5
12V
3
Li-Ion
Battery
Ground Current (A)
•
•
•
•
•
The TLV704 LDO supports a low dropout of typically
850 mV at 100 mA of load current. The low quiescent
current (3.4 μA typically) is stable over the entire
range of output load current (0 mA to 150 mA). The
TLV704 also features an internal soft-start to lower the
inrush current. The built-in overcurrent limit protection
helps protect the regulator in the event of a load short
or fault.
2.5
2
VOUT = 3.3V
CIN
MCU
•
•
•
•
•
•
OUT
GND
COUT
0.1µF
•
Input voltage range:
– 2.5 V to 24 V (30 V max for new chip only)
Available output voltage options:
– Fixed: 1.8 V to 5 V
Output current: Up to 150 mA
Very low IQ: 3.4 μA at 100-mA load current
Stable with output capacitor ≥ 0.47 μF
Overcurrent protection
Package: 5-pin SOT-23 (DBV)
Operating junction temperature: –40°C to +125°C
1µF
Typical Application
1.5
1
-55°C
-40°C
0.5
0°C
25°C
85°C
125°C
150°C
0
0
30
60
90
Output Current (mA)
120
150
Figure 3-1. Quiescent Current vs Load Current for
TLV704xx (New Chip Only)
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLV704
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SBVS148F – SEPTEMBER 2010 – REVISED MARCH 2023
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................5
Thermal Information..........................................................5
6.4 Electrical Characteristics.............................................6
6.5 Typical Characteristics................................................ 7
7 Detailed Description......................................................12
7.1 Overview................................................................... 12
7.2 Functional Block Diagram......................................... 12
7.3 Feature Description...................................................12
7.4 Device Functional Modes..........................................14
8 Application and Implementation.................................. 15
8.1 Application Information............................................. 15
8.2 Typical Application.................................................... 15
8.3 Best Design Practices...............................................19
8.4 Power Supply Recommendations.............................20
8.5 Layout....................................................................... 20
9 Device and Documentation Support............................21
9.1 Device Support......................................................... 21
9.2 Documentation Support............................................ 21
9.3 Receiving Notification of Documentation Updates....21
9.4 Support Resources................................................... 21
9.5 Trademarks............................................................... 21
9.6 Electrostatic Discharge Caution................................21
9.7 Glossary....................................................................21
10 Mechanical, Packaging, and Orderable
Information.................................................................... 22
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (December 2022) to Revision F (March 2023)
Page
• Changed fixed output options to show the range of options instead of each individually in Features section... 1
• Corrected the abs max rating of VOUT pin for legacy chip ................................................................................ 4
• Corrected the operating max range of VOUT pin................................................................................................ 5
• Corrected the supported output current range from 50 mA to 150 mA..............................................................5
• Changed Application Curves section................................................................................................................18
Changes from Revision D (January 2015) to Revision E (December 2022)
Page
• Changed document title, Features, Applications, and Description sections and added M3 device information
to document........................................................................................................................................................ 1
• Changed Pin Configuration and Functions section.............................................................................................3
• Added new chip specific curves to Typical Characteristics section.................................................................... 7
• Changed Overview section...............................................................................................................................12
• Changed Functional Block Diagram image...................................................................................................... 12
• Changed Feature Description section.............................................................................................................. 12
• Deleted thermal shutdown discussion from Current Limit section.................................................................... 13
• Changed Normal Operation section................................................................................................................. 14
• Changed Dropout Operation section................................................................................................................ 14
• Changed Application Information section......................................................................................................... 15
• Added External Capacitor Requirements, Reverse Current, and Power Dissipation sub-sections to Detailed
Design Procedure section.................................................................................................................................15
• Changed Input and Output Capacitor Requirements section........................................................................... 15
• Added Reverse Current section........................................................................................................................16
• Changed Estimating Junction Temperature section......................................................................................... 17
• Added Best Design Practices section...............................................................................................................19
• Changed Power Supply Recommendations section.........................................................................................20
• Changed Layout Guidelines section................................................................................................................. 20
• Changed Power Dissipation section: changed title and deleted last sentence from section............................ 20
• Added M3 row to Available Options table.........................................................................................................21
2
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SBVS148F – SEPTEMBER 2010 – REVISED MARCH 2023
5 Pin Configuration and Functions
NC
GND
IN
TLV704
OUT
NC
Figure 5-1. DBV Package, 5-Pin SOT-23 (Top View)
Table 5-1. Pin Functions
PIN
NAME
DBV
TYPE
DESCRIPTION
GND
1
—
IN
2
I
Input supply pin. A capacitor with a value of 0.1 µF or larger is recommended from this pin
to ground. See the Input and Output Capacitor Requirements section for more information.
OUT
3
O
Output of the regulator. A capacitor with a value of 1 µF or larger is required from this pin to
ground.(1) See the Input and Output Capacitor Requirements section for more information.
4, 5
—
Not internally connected. This pin can be left open or tied to ground for improved thermal
performance.
NC
(1)
Ground pin.
The nominal output capacitance must be greater than 0.47 µF. Throughout this document, the nominal derating on these capacitors is
50%. Make sure that the effective capacitance at the pin is greater than 0.47 µF.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating temperature range (unless otherwise noted)(1) (2)
MIN
MAX
VIN (for legacy chip only)
–0.3
24
VIN (for new chip only)
–0.3
30
VOUT (for legacy chip only)
–0.3
5.0
V
Voltage
VOUT (for fixed output new chip only)
2 × VOUT(typ)
or VIN + 0.3
–0.3
or 5.5
(whichever is
lower)
V
Current
Peak output current
Voltage
Voltage
Temperature
(1)
(2)
UNIT
V
Internally limited
Junction, TJ
–40
150
Storage, Tstg
–65
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
All voltage values are with respect to network ground terminal.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
4
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
±2000
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)
MIN
VIN
Input supply voltage
VOUT
NOM
MAX
2.5
24
Output voltage
1.205
5
IOUT
Output current
0
150
CIN
Input capacitor(2)
0
0.047
Output capacitor (for legacy chip only)
0.47
1
Output capacitor (for new chip only) (3)
1
COUT
TJ
(1)
(2)
(3)
Operating junction temperature
-40
UNIT
V
V
mA
µF
125
°C
All voltages are with respect to GND.
An input capacitor is not required for LDO stability. However, an input capacitor with an effective value of 0.047 μF is
recommended to counteract the effect of source resistance and inductance, which may in some cases cause symptoms of system
level instability such as ringing or oscillation, especially in the presence of load transients.
All capacitor values are assumed to derate to 50% of the nominal capacitor value. Maintain an effective output capacitance of 0.47 μF
minimum for the stability.
Thermal Information
THERMAL METRIC(1)
Legacy Chip
New Chip
DBV (SOT-23)
DBV (SOT-23)
UNIT
5 PINS
5 PINS
RθJA
Junction-to-ambient thermal resistance
213.1
170.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
110.9
68.7
°C/W
RθJB
Junction-to-board thermal resistance
97.4
76.7
°C/W
ψJT
Junction-to-top characterization parameter
22.0
10.3
°C/W
ψJB
Junction-to-board characterization parameter
78.4
76.3
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application
report.
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SBVS148F – SEPTEMBER 2010 – REVISED MARCH 2023
6.4 Electrical Characteristics
over operating junction temperature range (TJ = –40°C to 125°C), VIN = VOUT(nom) + 1 V, IOUT = 1 mA, and COUT = 1 μF
(unless otherwise noted); typical values are at TJ = 25°C
PARAMETER
TEST CONDITIONS
Input voltage range (1)
VIN
(1)
TYP
MAX
24
UNIT
V
VOUT
Output voltage range
TJ = 25°C
1.2
5
V
VOUT
DC output accuracy(1)
TJ = 25°C
–2
2
%
Ground pin current (legacy
chip) (2)
IOUT = 0 mA, TJ = 25°C
3.2
4.5
IOUT = 100 mA, TJ = 25°C
3.2
5.5
Ground pin current (new chip)
IOUT = 0 mA, TJ = 25°C
3.2
4.1
4.5
IGND
(2)
ΔVOUT (ΔIOUT)
Load regulation
ΔVOUT (ΔVIN)
Line regulation (1)
ICL
Output current limit (legacy
chip)
IOUT = 100 mA, TJ = 25°C
3.4
VOUT < 3.3V, 0 < IOUT < 10 mA , TJ =
25°C
10
VOUT < 3.3V, 0 < IOUT < 50 mA , TJ =
25°C
25
VOUT < 3.3V, 0 < IOUT < 100 mA , TJ
= 25°C
33
VOUT ≥ 3.3 V, 0 < IOUT < 10 mA , TJ =
25°C
7
VOUT ≥ 3.3 V, 0 < IOUT < 50 mA , TJ =
25°C
35
VOUT ≥ 3.3 V, 0 < IOUT < 100 mA , TJ
= 25°C
50
75
VOUT(NOM) + 1 V ≤ VIN ≤ 24 V , TJ =
25°C
20
50
VOUT = 0 V , TJ = 25°C
Output current limit (new chip)
PSRR
VDO
TJ
(1)
(2)
6
MIN
TJ = 25°C
Power-supply ripple rejection
Dropout voltage
50
mV
160
1000
160
500
f = 100 kHz, COUT = 10 μF
60
VIN = VOUT(nom) – 0.1 V, IOUT = 10
mA , TJ = 25°C
75
VIN = VOUT(nom) – 0.1 V, IOUT = 50
mA , TJ = 25°C
400
VIN = VOUT(nom) – 0.1 V, IOUT = 100
mA , TJ = 25°C
850
Operating junction
temperature
μA
–40
mV
mA
dB
mV
1100
125
℃
Minimum VIN = VOUT + VDO or the value shown for Input voltage in this table, whichever is greater.
This device employs a leakage null control circuit. This circuit is active only if output current is less than pass transistor leakage
current. The circuit is typically active when output load is less than 5 μA, VIN is greater than 18 V, and die temperature is greater than
100°C.
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6.5 Typical Characteristics
at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 1.0 V or 2.5 V (whichever is greater), IOUT = 1 mA, CIN = 1 µF, and
COUT = 1 µF (unless otherwise noted)
3.4
3.4
VOUT = 3.3 V
IOUT = 5 mA
3.36
3.36
3.34
3.34
3.32
3.3
3.28
3.26
-40°C
+25°C
+85°C
3.24
3.22
8
12
16
20
3.32
3.3
3.28
3.26
3.24
4
3.6
3.6
3.5
3.5
3.4
3.3
3.2
0
30
150
Figure 6-3. Load Regulation (VOUT = 3.3 V) for Legacy Chip
3.432
24
-55°C
-40°C
30
0°C
25°C
85°C
125°C
60
90
Output Current (mA)
150°C
120
150
Figure 6-4. Load Regulation (VOUT = 3.3 V) for New Chip
3.465
VIN = 4.3 V
3.432
1mA
80mA
VIN = 4.3V
3.399
3.399
3.366
3.333
Output Voltage (V)
Output Voltage (V)
20
VOUT = 3.3V
VIN = 4.3V
0
Output Current (mA)
3.465
12
16
Input Voltage (V)
3.2
3
120
8
3.3
3.1
90
150°C
3.4
-40°C
+25°C
+85°C
60
85°C
125°C
Figure 6-2. Line Regulation for New Chip
Output Voltage (V)
Output Voltage (V)
Figure 6-1. Line Regulation for Legacy Chip
3
0°C
25°C
3.2
24
Input Voltage (V)
3.1
-55°C
-40°C
3.22
3.2
4
VOUT = 3.3V
IOUT = 5mA
3.38
Output Voltage (V)
Output Voltage (V)
3.38
IOUT = 10 mA
3.3
3.267
3.234
IOUT = 80 mA
3.201
3.366
3.333
3.3
3.267
3.234
3.201
3.168
3.168
3.135
-40 -25 -10
5
20
35
50
65
80
95
110 125
Junction Temperature (°C)
Figure 6-5. Output Voltage vs Junction Temperature for
Legacy Chip
3.135
-55
-25
5
35
65
95
Junction Temperature (C)
125
150
Figure 6-6. Output Voltage vs Junction Temperature for
New Chip
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6.5 Typical Characteristics (continued)
at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 1.0 V or 2.5 V (whichever is greater), IOUT = 1 mA, CIN = 1 µF, and
COUT = 1 µF (unless otherwise noted)
120
120
IOUT = 10mA
IOUT = 10 mA
100
Dropout Voltage ( mV)
Dropout Voltage (mV)
100
80
60
40
-40°C
+25°C
+85°C
20
2.6
2.7
2.8
2.9
3
3.1
3.2
40
Figure 6-7. Dropout Voltage vs Input Voltage (TLV70433) for
Legacy Chip
1800
1800
900
600
-40°C
+25°C
+85°C
300
Dropout Voltage (mV)
2100
1200
30
60
90
120
3.2
3.3
0°C
25°C
85°C
125°C
150°C
1200
900
600
30
60
90
Output Current (mA)
120
150
Figure 6-10. Dropout Voltage vs Output Current for New Chip
4.5
4
Ground Current (A)
Ground Current (mA)
-55°C
-40°C
0
VIN = 4.3 V
VOUT = 3.3 V
IOUT = 1 mF
3.5
3
2.5
VIN = 4.3V
VOUT = 3.3V
COUT = 1F
3.5
3
2.5
2
-40 -25 -10
5
20
35
50
65
80
95
110 125
Junction Temperature (°C)
Figure 6-11. Ground Current vs Junction Temperature for
Legacy Chip
8
3.1
0
150
4.5
4
2.8
2.9
3
Input Voltage (V)
150°C
1500
Output Current (mA)
Figure 6-9. Dropout Voltage vs Output Current for Legacy Chip
2.7
85°C
125°C
300
0
0
2.6
0°C
25°C
Figure 6-8. Dropout Voltage vs Input Voltage (TLV70433) for
New Chip
2100
1500
-55°C
-40°C
0
2.5
3.3
Input Voltage (V)
Dropout Voltage (mV)
60
20
0
2.5
80
2
-55
-25
5
35
65
95
Junction Temperature (C)
125
150
Figure 6-12. Ground Current vs Junction Temperature for
New Chip
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6.5 Typical Characteristics (continued)
at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 1.0 V or 2.5 V (whichever is greater), IOUT = 1 mA, CIN = 1 µF, and
COUT = 1 µF (unless otherwise noted)
4.5
4.5
VOUT = 3.3 V
4
3.5
3.5
Ground Current (A)
Ground Pin Current (mA)
4
3
2.5
2
1.5
1
-40°C
+25°C
+85°C
0.5
6
9
12
15
18
21
2
3
150°C
6
9
12
15
Input Voltage (V)
18
21
24
Figure 6-14. Ground Pin Current vs Input Voltage for New Chip
VOUT = 3.3 V
4
4
3.5
3.5
Ground Current (A)
Ground Pin Current (mA)
85°C
125°C
4.5
4.5
3
2.5
2
1.5
1
-40°C
+25°C
+85°C
0.5
0
30
60
90
120
3
2.5
2
1.5
1
-55°C
-40°C
0°C
25°C
85°C
125°C
150°C
0
150
0
Output Current (mA)
Figure 6-15. Ground Pin Current vs Load Current for
Legacy Chip
VOUT = 3.3V
0.5
0
30
60
90
Output Current (mA)
120
150
Figure 6-16. Ground Pin Current vs Load Current for New Chip
300
VOUT = 3.3 V, VIN = 4.8 V
-40°C
+25°C
250
+85°C
Current Limit (mA)
Current Limit (mA)
0°C
25°C
0
24
Figure 6-13. Ground Pin Current vs Input Voltage for
Legacy Chip
200
-55°C
-40°C
0.5
Input Voltage (V)
250
VOUT = 3.3V
1.5
1
0
3
3
2.5
150
100
200
150
100
50
50
0
-55
0
Temperature (°C)
Figure 6-17. Current Limit vs Junction Temperature for
Legacy Chip
VOUT = 3.3V
VIN = 4.8V
-25
5
35
65
Temperature (C)
95
125
150
Figure 6-18. Current Limit vs Junction Temperature for
New Chip
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6.5 Typical Characteristics (continued)
7
VIN = 4.3 V
VOUT = 3.3 V
COUT = 1 mF
IOUT = 1 mA
6
IOUT = 50 mA
5
4
3
2
1
0
100
1k
10 k
100 k
Frequency (Hz)
100
VIN = 4.3 V
VOUT = 3.3 V
COUT = 10 mF
TJ = +25°C
90
80
70
IOUT = 1 mA
60
50
40
30
IOUT = 50 mA
20
10
0
10
100
1k
10 k
100 k
1M
10 M
Frequency (Hz)
Figure 6-21. Power-Supply Ripple Rejection vs Frequency for
Legacy Chip
2
1
0.5
0.2
0.1
0.05
0.02
0.01
0.005
1x107
1mA
50mA
90
80
70
60
50
40
VIN = 4.3V
VOUT = 3.3V
COUT = 10F
TJ = 25C
30
20
10
0
1x101
1x102
1x103
1x104
1x105
f - Frequency (Hz)
1x106
1x107
Figure 6-22. Power-Supply Ripple Rejection vs Frequency for
New Chip
8
VOUT = 3.3 V
RL = 66 W
COUT = 10 mF
5
4
3
VIN
VOUT = 3.3V
IOUT = 50mA
COUT = 10F
7
VOUT
2
6
5
VIN
4
3
VOUT
2
1
1
0
0
0
Time (2 ms/div)
Figure 6-23. Power-Up, Power-Down for Legacy Chip
10
1x106
100
VOUT - Output Voltage - V
VIN - Input Voltage - V
Input Voltage (V)
Output Voltage (V)
6
Integrated Noise from
200Hz to 100KHz
1mA : 473VRMS
50mA : 565VRMS
0.002
0.001
1x101
1x102
1x103
1x104
1x105
f - Frequency - Hz
8
7
1mA
50mA
Figure 6-20. Output Spectral Noise Density vs Frequency for
New Chip
PSRR - Power Supply Ripple Rejection - dB
Figure 6-19. Output Spectral Noise Density vs Frequency for
Legacy Chip
Power-Supply Rejection Ratio (dB)
20
10
5
8
Output Spectral Noise Density - V/Hz
Output Spectral Noise Density (mV/?Hz)
at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 1.0 V or 2.5 V (whichever is greater), IOUT = 1 mA, CIN = 1 µF, and
COUT = 1 µF (unless otherwise noted)
2
4
6
8
10 12 14
t - Time - ms
16
18
20
22
Figure 6-24. Power-Up, Power-Down for New Chip
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6.5 Typical Characteristics (continued)
-50
5.3
50
7
0
6.5
-50
6
5.5
5
-200
-250
4
4.3
0
Time (50 ms/div)
50
100
150
200 250 300
t - Time - s
350
400
0
-200
100
50
120
-200
60
-400
40
-600
20
-800
0
0
Figure 6-27. Load Transient Response for Legacy Chip
4
3
15
2
COUT = 10F
dV/dt = 1.15V/s
VIN
10
5
1
0
0
2000
4000
6000
t - Time - s
8000
-1
10000
Figure 6-29. Line Transient Response for New Chip
-1000
900 1200 1500 1800 2100 2400 2700 3000
t - Time - us
7
VIN
VOUT
IOUT = 50mA
COUT = 10F
dV/dt = 0.66V/s
25
VIN - Inout Voltage - V
20
600
30
VOUT - Output Voltage - V
25
300
Figure 6-28. Load Transient Response for New Chip
5
0
0
80
Time (0.5 ms/div)
VOUT(1mA)
VOUT(50mA)
200
100
0
30
-300
500
600
IOUT
VOUT 400
VIN = 6V
VOUT = 5V
COUT = 10F
dI/dt = 0.5A/s
140
IOUT - Output Current - mA
200
VIN = 4.3 V
VOUT = 3.3 V
COUT = 10 mF
450
Figure 6-26. Line Transient Response for New Chip
160
Output Current (mA) Output Voltage (mV)
-150
4.5
Figure 6-25. Line Transient Response for Legacy Chip
VIN - Input Voltage - V
-100
VOUT = 3.3V
IOUT = 50mA
COUT = 10F
dV/dt = 0.2V/s
AC Coupled Output Voltage - mV
0
7.5
6
20
5
15
4
10
3
5
2
0
VOUT - Output Voltage - V
50
150
VIN
VOUT 100
8
VIN - Input Voltage - V
Input Voltage (V)
Output Voltage (mV)
8.5
VIN = 3.3 V
IOUT = 50 mA
COUT = 10 mF
100
AC Coupled Output Voltage -mV
at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 1.0 V or 2.5 V (whichever is greater), IOUT = 1 mA, CIN = 1 µF, and
COUT = 1 µF (unless otherwise noted)
1
0
0.5
1
1.5
2
2.5
t - Time - ms
3
3.5
4
Figure 6-30. Dropout Exit Transient Response for New Chip
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7 Detailed Description
7.1 Overview
The TLV704 low-dropout regulator (LDO) consumes only 3.4 μA of quiescent current across the entire output
current range, and offers a wide input voltage range and low-dropout voltage in a small package. The device,
which operates over an input range of 2.5 V to 24 V, is stable with any output capacitor greater than or equal
to 0.47 μF. The low quiescent current across the complete load current range makes the TLV704 designed
for powering battery-operated applications. The TLV704 has internal soft-start to control inrush current into the
output capacitor. This LDO also has overcurrent protection during a load-short or fault condition on the output.
7.2 Functional Block Diagram
V(IN)
V(OUT)
Current
Sense
Leakage Null
Control Circuit
+
–
R1
GND
ILIM
GND
GND
R2
Bandgap
Reference
VREF = 1.205 V
GND
7.3 Feature Description
7.3.1 Wide Supply Range
This device has an operational input supply range of 2.5 V to 24 V, allowing for a wide range of applications. This
wide supply range is designed for applications that have either large transients or high DC voltage supplies.
7.3.2 Low Quiescent Current
This device only requires 3.4 μA (typical) of quiescent current across the complete load current range (0 mA to
150 mA) and has a maximum current consumption of 4.5 μA (for new device only) at –40°C to +125°C.
7.3.3 Dropout Voltage (VDO)
Dropout voltage (VDO) is defined as the input voltage minus the output voltage (VIN – VOUT) at the rated output
current (IRATED), where the pass transistor is fully on. IRATED is the maximum IOUT listed in the Recommended
Operating Conditions table. In dropout operation, the pass transistor is in the ohmic or triode region of operation,
and acts as a switch. The dropout voltage indirectly specifies a minimum input voltage greater than the nominal
programmed output voltage at which the output voltage is expected to stay in regulation. If the input voltage falls
to less than the value required to maintain output regulation, the output voltage falls as well.
For a CMOS regulator, the dropout voltage is determined by the drain-source, on-state resistance (RDS(ON)) of
the pass transistor. Therefore, if the linear regulator operates at less than the rated current, the dropout voltage
for that current scales accordingly. Use Equation 1 to calculate the RDS(ON) of the device.
V
RDS ON = I DO
RATED
12
(1)
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7.3.4 Current Limit
The device has an internal current limit circuit that protects the regulator during transient high-load current faults
or shorting events. The current limit is a brick-wall scheme. In a high-load current fault, the brick-wall scheme
limits the output current to the current limit (ICL). ICL is listed in the Electrical Characteristics table.
The output voltage is not regulated when the device is in current limit. When a current limit event occurs, the
device begins to heat up because of the increase in power dissipation. When the device is in brick-wall current
limit, the pass transistor dissipates power [(VIN – VOUT) × ICL]. For more information on current limits, see the
Know Your Limits application note.
Figure 7-1 shows a diagram of the current limit.
VOUT
Brickwall
VOUT(nom)
IOUT
0V
0mA
IRATED
ICL
Figure 7-1. Current Limit
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7.4 Device Functional Modes
Table 7-1 provides a quick comparison between the normal, dropout, and disabled modes of operation.
Table 7-1. Device Functional Mode Comparison
OPERATING MODE
PARAMETER
VIN
IOUT
Normal
VIN > VOUT(nom) + VDO
IOUT < ICL
Dropout
VIN < VOUT(nom) + VDO
IOUT < ICL
7.4.1 Normal Operation
The device regulates to the nominal output voltage under the following conditions:
•
•
•
The input voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(nom) + VDO)
The output current is less than the current limit (IOUT < ICL)
The device junction temperature is greater than –40°C and less than +125°C
7.4.2 Dropout Operation
If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other
conditions are met for normal operation, the device operates in dropout mode. In this mode, the output voltage
tracks the input voltage. During this mode, the transient performance of the device becomes significantly
degraded because the pass transistor is in the ohmic or triode region, and acts as a switch. Line or load
transients in dropout can result in large output voltage deviations.
When the device is in a steady dropout state (defined as when the device is in dropout, VIN < VOUT(NOM) + VDO,
directly after being in a normal regulation state, but not during start up), the pass transistor is driven into the
ohmic or triode region. When the input voltage returns to a value greater than or equal to the nominal output
voltage plus the dropout voltage (VOUT(NOM) + VDO), the output voltage can overshoot for a short period of time
while the device pulls the pass transistor back into the linear region.
14
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The TLV704 LDO regulator is designed for battery-powered applications and is a good attachment to low-power
microcontrollers (such as the MSP430) because of the device low IQ performance across the entire load current
range. The ultra-low supply current of the TLV704 maximizes efficiency at light loads, and the high input voltage
range and flexibility of output voltage selection in fixed output levels makes the device applicable for supplies
such as unconditioned solar panels.
8.2 Typical Application
TLV70433
VOUT
VIN
IN
OUT
0.1μF
MCU
1μF
GND
GND
Figure 8-1. Typical Application
8.2.1 Design Requirements
Select the desired device based on the output voltage.
Provide an input supply with adequate headroom to account for dropout and output current to account for the
GND terminal current, and power the load.
8.2.2 Detailed Design Procedure
8.2.2.1 External Capacitor Requirements
The device is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at the input
and output. Multilayer ceramic capacitors have become the industry standard for these types of applications and
are recommended, but must be used with good judgment. Ceramic capacitors that employ X7R-, X5R-, and
C0G-rated dielectric materials provide relatively good capacitive stability across temperature, whereas the use of
Y5V-rated capacitors is discouraged because of large variations in capacitance.
Regardless of the ceramic capacitor type selected, the effective capacitance varies with operating voltage and
temperature. Generally, expect the effective capacitance to decrease by as much as 50%. The input and output
capacitors recommended in the Recommended Operating Conditions table account for an effective capacitance
of approximately 50% of the nominal value.
8.2.2.2 Input and Output Capacitor Requirements
Although an input capacitor is not required for stability, good analog design practice is to connect a capacitor
from IN to GND. This capacitor counteracts reactive input sources and improves transient response, input ripple,
and PSRR. Use an input capacitor if the source impedance is more than 0.5 Ω. A higher value capacitor can be
necessary if large, fast rise-time load or line transients are anticipated or if the device is located several inches
from the input power source.
Dynamic performance of the device is improved by using a large output capacitor. Use an output capacitor within
the range specified in the Recommended Operating Conditions table for stability.
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8.2.2.3 Reverse Current
Excessive reverse current can damage this device. Reverse current flows through the intrinsic body diode of the
PMOS pass transistor instead of the normal conducting channel. At high magnitudes, this current flow degrades
the long-term reliability of the device.
Conditions where reverse current can occur are outlined in this section, all of which can exceed the absolute
maximum rating of VOUT ≤ VIN + 0.3 V. These conditions are:
•
•
•
If the device has a large COUT and the input supply collapses with little or no load current
The output is biased when the input supply is not established
The output is biased above the input supply
If reverse current flow is expected in the application, external protection is recommended to protect the device.
Reverse current is not limited in the device, so external limiting is required if extended reverse voltage operation
is anticipated. Limit reverse current to 5% or less of the rated output current of the device in the event this
current cannot be avoided.
Figure 8-2 shows one approach for protecting the device.
Schottky Diode
Internal Body Diode
IN
OUT
CIN
COUT
GND
GND
GND
GND
Figure 8-2. Example Circuit for Reverse Current Protection Using a Schottky Diode
8.2.2.4 Power Dissipation (PD)
Circuit reliability requires consideration of the device power dissipation, location of the circuit on the printed
circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator must have few
or no other heat-generating devices that cause added thermal stress.
To first-order approximation, power dissipation in the regulator depends on the input-to-output voltage difference
and load conditions. The following equation calculates power dissipation (PD).
PD = (VIN – VOUT) × IOUT
(2)
Note
Power dissipation can be minimized, and therefore greater efficiency can be achieved, by correct
selection of the system voltage rails. For the lowest power dissipation, use the minimum input voltage
required for correct output regulation.
For devices with a thermal pad, the primary heat conduction path for the device package is through the thermal
pad to the PCB. Solder the thermal pad to a copper pad area under the device. This pad area must contain an
array of plated vias that conduct heat to additional copper planes for increased heat dissipation.
16
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The maximum power dissipation determines the maximum allowable ambient temperature (TA) for the device.
According to the following equation, power dissipation and junction temperature are most often related by the
junction-to-ambient thermal resistance (RθJA) of the combined PCB and device package and the temperature of
the ambient air (TA).
TJ = TA + (RθJA × PD)
(3)
Thermal resistance (RθJA) is highly dependent on the heat-spreading capability built into the particular PCB
design, and therefore varies according to the total copper area, copper weight, and location of the planes.
The junction-to-ambient thermal resistance listed in the Thermal Information table is determined by the JEDEC
standard PCB and copper-spreading area, and is used as a relative measure of package thermal performance.
8.2.2.5 Estimating Junction Temperature
The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures
of the linear regulator when in-circuit on a typical PCB board application. These metrics are not thermal
resistance parameters and instead offer a practical and relative way to estimate junction temperature. These
psi metrics are determined to be significantly independent of the copper area available for heat-spreading.
The Thermal Information table lists the primary thermal metrics, which are the junction-to-top characterization
parameter (ψJT) and junction-to-board characterization parameter (ψJB). These parameters provide two methods
for calculating the junction temperature (TJ), as described in the following equations. Use the junction-to-top
characterization parameter (ψJT) with the temperature at the center-top of device package (TT) to calculate
the junction temperature. Use the junction-to-board characterization parameter (ψJB) with the PCB surface
temperature 1 mm from the device package (TB) to calculate the junction temperature.
TJ = TT + ψJT × PD
(4)
where:
•
•
PD is the dissipated power
TT is the temperature at the center-top of the device package
TJ = TB + ψJB × PD
(5)
where:
•
TB is the PCB surface temperature measured 1 mm from the device package and centered on the package
edge
For detailed information on the thermal metrics and how to use them, see the Semiconductor and IC Package
Thermal Metrics application note.
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8.2.3 Application Curves
8
8
5
4
3
VIN
VOUT
2
6
5
VIN
4
3
VOUT
2
1
1
0
0
0
Time (2 ms/div)
4
6
8
10 12 14
t - Time - ms
16
50
0
-50
5.3
7.5
50
7
0
6.5
-50
6
VOUT = 3.3V
IOUT = 50mA
COUT = 10F
dV/dt = 0.2V/s
5.5
5
4.5
4.3
0
Time (50 ms/div)
50
100
150
200 250 300
t - Time - s
350
0
-200
100
50
120
100
400
450
-300
500
600
IOUT
VOUT 400
200
0
-200
60
-400
40
-600
20
-800
0
Time (0.5 ms/div)
-200
80
0
0
Figure 8-7. Load Transient Response for Legacy
Chip
18
VIN = 6V
VOUT = 5V
COUT = 10F
dI/dt = 0.5A/s
140
IOUT - Output Current - mA
Output Current (mA) Output Voltage (mV)
200
-150
Figure 8-6. Line Transient Response for New Chip
160
VIN = 4.3 V
VOUT = 3.3 V
COUT = 10 mF
-100
-250
4
Figure 8-5. Line Transient Response for Legacy
Chip
22
150
VIN
VOUT 100
8
VIN - Input Voltage - V
Output Voltage (mV)
Input Voltage (V)
100
20
Figure 8-4. Power-Up, Power-Down for New Chip
8.5
VIN = 3.3 V
IOUT = 50 mA
COUT = 10 mF
18
AC Coupled Output Voltage -mV
Figure 8-3. Power-Up, Power-Down for Legacy
Chip
2
300
600
AC Coupled Output Voltage - mV
6
VOUT = 3.3V
IOUT = 50mA
COUT = 10F
7
VOUT - Output Voltage - V
VIN - Input Voltage - V
Input Voltage (V)
Output Voltage (V)
7
VOUT = 3.3 V
RL = 66 W
COUT = 10 mF
-1000
900 1200 1500 1800 2100 2400 2700 3000
t - Time - us
Figure 8-8. Load Transient Response for New Chip
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3
15
2
COUT = 10F
dV/dt = 1.15V/s
VIN
10
1
5
25
0
0
0
2000
4000
6000
t - Time - s
8000
7
-1
10000
Figure 8-9. Line Transient Response for New Chip
VIN
VOUT
IOUT = 50mA
COUT = 10F
dV/dt = 0.66V/s
6
20
5
15
4
10
3
5
2
0
VOUT - Output Voltage - V
20
4
VIN - Inout Voltage - V
25
VIN - Input Voltage - V
30
5
VOUT(1mA)
VOUT(50mA)
VOUT - Output Voltage - V
30
1
0
0.5
1
1.5
2
2.5
t - Time - ms
3
3.5
4
Figure 8-10. Dropout Exit Transient Response for
New Chip
8.3 Best Design Practices
Place at least one 0.47-µF capacitor as close as possible to the OUT and GND pins of the regulator.
Do not connect the output capacitor to the regulator using a long, thin trace.
Connect an input capacitor as close as possible to the IN and GND pins of the regulator for best performance.
Do not exceed the absolute maximum ratings.
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8.4 Power Supply Recommendations
The TLV704 is designed to operate from an input voltage supply range between 2.5 V and 24 V. The input
voltage range must provide adequate headroom for the device to have a regulated output. Inductive impedances
between the input supply and the IN pin can create significant voltage excursions at the IN pin during start-up or
load transient events. If inductive impedances are unavoidable, use an input capacitor.
8.5 Layout
8.5.1 Layout Guidelines
For best overall performance, place all circuit components on the same side of the printed-circuit-board and
as near as practical to the respective LDO pin connections. Place ground return connections for the input
and output capacitors as close to the GND pin as possible, using wide, component-side, copper planes. Do
not use vias and long traces to create LDO circuit connections to the input capacitor, output capacitor, or the
resistor divider because this practice negatively affects system performance. This grounding and layout scheme
minimizes inductive parasitics, and thereby reduces load-current transients, minimizes noise, and increases
circuit stability. A ground reference plane is also recommended and is either embedded in the PCB or located
on the bottom side of the PCB opposite the components. This reference plane serves to assure accuracy of the
output voltage and shield the LDO from noise.
8.5.1.1 Power Dissipation
To provide reliable operation, worst-case junction temperature must not exceed 125°C. This restriction limits the
power dissipation the regulator can handle in any given application. To make sure the junction temperature is
within acceptable limits, calculate the maximum allowable dissipation, PD(max), and the actual dissipation, PD,
which must be less than or equal to PD(max).
The maximum-power-dissipation limit is determined using Equation 6:
where:
•
•
•
PD max =
TJmax− TA
RθJA
(6)
TJmax is the maximum allowable junction temperature
RθJA is the thermal resistance junction-to-ambient for the package (see the Thermal Informationtable)
TA is the ambient temperature
The regulator dissipation is calculated using Equation 7:
PD = VIN − VOUT × IOUT
(7)
8.5.2 Layout Example
VOUT
VIN
COUT
CIN
GND PLANE
Figure 8-11. Layout Example for the DBV Package
20
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9 Device and Documentation Support
9.1 Device Support
9.1.1 Development Support
9.1.1.1 Evaluation Module
An evaluation module (EVM) is available to assist in the initial circuit performance evaluation using the TLV704.
The TLV70433DBVEVM-712 evaluation module (and related user guide) can be requested at the Texas
Instruments website through the product folders or purchased directly from the TI eStore.
9.1.2 Device Nomenclature
Table 9-1. Available Options(1)
PRODUCT
VOUT
xx is the nominal output voltage (for example 33 = 3.3 V).
yyy is the package designator.
z is the package quantity.
TLV704xxyyyz
Legacy chip
xx is the nominal output voltage (for example 33 = 3.3 V).
yyy is the package designator.
z is the package quantity. M3 is a suffix designator for newer chip
redesigns, fabricated on the latest TI process technology.
TLV704xxyyyzM3
New chip
(1)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
9.2 Documentation Support
9.2.1 Related Documentation
For related documentation see the following:
•
Texas Instruments, TLV70433DBVEVM-712, TLV70433PKEVM-712 Evaluation Modules user guide
9.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
9.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
9.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
9.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
9.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
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10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
3-May-2023
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TLV70418DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
1NG
Samples
TLV70430DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
QUQ
Samples
TLV70430DBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
QUQ
Samples
TLV70433DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PAO
Samples
TLV70433DBVRM3
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PAO
Samples
TLV70433DBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PAO
Samples
TLV704345DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
13T
Samples
TLV704345DBVRM3
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
13T
Samples
TLV704345DBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
13T
Samples
TLV70436DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PAW
Samples
TLV70436DBVRM3
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PAW
Samples
TLV70436DBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PAW
Samples
TLV70450DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PAX
Samples
TLV70450DBVRM3
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PAX
Samples
TLV70450DBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PAX
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
3-May-2023
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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