TLV7031, TLV7032, TLV7041, TLV7042, TLV7034, TLV7044
SLVSE13H – SEPTEMBER 2017 – REVISED JULY 2021
TLV703x and TLV704x Small-Size, Nanopower, Low-Voltage Comparators
1 Features
•
•
•
•
•
•
•
•
•
•
•
Ultra-small X2SON, WSON, WQFN packages
Tiny SOT-23, SC70, VSSOP, and TSSOP
packages
Wide supply voltage range of 1.6 V to 6.5 V
Quiescent supply current of 315 nA
Low propagation delay of 3 µs
Rail-to-rail common-mode input voltage
Internal hysteresis
Push-pull output (TLV703x)
Open-drain output (TLV704x)
No phase reversal for overdriven inputs
–40°C to 125°C Operating temperature
2 Applications
•
•
•
•
•
•
•
•
Mobile phones and tablets
Headsets/headphones & earbuds
PC & notebooks
Gas Detector
Smoke & heat detector
Motion Detector
Gas Meter
Servo drive position sensor
delay of 3 μs and a quiescent supply current of 315
nA. The benefit of fast response time at nanoPower
enables power-conscious systems to monitor and
respond quickly to fault conditions. With an operating
voltage range of 1.6 V to 6.5 V, these comparators are
compatible with 3-V and 5-V systems.
The TLV703x and TLV704x also ensure no output
phase inversion with overdriven inputs and internal
hysteresis, so engineers can use this family of
comparators for precision voltage monitoring in harsh,
noisy environments where slow-moving input signals
must be converted into clean digital outputs.
The TLV703x has a push-pull output stage capable
of sinking and sourcing milliamps of current when
controlling an LED or driving a capacitive load. The
TLV704x has an open-drain output stage that can
be pulled beyond VCC, making it appropriate for level
translators and bipolar to single-ended converters.
Device Information
PACKAGE (PINS) (1)
PART NUMBERS
X2SON (5)
0.80 mm × 0.80 mm
TLV7031, TLV7041 SC70 (5)
2.00 mm × 1.25 mm
SOT-23 (5)
2.90 mm × 1.60 mm
VSSOP (8)
3.00 mm x 3.00 mm
TLV7032, TLV7042 SOT-23 (8)
2.90 mm x 1.60 mm
3 Description
The TLV7031/TLV7041 (single-channel), TLV7032/42
(dual-channel), and TLV7034/44 (quad-channel) are
low-voltage, nanoPower comparators. These devices
are available in an ultra-small, leadless packages as
well as standard 5-pin SC70, SOT-23, VSSOP, and
TSSOP packages, making them applicable for spacecritical designs like smartphones, smart meters, and
other portable or battery-powered applications.
BODY SIZE (NOM)
TLV7034, TLV7044
(1)
WSON (8)
2.00 mm x 2.00 mm
WQFN (16)
3.00 mm x 3.00 mm
TSSOP (14)
4.40 mm x 5.00 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
The TLV703x and TLV704x offer an excellent
combination of speed and power, with a propagation
0.6
US dime (18x18x1.35 mm3)
5-Lead SC70
0.5
0.4
ICC (PA)
5-Pin X2SON
0.3
0.2
Temp -40°C
Temp 25°C
Temp 125°C
0.1
X2SON Package vs SC70 and US Dime
0
1.5
2.5
3.5
4.5
5.5
6.5
VCC (V)
ICC vs. Supply Voltage
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLV7031, TLV7032, TLV7041, TLV7042, TLV7034, TLV7044
www.ti.com
SLVSE13H – SEPTEMBER 2017 – REVISED JULY 2021
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................4
Pin Functions.................................................................... 4
Pin Functions: TLV7032/42...............................................5
Pin Functions: TLV7034/44...............................................6
6 Specifications.................................................................. 7
6.1 Absolute Maximum Ratings........................................ 7
6.2 ESD Ratings............................................................... 7
6.3 Recommended Operating Conditions.........................7
6.4 Thermal Information (Single)...................................... 7
6.5 Thermal Information (Dual)......................................... 8
6.6 Thermal Information (Quad)........................................8
6.7 Electrical Characteristics (Single)............................... 9
6.8 Switching Characteristics (Single).............................. 9
6.9 Electrical Characteristics (Dual)................................10
6.10 Switching Characteristics (Dual)............................. 10
6.11 Electrical Characteristics (Quad)............................. 11
6.12 Switching Characteristics (Quad)............................11
6.13 Timing Diagrams..................................................... 12
6.14 Typical Characteristics............................................ 13
7 Detailed Description......................................................18
7.1 Overview................................................................... 18
7.2 Functional Block Diagram......................................... 18
7.3 Feature Description...................................................18
7.4 Device Functional Modes..........................................18
8 Application and Implementation.................................. 20
8.1 Application Information............................................. 20
8.2 Typical Applications.................................................. 23
9 Power Supply Recommendations................................30
10 Layout...........................................................................31
10.1 Layout Guidelines................................................... 31
10.2 Layout Example...................................................... 31
11 Device and Documentation Support..........................32
11.1 Device Support........................................................32
11.2 Documentation Support.......................................... 32
11.3 Receiving Notification of Documentation Updates.. 32
11.4 Support Resources................................................. 32
11.5 Trademarks............................................................. 32
11.6 Electrostatic Discharge Caution.............................. 32
11.7 Glossary.................................................................. 32
12 Mechanical, Packaging, and Orderable
Information.................................................................... 32
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision G (Nov 2020) to Revision H (July 2021)
Page
• Releasing TSSOP package option..................................................................................................................... 1
Changes from Revision F (November 2019) to Revision G (December 2020)
Page
• Updated the numbering format for tables, figures, and cross-references throughout the document .................1
• Added SOT-23 (8) and WSON (8) for dual channel options...............................................................................1
Changes from Revision E (June 2019) to Revision F (November 2019)
Page
• Added quad channel versions............................................................................................................................ 1
• Added SOT-23 (8) and WSON (8) for dual channel options ..............................................................................1
• Added QUAD package options...........................................................................................................................1
• Added TSSOP and RTE pinout information to Pin Configuration and Functions section ..................................5
Changes from Revision D (April 2019) to Revision E (June 2019)
Page
• Changed VOH min from 4.7V to 4.65V for all package options in EC Table (Single) ........................................9
• Changed VOL max from 300mV to 350mV for all package options in EC Table (Single) ................................. 9
• Deleted separate rows for VOH & VOL for DBV package options only in EC Table (Single) ............................ 9
Changes from Revision C (March 2019) to Revision D (April 2019)
Page
• Added separate rows for VOH & VOL for DBV package options in EC Table (Single) ......................................9
Changes from Revision B (May 2018) to Revision C (March 2019)
Page
• Added dual channel versions in VSSOP package..............................................................................................1
• Changed TLV7031 to TLV703x and TLV7041 to TLV704x throughout the document ....................................... 1
• Added dual channel versions..............................................................................................................................1
2
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•
•
SLVSE13H – SEPTEMBER 2017 – REVISED JULY 2021
Added Device Information dual channel versions in VSSOP package...............................................................1
Deleted The SOT-23 package is in preview only................................................................................................1
Changes from Revision A (January 2018) to Revision B (May 2018)
Page
• Changed the preview SC70 package to production data................................................................................... 1
Changes from Revision * (September 2017) to Revision A (January 2018)
Page
• Changed data sheet title from: TLV7031/TLV7041 Small-Size, nanoPower, Low-Voltage Comparators to:
TLV7031 and TLV7041 Small Size, nanopower, Low-Voltage Comparators ..................................................... 1
• Added Internal Hysteresis bullet to Features .....................................................................................................1
• Specified which device has push-pull output and open-drain output options in Features ................................. 1
• Removed (TLV7031) from key graphic title because the graph covers both the TLV7031 and TLV7041
devices................................................................................................................................................................1
• Added X2SON tablenote to Pin Functions table ................................................................................................4
• Changed Figure 6-2 .........................................................................................................................................12
• Added note to the Timing Diagrams section.....................................................................................................12
• Smoothed Propagation Delay plots in Propagation Delay (L-H) vs Input Overdrive through .......................... 13
• Changed vertical labels on Output Voltage Low vs Output Sink Current, Output Voltage Low vs Output Sink
Current, Figure 6-17, and Rise/Fall Time vs Load Capacitance ...................................................................... 13
• Changed Functional Block Diagram ................................................................................................................ 18
• Changed text 'the TLV7041 features an open-drain output stage enabling the output logic levels to be pulled
up to an external source up to 7 V' to 'the TLV7041 features an open-drain output stage enabling the output
logic levels to be pulled up to an external source up to 6.5 V'.......................................................................... 19
• Changed Figure 8-3 .........................................................................................................................................23
• Added note to the Layout Example section...................................................................................................... 31
• Added Documentation Support section ........................................................................................................... 32
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SLVSE13H – SEPTEMBER 2017 – REVISED JULY 2021
5 Pin Configuration and Functions
OUT
1
5
IN+
3
VEE
VCC
2
4
± IN
Not to scale
Figure 5-1. DPW Package
5-Pin X2SON
Top View
OUT
1
VEE
2
IN+
3
5
VCC
4
IN-
Figure 5-2. DBV and DCK Package
5-Pin SOT-23 and SC70
Top View
Pin Functions
PIN
DESCRIPTION
SOT-23, SC70
NAME
1
1
OUT
O
Output
2
5
VCC
P
Positive (highest) power supply
3
2
VEE
P
Negative (lowest) power supply
4
4
IN–
I
Inverting input
5
3
IN+
I
Noninverting input
(1)
(2)
4
I/O(2)
X2SON(1)
The application report Designing and Manufacturing With TI's X2SON Packages (SCEA055) provides more details on the optimal PCB
designs.
I = Input, O = Output, P = Power
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SLVSE13H – SEPTEMBER 2017 – REVISED JULY 2021
OUTA
INAINA+
1
8
2
7
3
6
VEE
4
5
VCC
OUTB
INBINB+
Figure 5-3. TLV7032/42 DGK, DDF Packages
8-Pin VSSOP, SOT-23
Top View
A.
OUTA
INAINA+
2
3
6
VEE
4
5
1
8
7
VCC
OUTB
Thermal
Pad
INBINB+
Connect thermal pad to V–.
Figure 5-4. TLV7032/42 DSG Package
8-Pin WSON With Exposed Thermal Pad
Top View
Pin Functions: TLV7032/42
PIN
NAME
NO.
I/O
DESCRIPTION
INA–
2
I
Inverting input, channel A
INA+
3
I
Noninverting input, channel A
INB–
6
I
Inverting input, channel B
INB+
5
I
Noninverting input, channel B
OUTA
1
O
Output, channel A
OUTB
7
O
Output, channel B
VEE
4
—
Negative (lowest) supply or ground (for single-supply operation)
VCC
8
—
Positive (highest) supply
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VEE
+IN A
1
+IN B
5
10
+IN C
VCC
2
NC
3
+IN B
4
±IN B
6
9
±IN C
OUT B
7
8
OUT C
±IN D
11
13
4
Thermal
Pad
8
VCC
±IN C
+IN D
OUT D
12
14
3
7
+IN A
OUT C
±IN D
OUT A
13
15
2
6
±IN A
OUT B
OUT D
±IN A
14
5
1
±IN B
OUT A
16
SLVSE13H – SEPTEMBER 2017 – REVISED JULY 2021
12
+IN D
11
VEE
10
NC
9
+IN C
Not to scale
Figure 5-5. TLV7034/44 PW Packages
14-Pin TSSOP
Top View
A.
(TOP view,
not to scale)
Connect thermal pad to V–.
Figure 5-6. TLV7034/44 RTE Package
16-Pin WQFN With Exposed Thermal Pad
Top View
Pin Functions: TLV7034/44
PIN
NAME
6
TSSOP
WQFN
I/O
DESCRIPTION
–IN1 A
2
16
I
Inverting input, channel A
+IN A
3
1
I
Noninverting input, channel A
–IN B
6
5
I
Inverting input, channel B
+IN B
5
4
I
Noninverting input, channel B
–IN C
9
8
I
Inverting input, channel C
+IN C
10
9
I
Noninverting input, channel C
–IN D
13
13
I
Inverting input, channel D
+IN D
12
12
I
Noninverting input, channel D
NC
—
3, 10
—
No internal connection
OUT A
1
15
O
Output, channel A
OUT B
7
6
O
Output, channel B
OUT C
8
7
O
Output, channel C
OUT D
14
14
O
Output, channel D
VEE
11
11
—
Negative (lowest) supply or ground (for single-supply operation)
VCC
4
2
—
Positive (highest) supply
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SLVSE13H – SEPTEMBER 2017 – REVISED JULY 2021
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
–0.3
7
VEE – 0.3
7
Supply voltage VS = VCC - VEE
Input pins (IN+, IN-)(2)
Current into Input pins (IN+, IN-)
UNIT
V
V
±10
mA
Output (OUT) (TLV703x)(3)
VEE – 0.3
VCC + 0.3
V
Output (OUT) (TLV704x)
VEE – 0.3
7
V
Output short-circuit
duration(4)
Junction temperature, TJ
Storage temperature, Tstg
(1)
(2)
(3)
(4)
–65
10
s
150
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
Input terminals are diode-clamped to VEE. Input signals that can swing 0.3V below VEE must be current-limited to 10mA or less
Output maximum is (VCC + 0.3 V) or 7 V, whichever is less.
Short-circuit to ground, one comparator per package.
6.2 ESD Ratings
VALUE
Electrostatic
discharge
V(ESD)
(1)
(2)
Human-body model (HBM), per ANSI/ESDA/JEDEC
JS-001(1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
1.6
6.5
V
VEE – 0.1
VCC + 0.1
V
–40
125
°C
Supply voltage VS = VCC – VEE
Input voltage range
Ambient temperature, TA
UNIT
6.4 Thermal Information (Single)
TLV7031/TLV7041
THERMAL METRIC(1)
DPW (X2SON)
DBV (SOT-23)
DCK (SC70)
UNIT
5 PINS
5 PINS
5 PINS
RθJA
Junction-to-ambient thermal resistance
533.2
297.2
278.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
302.7
224.7
186.6
°C/W
RθJB
Junction-to-board thermal resistance
408.3
200.1
113.2
°C/W
ΨJT
Junction-to-top characterization parameter
71.5
141.2
82.3
°C/W
ΨJB
Junction-to-board characterization parameter
405.9
198.9
112.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
188.3
N/A
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SLVSE13H – SEPTEMBER 2017 – REVISED JULY 2021
6.5 Thermal Information (Dual)
TLV7032/TLV7042
THERMAL
METRIC(1)
DGK (VSSOP)
DDF (SOT-23)
DSG (WSON)
8 PINS
8 PINS
8 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
211.7
212.5
106.1
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
96.1
127.3
127.3
°C/W
RθJB
Junction-to-board thermal resistance
133.5
129.2
72.5
°C/W
ΨJT
Junction-to-top characterization parameter
28.3
25.8
16.8
°C/W
ΨJB
Junction-to-board characterization parameter
131.7
129.0
72.2
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
47.6
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.6 Thermal Information (Quad)
TLV7034/44
THERMAL
8
METRIC(1)
RTE (QFN)
PW (TSSOP)
16 PINS
14 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
65.4
131.0
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
70.2
60.5
°C/W
RθJB
Junction-to-board thermal resistance
40.5
74.1
°C/W
ΨJT
Junction-to-top characterization parameter
5.6
12.6
°C/W
ΨJB
Junction-to-board characterization parameter
40.5
73.5
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
24.1
n/a
°C/W
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SLVSE13H – SEPTEMBER 2017 – REVISED JULY 2021
6.7 Electrical Characteristics (Single)
VS = 1.8 V to 5 V, VCM = VS / 2; minimum and maximum values are at TA = –40°C to +125°C (unless otherwise noted).
Typical values are at TA = 25°C.
PARAMETER
VIO
TEST CONDITIONS
MIN
TYP
MAX
±0.1
±8
UNIT
mV
7
17
mV
Input Offset Voltage
VS = 1.8 V and 5 V, VCM = VS / 2
VHYS
Hysteresis
VS = 1.8 V and 5 V, VCM = VS / 2,
TA = 25°C
VCM
Common-mode voltage range
IB
Input bias current
2
pA
IOS
Input offset current
1
pA
VOH
Output voltage high
(for TLV7031 only)
VS = 5 V, VEE = 0 V, IO = 3 mA
4.8
V
VOL
Output voltage low
VS = 5 V, VEE = 0 V, IO = 3 mA
250
ILKG
Open-drain output leakage
current (TLV7041 only)
VS = 5 V, VID = +0.1 V (output high),
VPULLUP = VCC
100
pA
CMRR
Common-mode rejection ratio
VEE < VCM < VCC, VS = 5 V
73
dB
PSRR
Power supply rejection ratio
VS = 1.8 V to 5 V, VCM = VS / 2
77
dB
VS = 5 V, sourcing
29
VS = 5 V, sinking
33
ISC
Short-circuit current
ICC
Supply current
2
VEE
VCC + 0.1
4.65
VS = 1.8 V, no load, VID = –0.1 V (Output
Low)
335
350
V
mV
mA
900
nA
6.8 Switching Characteristics (Single)
Typical values are at TA = 25°C, VS = 5 V, VCM = VS / 2; CL = 15 pF, input overdrive = 100 mV (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tPHL
Propagation delay time, high tolow (RP = 2.5 kΩ TLV7041
only)
Midpoint of input to midpoint of output,
VOD = 100 mV
3
µs
tPLH
Propagation delay time, low-to high
(RP = 2.5 kΩ TLV7041
only)
Midpoint of input to midpoint of output,
VOD = 100 mV
3
µs
tR
Rise time (TLV7031 only)
Measured from 10% to 90%
4.5
ns
tF
Fall time
Measured from 10% to 90%
4.5
ns
Power-up time
During power on, VCC must exceed 1.6V for
200 µs before the output will reflect the input.
200
µs
tON
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6.9 Electrical Characteristics (Dual)
VS = 1.8 V to 5 V, VCM = VS / 2; minimum and maximum values are at TA = –40°C to +125°C (unless otherwise noted).
Typical values are at TA = 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
±0.1
±8
UNIT
mV
10
25
mV
VIO
Input Offset Voltage
VS = 1.8 V and 5 V, VCM = VS / 2
VHYS
Hysteresis
VS = 1.8 V and 5 V, VCM = VS / 2
VCM
Common-mode voltage range
IB
Input bias current
2
pA
IOS
Input offset current
1
pA
VOH
Output voltage high (for TLV7032
only)
VS = 5 V, VEE = 0 V, IO = 3 mA
4.8
V
VOL
Output voltage low
VS = 5 V, VEE = 0 V, IO = 3 mA
250
ILKG
Open-drain output leakage
current (TLV7042 only)
VS = 5 V, VID = +0.1 V (output high),
VPULLUP = VCC
100
pA
CMRR
Common-mode rejection ratio
VEE < VCM < VCC, VS = 5 V
73
dB
PSRR
Power supply rejection ratio
VS = 1.8 V to 5 V, VCM = VS / 2
77
dB
VS = 5 V, sourcing (for TLV7032 only)
29
VS = 5 V, sinking
33
ISC
Short-circuit current
ICC
Supply current / Channel
3
VEE
4.65
VS = 1.8 V, no load, VID = –0.1 V (Output Low)
VCC + 0.1
315
350
V
mV
mA
750
nA
6.10 Switching Characteristics (Dual)
Typical values are at TA = 25°C, VS = 5 V, VCM = VS / 2; CL = 15 pF, input overdrive = 100 mV (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tPHL
Propagation delay time, high tolow (RP = 4.99 kΩ TLV7042
only) (1)
Midpoint of input to midpoint of output,
VOD = 100 mV
3
µs
tPLH
Propagation delay time, low-to high
(RP = 4.99 kΩ TLV7042
only) (1)
Midpoint of input to midpoint of output,
VOD = 100 mV
3
µs
tR
Rise time (TLV7032 only)
Measured from 20% to 80%
4.5
ns
tF
Fall time
Measured from 20% to 80%
4.5
ns
Power-up time
During power on, VCC must exceed 1.6V for tON
before the output will reflect the input.
200
µs
tON
(1)
10
The lower limit for RP is 650 Ω
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6.11 Electrical Characteristics (Quad)
VS = 1.8 V to 5 V, VCM = VS / 2; minimum and maximum values are at TA = –40°C to +125°C (unless otherwise noted).
Typical values are at TA = 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
±0.1
±8
UNIT
mV
10
25
mV
VIO
Input Offset Voltage
VS = 1.8 V and 5 V, VCM = VS / 2
VHYS
Hysteresis
VS = 1.8 V and 5 V, VCM = VS / 2
VCM
Common-mode voltage range
IB
Input bias current
2
pA
IOS
Input offset current
1
pA
VOH
Output voltage high (for TLV7034
only)
VS = 5 V, VEE = 0 V, IO = 3 mA
4.8
V
VOL
Output voltage low
VS = 5 V, VEE = 0 V, IO = 3 mA
250
ILKG
Open-drain output leakage
current (TLV7044 only)
VS = 5 V, VID = +0.1 V (output high),
VPULLUP = VCC
100
pA
CMRR
Common-mode rejection ratio
VEE < VCM < VCC, VS = 5 V
73
dB
PSRR
Power supply rejection ratio
VS = 1.8 V to 5 V, VCM = VS / 2
77
dB
VS = 5 V, sourcing (for TLV7034 only)
29
VS = 5 V, sinking
33
ISC
Short-circuit current
ICC
Supply current / Channel
3
VEE
VCC + 0.1
4.65
VS = 1.8 V, no load, VID = –0.1 V (Output Low)
315
350
V
mV
mA
750
nA
6.12 Switching Characteristics (Quad)
Typical values are at TA = 25°C, VS = 5 V, VCM = VS / 2; CL = 15 pF, input overdrive = 100 mV (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tPHL
Propagation delay time, high tolow (RP = 4.99 kΩ TLV7044
only) (1)
Midpoint of input to midpoint of output,
VOD = 100 mV
3
µs
tPLH
Propagation delay time, low-to high
(RP = 4.99 kΩ TLV7044
only) (1)
Midpoint of input to midpoint of output,
VOD = 100 mV
3
µs
tR
Rise time (TLV7034 only)
Measured from 20% to 80%
4.5
ns
tF
Fall time
Measured from 20% to 80%
4.5
ns
Power-up time
During power on, VCC must exceed 1.6V for tON
before the output will reflect the input..
400
µs
tON
(1)
The lower limit for RP is 650 Ω
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6.13 Timing Diagrams
tON
VEE
VCC
VEE + 1.6V
VOH/2
VEE
OUT
Figure 6-1. Start-Up Time Timing Diagram (IN+ > IN–)
Figure 6-2. Propagation Delay Timing Diagram
Note
The propagation delays tpLH and tpHL include the contribution of input offset and hysteresis.
12
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6.14 Typical Characteristics
TA = 25°C, VCC = 5 V, VEE = 0 V, VCM = VCC/2, CL = 15 pF
0.7
0.7
VCM = VCC /2
VCM = VCC
VCM = 0
VCM = VCC /2
VCM = VCC
VCM = 0
0.6
0.5
Input Offset (mV)
Input Offset (mV)
0.6
0.4
0.3
0.2
0.1
0.5
0.4
0.3
0.2
0.1
0
-40
-20
0
20
40
60
80
Temperature (°C)
100
120
0
-40
140
-20
0
20
vio_
VCC = 1.8 V
40
60
80
Temperature (°C)
Figure 6-3. Input Offset vs Temperature
140
vio_
Figure 6-4. Input Offset vs Temperature
1
Temp -40°C
Temp 25°C
Temp 125°C
0.9
0.6
0.8
0.5
Input Offset (mV)
Input Offset (mV)
120
VCC = 3.3 V
0.7
0.4
0.3
0.2
0
-40
0.7
0.6
0.5
0.4
0.3
0.2
VCM = VCC /2
VCM = VCC
VCM = 0
0.1
0.1
0
-20
0
20
40
60
80
Temperature (°C)
100
120
140
0
0.2
0.4
0.6
0.8
vio_
VCC = 5 V
1
1.2
VCM (V)
1.4
1.6
1.8
2
vio_
VCC = 1.8 V
Figure 6-5. Input Offset vs Temperature
Figure 6-6. Input Offset Voltage vs VCM
1
1
Temp -40°C
Temp 25°C
Temp 125°C
0.9
0.8
Temp -40°C
Temp 25°C
Temp 125°C
0.9
0.8
0.7
Input Offset (mV)
Input Offset (mV)
100
0.6
0.5
0.4
0.3
0.7
0.6
0.5
0.4
0.3
0.2
0.2
0.1
0.1
0
0
0
0.5
1
1.5
2
VCM (V)
2.5
VCC = 3.3 V
3
3.5
0
vio_
0.5
1
1.5
2
2.5
3
VCM (V)
3.5
4
4.5
5
vio_
VCC = 5 V
Figure 6-7. Input Offset Voltage vs VCM
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Figure 6-8. Input Offset Voltage vs VCM
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6.14 Typical Characteristics (continued)
10
10
9
9
8
8
7
7
Hysteresis (mV)
Hysteresis (mV)
TA = 25°C, VCC = 5 V, VEE = 0 V, VCM = VCC/2, CL = 15 pF
6
5
4
3
1
-40
5
4
3
VCM = VCC /2
VCM = VCC
VCM = 0
2
6
Temp -40°C
Temp 25°C
Temp 125°C
2
1
-20
0
20
40
60
80
Temperature (°C)
100
120
140
0
VCC = 1.8 V to 5 V
TLV70x1
1
VCM (V)
9
8
8
7
7
Hysteresis (mV)
10
9
6
5
4
hyst
TLV70x1
6
5
4
3
Temp -40°C
Temp 25°C
Temp 125°C
2
2
Figure 6-10. Hysteresis vs VCM
10
3
1.5
VCC = 1.8 V
Figure 6-9. Hysteresis vs Temperature
Hysteresis (mV)
0.5
hyst
Temp -40°C
Temp 25°C
Temp 125°C
2
1
1
0
1
2
3
4
VCM (V)
0
1
VCC = 3.3 V
TLV70x1
2
3
4
5
VCM (V)
hyst
hyst
VCC = 5 V
Figure 6-11. Hysteresis vs VCM
TLV70x1
Figure 6-12. Hysteresis vs VCM
18
14.5
14
13.5
16
13
14
VHYST (mV)
VHYST (mV)
12.5
12
11.5
11
10.5
10
10
VCM = VCC/2
VCM = VCC
VCM = 0
9.5
9
8.5
-40
12
-20
0
20
40
60
80
Temperature (°C)
VCC = 1.8 V to 5 V
100
120
140
6
-0.5
0
0.5
1
1.5
2
VCM (V)
TLV70x2
Figure 6-13. Hysteresis vs Temperature
Temp -40°C
Temp 25°C
Temp 125°C
8
VCC = 1.8 V
TLV70x2
Figure 6-14. Hysteresis vs VCM
14
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6.14 Typical Characteristics (continued)
TA = 25°C, VCC = 5 V, VEE = 0 V, VCM = VCC/2, CL = 15 pF
15
16
14
14
13
VHYST (mV)
VHYST (mV)
12
12
10
11
10
9
8
8
Temp -40°C
Temp 25°C
Temp 125°C
6
-0.5
0.5
1.5
VCM (V)
2.5
VCC = 3.3 V
Temp -40°C
Temp 25°C
Temp 125°C
7
6
-0.5
3.5
TLV70x2
0.5
1.5
2.5
VCM (V)
3.5
4.5
VCC = 5 V
Figure 6-15. Hysteresis vs VCM
5.5
TLV70x2
Figure 6-16. Hysteresis vs VCM
1.795
1000
100
1.785
1.78
10
VOH (V)
Input Bias Current (pA)
1.79
1
1.775
1.77
1.765
0.1
1.76
0.01
-40
-20
0
20
40
60
80
Temperature (°C)
100
120
1.755
0.1
140
tlv7
A.
VCC = 5 V
0.15
0.2
0.25
0.3
0.35
0.4
Output Source Current (mA)
VCC = 1.8 V
Figure 6-17. Input Bias Current vs Temperature
0.45
0.5
voh_
TLV703x
Figure 6-18. Output Voltage High vs Output Source Current
5
0.1
4.98
0.08
0.07
0.06
4.96
4.94
0.05
VOL (V)
4.92
VOH (V)
Temp -40°C
Temp 25°C
Temp 85°C
Temp 125°C
4.9
4.88
0.04
0.03
4.86
0.02
4.84
Temp -40°C
Temp 25°C
Temp 85°C
Temp 125°C
4.82
4.8
Temp -40°C
Temp 25°C
Temp 125°C
4.78
0
0.5
1
1.5
2
2.5
3
3.5
Output Source Current (mA)
VCC = 5 V
4
4.5
5
voh_
TLV703x
Figure 6-19. Output Voltage High vs Output Source Current
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0.01
0.1
0.2
0.3
Output Sink Current (mA)
0.4
0.5
vol_
VCC = 1.8 V
Figure 6-20. Output Voltage Low vs Output Sink Current
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6.14 Typical Characteristics (continued)
TA = 25°C, VCC = 5 V, VEE = 0 V, VCM = VCC/2, CL = 15 pF
50
0.5
VCC=3.5V
VCC=5.5V
0.3
0.2
40
ISC (mA)
VOL (V)
0.1
0.07
0.05
0.03
30
0.02
20
Temp -40°C
Temp 25°C
Temp 125°C
0.01
0.007
0.005
0.1
0.2
0.3 0.4 0.5 0.7 1
Output Sink Current (mA)
2
3
10
-40
4 5
-20
0
20
vol_
VCC = 5 V
40
60
80
Temperature (°C)
100
120
140
nisc
VCM = VCC / 2
Figure 6-21. Output Voltage Low vs Output Sink Current
Figure 6-22. Output Short-Circuit (Sink) Current vs Temperature
50
50
Vcc=3.5V
Vcc=5.5V
40
ISC (mA)
Isc (mA)
40
30
30
20
20
10
10
-40
Temp -40°C
Temp 25°C
Temp 125°C
0
-20
0
20
40
60
80
Temperature ( °C)
100
120
1
140
1.5
2
2.5
3
pisc
VCM = VCC / 2
3.5 4
VCC(V)
4.5
5
5.5
6
6.5
nisc
VCM = VCC / 2
TLV703x
Figure 6-24. Output Short Circuit (Sink) vs VCC
Figure 6-23. Output Short-Circuit (Source) Current vs
Temperature
0.6
50
45
40
0.5
30
ICC (PA)
Isc (mA)
35
25
20
15
0.3
10
VCC = 1V
VCC = 3V
VCC = 5V
Temp -40C
Temp 25C
Temp 125C
5
0
1
1.5
2
2.5
3
3.5 4
Vcc (V)
VCM = VCC / 2
4.5
5
5.5
6
6.5
TLV703x
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0.2
-40
-20
pisc
Figure 6-25. Output Short Circuit (Source) vs VCC
16
0.4
0
20
40
60
80
Temperature (°C)
100
VCM = VCC / 2
120
140
icc_
TLV70x1
Figure 6-26. ICC vs Temperature
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6.14 Typical Characteristics (continued)
TA = 25°C, VCC = 5 V, VEE = 0 V, VCM = VCC/2, CL = 15 pF
0.6
0.6
0.5
0.5
ICC (PA
ICC (PA)
0.4
0.3
0.4
0.2
0.3
Temp -40°C
Temp 25°C
Temp 125°C
0.1
VCC = 1.8V
VCC = 3.3V
VCC = 5.0V
0
1
2
3
4
5
0.2
-40
6
VCC (V)
-20
VCM = VCC / 2
0.6
20000
10000
5000
0.5
0.3
0.2
4.5
5.5
140
TLV70x2
VCM = VCC / 2
Fall Time
Rise Time
20
10
5
2
10 2030 50 100 200 5001000
10000
Load Capacitance (pF)
6.5
VCC (V)
VOD = 100 mV
TLV70x2
100000
tlv7
TLV703x Rise only
Figure 6-30. Rise/Fall Time vs Load Capacitance
Figure 6-29. ICC vs VCC
7
7
Temp -40°C
Temp 25°C
Temp 85°C
Temp 125°C
Temp -40°C
Temp 25°C
Temp 85°C
Temp 125°C
6
Propagation Delay (Ps)
6
Propagation Delay (Ps)
120
200
100
50
Temp -40°C
Temp 25°C
Temp 125°C
3.5
100
2000
1000
500
Rise/Fall Time (ns)
ICC (PA)
0.4
2.5
40
60
80
Temperature (°C)
Figure 6-28. ICC vs Temperature
Figure 6-27. ICC vs VCC
0.1
20
VCM = VCC / 2
TLV70x1
0
1.5
0
icc_
5
4
3
5
4
3
2
2
1
1
0
100
200
300
VOD (mV)
VCC = 3.3 V to 5 V
400
500
TLV703x
Figure 6-31. Propagation Delay (L-H) vs Input Overdrive
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0
100
tlv7
200
300
VOD (mV)
400
500
tlv7
VCC = 3.3 V to 5 V
Figure 6-32. Propagation Delay (H-L) vs Input Overdrive
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7 Detailed Description
7.1 Overview
The TLV703x and TLV704x are nano-power comparators with push-pull and open-drain outputs. Operating from
1.6 V to 6.5 V and consuming only 315 nA, the TLV703x and TLV704x are designed for portable and industrial
applications. The TLV703x and TLV704x are available in a variety of leadless and leaded packages to offer
significant board space saving in space-challenged designs.
7.2 Functional Block Diagram
VCC
IN+
+
IN-
-
OUT
Power-on-reset
Bias
VEE
7.3 Feature Description
The TLV703x and TLV704x devices are nanoPower comparators that are capable of operating at low voltages.
The TLV703x and TLV704x feature a rail-to-rail input stage capable of operating up to 100 mV beyond the VCC
power supply rail. The TLV703x (push-pull) and TLV704x (open-drain) also feature internal hysteresis.
7.4 Device Functional Modes
The TLV703x and TLV704x have a power-on-reset (POR) circuit. While the power supply (VS) is less than the
minimum supply voltage, either upon ramp-up or ramp-down, the POR circuitry is activated.
For the TLV703x, the POR circuit holds the output low (at VEE) while activated.
For the TLV704x, the POR circuit keeps the output high impedance (logical high) while activated.
When the supply voltage is greater than, or equal to, the minimum supply voltage, the comparator output reflects
the state of the differential input (VID).
18
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7.4.1 Inputs
The TLV703x and TLV704x input common-mode extends from VEE to 100 mV above VCC. The differential input
voltage (VID) can be any voltage within these limits. No phase inversion of the comparator output occurs when
the input pins exceed VCC and VEE.
The input of TLV703x and TLV704x is fault tolerant. It maintains the same high input impedance when VCC is
unpowered or ramping up. The input can be safely driven up to the specified maximum voltage (7 V) with VCC =
0 V or any value up to the maximum specified. The VCC is isolated from the input such that it maintains its value
even when a higher voltage is applied to the input.
The input bias current is typically 1 pA for input voltages between VCC and VEE. The comparator inputs are
protected from voltages below VEE by internal diodes connected to VEE. As the input voltage goes under VEE,
the protection diodes become forward biased and begin to conduct causing the input bias current to increase
exponentially. Input bias current typically doubles every 10°C temperature increases.
7.4.2 Internal Hysteresis
The device hysteresis transfer curve is shown in Figure 7-1. This curve is a function of three components: VTH,
VOS, and VHYST:
• VTH is the actual set voltage or threshold trip voltage.
• VOS is the internal offset voltage between VIN+ and VIN–. This voltage is added to VTH to form the actual trip
point at which the comparator must respond to change output states.
• VHYST is the internal hysteresis (or trip window) that is designed to reduce comparator sensitivity to noise
(7 mV for both TLV703x and TLV704x).
VTH + VOS - (VHYST / 2)
VTH + VOS
VTH + VOS + (VHYST / 2)
Figure 7-1. Hysteresis Transfer Curve
7.4.3 Output
The TLV703x features a push-pull output stage eliminating the need for an external pullup resistor. On the other
hand, the TLV704x features an open-drain output stage enabling the output logic levels to be pulled up to an
external source up to 6.5 V independent of the supply voltage.
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The TLV703x and TLV704x are nano-power comparators with reasonable response time. The comparators have
a rail-to-rail input stage that can monitor signals beyond the positive supply rail with integrated hysteresis. When
higher levels of hysteresis are required, positive feedback can be externally added. The push-pull output stage
of the TLV703x is optimal for reduced power budget applications and features no shoot-through current. When
level shifting or wire-ORing of the comparator outputs is needed, the TLV704x with its open-drain output stage
is well suited to meet the system needs. In either case, the wide operating voltage range, low quiescent current,
and small size of the TLV703x and TLV704x make these comparators excellent candidates for battery-operated
and portable, handheld designs.
8.1.1 Inverting Comparator With Hysteresis for TLV703x
The inverting comparator with hysteresis requires a three-resistor network that is referenced to the comparator
supply voltage (VCC), as shown in Figure 8-1. When VIN at the inverting input is less than VA, the output voltage
is high (for simplicity, assume VO switches as high as VCC). The three network resistors can be represented as
R1 || R3 in series with R2. Equation 1 defines the high-to-low trip voltage (VA1).
VA1 = VCC ´
R2
(R1 || R3) + R2
(1)
When VIN is greater than VA, the output voltage is low, very close to ground. In this case, the three network
resistors can be presented as R2 || R3 in series with R1. Use Equation 2 to define the low to high trip voltage
(VA2).
VA2 = VCC ´
R2 || R3
R1 + (R2 || R3)
(2)
Equation 3 defines the total hysteresis provided by the network.
DVA = VA1 - VA2
20
(3)
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+VCC
+5 V
R1
1 MW
VIN
5V
RLOAD
100 kW
VA
VO
VA2
VA1
0V
1.67 V
R3
1 MW
R2
1 MW
VO High
+VCC
R1
VIN
3.33 V
VO Low
+VCC
R3
R1
VA1
VA2
R2
R2
R3
Copyright © 2016, Texas Instruments Incorporated
Figure 8-1. TLV703x in an Inverting Configuration With Hysteresis
8.1.2 Noninverting Comparator With Hysteresis for TLV703x
A noninverting comparator with hysteresis requires a two-resistor network, as shown in Figure 8-2, and a voltage
reference (VREF) at the inverting input. When VIN is low, the output is also low. For the output to switch from low
to high, VIN must rise to VIN1. Use Equation 4 to calculate VIN1.
VIN1 = R1 ´
VREF
R2
+ VREF
(4)
When VIN is high, the output is also high. For the comparator to switch back to a low state, VIN must drop to VIN2
such that VA is equal to VREF. Use Equation 5 to calculate VIN2.
VIN2 =
VREF (R1 + R2) - VCC ´ R1
(5)
R2
The hysteresis of this circuit is the difference between VIN1 and VIN2, as shown in Equation 6.
DVIN = VCC ´
R1
R2
(6)
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+VCC
+5 V
VREF
+2.5 V
VO
VA
VIN
RLOAD
R1
330 kW
R2
1 MW
VO High
+VCC
VO Low
VIN1
5V
R2
R1
VA = VREF
VA = VREF
R1
R2
VO
VIN2
VIN1
0V
1.675 V
3.325 V
VIN
VIN2
Copyright © 2016, Texas Instruments Incorporated
Figure 8-2. TLV703x in a Noninverting Configuration With Hysteresis
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8.2 Typical Applications
8.2.1 Window Comparator
Window comparators are commonly used to detect undervoltage and overvoltage conditions. Figure 8-3 shows a
simple window comparator circuit.
3.3V
RPU
R1
UV_OV
+
MicroController
Sensor
R2
+
R3
Figure 8-3. TLV704x-Based Window Comparator
8.2.1.1 Design Requirements
For this design, follow these design requirements:
• Alert (logic low output) when an input signal is less than 1.1 V
• Alert (logic low output) when an input signal is greater than 2.2 V
• Alert signal is active low
• Operate from a 3.3-V power supply
8.2.1.2 Detailed Design Procedure
Configure the circuit as shown in Figure 8-3. Connect VCC to a 3.3-V power supply and VEE to ground. Make R1,
R2, and R3 each 10-MΩ resistors. These three resistors are used to create the positive and negative thresholds
for the window comparator (VTH+ and VTH–). With each resistor being equal, VTH+ is 2.2 V and VTH- is 1.1 V.
Large resistor values such as 10 MΩ are used to minimize power consumption. The sensor output voltage
is applied to the inverting and noninverting inputs of the two TLV704x devices. The TLV704x is used for its
open-drain output configuration. Using the TLV704x allows the two comparator outputs to be wire-ored together.
The respective comparator outputs are low when the sensor is less than 1.1 V or greater than 2.2 V. VOUT is high
when the sensor is in the range of 1.1 V to 2.2 V.
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8.2.1.3 Application Curve
VIN
VTH+ = 2.2 V
VTH± = 1.1 V
Time (usec)
VOUT
50
100
150
200
Time (usec)
Figure 8-4. Window Comparator Results
8.2.2 IR Receiver Analog Front End
A single TLV703x device can be used to build a complete IR receiver analog front end (AFE). The nanoamp
quiescent current and low input bias current make it possible to be powered with a coin cell battery, which could
last for years.
Vref
470 k
3V
R2
IR LED
470 k
R3
10M
R4
+
U1
Output to MCU
(Also to wake-up MCU)
±
10M
C1
VIN
VOUT
TLV7031
R1
0.01 F
GND
Copyright © 2017, Texas Instruments Incorporated
Figure 8-5. IR Receiver Analog Front End Using TLV703x
8.2.2.1 Design Requirements
For this design, follow these design requirements:
• Use a proper resistor (R1) value to generate an adequate signal amplitude applied to the inverting input of the
comparator.
• The low input bias current IB (2 pA typical) ensures that a greater value of R1 to be used.
• The RC constant value (R2 and C1) must support the targeted data rate (that is, 9,600 bauds) in order to
maintain a valid tripping threshold.
• The hysteresis introduced with R3 and R4 helps to avoid spurious output toggles.
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8.2.2.2 Detailed Design Procedure
The IR receiver AFE design is highly streamlined and optimized. R1 converts the IR light energy induced current
into voltage and applies to the inverting input of the comparator. The RC network of R2 and C1 establishes
a reference voltage Vref, which tracks the mean amplitude of the IR signal. The noninverting input is directly
connected to Vref through R3. R3 and R4 are used to produce a hysteresis to keep transitions free of spurious
toggles. To reduce the current drain from the coin cell battery, data transmission must be short and infrequent.
More technical details are provided in the TI TechNote Low Power Comparator for Signal Processing and
Wake-Up Circuit in Smart Meters (SNVA808).
8.2.2.3 Application Curve
1.8 V
VIN
1.2 V
4.0 V
VOUT
0.0 V
1.61 V
VREF
1.58 V
0.0
200.0 u
400.0 u
600.0 u
800.0 u
Time
Figure 8-6. IR Receiver AFE Waveforms
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8.2.3 Square-Wave Oscillator
A square-wave oscillator can be used as low-cost timing reference or system supervisory clock source.
Figure 8-7. Square-Wave Oscillator
8.2.3.1 Design Requirements
The square-wave period is determined by the RC time constant of the capacitor and resistor. The maximum
frequency is limited by the propagation delay of the device and the capacitance load at the output. The low input
bias current allows a lower capacitor value and larger resistor value combination for a given oscillator frequency,
which may help reduce BOM cost and board space.
8.2.3.2 Detailed Design Procedure
The oscillation frequency is determined by the resistor and capacitor values. The following section provides
details to calculate these component values.
Figure 8-8. Square-Wave Oscillator Timing Thresholds
First consider the output of figure Figure 8-7 is high, which indicates the inverted input VC is lower than the
noninverting input (VA). This causes the C1 to be charged through R4, and the voltage VC increases until it is
equal to the noninverting input. The value of VA at the point is calculated by Equation 7.
VA1
VCC u R 2
R 2 R 1 IIR 3
(7)
If R1 = R2= R3, then VA1 = 2 VCC/ 3
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At this time the comparator output trips pulling down the output to the negative rail. The value of VA at this point
is calculated by Equation 8.
VA 2
VCC (R 2IIR 3 )
R 1+ R 2IIR 3
(8)
If R1 = R2 = R3, then VA2 = VCC/3
The C1 now discharges though the R4, and the voltage VCC decreases until it reaches VA2. At this point, the
output switches back to the starting state. The oscillation period equals the time duration from 2 VCC / 3 to
VCC / 3 then back to 2 VCC / 3, which is given by R4C1 × ln2 for each trip. Therefore, the total time duration is
calculated as 2 R4C1 × ln2. The oscillation frequency can be obtained by Equation 9:
f
1/ 2 R4 u C1u In2
(9)
8.2.3.3 Application Curve
Figure 8-9 shows the simulated results of an oscillator using the following component values:
•
•
•
•
R1 = R2 = R3 = R4 = 100 kΩ
C1 = 100 pF, CL = 20 pF
V+ = 5 V, V– = GND
Cstray (not shown) from VA to GND = 10 pF
Figure 8-9. Square-Wave Oscillator Output Waveform
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8.2.4 Quadrature Rotary Encoder
A quadrature encoder for rotary motors/shafts utilizing a Tunneling Magnetoresitance (TMR) Rotation Sensor
can track the position of the motor shaft even when power is turned off, while the TLV7032 provides additional
hysteresis to prevent unwanted output toggling between quadrants. The TLV7032 can be used with other
sensing techniques as well, such as optical, capacitive, or inductive.
Figure 8-10. Quadrant Encoder Detector
8.2.4.1 Design Requirements
TMR Rotation Sensors general have two digital, binary outputs that are 90 degrees out of phase. The TLV7032
can be used to provide additional hysteresis to ensure there isn't any unwanted toggling of the output when
the sensors are between the transition points of two quadrants. The TLV7032 already provides 10mV of typical
internal hysteresis. By dividing down the output voltage from the rotation sensor using a voltage divider, the
internal hysteresis will be scaled up by the same voltage divider ratio.
Figure 8-11. Voltage Divider Equation
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8.2.4.2 Detailed Design Procedure
First, choose a target range of hysteresis to achieve. For this design example, 50mV of hysteresis will be the
target. Since the TLV7032 already has 10mV (typ) of internal hysteresis, the voltage output from the TMR
Rotation Sensor should be scaled down by a factor of 5. This way, the 10mV of internal hysteresis gets scaled
up by a factor of 5, resulting in 50mV of hysteresis. The minimum output HIGH level for the TMR Rotation
Sensor used in Figure 47 is 5.25 V. Since 5.25V will be the minimum output high value, it can be used to
substitute VIN from the Voltage Divider Equation in Figure 48. Since the voltage from the TMR rotation sensor
needs to be scaled down by a factor of 5, the equation in Figure 48 can be rewritten as:
The above equation can be solved for using standard resistor values, where R1 = 100kΩ, and R2 = 24.9kΩ. The
minimum voltage seen at the noninverting pins of the comparator when the output is HIGH will be 1.05V. To
make the device transition at 50% output high level, the inverting pins of the TLV7032 should be tied to a 0.525V
reference.
8.2.4.3 Application Curve
Figure 49 shows the TLV7032 achieving approximately 50mV of hysteresis using the following component
values:
• R1 = 100kΩ
• R2 = 24.9kΩ
• VREF (IN-) = 0.525V
Figure 8-12. DC Input Voltage Sweep
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9 Power Supply Recommendations
The TLV703x and TLV704x have a recommended operating voltage range (VS) of 1.6 V to 6.5 V. VS is
defined as VCC – VEE. Therefore, the supply voltages used to create VS can be single-ended or bipolar. For
example, single-ended supply voltages of 5 V and 0 V and bipolar supply voltages of +2.5 V and –2.5 V create
comparable operating voltages for VS. However, when bipolar supply voltages are used, it is important to realize
that the logic low level of the comparator output is referenced to VEE.
Output capacitive loading and output toggle rate will cause the average supply current to rise over the quiescent
current.
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10 Layout
10.1 Layout Guidelines
To reduce PCB fabrication cost and improve reliability, TI recommends using a 4-mil via at the center pad
connected to the ground trace or plane on the bottom layer.
TI recommends a power-supply bypass capacitor of 100 nF when supply output impedance is high, supply
traces are long, or when excessive noise is expected on the supply lines. Bypass capacitors are also
recommended when the comparator output drives a long trace or is required to drive a capacitive load.
Due to the fast rising and falling edge rates and high-output sink and source capability of the TLV703x and
TLV704x output stages, higher than normal quiescent current can be drawn from the power supply. Under this
circumstance, the system would benefit from a bypass capacitor across the supply pins.
10.2 Layout Example
Figure 10-1. Layout Example
The application report Designing and Manufacturing With TI's X2SON Packages (SCEA055) helps PCB
designers to achieve optimal designs.
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 Evaluation Module
An evaluation module (EVM) is available to assist in the initial circuit performance evaluation using the TLV70x1
device family. The TLV7011 Micro-Power Comparator Dip Adaptor Evaluation Module can be requested at the
Texas Instruments website through the product folder or purchased directly from the TI eStore.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation, see the following:
• Designing and Manufacturing With TI's X2SON Packages (SCEA055)
• Low Power Comparator for Signal Processing and Wake-Up Circuit in Smart Meters (SNVA808)
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TLV7031DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
1IE2
TLV7031DCKR
ACTIVE
SC70
DCK
5
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
19P
TLV7031DCKT
ACTIVE
SC70
DCK
5
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
19P
TLV7031DPWR
ACTIVE
X2SON
DPW
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
7K
TLV7032DDFR
ACTIVE
SOT-23-THIN
DDF
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
22KF
TLV7032DGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
7032
TLV7032DSGR
ACTIVE
WSON
DSG
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
1ZXH
TLV7034PWR
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TLV7034
TLV7034RTER
ACTIVE
WQFN
RTE
16
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TL7034
TLV7041DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
1IF2
TLV7041DCKR
ACTIVE
SC70
DCK
5
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
19Q
TLV7041DCKT
ACTIVE
SC70
DCK
5
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
19Q
TLV7041DPWR
ACTIVE
X2SON
DPW
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
7L
TLV7042DDFR
ACTIVE
SOT-23-THIN
DDF
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
22LF
TLV7042DGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
7042
TLV7042DSGR
ACTIVE
WSON
DSG
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
1ZZH
TLV7044PWR
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TLV7044
TLV7044RTER
ACTIVE
WQFN
RTE
16
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TL7044
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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