TLV709
SLVSGU2D – FEBRUARY 2023 – REVISED JANUARY 2024
TLV709 150-mA, 30-V, 3.2-μA Quiescent Current, Low-Dropout Linear Regulator
1 Features
3 Description
•
•
The TLV709 low-dropout (LDO) linear voltage
regulator is a low quiescent current device that
offers the benefits of a wide input voltage range
and low-power operation in miniaturized packaging.
The TLV709 is optimized to power microcontrollers
and other low power loads for battery-powered
applications.
2 Applications
Home and building automation
Retail automation and payment
Grid infrastructure
Medical applications
Lighting applications
The TLV709 is available in a 2.90mm × 1.60mm, 5pin SOT-23 (DBV) package for fixed and adjustable
outputs, and in a 4.50mm × 2.5mm, 3-pin SOT-89
(PK) package for fixed outputs.
Package Information
PACKAGE(1)
PART NUMBER
TLV709
(1)
(2)
-55°C
-40°C
6
0°C
25°C
85°C
125°C
PACKAGE SIZE(2)
DBV (SOT-23, 5)
2.9mm × 2.8mm
PK (SOT-89, 3)
4.5mm × 4.095mm
For more information, see the Mechanical, Packaging, and
Orderable Information.
The package size (length × width) is a nominal value and
includes pins, where applicable.
6.5
TLV70933
150°C
IN
5.5
12V
5
Li-Ion
Battery
Ground Current (A)
•
•
•
•
•
4.5
4
CIN
MCU
•
The TLV709 LDO supports a low dropout of typically
600mV at 100mA of load current. The low quiescent
current (3.2μA typically) does not vary across the
entire range of output load current (0mA to 150mA).
The TLV709 also features an internal soft-start to
lower the inrush current during start-up. The built-in
overcurrent limit protection helps protect the regulator
in the event of a load short or fault condition.
0.1µF
•
•
•
•
•
Input voltage range: 2.5V to 30V
Available output voltage options:
– Fixed: 1.2V to 5V
– Adjustable: 1.2V to 28V
Output current: Up to 150mA
Very-low IQ: 3.2μA at 150mA load current
Stable with output capacitor ≥ 0.47μF
Overcurrent protection
Packages:
– 4-pin SOT-89 (PK) (fixed configuration only)
– 5-pin SOT-23 (DBV) (both fixed and adjustable
configurations)
Operating junction temperature: –40°C to +125°C
OUT
GND
COUT
0.47µF
Typical Application
3.5
3
2.5
0
30
60
90
Output Current (mA)
120
150
VIN = 4.3V, VOUT = 3.3V
Quiescent Current vs Load Current
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLV709
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SLVSGU2D – FEBRUARY 2023 – REVISED JANUARY 2024
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Pin Configuration and Functions...................................3
5 Specifications.................................................................. 4
5.1 Absolute Maximum Ratings........................................ 4
5.2 ESD Ratings............................................................... 4
5.3 Recommended Operating Conditions.........................4
5.4 Thermal Information....................................................5
5.5 Electrical Characteristics.............................................6
5.6 Typical Characteristics................................................ 7
6 Detailed Description......................................................10
6.1 Overview................................................................... 10
6.2 Functional Block Diagrams....................................... 10
6.3 Feature Description...................................................11
6.4 Device Functional Modes..........................................12
7 Application and Implementation.................................. 13
2
7.1 Application Information............................................. 13
7.2 Typical Application.................................................... 13
7.3 Best Design Practices...............................................17
7.4 Power Supply Recommendations.............................17
7.5 Layout....................................................................... 17
8 Device and Documentation Support............................20
8.1 Device Support......................................................... 20
8.2 Documentation Support............................................ 20
8.3 Receiving Notification of Documentation Updates....20
8.4 Support Resources................................................... 20
8.5 Trademarks............................................................... 20
8.6 Electrostatic Discharge Caution................................21
8.7 Glossary....................................................................21
9 Revision History............................................................ 21
10 Mechanical, Packaging, and Orderable
Information.................................................................... 21
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4 Pin Configuration and Functions
IN
1
GND
2
NC
3
OUT
5
1
GND
2
NC
3
NC
4
Figure 4-1. DBV Package (Fixed), 5-Pin SOT-23
(Top View)
3
OUT
2
IN
1
GND
5
OUT
4
FB
Figure 4-2. DBV Package (Adjustable),
5-Pin SOT-23 (Top View)
GND
IN
IN
Figure 4-3. TLV709xxPKR PK Package (IN Tab),
3-Pin SOT-89 (Top View)
3
IN
2
GND
1
OUT
Figure 4-4. TLV709AxxPKR PK Package (GND Tab),
3-Pin SOT-89 (Top View)
Table 4-1. Pin Functions
PIN
DBV
(Fixed)
DBV
(Adj)
PK
(IN Tab)
PK
(GND Tab)
TYPE
GND
2
2
1
2, tab
—
IN
1
1
2, tab
3
I
Input supply pin. See the Recommended Operating Conditions table
and the Input and Output Capacitor Requirements section for more
information.
OUT
5
5
3
1
O
Output of the regulator. See the Recommended Operating Conditions
table and the Input and Output Capacitor Requirements section for more
information.
FB
—
4
—
—
I
In the adjustable configuration, this pin sets the output voltage with the
help of a feedback divider.
NC
3, 4
3
—
—
—
Not internally connected. This pin can be left open or tied to ground for
improved thermal performance.
NAME
DESCRIPTION
Ground pin.
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5 Specifications
5.1 Absolute Maximum Ratings
over operating temperature range (unless otherwise noted)(1) (2)
Voltage
MIN
MAX
VIN
–0.3
30
VOUT (for fixed device only)
2 × VOUT(typ)
or VIN + 0.3
–0.3
or 5.5
(whichever is
lower)
VOUT (for adjustable device only)
–0.3
VIN + 0.3
–0.3
2.4
VFB
Current
Peak output current
Temperature
(1)
(2)
UNIT
V
Internally limited
Junction, TJ
–40
150
Storage, Tstg
–65
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
All voltage values are with respect to the ground terminal.
5.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
±2000
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
5.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)
MIN
VIN
VOUT
MAX
1.205
28
1.205
5.0
Output current
Input capacitor(2)
COUT
Output capacitor(3)
TJ
Operating junction temperature
0
150
0.47
V
mA
µF
1
–40
UNIT
30
Output voltage (for fixed device only)
CIN
(3)
NOM
2.5
Output voltage (for adjustable device only)
IOUT
(1)
(2)
4
Input supply voltage
125
°C
All voltages are with respect to GND.
An input capacitor is not required for LDO stability. However, an input capacitance with an effective value of 0.1 μF minimum is
recommended to counteract the effect of source resistance and inductance, which may in some cases cause symptoms of systemlevel
instability such as ringing or oscillation, especially in the presence of load transients.
All capacitor values listed are the nominal value and the effective capacitance is assumed to derate to 50% of the nominal capacitor
value.
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5.4 Thermal Information
TLV709 (2)
THERMAL METRIC(1)
DBV
[SOT-23]
PK
[SOT-89]
AxxPK
[SOT-89]
5 PINS
4 PINS
4 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
195.7
131.7
72.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
88.2
65.8
121.4
°C/W
RθJB
Junction-to-board thermal resistance
40.7
32.4
37.3
°C/W
ψJT
Junction-to-top characterization parameter
11.2
69.8
29.6
°C/W
ψJB
Junction-to-board characterization parameter
40.5
96.2
36.8
°C/W
(1)
(2)
For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application
report.
Thermal performance results are based on the JEDEC standard of 2s2p PCB configuration. These thermal metric parameters can be
further improved by 35-55% based on thermally optimized PCB layout designs. See the analysis of the Impact of board layout on LDO
thermal performance application report.
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5.5 Electrical Characteristics
over operating junction temperature range (TJ = –40°C to 125°C), VIN = VOUT(nom) + 1V, IOUT = 100µA, and COUT = 1μF,
unless otherwise noted; typical values are at TJ = 25°C. (1)
PARAMETER
TEST CONDITIONS
Input voltage (2)
VIN
10mA ≤ IO < 50mA
3.0
30
50mA ≤ IO ≤ 150mA
3.5
30
28
1.205
VFB
Internal reference(2)
1.12
Output voltage Over VIN,
accuracy (1) (2) temp and
(3)
IOUT = 10mA
Ground pin current(1) (4)
(For A version only)
IGND
Ground pin current(1) (4)
(For non-A version only)
ΔVOUT (ΔIOUT)
Load regulation (1)
4
VOUT + 1.0V ≤ VIN ≤ 30V
IOUT = 10mA
-4
4
–2
2
IOUT = 0mA
3.2
4.2
100µA ≤ IOUT ≤ 150mA
3.2
4.8
100µA ≤ IOUT ≤ 150mA , TJ = –40°C
to 85°C
3.4
4.3
100µA ≤ IOUT ≤ 150mA
3.4
5.8
VOUT ≥ 3.3V, 100µA < IOUT < 10mA
1
VOUT ≥ 3.3V, 100µA < IOUT < 50mA
1
VOUT ≥ 3.3V, 100µA < IOUT < 150mA
1
2.5
0.02
0.05
Vn
Output noise
voltage
ICL
Output current limit
PSRR
Power-supply ripple rejection
VDO
(1)
(2)
(3)
(4)
(5)
Dropout voltage
VOUT(NOM) + 1V ≤ VIN ≤ 30V
%
μA
%/A
%/V
487
μVrms
577
VOUT = 0V, VIN ≥ 3.5V
160
1000
VOUT = 0V, VIN < 3.5V
90
1000
f = 100kHz, COUT = 10μF
60
VIN = VOUT(nom) – 0.1V, IOUT = 10mA
75
VIN = VOUT(nom) – 0.1V, IOUT = 50mA
400
VIN = VOUT(nom) – 0.1V, IOUT =
150mA
V
10
100µA ≤ IOUT ≤ 150mA , TJ = –40°C
to 85°C
BW = 10Hz to IOUT = 1mA
100kHz, COUT
IOUT = 50mA
= 10μF
V
3.2
100µA ≤ IOUT ≤ 150mA , VIN = 30V
(2)
UNIT
1.24
–4
Line regulation
ΔVOUT (ΔVIN)
1.205
VOUT + 1.0V ≤ VIN ≤ 30V
100µA ≤ IOUT ≤ 150mA
Over
VOUT + 1V ≤ VIN ≤ 30V
VIN , IOUT, and 100µA ≤ IOUT ≤ 150mA and TJ =
TJ = 25℃
25℃
Ground pin current(1) (4)
MAX
30
Output voltage range
(TLV709A01)
VOUT (5)
TYP
2.5
VOUT
Over VIN,
IOUT, and
temp
6
MIN
IO = 10mA
1000
mA
dB
150
mV
1600
TLV709 is stable and fuctional over the entire load current range from 0 mA to ICL.
Minimum VIN = VOUT + 1 V or the value shown for Input voltage in this table, whichever is greater.
For adjustable device, output accuracy excludes the tolerance and mismatch associated with external resistors used for setting up the
output voltage.
See Leakage null control circuit . The TLV709 family employs a leakage null control circuit. This circuit is active only if output current is
less than pass FET leakage current. The circuit is typically active when output load is less than 5 μA, VIN is greater than 18 V, and die
temperature is greater than 100°C.
Minimum VIN used for IOUT = 150 mA is VOUT + 1.6 V.
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5.6 Typical Characteristics
at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 1.0 V or 2.5 V (whichever is greater), VOUT(typ) = 3.3 V, IOUT = 1 mA,
CIN = 1 µF, and COUT = 1 µF (unless otherwise noted)
3.34
3.34
3.33
3.32
Output Voltage (V)
Output Voltage (V)
3.32
3.31
3.3
3.29
3.28
3.3
3.28
3.27
-55°C
-40°C
0°C
25°C
85°C
125°C
150°C
-55°C
-40°C
3.26
4
8
12
16
Input Voltage (V)
20
0°C
25°C
85°C
125°C
150°C
3.26
24
0
VOUT = 3.3 V, IOUT = 5 mA
30
60
Output Current (mA)
90
VIN = 4.3 V, VOUT = 3.3 V, 0 mA ≤ IOUT ≤ 100 mA
Figure 5-1. Line Regulation
Figure 5-2. Load Regulation
3.6
3.32
1mA
80mA
3.5
Output Voltage (V)
Output Voltage (V)
3.31
3.4
3.3
3.2
3.3
3.29
3.1
-55°C
-40°C
0°C
25°C
85°C
125°C
150°C
3.28
-55
3
0
30
60
90
Output Current (mA)
120
150
-25
5
35
65
95
Junction Temperature (C)
Figure 5-4. VOUT vs Temperature and IOUT
Figure 5-3. Load Regulation
120
2100
-55°C
-40°C
1800
Dropout Voltage (mV)
100
Dropout Voltage ( mV)
150
VIN = 4.3 V, VOUT = 3.3 V
VIN = 4.3 V, VOUT = 3.3 V, 0 mA ≤ IOUT ≤ 150 mA
80
60
40
20
0
2.5
125
-55°C
-40°C
2.6
2.7
0°C
25°C
2.8
2.9
3
Input Voltage (V)
85°C
125°C
3.1
150°C
0°C
25°C
85°C
125°C
150°C
1500
1200
900
600
300
0
3.2
3.3
0
30
60
90
Output Current (mA)
120
150
VOUT = 3.3 V
VOUT = 3.3 V, IOUT = 10 mA
Figure 5-6. VDO vs IOUT
Figure 5-5. VDO vs VIN
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5.6 Typical Characteristics (continued)
at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 1.0 V or 2.5 V (whichever is greater), VOUT(typ) = 3.3 V, IOUT = 1 mA,
CIN = 1 µF, and COUT = 1 µF (unless otherwise noted)
4.5
4.5
4
3.5
Ground Current (A)
Ground Current (A)
4
3.5
3
3
2.5
2
VOUT = 3.3V
1.5
1
2.5
-55°C
-40°C
0.5
2
-55
-25
5
35
65
95
Junction Temperature (C)
125
150
3
6
VIN = 4.3 V, VOUT = 3.3 V, IOUT = 0 mA, COUT = 1 μF
Figure 5-7. Ground Current vs Temperature
9
12
15
Input Voltage (V)
18
21
24
Figure 5-8. Ground Current vs VIN
-55°C
-40°C
0°C
25°C
85°C
125°C
150°C
250
5.5
Current Limit (mA)
Ground Current (A)
150°C
300
6
5
4.5
4
200
150
100
3.5
50
3
0
-55
2.5
0
30
60
90
Output Current (mA)
120
150
-25
100
Output Spectral Noise Density - V/Hz
1mA
50mA
90
80
70
60
50
40
30
20
10
1x10
2
3
4
1x10
1x10
1x10
f - Frequency (Hz)
5
95
125
1x10
6
1x10
7
20
10
5
150
1mA
50mA
2
1
0.5
0.2
0.1
0.05
0.02
0.01
0.005
Integrated Noise from
10Hz to 100KHz
1mA : 487VRMS
50mA : 577VRMS
0.002
0.001
1x101
VIN = 4.3 V, VOUT = 3.3 V, COUT = 10 μF
Figure 5-11. PSRR vs Frequency
35
65
Temperature (C)
Figure 5-10. ICL vs Temperature
Figure 5-9. Ground Current vs IOUT
0
1x101
5
VIN = 4.8 V, VOUT = 3.3 V
VIN = 4.3 V, VOUT = 3.3 V, COUT = 1 μF
PSRR - Power Supply Ripple Rejection - dB
85°C
125°C
VOUT = 3.3 V, IOUT = 0 mA, COUT = 1 μF
6.5
8
0°C
25°C
0
1x102
1x103
1x104
1x105
f - Frequency - Hz
1x106
1x107
VIN = 4.3 V, VOUT = 3.3 V, COUT = 10 μF
Figure 5-12. Output Noise (VN) vs Frequency
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5.6 Typical Characteristics (continued)
8.5
7
8
6
5
VIN
4
3
VOUT
2
150
VIN
VOUT 100
7.5
50
7
0
6.5
-50
6
-100
5.5
-150
5
-200
1
4.5
-250
0
4
4
6
8
10
12
14
t - Time - ms
16
18
20
0
22
50
VIN = 4.3 V, VOUT = 3.3 V, COUT = 10 μF, IOUT = 50 mA
300
-300
400
350
Figure 5-14. VIN Line Transient Response (4.3 V to 5.3 V)
160
600
400
140
IOUT
VOUT 400
350
600
IOUT
VOUT 400
120
200
300
200
100
0
250
0
200
-200
150
-400
100
-600
50
-800
-200
60
-400
VIN = 4.3 V
VOUT = 3.3 V
COUT = 10 F
dI/dt = 0.5 A/s
40
20
0
0
300
600
-600
-800
Output Current (mA)
80
AC Coupled Output Voltage - mV
IOUT - Output Current - mA
150
200
250
t - Time - s
VOUT = 3.3 V, COUT = 10 µF, ramp rate = 0.2 V/µs
Figure 5-13. Power-Up, Power-Down With VIN Ramp
0
600
-1000
900 1200 1500 1800 2100 2400 2700 3000
t - Time - s
VIN = 4.3 V, VOUT = 3.3 V, COUT = 10 µF, ramp rate = 0.5 A/µs
4
3
15
2
VIN
10
5
1
0
0
0
2000
4000
6000
t - Time - s
-1
10000
8000
VOUT = 5 V, COUT = 10 µF, ramp rate = 1.15 V/µs
2600
3000
-1000
3400
7
VIN
VOUT
IOUT = 50mA
COUT = 10F
dV/dt = 0.66V/s
25
VIN - Inout Voltage - V
20
COUT = 10F
dV/dt = 1.15V/s
1800
2200
Time (s)
Figure 5-16. IOUT Transient From 1 mA to 80 mA
VOUT - Output Voltage - V
25
1400
30
5
VOUT(1mA)
VOUT(50mA)
1000
VIN = 4.3 V, VOUT = 3.3 V, COUT = 10 µF ramp rate = 0.5 A/µs
Figure 5-15. IOUT Transient From 1 mA to 50 mA
30
VIN - Input Voltage - V
100
AC Coupled Output Voltage - mV
2
6
20
5
15
4
10
3
5
2
0
VOUT - Output Voltage - V
0
AC Coupled Output Voltage -mV
8
VIN - Input Voltage - V
VOUT - Output Voltage - V
VIN - Input Voltage - V
at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 1.0 V or 2.5 V (whichever is greater), VOUT(typ) = 3.3 V, IOUT = 1 mA,
CIN = 1 µF, and COUT = 1 µF (unless otherwise noted)
1
0
0.5
1
1.5
2
2.5
t - Time - ms
3
3.5
4
VOUT = 5 V, COUT = 10 µF, ramp rate = 0.66 V/µs
Figure 5-17. Dropout Exit Line Transient
(2.5 V to 14 V for VOUT = 5 V)
Figure 5-18. VIN Line Transient (5 V to 14 V for VOUT = 5 V)
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6 Detailed Description
6.1 Overview
The TLV709 low-dropout regulator (LDO) consumes only 3.2 μA (typ) of quiescent current across the entire
output current range, while offering a wide input voltage range and low-dropout voltage in small packaging. The
device, which operates over an input range of 2.5 V to 30 V, is stable with any output capacitor greater than
or equal to 1 μF. The low quiescent current across the complete load current range makes the TLV709 a great
choice for powering battery-operated applications. The TLV709 has an internal soft-start to control inrush current
into the output capacitor. This LDO also has overcurrent protection during a load-short or fault condition on the
output.
6.2 Functional Block Diagrams
V(IN)
V(OUT)
Current
Sense
Leakage Null
Control Circuit
R1
GND
+
–
ILIM
GND
FB
GND
R2
Bandgap
Reference
VREF = 1.205 V
GND
Figure 6-1. Functional Block Diagram: Adjustable Version
V(IN)
V(OUT)
Current
Sense
Leakage Null
Control Circuit
+
–
R1
GND
ILIM
GND
GND
R2
Bandgap
Reference
VREF = 1.205 V
GND
Figure 6-2. Functional Block Diagram: Fixed Version
10
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6.3 Feature Description
6.3.1 Wide Supply Range
This device has an operational input supply range of 2.5 V to 30 V, allowing for a wide range of applications. This
wide supply range is designed for applications that have either large transients or high DC voltage supplies.
6.3.2 Low Quiescent Current
This device only requires 3.2 μA (typical) of quiescent current across the complete load current range (0 mA to
150 mA) at room temperature and 4.8 μA (max) across the temperature range of –40°C to +125°C.
6.3.3 Dropout Voltage (VDO)
Dropout voltage (VDO) is defined as the input voltage minus the output voltage (VIN – VOUT) at the rated output
current (IRATED), where the pass transistor is fully on. IRATED is the maximum IOUT listed in the Recommended
Operating Conditions table. In dropout operation, the pass transistor is in the ohmic or triode region of operation,
and acts as a switch. The dropout voltage indirectly specifies a minimum input voltage greater than the nominal
programmed output voltage at which the output voltage is expected to stay in regulation. If the input voltage falls
to less than the value required to maintain output regulation, then the output voltage falls as well.
For a CMOS regulator, the dropout voltage is determined by the drain-source, on-state resistance (RDS(ON)) of
the pass transistor. Therefore, if the linear regulator operates at less than the rated current, the dropout voltage
for that current scales accordingly. Use Equation 1 to calculate the RDS(ON) of the device.
(1)
6.3.4 Current Limit
The device has an internal current limit circuit that protects the regulator during transient high-load current faults
or shorting events. The current limit is a brick-wall scheme. In a high-load current fault, the brick-wall scheme
limits the output current to the current limit (ICL). ICL is listed in the Electrical Characteristics table.
The output voltage is not regulated when the device is in current limit. When a current limit event occurs, the
device begins to heat up because of the increase in power dissipation. When the device is in brick-wall current
limit, the pass transistor dissipates power [(VIN – VOUT) × ICL]. For more information on current limits, see the
Know Your Limits application note.
Figure 6-3 shows a diagram of the current limit.
VOUT
Brickwall
VOUT(NOM)
IOUT
0V
0 mA
IRATED
ICL
Figure 6-3. Current Limit
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6.3.5 Leakage Null Control Circuit
This device has a built-in leakage-null control circuit. At high temperatures, pass-transistor leakage increases
and starts impacting the VOUT accuracy at no-load (IOUT = 0 mA) conditions. This leakage becomes more
aggravated with higher headroom across the LDO (VIN – VOUT). The TLV709 has a built-in leakage-null control
circuit that detects pass-transistor leakage and provides a ground discharge path for the leakage. This circuitry
helps the TLV709 maintain much tighter VOUT accuracy across wide VIN and temperature (–40°C to +125°C )
ranges.
6.4 Device Functional Modes
Table 6-1 provides a quick comparison between the normal and dropout modes of operation.
Table 6-1. Device Functional Mode Comparison
OPERATING MODE
PARAMETER
VIN
IOUT
Normal
VIN > VOUT(nom) + VDO
IOUT < ICL
Dropout
VIN < VOUT(nom) + VDO
IOUT < ICL
6.4.1 Normal Operation
The device regulates to the nominal output voltage under the following conditions:
•
•
•
The input voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(nom) + VDO)
The output current is less than the current limit (IOUT < ICL)
The device junction temperature is greater than –40°C and less than +125°C
6.4.2 Dropout Operation
If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other
conditions are met for normal operation, the device operates in dropout mode. In this mode, the output voltage
tracks the input voltage. During this mode, the transient performance of the device becomes significantly
degraded because the pass transistor is in the ohmic or triode region, and acts as a switch. Line or load
transients in dropout can result in large output voltage deviations.
When the device is in a steady dropout state (defined as when the device is in dropout, VIN < VOUT(NOM) + VDO,
directly after being in a normal regulation state, but not during start up), the pass transistor is driven into the
ohmic or triode region. When the input voltage returns to a value greater than or equal to the nominal output
voltage plus the dropout voltage (VOUT(NOM) + VDO), the output voltage can overshoot for a short period of time
while the device pulls the pass transistor back into the linear region.
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7 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
7.1 Application Information
The TLV709 LDO regulator is a good choice for battery-powered applications and is a good supply for low-power
microcontrollers, such as the MSP430, because of the device low IQ performance across load current range. The
ultra-low-supply current of the TLV709 maximizes efficiency at light loads and the high input voltage range and
flexibility of output voltage selection in adjustable configuration and fixed output levels makes the device optimal
as a supply in building automation and power tools.
7.2 Typical Application
TLV70933
VIN
IN
VOUT
OUT
0.1μF
0.47μF
GND
GND
Figure 7-1. Typical Application Circuit (Fixed-Voltage Version)
VIN
IN
0.1μF
VOUT
OUT
GND
CFB
0.47µF
R1
TLV70901
FB
R2
GND
GND
GND
Figure 7-2. TLV70901 Adjustable LDO Regulator Programming
NOTE: Dotted lines indicate an optional input capacitor. See the Recommended Operating Conditions table and the Input and Output
Capacitor Requirements section.
Table 7-1. Adjustable Output Voltage for Resistors R1 and R2
OUTPUT VOLTAGE (V)
R1 (MΩ)
R2 (MΩ)
1.8
0.499
1
2.8
1.33
1
5.0
3.16
1
7.2.1 Design Requirements
Table 7-2 summarizes the design requirements for Figure 7-1.
Table 7-2. Design Parameters
PARAMETER
DESIGN REQUIREMENT
Input voltage
12 V
Output voltage
3.3 V
Output current
100 mA
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7.2.2 Detailed Design Procedure
7.2.2.1 Setting VOUT for the TLV70901 Adjustable LDO
As illustrated in Figure 7-2, the TLV709 contains an adjustable version (the TLV70901) that sets the output
voltage using an external resistor divider. The output voltage operating range is 1.2 V to 28 V, and is calculated
using:
R1 ö
æ
VOUT = VREF ´ ç 1 +
÷
R2
è
ø
(2)
where:
•
VREF = 1.205 V (typical)
Choose resistors R1 and R2 to allow approximately 1.5 μA of current through the resistor divider. Lower value
resistors can be used for improved noise performance, but consume more power. Avoid higher resistor values
because leakage current into or out of FB across R1 / R2 creates an offset voltage that is proportional to VOUT
divided by VREF. The recommended design procedure is to choose R2 = 1 MΩ to set the divider current at
1.5 μA, and then calculate R1 using Equation 3:
V
R1 = VOUT − 1 × R2
REF
(3)
Figure 7-2 depicts this configuration.
7.2.2.2 External Capacitor Requirements
The device is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at the input
and output. Multilayer ceramic capacitors have become the industry standard for these types of applications and
are recommended, but must be used with good judgment. Ceramic capacitors that employ X7R-, X5R-, and
C0G-rated dielectric materials provide relatively good capacitive stability across temperature, whereas the use of
Y5V-rated capacitors is discouraged because of large variations in capacitance.
Regardless of the ceramic capacitor type selected, the effective capacitance varies with operating voltage
and temperature. Generally, expect the effective capacitance to decrease by as much as 50%. The input and
output capacitors listed in the Recommended Operating Conditions table account for an effective capacitance of
approximately 50% of the nominal value.
7.2.2.3 Input and Output Capacitor Requirements
Although an input capacitor is not required for stability, good analog design practice is to connect a capacitor
from IN to GND. This capacitor counteracts reactive input sources and improves transient response, input ripple,
and PSRR. Use an input capacitor if the source impedance is more than 0.5 Ω. A higher value capacitor can be
necessary if large, fast rise-time load or line transients are anticipated or if the device is located several inches
from the input power source.
Dynamic performance of the device is improved by using a larger output capacitor. The TLV709 requires
an output capacitor of 1 μF or larger (0.47 μF or larger capacitance) for stability and an equivalent series
resistance (ESR) between 0.001 Ω and 1 Ω. For best transient performance, use X5R- and X7R-type ceramic
capacitors because these capacitors have minimal variation in value and ESR over temperature. When choosing
a capacitor for a specific application, be mindful of the DC bias characteristics for the capacitor. Higher output
voltages cause a significant derating of the capacitor. Use an output capacitor within the range specified in the
Recommended Operating Conditions table for stability.
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7.2.2.4 Reverse Current
Excessive reverse current can damage this device. Reverse current flows through the intrinsic body diode of the
PMOS pass transistor instead of the normal conducting channel. At high magnitudes, this current flow degrades
the long-term reliability of the device.
Conditions where reverse current can occur are outlined in this section, all of which can exceed the absolute
maximum rating of VOUT ≤ VIN + 0.3 V. These conditions are:
•
•
•
If the device has a large COUT and the input supply collapses with little or no load current
The output is biased when the input supply is not established
The output is biased above the input supply
If reverse current flow is expected in the application, use external protection to protect the device. Reverse
current is not limited in the device, so external limiting is required if extended reverse voltage operation is
anticipated. Limit reverse current to 5% or less of the rated output current of the device in the event this current
cannot be avoided.
Figure 7-3 shows one approach for protecting the device.
Schottky Diode
Internal Body Diode
IN
OUT
CIN
COUT
GND
GND
GND
GND
Figure 7-3. Example Circuit for Reverse Current Protection Using a Schottky Diode
7.2.2.5 Feed-Forward Capacitor (CFF)
For the adjustable-voltage version device, a feed-forward capacitor (CFF) can be connected from the OUT pin
to the FB pin. CFF improves transient, noise, and PSRR performance, but is not required for regulator stability.
Recommended CFF values are listed in the Recommended Operating Conditions table. A higher capacitance
CFF can be used; however, the start-up time increases. For a detailed description of CFF tradeoffs, see the Pros
and Cons of Using a Feedforward Capacitor with a Low-Dropout Regulator application note.
CFF and R1 form a zero in the loop gain at frequency fZ, while CFF, R1, and R2 form a pole in the loop gain at
frequency fP. CFF zero and pole frequencies can be calculated from the following equations:
fZ = 1 / (2 × π × CFF × R1)
(4)
fP = 1 / (2 × π × CFF × (R1 || R2))
(5)
CFF ≥ 10 pF is required for stability if the feedback divider current is less than 5 μA. Equation 6 calculates the
feedback divider current.
IFB_Divider = VOUT / (R1 + R2)
(6)
To avoid start-up time increases from CFF, limit the product CFF × R1 < 50 µs.
For an output voltage of 1.205 V with the FB pin tied to the OUT pin, no CFF is used.
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7.2.2.6 Power Dissipation (PD)
Circuit reliability requires consideration of the device power dissipation, location of the circuit on the printed
circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator must have few
or no other heat-generating devices that cause added thermal stress.
To first-order approximation, power dissipation in the regulator depends on the input-to-output voltage difference
and load conditions. The following equation calculates power dissipation (PD).
PD = (VIN – VOUT) × IOUT
(7)
Note
Power dissipation can be minimized, and therefore greater efficiency can be achieved, by correct
selection of the system voltage rails. For the lowest power dissipation, use the minimum input voltage
required for correct output regulation.
For devices with a thermal pad, the primary heat conduction path for the device package is through the thermal
pad to the PCB. Solder the thermal pad to a copper pad area under the device. This pad area must contain an
array of plated vias that conduct heat to additional copper planes for increased heat dissipation.
The maximum power dissipation determines the maximum allowable ambient temperature (TA) for the device.
According to the following equation, power dissipation and junction temperature are most often related by the
junction-to-ambient thermal resistance (RθJA) of the combined PCB and device package and the temperature of
the ambient air (TA).
TJ = TA + (RθJA × PD)
(8)
Thermal resistance (RθJA) is highly dependent on the heat-spreading capability built into the particular PCB
design, and therefore varies according to the total copper area, copper weight, and location of the planes.
The junction-to-ambient thermal resistance listed in the Thermal Information table is determined by the JEDEC
standard PCB and copper-spreading area, and is used as a relative measure of package thermal performance.
As mentioned in the An empirical analysis of the impact of board layout on LDO thermal performance application
note, RθJA can be improved by 35% to 55% compared to the Thermal Information table value with the PCB
board layout optimization.
7.2.2.7 Estimating Junction Temperature
The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures
of the linear regulator when in-circuit on a typical PCB board application. These metrics are not thermal
resistance parameters and instead offer a practical and relative way to estimate junction temperature. These
psi metrics are determined to be significantly independent of the copper area available for heat-spreading.
The Thermal Information table lists the primary thermal metrics, which are the junction-to-top characterization
parameter (ψJT) and junction-to-board characterization parameter (ψJB). These parameters provide two methods
for calculating the junction temperature (TJ), as described in the following equations. Use the junction-to-top
characterization parameter (ψJT) with the temperature at the center-top of device package (TT) to calculate
the junction temperature. Use the junction-to-board characterization parameter (ψJB) with the PCB surface
temperature 1 mm from the device package (TB) to calculate the junction temperature.
TJ = TT + ψJT × PD
(9)
where:
•
•
16
PD is the dissipated power
TT is the temperature at the center-top of the device package
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TJ = TB + ψJB × PD
(10)
where:
•
TB is the PCB surface temperature measured 1 mm from the device package and centered on the package
edge
For detailed information on the thermal metrics and how to use them, see the Semiconductor and IC Package
Thermal Metrics application note.
7.3 Best Design Practices
Place at least one 0.47-µF capacitor as close as possible to the OUT and GND pins of the regulator.
Do not connect the output capacitor to the regulator using a long, thin trace.
Connect an input capacitor as close as possible to the IN and GND pins of the regulator for best performance.
Do not exceed the absolute maximum ratings.
7.4 Power Supply Recommendations
The TLV709 is designed to operate from an input voltage supply range between 2.5 V and 30 V. The input
voltage range provides adequate headroom in order for the device to have a regulated output. If the input supply
is noisy, additional input capacitors with low ESR can help improve the output noise performance.
7.5 Layout
7.5.1 Layout Guidelines
For best overall performance, place all circuit components on the same side of the printed circuit board (PCB)
and as near as practical to the respective LDO pin connections. Place ground return connections for the input
and output capacitors as close to the GND pin as possible, using wide, component-side, copper planes. Do
not use vias and long traces to create LDO circuit connections to the input capacitor, output capacitor, or the
resistor divider because this practice negatively affects system performance. This grounding and layout scheme
minimizes inductive parasitics, and thereby reduces load current transients, minimizes noise, and increases
circuit stability. A ground reference plane is also recommended and is either embedded in the PCB or located
on the bottom side of the PCB opposite the components. This reference plane serves to assure accuracy of the
output voltage and shield the LDO from noise.
7.5.1.1 Power Dissipation
To ensure reliable operation, worst-case junction temperature must not exceed 125°C. This restriction limits the
power dissipation the regulator can handle in any given application. To ensure the junction temperature is within
acceptable limits, calculate the maximum allowable dissipation, PD(max), and the actual dissipation, PD, which
must be less than or equal to PD(max).
Equation 11 determines the maximum-power-dissipation limit:
PD(max) =
TJ max - TA
RqJA
(11)
where:
•
•
•
TJmax is the maximum allowable junction temperature
RθJA is the thermal resistance junction-to-ambient for the package (see the Thermal Informationtable)
TA is the ambient temperature
Equation 12 calculates the regulator dissipation:
PD = (VIN - VOUT ) ´ IOUT
(12)
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7.5.2 Layout Examples
GND
R2
NC
GND
FB
TLV709A01DBV
CIN
VIN
R1
OUT
IN
COUT
VOUT
GND
Figure 7-4. Example Layout for the TLV709A01DBV
INPUT
GND
Tab
CIN
COUT
1
2
3
GND
OUTPUT
Figure 7-5. Example Layout for the TLV709xxPK (IN Tab)
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GND
Tab
CIN
COUT
1
2
3
INPUT
OUTPUT
Figure 7-6. Example Layout for the TLV709AxxPK (GND Tab)
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8 Device and Documentation Support
8.1 Device Support
8.1.1 Development Support
8.1.1.1 Evaluation Module
An evaluation module (EVM) is available to assist in the initial circuit performance evaluation using the TLV709.
The TPS71533EVM evaluation module (and related user's guide) can be requested at the TI website through the
product folders or purchased directly from the TI eStore.
8.1.1.2 Spice Models
Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of
analog circuits and systems. A SPICE model for the TLV709 is available through the product folders under Tools
& Software.
8.1.2 Device Nomenclature
Table 8-1. Device Nomenclature(1)
PRODUCT
TLV709AxxDBVz
(1)
VOUT
In the SOT-23 (DBV) package:
XX is the nominal output voltage (for example, 33 = 3.3 V, 50 = 50 V, 01 = Adjustable).
Z is the package quantity.
TLV709xxPKz
In the SOT-89 (PK) package with an IN tab:
XX is the nominal output voltage (for example, 33 = 3.3 V, 50 = 50 V).
Z is the package quantity.
TLV709AxxPKz
In the SOT-89 (PK) package with a GND tab:
XX is the nominal output voltage (for example, 33 = 3.3 V, 50 = 50 V).
Z is the package quantity.
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
8.2 Documentation Support
8.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, TPS71533EVM LDO Regulator Evaluation Module user guide
8.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Notifications to register and receive a weekly digest of any product information that has changed. For change
details, review the revision history included in any revised document.
8.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
8.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
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8.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
8.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
9 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (November 2023) to Revision D (January 2024)
Page
• Updated ground pin current parameter for non-A version devices.....................................................................6
Changes from Revision B (June 2023) to Revision C (November 2023)
Page
• Added AxxPK column to Thermal Information table........................................................................................... 5
• Changed title of Example Layout for the TLV70901DBV figure to Example Layout for the TLV709A01DBV . 18
10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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20-Jan-2024
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
PTLV709A33DBVR
ACTIVE
SOT-23
DBV
5
3000
TBD
Call TI
Call TI
-40 to 125
TLV70933PKR
ACTIVE
SOT-89
PK
3
1000
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 125
NS
Samples
TLV70950PKR
ACTIVE
SOT-89
PK
3
1000
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 125
NV
Samples
TLV709A01DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
2V8F
Samples
TLV709A33DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
2V6F
Samples
TLV709A33PKR
ACTIVE
SOT-89
PK
3
1000
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 125
NT
Samples
TLV709A50DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
2V7F
Samples
TLV709A50PKR
ACTIVE
SOT-89
PK
3
1000
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 125
NW
Samples
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
