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TLV733P
SBVS235C – OCTOBER 2014 – REVISED JULY 2019
TLV733P Capacitor-Free, 300-mA, Low-Dropout Regulator
in 1-mm × 1-mm X2SON Package
1 Features
3 Description
•
•
•
•
The TLV733 series of low-dropout linear regulators
(LDOs) are ultra-small, low quiescent current LDOs
that can source 300 mA with good line and load
transient performance. These devices provide a
typical accuracy of 1%.
1
•
•
•
•
•
•
Input Voltage Range: 1.4 V to 5.5 V
Stable Operation With or Without Capacitors
Foldback Overcurrent Protection
Packages:
– 1.0-mm × 1.0-mm X2SON (4)
– SOT-23 (5)
Very Low Dropout: 125 mV at 300 mA (3.3 VOUT)
Accuracy: 1% typical, 1.4% maximum
Low IQ: 34 µA
Available in Fixed-Output Voltages:
1.0 V to 3.3 V
High PSRR: 50 dB at 1 kHz
Active Output Discharge
The TLV733 provides an active pull-down circuit to
quickly discharge output loads when disabled.
2 Applications
•
•
•
•
•
•
The TLV733 series is designed with a modern
capacitor-free architecture to ensure stability without
an input or output capacitor. The removal of the
output capacitor allows for a very small solution size,
and can eliminate inrush current at startup. However,
the TLV733 series is also stable with ceramic output
capacitors if an output capacitor is necessary. The
TLV733 also provides foldback current control during
device power-up and enabling if an output capacitor
is used. This functionality is especially important in
battery-operated devices.
Tablets
Smartphones
Notebook and Desktop Computers
Portable Industrial and Consumer Products
WLAN and Other PC Add-On Cards
Camera Modules
The TLV733 series is available in standard DBV
(SOT-23) and DQN (X2SON) packages.
Device Information(1)
PART NUMBER
TLV733P
PACKAGE
BODY SIZE (NOM)
SOT-23 (5)
2.90 mm × 1.60 mm
X2SON (4)
1.00 mm × 1.00 mm
(1) For all available packages, see the package option addendum
at the end of the data sheet.
Typical Application Circuit
Dropout Voltage vs Output Current
180
TLV733
CIN
EN
Optional
ON
OFF
OUT
140
COUT
GND
VOUT = 3.3 V
VOUT = 1.8 V
160
120
Optional
VDO (mV)
IN
100
80
60
40
20
0
0
30
60
90
120 150 180
IOUT (mA)
210
240
270
300
D020
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLV733P
SBVS235C – OCTOBER 2014 – REVISED JULY 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
4
5
6.1
6.2
6.3
6.4
6.5
6.6
5
5
5
5
6
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 13
7.1
7.2
7.3
7.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
13
13
14
15
8
Application and Implementation ........................ 16
8.1 Application Information............................................ 16
8.2 Typical Applications ............................................... 18
9 Power Supply Recommendations...................... 20
10 Layout................................................................... 20
10.1 Layout Guidelines ................................................. 20
10.2 Layout Examples................................................... 20
11 Device and Documentation Support ................. 21
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Device Support ....................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
21
21
21
21
21
21
22
12 Mechanical, Packaging, and Orderable
Information ........................................................... 22
4 Revision History
Changes from Revision B (November 2015) to Revision C
Page
•
Changed description of EN pin from 0.9 V to VEN(HI) and from 0.35 V to VEN(LO) .................................................................. 4
•
Deleted typical specifications from VEN(HI) and VEN(LO) parameters ....................................................................................... 6
•
Added maximum specification to ILIM parameter ................................................................................................................... 6
•
Changed Shutdown and Output Enable title from Shutdown and changed first paragraph................................................. 14
•
Added DBV package to last paragraph of Power Dissipation section.................................................................................. 17
•
Added (3) to Device Nomenclature table ............................................................................................................................. 21
Changes from Revision A (December 2014) to Revision B
Page
•
Changed Low Dropout Feature bullet value from 122 mV to 125 mV to match value in Electrical Characteristics ............. 1
•
Changed VOUT labels on front page plot ................................................................................................................................. 1
•
Changed min junction temperature value from –55 to –40 in Absolute Maximum Ratings table .......................................... 5
•
Changed max junction temperature value from 160 to 150 in Absolute Maximum Ratings table ........................................ 5
•
Changed max storage temperature value from 150 to 160 in Absolute Maximum Ratings table.......................................... 5
•
Added test condition to line regulation parameter in Electrical Characteristics table............................................................. 6
•
Changed unit for line regulation parameter from mV/V to mV ............................................................................................... 6
•
Added test condition to load regulation parameter in Electrical Characteristics table .......................................................... 6
Changes from Original (October 2014) to Revision A
Page
•
Changed top page header information for data sheet to reflect device family instead of individual devices......................... 1
•
Changed Input Voltage Range Features bullet to be first in list ............................................................................................. 1
•
Changed Typical Application Circuit on front page; corrected error in optional capacitor identification ................................ 1
•
Changed format of I/O column contents and order of packages in Pin Functions table ....................................................... 4
•
Moved storage temperature range specification to Absolute Maximum Ratings table ......................................................... 5
•
Changed Handling Ratings table title to ESD Ratings, updated table format ........................................................................ 5
•
Added new first row to the VDO parameter in the Electrical Characteristics table .................................................................. 6
2
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TLV733P
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SBVS235C – OCTOBER 2014 – REVISED JULY 2019
•
Changed condition text for Figure 34 .................................................................................................................................. 17
•
Added Evaluation Module subsection ................................................................................................................................. 21
•
Deleted Related Links section ............................................................................................................................................. 21
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TLV733P
SBVS235C – OCTOBER 2014 – REVISED JULY 2019
www.ti.com
5 Pin Configuration and Functions
DBV Package
5-Pin SOT-23
Top View
IN
1
GND
2
EN
3
DQN Package
4-Pin 1-mm × 1-mm X2SON
Top View
5
OUT
4
NC
IN
EN
4
3
1
2
OUT
GND
Pin Functions
PIN
NO.
NAME
DQN
I/O
DESCRIPTION
Enable pin. Drive EN greater than VEN(HI) to turn on the regulator.
Drive EN less than VEN(LO) to put the LDO into shutdown mode.
EN
3
3
I
GND
2
2
—
IN
4
1
I
NC
N/A
4
—
No internal connection
OUT
1
5
O
Regulated output voltage pin. For best transient response, use a small 1-μF
ceramic capacitor from this pin to ground.
See the Input and Output Capacitor Selection section for more details.
—
—
The thermal pad is electrically connected to the GND node.
Connect to the GND plane for improved thermal performance.
Thermal pad
4
DBV
Ground pin
Input pin. A small capacitor is recommended from this pin to ground.
See the Input and Output Capacitor Selection section for more details.
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SBVS235C – OCTOBER 2014 – REVISED JULY 2019
6 Specifications
6.1 Absolute Maximum Ratings
over operating junction temperature range (unless otherwise noted); all voltages are with respect to GND (1)
Voltage
Current
MIN
MAX
VIN
–0.3
6.0
VEN
–0.3
VIN + 0.3
VOUT
–0.3
3.6
IOUT
V
Internally limited
Output short-circuit duration
A
Indefinite
Temperature
(1)
UNIT
Operating junction, TJ
–40
150
Storage, Tstg
–65
160
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
Input range, VIN
1.4
5.5
V
Output range, VOUT
1.0
3.3
V
Output current, IOUT
0
300
mA
Enable range, VEN
0
VIN
V
–40
125
°C
Junction temperature, TJ
6.4 Thermal Information
TLV733P
THERMAL METRIC (1)
DQN (X2SON)
DBV (SOT-23)
UNIT
4 PINS
5 PINS
RθJA
Junction-to-ambient thermal resistance
218.6
228.4
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
164.8
151.5
°C/W
RθJB
Junction-to-board thermal resistance
164.9
55.8
°C/W
ψJT
Junction-to-top characterization parameter
5.6
31.4
°C/W
ψJB
Junction-to-board characterization parameter
163.9
54.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
131.4
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SBVS235C – OCTOBER 2014 – REVISED JULY 2019
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6.5 Electrical Characteristics
At operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA,
VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted). All typical values at TJ = 25°C.
PARAMETER
VIN
TEST CONDITIONS
MIN
Input voltage
DC output accuracy
UVLO
Undervoltage lockout
ΔVO(ΔVI)
Line regulation
ΔVO(ΔIO)
Load regulation
Dropout voltage (1)
VDO
TYP
1.4
TJ = 25°C
–40°C ≤ TJ ≤ +125°C
5.5
–1%
1%
–1.4%
1.4%
VIN rising
1.3
VIN falling
1.25
ΔVI = VIN(nom) to VIN(nom) + 1
1
DQN package
16
DBV package
25
ΔIO = 1 mA to
300 mA
VOUT = 0.98 ×
VOUT(nom),
IOUT = 300 mA
MAX
1.4
V
V
mV
mV
VOUT = 1.1 V, –40°C ≤ TJ ≤ 85°C
460
1.2 V ≤ VOUT < 1.5 V, –40°C ≤ TJ ≤ 85°C
420
1.5 V ≤ VOUT < 1.8 V, –40°C ≤ TJ ≤ 85°C
370
1.8 V ≤ VOUT < 2.5 V, –40°C ≤ TJ ≤ 85°C
270
2.5 V ≤ VOUT < 3.3 V, –40°C ≤ TJ ≤ 85°C
UNIT
260
VOUT = 3.3 V, –40°C ≤ TJ ≤ 85°C
125
220
1.2 V ≤ VOUT < 1.5 V, –40°C ≤ TJ ≤ 125°C
450
1.5 V ≤ VOUT < 1.8 V, –40°C ≤ TJ ≤ 125°C
400
1.8 V ≤ VOUT < 2.5 V, –40°C ≤ TJ ≤ 125°C
300
2.5 V ≤ VOUT < 3.3 V, –40°C ≤ TJ ≤ 125°C
290
VOUT = 3.3 V, –40°C ≤ TJ ≤ 125°C
mV
125
270
IGND
Ground pin current
IOUT = 0 mA
34
60
µA
ISHDN
Shutdown current
VEN ≤ 0.35 V, 2.0 V ≤ VIN ≤ 5.5 V, TJ = 25°C
0.1
1
µA
f = 100 Hz
68
PSRR
Power-supply
rejection ratio
VOUT = 1.8 V,
IOUT = 300 mA
f = 10 kHz
35
f = 100 kHz
28
Vn
Output noise voltage
VEN(HI)
EN pin high voltage
(enabled)
VEN(LO)
EN pin low voltage
(disabled)
IEN
EN pin current
tSTR
Startup time
Pull-down resistor
ILIM
Output current limit
IOS
Short-circuit current
limit
Tsd
Thermal shutdown
(1)
6
BW = 10 Hz to 100 kHz, VOUT = 1.8 V, IOUT = 10 mA
dB
120
µVRMS
0.9
V
0.35
VEN = 5.5 V
0.01
Time from EN assertion to 98% × VOUT(nom), VOUT = 1.0
V, IOUT = 0 mA
250
Time from EN assertion to 98% × VOUT(nom), VOUT = 3.3
V, IOUT = 0 mA
800
VIN = 2.3 V
120
V
µA
µs
360
Ω
700
VOUT shorted to GND, VOUT = 1.0 V
150
VOUT shorted to GND, VOUT = 3.3 V
170
Shutdown, temperature increasing
160
Reset, temperature decreasing
140
mA
mA
°C
Dropout voltage for the TLV73310P is not valid at room temperature. The device engages undervoltage lockout (VIN < UVLOFALL) before
the dropout condition is met.
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6.6 Typical Characteristics
at operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA,
VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted)
1.03
1.004
TJ = -40 qC
TJ = 0 qC
TJ = 25 qC
TJ = 85 qC
TJ = 125 qC
1.02
0.996
VOUT (V)
VOUT (V)
1.01
TJ = -40 qC
TJ = 0 qC
TJ = 25 qC
TJ = 85 qC
TJ = 125 qC
1
1
0.99
0.992
0.988
0.98
0.984
0.97
0.98
0.96
0.976
0
50
100
150
200
Current (mA)
250
300
0
50
TLV73310PDBV
Figure 1. 1.0-V Load Regulation vs IOUT and Temperature
250
300
D005
Figure 2. 1.0-V Load Regulation vs IOUT and Temperature
1.8
TJ = -40 qC
TJ = 0 qC
TJ = 25 qC
TJ = 85 qC
TJ = 125 qC
1.808
TJ = -40 qC
TJ = 0 qC
TJ = 25 qC
TJ = 85 qC
TJ = 125 qC
1.797
1.794
VOUT (V)
1.8
VOUT (V)
150
200
Current (mA)
TLV73310PDQN
1.816
1.792
1.784
1.791
1.788
1.776
1.785
1.768
1.782
1.76
1.779
0
50
100
150
200
Current (mA)
250
300
0
50
100
D002
TLV73318PDBV
150
200
Current (mA)
250
300
D006
TLV73318PDQN
Figure 3. 1.8-V Load Regulation vs IO and Temperature
Figure 4. 1.8-V Load Regulation vs IOUT and Temperature
3.345
3.32
TJ = -40 qC
TJ = 0 qC
TJ = 25 qC
TJ = 85 qC
TJ = 125 qC
3.33
TJ = -40 qC
TJ = 0 qC
TJ = 25 qC
TJ = 85 qC
TJ = 125 qC
3.312
3.304
VOUT (V)
3.315
VOUT (V)
100
D001
3.3
3.285
3.296
3.288
3.27
3.28
3.255
3.272
3.24
3.264
0
50
100
150
200
Current (mA)
250
300
0
D003
TLV73333PDBV
50
100
150
200
Current (mA)
250
300
D007
TLV73333PDQN
Figure 5. 3.3-V Load Regulation vs IOUT and Temperature
Figure 6. 3.3-V Load Regulation vs IOUT and Temperature
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Typical Characteristics (continued)
at operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA,
VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted)
390
400
TJ = -40 qC
TJ = 0 qC
TJ = 25 qC
TJ = 85 qC
TJ = 125 qC
350
330
300
VDO (mV)
VDO (mV)
300
TJ = -40 qC
TJ = 0 qC
TJ = 25 qC
TJ = 85 qC
TJ = 125 qC
360
250
200
270
240
210
180
150
150
120
100
90
60
50
0
30
60
90
120 150 180
Current (mA)
210
240
270
0
300
30
60
90
D024
TLV73312PDBV
210
240
270
300
D025
TLV73312PDQN
Figure 7. 1.2-V Dropout Voltage vs IOUT and Temperature
Figure 8. 1.2-V Dropout Voltage vs IOUT and Temperature
300
275
TJ = -40 qC
TJ = 0 qC
TJ = 25 qC
TJ = 85 qC
TJ = 125 qC
250
225
200
TJ = -40 qC
TJ = 0 qC
TJ = 25 qC
TJ = 85 qC
TJ = 125 qC
250
200
175
VDO (mV)
VDO (mV)
120 150 180
Current (mA)
150
125
100
150
100
75
50
50
25
0
0
0
30
60
90
120 150 180
Current (mA)
210
240
270
300
0
30
60
90
D008
TLV73318PDBV
Figure 9. 1.8-V Dropout Voltage vs IOUT and Temperature
240
270
300
D010
Figure 10. 1.8-V Dropout Voltage vs IOUT and Temperature
300
TJ = -40 qC
TJ = 0 qC
TJ = 25 qC
TJ = 85 qC
TJ = 125 qC
250
TJ = -40 qC
TJ = 0 qC
TJ = 25 qC
TJ = 85 qC
TJ = 125 qC
250
200
VDO (mV)
200
VDO (mV)
210
TLV73318PDQN
300
150
150
100
100
50
50
0
0
0
30
60
90
120 150 180
Current (mA)
210
240
270
300
0
D009
TLV73333PDBV
30
60
90
120 150 180
Current (mA)
210
240
270
300
D011
TLV73333PDQN
Figure 11. 3.3-V Dropout Voltage vs IOUT and Temperature
8
120 150 180
Current (mA)
Figure 12. 3.3-V Dropout Voltage vs IOUT and Temperature
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Typical Characteristics (continued)
at operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA,
VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted)
1.816
70
TJ = -40qC
TJ = 0qC
TJ = 25qC
TJ = 85qC
TJ = 125qC
1.814
1.812
60
55
1.808
IGND (PA)
VOUT (V)
1.81
TJ = -40qC
TJ = 0qC
TJ = 25qC
TJ = 85qC
TJ = 125qC
65
1.806
1.804
50
45
40
1.802
1.8
35
1.798
30
1.796
25
2
2.5
3
3.5
4
VIN (V)
4.5
5
5.5
0
30
60
90
120 150 180
IOUT (mA)
D019
210
240
270
300
D012
TLV73318PDBV
Figure 13. 1.8-V Regulation vs VIN (Line Regulation) and
Temperature
Figure 14. Ground Pin Current vs IOUT and Temperature
100
40
TJ = -40qC
TJ = 0qC
TJ = 25qC
TJ = 85qC
TJ = 125qC
TJ = 25qC
35
10
25
ISHDN (PA)
IGND (PA)
30
20
15
1
0.1
10
5
0
0.5
0.01
1
1.5
2
2.5
3
3.5
VIN (V)
4
4.5
5
0
5.5
D013
1
2
3
VIN (V)
4
5
6
D015
IOUT = 0 mA
Figure 15. Ground Pin Current vs VIN
Figure 16. Shutdown Current vs VIN and Temperature
1
0.675
VEN(LO)
VEN(HI)
0.9
0.625
0.8
0.6
0.7
0.575
0.6
VOUT (V)
Enable Threshold (V)
0.65
0.55
0.525
0.5
0.4
0.5
0.3
0.475
0.2
0.45
0.1
0.425
-40
-20
0
20
40
60
TJ (qC)
80
100
120
140
D014
TJ = -40°C
TJ = 0°C
TJ = 25°C
TJ = 85°C
TJ = 125°C
0
150 200 250 300 350 400 450 500 550 600 650 700
Output Current (mA)
D023
TLV73310PDBV
Figure 17. Enable Threshold vs Temperature
Figure 18. 1.0-V Foldback Current Limit vs
IOUT and Temperature
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Typical Characteristics (continued)
at operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA,
VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted)
2
3.5
1.75
3
2.5
1.25
VOUT (V)
VOUT (V)
1.5
1
2
1.5
0.75
TJ = -40°C
TJ = 0°C
TJ = 25°C
TJ = 85°C
TJ = 125°C
0.5
0.25
0
150
200
250
300
350
400
Output Current (mA)
450
TJ = -40°C
TJ = 0°C
TJ = 25°C
TJ = 85°C
TJ = 125°C
1
0.5
0
150
500
200
250
D021
TLV73318PDBV
D022
10
No Output Capacitor
1-PF Output Capacitor
70
VOUT = 1 V
VOUT = 1.8 V
VOUT = 3.3 V
Noise Density (PV/—Hz)
60
PSRR (dB)
500
Figure 20. 3.3-V Foldback Current Limit vs
IOUT and Temperature
80
50
40
30
20
10
1
0.1
0.01
100
1k
10k
Frequency (Hz)
100k
1M
0.005
10
D017
TLV73318PDQN, IOUT = 300 mA
100
1k
10k
Frequency (Hz)
100k
1M
D016
IOUT = 300 mA
Figure 21. Power-Supply Rejection Ratio vs Frequency
Figure 22. Output Spectral Noise Density
VIN (2 V/div)
VIN (2 V/div)
VOUT (1 V/div,
AC Coupled)
VOUT (1 V/div,
AC Coupled)
Time (20 µs/div)
Time (20 µs/div)
TLV73318PDBV, IOUT = 10 mA, 1-µF output capacitor
TLV73318PDBV, IOUT = 300 mA, 1-µF output capacitor
Figure 23. Line Transient
10
450
TLV73333PDBV
Figure 19. 1.8-V Foldback Current Limit vs
IOUT and Temperature
0
10
300
350
400
Output Current (mA)
Figure 24. Line Transient
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Typical Characteristics (continued)
at operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA,
VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted)
VOUT (200 mV/div,
AC Coupled)
VOUT (200 mV/div,
AC Coupled)
ILOAD (100 mA/div)
ILOAD (100 mA/div)
Time (20 µs/div)
Time (20 µs/div)
TLV73310PDBV, VIN = 2.0 V, 1-µF output capacitor, output
current slew rate = 0.25 A/µs
TLV73310PDBV, VIN = 2.0 V, no output capacitor, output current
slew rate = 0.25 A/µs
Figure 25. 1.0-V, 50-mA to 300-mA Load Transient
Figure 26. 1.0 V, 50-mA to 300-mA Load Transient
VOUT (100 mV/div,
AC Coupled)
VOUT (100 mV/div,
AC coupled)
ILOAD (100 mA/div)
ILOAD (200 mA/div)
Time (20 µs/div)
Time (50 µs/div)
TLV73333PDBV, VIN = 3.8 V,1-µF output capacitor, output current
slew rate = 0.25 A/µs
TLV73333PDBV, VIN = 3.8 V, no output capacitor, output current
slew rate = 0.25 A/µs
Figure 27. 3.3 V, 50-mA to 300-mA Load Transient
Figure 28. 3.3 V, 50-mA to 300-mA Load Transient
VEN (500 mV/div)
VIN (1 V/div)
VOUT (1 V/div)
ILOAD (200 mA/div)
VOUT (500 mV/div)
Time (100 µs/div)
Time (100 µs/div)
TLV73318PDBV, RL = 6.2 Ω, VEN = VIN, 1-µF output capacitor
TLV73318PDBV, RL = 6.2 Ω, 1-µF output capacitor
Figure 29. VIN Power-Up and Power-Down
Figure 30. Startup with EN
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Typical Characteristics (continued)
at operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA,
VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted)
VOUT (500 mV/div)
VEN (500 mV/div)
VOUT (500 mV/div)
ILOAD (200 mA/div)
Time (100 µs/div)
Time (100 µs/div)
TLV73318PDBV, IOUT = 300 mA, 1-µF output capacitor
TLV73318PDBV, 1-µF output capacitor
Figure 31. Shutdown Response with Enable
12
Figure 32. Foldback Current Limit Response
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7 Detailed Description
7.1 Overview
The TLV733 belongs to a new family of next-generation, low-dropout regulators (LDOs). These devices consume
low quiescent current and deliver excellent line and load transient performance. These characteristics, combined
with low noise, good PSRR with low dropout voltage, make this family of devices ideal for portable consumer
applications.
This family of regulators offers foldback current limit, shutdown, and thermal protection. The operating junction
temperature for this family of devices is –40°C to 125°C.
7.2 Functional Block Diagram
IN
OUT
Current
Limit
Thermal
Shutdown
UVLO
EN
120 W
Bandgap
Logic
TLV733
GND
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7.3 Feature Description
7.3.1 Undervoltage Lockout (UVLO)
The TLV733 uses an undervoltage lockout (UVLO) circuit that disables the output until the input voltage is
greater than the rising UVLO voltage, UVLORISE. This circuit ensures that the device does not exhibit any
unpredictable behavior when the supply voltage is lower than the operational range of the internal circuitry.
During UVLO disable, the output is connected to ground with a 120-Ω pulldown resistor.
7.3.2 Shutdown and Output Enable
The enable pin (EN) is active high. Enable the device by forcing the EN pin to exceed VEN(HI). Turn off the device
by forcing the EN pin to drop below VEN(LO). If shutdown capability is not required, connect EN to IN. There is no
internal pulldown resistor connected to the EN pin.
The TLV733 has an internal pulldown MOSFET that connects a 120-Ω resistor to ground when the device is
disabled. The discharge time after disabling depends on the output capacitance (COUT) and the load resistance
(RL) in parallel with the 120-Ω pulldown resistor. The time constant is calculated in Equation 1:
120 · RL
t=
· COUT
120 + RL
(1)
7.3.3 Internal Foldback Current Limit
The TLV733 has an internal foldback current limit that protects the regulator during fault conditions. The current
allowed through the device is reduced as the output voltage falls. When the output is shorted, the LDO supplies a
typical current of 150 mA. The output voltage is not regulated when the device is in current limit. In this condition,
the output voltage is the product of the regulated current and the load resistance. When the device output is
shorted, the PMOS pass transistor dissipates power [(VIN – VOUT) × IOS] until thermal shutdown is triggered and
the device turns off. After the device cools down, the internal thermal shutdown circuit turns the device back on.
If the fault condition continues, the device cycles between current limit and thermal shutdown. See the Thermal
Information table for more details.
The foldback current-limit circuit limits the current allowed through the device to current levels lower than the
minimum current limit at nominal VOUT current limit (ILIM) during startup. See Figure 18 to Figure 20 for typical
foldback current limit values. If the output is loaded by a constant-current load during startup, or if the output
voltage is negative when the device is enabled, then the load current demanded by the load may exceed the
foldback current limit and the device may not rise to the full output voltage. For constant-current loads, disable
the output load until the TLV733 has fully risen to its nominal output voltage.
The TLV733 PMOS pass element has an intrinsic body diode that conducts current when the voltage at the OUT
pin exceeds the voltage at the IN pin. Do not force the output voltage to exceed the input voltage because
excessively high current may flow through the body diode.
7.3.4 Thermal Shutdown
Thermal shutdown protection disables the output when the junction temperature rises to approximately 160°C.
Disabling the device eliminates the power dissipated by the device, allowing the device to cool. When the
junction temperature cools to approximately 140°C, the output circuitry is again enabled. Depending on power
dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off.
This cycling limits regulator dissipation, protecting it from damage as a result of overheating.
Activating the thermal shutdown feature usually indicates excessive power dissipation as a result of the product
of the (VIN –VOUT) voltage and the load current. For reliable operation, limit junction temperature to 125°C
maximum. To estimate the margin of safety in a complete design, increase the ambient temperature until the
thermal protection is triggered; use worst-case loads and signal conditions.
The TLV733 internal protection circuitry protects against overload conditions but is not intended to be activated in
normal operation. Continuously running the TLV733 into thermal shutdown degrades device reliability.
14
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7.4 Device Functional Modes
7.4.1 Normal Operation
The device regulates to the nominal output voltage under the following conditions:
•
•
•
•
•
The input voltage has previously exceeded the UVLO rising voltage and has not decreased below the UVLO
falling threshold.
The input voltage is greater than the nominal output voltage added to the dropout voltage.
The enable voltage has previously exceeded the enable rising threshold voltage and not decreased below the
enable falling threshold.
The output current is less than the current limit.
The device junction temperature is less than the thermal shutdown temperature.
7.4.2 Dropout Operation
If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other
conditions are met for normal operation, the device operates in dropout mode. In this condition, the output
voltage is the same the input voltage minus the dropout voltage. The transient performance of the device is
significantly degraded because the pass device is in a triode state and no longer controls the current through the
LDO. Line or load transients in dropout may result in large output voltage deviations.
7.4.3 Disabled
The device is disabled under the following conditions:
• The input voltage is less than the UVLO falling voltage, or has not yet exceeded the UVLO rising threshold.
• The enable voltage is less than the enable falling threshold voltage or has not yet exceeded the enable rising
threshold.
• The device junction temperature is greater than the thermal shutdown temperature.
When the device is disabled, the active pulldown resistor discharges the output.
Table 1 shows the conditions that lead to the different modes of operation.
Table 1. Device Functional Mode Comparison
OPERATING MODE
PARAMETER
VIN
VEN
IOUT
TJ
Normal mode
VIN > VOUT(nom) + VDO
and VIN > UVLORISE
VEN > VEN(HI)
IOUT < ILIM
TJ < 160°C
Dropout mode
UVLORISE < VIN < VOUT(nom) + VDO
VEN > VEN(HI)
IOUT < ILIM
TJ < 160°C
VIN < UVLOFALL
VEN < VEN(LO)
—
TJ > 160°C
Disabled mode
(any true condition
disables the device)
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Input and Output Capacitor Selection
The TLV733 uses an advanced internal control loop to obtain stable operation both with and without the use of
input or output capacitors. Dynamic performance is improved with the use of an output capacitor, and may be
improved with an input capacitor. An output capacitance of 0.1 μF or larger generally provides good dynamic
response. Use X5R- and X7R-type ceramic capacitors because these capacitors have minimal variation in value
and equivalent series resistance (ESR) over temperature.
Although an input capacitor is not required for stability, increased output impedance from the input supply may
compromise the performance of the TLV733. Good analog design practice is to connect a 0.1-µF to 1-µF
capacitor from IN to GND. This capacitor counteracts reactive input sources and improves transient response,
input ripple, and PSRR. Use an input capacitor if the source impedance is greater than 0.5 Ω. Use a higher-value
capacitor if large, fast, rise-time load transients are anticipated, or if the device is located several inches from the
input power source.
Figure 33 shows the transient performance improvements with an external 1-µF capacitor on the output versus
no output capacitor. The data in this figure are taken with an increasing load step from 50 mA to 300 mA, and the
peak output voltage deviation (load transient response) is measured. For low output current slew rates,
(< 0.1 A/µs), the transient performance of the device is similar with or without an output capacitor. As the current
slew rate is increased, the peak voltage deviation is significantly increased. For loads that exhibit fast current
slew rates above 0.1 A/µs, use an output capacitor. For best performance, the maximum recommended output
capacitance is 100 µF.
Peak Output Voltage Change (%VOUT)
35
30
1-PF COUT
COUT Removed
25
20
15
10
5
0
0.01
0.1
Output Load Transient Slew Rate (A/Ps)
1
D027
TLV73333PDBV, output current stepped from 50 mA to 300 mA, output voltage change measured at positive dI/dt
Figure 33. Output Voltage Deviation vs Load Step Slew Rate
Some applications benefit from the removal of the output capacitor. In addition to space and cost savings, the
removal of the output capacitor lowers inrush current as a result of eliminating the required current flow into the
output capacitor upon startup. In these cases, take care to ensure that the load is tolerant of the additional output
voltage deviations.
16
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Application Information (continued)
8.1.2 Dropout Voltage
The TLV733 uses a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the dropout
voltage (VDO), the PMOS pass device is in the linear region of operation and the input-to-output resistance is the
RDS(ON) of the PMOS pass element. VDO scales approximately with output current because the PMOS device
behaves like a resistor in dropout mode. As with any linear regulator, PSRR and transient response degrade as
(VIN – VOUT) approaches dropout operation. See Figure 7 to Figure 12 for typical dropout values.
8.1.3 Power Dissipation
The ability to remove heat from the die is different for each package type, presenting different considerations in
the printed circuit board (PCB) layout. The PCB area around the device that is free of other components moves
the heat from the device to ambient air. Performance data for JEDEC high-K boards are given in the Thermal
Information table. Using heavier copper increases the effectiveness in removing heat from the device. The
addition of plated through-holes to heat-dissipating layers also improves heatsink effectiveness.
Power dissipation (PD) depends on input voltage and load conditions. PD is equal to the product of the output
current and voltage drop across the output pass element, as shown in Equation 2.
PD = (VIN – VOUT) × IOUT
(2)
Maximum Ambient Temperature (qC)
Figure 34 shows the maximum ambient temperature versus the power dissipation of the TLV733 in the DQN and
DBV packages. This figure assumes the device is soldered on JEDEC standard high-K layout with no airflow
over the board. Actual board thermal impedances vary widely. If the application requires high power dissipation,
having a thorough understanding of the board temperature and thermal impedances is helpful to make sure the
TLV733 does not operate continuously above a junction temperature of 125°C.
125
120
115
110
105
100
95
90
85
80
75
70
65
60
55
TLV733 DQN, High-K Layout
TLV733 DBV, High-K Layout
0
0.03 0.06 0.09 0.12 0.15 0.18 0.21 0.24 0.27
Power Dissipation (W)
0.3
D028
TLV733, high-K layout
Figure 34. Maximum Ambient Temperature vs Device Power Dissipation
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8.2 Typical Applications
8.2.1 DC-DC Converter Post Regulation
VOUT
1.8 V
IN
CIN
1 µF
DC-DC
Converter
OUT
VOUT
1.5 V
COUT
1 µF
TLV733
EN
Load
GND
ON
OFF
Figure 35. DC-DC Converter Post Regulation
8.2.1.1 Design Requirements
Table 2. Design Parameters
PARAMETER
DESIGN REQUIREMENT
Input voltage
1.8 V, ±5%
Output voltage
1.5 V, ±1%
Output current
200-mA dc, 300-mA peak
Output voltage transient deviation
< 10%, 1-A/µs load step from 50 mA to 200 mA
Maximum ambient temperature
85°C
8.2.1.2 Design Considerations
Input and output capacitors are required to achieve the output voltage transient requirements. Capacitance
values of 1 µF are selected to give the maximum output capacitance in a small, low-cost package.
Figure 7 shows the 1.2-V option dropout voltage. Given that dropout voltages are higher for lower output-voltage
options, and given that the 1.2-V option dropout voltage is typically less than 300 mV at 125°C, then the 1.5-V
option dropout voltage is typically less than 300 mV at 125°C.
Verify that the maximum junction temperature is not exceeded by referring to Figure 34.
8.2.1.3 Application Curve
VIN (500 mV/div)
VOUT (500 mV/div)
IOUT (100 mA/div)
Time (50 µs/div)
Figure 36. 1.8-V to 1.5-V Regulation at 300 mA
18
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8.2.2 Capacitor-Free Operation from Battery Input Supply
IN
OUT
TLV733
VBAT
Load
EN
GND
Figure 37. Capacitor-Free Operation from Battery Input Supply
8.2.2.1 Design Requirements
Table 3. Design Parameters
PARAMETER
DESIGN REQUIREMENT
Input voltage
3.0 V to 1.8 V (two 1.5-V batteries)
Output voltage
1.0 V, ±1%
Input current
200 mA, maximum
Output load
100-mA dc
Maximum ambient temperature
70°C
8.2.2.2 Design Considerations
An input capacitor is not required for this design because of the low impedance connection directly to the battery.
No output capacitor allows for the minimal possible inrush current during startup, ensuring the 200-mA maximum
input current is not exceeded.
Verify that the maximum junction temperature is not exceeded by referring to Figure 34.
8.2.2.3 Application Curve
VIN (1 V/div)
VOUT (500 mV/div)
IIN (100 mA/div)
Time (50 µs/div)
Figure 38. No Inrush Startup, 3.0-V to 1.0-V Regulation
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9 Power Supply Recommendations
Connect a low output impedance power supply directly to the IN pin of the TLV733. Inductive impedances
between the input supply and the IN pin can create significant voltage excursions at the IN pin during startup or
load transient events. If inductive impedances are unavoidable, use an input capacitor.
10 Layout
10.1 Layout Guidelines
•
•
•
•
Place input and output capacitors as close to the device as possible.
Use copper planes for device connections, in order to optimize thermal performance.
Place thermal vias around the device to distribute the heat.
Do not place a thermal via directly beneath the thermal pad of the DQN package. A via can wick solder or
solder paste away from the thermal pad joint during the soldering process, leading to a compromised solder
joint on the thermal pad.
10.2 Layout Examples
VOUT
VIN
TLV733
1
4
COUT*
CIN*
3
2
GND PLANE
Represents via used for
application specific connections
*not required
Figure 39. Layout Example for the DQN Package
VOUT
VIN
1
CIN*
5
COUT*
2
3
4
GND PLANE
Represents via used for
application specific connections
*not required
Figure 40. Layout Example for the DBV Package
20
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 Evaluation Module
An evaluation module (EVM) is available to assist in the initial circuit performance evaluation using the TLV733.
The TLV73312PEVM-643 evaluation module (and related user guide) can be requested at the Texas Instruments
website through the product folders or purchased directly from the TI eStore.
11.1.2 Device Nomenclature
Table 4. Device Nomenclature (1) (2)
(1)
(2)
PRODUCT
VOUT
TLV733xx(x)Pyyyz(3)
xx(x) is the nominal output voltage. For output voltages with a resolution of 100 mV, two digits are used
in the ordering number; otherwise, three digits are used (for example, 28 = 2.8 V; 125 = 1.25 V).
P indicates an active output discharge feature. All members of the TLV733 family will actively discharge
the output when the device is disabled.
yyy is the package designator.
z is the package quantity. R is for reel (3000 pieces), T is for tape (250 pieces).
(3) indicates an alternative tape and reel orientation. 3 indicates that pin 1 is in quadrant 3. See the
Package Materials Information addendum for more information.
For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the
device product folder on www.ti.com.
Output voltages from 1.0 V to 3.3 V in 50-mV increments are available. Contact the factory for details and availability.
11.2 Documentation Support
11.2.1 Related Documentation
Texas Instruments, TLV73312PDQN-643 Evaluation Module user guide
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
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11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OUTLINE
DQN0004A
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
4215302/D 06/2016
NOTES:
1.
2.
3.
4.
All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
This drawing is subject to change without notice.
The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
Features may not exist. Recommend use of pin 1 marking on top of package for orientation purposes.
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EXAMPLE BOARD LAYOUT
DQN0004A
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
4215302/D 06/2016
NOTES: (continued)
24
5.
This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271) .
6.
If any vias are implemented, it is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
DQN0004A
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
4215302/D 06/2016
NOTES: (continued)
7.
Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TLV73310PDBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
VCCQ
Samples
TLV73310PDBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
VCCQ
Samples
TLV73310PDQNR
ACTIVE
X2SON
DQN
4
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
FG
Samples
TLV73310PDQNT
ACTIVE
X2SON
DQN
4
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
FG
Samples
TLV73311PDBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
ZBLW
Samples
TLV73311PDBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
ZBLW
Samples
TLV73311PDQNR
ACTIVE
X2SON
DQN
4
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
GR
Samples
TLV73311PDQNT
ACTIVE
X2SON
DQN
4
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
GR
Samples
TLV73312PDBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
VCDQ
Samples
TLV73312PDBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
VCDQ
Samples
TLV73312PDQNR
ACTIVE
X2SON
DQN
4
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
FI
Samples
TLV73312PDQNR3
ACTIVE
X2SON
DQN
4
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
FI
Samples
TLV73312PDQNT
ACTIVE
X2SON
DQN
4
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
FI
Samples
TLV73315PDBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
VCFQ
Samples
TLV73315PDBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
VCFQ
Samples
TLV73315PDQNR
ACTIVE
X2SON
DQN
4
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
FJ
Samples
TLV73315PDQNR3
ACTIVE
X2SON
DQN
4
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
FJ
Samples
TLV73315PDQNT
ACTIVE
X2SON
DQN
4
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
FJ
Samples
TLV73318PDBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
VCGQ
Samples
TLV73318PDBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
VCGQ
Samples
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
6-Dec-2022
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TLV73318PDQNR
ACTIVE
X2SON
DQN
4
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
FK
Samples
TLV73318PDQNR3
ACTIVE
X2SON
DQN
4
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
FK
Samples
TLV73318PDQNT
ACTIVE
X2SON
DQN
4
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
FK
Samples
TLV73325PDBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
VCHQ
Samples
TLV73325PDBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
VCHQ
Samples
TLV73325PDQNR
ACTIVE
X2SON
DQN
4
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
FL
Samples
TLV73325PDQNT
ACTIVE
X2SON
DQN
4
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
FL
Samples
TLV733285PDBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
ZDRW
Samples
TLV733285PDBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
ZDRW
Samples
TLV733285PDQNR
ACTIVE
X2SON
DQN
4
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
GZ
Samples
TLV733285PDQNT
ACTIVE
X2SON
DQN
4
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
GZ
Samples
TLV73328PDBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
ZDQW
Samples
TLV73328PDBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
ZDQW
Samples
TLV73328PDQNR
ACTIVE
X2SON
DQN
4
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
GY
Samples
TLV73328PDQNR3
ACTIVE
X2SON
DQN
4
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
GY
Samples
TLV73328PDQNT
ACTIVE
X2SON
DQN
4
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
GY
Samples
TLV73330PDBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
ZDMW
Samples
TLV73330PDBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
ZDMW
Samples
TLV73330PDQNR
ACTIVE
X2SON
DQN
4
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
GW
Samples
TLV73330PDQNT
ACTIVE
X2SON
DQN
4
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
GW
Samples
TLV73333PDBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
VCIQ
Samples
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
6-Dec-2022
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TLV73333PDBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
VCIQ
Samples
TLV73333PDQNR
ACTIVE
X2SON
DQN
4
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
FM
Samples
TLV73333PDQNT
ACTIVE
X2SON
DQN
4
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
FM
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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