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TLV755P
SBVS320A – NOVEMBER 2017 – REVISED MAY 2018
TLV755P 500-mA, Low IQ, Small Size, Low Dropout Regulator
1 Features
3 Description
•
•
•
The TLV755P is an ultra-small, low quiescent current,
low-dropout regulator (LDO) that sources 500 mA
with good line and load transient performance. The
TLV755P is optimized for a wide variety of
applications by supporting an input voltage range
from 1.45 V to 5.5 V. To minimize cost and solution
size, the device is offered in fixed output voltages
ranging from 0.6 V to 5 V to support the lower core
voltages of modern microcontrollers (MCUs).
Additionally, the TLV755P has a low IQ with enable
functionality to minimize standby power. This device
features an internal soft-start to lower inrush current,
thus providing a controlled voltage to the load and
minimizing the input voltage drop during start up.
When shutdown, the device actively pulls down the
output to quickly discharge the outputs and ensure a
known start-up state.
1
•
•
•
•
•
•
•
Input Voltage Range: 1.45 V to 5.5 V
Low IQ: 25 µA (Typical)
Low Dropout:
– 238 mV (Maximum) at 500 mA (3.3 VOUT)
Output Accuracy: 1% (Maximum at 85°C)
Built-In Soft-Start With Monotonic VOUT Rise
Foldback Current Limit
Active Output Discharge
High PSRR: 46 dB at 100 kHz
Stable With a 1-µF Ceramic Output Capacitor
Packages:
– 2.9-mm × 1.6-mm SOT-23-5
– 1-mm x 1-mm X2SON-4
– 2 mm × 2 mm WSON-6
2 Applications
•
•
•
•
•
•
•
Set-Top Boxes, TV, and Gaming Consoles
Portable and Battery-Powered Equipment
Desktop, Notebooks, and Ultrabooks
Tablets and Remote Controls
White Goods and Appliances
Grid Infrastructure and Protection Relays
Camera Modules and Image Sensors
The TLV755P is stable with small ceramic output
capacitors allowing for a small overall solution size. A
precision band-gap and error amplifier provides a
typical accuracy of 1%. All device versions have
integrated thermal shutdown, current limit, and
undervoltage lockout (UVLO). The TLV755P has an
internal foldback current limit that helps reduce the
thermal dissipation during short-circuit events.
Device Information(1)
PART NUMBER
PACKAGE
TLV755P
BODY SIZE (NOM)
X2SON (4)
1.00 mm × 1.00 mm
SOT-23 (5)
2.90 mm × 1.60 mm
SON (6)
2.00 mm × 2.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application
Startup Waveform
7
EN
ON
OFF
GND
VIN
VEN
IOUT
6
150
5
125
4
100
3
75
2
50
1
25
COUT
0
Output Current (mA)
TLV755P
CIN
175
VOUT
OUT
Voltage (V)
IN
0
0
0.2
0.4
0.6
0.8
1
1.2
Time (ms)
1.4
1.6
1.8
2
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLV755P
SBVS320A – NOVEMBER 2017 – REVISED MAY 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information .................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 12
7.1 Overview ................................................................. 12
7.2 Functional Block Diagram ....................................... 12
7.3 Feature Description................................................. 12
7.4 Device Functional Modes........................................ 14
8
Application and Implementation ........................ 15
8.1 Application Information............................................ 15
8.2 Typical Application ................................................. 19
9 Power Supply Recommendations...................... 20
10 Layout................................................................... 21
10.1 Layout Guidelines ................................................. 21
10.2 Layout Examples................................................... 21
11 Device and Documentation Support ................. 22
11.1
11.2
11.3
11.4
11.5
11.6
Device Support......................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
22
22
22
22
22
22
12 Mechanical, Packaging, and Orderable
Information ........................................................... 22
4 Revision History
Changes from Original (November 2017) to Revision A
•
2
Page
Released to production .......................................................................................................................................................... 1
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SBVS320A – NOVEMBER 2017 – REVISED MAY 2018
5 Pin Configuration and Functions
DQN Package
4-Pin X2SON
Top View
OUT
1
DBV Package
5-Pin SOT-23
Top View
4
IN
5
GND
2
3
IN
1
GND
2
EN
3
EN
Not to scale
5
OUT
4
NC
Not to scale
DRV Package
6-Pin WSON With Exposed Thermal Pad
Top View
OUT
1
NC
GND
6
IN
2 Thermal 5
Pad
NC
3
EN
4
Not to scale
NC = no internal connection.
Pin Functions
PIN
NAME
I/O
DESCRIPTION
DQN
DBV
DRV
EN
3
3
4
I
GND
2
2
3
—
IN
4
1
6
I
NC
—
4
2, 5
—
No internal connection.
OUT
1
5
1
O
Regulated output voltage pin. A capacitor with a value of 1 µF or larger
is required from this pin to ground (1). See the Input and Output
Capacitor Selection section for more information.
Pad
—
Pad
—
Connect the thermal pad to a large-area ground plane.
The thermal pad is internally connected to GND.
Thermal pad
(1)
Enable pin. Drive EN greater than VHI to turn on the regulator.
Drive EN less than VLO to place the LDO into shutdown mode.
Ground pin.
Input pin. A capacitor with a value of 1 µF or larger is required from
this pin to ground (1). See the Input and Output Capacitor Selection
section for more information.
The nominal input and output capacitance must be greater than 0.47 µF; throughout this document the nominal derating on these
capacitors is 50%. Make sure that the effective capacitance at the pin is greater than 0.47 µF.
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SBVS320A – NOVEMBER 2017 – REVISED MAY 2018
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
Supply voltage, VIN
-0.3
6.0
V
Enable voltage, VEN
-0.3
6.0
V
Output voltage, VOUT
-0.3
VIN + 0.3 (2)
V
Operating junction temperature range, TJ
-40
150
°C
Storage temperature, Tstg
-65
150
°C
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The absolute maximum rating is VIN + 0.3 V or 6.0 V, whichever is smaller
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±1000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VIN
Input voltage
VOUT
VEN
NOM
MAX
UNIT
1.45
5.5
V
Output voltage
0.6
5.0
V
Enable voltage
0
5.5
V
IOUT
Output current
0
500
mA
CIN
Input capacitor
1
COUT
Output capacitor
1
fEN
Enable toggle frequency
TJ
Junction temperature
μF
–40
200
μF
10
kHz
125
°C
6.4 Thermal Information
TLV755
DQN (X2SON) DBV (SOT-235)
THERMAL METRIC (1)
DRV (SON)
4 PINS
5 PINS
6 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
168.4
231.1
100.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
139.1
118.4
108.5
°C/W
RθJB
Junction-to-board thermal resistance
101.4
64.4
64.3
°C/W
ψJT
Junction-to-top characterization parameter
5.6
28.4
10.4
°C/W
ψJB
Junction-to-board characterization parameter
101.7
63.8
64.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
88.4
N/A
34.7
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SBVS320A – NOVEMBER 2017 – REVISED MAY 2018
6.5 Electrical Characteristics
at operating temperature range (TJ = –40°C to 125°C), VIN = VOUT(NOM) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA,
VEN = VIN, and CIN = COUT = 1 μF, unless otherwise noted. All typical values at TJ = 25°C.
PARAMETER
VIN
Input voltage
VOUT
Output voltage
TEST CONDITIONS
-40°C ≤ TJ ≤ +85°C, DBV and DRV package
VOUT ≥ 1.0 V, DQN package
Output accuracy
-40°C ≤ TJ ≤ +85°C; 0.6 V ≤ VOUT < 1.0 V
VOUT ≥ 1 V
0.6 V ≤ VOUT < 1 V
(ΔVOUT)
Line regulation
ΔVIN
VOUT + 0.5 V ≤ VIN ≤ 5.5 V, VOUT > 1.5 V
ΔVOUT/
ΔIOUT
0.1 mA ≤
IOUT ≤ 500
mA
Load regulation
Ground current
-1.2%
1.2%
-10
10
-1.5%
1.5%
-15
15
0.044
14
25
IOUT =
500mA,
-40°C ≤ TJ
≤ +85°C
Dropout voltage
IOUT =
500mA,
-40°C ≤ TJ
≤ +125°C
0.1
1
VOUT = VOUT - 0.2 V, VOUT ≤ 1.5V
560
720
865
VOUT = 0.9 x VOUT, 1.5V < VOUT ≤ 4.5V
560
720
865
675
1080
0.8 V ≤ VOUT < 1.0V
600
930
1.0 V ≤ VOUT < 1.2 V
550
780
1.2 V ≤ VOUT < 1.5 V
500
630
1.5 V ≤ VOUT < 1.8 V
350
400
1.8 V ≤ VOUT < 2.5 V
325
380
2.5 V ≤ VOUT < 3.3 V
250
300
3.3 V ≤ VOUT < 5.0 V
150
mA
215
0.6 V ≤ VOUT < 0.8 V
1140
0.8 V ≤ VOUT < 1.0 V
985
1.0 V ≤ VOUT < 1.2 V
825
1.2 V ≤ VOUT < 1.5 V
665
1.5 V ≤ VOUT < 1.8 V
425
1.8 V ≤ VOUT < 2.5 V
400
2.5 V ≤ VOUT < 3.3 V
325
52
f = 100 kHz, VIN = VOUT + 1 V, IOUT = 50 mA
46
f = 1 MHz, VIN = VOUT + 1 V, IOUT = 50 mA
52
BW = 10 Hz to 100 kHz; VOUT = 1.2 V, IOUT = 500
mA
VUVLO
Undervoltage lockout
VIN rising
VUVLO,HY Undervoltage lockout
hysteresis
ST
VIN falling
mV
238
f = 1 kHz, VIN = VOUT + 1 V, IOUT = 50 mA
Output noise voltage
EN pin high voltage (enabled)
µA
mA
0.6 V ≤ VOUT < 0.8 V
VN
Startup time
µA
355
3.3 V ≤ VOUT < 5.0 V
VHI
31
40
VOUT = 0 V
tSTR
V/A
33
Short circuit current limit
mV
mV
-40°C ≤ TJ ≤ +125°C, IOUT = 0 mA
ISC
mV
2
-40°C ≤ TJ ≤ +85°C, IOUT = 0 mA
Output current limit
Power-supply rejection ratio
V
5.0
DRV package
ICL
PSRR
V
1%
0.060
VIN =
VOUT+
VDO(MAX) +
0.25 V
UNIT
5.5
0.6
0.036
VEN ≤ 0.4 V, 1.4 V ≤ VIN ≤ 5.5 V, -40°C ≤ TJ ≤
+125°C
VDO
MAX
-1%
DBV package
Shutdown current
ISHDN
TYP
DQN package
TJ = 25°C, IOUT = 0 mA
IGND
MIN
1.45
dB
71.5
1.21
1.3
µVRMS
1.44
40
mV
550
µs
1
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V
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Electrical Characteristics (continued)
at operating temperature range (TJ = –40°C to 125°C), VIN = VOUT(NOM) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA,
VEN = VIN, and CIN = COUT = 1 μF, unless otherwise noted. All typical values at TJ = 25°C.
PARAMETER
VLO
EN pin low voltage (enabled)
IEN
Enable pin current
TSD
Thermal shutdown
RPULLDO
Pulldown resistance
WN
6
TEST CONDITIONS
MIN
TYP
MAX
0.3
EN = 5.5V
10
Shutdown, temperature increasing
165
Reset, temperature decreasing
155
VIN = 5.5V
120
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UNIT
V
nA
°C
Ω
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6.6 Typical Characteristics
at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 0.5 V or 1.45 V (whichever is greater), IOUT = 1 mA, VEN = VIN, and CIN
= COUT = 1 µF (unless otherwise noted)
100
Power Supply Rejection Ratio (dB)
Power Supply Rejection Ratio (dB)
100
80
60
40
20
0
10
IOUT = 10 mA
IOUT = 50 mA
IOUT = 100 mA
IOUT = 500 mA
100
1k
10k
100k
Frequency (Hz)
1M
80
60
40
VIN
3.8 V
4V
4.3 V
4.5 V
5V
20
0
10
10M
100
VIN = 4.3 V, VOUT = 3.3 V, COUT = 1 µF
Figure 1. PSRR vs Frequency and IOUT
Noise (PV/—Hz)
Power Supply Rejection Ratio (dB)
40
2
1
0.5
COUT = 1 PF
COUT = 10 PF
COUT = 22 PF
COUT = 100 PF
100
1k
10k
100k
Frequency (Hz)
1M
10M
0.2
0.1
0.05
0.02
0.01
0.005
100
1k
10k
100k
Frequency (Hz)
1M
10M
VOUT = 3.3 V, VRMS BW = 10 Hz to 100 kHz
Figure 3. PSRR vs Frequency and COUT
Figure 4. Output Spectral Noise Density vs
Frequency and COUT
10
5
220
200
2
1
0.5
Output Noise Voltage (PVRMS)
Noise (PV/—Hz)
COUT
1 PF, 143 PVRMS
10 PF, 150 PVRMS
22 PF, 149 PVRMS
100 PF, 146 PVRMS
0.002
0.001
10
VIN = 4.3 V, VOUT = 3.3 V, IOUT = 500 mA
0.2
0.1
0.05
0.002
0.001
10
10M
Figure 2. PSRR vs Frequency and VIN
60
0.02
0.01
0.005
1M
10
5
80
0
10
10k
100k
Frequency (Hz)
VOUT = 3.3 V, COUT = 1 µF, IOUT = 500 mA
100
20
1k
IOUT
10 mA, 140 PVRMS
50 mA, 142 PVRMS
100 mA, 142 PVRMS
500 mA, 143 PVRMS
100
1k
10k
100k
Frequency (Hz)
180
160
140
120
100
80
60
1M
10M
VOUT = 3.3 V, IOUT = 500 mA, COUT = 1 µF, VRMS BW = 10 Hz to
100 kHz
40
0.5
1
1.5
2
2.5
3
3.5
Output Voltage (V)
4
4.5
5
IOUT = 500 mA, COUT = 1 µF, VRMS BW = 10 Hz to 100 kHz
Figure 5. Output Spectral Noise Density vs
Frequency and IOUT
Figure 6. Output Noise Voltage vs VOUT
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Typical Characteristics (continued)
at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 0.5 V or 1.45 V (whichever is greater), IOUT = 1 mA, VEN = VIN, and CIN
= COUT = 1 µF (unless otherwise noted)
3.328
VIN
VOUT
3.312
3
3.304
2
3.296
1
3.288
0
0
20
Time (ms)
3.35
480
3.325
400
3.3
320
3.275
240
3.25
160
3.225
80
0
0
VOUT = 3.3 V, COUT = 1 µF, VIN slew rate = 1 V/µs
40
Figure 7. Line Transient
Figure 8. 3.3-V, 1-mA to 500-mA Load Transient
6
VIN
VOUT
5
VIN
VOUT
5
4
4
Voltage (V)
Voltage (V)
80 120 160 200 240 280 320 360 400 440 480
Time (Ps)
VIN = 5 V, VOUT = 3.3 V, COUT = 1 µF, IOUT slew rate = 1 A/µs
6
3
3
2
2
1
1
0
0
0
0.5
1
1.5
2
2.5
3
Time (ms)
3.5
4
4.5
5
0
1
Figure 9. VIN = VEN Power-Up
175
10
6
150
5
5
125
4
100
3
75
2
50
1
25
-25
0
-30
VEN
0
0.2
0.4
0.6
0.8
1
1.2
Time (ms)
1.4
1.6
3
4
5
6
Time (ms)
7
8
IOUT
1.8
2
Output Voltage (mV)
VIN
Output Current (mA)
Voltage (V)
VOUT
2
9
10
Figure 10. VIN = VEN Shutdown
7
0
560
3.2
3.28
50
40
Output Voltage (V)
4
640
VOUT
IOUT
3.375
3.32
Output Voltage (V)
Input Voltage (V)
5
3.4
Output Current (A)
6
-40°C
0°C
25°C
85°C
125°C
0
-5
-10
-15
-20
0
50
100
150
200 250 300 350
Output Current (mA)
400
450
500
VIN = 5 V, IOUT = 100 mA, VEN slew rate = 1 V/µs, VOUT = 3.3 V
Figure 11. EN Startup
8
Figure 12. Load Regulation vs IOUT
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Typical Characteristics (continued)
at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 0.5 V or 1.45 V (whichever is greater), IOUT = 1 mA, VEN = VIN, and CIN
= COUT = 1 µF (unless otherwise noted)
200
200
-40qC
0qC
25qC
-40qC
0qC
25qC
160
150
Dropout Voltage (mV)
Dropout Voltage (mV)
175
85qC
125qC
125
100
75
50
85qC
125qC
120
80
40
25
0
0
0
50
100
150
200 250 300 350
Output Current (mA)
400
450
500
0
Figure 13. 3.3-V Dropout Voltage vs IOUT
-40qC
0qC
25qC
85qC
-40qC
0qC
0.75
400
450
500
25qC
85qC
125qC
Accuracy (%)
0.5
0.25
0
-0.25
0.25
0
-0.25
-0.5
-0.5
-0.75
-0.75
-1
3.75
4
4.25
4.5
4.75
Input Voltage (V)
5
5.25
5.5
5
5.1
VOUT = 3.3 V, IOUT = 1 mA
600
500
400
300
-40°C
0°C
25°C
85°C
125°C
200
100
0
150
200 250 300 350
Output Current (mA)
400
450
500
GND Pin Current (PA)
700
100
5.4
5.5
Figure 16. 5.0-V Accuracy vs VIN (Line Regulation)
800
50
5.2
5.3
Input Voltage (V)
IOUT = 1 mA, VOUT = 5 V
Figure 15. 3.3-V Regulation vs VIN (Line Regulation)
GND Pin Current (ɥA)
200 250 300 350
Output Current (mA)
125qC
0.5
0
150
1
0.75
Accuracy (%)
100
Figure 14. 5.0-V Dropout Voltage vs IOUT
1
-1
3.5
50
650
600
550
500
450
400
350
300
250
200
150
100
50
0
-40qC
0qC
25qC
85qC
125qC
0
1
2
3
4
Input Voltage (V)
5
6
VOUT = 3.3 V, IOUT = 1 mA
Figure 17. IGND vs IOUT
Figure 18. IGND vs VIN
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Typical Characteristics (continued)
at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 0.5 V or 1.45 V (whichever is greater), IOUT = 1 mA, VEN = VIN, and CIN
= COUT = 1 µF (unless otherwise noted)
350
300
-40qC
0qC
25qC
85qC
125qC
200
Shutdown Current (nA)
Quiescent Current (PA)
250
-40qC
0qC
25qC
85qC
125qC
300
150
100
50
250
200
150
100
50
0
0
0
1
2
3
4
Input Voltage (V)
5
6
0
1
2
VOUT = 3.3 V, IOUT = 0 mA
3
4
Input Voltage (V)
5
6
VEN = 0 V
Figure 19. IQ vs VIN
Figure 20. ISHDN vs VIN
180
800
160
Enable Threshold (mV)
Shutdown Current (nA)
750
140
120
100
80
60
40
700
650
600
550
20
EN Negative
0
-40
-20
0
20
40
60
80
Temperature (qC)
100
120
500
-50
140
-25
0
EN Positive
25
50
Temperature (qC)
75
100
125
VEN = 0 V
Figure 21. ISHDN vs Temperature
Figure 22. Enable Threshold vs Temperature
250
1.4
-40qC
0qC
25qC
85qC
125qC
1.36
UVLO Threshold (V)
Enable Current (PA)
200
150
100
1.32
1.28
1.24
50
UVLO Negative
0
0
1
2
3
4
Input Voltage (V)
5
6
1.2
-50
-25
0
UVLO Positive
25
50
Temperature (qC)
75
100
125
VEN = 5.5 V
Figure 23. IEN vs VIN
10
Figure 24. UVLO Threshold vs Temperature
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Typical Characteristics (continued)
at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 0.5 V or 1.45 V (whichever is greater), IOUT = 1 mA, VEN = VIN, and CIN
= COUT = 1 µF (unless otherwise noted)
600
3.5
-40qC
0qC
25qC
550
3
450
Output Voltage (mV)
Output Voltage (mV)
500
85qC
125qC
400
350
300
250
200
150
100
2.5
2
1.5
-40°C
0°C
25°C
85°C
125°C
1
0.5
50
0
0
0
1
2
3
Output Current (mA)
4
Figure 25. VOUT vs IOUT Pulldown Resistor
5
0
100
200
300
400
500
Output Current (mA)
600
700
800
Figure 26. 3.3-V Foldback Current Limit, VOUT vs IOUT
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7 Detailed Description
7.1 Overview
The TLV755P belongs to a family of next-generation, low-dropout regulators (LDOs). This device consumes low
quiescent current and delivers excellent line and load transient performance. The TLV755P is optimized for a
wide variety of applications by supporting an input voltage range from 1.45 V to 5.5 V. To minimize cost and
solution size, the device is offered in fixed output voltages ranging from 0.6 V to 5 V to support the lower core
voltages of modern microcontrollers (MCUs).
This regulator offers foldback current limit, shutdown, and thermal protection. The operating junction temperature
is –40°C to +125°C.
7.2 Functional Block Diagram
OUT
IN
Current
Limit
R1
±
+
Thermal
Shutdown
UVLO
120 Ÿ
R2
EN
Bandgap
GND
Logic
NOTE: R2 = 550 kΩ, R1 = adjustable.
7.3 Feature Description
7.3.1 Undervoltage Lockout (UVLO)
An undervoltage lockout (UVLO) circuit disables the output until the input voltage is greater than the rising UVLO
voltage (VUVLO). This circuit ensures that the device does not exhibit any unpredictable behavior when the supply
voltage is lower than the operational range of the internal circuitry. When VIN is less than VUVLO, the output is
connected to ground with a 120-Ω pulldown resistor.
7.3.2 Enable (EN)
The enable pin (EN) is active high. Enable the device by forcing the EN pin to exceed VHI. Turn off the device by
forcing the EN pin below VLO. If shutdown capability is not required, connect EN to IN.
The device has an internal pulldown that connects a 120-Ω resistor to ground when the device is disabled. The
discharge time after disabling depends on the output capacitance (COUT) and the load resistance (RL) in parallel
with the 120-Ω pulldown resistor. Equation 1 calculates the time constant τ:
120 · RL
t=
· COUT
120 + RL
(1)
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Feature Description (continued)
The EN pin is independent of the input pin (IN), but if the EN pin is driven to a higher voltage than VIN, the
current into the EN pin increases. This effect is illustrated in Figure 23. When the EN voltage is higher than the
input voltage there is an increased current flow into the EN pin. If this increased flow causes problems in the
application, sequence the EN pin after VIN is high, or to tie EN to VIN to prevent this flow increase from
happening. If EN is driven to a higher voltage than VIN, limit the frequency on EN to below 10 kHz.
7.3.3 Internal Foldback Current Limit
The TLV755P has an internal current limit that protects the regulator during fault conditions. The current limit is a
hybrid scheme with brick wall until the output voltage is less than 0.4 V × VOUT(NOM). When the voltage drops
below 0.4 V × VOUT(NOM), a foldback current limit is implemented that scales back the current as the output
voltage approaches GND. When the output shorts, the LDO supplies a typical current of ISC. The output voltage
is not regulated when the device is in current limit. In this condition, the output voltage is the product of the
regulated current and the load resistance. When the device output shorts, the PMOS pass transistor dissipates
power [(VIN – VOUT) × ISC] until thermal shutdown is triggered and the device turns off. After the device cools
down, the internal thermal shutdown circuit turns the device back on. If the fault condition continues, the device
cycles between current limit and thermal shutdown.
The foldback current-limit circuit limits the current that is allowed through the device to current levels lower than
the minimum current limit at nominal VOUT current limit (ICL) during start up. See Figure 26 for typical current limit
values. If the output is loaded by a constant-current load during start up, or if the output voltage is negative when
the device is enabled, then the load current demanded by the load may exceed the foldback current limit and the
device may not rise to the full output voltage. For constant-current loads, disable the output load until the output
has risen to the nominal voltage.
Excess inductance can cause the current limit to oscillate. Minimize the inductance to keep the current limit from
oscillating during a fault condition.
7.3.4 Thermal Shutdown
Thermal shutdown protection disables the output when the junction temperature rises to approximately 165°C.
Disabling the device eliminates the power dissipated by the device, allowing the device to cool. When the
junction temperature cools to approximately 155°C, the output circuitry is enabled again. Depending on power
dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off.
This cycling limits regulator dissipation that protects the circuit from damage as a result of overheating.
Activating the thermal shutdown feature usually indicates excessive power dissipation as a result of the product
of the (VIN – VOUT) voltage and the load current. For reliable operation, limit junction temperature to a maximum
of 125°C. To estimate the margin of safety in a complete design, increase the ambient temperature until the
thermal protection is triggered; use worst-case loads and signal conditions.
The internal protection circuitry protects against overload conditions but is not intended to be activated in normal
operation. Continuously running the device into thermal shutdown degrades device reliability.
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7.4 Device Functional Modes
Table 1 lists a comparison between the normal, dropout, and disabled modes of operation.
Table 1. Device Functional Modes Comparison
PARAMETER
OPERATING MODE
(1)
(2)
VIN
EN
IOUT
TJ
Normal (1)
VIN > VOUT(NOM) + VDO
VEN > VHI
IOUT < ICL
TJ < TSD
Dropout (1)
VIN < VOUT(NOM) + VDO
VEN > VHI
—
TJ < TSD
Disabled (2)
VIN < VUVLO
VEN < VLO
—
TJ > TSD
All table conditions must be met.
The device is disabled when any condition is met.
7.4.1 Normal Operation
The device regulates to the nominal output voltage when all of the following conditions are met.
• The input voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(NOM) + VDO)
• The enable voltage has previously exceeded the enable rising threshold voltage and has not decreased
below the enable falling threshold
• The output current is less than the current limit (IOUT < ICL)
• The device junction temperature is less than the thermal shutdown temperature (TJ < TSD)
7.4.2 Dropout Operation
If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other
conditions are met for normal operation, the device operates in dropout. In this mode, the output voltage tracks
the input voltage. During this mode, the transient performance of the device degrades because the pass device
is in a triode state and no longer controls the output voltage of the LDO. Line or load transients in dropout can
result in large output-voltage deviations.
When the device is in a steady dropout state (defined as when the device is in dropout, VIN < VOUT(NOM) + VDO,
right after being in a normal regulation state, but not during startup), the pass-FET is driven as hard as possible
when the control loop is out of balance. During the normal time required for the device to regain regulation, VIN ≥
VOUT(NOM) + VDO, VOUT can overshoot VOUT(NOM) during fast transients.
7.4.3 Disabled
The output is shut down by forcing the enable pin below VLO. When disabled, the pass device is turned off,
internal circuits are shut down, and the output voltage is actively discharged to ground by an internal switch from
the output to ground. The active pulldown is on when sufficient input voltage is provided.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Input and Output Capacitor Selection
The TLV755P requires an output capacitance of 0.47 µF or larger for stability. Use X5R- and X7R-type ceramic
capacitors because these capacitors have minimal variation in capacitance value and equivalent series
resistance (ESR) over temperature. When selecting a capacitor for a specific application, consider the DC bias
characteristics for the capacitor. Higher output voltages cause a significant derating of the capacitor. As a
general rule, ceramic capacitors must be derated by 50%. For best performance, TI recommends a maximum
output capacitance value of 200 µF.
Place a 1 µF or greater capacitor on the input pin of the LDO. Some input supplies have a high impedance.
Placing a capacitor on the input supply reduces the input impedance. The input capacitor counteracts reactive
input sources and improves transient response and PSRR. If the input supply has a high impedance over a large
range of frequencies, several input capacitors are used in parallel to lower the impedance over frequency. Use a
higher-value capacitor if large, fast, rise-time load transients are expected, or if the device is located several
inches from the input power source.
8.1.2 Dropout Voltage
The TLV755P uses a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the dropout
voltage (VDO), the PMOS pass device is in the linear region of operation and the input-to-output resistance is the
RDS(ON) of the PMOS pass element. VDO scales linearly with the output current because the PMOS device
functions like a resistor in dropout mode. As with any linear regulator, PSRR and transient response degrade as
(VIN – VOUT) approaches dropout operation. See Figure 13 and Figure 14 for typical dropout values.
8.1.3 Exiting Dropout
Some applications have transients that place the LDO into dropout, such as slower ramps on VIN during start-up.
As with other LDOs, the output may overshoot on recovery from these conditions. A ramping input supply causes
an LDO to overshoot on start-up when the slew rate and voltage levels are in the correct range; see Figure 27.
Use an enable signal to avoid this condition.
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Application Information (continued)
Input Voltage
Response time for
LDO to get back into
regulation.
Load current discharges
output voltage.
VIN = VOUT(nom) + VDO
Voltage
Output Voltage
Dropout
VOUT = VIN - VDO
Output Voltage in
normal regulation.
Time
Figure 27. Startup Into Dropout
Line transients out of dropout can also cause overshoot on the output of the regulator. These overshoots are
caused by the error amplifier having to drive the gate capacitance of the pass element and bring the gate back to
the correct voltage for proper regulation. Figure 28 illustrates what is happening internally with the gate voltage
and how overshoot can be caused during operation. When the LDO is placed in dropout, the gate voltage (VGS)
is pulled all the way down to ground to give the pass device the lowest on-resistance as possible. However, if a
line transient occurs while the device is in dropout, the loop is not in regulation and can cause the output to
overshoot until the loop responds and the output current pulls the output voltage back down into regulation. If
these transients are not acceptable, then continue to add input capacitance in the system until the transient is
slow enough to reduce the overshoot.
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Application Information (continued)
Transient response
time of the LDO
Input Voltage
Load current
discharges
output
voltage
Output Voltage
Voltage
VDO
Output Voltage in
normal regulation
Dropout
VOUT = VIN - VDO
VGS voltage
(pass device
fully off)
Input Voltage
VGS voltage for
normal operation
VGS voltage for
normal operation
Gate Voltage
VGS voltage in
dropout (pass device
fully on)
Time
Figure 28. Line Transients From Dropout
8.1.4 Reverse Current
As with most LDOs, excessive reverse current can damage this device.
Reverse current flows through the body diode on the pass element instead of the normal conducting channel. At
high magnitudes, this current flow degrades the long-term reliability of the device, as a result of one of the
following conditions:
• Degradation caused by electromigration
• Excessive heat dissipation
• Potential for a latch-up condition
Conditions where reverse current can occur are outlined in this section, all of which can exceed the absolute
maximum rating of VOUT > VIN + 0.3 V:
• If the device has a large COUT and the input supply collapses with little or no load current
• The output is biased when the input supply is not established
• The output is biased above the input supply
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Application Information (continued)
If reverse current flow is expected in the application, external protection must be used to protect the device.
Figure 29 shows one approach of protecting the device.
Schottky Diode
IN
CIN
Internal Body Diode
OUT
Device
COUT
GND
Figure 29. Example Circuit for Reverse Current Protection Using a Schottky Diode
8.1.5 Power Dissipation (PD)
Circuit reliability demands that proper consideration be given to device power dissipation, location of the circuit
on the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator
must be as free of other heat-generating devices as possible that cause added thermal stresses.
As a first-order approximation, power dissipation in the regulator depends on the input-to-output voltage
difference and load conditions. Use Equation 2 to approximate PD:
PD = (VIN – VOUT) × IOUT
(2)
Power dissipation must be minimized to achieve greater efficiency. This minimizing process is achieved by
selecting the correct system voltage rails. Proper selection helps obtain the minimum input-to-output voltage
differential. The low dropout of the device allows for maximum efficiency across a wide range of output voltages.
The main heat-conduction path for the device is through the thermal pad on the package. As such, the thermal
pad must be soldered to a copper pad area under the device. This pad area contains an array of plated vias that
conduct heat to inner plane areas or to a bottom-side copper plane.
The maximum allowable junction temperature (TJ) determines the maximum power dissipation for the device.
According to Equation 3, power dissipation and junction temperature are most often related by the junction-toambient thermal resistance (RθJA) of the combined PCB, device package, and the temperature of the ambient air
(TA).
TJ = TA + RθJA × PD
(3)
Unfortunately, this thermal resistance (RθJA) is dependent on the heat-spreading capability built into the particular
PCB design, and therefore varies according to the total copper area, copper weight, and location of the planes.
The RθJA value is only used as a relative measure of package thermal performance. RθJA is the sum of the
package junction-to-case (bottom) thermal resistance (RθJCbot) plus the thermal resistance contribution by the
PCB copper.
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Application Information (continued)
8.1.5.1 Estimating Junction Temperature
The JEDEC standard recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures of
the LDO when in-circuit on a typical PCB board application. These metrics are not thermal resistances, but offer
practical and relative means of estimating junction temperatures. These psi metrics are independent of the
copper-spreading area. The key thermal metrics (ΨJT and ΨJB) are used in accordance with Equation 4 and are
described in the table.
YJT: TJ = TT + YJT ´ PD
YJB: TJ = TB + YJB ´ PD
where:
•
•
•
PD is the power dissipated as shown in Equation 2
TT is the temperature at the center-top of the device package
TB is the PCB surface temperature measured 1 mm from the device package and centered on the package
edge
(4)
8.2 Typical Application
IN
OUT
1 …F
DC/DC
Converter
1 …F
TLV755P
EN
Load
GND
ON
OFF
Figure 30. TLV755P Typical Application
8.2.1 Design Requirements
Table 2 lists the design requirements for this application.
Table 2. Design Parameters
PARAMETER
DESIGN REQUIREMENT
Input voltage
4.3 V
Output voltage
3.3 V
Input current
500 mA (maximum)
Output load
250-mA DC
Maximum ambient temperature
70°C
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8.2.2 Detailed Design Procedure
8.2.2.1 Input Current
During normal operation, the input current to the LDO is approximately equal to the output current of the LDO.
During startup, the input current is higher as a result of the inrush current charging the output capacitor. Use
Equation 5 to calculate the current through the input.
VOUT(t)
COUT ´ dVOUT(t)
IOUT(t) =
+
RLOAD
dt
where:
•
•
•
VOUT(t) is the instantaneous output voltage of the turn-on ramp
dVOUT(t) / dt is the slope of the VOUT ramp
RLOAD is the resistive load impedance
(5)
8.2.2.2 Thermal Dissipation
The junction temperature can be determined using the junction-to-ambient thermal resistance (RθJA) and the total
power dissipation (PD). Use Equation 6 to calculate the power dissipation. Multiply PD by RθJA as Equation 7
shows and add the ambient temperature (TA) to calculate the junction temperature (TJ).
PD = (IGND+ IOUT) × (VIN – VOUT)
TJ = RθJA × PD + TA
(6)
(7)
Calculate the maximum ambient temperature as Equation 8 shows if the (TJ(MAX)) value does not exceed 125°C.
Equation 9 calculates the maximum ambient temperature with a value of 99.95°C.
TA(MAX) = TJ(MAX) – RθJA × PD
TA(MAX) = 125°C – 100.2°C/W × (4.3 V – 3.3 V) × (0.25 A) = 99.95°C
(8)
(9)
8.2.3 Application Curve
Power Supply Rejection Ratio (dB)
100
80
60
40
20
0
10
IOUT = 10 mA
IOUT = 50 mA
IOUT = 100 mA
IOUT = 500 mA
100
1k
10k
100k
Frequency (Hz)
1M
10M
VIN = 4.3 V, VOUT = 3.3 V
Figure 31. PSRR vs Frequency (4.3 V to 3.3 V)
9 Power Supply Recommendations
Connect a low output impedance power supply directly to the IN pin of the TLV755P. If the input source is
reactive, consider using multiple input capacitors in parallel with the 1-µF input capacitor to lower the input supply
impedance over frequency.
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10 Layout
10.1 Layout Guidelines
•
•
•
Place input and output capacitors as close as possible to the device.
Use copper planes for device connections to optimize thermal performance.
Place thermal vias around the device to distribute the heat.
10.2 Layout Examples
OUT
IN
1
4
COUT
CIN
EN
3
2
GND PLANE
Represents via used for application
specific connections
Figure 32. Layout Example for the DQN Package
VOUT
VIN
1
CIN
5
COUT
2
3
4
EN
GND PLANE
Represents via used for
application specific connections
Figure 33. Layout Example for the DBV Package
VIN
VOUT
COUT
1
6
2
5
3
4
CIN
EN
GND PLANE
Represents via used for
application specific connections
Figure 34. Layout Example for the DRV Package
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Device Nomenclature
Table 3. Device Nomenclature (1) (2)
(1)
(2)
PRODUCT
VOUT
TLV755xx(x)Pyyyz
xx(x) is the nominal output voltage. For output voltages with a resolution of 100 mV, two digits are used
in the ordering number; otherwise, three digits are used (for example, 28 = 2.8 V; 125 = 1.25 V).
P indicates an active output discharge feature. All members of the TLV755P family actively discharge
the output when the device is disabled.
yyy is the package designator.
z is the package quantity. R is for reel (3000 pieces), T is for tape (250 pieces).
For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the
device product folder on www.ti.com.
Output voltages from 0.6 V to 5 V in 50-mV increments are available. Contact the factory for details and availability.
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TLV75507PDQNR
ACTIVE
X2SON
DQN
4
3000
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
KD
TLV75507PDQNT
ACTIVE
X2SON
DQN
4
250
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
KD
TLV75509PDBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
Level-1-260C-UNLIM
-40 to 125
1HAF
TLV75509PDQNR
ACTIVE
X2SON
DQN
4
3000
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
AX
TLV75509PDQNT
ACTIVE
X2SON
DQN
4
250
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
AX
TLV75509PDRVR
ACTIVE
WSON
DRV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
1HDH
TLV75510PDBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
1FPF
TLV75510PDQNR
ACTIVE
X2SON
DQN
4
3000
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
KE
TLV75510PDQNT
ACTIVE
X2SON
DQN
4
250
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
KE
TLV75510PDRVR
ACTIVE
WSON
DRV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
1GUH
TLV75511PDQNR
ACTIVE
X2SON
DQN
4
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
E8
TLV75512PDBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
1FQF
TLV75512PDQNR
ACTIVE
X2SON
DQN
4
3000
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
AG
TLV75512PDQNT
ACTIVE
X2SON
DQN
4
250
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
AG
TLV75512PDRVR
ACTIVE
WSON
DRV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
1GVH
TLV75515PDBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
1FRF
TLV75515PDQNR
ACTIVE
X2SON
DQN
4
3000
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
KF
TLV75515PDQNT
ACTIVE
X2SON
DQN
4
250
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
KF
TLV75515PDRVR
ACTIVE
WSON
DRV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
1GWH
TLV755185PDQNR
ACTIVE
X2SON
DQN
4
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
EZ
NIPDAU | SN
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
10-Dec-2020
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
NIPDAU | SN
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TLV75518PDBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
Level-1-260C-UNLIM
-40 to 125
1FSF
TLV75518PDQNR
ACTIVE
X2SON
DQN
4
3000
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
AI
TLV75518PDQNT
ACTIVE
X2SON
DQN
4
250
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
AI
TLV75518PDRVR
ACTIVE
WSON
DRV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
1GXH
TLV75519PDBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
1HBF
TLV75519PDQNR
ACTIVE
X2SON
DQN
4
3000
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
B5
TLV75519PDQNT
ACTIVE
X2SON
DQN
4
250
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
B5
TLV75519PDRVR
ACTIVE
WSON
DRV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
1HEH
TLV75525PDBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
1FTF
TLV75525PDQNR
ACTIVE
X2SON
DQN
4
3000
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
AJ
TLV75525PDQNT
ACTIVE
X2SON
DQN
4
250
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
AJ
TLV75525PDRVR
ACTIVE
WSON
DRV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
1GZH
TLV75528PDBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
1FUF
TLV75528PDQNR
ACTIVE
X2SON
DQN
4
3000
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
KG
TLV75528PDQNT
ACTIVE
X2SON
DQN
4
250
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
KG
TLV75528PDRVR
ACTIVE
WSON
DRV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
1H1H
TLV75529PDBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
1HCF
TLV75529PDRVR
ACTIVE
WSON
DRV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
1HFH
TLV75530PDBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
1FVF
TLV75530PDQNR
ACTIVE
X2SON
DQN
4
3000
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
KI
TLV75530PDQNT
ACTIVE
X2SON
DQN
4
250
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
KI
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
10-Dec-2020
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TLV75530PDRVR
ACTIVE
WSON
DRV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
1H2H
TLV75533PDBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
1FWF
TLV75533PDQNR
ACTIVE
X2SON
DQN
4
3000
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
AN
TLV75533PDQNT
ACTIVE
X2SON
DQN
4
250
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
AN
TLV75533PDRVR
ACTIVE
WSON
DRV
6
3000
RoHS & Green
Level-1-260C-UNLIM
-40 to 125
1H3H
NIPDAU
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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