TLV767
SLVSE84D – DECEMBER 2017 – REVISED JULY 2021
TLV767 1-A, 16-V Precision Linear Voltage Regulator
1 Features
3 Description
•
•
The TLV767 is a wide input linear voltage regulator
supporting an input voltage range from 2.5 V to 16 V
and up to 1 A of load current. The output range is
from 0.8 V to 6.6 V or up to 14.6 V in the adjustable
version.
VIN: 2.5 V to 16 V
VOUT:
– 0.8 V to 14.6 V (adjustable)
– 0.8 V to 6.6 V (fixed, 50-mV steps)
1% output accuracy over load and temperature
Low IQ: 50 µA (typical, ~1.5 µA in shutdown)
Internal soft-start time: 500 µs (typical)
Fold-back current limiting and thermal protection
Stable with 1-µF ceramic capacitors
High PSRR: 70 dB at 1 kHz, 46 dB at 1 MHz
Temperature range: –40°C to +125°C
Packages:
– 6-pin 2-mm × 2-mm WSON
– 8-pin 3-mm x 3-mm HVSSOP
– 5-pin 2.9-mm x 1.6-mm SOT-23
•
•
•
•
•
•
•
•
Additionally, the TLV767 has a 1% output
accuracy that can meet the needs of low voltage
microcontrollers (MCUs) and processors.
The TLV767 is designed to have a much lower
IQ than traditional wide-VIN regulators, thus making
the device well positioned to meet the needs of
increasingly stringent standby power requirements.
When disabled, the TLV767 draws only 1.5 µA of IQ.
The internal soft-start time and foldback current limit
reduce inrush current during start up, thus minimizing
input capacitance.
2 Applications
•
•
•
•
•
•
Appliances
TVs, monitors, and set top boxes
Motion detectors (PIR, uWave, and so forth)
Motor drives and control boards
Printers and PC peripherals
Wi-Fi access points and routers
Wide bandwidth PSRR performance is greater than
70 dB at 1 kHz and 46 dB at 1 MHz, which helps
attenuate the switching frequency of an upstream
DC/DC converter and minimizes post regulator
filtering. To allow for more flexibility, the TLV767 has
both fixed and adjustable versions.
9
0.75
8
0.5
7
0.25
6
0
5
-0.25
VOUT
IIN
VIN
VEN
4
3
-0.5
-0.75
2
-1
1
-1.25
0
-1.5
-1
Device Information(1)
PART
NUMBER
Current (A)
Voltage (V)
The TLV767 is available in a 6-pin, 2-mm × 2-mm
WSON (DRV), an 8-pin 3-mm x 3-mm HVSSOP
(DGN), and a 5-pin 2.9-mm x 1.6-mm SOT-23 (DBV)
package.
TLV767
(1)
0.5
1
1.5
2
2.5
3
Time (ms)
3.5
4
4.5
BODY SIZE (NOM)
WSON (6)
2.00 mm × 2.00 mm
HVSSOP (8)
3.00 mm x 3.00 mm
SOT-23 (5)
2.90 mm x 1.60 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
OUT
IN
-1.75
0
PACKAGE
5
D003
Reduced Inrush Current With 22 µF at COUT
CIN
EN
R1
TLV767
CFF
(opt.)
COUT
FB
GND
R2
Typical Application Circuit
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLV767
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SLVSE84D – DECEMBER 2017 – REVISED JULY 2021
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings ....................................... 5
6.2 ESD Ratings .............................................................. 5
6.3 Recommended Operating Conditions ........................5
6.4 Thermal Information ...................................................6
6.5 Electrical Characteristics ............................................6
7 Typical Characteristics................................................... 8
8 Detailed Description......................................................14
8.1 Overview................................................................... 14
8.2 Functional Block Diagrams....................................... 14
8.3 Feature Description...................................................15
8.4 Device Functional Modes..........................................18
9 Application and Implementation.................................. 19
9.1 Application Information............................................. 19
9.2 Typical Application.................................................... 22
10 Power Supply Recommendations..............................23
11 Layout........................................................................... 24
11.1 Layout Guidelines................................................... 24
11.2 Layout Examples.....................................................24
12 Device and Documentation Support..........................25
12.1 Device Support....................................................... 25
12.2 Documentation Support.......................................... 25
12.3 Receiving Notification of Documentation Updates..25
12.4 Support Resources................................................. 25
12.5 Trademarks............................................................. 25
12.6 Electrostatic Discharge Caution..............................25
12.7 Glossary..................................................................25
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (June 2020) to Revision D (July 2021)
Page
• Added DBV (SOT-23) package to document......................................................................................................1
• Changed VOUT adjustable Features bullet from 0.8 V to 13.6 V (adjustable) to 0.8 V to 14.6 V (adjustable) ..1
• Changed maximum output range for adjustable version from 13.6 V to 14.6 V ................................................ 1
• Added DBV pinout and pin information to Pin Configuration and Functions section.......................................... 3
• Added Layout Example for the Fixed DBV Version figure to the Layout Examples section............................. 24
Changes from Revision B (April 2019) to Revision C (June 2020)
Page
• Added DGN (HVSSOP) package to document...................................................................................................1
• Changed Applications section............................................................................................................................ 1
• Added DGN pinouts and pin information to Pin Configuration and Functions section........................................3
• Added HVSSOP thermal information .................................................................................................................6
• Added Layout Example for the Fixed HVSSOP Version and Layout Example for the Adjustable HVSSOP
Version figures to the Layout Examples section............................................................................................... 24
2
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SLVSE84D – DECEMBER 2017 – REVISED JULY 2021
5 Pin Configuration and Functions
OUT
1
FB
6
IN
1
GND
EN
2 Thermal 5
GND
SNS
3
EN
GND
3
4
Not to scale
1
FB
2
IN
4
Not to scale
Figure 5-1. DRV Package (Adjustable), 6-Pin
WSON,
Top View
OUT
6
Thermal
2
5
pad
pad
GND
OUT
Figure 5-2. DRV Package (Fixed), 6-Pin WSON,
Top View
8
IN
OUT
1
7
NC
SNS
2
Thermal pad
8
IN
7
NC
Thermal pad
NC
3
6
GND
NC
3
6
GND
GND
4
5
EN
GND
4
5
EN
Not to scale
Not to scale
Figure 5-3. DGN Package (Adjustable),
8-Pin HVSSOP, Top View
Figure 5-4. DGN Package (Fixed), 8-Pin HVSSOP,
Top View
IN
1
GND
2
EN
3
5
OUT
4
DNC
Not to scale
Figure 5-5. DBV Package (Fixed),
5-Pin SOT-23, Top View
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SLVSE84D – DECEMBER 2017 – REVISED JULY 2021
Table 5-1. Pin Functions
PIN
NAME
DRV
(Fixed)
DGN
(Adj)
DGN
(Fixed)
DBV
(Fixed)
I/O
DESCRIPTION
EN
4
4
5
5
3
I
Enable pin. Driving the enable pin high enables the device.
Driving this pin low disables the device. High and low
thresholds are listed in the Electrical Characteristics table.
This pin has an internal pullup and can be left floating to
enable the device or the pin can be connected to the input
pin.
FB
2
—
2
—
—
I
Feedback pin. Input to the control-loop error amplifier. This
pin is used to set the output voltage of the device with
the use of external resistors. Do not float this pin. For
adjustable-voltage version devices only.
GND
3, 5
3, 5
4, 6
4, 6
2
—
Ground pin. All ground pins must be grounded.
DNC
—
—
—
—
4
—
Do not connect to a biased voltage. Tie this pin to ground or
leave floating
IN
6
6
8
8
1
I
Input pin. Use the recommended capacitor value as listed
in the Recommended Operating Conditions table. Place the
input capacitor as close to the IN and GND pins of the
device as possible.
O
Output pin. Use the recommended capacitor value as listed
in the Recommended Operating Conditions table. Place the
output capacitor as close to the OUT and GND pins of the
device as possible.
OUT
1
SNS
Thermal
pad
4
DRV
(Adj)
1
1
1
5
—
2
—
2
—
I
Output sense pin. Connect the SNS pin to the OUT pin, or
to remotely sense the output voltage at the load, connect
the SNS pin to the load. Do not float this pin. For fixedvoltage version devices only.
Pad
Pad
Pad
Pad
—
—
Exposed pad of the package. Connect this pad to ground
or leave floating. Connect the thermal pad to a large-area
ground plane for best thermal performance.
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6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)(1)
MIN
Voltage(2)
VIN
–0.3
18
VOUT (3)
–0.3
VIN + 0.3
VSNS (3)
–0.3
VIN + 0.3
VFB
–0.3
3
–0.3
18
VEN
Current
Temperature
(1)
(2)
(3)
MAX
Maximum output current
UNIT
V
Internally Limited
A
Operating junction (TJ)
–50
150
Storage (TSTG)
–65
150
°C
Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated
under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
All voltages with respect to GND.
VIN + 0.3 V or 18 V (whichever is smaller)
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/
JEDEC JS-001, all pins(1)
±3000
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins(2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VIN
Input voltage
2.5
16
V
VEN
Enable voltage
0
16
V
VOUT
Output voltage
0.8
14.6
V
IOUT
Output current (2.5 V ≤ VIN < 3 V)
0
0.8
A
IOUT
Output current (VIN ≥ 3 V)
0
COUT
Output capacitor(1)
1
COUT ESR
Output capacitor ESR
2
CIN
Input capacitor
CFF
Feed-forward capacitor (optional(2), for adjustable device only)
current(2)
IFB_DIVIDER
Feedback divider
TJ
Junction temperature
(1)
(2)
(adjustable device only)
2.2
1
A
220
µF
500
mΩ
1
µF
10
pF
5
–40
µA
125
°C
Effective output capacitance of 0.5 µF minimum required for stability.
CFF required for stability if the feedback divider current < 5 µA. Feedback divider current = VOUT / (R1 + R2). See Feed-Forward
Capacitor (CFF) section for details.
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6.4 Thermal Information
TLV767
THERMAL
METRIC(1)
DBV (SOT23)
DGN (HVSSOP)
DRV (WSON)
5 PINS
8 PINS
6 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
165.7
60.1
77.7
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
61.6
81.7
92.3
°C/W
RθJB
Junction-to-board thermal resistance
37.9
32.8
40.8
°C/W
ΨJT
Junction-to-top characterization parameter
11.6
6
4.3
°C/W
ΨJB
Junction-to-board characterization parameter
37.6
32.7
40.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
15.5
18.9
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
Specified at TJ = –40°C to 125°C, VIN = VOUT(nom) + 1.5 V or VIN = 2.5 V (whichever is greater), FB/SNS tied to OUT, IOUT =
10 mA, VEN = 2 V, CIN = 1.0 µF, COUT = 1.0 µF (unless otherwise noted). Typical values are at TJ= 25ºC.
PARAMETER
VOUT
Nominal output accuracy
TEST CONDITIONS
TJ = 25°C
–0.5
0.5
–1
1
2.5 V ≤ VIN < 3.0 V, 1 mA ≤ IOUT ≤ 800 mA
–1
1
Output accuracy over temperature
VFB
Feedback voltage
VREF
Internal reference (adjustable device)
IFB
Feedback pin current
VFB = 1 V
ΔVOUT(ΔVIN)
Line regulation(1)
VOUT(NOM) +1.5 V ≤ VIN ≤ 16 V, IOUT = 10 mA
Dropout voltage(2)
VDO
TYP MAX
VIN ≥ 3.0 V, 1 mA ≤ IOUT ≤ 1 A
VOUT
ΔVOUT(ΔIOUT) Load regulation
MIN
0.8
TJ = 25ºC
0.5
–1
1
6
ICL
Output current limit
ISC
Short-circuit current limit
50
0.02
1 mA ≤ IOUT ≤ 1 A, VIN ≥ 3.0 V
0.1
0.5
1 mA ≤ IOUT ≤ 800 mA, 2.5 V ≤ VIN < 3.0 V
0.1
0.5
VIN ≥ 3.0V, IOUT = 1 A, DGN package
0.9
1.5
VIN ≥ 3.0V, IOUT = 1 A, DRV package
0.9
1.4
0.8
1.3
2.5 V ≤ VIN < 3.0 V, IOUT = 800 mA
VOUT = 0.9 x VOUT(NOM) , VIN ≥ 3.0V
VOUT = 0.9 x VOUT(NOM), 2.5 V ≤ VIN < 3.0 V
1.1
1.6
0.81
1.6
VOUT = 0 V, DGN package
250
VOUT = 0 V, DRV package
150
%
%
V
–0.5
10
UNIT
%
nA
%/V
%/A
V
A
mA
250
350
IOUT = 0 mA
50
80
Fixed output devices, IOUT = 0 mA
60
95
1.5
mA
IQ
Quiescent current
IGND
Ground current
IOUT = 1 A, VIN ≥ 3.0 V
ISHUTDOWN
Shutdown current
VEN ≤ 0.4 V, VIN = 16 V
VEN(HIGH)
Enable pin logic high
2.5 V ≤ VIN ≤ 16 V
VEN(LOW)
Enable pin logic low
2.5 V ≤ VIN ≤ 16 V
IEN
Enable pullup current
VEN = 0 V
400
nA
IPULLDOWN
Output pulldown current
VIN = 16 V, VOUT = 2.5 V, VEN=0V
1.2
mA
PSRR
Power-supply rejection ratio
VIN = 3.3 V, VOUT = 1.8 V, IOUT = 300 mA, f = 120 Hz
70
dB
Vn
Output noise voltage
BW = 10 Hz to 100 kHz, VIN = 3.3 V, VOUT = 0.8 V,
IOUT = 100 mA
60
µVRMS
VUVLO+
UVLO threshold rising
VIN rising
2.2
VUVLO(HYS)
UVLO hysteresis
1.5
mA
3
1.2
µA
V
0.4
130
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µA
2.4
V
V
mV
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6.5 Electrical Characteristics (continued)
Specified at TJ = –40°C to 125°C, VIN = VOUT(nom) + 1.5 V or VIN = 2.5 V (whichever is greater), FB/SNS tied to OUT, IOUT =
10 mA, VEN = 2 V, CIN = 1.0 µF, COUT = 1.0 µF (unless otherwise noted). Typical values are at TJ= 25ºC.
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UVLO threshold falling
VIN falling
TSD(shutdown)
Thermal shutdown temperature
Temperature increasing
180
ºC
TSD(reset)
Thermal shutdown reset temperature
Temperature falling
160
ºC
(1)
(2)
1.9
UNIT
VUVLO-
V
Line regulation is measured with VIN = VOUT(NOM) + 1.5 V or 2.5 V (whichever is greater)
VDO is measured with VIN = 95% x VOUT(nom) for fixed output devices. VDO is not measured for fixed output devices when VOUT < 2.5 V.
For adjustable output device, VDO is measured with VFB = 95% x VFB(nom)
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7 Typical Characteristics
at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 1.5 V or 2.5 V (whichever is greater), IOUT = 10 mA, VEN = 2.0 V, CIN =
1.0 µF, and COUT = 1.0 µF (unless otherwise noted)
VOUT)
0.2
0.1
Output Voltage Accuracy (
Output Voltage Accuracy (
VOUT)
0.2
0
-0.1
-0.2
TJ
-0.3
-50°C
-40°C
0°C
25°C
85°C
125°C
150°C
0.1
0.2
0.3
0
-0.1
-0.2
TJ
-0.3
-50°C
-40°C
0°C
25°C
0.4 0.5 0.6 0.7
Output Current (A)
0.8
0.9
0
1
0.1
0.2
Quiescent Current in Shutdown (uA)
VOUT)
0.6
0.7
0.8
14
16
5
0.2
Output Voltage Accuracy (
0.3
0.4
0.5
Output Current (A)
Figure 7-2. VOUT Accuracy vs IOUT
Figure 7-1. VOUT Accuracy vs IOUT
0.1
0
-0.1
-0.2
-0.4
2.5
150°C
VIN = 2.5 V
VIN = 3.0 V
-0.3
85°C
125°C
-0.4
-0.4
0
0.1
TJ
-50°C
-40°C
4
0°C
25°C
5.5
7
85°C
125°C
150°C
8.5
10
11.5
Input Voltage (V)
13
14.5
TJ
25°C
85°C
125°C
-50°C
-40°C
0°C
4
150°C
3
2
1
0
16
0
2
IOUT = 10 mA
4
6
8
10
Input Voltage (V)
12
Figure 7-4. ISHUTDOWN vs VIN
80
90
70
80
Quiescent Current (PA)
Quiescent Current (PA)
Figure 7-3. VOUT Accuracy vs VIN
60
50
40
TJ
30
20
2.5
-50°C
-40°C
4.5
6.5
0°C
25°C
8.5
10.5
Input Voltage (V)
70
60
50
40
85°C
125°C
0.8 V
1.8 V
150°C
12.5
14.5
IOUT = 0 mA, adjustable-voltage version devices
16
30
-50
0
25
50
75
Temperature (°C)
100
5.0 V
125
150
IOUT = 0 mA, fixed-voltage version devices
Figure 7-6. IQ vs Temperature
Figure 7-5. IQ vs VIN
8
-25
VOUT
2.8 V
3.3 V
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7 Typical Characteristics (continued)
at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 1.5 V or 2.5 V (whichever is greater), IOUT = 10 mA, VEN = 2.0 V, CIN =
1.0 µF, and COUT = 1.0 µF (unless otherwise noted)
2.5
2.5
TJ
2
Ground Current (mA)
2
Ground Current (mA)
-50°C
-40°C
1.5
1
0.5
-0°C
25°C
0.1
0.2
0.3
1
85°C
125°C
150°C
0.4
0.5 0.6 0.7
Output Current (A)
0
0.8
0.9
0
1
0.1
0.2
Output Current (mA)
Quiescent Current (PA)
100
50
30
10
-10
0.5
1
1.5
2
Input Voltage (V)
2.5
3
IOUT = 0 mA
0
400
-100
300
-200
200
-300
100
-400
0
-500
-100
-600
-200
-700
-300
-800
-400
-900
0
100
-500
900 1000
D021
500
300
-1000
200
-1500
100
-2000
0
-2500
-100
-3000
-200
-3500
-300
-4000
-400
-1750
-500
500
-2000
-4500
350
400
450
AC-Coupled Output Voltage (mV)
-500
250
400
0
300
-250
200
-500
100
-750
0
-1000
-100
-1250
-200
-1500
-300
IOUT
VOUT -400
-500
180 200
0
D034
VIN = 5 V, VOUT = 3.3 V, CFF = 10 pF, ramp rate = 0.5 A/µs
Figure 7-11. IOUT Transient From 1 mA to 1 A
20
40
60
80
100 120
Time (µs)
140
160
AC-Coupled Output Voltage (mV)
600
500
400
200 250 300
Time (µs)
800
700
0
150
700
750
500
100
400 500 600
Time (µs)
1000
700
IOUT 600
VOUT
500
1000
50
300
Figure 7-10. IOUT Transient From 0 mA to 100 mA
Output Current (mA)
1500
0
200
VIN = 5 V, VOUT = 3.3 V, CFF = 10 pF, ramp rate = 0.4 A/µs
Figure 7-9. IQ Increase Below Minimum VIN
Output Current (mA)
700
IOUT 600
VOUT
500
200
70
0
0.8
AC-Coupled Output Voltage (mV)
90
0.7
300
TJ
-50°C
-40°C
0°C
25°C
85°C
125°C
150°C
110
0.6
Figure 7-8. IGND vs IOUT
Figure 7-7. IGND vs IOUT
130
0.3
0.4
0.5
Output Current (A)
VIN = 2.5 V
VIN = 3.0 V
150
150°C
1.5
0
0
85°C
125°C
0.5
TJ
-50°C
-40°C
-0°C
25°C
D035
VIN = 5 V, VOUT = 3.3 V, ramp rate = 0.8 A/µs
Figure 7-12. IOUT Transient From 250 mA to 850 mA
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7 Typical Characteristics (continued)
at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 1.5 V or 2.5 V (whichever is greater), IOUT = 10 mA, VEN = 2.0 V, CIN =
1.0 µF, and COUT = 1.0 µF (unless otherwise noted)
30
600
35
30
200
25
0
20
-200
15
-400
10
-600
5
-800
0
900 1000
0
100
200
300
400 500 600
Time (µs)
700
800
40
VOUT
VIN
20
10
30
0
25
-10
20
-20
15
-30
10
-40
5
-50
0
100
200
300
D037
VOUT = 3.3 V, IOUT = 1 A, VIN ramp rate = 0.6 V/µs
0
900 1000
800
D038
1.4
TJ
1.3
-50°C
-40°C
0°C
25°C
85°C
125°C
1
0.9
0.8
0.8
0.6
7.5
9
10.5
Input Voltage (V)
12
13.5
15
0.5
2.5
16
150°C
1
0.7
6
85°C
125°C
0.9
0.6
0.5
0°C
25°C
1.1
0.7
4.5
-50°C
-40°C
1.2
1.1
3
TJ
1.3
150°C
Dropout Voltage (V)
1.2
4
5.5
IOUT = 1.0 A
7
8.5
10
11.5
Input Voltage (V)
13
14.5
16
IOUT = 0.8 A
Figure 7-15. VDO vs VIN
Figure 7-16. VDO vs VIN
1.4
1.4
1
TJ
25°C
85°C
125°C
TJ
150°C
-50°C
-40°C
1.2
Dropout Voltage (V)
-50°C
-40°C
0°C
1.2
Dropout Voltage (V)
700
Figure 7-14. VIN Transient From 5 V to 16 V
1.4
0.8
0.6
0.4
0°C
25°C
85°C
125°C
150°C
1
0.8
0.6
0.4
0.2
0.2
0
0
0
0.1
0.2
0.3
0.4
0.5 0.6 0.7
Output Current (A)
0.8
0.9
1
0
0.1
0.2
0.3
0.4
0.5
Output Current (A)
0.6
0.7
0.8
VIN = 2.5 V
VIN = 3.0 V
Figure 7-18. VDO vs IOUT
Figure 7-17. VDO vs IOUT
10
400 500 600
Time (µs)
VOUT = 3.3 V, IOUT = 33 µA, VIN ramp rate = 1.6 V/µs
Figure 7-13. VIN Transient in Dropout From 4 V to 13 V
Dropout Voltage (V)
35
Input Voltage (V)
400
AC-Coupled Output Voltage (mV)
40
VOUT
VIN
Input Voltage (V)
AC-Coupled Output Voltage (mV)
800
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7 Typical Characteristics (continued)
at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 1.5 V or 2.5 V (whichever is greater), IOUT = 10 mA, VEN = 2.0 V, CIN =
1.0 µF, and COUT = 1.0 µF (unless otherwise noted)
150
150
TJ
-50°C
-40°C
0°C
25°C
TJ
85°C
125°C
150°C
100
75
50
-50°C
-40°C
125
Output Voltage (%)
Output Voltage (%)
125
25
150°C
100
75
50
0
0
0.2
0.4
0.6
0.8
1
Output Current (A)
1.2
1.4
1.6
0
0.2
0.4
VIN = 3.0 V
0.6
0.8
1
Output Current (A)
1.2
1.4
Figure 7-20. Foldback Current Limit vs Temperature
5.5
5.5
VOUT
VIN
VEN
4.5
1.6
VIN = 2.5 V
Figure 7-19. Foldback Current Limit vs Temperature
5
VOUT
VIN
VEN
5
4.5
4
4
3.5
3.5
Voltage (V)
Voltage (V)
85°C
125°C
25
0
3
2.5
2
3
2.5
2
1.5
1.5
1
1
0.5
0.5
0
0
-0.5
-0.5
0
0.5
1
1.5
2
2.5
3
Time (ms)
3.5
4
4.5
0
5
0.5
1
1.5
D032
2
2.5
3
Time (ms)
3.5
4
4.5
5
D004
Enable pulled up internally, VOUT = 0.8 V
VOUT = 3.3 V
Figure 7-22. Startup With VEN Floating
Figure 7-21. Startup With Separate VEN and VIN
0.9
0.9
VEN(HIGH)
VEN(LOW)
0.85
Enable Voltage (V)
0.85
Enable Voltage (V)
0°C
25°C
0.8
0.75
0.7
0.8
0.75
0.7
0.65
0.65
0.6
-50
-25
0
25
50
75
Temperature (qC)
100
125
150
VEN(HIGH)
VEN(LOW)
0.6
-50
VIN = 2.5 V
-25
0
25
50
75
Temperature (qC)
100
125
150
VIN = 16 V
Figure 7-23. VEN Thresholds vs Temperature
Figure 7-24. VEN Thresholds vs Temperature
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7 Typical Characteristics (continued)
at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 1.5 V or 2.5 V (whichever is greater), IOUT = 10 mA, VEN = 2.0 V, CIN =
1.0 µF, and COUT = 1.0 µF (unless otherwise noted)
100
2.3
Input Voltage (V)
2.25
Power Supply Rejection Ratio (dB)
VUVLO+ (VIN rising)
VUVLO- (VIN falling)
2.2
2.15
2.1
2.05
2
-50
-25
0
25
50
75
Temperature (qC)
100
125
90
80
70
60
50
40
30
IOUT
60 mA
300 mA
550 mA
1.0 A
20
10
0
10
150
100
1k
10k
100k
Frequency (Hz)
1M
10M
1M
10M
VOUT = 1.8 V, VIN = 3.3 V, CFF = 1 nF
Figure 7-26. PSRR vs IOUT
100
100
90
90
Power Supply Rejection Ratio (dB)
Power Supply Rejection Ratio (dB)
Figure 7-25. UVLO Thresholds vs Temperature
80
70
60
50
40
30
2.8
3.0
3.3
3.5
20
10
0
10
VIN
V
V
V
V
100
3.8 V
4.0 V
4.3 V
1k
10k
100k
Frequency (Hz)
1M
80
70
60
50
40
30
20
CFF
0 nF
1.0 nF
10
0
10
10M
100
1k
10k
100k
Frequency (Hz)
D001
VOUT = 1.8 V, IOUT = 0.55 A, CFF = 1 nF
VOUT = 3.3 V, VIN = 4.8 V, IOUT = 0.33 A
Figure 7-27. PSRR vs VIN
Figure 7-28. PSRR vs CFF
700
20
5
Enable Pullup Current (nA)
Output Voltage Noise (PV —Hz)
10
2
1
0.5
0.2
0.1
0.05
0.02
0.01
0.005
10
VOUT
0.8 V, RMS Noise = 66.4 PV RMS
3.3 V, RMS Noise = 216.5 PV RMS
100
1k
10k
100k
Frequency (Hz)
600
500
400
300
1M
10M
100
2.5
CFF = 0 nF, IOUT = 0.1 A, RMS noise BW = 10 Hz to 100 kHz
Figure 7-29. Output Noise (Vn) vs VOUT
12
TJ
200
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-50°C
-40°C
4.5
6.5
0°C
25°C
8.5
10.5
Input Voltage (V)
85°C
125°C
12.5
150°C
14.5
16
VEN = 0 V
Figure 7-30. IEN vs VIN
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7 Typical Characteristics (continued)
at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 1.5 V or 2.5 V (whichever is greater), IOUT = 10 mA, VEN = 2.0 V, CIN =
1.0 µF, and COUT = 1.0 µF (unless otherwise noted)
1.5
100
VIN
2.5 V
7.5 V
12.5 V
16 V
Feedback Pin Current (nA)
Output Pulldown Current (mA)
90
1.4
1.3
1.2
1.1
TJ
25°C
85°C
125°C
-50°C
-40°C
0°C
1
0.9
2.5
4.5
6.5
8.5
10.5
Input Voltage (V)
12.5
150°C
80
70
60
50
40
30
20
10
0
14.5
-10
-50
16
-25
0
100
125
Figure 7-32. IFB vs Temperature
Figure 7-31. IPULLDOWN vs VIN
0.75
8
0.5
7
0.25
7
0.25
6
0
6
0
5
-0.25
VOUT
IIN
VIN
VEN
3
-0.5
-0.75
Voltage (V)
9
0.5
5
-0.25
VOUT
IIN
VIN
VEN
4
3
-0.5
-0.75
2
-1
2
-1
1
-1.25
1
-1.25
0
-1.5
0
-1.5
-1.75
-1
-1
0
0.5
1
1.5
2
2.5
3
Time (ms)
3.5
4
4.5
5
Current (A)
0.75
8
Current (A)
9
4
150
VFB = 1.0 V
VOUT = 2.5 V
Voltage (V)
25
50
75
Temperature (°C)
-1.75
0
0.5
D003
VOUT = 3.3 V, IOUT = 33 µA
1
1.5
2
2.5
3
Time (ms)
3.5
4
4.5
5
D031
VOUT = 3.3 V, IOUT = 33 µA
Figure 7-33. Startup Inrush Current With COUT = 22 µF
Figure 7-34. Startup Inrush Current With COUT = 47 µF
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8 Detailed Description
8.1 Overview
The TLV767 is a low quiescent current, high PSRR linear regulator capable of handling up to 1 A of load current.
Unlike typical high current linear regulators, the TLV767 consumes significantly less quiescent current. This
device is ideal for high current applications that require very sensitive power-supply rails.
This device features integrated foldback current limit, thermal shutdown, output enable, internal output pulldown
and undervoltage lockout (UVLO). This device delivers excellent line and load transient performance. This
device is low noise and exhibits a very good PSRR. The operating ambient temperature range of the device is
–40°C to +125°C.
8.2 Functional Block Diagrams
Current Limit
IN
OUT
+
–
Internal
Controller
UVLO
FB
0.8-V
Reference
EN
Thermal
Shutdown
Output
Pulldown
GND
Figure 8-1. Adjustable Version Block Diagram
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Current Limit
IN
OUT
SNS
+
±
R1
2 pF
Internal
Controller
UVLO
0.8-V
Reference
EN
R2
Thermal
Shutdown
Output
Pulldown
Internal Resistors
R1
531 kŸ or 1.062 MŸ
R2
66.9 kŸ ± 8.5 MŸ
GND
Figure 8-2. Fixed Version Block Diagram
8.3 Feature Description
8.3.1 Output Enable
The enable pin for the device is an active-high pin. The output voltage is enabled when the voltage of the enable
pin is greater than the high-level input voltage of the EN pin and disabled with the enable pin voltage is less than
the low-level input voltage of the EN pin. If independent control of the output voltage is not needed, connect the
enable pin to the input of the device.
This device has an internal pullup current on the EN pin. The EN pin can be left floating to enable the device.
The device has an internal pulldown circuit that activates when the device is disabled to actively discharge the
output voltage.
8.3.2 Dropout Voltage
Dropout voltage (VDO) is defined as the input voltage minus the output voltage (VIN – VOUT) at the rated output
current (IRATED), where the pass transistor is fully on. IRATED is the maximum IOUT listed in the Recommended
Operating Conditions table. The pass transistor is in the ohmic or triode region of operation, and acts as a
switch. The dropout voltage indirectly specifies a minimum input voltage greater than the nominal programmed
output voltage at which the output voltage is expected to stay in regulation. If the input voltage falls to less than
the nominal output regulation, then the output voltage falls as well.
For a CMOS regulator, the dropout voltage is determined by the drain-source on-state resistance (RDS(ON)) of the
pass transistor. Therefore, if the linear regulator operates at less than the rated current, the dropout voltage for
that current scales accordingly. The following equation calculates the RDS(ON) of the device.
RDS(ON) =
VDO
IRATED
(1)
8.3.3 Foldback Current Limit
The device has an internal current limit circuit that protects the regulator during transient high-load current faults
or shorting events. The current limit is a hybrid brickwall-foldback scheme. The current limit transitions from a
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brickwall scheme to a foldback scheme at the foldback voltage (VFOLDBACK). In a high-load current fault with
the output voltage above VFOLDBACK, the brickwall scheme limits the output current to the current limit (ICL).
When the voltage drops below VFOLDBACK, a foldback current limit activates that scales back the current as the
output voltage approaches GND. When the output is shorted, the device supplies a typical current called the
short-circuit current limit (ISC). ICL and ISC are listed in the Electrical Characteristics table.
For this device, VFOLDBACK = 50% × VOUT(nom).
The output voltage is not regulated when the device is in current limit. When a current limit event occurs, the
device begins to heat up because of the increase in power dissipation. When the device is in brickwall current
limit, the pass transistor dissipates power [(VIN – V OUT) × ICL]. When the device output is shorted and the output
is below VFOLDBACK, the pass transistor dissipates power [(VIN – VOUT) × ISC]. If thermal shutdown is triggered,
the device turns off. After the device cools down, the internal thermal shutdown circuit turns the device back on.
If the output current fault condition continues, the device cycles between current limit and thermal shutdown. For
more information on current limits, see the Know Your Limits application report.
Figure 8-3 shows a diagram of the foldback current limit.
VOUT
Brickwall
VOUT(NOM)
VFOLDBACK
Foldback
IOUT
0V
0 mA
ISC
IRATED
ICL
Figure 8-3. Foldback Current Limit
8.3.4 Undervoltage Lockout (UVLO)
The device has an independent undervoltage lockout (UVLO) circuit that monitors the input voltage, allowing a
controlled and consistent turn on and off of the output voltage. To prevent the device from turning off if the input
drops during turn on, the UVLO has hysteresis as specified in the Electrical Characteristics table.
8.3.5 Output Pulldown
The device has an output pulldown circuit. VOUT pulldown sink to ground capability is listed in the Electrical
Characteristics table. The output pulldown activates under the following conditions:
•
•
Device disabled
1.0 V < VIN < VUVLO
The output pulldown current for this device is 1.2 mA typical, as listed in the Electrical Characteristics table.
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Do not rely on the output pulldown circuit for discharging a large amount of output capacitance after the input
supply has collapsed because reverse current can flow from the output to the input. This reverse current flow
can cause damage to the device. See the Reverse Current section for more details.
8.3.6 Thermal Shutdown
The device contains a thermal shutdown protection circuit to disable the device when the junction temperature
(TJ) of the pass transistor rises to TSD(shutdown) (typical). Thermal shutdown hysteresis assures that the device
resets (turns on) when the temperature falls to TSD(reset) (typical).
The thermal time-constant of the semiconductor die is fairly short, thus the device may cycle on and off
when thermal shutdown is reached until power dissipation is reduced. Power dissipation during start up can
be high from large VIN – VOUT voltage drops across the device or from high inrush currents charging large
output capacitors. Under some conditions, the thermal shutdown protection disables the device before start up
completes.
For reliable operation, limit the junction temperature to the maximum listed in the Recommended Operating
Conditions table. Operation above this maximum temperature causes the device to exceed its operational
specifications. Although the internal protection circuitry of the device is designed to protect against thermal
overall conditions, this circuitry is not intended to replace proper heat sinking. Continuously running the device
into thermal shutdown or above the maximum recommended junction temperature reduces long-term reliability.
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8.4 Device Functional Modes
8.4.1 Device Functional Mode Comparison
Table 8-1 shows the conditions that lead to the different modes of operation. See the Electrical Characteristics
table for parameter values.
Table 8-1. Device Functional Mode Comparison
PARAMETER
OPERATING MODE
VIN
VEN
IOUT
TJ
Normal operation
VIN > VOUT(nom) + VDO and VIN > VIN(min)
VEN > VEN(HI)
IOUT < IOUT(max)
TJ < TSD(shutdown)
Dropout operation
VIN(min) < VIN < VOUT(nom) + VDO
VEN > VEN(HI)
IOUT < IOUT(max)
TJ < TSD(shutdown)
VIN < VUVLO
VEN < VEN(LOW)
Not applicable
TJ > TSD(shutdown)
Disabled
(any true condition
disables the device)
8.4.2 Normal Operation
The device regulates to the nominal output voltage when the following conditions are met:
•
•
•
The input voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(nom) + VDO)
The output current is less than the current limit (IOUT < ICL)
The device junction temperature is less than the thermal shutdown temperature (TJ < TSD)
•
The enable voltage has previously exceeded the enable rising threshold voltage and has not yet decreased
to less than the enable falling threshold
8.4.3 Dropout Operation
If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other
conditions are met for normal operation, the device operates in dropout mode. In this mode, the output voltage
tracks the input voltage. During this mode, the transient performance of the device becomes significantly
degraded because the pass transistor is in the ohmic or triode region, and acts as a switch. Line or load
transients in dropout can result in large output-voltage deviations.
When the device is in a steady dropout state (defined as when the device is in dropout, VIN < VOUT(NOM) + VDO,
directly after being in a normal regulation state, but not during startup), the pass transistor is driven into the
ohmic or triode region. When the input voltage returns to a value greater than or equal to the nominal output
voltage plus the dropout voltage (VOUT(NOM) + VDO), the output voltage can overshoot for a short period of time
while the device pulls the pass transistor back into the linear region.
8.4.4 Disabled
The output of the device can be shutdown by forcing the voltage of the enable pin to less than the maximum
EN pin low-level input voltage (see the Electrical Characteristics table). When disabled, the pass transistor is
turned off, internal circuits are shutdown, and the output voltage is actively discharged to ground by an internal
discharge circuit from the output to ground.
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
9.1.1 Adjustable Device Feedback Resistors
The adjustable-version device requires external feedback divider resistors to set the output voltage. VOUT is set
using the feedback divider resistors, R1 and R2, according to the following equation:
VOUT = VFB × (1 + R1 / R2)
(2)
To ignore the FB pin current error term in the VOUT equation, set the feedback divider current to 100x the FB pin
current listed in the Electrical Characteristics table. This setting provides the maximum feedback divider series
resistance, as shown in the following equation:
R1 + R2 ≤ VOUT / (IFB × 100)
(3)
9.1.2 Recommended Capacitor Types
The device is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at the input
and output. Multilayer ceramic capacitors have become the industry standard for these types of applications and
are recommended, but must be used with good judgment. Ceramic capacitors that employ X7R-, X5R-, and
C0G-rated dielectric materials provide relatively good capacitive stability across temperature, whereas the use of
Y5V-rated capacitors is discouraged because of large variations in capacitance.
Regardless of the ceramic capacitor type selected, the effective capacitance varies with operating voltage and
temperature. As a rule of thumb, expect the effective capacitance to decrease by as much as 50%. The input
and output capacitors recommended in the Recommended Operating Conditions table account for an effective
capacitance of approximately 50% of the nominal value.
9.1.3 Input and Output Capacitor Requirements
Although an input capacitor is not required for stability, good analog design practice is to connect a capacitor
from IN to GND. This capacitor counteracts reactive input sources and improves transient response, input ripple,
and PSRR. An input capacitor is recommended if the source impedance is more than 0.5 Ω. A higher value
capacitor may be necessary if large, fast rise-time load or line transients are anticipated or if the device is
located several inches from the input power source.
Dynamic performance of the device is improved with the use of an output capacitor. Use an output capacitor
within the range specified in the Recommended Operating Conditions table for stability.
9.1.4 Reverse Current
Excessive reverse current can damage this device. Reverse current flows through the intrinsic body diode of the
pass transistor instead of the normal conducting channel. At high magnitudes, this current flow degrades the
long-term reliability of the device.
Conditions where reverse current can occur are outlined in this section, all of which can exceed the absolute
maximum rating of VOUT ≤ VIN + 0.3 V.
•
•
•
If the device has a large COUT and the input supply collapses with little or no load current
The output is biased when the input supply is not established
The output is biased above the input supply
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If reverse current flow is expected in the application, external protection is recommended to protect the device.
Reverse current is not limited in the device, so external limiting is required if extended reverse voltage operation
is anticipated.
Figure 9-1 shows one approach for protecting the device.
Schottky Diode
IN
CIN
Internal Body Diode
Device
OUT
COUT
GND
Figure 9-1. Example Circuit for Reverse Current Protection Using a Schottky Diode
9.1.5 Feed-Forward Capacitor (CFF)
For the adjustable-voltage version device, a feed-forward capacitor (CFF) can be connected from the OUT pin
to the FB pin. CFF improves transient, noise, and PSRR performance, but is not required for regulator stability.
Recommended CFF values are listed in the Recommended Operating Conditions table. A higher capacitance
CFF can be used; however, the start-up time increases. For a detailed description of CFF tradeoffs, see the Pros
and Cons of Using a Feedforward Capacitor with a Low-Dropout Regulator application report.
CFF and R1 form a zero in the loop gain at frequency fZ, while CFF, R1, and R2 form a pole in the loop gain at
frequency fP. CFF zero and pole frequencies can be calculated from the following equations:
fZ = 1 / (2 × π × CFF × R1)
(4)
fP = 1 / (2 × π × CFF × (R1 || R2))
(5)
CFF ≥ 10 pF is required for stability if the feedback divider current is less than 5 µA. Equation 6 calculates the
feedback divider current.
IFB_Divider = VOUT / (R1 + R2)
(6)
To avoid start-up time increases from CFF, limit the product CFF × R1 < 50 µs.
For an output voltage of 0.8 V with the FB pin tied to the OUT pin, no CFF is used.
9.1.6 Power Dissipation (PD)
Circuit reliability requires consideration of the device power dissipation, location of the circuit on the printed
circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator must have few
or no other heat-generating devices that cause added thermal stress.
To first-order approximation, power dissipation in the regulator depends on the input-to-output voltage difference
and load conditions. The following equation calculates power dissipation (PD).
PD = (VIN – VOUT) × IOUT
(7)
Note
Power dissipation can be minimized, and therefore greater efficiency can be achieved, by correct
selection of the system voltage rails. For the lowest power dissipation use the minimum input voltage
required for correct output regulation.
For devices with a thermal pad, the primary heat conduction path for the device package is through the thermal
pad to the PCB. Solder the thermal pad to a copper pad area under the device. This pad area must contain an
array of plated vias that conduct heat to additional copper planes for increased heat dissipation.
The maximum power dissipation determines the maximum allowable ambient temperature (TA) for the device.
According to the following equation, power dissipation and junction temperature are most often related by the
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junction-to-ambient thermal resistance (RθJA) of the combined PCB and device package and the temperature of
the ambient air (TA).
TJ = TA + (RθJA × PD)
(8)
Thermal resistance (RθJA) is highly dependent on the heat-spreading capability built into the particular PCB
design, and therefore varies according to the total copper area, copper weight, and location of the planes.
The junction-to-ambient thermal resistance listed in the Thermal Information table is determined by the JEDEC
standard PCB and copper-spreading area, and is used as a relative measure of package thermal performance.
9.1.7 Estimating Junction Temperature
The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures
of the linear regulator when in-circuit on a typical PCB board application. These metrics are not thermal
resistance parameters and instead offer a practical and relative way to estimate junction temperature. These
psi metrics are determined to be significantly independent of the copper area available for heat-spreading.
The Thermal Information table lists the primary thermal metrics, which are the junction-to-top characterization
parameter (ψJT) and junction-to-board characterization parameter (ψJB). These parameters provide two methods
for calculating the junction temperature (TJ), as described in the following equations. Use the junction-to-top
characterization parameter (ψJT) with the temperature at the center-top of device package (TT) to calculate
the junction temperature. Use the junction-to-board characterization parameter (ψJB) with the PCB surface
temperature 1 mm from the device package (TB) to calculate the junction temperature.
TJ = TT + ψJT × PD
(9)
where:
•
•
PD is the dissipated power
TT is the temperature at the center-top of the device package
TJ = TB + ψJB × PD
(10)
where
•
TB is the PCB surface temperature measured 1 mm from the device package and centered on the package
edge
For detailed information on the thermal metrics and how to use them, see the Semiconductor and IC Package
Thermal Metrics application report.
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9.2 Typical Application
This section discusses implementing this device for a typical application. Figure 9-2 shows the application circuit.
OUT
IN
CIN
EN
R1
TLV767
CFF
(opt.)
COUT
FB
GND
R2
Figure 9-2. Typical Application Circuit
9.2.1 Design Requirements
Table 9-1 summarizes the design requirements for this application.
Table 9-1. Design Parameters
PARAMETER
DESIGN REQUIREMENT
Input voltage
5V
Output voltage
3.3 V
Output current
100 mA
9.2.2 Detailed Design Procedure
9.2.2.1 Transient Response
As with any regulator, increasing the size of the output capacitor reduces overshoot and undershoot magnitude.
If load transients are expected with ramp rates greater than 0.5 A/µs, use a 2.2-µF or larger output capacitor.
9.2.2.2 Choose Feedback Resistors
For this design example, VOUT is set to 3.3 V. Equation 11 and Equation 12 set the feedback divider resistors for
the desired output voltage:
VOUT = VFB × (1 + R1 / R2)
(11)
R1 + R2 ≤ VOUT / (IFB × 100)
(12)
For improved output accuracy, use Equation 12 and IFB = 50 nA as listed in the Electrical Characteristics table to
calculate the upper limit for series feedback resistance (R1 + R2 ≤ 660 kΩ).
The control-loop error amplifier drives the FB pin to the same voltage as the internal reference (VFB = 0.8 V,
as listed in the Electrical Characteristics table). Use Equation 11 to determine the ratio of R1 / R2 = 3.125. Use
this ratio and solve Equation 12 for R2. Now calculate the upper limit for R2 ≤ 160 kΩ. Select a standard value
resistor for R2 = 160 kΩ.
Reference Equation 11 and solve for R1:
R1 = (VOUT / VFB – 1) × R2
(13)
From Equation 13, R1 = 500 kΩ can be determined. Select a standard value resistor for R1 = 499 kΩ. VOUT =
3.3 V (as determined by Equation 11).
22
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9.2.3 Application Curves
0
400
-100
300
-200
200
-300
100
-400
0
-500
-100
-600
-200
-700
-300
-800
-400
Output Current (mA)
-900
0
100
200
300
400 500 600
Time (µs)
700
800
100
AC-Coupled Output Voltage (mV)
100
700
IOUT 600
VOUT
500
200
-500
900 1000
Power Supply Rejection Ratio (dB)
300
90
80
70
60
50
40
30
20
IOUT
100 mA
10
0
10
100
D021
VIN = 5 V, VOUT = 3.3 V, COUT = 1 µF, CFF = 10 pF
Figure 9-3. Load Transient Response, IOUT 0 mA to
100 mA
1k
10k
100k
Frequency (Hz)
1M
10M
VIN = 5 V, VOUT = 3.3 V, COUT = 1 µF, CFF = 0 pF
Figure 9-4. PSRR Performance
10 Power Supply Recommendations
This device is designed to operate from an input supply voltage range of 2.5 V to 16 V. To ensure that the output
voltage is well regulated and dynamic performance is optimum, the input supply must be at least VOUT(nom)
+ 1.5 V. For 1-A output current operation, the input supply must be 3 V or greater. Connect a low output
impedance power supply directly to the input pin of the TLV767.
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11 Layout
11.1 Layout Guidelines
•
•
•
Place input and output capacitors as close to the device as possible
Use copper planes for device connections to IN, OUT, and GND pins to optimize thermal performance
Place thermal vias around the device to distribute heat
11.2 Layout Examples
VOUT CFF
(opt.)
R1
VIN
COUT
FB
R2
1
6
2
5
3
4
VIN
VOUT
CIN
COUT
GND
EN
1
6
CIN
2
5
GND
3
4
EN
GND PLANE
GND PLANE
Represents via used for application-specific connections
Figure 11-1. Layout Example for the Adjustable
WSON Version
VIN
VOUT
Represents via used for application-specific connections
Figure 11-2. Layout Example for the Fixed WSON
Version
VIN
VOUT
COUT
CFF
COUT
(OPT)
1
8
2
7
3
6
4
5
1
8
2
7
3
6
4
5
R1
CIN
FB
CIN
R2
GND
GND
EN
EN
GND PLANE
GND PLANE
Represents via used for application-specific connections
Represents via used for application-specific connections
Figure 11-3. Layout Example for the Fixed HVSSOP
Version
Figure 11-4. Layout Example for the Adjustable
HVSSOP Version
VOUT
VIN
1
CIN
5
COUT
2
3
4
EN
GND PLANE
Represents via used for
application specific connections
Figure 11-5. Layout Example for the Fixed DBV Version
24
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Device Nomenclature
Table 12-1. Available Options(1)
(1)
PRODUCT
VOUT
TLV767xx(x)yyyz
xx(x) is nominal output voltage. For output voltages with a resolution of 100 mV, two
digits are used in the ordering number; otherwise, three digits are used (for example, 33
= 3.3 V; 125 = 1.25 V). 01 indicates adjustable output version.
yyy is package designator.
z is package quantity. R is for large quantity reel, T is for small quantity reel.
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation see the following:
•
•
•
•
Texas Instruments, TLV767EVM-014 Evaluation module user's guide
Texas Instruments, Pros and cons of using a feedforward capacitor with a low-dropout regulator application
report
Texas Instruments, Know your limits application report
Texas Instruments, Universal low-dropout (LDO) linear voltage regulator MultiPkgLDOEVM-823 evaluation
module user's guide
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
15-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TLV76701DGNR
ACTIVE
HVSSOP
DGN
8
2500
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
2BKX
TLV76701DRVR
ACTIVE
WSON
DRV
6
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
1RMH
TLV76701DRVT
ACTIVE
WSON
DRV
6
250
RoHS & Green NIPDAU | NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
1RMH
TLV76708DGNR
ACTIVE
HVSSOP
DGN
8
2500
RoHS & Green
Level-2-260C-1 YEAR
-40 to 125
2BLX
TLV76708DRVR
ACTIVE
WSON
DRV
6
3000
RoHS & Green NIPDAU | NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
1RNH
TLV76708DRVT
ACTIVE
WSON
DRV
6
250
RoHS & Green NIPDAU | NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
1RNH
TLV76718DGNR
ACTIVE
HVSSOP
DGN
8
2500
RoHS & Green
Level-2-260C-1 YEAR
-40 to 125
2BMX
TLV76718DRVR
ACTIVE
WSON
DRV
6
3000
RoHS & Green NIPDAU | NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
1ROH
TLV76718DRVT
ACTIVE
WSON
DRV
6
250
RoHS & Green NIPDAU | NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
1ROH
TLV76725DGNR
ACTIVE
HVSSOP
DGN
8
2500
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
2GT7
TLV76728DGNR
ACTIVE
HVSSOP
DGN
8
2500
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
2BNX
TLV76728DRVR
ACTIVE
WSON
DRV
6
3000
RoHS & Green NIPDAU | NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
1RPH
TLV76728DRVT
ACTIVE
WSON
DRV
6
250
RoHS & Green NIPDAU | NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
1RPH
TLV76733DGNR
ACTIVE
HVSSOP
DGN
8
2500
RoHS & Green
Level-2-260C-1 YEAR
-40 to 125
2BOX
TLV76733DRVR
ACTIVE
WSON
DRV
6
3000
RoHS & Green NIPDAU | NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
1RQH
TLV76733DRVT
ACTIVE
WSON
DRV
6
250
RoHS & Green NIPDAU | NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
1RQH
TLV76750DGNR
ACTIVE
HVSSOP
DGN
8
2500
RoHS & Green
Level-2-260C-1 YEAR
-40 to 125
2BPX
TLV76750DRVR
ACTIVE
WSON
DRV
6
3000
RoHS & Green NIPDAU | NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
1RRH
TLV76750DRVT
ACTIVE
WSON
DRV
6
250
RoHS & Green NIPDAU | NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
1RRH
TLV76780DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
Level-1-260C-UNLIM
-40 to 125
2D2T
Addendum-Page 1
NIPDAUAG
NIPDAUAG
NIPDAUAG
NIPDAUAG
SN
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
15-Sep-2021
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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