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TLV803, TLV853, TLV863
ZHCS187C – APRIL 2011 – REVISED SEPTEMBER 2015
TLV8x3 具有低电平有效的开漏复位功能的 3 引脚电压监控器
1 特性
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1
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3 说明
3 引脚 SOT23 封装
电源电流：9µA（典型值）
精密电源电压监视器：
2.5V、3V、3.3V 和 5V
具有 200ms 固定延迟时间的
上电复位发生器
与 MAX803 引脚兼容
温度范围：-40°C 至 +125°C
开漏、RESET 输出
TLV8x3 系列监控电路主要为数字信号处理器 (DSP)
以及基于处理器的系统提供电路初始化和时序监控。
TLV803、TLV853 和 TLV863 在功能上是等效的。
TLV853 和 TLV863 分别提供了与 TLV803 不同的替
代引脚分配。
上电期间，RESET 会在电源电压 (VDD) 超出 1.1V 时
置为有效。因此只要满足以下条件，监控电路就会监视
VDD 并将 RESET 保持为有效状态：VDD 保持在阈值电
压 VIT 以下。内部定时器将使输出延迟恢复至待机状态
（高电平），以确保系统正常复位。延迟时间 (td(typ) =
200ms) 从 VDD 超过阈值电压 VIT 后开始。当电源电压
降至阈值电压 VIT 以下时，输出再次变为激活状态（低
电平）。该系列中的所有器件均具有一个通过内部分压
器设定的固定感测阈值电压 (VIT)。
2 应用
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•
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数字信号处理器 (DSP)、微控制器和微处理器
便携式和电池供电类设备
机顶盒
服务器
电器
可编程控制元件
智能仪表
工业设备
车载系统
该产品系列专为 2.5V、3V、 3.3 以及 5V 电源电压而
设计。这些器件采用 3 引脚小外形尺寸晶体管 (SOT)23 封装。TLV803 器件的额定工作温度范围为 -40°C
至 +125°C。
器件信息(1)
器件型号
封装
TLV8x3
SOT-23 (3)
封装尺寸（标称值）
2.92mm × 1.30mm
(1) 要了解所有可用封装，请参见数据表末尾的封装选项附录。
典型应用
3.3-V LDO
3.3 V
5V
OUT
IN
GND
VDD
VDD
DSP/FPGA/ASIC
TLV803S
RESET
RESET
GND
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SBVS157
TLV803, TLV853, TLV863
ZHCS187C – APRIL 2011 – REVISED SEPTEMBER 2015
www.ti.com.cn
目录
1
2
3
4
5
6
7
8
特性 ..........................................................................
应用 ..........................................................................
说明 ..........................................................................
修订历史记录 ...........................................................
Device Comparison ...............................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
4
4
4
4
5
5
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Thermal Information ..................................................
Recommended Operating Conditions.......................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 7
8.1 Overview ................................................................... 7
8.2 Functional Block Diagram ......................................... 7
8.3 Feature Description................................................... 7
8.4 Device Functional Modes.......................................... 8
9
Application and Implementation .......................... 9
9.1 Application Information.............................................. 9
9.2 Typical Application ................................................. 10
10 Power Supply Recommendations ..................... 11
11 Layout................................................................... 11
11.1 Layout Guidelines ................................................. 11
11.2 Layout Example .................................................... 11
12 器件和文档支持 ..................................................... 12
12.1
12.2
12.3
12.4
12.5
12.6
12.7
器件支持 ...............................................................
文档支持 ...............................................................
相关链接................................................................
社区资源................................................................
商标 .......................................................................
静电放电警告.........................................................
Glossary ................................................................
12
12
12
12
13
13
13
13 机械、封装和可订购信息 ....................................... 13
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision B (August 2011) to Revision C
Page
•
已将 TLV853 器件添加至数据表 ............................................................................................................................................. 1
•
已将页眉上显示的器件部件编号从标有字母的器件版本更改为显示单个 TLV803 器件 .......................................................... 1
•
已添加器件信息和 ESD 额定值表 ........................................................................................................................................... 1
•
已添加详细 说明，应用和实施，电源相关建议，布局，器件和文档支持以及机械、封装和可订购信息部分 ......................... 1
•
已更改应用部分要点 ............................................................................................................................................................... 1
•
已从首页中删除引脚分配并将其移动至引脚配置和功能部分 .................................................................................................. 1
•
Deleted Package/Ordering Information table; for package and ordering information, see the package option
addendum at the end of the data sheet. ................................................................................................................................ 3
•
Changed all "free-air" to "junction" and all "TA" to "TJ" for all temperature ranges throughout data sheet ............................ 4
•
Changed "free-air temperature" to "junction temperature" in Absolute Maximum Ratings condition statement ................... 4
•
Deleted Soldering temperature from Absolute Maximum Ratings table ............................................................................... 4
•
Changed Thermal Information table; updated thermal resistance values for all parameters ................................................ 4
•
Changed "free-air temperature" to "junction temperature" in Electrical Characteristics condition statement ....................... 5
•
Changed temperature noted in Switching Characteristics condition statement .................................................................... 5
Changes from Revision A (June 2011) to Revision B
Page
•
已将关于 TLV863 的新段落添加至说明部分 ........................................................................................................................... 1
•
已在首页中添加 TLV863 引脚分配.......................................................................................................................................... 1
•
Added TLV863M to Package/Ordering Information................................................................................................................ 3
•
Added TLV863 to Thermal Information .................................................................................................................................. 4
•
Added TLV863M to Negative-Going Input Threshold Voltage parameter.............................................................................. 5
•
Added TLV863M to Hysteresis parameter ............................................................................................................................. 5
•
Added TLV863 to Functional Block Diagram ......................................................................................................................... 7
2
Copyright © 2011–2015, Texas Instruments Incorporated
TLV803, TLV853, TLV863
www.ti.com.cn
ZHCS187C – APRIL 2011 – REVISED SEPTEMBER 2015
5 Device Comparison
Table 1. Device Threshold Options
DEVICE
THRESHOLD VOLTAGE
TLV803Z
2.25 V
TLV803R
2.64 V
TLV803S
2.93 V
TLV803M
4.38 V
TLV853M
4.38 V
TLV863M
4.38 V
Table 2. Device Family Comparison
DEVICE
FUNCTION
TLV803
Open-Drain, RESET Output
TLV809
Push-Pull, RESET Output
TLV810
Push-Pull, RESET Output
6 Pin Configuration and Functions
TLV803: DBZ Package
3-Pin SOT-23
Top View
GND
1
RESET
3
RESET
TLV853: DBZ Package
3-Pin SOT-23
Top View
1
VDD
3
2
GND
VDD
2
TLV863: DBZ Package
3-Pin SOT-23
Top View
RESET
1
3
VDD
GND
2
Pin Functions
PIN
NAME
I/O
DESCRIPTION
TLV803
TLV853
TLV863
GND
1
2
3
—
Ground pin.
RESET
2
1
1
O
RESET is an open-drain output that is driven to a low impedance state
when RESET is asserted. RESET remains low (asserted) for the delay time
(td) after VDD exceeds VIT–. Use a 10-kΩ to 1-MΩ pullup resistor on this pin.
The pullup voltage is not limited by VDD.
VDD
3
3
2
I
Supply voltage pin. It is good analog design practice to place a 0.1-µF
ceramic capacitor close to this pin.
Copyright © 2011–2015, Texas Instruments Incorporated
3
TLV803, TLV853, TLV863
ZHCS187C – APRIL 2011 – REVISED SEPTEMBER 2015
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings (1)
over operating junction temperature range (unless otherwise noted)
VDD (2)
Voltage
All other pins (2)
Current
MIN
MAX
0
7
–0.3
+7
Maximum low output current, IOL
5
Maximum high output current, IOH
–5
Input clamp current, IIK (VI < 0 or VI > VDD)
±20
Output clamp current, IOK (VO < 0 or VO > VDD)
Temperature
(1)
(2)
UNIT
V
mA
±20
Operating junction temperature range, TJ
–40
125
Storage temperature range, Tstg
–65
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to GND. For reliable operation the device should not be operated at 7 V for more than t = 1000h
continuously
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Thermal Information
TLV8x3
THERMAL METRIC (1)
DBZ (SOT-23)
UNITS
3 PINS
RθJA
Junction-to-ambient thermal resistance
328.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
135.4
°C/W
RθJB
Junction-to-board thermal resistance
58.3
°C/W
ψJT
Junction-to-top characterization parameter
5.2
°C/W
ψJB
Junction-to-board characterization parameter
59.6
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
7.4 Recommended Operating Conditions
at specified temperature range (unless otherwise noted)
MIN
MAX
VDD
Supply voltage
1.1
6
V
TJ
Operating junction temperature
–40
125
°C
4
UNIT
Copyright © 2011–2015, Texas Instruments Incorporated
TLV803, TLV853, TLV863
www.ti.com.cn
ZHCS187C – APRIL 2011 – REVISED SEPTEMBER 2015
7.5 Electrical Characteristics
over recommended operating junction temperature range (unless otherwise noted)
PARAMETER
VOL
TEST CONDITIONS
Low-level output voltage
Power-up reset voltage (1)
VIT–
0.2
0.4
VDD = 6 V, IOL = 4 mA
0.4
1.1
2.20
2.25
2.30
TLV803R
2.58
2.64
2.70
2.87
2.93
2.99
4.28
4.38
4.48
TJ = – 40°C to +125°C
TLV803Z
TLV803R
TLV803S
Supply current
IOH
Output leakage current
(1)
(2)
V
V
30
35
TJ = 25°C, IOL = 50 µA
mV
40
TLV8x3M
IDD
UNIT
V
TLV803Z
TLV803S
Hysteresis
MAX
VDD = 3.3 V, IOL = 2 mA
TLV8x3M
Vhys
TYP
VDD = 2 V to 6 V, IOL = 500 µA
IOL = 50 µA, VOL < 0.2 V
Negative-going input
threshold voltage (2)
MIN
60
VDD = 2 V, output unconnected
9
15
VDD = 6 V, output unconnected
20
30
VDD = 6 V
100
µA
nA
The lowest supply voltage at which RESET becomes valid. tr,VDD ≤ 66.7 V/ms.
To ensure best stability of the threshold voltage, place a bypass capacitor (0.1-µF ceramic) near the supply terminals.
7.6 Switching Characteristics
over operating temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tw
Pulse duration at VDD
VDD = 1.08 VIT– to 0.92 VIT–
td
Delay time
VDD ≥ VIT– + 0.2 V; see Timing Diagram
MIN
TYP
MAX
UNIT
280
ms
1
120
200
µs
VDD
VIT-
1.1 V
t
RESET
1
0
td
td
t
For VDD < 1.1 V Undefined
Behavior of RESET Output
Figure 1. Timing Diagram
Copyright © 2011–2015, Texas Instruments Incorporated
5
TLV803, TLV853, TLV863
ZHCS187C – APRIL 2011 – REVISED SEPTEMBER 2015
www.ti.com.cn
7.7 Typical Characteristics
at TJ = 25°C, VIT– = 4.38 V, and VDD = 5.0 V (unless otherwise noted)
1.2
25
+125°C
+85°C
+25°C
0°C
-40°C
1
20
IDD (mA)
VOL (V)
0.8
+125°C
+85°C
+25°C
0°C
-40°C
0.6
15
10
0.4
5
0.2
VDD = 2.5 V
0
0
0
1
2
3
4
5
0
1
2
3
VDD (V)
IOL (mA)
Figure 2. Low-Level Output Voltage vs Low-Level Output
Current
6
Minimum Pulse Duration at VDD (ms)
1.6
1
0.999
0.998
0.997
0.996
0.995
0.994
1.4
1.2
1
0.8
0.6
+125°C
+85°C
+25°C
0°C
-40°C
0.4
0.2
0
-40 -25 -10
5
20 35 50 65
Temperature (°C)
80
95
110 125
0
Figure 4. Normalized to 25°C Negative-Going Input
Threshold Voltage vs Temperature
0.5
1
1.5
(VIT-) - VDD (V)
2
2.5
Figure 5. Minimum Pulse Duration At VDD vs Overdrive
Voltage
0.8
220
RESET Pulled Up to VDD
with 22.1-kW Resistor
TLV803M
0.7
TLV803Z
210
+125°C
+85°C
+25°C
0°C
-40°C
0.6
200
0.5
VOL (V)
td (ms)
5
Figure 3. Supply Current vs Supply Voltage
1.001
Normalized VIT- (V)
4
190
0.4
0.3
180
0.2
170
0.1
0
160
-40 -25 -10
5
20 35 50 65
Temperature (°C)
80
95
Figure 6. Delay Time vs Temperature
6
110 125
0
0.25
0.5
0.75
VDD (V)
1
1.25
1.5
Figure 7. Power-Up Low-Level Output Voltage vs Supply
Voltage
Copyright © 2011–2015, Texas Instruments Incorporated
TLV803, TLV853, TLV863
www.ti.com.cn
ZHCS187C – APRIL 2011 – REVISED SEPTEMBER 2015
8 Detailed Description
8.1 Overview
The TLV803 family of supervisory circuits provides circuit initialization and timing supervision. The TLV853 and
TLV863 are both functionally equivalent to the TLV803. These devices output a logic low whenever VDD drops
below the negative-going threshold voltage (VIT–). The output, RESET, remains low for approximately 200 ms
after the VDD voltage exceeds the positive-going threshold voltage (VIT– + Vhys). These devices are designed to
ignore fast transients on the VDD pin.
8.2 Functional Block Diagram
TLV8x3
R1
_
VDD
Reset
Logic
+
Timer
+
R2
RESET
GND
Oscillator
Reference
Voltage
of 1.137 V
8.3 Feature Description
8.3.1 VDD Transient Rejection
The TLV803 has built-in rejection of fast transients on the VDD pin. The rejection of transients depends on both
the duration and the amplitude of the transient. The amplitude of the transient is measured from the bottom of the
transient to the negative threshold voltage of the TLV803, as shown in Figure 8.
VDD
VITTransient
Amplitude
tw
Duration
Figure 8. Voltage Transient Measurement
The TLV803 does not respond to transients that are fast duration/low amplitude or long duration/small amplitude.
Figure 5 shows the relationship between the transient amplitude and duration needed to trigger a reset. Any
combination of duration and amplitude above the curve generates a reset signal.
Copyright © 2011–2015, Texas Instruments Incorporated
7
TLV803, TLV853, TLV863
ZHCS187C – APRIL 2011 – REVISED SEPTEMBER 2015
www.ti.com.cn
Feature Description (continued)
8.3.2 Reset During Power Up and Power Down
The TLV803 output is valid when VDD is greater than 1.1 V. When VDD is less than 1.1 V, the output transistor
turns off and becomes high impedance. The voltage on the RESET pin rises to the voltage level connected to the
pull-up resistor. Figure 9 shows a typical waveform for power-up, assuming the RESET pin has a pull-up resistor
connected to the VDD pin.
VIT- + VHYS
VDD
1.1 V
td
RESET
Valid Output
Figure 9. Power-Up Response
8.3.3 Bidirectional Reset Pins
Some microcontrollers have bidirectional reset pins that act as both inputs and outputs. In a situation where the
TLV803 is pulling the RESET line low while the microcontroller is trying the force the RESET line high, a series
resistor should be placed between the output of the TLV803 and the RESET pin of the microcontroller to protect
against excessive current flow. Figure 10 shows the connection of the TLV803 to a microcontroller using a series
resistor to drive a bidirectional RESET line.
3.3 V
VCC
VDD
TLV803S
100 kW
RESET
Microprocessor
47 kW RST
GND
Figure 10. Connection To Bidirectional Reset Pin
8.4 Device Functional Modes
8.4.1 Normal Operation (VDD > Power-Up Reset Voltage)
When the voltage on VDD is greater than 1.1 V, the RESET signal asserts when VDD is less than VIT– and
deasserts when VDD is greater thanVIT–.
8.4.2 Power On Reset (VDD < Power-Up Reset Voltage)
When the voltage on VDD is lower than the required voltage to internally pull the asserted output to GND (powerup reset voltage), both outputs are in a high-impedance state.
8
Copyright © 2011–2015, Texas Instruments Incorporated
TLV803, TLV853, TLV863
www.ti.com.cn
ZHCS187C – APRIL 2011 – REVISED SEPTEMBER 2015
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.1.1 Monitoring Multiple Supplies
Because the TLV803 has an open-drain output, multiple TLV803 outputs can be directly tied together to form a
logical OR-ing function for the RESET line. Only one pull-up resistor is required for this configuration. Figure 11
shows two TLV803s connected together to provide monitoring of a 3.3-V power rail and a 5.0-V power rail. A
reset is generated if either power rail falls below the threshold voltage of its corresponding TLV803.
5.0 V
3.3 V
0.1 mF
VDD
TLV803M
RESET
100 kW
VIO
VCORE
Microprocessor
RST
GND
3.3 V
0.1 mF
VDD
TLV803S
RESET
GND
Figure 11. Multiple Voltage Rail Monitoring
9.1.2 Output Level Shifting
The RESET output of the TLV803 can be pulled to a maximum voltage of 6 V and can be pulled higher in voltage
than VDD. It is useful to provide level shifting of the output for cases where the monitored voltage is less than the
useful logic levels of the load. Figure 12 shows the TLV803Z used to monitor a 2.5-V power rail, with a logic
RESET input to a microprocessor that is connected to 5.0 V and has 5.0-V logic levels.
Copyright © 2011–2015, Texas Instruments Incorporated
9
TLV803, TLV853, TLV863
ZHCS187C – APRIL 2011 – REVISED SEPTEMBER 2015
www.ti.com.cn
Application Information (continued)
2.5 V
5.0 V
0.1 mF
VDD
10 kW
TLV803Z
RESET
Microprocessor
RST
GND
Figure 12. Output Voltage Level Shifting
9.2 Typical Application
Figure 13 shows TLV803S being used to monitor the supply rail for a DSP, FPGA, or ASIC.
3.3-V LDO
3.3 V
5V
OUT
IN
GND
VDD
VDD
DSP/FPGA/ASIC
TLV803S
RESET
RESET
GND
GND
Figure 13. Typical Application
9.2.1 Design Requirements
This design calls for a 3.3-V rail to be monitored. The design resets if the supply rail falls below 2.93 V. The
output must satisfy 3.3-V CMOS logic.
9.2.2 Detailed Design Procedure
Select the TLV803S to satisfy the voltage threshold requirement.
Place a pullup resistor on RESET to VDD in order to satisfy the output logic requirement.
10
Copyright © 2011–2015, Texas Instruments Incorporated
TLV803, TLV853, TLV863
www.ti.com.cn
ZHCS187C – APRIL 2011 – REVISED SEPTEMBER 2015
Typical Application (continued)
9.2.3 Application Curves
Minimum Pulse Duration at VDD (ms)
1.6
1.4
1.2
1
0.8
0.6
+125°C
+85°C
+25°C
0°C
-40°C
0.4
0.2
0
0
0.5
1
1.5
(VIT-) - VDD (V)
2
2.5
Figure 14. Minimum Pulse Duration At VDD vs Overdrive Threshold Voltage vs Temperature Voltage
10 Power Supply Recommendations
These devices are designed to operate from an input voltage supply range between 1.1 V and 6 V.
11 Layout
11.1 Layout Guidelines
Place the CIN decoupling capacitor close to the device.
11.2 Layout Example
RPU
VDD
CIN
RESET
TLV803
GND Plane
Figure 15. Layout Example (DBZ Package)
版权 © 2011–2015, Texas Instruments Incorporated
11
TLV803, TLV853, TLV863
ZHCS187C – APRIL 2011 – REVISED SEPTEMBER 2015
www.ti.com.cn
12 器件和文档支持
12.1 器件支持
12.1.1 开发支持
12.1.1.1 评估模块
评估模块 (EVM) 可与 TLV803 配套使用，帮助评估初始电路性能。TLV803SEVM-019 评估模块（和相关用户指
南）可在德州仪器 (TI) 网站上的产品文件夹中获取，也可直接从 TI 网上商店购买。
12.1.1.2 Spice 模型
分析模拟电路和系统的性能时，使用 SPICE 模型对电路性能进行计算机仿真非常有用。您可以从相应产品文件夹
中的工具和软件下获取 TLV803、TLV853 和 TLV863 的 SPICE 模型。
12.2 文档支持
12.2.1 相关文档
• 《TLV803SEVM-019 用户指南》。文献编号：SLVU461。
12.3 相关链接
表 3 列出了快速访问链接。范围包括技术文档、支持与社区资源、工具和软件，以及样片与购买的快速访问。
表 3. 相关链接
部件
产品文件夹
样片与购买
技术文档
工具与软件
支持与社区
TLV803
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
TLV853
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
TLV863
请单击此处
请单击此处
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12.4 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12
版权 © 2011–2015, Texas Instruments Incorporated
TLV803, TLV853, TLV863
www.ti.com.cn
ZHCS187C – APRIL 2011 – REVISED SEPTEMBER 2015
12.5 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2011–2015, Texas Instruments Incorporated
13
PACKAGE OPTION ADDENDUM
www.ti.com
2-Aug-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TLV803MDBZR
ACTIVE
SOT-23
DBZ
3
3000
RoHS & Green
NIPDAUAG | SN
Level-1-260C-UNLIM
-40 to 125
VOUQ
Samples
TLV803MDBZT
ACTIVE
SOT-23
DBZ
3
250
RoHS & Green
NIPDAUAG | SN
Level-1-260C-UNLIM
-40 to 125
VOUQ
Samples
TLV803RDBZR
ACTIVE
SOT-23
DBZ
3
3000
RoHS & Green
NIPDAU | SN
| NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
VOSQ
Samples
TLV803RDBZT
ACTIVE
SOT-23
DBZ
3
250
RoHS & Green
NIPDAUAG | SN
Level-1-260C-UNLIM
-40 to 125
VOSQ
Samples
TLV803SDBZR
ACTIVE
SOT-23
DBZ
3
3000
RoHS & Green
NIPDAU | SN
| NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
VOTQ
Samples
TLV803SDBZT
ACTIVE
SOT-23
DBZ
3
250
RoHS & Green
NIPDAUAG | SN
Level-1-260C-UNLIM
-40 to 125
VOTQ
Samples
TLV803ZDBZR
ACTIVE
SOT-23
DBZ
3
3000
RoHS & Green
NIPDAU | SN
| NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
VORQ
Samples
TLV803ZDBZT
ACTIVE
SOT-23
DBZ
3
250
RoHS & Green
NIPDAUAG | SN
Level-1-260C-UNLIM
-40 to 125
VORQ
Samples
TLV853MDBZR
ACTIVE
SOT-23
DBZ
3
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
ZGM4
Samples
TLV853MDBZT
ACTIVE
SOT-23
DBZ
3
250
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
ZGM4
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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