User's Guide
SLVU461 – May 2011
TLV8xxxEVM-019 Evaluation Modules
This user’s guide describes the characteristics, operation, and use of the TLV809K (TLV809KEVM-019),
TLV810S (TLV810SEVM-019), and TLV803S (TLV803SEVM-019) evaluation modules (EVM). The
TLV8xxxEVM is a fully assembled and tested platform for evaluating the performance of the TLV8xxx
family of supervisory circuits. The TLV809K, TLV810S, and TLV803S are single channel, 3-pin, 3.3-V
supply voltage supervisors (SVS) with built-in power-on reset generator with fixed delay time of 200ms.
This user’s guide includes setup configuration instructions, a complete schematic diagram, bill of materials
(BOM), and printed circuit board (PCB) layout drawings for the evaluation module.
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Contents
Introduction ..................................................................................................................
Schematic ....................................................................................................................
Setup and Board Description ..............................................................................................
Operation .....................................................................................................................
Board Layout ................................................................................................................
Bill of Materials ..............................................................................................................
1
TLV8xxxEVM Rev A Schematic
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2
2
3
4
7
List of Figures
2
3
4
5
6
7
..........................................................................................
Quick Start Connection Setup .............................................................................................
Timing Diagram for TLV8xxxEVM ........................................................................................
Silkscreen Layer ............................................................................................................
Assembly Layer .............................................................................................................
Top Layer Routing ..........................................................................................................
Bottom Layer Routing ......................................................................................................
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List of Tables
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3
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................................................................
Bill of Materials ..............................................................................................................
Assembly Number and Corresponding Label Text .....................................................................
Threshold voltage, VIT, Values for Each TLV8xxxEVM
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Introduction
The TLV8xxxEVM helps designers evaluate the operation and performance of the TLV8xxx family of
single channel supervisors in a 3-pin SOT-23 package. This particular EVM configuration contains a single
SVS capable of supervising up to 6-V supply voltage. The TLV8xxx EVM is assembled with the TLV809K,
TLV810S, or TLV803S, all of which are 3.3-V supply voltage supervisors with threshold voltage, VIT, of
2.93-V. To evaluate the TLV8xxx EVM with a different supply voltage, the IC will need to be replaced. The
TLV8xxx family of supervisory circuits provides initialization and timing supervision, primarily for DSPs and
processor-based systems; and, is available for supply voltages of 2.5-V, 3.0-V, 3.3-V, and 5.0-V.
1.1
Features
•
•
Low supply current: 9 µA (typical)
Power-on RESET / RESET generator with fixed delay time of 200ms
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1
Schematic
1.2
Orderable Options
•
•
•
2
www.ti.com
TLV809KEVM-019: 3.3-V single channel supervisor with active low, push-pull RESET output
TLV810SEVM-019: 3.3-V single channel supervisor with active high, push-pull RESET output
TLV803SEVM-019: 3.3-V single channel supervisor with active low, open-drain RESET output
Schematic
Figure 1. TLV8xxxEVM Rev A Schematic
3
Setup and Board Description
3.1
EVM Input/Output Connectors and Test Jumpers
2
Connector
Label
Description
J1
VDD
Input power supply connection: 2V to 6V
J2
GND
Return connection for input power supply
J3
RESET
RESET
J4
GND
JP1
Pull-Up
RESET / RESET output of supervisor IC. Connect this output to a multimeter or oscilloscope to verify
output voltage.
Return connection for output (RESET / RESET)
Necessary for TLV803SEVM-019 only. Placing a jumper on JP1 connects the 49.9kΩ (R1) pull-up
resistor to VDD and RESET output.
TLV8xxxEVM-019 Evaluation Modules
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Operation
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3.2
Connection Setup
Install jumper
on JP1 for
TLV803S only
A
Power
Supply
V
V
Figure 2. Quick Start Connection Setup
1. Connect the power supply and its return connection to J1 and J2 as shown above.
2. An ammeter can be connected in series with the power supply to measure the supply current. A
voltmeter can also be connected across J1 and J2 to measure the effective voltage at the pins.
3. Connect a voltmeter or an oscilloscope voltage probe across the output pins J3 and J4 to observe and
measure the output voltage.
NOTE: For TLV803SEVM-019, please verify that jumper on JP1 is present so that pull-up resistor
R1 is connected to VDD and to RESET. If an output voltage different from VDD is desired, a
power supply can be connected to JP1 to pull the RESET pin to a different voltage.
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Operation
This section provides information about the operation of the TLV8xxxEVM and the outputs expected. The
TLV8xxx parts can support supply voltage, VDD, in the range of 2-V to 6-V. No external components are
required. All the devices in this family have a fixed sense-threshold voltage (VIT) set by an internal voltage
divider.
4.1
Threshold Voltage, VIT
During power-on, RESET / RESET is asserted when the supply voltage (VDD) becomes higher than 1.1-V.
Thereafter, for active low devices, the supervisory circuit monitors VDD and keeps RESET active as long
as VDD remains below the threshold voltage, VIT. For active high devices, the supervisory circuit keeps
RESET active as long as VDD remains above the threshold voltage, VIT.
TLV809K and TLV803S (active low RESET output):
• When VDD < VIT, the output across the RESET pins J3 and J4 should be 0-V (low).
• When VDD > VIT, the output across the RESET pins J3 and J4 should equal VDD ± 0.5-V (high) with no
load.
TLV810S (active high RESET output):
• When VDD < VIT, the output across the RESET pins J3 and J4 should equal VDD ± 0.5-V (high) with no
load.
• When VDD > VIT, the output across the RESET pins J3 and J4 should be 0-V (low).
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Board Layout
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Table 1. Threshold voltage, VIT, Values for Each TLV8xxxEVM
VIT
Part
(1)
4.2
(1)
Min (V)
Typ (V)
Max (V)
TLV809K
2.87
2.93
2.99
TLV810S
2.87
2.93
2.99
TLV803S
2.87
2.93
2.99
VIT values taken from datasheet.
Timing
The TLV8xxx parts have a reset generator with a fixed delay time. An internal timer delays the return of
the output to the inactive state (high) to ensure proper system reset. The delay time (td(typ) = 200ms) starts
after VDD has risen above the threshold voltage, VIT. When the supply voltage, VDD, drops below the VIT
voltage, the output becomes active (low) again. Min and max values for td can be found in the datasheet,
labeled Switching Characteristics.
t d = 211ms
Figure 3. Timing Diagram for TLV8xxxEVM
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Board Layout
This section provides the TLV8xxxEVM board layout and illustrations.
5.1
Layout
NOTE: Board layouts are not to scale. These figures are intended to show how the board is laid out; they
are not intended to be used for manufacturing TLV8xxx EVM PCBs.
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TLV8xxxEVM-019 Evaluation Modules
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Board Layout
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Figure 4. Silkscreen Layer
JP1
EVM P/N
TEXAS INSTRUMENTS
PWR019 REV. A
J3
J1
RESET /RESET
VDD
U1
1
C1
R1
J2
J4
GND
GND
2011
Figure 5. Assembly Layer
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Board Layout
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Figure 6. Top Layer Routing
Figure 7. Bottom Layer Routing
6
TLV8xxxEVM-019 Evaluation Modules
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Bill of Materials
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6
Bill of Materials
Table 2. Bill of Materials
PWR019001
PWR019002
PWR019003
COUNT
COUNT
COUNT
1
1
4
4
0
RefDes
Value
Description
Size
Part Number
MFR
1
C1
0.1uF
Capacitor, Ceramic, 10V, X7R, 20%
0603
STD
STD
4
J1, J2, J3,
J4
PEC02SAAN
Header, Male 2-pin, 100mil spacing
0.100 inch x 2
PEC02SAAN
Sullins
0
1
JP1
PEC02SAAN
Header, Male 2-pin, 100mil spacing
0.100 inch x 2
PEC02SAAN
Sullins
0
0
1
R1
49.9k
Resistor, Chip, 1/16W, 1%
0603
STD
STD
1
0
0
U1
TLV809KDBZ
IC, Voltage Supervisors with Active-Low, Push-Pull
RESET
SOT23-3
TLV809K33DBZ
TI
0
1
0
U1
TLV810SDBZ
IC, Voltage Supervisors with Active-High, Push-Pull
RESET
SOT23-3
TLV810SDBZ
TI
0
0
1
U1
TLV803SDBZ
IC, Voltage Supervisors with Active-Low, Open-Drain
RESET
SOT23-3
TLV803SDBZ
TI
0
0
1
–
Shunt, 100-mil, Black
0.1
929950-00
3M
1
1
1
–
Label
1.25 x 0.25 inch
THT-13-457-10
Brady
1
1
1
–
1.645 x 1.300 x 0 .062 inch 2 layer 2oz. PCB
1.645 inch x 1.300 inch
PWR019
Any
PWR019
Notes 1. These assemblies are ESD sensitive, ESD precautions shall be observed.
2. These assemblies must be clean and free from flux and all contaminants. Use of no clean flux is not acceptable.
3. These assemblies must comply with workmanship standards IPC-A-610 Class 2.
4. Ref designators marked with an asterisk ('**') cannot be substituted. All other components can be substituted with equivalent MFG's components.
5. Install label after final wash. Text shall be 8 pt font. Text shall be per Table 3.
Table 3. Assembly Number and Corresponding Label Text
Assembly Number
PWR019-001
PWR019-002
PWR019-003
Text
TLV809KEVM-019
TLV810SEVM-019
TLV803SEVM-019
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Evaluation Board/Kit Important Notice
Texas Instruments (TI) provides the enclosed product(s) under the following conditions:
This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION
PURPOSES ONLY and is not considered by TI to be a finished end-product fit for general consumer use. Persons handling the
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including product safety and environmental measures typically found in end products that incorporate such semiconductor
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electromagnetic compatibility, restricted substances (RoHS), recycling (WEEE), FCC, CE or UL, and therefore may not meet the
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Should this evaluation board/kit not meet the specifications indicated in the User’s Guide, the board/kit may be returned within 30
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EVM Warnings and Restrictions
It is important to operate this EVM within the input voltage range of 2 V to 6 V and the output voltage range of 0 V to 6 V .
Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are
questions concerning the input range, please contact a TI field representative prior to connecting the input power.
Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to the
EVM. Please consult the EVM User's Guide prior to connecting any load to the EVM output. If there is uncertainty as to the load
specification, please contact a TI field representative.
During normal operation, some circuit components may have case temperatures greater than 85° C. The EVM is designed to
operate properly with certain components above 85° C as long as the input and output ranges are maintained. These components
include but are not limited to linear regulators, switching transistors, pass transistors, and current sense resistors. These types of
devices can be identified using the EVM schematic located in the EVM User's Guide. When placing measurement probes near
these devices during operation, please be aware that these devices may be very warm to the touch.
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