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TLV8811, TLV8812
SNOSD35A – OCTOBER 2016 – REVISED NOVEMBER 2016
TLV8811,TLV8812 425 nA Precision Nanopower Op Amps for Cost-Optimized Systems
1 Features
3 Description
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The TLV8811 (single) and TLV8812 (dual) family of
precision ultra-low-power operational amplifiers are
ideal for cost-optimized, “Always ON” sensing
applications in battery powered wireless and low
power wired equipment. With 6 kHz of bandwidth
from 425 nA of quiescent current and a trimmed
offset voltage to under 500µV, the TLV881x
amplifiers provide high precision while minimizing
power consumption in equipment such as CO gas
detectors and portable electronic devices where
operational battery-life is critical. They also have a
CMOS input stage enabling fempto-amp bias
currents, thereby reducing IBIAS and IOS errors that
would otherwise impact high source impedance
sensing applications. Additionally, built-in EMI
protection reduces sensitivity to unwanted RF signals
from mobile phones, WiFi, radio transmitters, and tag
readers.
1
For Cost-Optimized Systems
Nanopower Supply Current: 425 nA/channel
Offset Voltage: 500 µV (max)
TcVos: 1 µV/°C
Gain-Bandwidth: 6 kHz
Unity-Gain Stable
Low Input Bias Current : 100 fA
Wide Supply Range: 1.7 V to 5.5 V
Rail-to-Rail Output
No Output Reversals
EMI Protection
Temperature Range: –40°C to 125°C
Industry Standard Packages:
– Single in 5-pin SOT-23
– Dual in 8-pin VSSOP
2 Applications
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Gas Detectors (CO and O2)
PIR Motion Detectors
Current Sensing
Thermostats
IoT (Internet of Things) Remote Sensors
Active RFID Readers and Tags
Portable Medical Equipment
Portable Glucose Monitors
The TLV8811 (single) and TLV8812 (dual) channel
versions are available in industry standard 5-pin SOT23 and 8-pin VSSOP packages respectively.
Device Information (1)
PART
NUMBER
BODY SIZE
TLV8811
SOT-23 (5)
2.90 mm x 1.60 mm
TLV8812
VSSOP (8)
3.00 mm × 3.00 mm
LPV81x and TLV881x Nanopower Amplifiers
CHANNELS
SUPPLY
CURRENT
(Typ per
Channel)
OFFSET
VOLTAGE
(Max at 25°C)
LPV811
1
450 nA
370 µV
PART
NUMBER
(1)
Nanopower Oxygen Sensor
PACKAGE
LPV812
2
425 nA
300 µV
TLV8811
1
450 nA
550 µV
TLV8812
2
425 nA
500 µV
For all available packages, see the orderable addendum at
the end of the data sheet.
Nanopower CO Sensor
22 M
1M
+
V
V
220 k
+
RL
+
VOUT
CO
Sensor
+
VOUT
RL
OXYGEN SENSOR
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLV8811, TLV8812
SNOSD35A – OCTOBER 2016 – REVISED NOVEMBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
6
Detailed Description ............................................ 12
7.1
7.2
7.3
7.4
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
12
12
12
12
Application and Implementation ........................ 14
8.1 Application Information............................................ 14
8.2 Typical Application: Three Terminal CO Gas Sensor
Amplifier ................................................................... 14
8.3 Do's and Don'ts ...................................................... 17
9 Power Supply Recommendations...................... 17
10 Layout................................................................... 17
10.1 Layout Guidelines ................................................. 17
10.2 Layout Example .................................................... 17
11 Device and Documentation Support ................. 18
11.1
11.2
11.3
11.4
11.5
11.6
11.7
11.8
Device Support ....................................................
Documentation Support .......................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
18
18
18
18
18
18
19
19
12 Mechanical, Packaging, and Orderable
Information ........................................................... 19
4 Revision History
Changes from Original (October 2016) to Revision A
Page
•
Changed Description text ...................................................................................................................................................... 1
•
Deleted large family table, moved to front page. ................................................................................................................... 1
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Added Family table to front page .......................................................................................................................................... 1
•
Deleted "LPV8811 specs prelim until release" table footnote ............................................................................................... 5
•
Added seporate CMRR Spec row for TLV8811 .................................................................................................................... 5
2
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Copyright © 2016, Texas Instruments Incorporated
TLV8811, TLV8812
www.ti.com
SNOSD35A – OCTOBER 2016 – REVISED NOVEMBER 2016
5 Pin Configuration and Functions
TLV8812 8-Pin VSSOP
DGK Package
Top View
TLV8811 5-Pin SOT-23
DBV Package
Top View
OUT A
OUT
1
V-
2
+IN
3
5
1
8
V+
7
OUT B
A
V+
-IN A
2
B
4
+IN A
3
6
-IN B
V-
4
5
+IN B
-IN
Pin Functions: TLV8811 DBV
PIN
TYPE
DESCRIPTION
NAME
NUMBER
OUT
1
O
Output
-IN
4
I
Inverting Input
+IN
3
I
Non-Inverting Input
V-
2
P
Negative (lowest) power supply
V+
5
P
Positive (highest) power supply
Pin Functions: TLV8812 DGK
PIN
TYPE
DESCRIPTION
NAME
NUMBER
OUT A
1
O
Channel A Output
-IN A
2
I
Channel A Inverting Input
+IN A
3
I
Channel A Non-Inverting Input
V-
4
P
Negative (lowest) power supply
+IN B
5
I
Channel B Non-Inverting Input
-IN B
6
I
Channel B Inverting Input
OUT B
7
O
Channel B Output
V+
8
P
Positive (highest) power supply
Copyright © 2016, Texas Instruments Incorporated
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TLV8811, TLV8812
SNOSD35A – OCTOBER 2016 – REVISED NOVEMBER 2016
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6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
UNIT
–0.3
6
V
Common mode
(V-) - 0.3
(V+) + 0.3
V
Differential
(V-) - 0.3
(V+) + 0.3
V
-10
10
mA
Continuous
Continuous
–65
150
°C
150
°C
Supply voltage, Vs = (V+) - (V-)
Voltage
Input pins
Input pins
(2) (3)
Current
Output short
current (4)
Storage temperature, Tstg
Junction temperature
(1)
(2)
(3)
(4)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Not to exceed -0.3V or +6.0V on ANY pin, referred to VInput terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.3 V beyond the supply rails should
be current-limited to 10 mA or less.
Short-circuit to Vs/2, one amplifier per package. Continuous short circuit operation at elevated ambient temperature can result in
exceeding the maximum allowed junction temperature of 150°C.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
(1)
(2)
Electrostatic discharge
(1)
UNIT
±1000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±250
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions. Pins listed as ±2000 V may actually have higher performance.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions. Pins listed as ±750 V may actually have higher performance.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
Supply voltage (V+ – V–)
1.7
5.5
UNIT
V
Specified temperature
-40
125
°C
6.4 Thermal Information
THERMAL METRIC
(1)
TLV8811
DBV
(SOT-23)
5 PINS
TLV8812
DGK
(VSSOP)
8 PINS
θJA
Junction-to-ambient thermal resistance
177.4
177.6
θJCtop
Junction-to-case (top) thermal resistance
133.9
68.8
θJB
Junction-to-board thermal resistance
36.3
98.2
ψJT
Junction-to-top characterization parameter
23.6
12.3
ψJB
Junction-to-board characterization parameter
35.7
96.7
(1)
4
UNIT
ºC/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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Copyright © 2016, Texas Instruments Incorporated
TLV8811, TLV8812
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SNOSD35A – OCTOBER 2016 – REVISED NOVEMBER 2016
6.5 Electrical Characteristics
TA = 25°C, VS = 1.8 V to 5 V, VCM = VOUT = VS/2, and RL≥ 10 MΩ to VS / 2, unless otherwise noted .
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
Input offset voltage,
TLV8811
VS = 1.8V and 3.3V, VCM = V-
±75
±550
µV
Input offset voltage,
TLV8812
VS = 1.8V and 3.3V, VCM = V-
±55
±500
µV
ΔVOS/ΔT
Input offset drift
VCM = V-
PSRR
Power-supply rejection
ratio
VS = 1.8V to 3.3V, VCM = V-
VOS
TA = –40°C to 125°C
±1
±1.6
µV/°C
±60
µV/V
2.4
V
INPUT VOLTAGE RANGE
VCM
CMRR
Common-mode voltage
range
VS = 3.3V
Common-mode rejection
ratio, TLV8811
(V–) ≤ VCM ≤ (V+) – 0.9 V, VS = 3.3V
77
95
dB
Common-mode rejection
ratio, TLV8812
(V–) ≤ VCM ≤ (V+) – 0.9 V, VS = 3.3V
80
98
dB
0
INPUT BIAS CURRENT
IB
Input bias current
VS = 1.8V
±100
fA
IOS
Input offset current
VS = 1.8V
±100
fA
Differential
7
pF
Common mode
3
pF
8
µVp-p
INPUT IMPEDANCE
NOISE
En
Input voltage noise
ƒ = 0.1 Hz to 10 Hz
en
Input voltage noise
density
ƒ = 100 Hz
360
ƒ = 1 kHz
450
Open-loop voltage gain
(V–) + 0.3 V ≤ VO ≤ (V+) – 0.3 V, RL = 100 kΩ
120
VOH
Voltage output swing
from positive rail
VS = 1.8V, RL = 100 kΩ to V+/2
VOL
Voltage output swing
from negative rail
VS = 1.8V, RL = 100 kΩ to V+/2
2.5
ISC
Short-circuit current
VS = 3.3V, Short to VS/2
4.7
mA
ZO
Open loop output
impedance
ƒ = 1 KHz, IO = 0 A
90
kΩ
6
kHz
nV/√Hz
OPEN-LOOP GAIN
AOL
dB
OUTPUT
10
3.5
mV
10
FREQUENCY RESPONSE
GBP
SR
Gain-bandwidth product
CL = 20 pF, RL = 10 MΩ, VS = 5V
G = 1, Rising Edge, CL = 20 pF, VS = 5V
1.4
G = 1, Falling Edge, CL = 20 pF, VS = 5V
1.5
Quiescent Current,
TLV8811
VCM = V-, IO = 0, VS = 3.3V
450
750
Quiescent Current,
Per Channel, TLV8812
VCM = V-, IO = 0, VS = 3.3V
425
700
Slew rate (10% to 90%)
V/ms
POWER
SUPPLY
IQ
nA
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6.6 Typical Characteristics
at TA = 25°C, RL = 10MΩ to VS/2 ,CL = 20pF, VCM = VS / 2V unless otherwise specified.
1000
900
900
Supply Current per Channel (nA)
1000
Supply Current (nA)
800
700
+125°C
600
+25°C
500
400
-40°C
300
200
100
1.5
2
2.5
3
3.5
4
4.5
5
Supply Voltage (V)
VCM = V-
600
+125°C
500
+25°C
400
300
-40°C
200
100
1.5
5.5
2
2.5
TLV8811
3
3.5
4
4.5
5
Supply Voltage (V)
C001
RL=No Load
VCM = V-
5.5
C001
TLV8812
RL=No Load
Figure 1. Supply Current vs. Supply Voltage, TLV8811
Figure 2. Supply Current vs. Supply Voltage, TLV8812
500
500
+125°C
400
+25°C
300
Offset Voltage (µV)
-40°C
200
+125°C
400
+25°C
300
Offset Voltage (µV)
700
0
0
100
0
±100
±200
-40°C
200
100
0
±100
±200
±300
±300
±400
±400
±500
±500
0
0.15
0.3
0.45
0.6
0.75
0
0.9
Common Mode Voltage (V)
RL= 10MΩ
1.6
2
2.4
C003
RL= 10MΩ
Figure 4. Typical Offset Voltage vs. Common Mode Voltage
1k
+125°C
+25°C
Input Bias Current (pA)
100
-40°C
200
1.2
VS= 3.3V
500
300
0.8
Common Mode Voltage (V)
Figure 3. Typical Offset Voltage vs. Common Mode Voltage
400
0.4
C003
VS= 1.8V
Offset Voltage (µV)
800
100
0
±100
±200
±300
10
1
100m
10m
±400
±500
1m
0
0.5
1
1.5
2
2.5
3
Common Mode Voltage (V)
VS= 5V
3.5
4
4.5
RL= 10MΩ
Figure 5. Typical Offset Voltage vs. Common Mode Voltage
6
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±50
±25
0
25
50
75
100
Temperature (ƒC)
C003
VS= 5V
TA = -40 to 125
125
C001
VCM = Vs/2
Figure 6. Input Bias Current vs. Temperature
Copyright © 2016, Texas Instruments Incorporated
TLV8811, TLV8812
www.ti.com
SNOSD35A – OCTOBER 2016 – REVISED NOVEMBER 2016
Typical Characteristics (continued)
100
100
80
80
60
60
Input Bias Current (fA)
Input Bias Current (fA)
at TA = 25°C, RL = 10MΩ to VS/2 ,CL = 20pF, VCM = VS / 2V unless otherwise specified.
40
20
0
±20
±40
±60
0
±20
±40
±60
±80
±100
±100
0.2
0.3
0.5
0.6
0.8
Common Mode Voltage (V)
VS= 1.8V
0.9
0.0
0.5
1.0
1.5
TA = -40°C
VS= 5V
800
800
600
600
Input Bias Current (fA)
1000
200
0
±200
±400
3.0
3.5
4.0
4.5
C002
TA = -40°C
400
200
0
±200
±400
±600
±600
±800
±800
±1000
2.5
Figure 8. Input Bias Current vs. Common Mode Voltage
1000
400
2.0
Common Mode Voltage (V)
C001
Figure 7. Input Bias Current vs. Common Mode Voltage
Input Bias Current (fA)
20
±80
0.0
±1000
0.0
0.2
0.3
0.5
0.6
0.8
Common Mode Voltage (V)
VS= 1.8V
0.9
0.0
0.5
1.0
1.5
TA = 25°C
VS= 5V
400
300
300
Input Bias Current (pA)
500
400
100
0
±100
±200
3.0
3.5
4.0
4.5
C005
TA = 25°C
200
100
0
±100
±200
±300
±300
±400
±400
±500
2.5
Figure 10. Input Bias Current vs. Common Mode Voltage
500
200
2.0
Common Mode Voltage (V)
C004
Figure 9. Input Bias Current vs. Common Mode Voltage
Input Bias Current (pA)
40
±500
0.0
0.2
0.3
0.5
0.6
Common Mode Voltage (V)
VS= 1.8V
0.8
0.9
TA = 125°C
Figure 11. Input Bias Current vs. Common Mode Voltage
Copyright © 2016, Texas Instruments Incorporated
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
Common Mode Voltage (V)
C003
VS= 5V
4.5
C006
TA = 125°C
Figure 12. Input Bias Current vs. Common Mode Voltage
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Typical Characteristics (continued)
at TA = 25°C, RL = 10MΩ to VS/2 ,CL = 20pF, VCM = VS / 2V unless otherwise specified.
10
+125°C
+25°C
-40°C
1
100m
10m
1m
1m
Output Sourcing Current (A)
VS= 1.8V
1m
VS= 3.3V
1m
Figure 14. Output Swing vs. Sinking Current, 1.8V
100m
10m
1m
1m
1m
+125°C
+25°C
-40°C
1
100m
10m
1m
10m
1m
RL= No Load
10m
Output Sinking Current (A)
C001
Figure 17. Output Swing vs. Sourcing Current, 5V
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RL= No Load
Figure 16. Output Swing vs. Sinking Current, 3.3V
Output Swing from V- (V)
1m
C005
VS= 3.3V
10
10m
10m
Output Sinking Current (A)
C001
100m
VS= 5V
+125°C
+25°C
-40°C
1
RL= No Load
Output Sourcing Current (A)
RL= No Load
10m
+125°C
+25°C
-40°C
10m
C006
VS= 1.8V
Figure 15. Output Swing vs. Sourcing Current, 3.3V
Output Swing from V+ (V)
1m
Output Sinking Current (A)
Output Swing from V- (V)
Output Swing from V+ (V)
1m
Output Sourcing Current (A)
8
10m
10
10m
1
100m
RL= No Load
100m
10
-40°C
C003
+125°C
+25°C
-40°C
1
1
10m
Figure 13. Output Swing vs. Sourcing Current, 1.8V
10
+125°C
+25°C
Output Swing from V- (V)
Output Swing from V+ (V)
10
VS= 5V
C004
RL= No Load
Figure 18. Output Swing vs. Sinking Current, 5V
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Typical Characteristics (continued)
50 mV/div
50 mV/div
at TA = 25°C, RL = 10MΩ to VS/2 ,CL = 20pF, VCM = VS / 2V unless otherwise specified.
500 us/div
500 us/div
C002
TA = 25
VS= ±0.9V
RL= 10MΩ
CL= 20pF
C002
Vout = 200mVpp
AV = +1
TA = 25
VS= ±2.5V
Vout = 200mVpp
AV = +1
500 mV/div
Figure 20. Small Signal Pulse Response, 5V
200 mV/div
Figure 19. Small Signal Pulse Response, 1.8V
RL= 10MΩ
CL= 20pF
500 us/div
500 us/div
C002
TA = 25
VS= ±0.9V
RL= 10MΩ
CL= 20pF
C002
Vout = 1Vpp
AV = +1
TA = 25
VS= ±2.5V
Figure 21. Large Signal Pulse Response, 1.8V
RL= 10MΩ
CL= 20pF
Vout = 2Vpp
AV = +1
Figure 22. Large Signal Pulse Response, 5V
110
140
+PSRR
100
120
80
PSRR (dB)
100
CMRR (dB)
-PSRR
90
80
60
40
70
60
50
40
30
20
20
10
0
0
1
10
100
1k
10k
Frequency (Hz)
TA = 25
VS= 5V
VCM = Vs/2
RL= 10MΩ
CL= 20p
AV = +1
ΔVCM = 0.5Vpp
Figure 23. CMRR vs Frequency
Copyright © 2016, Texas Instruments Incorporated
10
100
1k
10k
Frequency (Hz)
C001
TA = 25
VS= 3.3V
VCM = Vs/2
RL= 10MΩ
CL= 20p
AV = +1
C001
ΔVS = 0.5Vpp
Figure 24. ±PSRR vs Frequency
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Typical Characteristics (continued)
at TA = 25°C, RL = 10MΩ to VS/2 ,CL = 20pF, VCM = VS / 2V unless otherwise specified.
140
135
120
100
113
100
113
80
90
80
90
60
68
PHASE
20
23
20
23
0
0
0
0
1m
10m
100m
1
-23
100k
10
100
1k
10k
Frequency (Hz)
TA = -40, 25, 125°C
VS= 5V
45
-23
100k
±20
1m
10m
100m
VOUT = 200mVPP
VCM = Vs/2
1
10
100
1k
10k
Frequency (Hz)
C001
RL= 10MΩ
CL= 20pF
TA = -40, 25, 125°C
VS= 3.3V
Figure 25. Open Loop Gain and Phase, 5V, 10 MΩ Load
C002
RL= 10MΩ
CL= 20pF
VOUT = 200mVPP
VCM = Vs/2
Figure 26. Open Loop Gain and Phase, 3.3V, 10 MΩ Load
160
158
140
135
120
100
113
100
113
80
90
80
90
60
68
140
125°C
25°C
-40°C
GAIN
120
PHASE
40
AOL (dB)
180
Phase (ƒ)
160
AOL (dB)
68
60
40
±20
180
125°C
25°C
-40°C
GAIN
158
135
60
68
PHASE
45
40
20
23
20
23
0
0
0
0
±20
1m
10m
100m
1
10
100
1k
10k
-23
100k
Frequency (Hz)
TA = -40, 25, 125°C
VS= 5V
1m
10m
100m
VOUT = 200mVPP
VCM = Vs/2
1
10
100
1k
10k
-23
100k
Frequency (Hz)
C003
RL= 1MΩ
CL= 20pF
45
±20
TA = -40, 25, 125°C
VS= 3.3V
Figure 27. Open Loop Gain and Phase, 5V, 1 MΩ Load
C002
RL= 1MΩ
CL= 20pF
VOUT = 200mVPP
VCM = Vs/2
Figure 28. Open Loop Gain and Phase, 3.3V, 1 MΩ Load
140
135
120
100
113
100
113
80
90
80
90
60
68
125°C
25°C
-40°C
GAIN
120
PHASE
AOL (dB)
160
158
140
Phase (ƒ)
180
160
AOL (dB)
135
45
40
125°C
25°C
-40°C
GAIN
180
158
135
68
60
PHASE
45
40
20
23
20
23
0
0
0
0
40
±20
1m
10m
100m
1
10
100
Frequency (Hz)
TA = -40, 25, 125°C
VS= 5V
RL= 100kΩ
CL= 20pF
1k
10k
-23
100k
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45
±20
1m
10m
100m
1
10
100
Frequency (Hz)
C001
VOUT = 200mVPP
VCM = Vs/2
Figure 29. Open Loop Gain and Phase, 5V, 100kΩ Load
10
158
Phase (ƒ)
AOL (dB)
PHASE
GAIN
180
Phase (ƒ)
GAIN
120
125°C
25°C
-40°C
TA = -40, 25, 125°C
VS= 3.3V
Phase (ƒ)
125°C
25°C
-40°C
AOL (dB)
160
158
140
Phase (ƒ)
180
160
RL= 100kΩ
CL= 20pF
1k
10k
-23
100k
C002
VOUT = 200mVPP
VCM = Vs/2
Figure 30. Open Loop Gain and Phase, 3.3V, 100kΩ Load
Copyright © 2016, Texas Instruments Incorporated
TLV8811, TLV8812
www.ti.com
SNOSD35A – OCTOBER 2016 – REVISED NOVEMBER 2016
Typical Characteristics (continued)
at TA = 25°C, RL = 10MΩ to VS/2 ,CL = 20pF, VCM = VS / 2V unless otherwise specified.
125°C
25°C
-40°C
GAIN
AOL (dB)
120
158
135
100
113
80
90
68
60
PHASE
40
23
0
0
100m
10k
1
10
100
1k
10k
Frequency (Hz)
TA = -40, 25, 125°C
VS= 1.8V
1k
-23
100k
±20
10m
100k
45
20
1m
1M
180
ZO (Ÿ
140
Phase (ƒ)
160
100
100m
C003
RL= 10MΩ
CL= 20pF
AOL (dB)
113
80
90
60
68
PHASE
45
20
23
0
0
±20
1m
10m
100m
1
10
100
1k
10k
C001
VS= 5 V
RL= 10MΩ
100
10
100m
C003
RL= 1MΩ
CL= 20pF
100k
1000
-23
100k
Frequency (Hz)
TA = -40, 25, 125°C
VS= 1.8V
10k
10000
135
100
40
1k
158
9ROWDJH 1RLVH Q9¥5W+]
GAIN
120
100
Figure 32. Open Loop Output Impedance
180
125°C
25°C
-40°C
Phase (ƒ)
140
10
TA = 25°C
Figure 31. Open Loop Gain and Phase, 1.8V, 10 MΩ Load
160
1
Frequency (Hz)
VOUT = 200mVPP
VCM = Vs/2
1
10
100
1k
10k
Frequency (Hz)
VOUT = 200mVPP
VCM = Vs/2
TA = 25
VS= 5V
RL= 1MΩ
CL= 20pF
C001
VCM = Vs/2
AV = +1
Figure 33. Open Loop Gain and Phase, 1.8V, 1 MΩ Load
Figure 34. Input Voltage Noise vs Frequency
125°C
25°C
-40°C
GAIN
AOL (dB)
120
113
80
90
68
PHASE
40
45
20
23
0
0
±20
1m
10m
100m
1
10
100
Frequency (Hz)
TA = -40, 25, 125°C
VS= 1.8V
100
135
100
60
RL= 100kΩ
CL= 20pF
1k
10k
TLV8812, -20dBm
TLV8812, -10dBm
TLV8812, 0dBm
158
EMIRR (dB)
140
120
180
Phase (ƒ)
160
80
60
40
20
-23
100k
0
C003
VOUT = 200mVPP
VCM = Vs/2
10
100
1000
Frequency (MHz)
TA = 25
VS= 3.3V
RL= 1MΩ
CL= 20pF
C001
VCM = Vs/2
AV = +1
Figure 35. Open Loop Gain and Phase, 1.8V, 100kΩ Load
Figure 36. EMIRR Performance
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7 Detailed Description
7.1 Overview
The TLV8811 (single) and TLV8812 (dual) series of nanoPower CMOS operational amplifiers are designed for
long-life battery-powered and energy harvested applications. They operate on a single supply with operation as
low as 1.7V. The Input Offset is trimmed to less than 500uV and the output is rail-to-rail and swings to within
3.5mV of the supplies with a 100kΩ load. The common-mode range extends to the negative supply making it
ideal for single-supply applications. EMI protection has been employed internally to reduce the effects of EMI.
Parameters that vary significantly with operating voltages or temperature are shown in the Typical Characteristics
curves.
7.2 Functional Block Diagram
V
IN –
IN +
+
_
OUT
+
V
–
Copyright © 2016,
Texas Instruments Incorporated
7.3 Feature Description
The amplifier's differential inputs consist of a non-inverting input (+IN) and an inverting input (–IN). The amplifier
amplifies only the difference in voltage between the two inputs, which is called the differential input voltage. The
output voltage of the op-amp VOUT is given by Equation 1:
VOUT = AOL (IN+ – IN–)
where
•
AOL is the open-loop gain of the amplifier, typically around 120 dB (1,000,000x, or 1,000,000 Volts per
microvolt).
(1)
7.4 Device Functional Modes
7.4.1 Negative-Rail Sensing Input
The input common-mode voltage range of the TLV881x extends from (V-) to (V+) – 0.9 V. In this range, low
offset can be expected with a minimum of 80dB CMRR. The TLV881x is protected from output "inversions" or
"reversals".
7.4.2 Rail to Rail Output Stage
The TLV881x output voltage swings 3.5 mV from rails at 1.8 V supply, which provides the maximum possible
dynamic range at the output. This is particularly important when operating on low supply voltages.
The TLV881x Maximum Output Voltage Swing graph defines the maximum swing possible under a particular
output load.
7.4.3 Design Optimization for Nanopower Operation
When designing for ultralow power, choose system feedback components carefully. To minimize quiescent
current consumption, select large-value feedback resistors. Any large resistors will react with stray capacitance in
the circuit and the input capacitance of the operational amplifier. These parasitic RC combinations can affect the
stability of the overall system. A feedback capacitor may be required to assure stability and limit overshoot or
gain peaking.
When possible, use AC coupling and AC feedback to reduce static current draw through the feedback elements.
Use film or ceramic capacitors since large electrolytics may have large static leakage currents in the nanoamps.
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Device Functional Modes (continued)
7.4.4 Driving Capacitive Load
The TLV881x is internally compensated for stable unity gain operation, with a 6 kHz typical gain bandwidth.
However, the unity gain follower is the most sensitive configuration to capacitive load. The combination of a
capacitive load placed directly on the output of an amplifier along with the amplifier’s output impedance creates a
phase lag, which reduces the phase margin of the amplifier. If the phase margin is significantly reduced, the
response will be under damped which causes peaking in the transfer and, when there is too much peaking, the
op amp might start oscillating.
In order to drive heavy (>50pF) capacitive loads, an isolation resistor, RISO, should be used, as shown in
Figure 37. By using this isolation resistor, the capacitive load is isolated from the amplifier’s output. The larger
the value of RISO, the more stable the amplifier will be. If the value of RISO is sufficiently large, the feedback loop
will be stable, independent of the value of CL. However, larger values of RISO result in reduced output swing and
reduced output current drive. The recommended value for RISO is 30-50kΩ.
-
RISO
VOUT
VIN
+
CL
Figure 37. Resistive Isolation Of Capacitive Load
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TLV881x is a ultra-low power operational amplifier that provides 6 kHz bandwidth with only 450nA typical
quiescent current, trimmed input offset voltage and precision drift specifications. These rail-to-rail output
amplifiers are specifically designed for battery-powered applications. The input common-mode voltage range
extends to the negative supply rail and the output swings to within millivolts of the rails, maintaining a wide
dynamic range.
8.2 Typical Application: Three Terminal CO Gas Sensor Amplifier
R1
10 k
C1
0.1µF
Potentiostat (Bias Loop)
CE
RE
CO Sensor
R2
10 NŸ
2.5V
U1
+
VREF
WE
Transimpedance Amplifier (I to V conversion)
ISENS
RF
Riso
49.9 k
RL
VREF
+
U2
VTIA
C2
1µF
Figure 38. Three Terminal Gas Sensor Amplifier Schematic
8.2.1 Design Requirements
Figure 38 shows a simple micropower potentiostat circuit for use with three terminal unbiased CO sensors,
though it is applicable to many other type of three terminal gas sensors or electrochemical cells.
The basic sensor has three electrodes; The Sense or Working Electrode (“WE”), Counter Electrode (“CE”) and
Reference Electrode (“RE”). A current flows between the CE and WE proportional to the detected concentration.
The RE monitors the potential of the internal reference point. For an unbiased sensor, the WE and RE electrodes
must be maintained at the same potential by adjusting the bias on CE. Through the Potentiostat circuit formed by
U1, the servo feedback action will maintain the RE pin at a potential set by VREF.
R1 is to maintain stability due to the large capacitance of the sensor. C1 and R2 form the Potentiostat integrator
and set the feedback time constant.
U2 forms a transimpedance amplifier ("TIA") to convert the resulting sensor current into a proportional voltage.
The transimpedance gain, and resulting sensitivity, is set by RF according to Equation 2.
VTIA = (-I * RF) + VREF
(2)
RL is a load resistor of which the value is normally specified by the sensor manufacturer (typically 10 ohms). The
potential at WE is set by the applied VREF. Riso provides capacitive isolation and, combined with C2, form the
output filter and ADC reservoir capacitor to drive the ADC.
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Typical Application: Three Terminal CO Gas Sensor Amplifier (continued)
8.2.2 Detailed Design Procedure
For this example, we will be using a CO sensor with a sensitivity of 69nA/ppm. The supply voltage and maximum
ADC input voltage is 2.5V, and the maximum concentration is 300ppm.
First the VREF voltage must be determined. This voltage is a compromise between maximum headroom and
resolution, as well as allowance for "footroom" for the minimum swing on the CE terminal, since the CE terminal
generally goes negative in relation to the RE potential as the concentration (sensor current) increases. Bench
measurements found the difference between CE and RE to be 180mV at 300ppm for this particular sensor.
To allow for negative CE swing "footroom" and voltage drop across the 10k resistor, 300mV was chosen for
VREF.
Therefore +300mV will be used as the minimum VZERO to add some headroom.
VZERO = VREF = +300mV
where
•
•
VZERO is the zero concentration voltage
VREF is the reference voltage (300mV)
(3)
Next we calculate the maximum sensor current at highest expected concentration:
ISENSMAX = IPERPPM * ppmMAX = 69nA * 300ppm = 20.7uA
where
•
•
•
ISENSMAX is the maximum expected sensor current
IPERPPM is the manufacturer specified sensor current in Amps per ppm
ppmMAX is the maximum required ppm reading
(4)
Now find the available output swing range above the reference voltage available for the measurement:
VSWING = VOUTMAX – VZERO = 2.5V – 0.3V = 2.2V
where
•
•
VSWING is the expected change in output voltage
VOUTMAX is the maximum amplifier output swing (usually near V+)
(5)
Now we calculate the transimpedance resistor ®F) value using the maximum swing and the maximum sensor
current:
RF = VSWING / ISENSMAX = 2.2V / 20.7µA = 106.28 kΩ (we will use 110 kΩ for a common value)
Copyright © 2016, Texas Instruments Incorporated
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Typical Application: Three Terminal CO Gas Sensor Amplifier (continued)
8.2.3 Application Curve
2.50
Vc
Vw
2.25
Vtia
2.00
Vdif
Measured Voltage (V)
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0.00
0
15
30
45
60
75
90
105
120
135
150
Time (sec)
C007
Figure 39. Monitored Voltages when Exposed to 200ppm CO
Figure 39 shows the resulting circuit voltages when the sensor was exposed to 200ppm step of carbon monoxide
gas. VC is the monitored CE pin voltage and clearly shows the expected CE voltage dropping below the WE
voltage, VW, as the concentration increases.
VTIA is the output of the transimpedance amplifier U2. VDIFF is the calculated difference between VREF and VTIA,
which will be used for the ppm calculation.
20
300
18
250
Concentration (ppm)
Sensor Current (uA)
16
14
12
10
8
6
4
200
150
100
50
2
0
0
0
15
30
45
60
75
90
105 120 135 150
Time (sec)
0
15
30
45
Figure 40. Calculated Sensor Current
60
75
90
105 120 135 150
Time (sec)
C002
C003
Figure 41. Calculated ppm
Figure 40 shows the calculated sensor current using the formula in Equation 7 :
ISENSOR = VDIFF / RF = 1.52V / 110 kΩ = 13.8uA
(7)
Equation 8 shows the resulting conversion of the sensor current into ppm.
ppm = ISENSOR / IPERPPM = 13.8µA / 69nA = 200
(8)
Total supply current for the amplifier section is less than 700 nA, minus sensor current. Note that the sensor
current is sourced from the amplifier output, which in turn comes from the amplifier supply voltage. Therefore,
any continuous sensor current must also be included in supply current budget calculations.
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8.3 Do's and Don'ts
Do properly bypass the power supplies.
Do add series resistance to the output when driving capacitive loads, particularly cables, Muxes and ADC inputs.
Do add series current limiting resistors and external schottky clamp diodes if input voltage is expected to exceed
the supplies. Limit the current to 1mA or less (1KΩ per volt).
9 Power Supply Recommendations
The TLV881x is specified for operation from 1.7 V to 5.5 V (±0.85 V to ±2.75 V) over a –40°C to 125°C
temperature range. Parameters that can exhibit significant variance with regard to operating voltage or
temperature are presented in the Typical Characteristics.
CAUTION
Supply voltages larger than 6 V can permanently damage the device.
For proper operation, the power supplies must be properly decoupled. For decoupling the supply lines it is
suggested that 100 nF capacitors be placed as close as possible to the operational amplifier power supply pins.
For single supply, place a capacitor between V+ and V– supply leads. For dual supplies, place one capacitor
between V+ and ground, and one capacitor between V– and ground.
Low bandwidth nanopower devices do not have good high frequency (> 1 kHz) AC PSRR rejection against highfrequency switching supplies and other 1 kHz and above noise sources, so extra supply filtering is recommended
if kilohertz or above noise is expected on the power supply lines.
10 Layout
10.1 Layout Guidelines
The V+ pin should be bypassed to ground with a low ESR capacitor.
The optimum placement is closest to the V+ and ground pins.
Care should be taken to minimize the loop area formed by the bypass capacitor connection between V+ and
ground.
The ground pin should be connected to the PCB ground plane at the pin of the device.
The feedback components should be placed as close to the device as possible to minimize strays.
10.2 Layout Example
Figure 42. SOT-23 Layout Example (Top View)
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
TINA-TI SPICE-Based Analog Simulation Program, http://www.ti.com/tool/tina-ti
DIP Adapter Evaluation Module, http://www.ti.com/tool/dip-adapter-evm
TI Universal Operational Amplifier Evaluation Module, http://www.ti.com/tool/opampevm
TI FilterPro Filter Design Software, http://www.ti.com/tool/filterpro
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation, see the following:
• AN-1798 Designing with Electro-Chemical Sensors, SNOA514
• AN-1803 Design Considerations for a Transimpedance Amplifier, SNOA515
• AN-1852 Designing With pH Electrodes, SNOA529
• Compensate Transimpedance Amplifiers Intuitively, SBOA055
• Transimpedance Considerations for High-Speed Operational Amplifiers, SBOA112
• Noise Analysis of FET Transimpedance Amplifiers, SBOA060
• Circuit Board Layout Techniques, SLOA089
• Handbook of Operational Amplifier Applications, SBOA092
11.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 1. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TLV8811
Click here
Click here
Click here
Click here
Click here
TLV8812
Click here
Click here
Click here
Click here
Click here
11.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.5 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.6 Trademarks
E2E is a trademark of Texas Instruments.
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11.6 Trademarks (continued)
All other trademarks are the property of their respective owners.
11.7 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
16-Nov-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TLV8811DBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
16EM
TLV8811DBVT
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
16EM
TLV8812DGKR
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
TLV
8812
TLV8812DGKT
ACTIVE
VSSOP
DGK
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
TLV
8812
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
16-Nov-2016
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
SCALE 4.000
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
1.75
1.45
PIN 1
INDEX AREA
1
0.1 C
B
A
5
2X 0.95
1.9
1.45 MAX
3.05
2.75
1.9
2
4
0.5
5X
0.3
0.2
3
(1.1)
C A B
0.15
TYP
0.00
0.25
GAGE PLANE
8
TYP
0
0.22
TYP
0.08
0.6
TYP
0.3
SEATING PLANE
4214839/C 04/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X (0.95)
3
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214839/C 04/2017
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X(0.95)
4
3
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/C 04/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
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