TLV9001-Q1, TLV9002-Q1, TLV9004-Q1
SBOS980E – MAY 2019 – REVISED APRIL 2023
TLV900x-Q1 Low-Power RRIO 1-MHz Automotive Operational Amplifier
1 Features
3 Description
•
The TLV900x-Q1 family includes single (TLV9001Q1), dual (TLV9002-Q1), and quad-channel
(TLV9004-Q1) low-voltage (1.8 V to 5.5 V) operational
amplifiers (op amps) with rail-to-rail input and output
swing capabilities. These op amps provide a costeffective solution for space-constrained automotive
applications such as infotainment and lighting where
low-voltage operation and high capacitive-load drive
are required. The capacitive-load drive of the
TLV900x-Q1 family is 500 pF, and the resistive openloop output impedance makes stabilization easier with
much higher capacitive loads. These op amps are
designed specifically for low-voltage operation (1.8 V
to 5.5 V) with performance specifications similar to the
TLV600x-Q1 devices.
•
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•
•
•
•
•
•
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AEC-Q100 qualified for automotive applications
– Temperature grade 1: –40°C to +125°C, TA
– Device HBM ESD classification level 2
– Device CDM ESD classification level C6
Scalable CMOS amplifier for low-cost applications
Rail-to-rail input and output
Low input offset voltage: ±0.4 mV
Unity-gain bandwidth: 1 MHz
Low broadband noise: 27 nV/√ Hz
Low input bias current: 5 pA
Low quiescent current: 60 µA\/Ch
Unity-gain stable
Internal RFI and EMI filter
Operational at supply voltages as low as 1.8 V
Easier to stabilize with higher capacitive load due
to resistive open-loop output impedance
Functional Safety-Capable
– Functional Safety Information
The robust design of the TLV900x-Q1 family simplifies
circuit design. The op amps feature unity-gain
stability, an integrated RFI and EMI rejection filter, and
no-phase reversal in overdrive conditions.
2 Applications
•
•
•
•
•
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Package Information(3)
Optimized for AEC-Q100 grade 1 applications
Infotainment and Cluster
Passive safety
Body electronics and lighting
HEV/EV inverter and motor control
On-board (OBC) and wireless charger
Power-train current sensor
Advanced driver assistance systems (ADAS)
Single-supply, low-side, unidirectional currentsensing circuit
PART NUMBER (1)
TLV9001-Q1
TLV9002-Q1
DCK (SC70, 5)
1.25 mm × 2.00 mm
D (SOIC, 8)
3.91 mm × 4.90 mm
8)(2)
3.00 mm × 4.40 mm
DGK (VSSOP, 8)
3.00 mm × 3.00 mm
DYY (SOT-23, 14)
4.20 mm × 1.90 mm
D (SOIC, 14)
8.65 mm × 3.91 mm
PW (TSSOP, 14)
4.40 mm × 5.00 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
Package is for preview only.
See Device Comparison Table
(2)
(3)
RG
BODY SIZE (NOM)
1.60 mm × 2.90 mm
PW (TSSOP,
TLV9004-Q1
(1)
PACKAGE
DBV (SOT-23, 5)
RF
R1
VOUT
VIN
C1
f-3 dB =
(
RF
VOUT
= 1+
RG
VIN
((
1
1 + sR1C1
1
2pR1C1
(
Single-Pole, Low-Pass Filter
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
TLV9001-Q1, TLV9002-Q1, TLV9004-Q1
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SBOS980E – MAY 2019 – REVISED APRIL 2023
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................4
6 Pin Configuration and Functions...................................5
7 Specifications.................................................................. 8
7.1 Absolute Maximum Ratings........................................ 8
7.2 ESD Ratings............................................................... 8
7.3 Recommended Operating Conditions.........................8
7.4 Thermal Information for Single Channel..................... 8
7.5 Thermal Information for Dual Channel........................9
7.6 Thermal Information for Quad Channel...................... 9
7.7 Electrical Characteristics...........................................10
7.8 Typical Characteristics.............................................. 12
8 Detailed Description......................................................18
8.1 Overview................................................................... 18
8.2 Functional Block Diagram......................................... 18
8.3 Feature Description...................................................19
8.4 Device Functional Modes..........................................19
9 Application and Implementation.................................. 20
9.1 Application Information............................................. 20
9.2 Typical Application.................................................... 20
9.3 Power Supply Recommendations.............................24
9.4 Layout....................................................................... 25
10 Device and Documentation Support..........................26
10.1 Documentation Support.......................................... 26
10.2 Receiving Notification of Documentation Updates..26
10.3 Support Resources................................................. 26
10.4 Trademarks............................................................. 26
10.5 Electrostatic Discharge Caution..............................26
10.6 Glossary..................................................................26
11 Mechanical, Packaging, and Orderable
Information.................................................................... 26
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (November 2022) to Revision E (April 2023)
Page
• Changed the status of the DBV package from: preview to: active .................................................................... 1
Changes from Revision C (October 2021) to Revision D (December 2022)
Page
• Deleted preview tag for SC70 (5) from Device information section....................................................................1
• Changed formatting of Pin Configuration and Functions section .......................................................................5
• Added Thermal Information for Single Channel DCK package.......................................................................... 8
Changes from Revision B (March 2021) to Revision C (October 2021)
Page
• Deleted preview tag for SOT-23 (14) and TSSOP (14) from Device information section...................................1
• Added preview tags for TLV9001-Q1 SOT-23 (5) and SC70 (5) packages to Device information section.........1
• Added TLV9001-Q1 GPN to the data sheet....................................................................................................... 1
• Added TLV9001-Q1 to Device Comparison Table section .................................................................................4
• Added TLV9001-Q1 DBV (SOT-23) and DCK (SC70) in Pin Configuration and Functions section .................. 5
Changes from Revision A (June 2020) to Revision B (March 2021)
Page
• Changed the numbering format for tables, figures and cross-references throughout the document................. 1
• Added Functional Safety-Capable document link in the Features section......................................................... 1
• Deleted preview tag for VSSOP (8) from Device information section................................................................ 1
• Added note 4 to differential input voltage in Absolute Maximum Ratings table ................................................. 8
• Added Thermal Information for DGK package....................................................................................................9
• Added Thermal Information for DYY package.................................................................................................... 9
Changes from Revision * (May 2019) to Revision A (June 2020)
Page
• Changed the device status from Advance Information to Production Data ....................................................... 1
• Added end equipment links in Application section ............................................................................................ 1
• Deleted preview tag for SOIC (8) from Device information section.................................................................... 1
• Added SOT-23 (14) in Device Information section ............................................................................................ 1
• Deleted preview tag for SOIC (14) from Device information section.................................................................. 1
• Added SOT-23 (DYY) package in Device Comparison Table section ............................................................... 4
2
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•
SBOS980E – MAY 2019 – REVISED APRIL 2023
Added DYY (SOT-23) in Pin Functions: TLV9004-Q1 section ...........................................................................5
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5 Device Comparison Table
4
PACKAGE LEADS
DEVICE
NO. OF
CHANNELS
TLV9001-Q1
1
TLV9002-Q1
2
TLV9004-Q1
4
—
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SOT-23
DBV
SC70
DCK
SOIC
D
TSSOP
PW
VSSOP
DGK
SOT-23
DYY
5
5
—
—
—
—
—
8
8
8
—
—
14
14
—
14
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SBOS980E – MAY 2019 – REVISED APRIL 2023
6 Pin Configuration and Functions
OUT
1
V±
2
IN+
3
5
V+
4
IN±
IN+
1
V±
2
IN±
3
Not to scale
5
V+
4
OUT
Not to scale
Figure 6-1. TLV9001-Q1 DBV Package,
5-Pin SOT-23
(Top View)
Figure 6-2. TLV9001-Q1 DCK Package,
5-Pin SC70
(Top View)
Table 6-1. Pin Functions: TLV9001-Q1
PIN
NAME
SOT-23
SC70
IN–
4
3
IN+
3
OUT
1
V–
V+
(1)
TYPE(1)
DESCRIPTION
I
Inverting input
1
I
Noninverting input
4
O
Output
2
2
I or —
5
5
I
Negative (low) supply or ground (for single-supply operation)
Positive (high) supply
I = input, O = output
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OUT1
1
8
V+
IN1±
2
7
OUT2
IN1+
3
6
IN2±
V±
4
5
IN2+
Not to scale
Figure 6-3. TLV9002-Q1 D, DGK, PW Packages,
8-Pin SOIC, VSSOP, TSSOP
(Top View)
Table 6-2. Pin Functions: TLV9002-Q1
PIN
NAME
TYPE(1)
DESCRIPTION
IN1–
2
I
Inverting input, channel 1
IN1+
3
I
Noninverting input, channel 1
IN2–
6
I
Inverting input, channel 2
IN2+
5
I
Noninverting input, channel 2
OUT1
1
O
Output, channel 1
OUT2
7
O
Output, channel 2
V–
4
I or —
V+
8
I
(1)
6
NO.
Negative (low) supply or ground (for single-supply operation)
Positive (high) supply
I = input, O = output
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SBOS980E – MAY 2019 – REVISED APRIL 2023
OUT1
1
14
OUT4
IN1±
2
13
IN4±
IN1+
3
12
IN4+
V+
4
11
V±
IN2+
5
10
IN3+
IN2±
6
9
IN3±
OUT2
7
8
OUT3
Not to scale
Figure 6-4. TLV9004-Q1 D, PW, DYY Packages,
14-Pin SOIC, TSSOP, SOT-23
(Top View)
Table 6-3. Pin Functions: TLV9004-Q1
PIN
NAME
NO.
TYPE(1)
DESCRIPTION
IN1–
2
I
Inverting input, channel 1
IN1+
3
I
Noninverting input, channel 1
IN2–
6
I
Inverting input, channel 2
IN2+
5
I
Noninverting input, channel 2
IN3–
9
I
Inverting input, channel 3
IN3+
10
I
Noninverting input, channel 3
IN4–
13
I
Inverting input, channel 4
IN4+
12
I
Noninverting input, channel 4
NC
—
—
No internal connection
OUT1
1
O
Output, channel 1
OUT2
7
O
Output, channel 2
OUT3
8
O
Output, channel 3
OUT4
14
O
Output, channel 4
V–
11
I or —
V+
4
I
(1)
Negative (low) supply or ground (for single-supply operation)
Positive (high) supply
I = input, O = output
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
Supply voltage ([V+] – [V–])
Common-mode
Voltage(2)
Signal input pins
MIN
MAX
0
6
V
(V+) + 0.5
V
(V–) – 0.5
Differential (4)
(V+) – (V–) + 0.2
Current(2)
–10
Output short-circuit(3)
10
Continuous
Operating, TA
Junction, TJ
(1)
(2)
(3)
(4)
V
mA
mA
–55
Storage, Tstg
UNIT
–65
150
°C
150
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
Input pins are diode-clamped to the power-supply rails. Input signals that may swing more than 0.5 V beyond the supply rails must be
current limited to 10 mA or less.
Short-circuit to ground, one amplifier per package.
Differential input voltages greater than 0.5 V applied continuously can result in a shift to the input offset voltage and quiescent current
above the maximum specifications of these parameters. The magnitude of this effect increases as the ambient operating temperature
rises.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
Human-body model (HBM), per AEC
Electrostatic discharge
Q100-002(1)
±2000
Charged-device model (CDM), per AEC Q100-011
UNIT
V
±1000
AEC Q100-002 indicates that HBM stressing shall be in accordance with ANSI/ESDA/JEDEC JS-001 Specification.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VS
Supply voltage
1.8
5.5
UNIT
V
TA
Specified temperature
–40
125
°C
7.4 Thermal Information for Single Channel
TLV9001-Q1
THERMAL METRIC (1)
DBV
(SOT-23)
DCK
(SC70)
UNIT
5 PINS
5 PINS
RθJA
Junction-to-ambient thermal resistance
232.5
239.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
131.0
148.5
°C/W
RθJB
Junction-to-board thermal resistance
99.6
82.3
°C/W
ψJT
Junction-to-top characterization parameter
66.5
54.5
°C/W
ψJB
Junction-to-board characterization parameter
99.1
81.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
TBD
°C/W
(1)
(2)
8
(2)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
This package option is preview for TLV9001-Q1.
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SBOS980E – MAY 2019 – REVISED APRIL 2023
7.5 Thermal Information for Dual Channel
TLV9002-Q1
THERMAL METRIC (1)
D (SOIC)
DGK (VSSOP)
PW (TSSOP)
8 PINS
8 PINS
8 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
151.9
196.6
TBD
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
92.0
86.2
TBD
°C/W
RθJB
Junction-to-board thermal resistance
95.4
118.3
TBD
°C/W
ψJT
Junction-to-top characterization parameter
40.2
23.2
TBD
°C/W
ψJB
Junction-to-board characterization parameter
94.7
116.7
TBD
°C/W
(1)
For more information about traditional and new thermal metrics, see Semiconductor and ICPackage Thermal Metrics application
report.
7.6 Thermal Information for Quad Channel
TLV9004-Q1
THERMAL METRIC (1)
D (SOIC)
DYY (SOT-23)
PW (TSSOP)
14 PINS
14 PINS
14 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
115.1
154.3
135.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
71.2
86.8
63.5
°C/W
RθJB
Junction-to-board thermal resistance
71.1
67.9
78.4
°C/W
ψJT
Junction-to-top characterization parameter
29.6
10.1
13.6
°C/W
ψJB
Junction-to-board characterization parameter
70.7
67.5
77.9
°C/W
(1)
For more information about traditional and new thermal metrics, see Semiconductor and ICPackage Thermal Metrics application
report.
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Product Folder Links: TLV9001-Q1 TLV9002-Q1 TLV9004-Q1
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7.7 Electrical Characteristics
For VS = (V+) – (V–) = 1.8 V to 5.5 V (±0.9 V to ±2.75 V), TA = 25 °C, RL = 10 kΩ connected to VS / 2, and VCM = VOUT = VS /
2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
±0.4
±1.85
mV
OFFSET VOLTAGE
Vs = 5 V
VOS
Input offset voltage
dVOS/dT
VOS vs temperature
TA = –40°C to 125°C
PSRR
Power-supply rejection ratio
VS = 1.8 to 5.5 V, VCM = (V–)
Vs = 5 V, TA = –40°C to 125°C
±2
80
mV
±0.6
μV/°C
105
dB
INPUT VOLTAGE RANGE
VCM
Common-mode voltage range
CMRR
No phase reversal, rail-to-rail input
Common-mode rejection ratio
(V–) – 0.1
(V+) + 0.1
V
VS = 1.8 V, (V–) – 0.1 V < VCM < (V+) – 1.4 V,
TA = –40°C to 125°C
86
dB
VS = 5.5 V, (V–) – 0.1 V < VCM < (V+) – 1.4 V,
TA = –40°C to 125°C
95
dB
77
dB
VS = 1.8 V, (V–) – 0.1 V < VCM < (V+)+ 0.1 V,
TA = –40°C to 125°C
68
dB
Vs = 5 V
±5
pA
±2
pA
VS = 5.5 V, (V–) – 0.1 V < VCM < (V+) + 0.1 V,
TA = –40°C to 125°C
63
INPUT BIAS CURRENT
IB
Input bias current
IOS
Input offset current
NOISE
En
Input voltage noise (peak-to-peak)
en
Input voltage noise density
in
Input current noise density
ƒ = 0.1 Hz to 10 Hz, Vs = 5 V
4.7
μVPP
ƒ = 1 kHz, Vs = 5 V
30
nV/√Hz
ƒ = 10 kHz, Vs = 5 V
27
nV/√Hz
ƒ = 1 kHz, Vs = 5 V
23
fA/√Hz
1.5
pF
5
pF
117
dB
VS = 1.8 V, (V–) + 0.04 V < VO < (V+) – 0.04 V,
RL = 10 kΩ
100
dB
VS = 1.8 V, (V–) + 0.1 V < VO < (V+) – 0.1 V,
RL = 2 kΩ
115
dB
VS = 5.5 V, (V–) + 0.15 V < VO < (V+) – 0.15 V,
RL = 2 kΩ
130
dB
INPUT CAPACITANCE
CID
Differential
CIC
Common-mode
OPEN-LOOP GAIN
VS = 5.5 V, (V–) + 0.05 V < VO < (V+) – 0.05 V,
RL = 10 kΩ
AOL
Open-loop voltage gain
104
FREQUENCY RESPONSE
GBW
Gain-bandwidth product
Vs = 5 V
φm
Phase margin
VS = 5.5 V, G = 1
SR
Slew rate
Vs = 5 V
To 0.1%, VS = 5 V, 2 V Step , G = +1, CL = 100 pF
tS
Settling time
tOR
Overload recovery time
VS = 5 V, VIN × gain > VS
Total harmonic distortion + noise
VS = 5.5 V, VCM = 2.5 V, VO = 1 VRMS, G = +1,
f = 1 kHz, 80 kHz measurement BW
THD+N
To 0.01%, VS = 5 V, 2 V Step , G = +1, CL = 100 pF
1
MHz
78
degrees
2
V/µs
2.5
μs
3
μs
0.85
μs
0.004
%
OUTPUT
VS = 5.5 V, RL = 10 kΩ
10
20
mV
VS = 5.5 V, RL = 2 kΩ
35
55
mV
VO
Voltage output swing from supply rails
ISC
Short-circuit current
Vs = 5.5 V
ZO
Open-loop output impedance
Vs = 5 V, f = 1 MHz
±40
mA
1200
Ω
POWER SUPPLY
10
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7.7 Electrical Characteristics (continued)
For VS = (V+) – (V–) = 1.8 V to 5.5 V (±0.9 V to ±2.75 V), TA = 25 °C, RL = 10 kΩ connected to VS / 2, and VCM = VOUT = VS /
2 (unless otherwise noted)
PARAMETER
VS
IQ
TEST CONDITIONS
Specified voltage range
MIN
TYP
1.8 (±0.9)
IO = 0 mA, VS = 5.5 V
Quiescent current per amplifier
60
IO = 0 mA, VS = 5.5 V, TA = –40°C to 125°C
Power-on time
VS = 0 V to 5 V, to 90% IQ level
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50
MAX
UNIT
5.5 (±2.75)
V
80
µA
85
µA
µs
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7.8 Typical Characteristics
at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise
noted)
25
40
35
20
Population (%)
Population (%)
30
25
20
15
10
15
10
5
5
0
0
-1200 -900 -600 -300
0
300
600
0
900 1200 1500 1800
0.2
0.6
0.8
1
1.2
1.4
1.6
1.8
D002
VS = 5 V, TA = –40°C to +125°C
Figure 7-2. Offset Voltage Drift Distribution Histogram
Figure 7-1. Offset Voltage Distribution Histogram
1000
2000
800
1500
600
1000
Offset Voltage (μV)
400
200
0
-200
-400
500
0
-500
-1000
-600
-1500
-800
-1000
-40
-20
0
20
40
60
80
Temperature (°C)
100
120
-2000
-4
140
-3
-2
D003
Figure 7-3. Input Offset Voltage vs Temperature
-1
0
1
2
Common-Mode Voltage (V)
3
D004
6
800
IB
I B+
IOS
4
600
2
400
IB and IOS (pA)
Offset Voltage (PV)
4
Figure 7-4. Offset Voltage vs Common-Mode
1000
200
0
-200
-400
0
-2
-4
-6
-600
-8
-800
-1000
1.5
2
2.5
3
3.5
4
4.5
Supply Voltage (V)
5
5.5
Figure 7-5. Offset Voltage vs Supply Voltage
12
2
Offset Voltage Drift (μV/°C)
VS = 5 V
Input Offset Voltage (µV)
0.4
D001
Offset Voltage (μV)
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6
D005
-10
-40
-20
0
20
40
60
80
Temperature (qC)
100
120
140
D006
Figure 7-6. IB and IOS vs Temperature
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7.8 Typical Characteristics (continued)
at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise
noted)
160
3.5
IB
3
IB+
IOS
140
2.5
120
Gain (dB)
IB and IOS (pA)
2
1.5
1
0.5
0
-0.5
-1
100
80
60
40
-1.5
20
-2
-2.5
-3
-2
-1
0
1
Common-Mode Voltage (V)
2
0
-40
3
20
100
60
80
40
60
40
20
Open-Loop Voltage Gain (dB)
80
Gain
Phase
40
60
80
Temperature (qC)
100
120
140
D008
160
Phase (q)
Gain (dB)
120
20
140
120
100
80
60
40
20
0
10k
100k
Frequency (Hz)
1M
0
-3
D009
CL = 10 pF
-2
-1
0
1
Output Voltage (V)
2
3
D010
Figure 7-10. Open-Loop Gain vs Output Voltage
Figure 7-9. Open-Loop Gain and Phase vs Frequency
80
3
Gain = 1
Gain = 1
Gain = 100
Gain = 1000
Gain = 10
70
60
2.5
2
1.5
Output Voltage (V)
50
Gain (dB)
0
Figure 7-8. Open-Loop Gain vs Temperature
100
-20
1k
-20
D007
Figure 7-7. IB and IOS vs Common-Mode Voltage
0
VS = 5.5 V
VS = 1.8 V
40
30
20
10
0
125°C
1
85°C
25°C
-40°C
0.5
0
-0.5
-1
85°C
-1.5
25°C
-40°C
125°C
-2
-10
-2.5
-20
100
-3
1k
10k
100k
Frequency (Hz)
1M
CL = 10 pF
0
D011
5
10
15
20
25
30
35
Output Current (mA)
40
45
50
D012
Figure 7-12. Output Voltage vs Output Current (Claw)
Figure 7-11. Closed-Loop Gain vs Frequency
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7.8 Typical Characteristics (continued)
at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise
noted)
120
PSRR+
PSRR
100
Power Supply Rejection Ratio (dB)
Power Supply Rejection Ratio (dB)
120
80
60
40
20
0
100
1k
10k
Frequency (Hz)
100k
100
80
60
40
20
0
-40
1M
-20
0
20
D013
Figure 7-13. PSRR vs Frequency
40
60
80
Temperature (qC)
100
120
140
D014
VS = 1.8 V to 5.5 V
Figure 7-14. DC PSRR vs Temperature
160
Common-Mode Rejection Ratio (dB)
Common-Mode Rejection Ratio (dB)
120
100
80
60
40
20
0
100
1k
10k
Frequency (Hz)
100k
140
120
100
80
60
40
20
0
-40
1M
VS = 1.8 V
VS = 5.5 V
-20
0
D015
Figure 7-15. CMRR vs Frequency
20
40
60
80
Temperature (qC)
100
120
140
D016
VCM = (V–) – 0.1 V to (V+) – 1.4 V
Amplitude (1 PV/div)
Input Voltage Noise Spectral Density (nV/—Hz)
Figure 7-16. DC CMRR vs Temperature
Time (1 s/div)
120
100
80
60
40
20
0
10
100
1k
Frequency (Hz)
D017
Figure 7-17. 0.1 Hz to 10 Hz Integrated Voltage Noise
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10k
100k
D018
Figure 7-18. Input Voltage Noise Spectral Density
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7.8 Typical Characteristics (continued)
at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise
noted)
0
-50
G = +1, RL = 2 k:
G = +1, RL = 10 k:
-20
THD + N (dB)
-60
THD + N (dB)
G = 1, RL = 2 k:
G = 1, RL = 10 k:
-70
-80
-40
-60
-80
-90
RL = 2K
RL = 10K
-100
100
1k
Frequency (Hz)
VS = 5.5 V
BW = 80 kHz
-100
0.001
10k
VCM = 2.5 V
VOUT = 0.5 VRMS
G=1
1
2
D020
VCM = 2.5 V
BW = 80 kHz
f = 1 kHz
Figure 7-20. THD + N vs Amplitude
70
70
60
60
Quiescent Current (PA)
Quiescent Current (PA)
0.1
Amplitude (V RMS)
VS = 5.5 V
G=1
Figure 7-19. THD + N vs Frequency
50
40
30
20
50
40
30
20
10
10
0
1.5
2
2.5
3
3.5
4
Voltage Supply (V)
4.5
5
0
-40
5.5
1800
45
1600
40
1400
35
Overshoot (%)
50
1200
1000
800
100
120
140
D022
20
15
10
200
5
1M
40
60
80
Temperature (qC)
25
400
100k
Frequency (Hz)
20
30
600
10k
0
Figure 7-22. Quiescent Current vs Temperature
2000
0
1k
-20
D021
Figure 7-21. Quiescent Current vs Supply Voltage
Open-Loop Output Impedance (:)
0.01
D019
10M
Overshoot (+)
Overshoot (–)
0
0
200
D023
Figure 7-23. Open-Loop Output Impedance vs Frequency
G=1
400
600
Capacitance Load (pF)
800
1000
D024
VIN = 100 mVpp
Figure 7-24. Small Signal Overshoot vs Capacitive Load
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7.8 Typical Characteristics (continued)
at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise
noted)
50
90
45
80
40
70
Phase Margin (q)
Overshoot (%)
35
30
25
20
15
60
50
40
30
20
10
Overshoot (+)
Overshoot (–)
5
10
0
0
0
200
G = –1
400
600
Capacitance Load (pF)
800
0
1000
200
D025
400
600
Capacitance Load (pF)
800
1000
D026
Figure 7-26. Phase Margin vs Capacitive Load
VIN = 100 mVpp
Figure 7-25. Small Signal Overshoot vs Capacitive Load
VOUT
VIN
Amplitude (1 V/div)
Amplitude (1 V/div)
VOUT
VIN
Time (100 Ps/div)
Time (20 Ps/div)
D027
G=1
D028
VIN = 6.5 VPP
G = –10
Figure 7-27. No Phase Reversal
VIN = 600 mVPP
Figure 7-28. Overload Recovery
VOUT
VIN
Voltage (1 V/div)
Voltage (20 mV/div)
VOUT
VIN
Time (10 Ps/div)
Time (10 Ps/div)
D029
G=1
VIN = 100 mVPP
CL = 10 pF
Figure 7-29. Small-Signal Step Response
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D030
G=1
VIN = 4 VPP
CL = 10 pF
Figure 7-30. Large-Signal Step Response
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7.8 Typical Characteristics (continued)
Output Voltage (1 mV/div)
Output Voltage (1 mV/div)
at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise
noted)
Time (1 Ps/div)
Time (1 μs/div)
D032
D031
G=1
CL = 100 pF
G=1
2-V step
Figure 7-32. Large-Signal Settling Time (Positive)
80
6
Maximum Output Voltage (V)
Short Circuit Current (mA)
2-V step
Figure 7-31. Large-Signal Settling Time (Negative)
60
40
20
0
-20
-40
-60
-80
-40
VS = 5.5 V
VS = 1.8 V
5
4
3
2
1
Sinking
Sourcing
0
-20
0
20
40
60
Temperature (qC)
80
100
1
120
100
1k
10k
100k
Frequency (Hz)
1M
10M
100M
D034
Figure 7-34. Maximum Output Voltage vs Frequency
0
120
-20
Channel Separation (dB)
140
100
80
60
40
-40
-60
-80
-100
-120
20
0
10M
10
D033
Figure 7-33. Short-Circuit Current vs Temperature
EMIRR (dB)
CL = 100 pF
100M
1G
Frequency (Hz)
10G
-140
1k
10k
D035
Figure 7-35. Electromagnetic Interference Rejection Ratio
Referred to Noninverting Input (EMIRR+) vs Frequency
100k
Frequency (Hz)
1M
10M
D036
Figure 7-36. Channel Separation
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8 Detailed Description
8.1 Overview
The TLV900x-Q1 is a family of automotive qualified, low-power, rail-to-rail input and output op amps. These
devices operate from 1.8 V to 5.5 V, are unity-gain stable, and are designed for a wide range of general-purpose
applications. The input common-mode voltage range includes both rails and allows the TLV900x-Q1 family to be
used in virtually any single-supply application. Rail-to-rail input and output swing significantly increases dynamic
range, especially in low-supply applications, and makes them suitable for driving sampling analog-to-digital
converters (ADCs).
8.2 Functional Block Diagram
V+
Reference
Current
VIN+
VINVBIAS1
Class AB
Control
Circuitry
VO
VBIAS2
V(Ground)
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8.3 Feature Description
8.3.1 Operating Voltage
The TLV900x-Q1 family of op amps are for operation from 1.8 V to 5.5 V. In addition, many specifications such
as input offset voltage, quiescent current, offset current, and short circuit current apply from –40°C to 125°C.
Parameters that vary significantly with operating voltages or temperature are shown in the typical characteristics
section.
8.3.2 Rail-to-Rail Input
The input common-mode voltage range of the TLV900x-Q1 family extends 100 mV beyond the supply rails for
the full supply voltage range of 1.8 V to 5.5 V. This performance is achieved with a complementary input stage:
an N-channel input differential pair in parallel with a P-channel differential pair, as shown in the Functional Block
Diagram section. The N-channel pair is active for input voltages close to the positive rail, typically (V+) – 1.4 V
to 100 mV above the positive supply, whereas the P-channel pair is active for inputs from 100 mV below the
negative supply to approximately (V+) – 1.4 V. There is a small transition region, typically (V+) – 1.2 V to (V+) – 1
V, in which both pairs are on. This 100-mV transition region can vary up to 100 mV with process variation. Thus,
the transition region (with both stages on) can range from (V+) – 1.4 V to (V+) – 1.2 V on the low end, and up to
(V+) – 1 V to (V+) – 0.8 V on the high end. Within this transition region, PSRR, CMRR, offset voltage, offset drift,
and THD can degrade compared to device operation outside this region.
8.3.3 Rail-to-Rail Output
Designed as a low-power, low-voltage operational amplifier, the TLV900x-Q1 family delivers a robust output
drive capability. A class-AB output stage with common-source transistors achieves full rail-to-rail output swing
capability. For resistive loads of 10 kΩ, the output swings to within 20 mV of either supply rail, regardless of the
applied power-supply voltage. Different load conditions change the ability of the amplifier to swing close to the
rails.
8.3.4 Overload Recovery
Overload recovery is defined as the time required for the operational amplifier output to recover from a saturated
state to a linear state. The output devices of the operational amplifier enter a saturation region when the output
voltage exceeds the rated operating voltage, because of the high input voltage or the high gain. After the device
enters the saturation region, the charge carriers in the output devices require time to return to the linear state.
After the charge carriers return to the linear state, the device begins to slew at the specified slew rate. Therefore,
the propagation delay (in case of an overload condition) is the sum of the overload recovery time and the slew
time. The overload recovery time for the TLV900x-Q1 family is approximately 850 ns.
8.4 Device Functional Modes
The TLV900x-Q1 family has a single functional mode. The devices are powered on as long as the power-supply
voltage is between 1.8 V (±0.9 V) and 5.5 V (±2.75 V).
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The TLV900x-Q1 family of low-power, rail-to-rail input and output operational amplifiers is specifically designed
for portable applications. The devices operate from 1.8 V to 5.5 V, are unity-gain stable, and are suitable for a
wide range of general-purpose applications. The class AB output stage is capable of driving less than or equal to
10‑kΩ loads connected to any point between V+ and V–. The input common-mode voltage range includes both
rails, and allows the TLV900x-Q1 devices to be used in any single-supply application.
9.2 Typical Application
9.2.1 TLV900x-Q1 Low-Side, Current Sensing Application
Figure 9-1 shows the TLV900x-Q1 configured in a low-side current sensing application.
VBUS
ILOAD
ZLOAD
5V
+
TLV9002-Q1
VSHUNT
VOUT
+
RSHUNT
0.1
RF
57.6 k
RG
1.2 k
Figure 9-1. TLV900x-Q1 in a Low-Side, Current-Sensing Application
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9.2.1.1 Design Requirements
The design requirements for this design are:
• Load current: 0 A to 1 A
• Output voltage: 4.9 V
• Maximum shunt voltage: 100 mV
9.2.1.2 Detailed Design Procedure
The transfer function of the circuit in Figure 9-1 is given in Equation 1:
VOUT = ILOAD × RSHUNT × Gain
(1)
The load current (ILOAD) produces a voltage drop across the shunt resistor (RSHUNT). The load current is set
from 0 A to 1 A. To keep the shunt voltage below 100 mV at maximum load current, the largest shunt resistor is
shown using Equation 2:
V
RSHUNT = ISHUNT_MAX = 100 mV
1 A = 100 mΩ
(2)
LOAD_MAX
Using Equation 2, RSHUNT is calculated to be 100 mΩ. The voltage drop produced by ILOAD and RSHUNT is
amplified by the TLV900x-Q1 to produce an output voltage of approximately 0 V to 4.9 V. The gain needed by
the TLV900x-Q1 to produce the necessary output voltage is calculated using Equation 3:
Gain =
VOUT_MAX − VOUT_MIN
VIN_MAX − VIN_MIN
(3)
Using Equation 3, the required gain is calculated to be 49 V/V, which is set with resistors RF and RG. Equation 4
sizes the resistors RF and RG, to set the gain of the TLV900x-Q1 to 49 V/V.
Gain = 1 +
RF
RG
(4)
Selecting RF as 57.6 kΩ and RG as 1.2 kΩ provides a combination that equals 49 V/V. Figure 9-2 shows the
measured transfer function of the circuit shown in Figure 9-1. Notice that the gain is only a function of the
feedback and gain resistors. This gain is adjusted by varying the ratio of the resistors and the actual resistors
values are determined by the impedance levels that the designer wants to establish. The impedance level
determines the current drain, the effect that stray capacitance has, and a few other behaviors. There is no
optimal impedance selection that works for every system, choose an impedance that is ideal for the system
parameters.
9.2.1.3 Application Curve
5
Output (V)
4
3
2
1
0
0
0.2
0.4
0.6
ILOAD (A)
0.8
1
C219
Figure 9-2. Low-Side, Current-Sense Transfer Function
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9.2.2 Single-Supply Photodiode Amplifier
Photodiodes are used in many applications to convert light signals to electrical signals. The current through
the photodiode is proportional to the photon energy absorbed, and is commonly in the range of a few hundred
picoamps to a few tens of microamps. An amplifier in a transimpedance configuration is typically used to convert
the low-level photodiode current to a voltage signal for processing in an MCU. The circuit shown in Figure 9-3 is
an example of a single-supply photodiode amplifier circuit using the TLV9002-Q1.
+3.3V
R1
11.5 k
CF
10 pF
VREF
R2
357
RF
309 k
3.3 V
–
VOUT
TLV9002-Q1
VREF
IIN
0-10 µA
CPD
47 pF
+
RL
10 k
Figure 9-3. Single-Supply Photodiode Amplifier Circuit
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9.2.2.1 Design Requirements
The design requirements for this design are:
•
•
•
•
Supply voltage: 3.3 V
Input: 0 µA to 10 µA
Output: 0.1 V to 3.2 V
Bandwidth: 50 kHz
9.2.2.2 Detailed Design Procedure
The transfer function between the output voltage (VOUT), the input current, (IIN) and the reference voltage (VREF)
is defined in Equation 5.
Where:
VOUT = IIN × RF + VREF
(5)
R ×R
VREF = V+ × R1 + R2
1
2
(6)
Set VREF to 100 mV to meet the minimum output voltage level by setting R1 and R2 to meet the required ratio
calculated in Equation 7.
VREF
0.1 V
V+ = 3.3 V = 0.0303
(7)
The closest resistor ratio to meet this ratio sets R1 to 11.5 kΩ and R2 to 357 Ω.
The required feedback resistance can be calculated based on the input current and desired output voltage.
V
− VREF
− 0.1 V
RF = OUTI
= 3.2 V
= 310 kV
10 µA
A ≈ 309 kΩ
IN
(8)
Calculate the value for the feedback capacitor based on RF and the desired –3-dB bandwidth, (f–3
Equation 9.
1
CF = 2 × π × R1 × f
= 2 × π × 309 kΩ
× 50 kHz = 10.3 pF ≈ 10 pF
F
−3 dB
dB)
using
(9)
The minimum op amp bandwidth required for this application is based on the value of RF, CF, and the
capacitance on the INx– pin of the TLV9002-Q1 which is equal to the sum of the photodiode shunt capacitance,
(CPD) the common-mode input capacitance, (CCM) and the differential input capacitance (CD) as Equation 10
shows.
CIN = CPD + CCM + CD = 47 pF + 5 pF + 1 pF = 53 pF
(10)
The minimum op amp bandwidth is calculated in Equation 11.
C
+ C
F
f = BGW ≥ 2 × πIN
× RF × CF2 ≥ 324 kHz
(11)
The 1-MHz bandwidth of the TLV900x-Q1 meets the minimum bandwidth requirement and remains stable in this
application configuration.
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9.2.2.3 Application Curves
The measured current-to-voltage transfer function for the photodiode amplifier circuit is shown in Figure 9-4. The
measured performance of the photodiode amplifier circuit is shown in Figure 9-5.
3
120
2.5
Output Voltage (V)
Gain (dB)
100
80
2
1.5
1
60
0.5
40
10
0
100
1k
10k
Frequency (Hz)
100k
1M
0
2E-6
D001
Figure 9-4. Photodiode Amplifier Circuit AC Gain
Results
4E-6
6E-6
Input Current (A)
8E-6
1E-5
D002
Figure 9-5. Photodiode Amplifier Circuit DC
Results
9.3 Power Supply Recommendations
The TLV900x-Q1 family is specified for operation from 1.8 V to 5.5 V (±0.9 V to ±2.75 V); many specifications
apply from –40°C to 125°C. The Typical Characteristics section presents parameters that may exhibit significant
variance with regard to operating voltage or temperature.
CAUTION
Supply voltages larger than 6 V may permanently damage the device; see the Absolute Maximum
Ratings table.
Place 0.1-µF bypass capacitors close to the power-supply pins to reduce coupling errors from noisy or highimpedance power supplies. For more detailed information on bypass capacitor placement, see the Layout
Guidelines section.
9.3.1 Input and ESD Protection
The TLV900x-Q1 family incorporates internal ESD protection circuits on all pins. For input and output pins, this
protection primarily consists of current-steering diodes connected between the input and power-supply pins.
These ESD protection diodes provide in-circuit, input overdrive protection, as long as the current is limited to
10 mA. Figure 9-6 shows how a series input resistor can be added to the driven input to limit the input current.
The added resistor contributes thermal noise at the amplifier input and the value must be kept to a minimum in
noise-sensitive applications.
V+
IOVERLOAD
10-mA maximum
Device
VOUT
VIN
5 kW
Figure 9-6. Input Current Protection
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9.4 Layout
9.4.1 Layout Guidelines
For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:
•
•
•
•
•
•
•
•
Noise can propagate into analog circuitry through the power connections of the board and propagate to the
power pins of the op amp itself. Bypass capacitors are used to reduce the coupled noise by providing a
low-impedance path to ground.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is adequate for single-supply
applications.
Separate grounding for analog and digital portions of circuitry is one of the simplest and most effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise pickup. Take care
to physically separate digital and analog grounds, paying attention to the flow of the ground current. For more
detailed information, see Circuit Board Layout Techniques.
To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible.
If these traces cannot be kept separate, crossing the sensitive trace at a 90 degree angle is much better as
opposed to running the traces in parallel with the noisy trace.
Place the external components as close to the device as possible, as shown in Figure 9-8. Keeping RF and
RG close to the inverting input minimizes parasitic capacitance.
Keep the length of input traces as short as possible. Remember that the input traces are the most sensitive
part of the circuit.
Consider a driven, low-impedance guard ring around the critical traces. A guard ring may significantly reduce
leakage currents from nearby traces that are at different potentials.
Cleaning the PCB following board assembly is recommended for best performance.
Any precision integrated circuit can experience performance shifts resulting from moisture ingress into the
plastic package. Following any aqueous PCB cleaning process, baking the PCB assembly is recommended
to remove moisture introduced into the device packaging during the cleaning process. A low-temperature,
post-cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
9.4.2 Layout Example
+
VIN 1
+
VIN 2
VOUT 1
RG
VOUT 2
RG
RF
RF
Figure 9-7. Schematic Representation for Figure 11-2
Place components
close to device and to
each other to reduce
parasitic errors .
OUT 1
VS+
OUT1
Use low-ESR,
ceramic bypass
capacitor . Place as
close to the device
as possible .
GND
V+
RF
OUT 2
GND
IN1 ±
OUT2
IN1 +
IN2 ±
RF
RG
VIN 1
GND
RG
V±
Use low-ESR,
ceramic bypass
capacitor . Place as
close to the device
as possible .
GND
VS±
IN2 +
Ground (GND) plane on another layer
VIN 2
Keep input traces short
and run the input traces
as far away from
the supply lines
as possible .
Figure 9-8. Layout Example
Copyright © 2023 Texas Instruments Incorporated
Product Folder Links: TLV9001-Q1 TLV9002-Q1 TLV9004-Q1
Submit Document Feedback
25
TLV9001-Q1, TLV9002-Q1, TLV9004-Q1
www.ti.com
SBOS980E – MAY 2019 – REVISED APRIL 2023
10 Device and Documentation Support
10.1 Documentation Support
10.1.1 Related Documentation
For related documentation, see the following:
•
Texas Instruments, EMI Rejection Ratio of Operational Amplifiers
10.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
10.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
10.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
26
Submit Document Feedback
Copyright © 2023 Texas Instruments Incorporated
Product Folder Links: TLV9001-Q1 TLV9002-Q1 TLV9004-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
17-Jun-2023
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TLV9001QDBVRQ1
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
2T5H
Samples
TLV9001QDCKRQ1
ACTIVE
SC70
DCK
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
1MZ
Samples
TLV9002QDGKRQ1
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
27DT
Samples
TLV9002QDRQ1
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
T9002Q
Samples
TLV9004QDRQ1
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
LV9004Q
Samples
TLV9004QDYYRQ1
ACTIVE
SOT-23-THIN
DYY
14
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TLV9004Q
Samples
TLV9004QPWRQ1
ACTIVE
TSSOP
PW
14
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
T9004Q
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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