TLV9041, TLV9042, TLV9044
SBOS836G – MARCH 2020 – REVISED MARCH 2022
TLV904x 1.2-V Ultra Low Voltage, 10µA Micro-Power RRIO Amplifier for
Power Conscious Applications
1 Features
•
•
•
•
•
•
•
•
•
•
•
•
•
Low power CMOS amplifier for cost-optimized
applications
Operational from supply voltage as low as 1.2 V
Low input bias current: 1-pA typical, 12-pA
maximum
Low quiescent current: 10 µA/ch
Low integrated noise of 6.5 µVp-p in 0.1 Hz – 10 Hz
Rail-to-rail input and output
High gain bandwidth product: 350 kHz
Thermal noise floor: 64 nV/√Hz
Low input offset voltage: ±0.6 mV
Unity-gain stable
Robustly drives 100 pF of load capacitance
Internal RFI and EMI filtered input pins
Wide specified temperature range: –40°C to 125°C
2 Applications
•
•
•
•
•
•
•
•
•
Portable electronics
Wearable fitness and activity monitor
Headsets/headphones and earbuds
Personal electronics
Building automation
Wearables (non-medical)
Motion detector (PIR, uWave, etc.)
Electronic point of sales (EPOS)
Single-supply, low-side, unidirectional currentsensing circuit
3 Description
The low-power TLV904x family includes single
(TLV9041), dual (TLV9042), and quad-channel
(TLV9044) ultra-low-voltage (1.2 V to 5.5 V)
operational amplifiers (op-amps) with rail-to-rail input
and output swing capabilities. The TLV904x enables
power savings both with its low quiescent current
(10 µA, typ.) and the ability to operate at supply
voltages as low as 1.2 V, making it one of the few
amplifiers in the industry capable of 1.5-V coin cell
applications. Further power savings can be achieved
using the shutdown mode (TLV9041S, TLV9042S,
and TLV9044S) that allows the amplifiers to be
switched off and enter into a standby mode with
typical current consumption of less than 150 nA.
These devices offer a cost-effective amplifier solution
for power and space-constrained applications such
as battery-powered IoT devices, wearable electronics,
and personal electronics where low-voltage operation
is crucial.
The robust design of the TLV904x family simplifies
circuit design. These op-amps feature an integrated
RFI and EMI rejection filter, unity-gain stability, and
no-phase reversal in input overdrive conditions. The
device also delivers excellent AC performance with
a gain bandwidth of 350 kHz and a high cap load
drive of 100 pF, enabling designers to achieve both
improved performance and lower power consumption.
Space-saving micro-size packages, such as X2QFN
and WSON, are offered for all channel variants
(single, dual, and quad), along with industry-standard
packages such as SOIC, VSSOP, TSSOP, and
SOT-23 packages.
Device Information
PART NUMBER(1) (2)
TLV9041
TLV9041S
TLV9042
TLV9042S
TLV9044
(1)
(2)
PACKAGE
BODY SIZE (NOM)
SOT-23 (5)
1.60 mm × 2.90 mm
SC70 (5)
1.25 mm × 2.00 mm
X2SON (5)
0.80 mm × 0.80 mm
SOT-23 (6)
1.60 mm × 2.90 mm
SOIC (8)
3.91 mm × 4.90 mm
SOT-23 (8)
1.60 mm × 2.90 mm
WSON (8)
2.00 mm × 2.00 mm
VSSOP (8)
3.00 mm × 3.00 mm
TSSOP (8)
3.00 mm × 4.40 mm
X2QFN (10)
1.50 mm × 2.00 mm
SOIC (14)
8.65 mm × 3.91 mm
TSSOP (14)
4.40 mm × 5.00 mm
SOT-23 (14)
4.20 mm × 1.90 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
Other single and dual channel package variants will release
shortly.
RG
RF
R1
VOUT
VIN
C1
f-3 dB =
(
RF
VOUT
= 1+
RG
VIN
((
1
1 + sR1C1
1
2pR1C1
(
Single-Pole, Low-Pass Filter
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLV9041, TLV9042, TLV9044
www.ti.com
SBOS836G – MARCH 2020 – REVISED MARCH 2022
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 7
7.1 Absolute Maximum Ratings........................................ 7
7.2 ESD Ratings .............................................................. 7
7.3 Recommended Operating Conditions.........................7
7.4 Thermal Information for Single Channel..................... 7
7.5 Thermal Information for Dual Channel........................8
7.6 Thermal Information for Quad Channel...................... 8
7.7 Electrical Characteristics.............................................9
7.8 Typical Characteristics.............................................. 11
8 Detailed Description......................................................19
8.1 Overview................................................................... 19
8.2 Functional Block Diagram......................................... 19
8.3 Feature Description...................................................20
8.4 Device Functional Modes..........................................24
9 Application and Implementation.................................. 25
9.1 Application Information............................................. 25
9.2 Typical Application.................................................... 25
10 Power Supply Recommendations..............................28
11 Layout........................................................................... 29
11.1 Layout Guidelines................................................... 29
11.2 Layout Example...................................................... 29
12 Device and Documentation Support..........................31
12.1 Documentation Support.......................................... 31
12.2 Receiving Notification of Documentation Updates..31
12.3 Support Resources................................................. 31
12.4 Electrostatic Discharge Caution..............................31
12.5 Glossary..................................................................31
13 Mechanical, Packaging, and Orderable
Information.................................................................... 31
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (February 2022) to Revision G (March 2022)
Page
• Updated Device Information section for X2SON (5) RTM.................................................................................. 1
• Updated Device Comparison section for TLV9041IDPWR RTM........................................................................ 3
• Added Thermal Information for TLV9041 DPW package to the Thermal Information for Single Channel
section ............................................................................................................................................................... 7
Changes from Revision E (August 2021) to Revision F (February 2022)
Page
• Updated Device Comparison section for TLV9044IDYYR RTM......................................................................... 3
• Added Thermal Information for TLV9044 DYY package to the Thermal Information for Quad Channel section
............................................................................................................................................................................7
Changes from Revision D (August 2021) to Revision E (August 2021)
Page
• Added Thermal Information for TLV9042 DGK package to the Thermal Information for Dual Channel section ..
7
2
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SBOS836G – MARCH 2020 – REVISED MARCH 2022
5 Device Comparison Table
DEVICE
NO. OF
CHANNELS
PACKAGE LEADS
SC70
DCK
SOIC
D
SOT-23
DBV
SOT-23
DYY
SOT-23-8
DDF
SOT-553
DRL(1)
TSSOP
PW
VSSOP
DGK
WQFN
RTE(1)
WSON
DSG
X2QFN
RUC(1)
X2SON
DPW
X2QFN
RUG
TLV9041
1
5
—
5
—
—
5
—
—
—
—
—
5
—
TLV9041S
1
—
—
6
—
—
—
—
—
—
—
—
—
—
TLV9042
2
—
8
—
—
8
—
8
8
—
8
—
—
—
TLV9042S
2
—
—
—
—
—
—
—
—
—
—
—
—
10
TLV9044
4
—
14
—
14
—
—
14
—
16
—
14
—
—
(1)
Package is preview only.
6 Pin Configuration and Functions
OUT
1
V±
2
IN+
3
5
V+
4
IN±
IN+
1
V±
2
IN±
3
Not to scale
V±
2
4
OUT
Figure 6-2. TLV9041U DBV Package
5-Pin SOT-23
Top View
OUT
1
V+
Not to scale
Figure 6-1. TLV9041 DBV Package
5-Pin SOT-23
Top View
IN+
5
5
1
5
V+
4
IN+
V+
3
IN±
3
4
V±
OUT
IN±
2
Not to scale
Not to scale
Figure 6-4. TLV9041 DPW Package
5-Pin X2SON
Top View
Figure 6-3. TLV9041 DCK Package
5-Pin SC70
Top View
Table 6-1. Pin Functions: TLV9041 and TLV9041U
PIN
NO.
NAME
TLV9041
SOT-23
SC70
TLV9041U
X2SON
SOT-23
IN–
4
3
2
3
IN+
3
1
4
OUT
1
4
1
V–
2
2
3
2
V+
5
5
5
5
I/O
DESCRIPTION
I
Inverting input
1
I
Noninverting input
4
O
Output
I or — Negative (low) supply or ground (for single-supply operation)
I
Positive (high) supply
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SBOS836G – MARCH 2020 – REVISED MARCH 2022
OUT
1
6
V+
V±
2
5
SHDN
IN+
3
4
IN±
Not to scale
Figure 6-5. TLV9041S DBV Package
6-Pin SOT-23
Top View
Table 6-2. Pin Functions: TLV9041S
PIN
NAME
NO.
I/O
DESCRIPTION
IN–
4
I
Inverting input
IN+
3
I
Noninverting input
OUT
1
O
Output
SHDN
5
I
Shutdown (low), enabled (high)
V–
2
I or —
V+
6
I
Negative (low) supply or ground (for single-supply operation)
Positive (high) supply
OUT1
1
8
V+
IN1±
2
7
OUT2
IN1+
3
6
IN2±
V±
4
5
IN2+
OUT1
1
IN1±
2
IN1+
3
V±
4
Thermal
Pad
8
V+
7
OUT2
6
IN2±
5
IN2+
Not to scale
Figure 6-6. TLV9042 D, DDF, DGK, and PW Package
8-Pin SOIC, SOT-23 8, VSSOP, and TSSOP
Top View
Not to scale
Connect exposed thermal pad to V–. See Section 8.3.11 for
more information.
Figure 6-7. TLV9042 DSG Package
8-Pin WSON With Exposed Thermal Pad
Top View
Table 6-3. Pin Functions: TLV9042
PIN
NAME
4
NO.
I/O
DESCRIPTION
IN1–
2
I
Inverting input, channel 1
IN1+
3
I
Noninverting input, channel 1
IN2–
6
I
Inverting input, channel 2
IN2+
5
I
Noninverting input, channel 2
OUT1
1
O
Output, channel 1
OUT2
7
O
Output, channel 2
V–
4
I
Negative (low) supply or ground (for single-supply operation)
V+
8
I
Positive (high) supply
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IN1+
SBOS836G – MARCH 2020 – REVISED MARCH 2022
1
9
IN1±
SHDN1
2
8
OUT1
SHDN2
3
7
V+
IN2+
4
6
OUT2
5
10
V±
IN2±
Not to scale
Figure 6-8. TLV9042S RUG Package
10-Pin X2QFN
Top View
Table 6-4. Pin Functions: TLV9042S
PIN
NAME
NO.
I/O
DESCRIPTION
IN1–
9
I
Inverting input, channel 1
IN1+
10
I
Noninverting input, channel 1
IN2–
5
I
Inverting input, channel 2
IN2+
4
I
Noninverting input, channel 2
OUT1
8
O
Output, channel 1
OUT2
6
O
Output, channel 2
SHDN1
2
I
Shutdown – low = disabled, high = enabled, channel 1
SHDN2
3
I
Shutdown – low = disabled, high = enabled, channel 2
V–
1
I
Negative (low) supply or ground (for single-supply operation)
V+
7
I
Positive (high) supply
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OUT1
1
14
OUT4
IN1±
2
13
IN4±
IN1+
3
12
IN4+
V+
4
11
V±
IN2+
5
10
IN3+
IN2±
6
9
IN3±
OUT2
7
8
OUT3
Not to scale
Figure 6-9. TLV9044 D, PW and DYY Packages
14-Pin SOIC, TSSOP and SOT-23
Top View
Table 6-5. Pin Functions: TLV9044
PIN
NAME
6
NO.
I/O
DESCRIPTION
IN1–
2
I
Inverting input, channel 1
IN1+
3
I
Noninverting input, channel 1
IN2–
6
I
Inverting input, channel 2
IN2+
5
I
Noninverting input, channel 2
IN3–
9
I
Inverting input, channel 3
IN3+
10
I
Noninverting input, channel 3
IN4–
13
I
Inverting input, channel 4
IN4+
12
I
Noninverting input, channel 4
NC
—
—
No internal connection
OUT1
1
O
Output, channel 1
OUT2
7
O
Output, channel 2
OUT3
8
O
Output, channel 3
OUT4
14
O
Output, channel 4
V–
11
I or —
V+
4
I
Negative (low) supply or ground (for single-supply operation)
Positive (high) supply
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7 Specifications
7.1 Absolute Maximum Ratings
over operating ambient temperature range (unless otherwise noted) (1)
MIN
MAX
0
6.0
V
(V–) – 0.5
(V+) + 0.5
V
Supply voltage, VS = (V+) – (V–)
Common-mode voltage
(2)
Differential voltage (2)
Signal input pins
VS + 0.2
Current (2)
–10
Output short-circuit (3)
–55
Junction temperature, TJ
Storage temperature, Tstg
(2)
(3)
V
10
mA
150
°C
150
°C
150
°C
Continuous
Operating ambient temperature, TA
(1)
UNIT
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
Input pins are diode-clamped to the power-supply rails. Input signals that may swing more than 0.5 V beyond the supply rails must be
current limited to 10 mA or less.
Short-circuit to ground, one amplifier per package.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±3000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
MIN
MAX
1.2
5.5
Input voltage range
(V–)
(V+)
V
Specified temperature
–40
125
°C
VS
Supply voltage, (V+) – (V–)
VI
TA
UNIT
V
7.4 Thermal Information for Single Channel
TLV9041, TLV9041S
THERMAL METRIC
DBV
(SOT-23)
(1)
DCK
(SC70)
DPW
(X2SON)
UNIT
5 PINS
6 PINS
5 PINS
5 PINS
RθJA
Junction-to-ambient thermal resistance
235.4
214.6
233.8
478.7
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
135.1
134.2
130.7
219.4
°C/W
RθJB
Junction-to-board thermal resistance
103.2
95.6
79.7
345.1
°C/W
ψJT
Junction-to-top characterization parameter
75.6
73.8
51.6
32.9
°C/W
ψJB
Junction-to-board characterization parameter
102.7
95.3
79.1
343.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
n/a
n/a
192.7
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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SBOS836G – MARCH 2020 – REVISED MARCH 2022
7.5 Thermal Information for Dual Channel
TLV9042
THERMAL METRIC (1)
TLV9042S
D
(SOIC)
DDF
(SOT-23-8)
DSG
(WSON)
PW
(TSSOP)
DGK
(VSSOP)
RUG
(X2QFN)
8 PINS
8 PINS
8 PINS
8 PINS
8 PINS
10 PINS
UNIT
RθJA
Junction-to-ambient thermal
resistance
148.3
203.8
99.8
203.1
196.6
196.9
°C/W
RθJC(top)
Junction-to-case (top) thermal
resistance
89.8
123.9
122.2
91.9
87.5
87.6
°C/W
RθJB
Junction-to-board thermal
resistance
91.6
121.6
66.0
133.8
118.5
117.8
°C/W
ψJT
Junction-to-top
characterization parameter
38.6
21.7
13.8
23.7
25.7
3.4
°C/W
ψJB
Junction-to-board
characterization parameter
90.9
199.6
65.9
132.1
116.8
117.6
°C/W
RθJC(bot)
Junction-to-case (bottom)
thermal resistance
n/a
n/a
41.9
n/a
n/a
n/a
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
7.6 Thermal Information for Quad Channel
TLV9044, TLV9044S
THERMAL METRIC
D
(SOIC)
PW
(TSSOP)
DYY
(SOT-23-14)
UNIT
14 PINS
14 PINS
14 PINS
RθJA
Junction-to-ambient thermal resistance
116.4
135.7
152.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
72.5
78.8
86.2
°C/W
RθJB
Junction-to-board thermal resistance
72.4
63.9
67.4
°C/W
ψJT
Junction-to-top characterization parameter
30.8
14.2
10.1
°C/W
ψJB
Junction-to-board characterization parameter
72
78.3
67.2
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
n/a
n/a
°C/W
(1)
8
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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7.7 Electrical Characteristics
For VS = (V+) – (V–) = 1.2 V to 5.5 V (±0.6 V to ±2.75 V) at TA = 25°C, RL = 100 kΩ connected to VS / 2, VCM = VS / 2, and
VO UT = VS / 2, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
±0.6
±2.25
UNIT
OFFSET VOLTAGE
VOS
Input offset voltage
dVOS/dT
Input offset voltage
drift
PSRR
Input offset voltage
versus power supply
VS = ±0.6 V to ±2.75 V , VCM = V–
±20
Channel separation
f = 10 kHz
±5.6
TA = –40°C to 125°C
±2.5
TA = –40°C to 125°C
±0.8
mV
µV/℃
±100
µV/V
µV/V
INPUT BIAS CURRENT
IB
Input bias current (1)
IOS
Input offset current (1)
±1
±12
pA
±0.5
±10
pA
NOISE
EN
eN
iN
Input voltage noise
Input voltage noise
density
Input current noise (2)
f = 0.1 to 10 Hz
6.5
f = 100 Hz
85
f = 1 kHz
66
f = 10 kHz
64
f = 1 kHz
20
μVPP
nV/√Hz
fA/√Hz
INPUT VOLTAGE RANGE
VCM
CMRR
Common-mode
voltage range
Common-mode
rejection ratio
(V–)
(V+)
(V–) < VCM < (V+) – 0.7 V, VS = 1.2 V
60
77
(V–) < VCM < (V+) – 0.7 V, VS = 5.5 V
75
89
(V–) < VCM < (V+), VS = 1.2 V
TA = –40°C to 125°C
(V–) < VCM < (V+), VS = 5.5 V
60
57
V
dB
72
INPUT IMPEDANCE
ZID
Differential
ZICM
Common-mode
80 || 1.4
GΩ || pF
100 || 0.5
GΩ || pF
OPEN-LOOP GAIN
VS = 1.2 V, (V–) + 0.2 V < VO < (V+) – 0.2 V,
RL = 10 kΩ to VS / 2
AOL
Open-loop voltage
gain
VS = 5.5 V, (V–) + 0.2 V < VO < (V+) – 0.2 V,
RL = 10 kΩ to VS / 2
VS = 1.2 V, (V–) + 0.1 V < VO < (V+) – 0.1 V,
RL = 100 kΩ to VS / 2
98
125
TA = –40°C to 125°C
VS = 5.5 V, (V–) + 0.1 V < VO < (V+) – 0.1 V,
RL = 100 kΩ to VS / 2
dB
105
107
130
FREQUENCY RESPONSE
THD+N
Total harmonic
distortion + noise (3)
VS = 5.5 V, VCM = 2.75 V, VO = 1 VRMS, G = +1, f = 1 kHz,
RL = 100 kΩ to VS / 2
GBW
Gain-bandwidth
product
RL = 1 MΩ connected to VS/2
350
kHz
SR
Slew rate
VS = 5.5 V, G = +1, CL = 10 pF
0.2
V/μs
To 0.1%, VS = 5.5 V, VSTEP = 4 V, G = +1, CL = 10 pF
25
To 0.1%, VS = 5.5 V, VSTEP = 2 V, G = +1, CL = 10 pF
22
To 0.01%, VS = 5.5 V, VSTEP = 4 V, G = +1, CL = 10 pF
35
tS
Settling time
0.013
%
μs
To 0.01%, VS = 5.5 V, VSTEP = 2 V, G = +1, CL = 10 pF
30
Phase margin
G = +1, RL = 100 kΩ connected to VS/2, CL = 10 pF
65
°
Overload recovery
time
VIN × gain > VS
13
μs
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7.7 Electrical Characteristics (continued)
For VS = (V+) – (V–) = 1.2 V to 5.5 V (±0.6 V to ±2.75 V) at TA = 25°C, RL = 100 kΩ connected to VS / 2, VCM = VS / 2, and
VO UT = VS / 2, unless otherwise noted.
PARAMETER
EMIRR
TEST CONDITIONS
Electro-magnetic
interference rejection
ratio
MIN
f = 1 GHz, VIN_EMIRR = 100 mV
TYP
MAX
70
UNIT
dB
OUTPUT
VS = 1.2 V,
RL = 100 kΩ to VS / 2
Positive rail headroom
Voltage output swing
from rail
Negative rail headroom
ISC
Short-circuit current
ZO
Open-loop output
impedance
(4)
0.75
7
VS = 5.5 V,
RL = 10 kΩ to VS / 2
10
21
VS = 5.5 V,
RL = 100 kΩ to VS / 2
1
8
VS = 1.2 V,
RL = 100 kΩ to VS / 2
0.75
5
VS = 5.5 V,
RL = 10 kΩ to VS / 2
10
21
VS = 5.5 V,
RL = 100 kΩ to VS / 2
1
8
mV
VS = 5.5 V
±40
mA
f = 10 kHz
7500
Ω
POWER SUPPLY
IQ
Quiescent current per
amplifier
VS = 5.5 V, IO = 0 A
IQ
Quiescent current per
amplifier
VS = 5.5 V, IO = 0 A, For TLV9041UIDBVR Only
10
TA = –40°C to 125°C
13
13.5
10
TA = –40°C to 125°C
µA
13.5
µA
14
µA
200
nA
SHUTDOWN
IQSD
Quiescent current per
amplifier
All amplifiers disabled, SHDN = V–
ZSHDN
Output impedance
during shutdown
Amplifier disabled
VIH
Logic high threshold
voltage (amplifier
enabled)
VIL
Logic low threshold
voltage (amplifier
disabled)
tON
(2)
(3)
(4)
(5)
(6)
10
V
(V–) + 0.2
V
160
Amplifier enable time
(partial shutdown)
G = +1, VCM = VS / 2, VO = 0.9 × VS / 2, RL connected to V–
120
G = +1, VCM = VS / 2, VO = 0.1 × VS / 2, RL connected to V–
10
Amplifier disable time
(5)
GΩ || pF
(V–) + 1 V
G = +1, VCM = VS / 2, VO = 0.9 × VS / 2, RL connected to V–
SHDN pin input bias
current (per pin)
(1)
43 || 11.5
Amplifier enable time
(full shutdown) (5) (6)
(5) (6)
tOFF
75
V
µs
(V+) ≥ SHDN ≥ (V–) + 1 V
(V–) ≤ SHDN ≤ (V–) + 0.2 V
100
50
µs
pA
Max IB and IOS limits are specified based on characterization results. Input differential voltages greater than 2.5V can cause increased
IB
Typical input current noise data is specified based on design simulation results
Third-order filter; bandwidth = 80 kHz at –3 dB.
Short circuit current is average of sourcing and sinking short circuit currents
Disable time (tOFF) and enable time (tON) are defined as the time interval between the 50% point of the signal applied to the SHDN pin
and the point at which the output voltage reaches the 10% (disable) or 90% (enable) level.
Full shutdown refers to the dual TLV9042S having both channels 1 and 2 disabled (SHDN1 = SHDN2 = V–) and the quad TLV9044S
having all channels 1 to 4 disabled (SHDN12 = SHDN34 = V–). For partial shutdown, only one SHDN pin is exercised; in this mode,
the internal biasing circuitry remains operational and the enable time is shorter.
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SBOS836G – MARCH 2020 – REVISED MARCH 2022
7.8 Typical Characteristics
45
20
40
18
35
16
14
30
Population (%)
Population (%)
at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise
noted)
25
20
15
12
10
8
6
10
4
5
2
0
0
-2
-1.6 -1.2 -0.8 -0.4
0
0.4
0.8
1.2
1.6
2
Offset Voltage (mV)
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
2.2
Offset Voltage Drift (µV/°C)
D01_
VS = 5.5 V
D04_
VS = 5.5 V, TA = –40°C to +125°C
Figure 7-1. Offset Voltage Distribution Histogram
Figure 7-2. Offset Voltage Drift Distribution Histogram
1600
2000
1200
1600
1200
800
VOS (µV)
VOS (µV)
800
400
0
-400
400
0
-400
-800
-800
-1200
-1200
-1600
-1600
-40
-20
0
20
40
60
80
Temperature (°C)
100
120
-2000
-40
140
-20
0
VS = 5.5 V, VCM = V–
2000
1600
1600
1200
1200
800
800
400
400
VOS (µV)
VOS (µV)
100
120
140
D05_
Figure 7-4. Input Offset Voltage vs Temperature
2000
0
-400
0
-400
-800
-800
-1200
-1200
-1600
-1600
-2000
-2000
1.25
1
40
60
80
Temperature (°C)
VS = 5.5 V, VCM = V+
Figure 7-3. Input Offset Voltage vs Temperature
-3 -2.5 -2 -1.5 -1 -0.5 0 0.5
VCM (V)
20
D06_
1.5
2
2.5
3
1.5
D07_
1.75
2
2.25
VCM (V)
2.5
2.75
3
D09_
VCM > (V+) – 1.4 V
Figure 7-5. Offset Voltage vs Common-Mode
Figure 7-6. Offset Voltage vs Common-Mode
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SBOS836G – MARCH 2020 – REVISED MARCH 2022
7.8 Typical Characteristics (continued)
at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise
noted)
Input Bias Current and Offset Current (pA)
1200
800
VOS (µV)
400
0
-400
-800
-1200
1
1.5
2
2.5
3
3.5
4
4.5
Supply Voltage (V)
5
5.5
6
D51_
24
IBIB+
IOS
22
20
18
16
14
12
10
8
6
4
2
0
-40
-20
0
20
40
60
80
Temperature (°C)
100
120
140
D14_
VCM = (V–)
Figure 7-8. IB and IOS vs Temperature
1.8
150
1.2
140
0.6
130
Open-Loop Gain (dB)
Input Bias Current and Offset Current (pA)
Figure 7-7. Offset Voltage vs Supply Voltage
0
-0.6
-1.2
-1.8
-2.4
2
2.5
100
90
80
50
-40
3
80
45
60
30
40
15
20
0
0
-20
-40
Gain
Phase
-60
10k
100k
Frequency (Hz)
1M
D16_
Open-loop output impedance (ohms)
60
-15
40
60
80
Temperature (°C)
100
120
140
D18_
8000
7000
6000
5000
4000
3000
2000
1000
0
100
1k
CL = 10 pF
Figure 7-11. Open-Loop Gain and Phase vs Frequency
12
20
9000
Phase ( o )
Gain (dB)
100
1k
0
Figure 7-10. Open-Loop Gain vs Temperature
75
-45
100
-20
D13_
Figure 7-9. IB and IOS vs Common-Mode Voltage
-30
VS = 5.5 V, RL = 100K:
VS = 1.2 V, RL = 100K:
VS = 1.2 V, RL = 10K:
VS = 5.5 V, RL = 10K:
60
-3.6
-3 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5
Common-Mode Voltage (V)
110
70
IBIB+
IOS
-3
120
10k
100k
Frequency (Hz)
1M
10M
D41_
Figure 7-12. Open-Loop Output Impedance vs Frequency
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SBOS836G – MARCH 2020 – REVISED MARCH 2022
7.8 Typical Characteristics (continued)
160
150
140
130
120
110
100
90
80
-40oC
70
25oC
60
125oC
50
40
30
20
10
0
-3 -2.5 -2 -1.5 -1 -0.5 0 0.5 1
Output Voltage (V)
30
20
10
0
Gain (dB)
Open-Loop Gain (dB)
at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise
noted)
-10
-20
-30
-40
-50
G = -1
G=1
G = 10
-60
1.5
2
2.5
-70
10k
3
100k
Frequency (Hz)
D19_
V+ = 2.75 V, V– = –2.75 V
RL = 10 kΩ
1M
D17_
CL = 10 pF
Figure 7-13. Open-Loop Gain vs Output Voltage
Figure 7-14. Closed-Loop Gain vs Frequency
3
0.75
2.5
2
0.5
1.5
0.25
-40oC
25oC
85oC
125oC
0
-0.5
Vo (V)
Vo (V)
1
0.5
-1
-40oC
25oC
85oC
125oC
0
-0.25
-1.5
-2
-0.5
-2.5
-3
-0.75
0
5
10
15
20
25 30 35
Iout (mA)
40
45
50
55
60
0
0.25
0.5
V+ = 2.75 V, V– = –2.75 V
1.5
1.75
2
D34_
Figure 7-16. Output Voltage vs Output Current (Claw)
40
80
Power-Supply Rejection Ratio (µV/V)
PSRR+
PSRR-
72
64
56
PSRR (dB)
1
1.25
Iout (mA)
V+ = 0.6 V, V– = –0.6 V
Figure 7-15. Output Voltage vs Output Current (Claw)
48
40
32
24
16
8
0
100
0.75
D32_
1k
10k
100k
Frequency (Hz)
36
32
28
24
20
16
12
8
4
0
-40
1M
-20
0
D10_
20
40
60
80
Temperature (°C)
100
120
140
D11_
VS = 1.2 V to 5.5 V
Figure 7-17. PSRR vs Frequency
Figure 7-18. DC PSRR vs Temperature
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SBOS836G – MARCH 2020 – REVISED MARCH 2022
7.8 Typical Characteristics (continued)
at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise
noted)
95
100
Common-Mode Rejection Ratio (dB)
CMRR
90
80
CMRR (dB)
70
60
50
40
30
20
10
0
100
1k
10k
100k
Frequency (Hz)
1M
90
85
80
75
VS = 5.5 V;VCM = 0 V to 4.7 V
VS = 3.3 V;VCM = 0 V to 2.6 V
VS = 1.8 V;VCM = 0 V to 1.1 V
VS = 1.2 V;VCM = 0 V to 0.5 V
70
65
-40
10M
-20
Figure 7-19. CMRR vs Frequency
20
Voltage noise spectral density (nV/rtHz)
2
1
0
-1
-2
-3
120
140
D12_
180
160
140
120
100
80
60
40
20
0
10
-4
Time (1s/div)
100
D011
10k
D15_
0
0
-10
1k
Frequency (Hz)
Figure 7-22. Input Voltage Noise Spectral Density
Figure 7-21. 0.1 Hz to 10 Hz Voltage Noise in Time Domain
RL = 10 k:
RL = 100 k:
-10
-20
-20
-30
-30
-40
-40
THD+N (dB)
THD+N (dB)
100
200
3
-50
-60
-70
RL = 10 k:
RL = 100 k:
-50
-60
-70
-80
-80
-90
-90
-100
-100
-110
-110
100
VS = 5.5 V
BW = 80 kHz
1k
Frequency (Hz)
100
10k
D30_
VCM = 2.5 V
VOUT = 0.5 VRMS
Figure 7-23. THD + N vs Frequency
14
40
60
80
Temperature (°C)
Figure 7-20. DC CMRR vs Temperature
4
Amplitude (1 uV/div)
0
D010
G=1
VS = 5.5 V
BW = 80 kHz
1k
Frequency (Hz)
VCM = 2.5 V
VOUT = 0.5 VRMS
10k
D30_
G = –1
Figure 7-24. THD + N vs Frequency
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SBOS836G – MARCH 2020 – REVISED MARCH 2022
7.8 Typical Characteristics (continued)
at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise
noted)
0
0
RL = 10 k:
RL = 100 k:
-20
-20
-30
-30
-40
-50
-40
-50
-60
-60
-70
-70
-80
-80
-90
1m
10m
VS = 5.5 V
G=1
100m
Amplitude(Vrms)
RL = 10 k:
RL = 100 k:
-10
THD+N (dB)
THD+N (dB)
-10
-90
1m
1
VCM = 2.5 V
BW = 80 kHz
f = 1 kHz
VS = 5.5 V
G = –1
Figure 7-25. THD + N vs Amplitude
11
11
10.5
10.5
1
D31_
VCM = 2.5 V
BW = 80 kHz
f = 1 kHz
VS = 5.5 V
VS = 1.2 V
10
Quiescent Current (µA)
Quiescent Current (µA)
100m
Amplitude(Vrms)
Figure 7-26. THD + N vs Amplitude
10
9.5
9
8.5
8
7.5
7
9.5
9
8.5
8
7.5
7
6.5
6.5
6
1
1.5
2
2.5
3
3.5
4
4.5
Supply Voltage (V)
5
5.5
6
-40
6
-20
0
D38_
Figure 7-27. Quiescent Current vs Supply Voltage
20
40
60
80
Temperature (°C)
100
120
140
D40_
Figure 7-28. Quiescent Current vs Temperature
70
70
RISO = 0: , Overshoot (+)
RISO = 0: ,Overshoot (-)
RISO = 50: , Overshoot (+)
RISO = 50: ,Overshoot (-)
60
RISO = 0: , Overshoot (+)
RISO = 0: ,Overshoot (-)
RISO = 50: , Overshoot (+)
RISO = 50: ,Overshoot (-)
60
50
Overshoot (%)
50
Overshoot (%)
10m
D31_
40
30
40
30
20
20
10
10
0
0
0
80
G=1
160
240
320
400
Capacitive Load (pF)
480
560
0
80
160
D23_
VIN = 100 mVpp
Figure 7-29. Small Signal Overshoot vs Capacitive Load
G = –1
240
320
400
Capacitive Load (pF)
480
560
D24_
VIN = 100 mVpp
Figure 7-30. Small Signal Overshoot vs Capacitive Load
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7.8 Typical Characteristics (continued)
72
3
68
2.4
64
1.8
VIN
VOUT
1.2
60
Amplitude (V)
Phase Margin (°)
at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise
noted)
56
52
48
0.6
0
-0.6
-1.2
44
-1.8
40
-2.4
36
10
-3
30
50
70
90
110
Capacitive Load (pF)
130
150
Time (25 µs/div)
D005
D21_
G=1
Figure 7-31. Phase Margin vs Capacitive Load
VIN = 6 VPP
Figure 7-32. No Phase Reversal
12.5
3
VIN
VOUT
10
7.5
1
0
-1
-2
5
Amplitude (mV)
Amplitude (V)
2
2.5
0
-2.5
-5
-7.5
VIN
VOUT
-10
-3
-12.5
Time (100 µs/div)
Time (10 µs/div)
D22_
G = –10
D25_
VIN = 600 mVPP
G=1
Figure 7-33. Overload Recovery
VIN
VOUT
1.5
Amplitude (V)
1
0.5
0
-0.5
-1
-1.5
-2
-2.5
Time (5 µs/div)
Time (10 µs/div)
D29_
D27_
G=1
VIN = 4 VPP
CL = 10 pF
Figure 7-35. Large-Signal Step Response
16
CL = 10 pF
Output Delta from Final Value (10 mV/div)
2.5
2
VIN = 20 mVPP
Figure 7-34. Small-Signal Step Response
G=1
VIN = 4 VPP
CL = 10 pF
Figure 7-36. Large-Signal Settling Time (Negative)
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7.8 Typical Characteristics (continued)
at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise
noted)
Output Delta from Final Value (10 mV/div)
2.5
2
1.5
VIN
VOUT
Amplitude (V)
1
0.5
0
-0.5
-1
-1.5
-2
-2.5
Time (10 µs/div)
Time (5 µs/div)
D28_
D29_
G=1
VIN = 4 VPP
G = –1
CL = 10 pF
80
6
Vs = 5.5 V
Vs = 1.2 V
5.4
Sinking
Sourcing
60
4.8
40
4.2
20
3.6
Isc (mA)
Maximum Output Voltage (V)
CL = 10 pF
Figure 7-38. Large-Signal Step Response
Figure 7-37. Large-Signal Settling Time (Positive)
3
2.4
0
-20
1.8
-40
1.2
-60
0.6
-80
-40
0
1
10
100
1k
10k
100k
Frequency (Hz)
1M
10M
100M
-20
0
20
D36_
Figure 7-39. Maximum Output Voltage vs Frequency
40
60
80
Temperature (°C)
100
120
140
D37_
Figure 7-40. Short-Circuit Current vs Temperature
140
100
SHDN Quiescent Current (nA)
90
SHDN Quiescent Current (nA)
VIN = 4 VPP
80
70
60
50
40
30
20
10
0
1
1.5
2
2.5
3
3.5
4
4.5
Supply Voltage (V)
5
5.5
6
120
Vs = 5.5 V
Vs = 1.2 V
100
80
60
40
20
0
-40
-20
0
D44_
Figure 7-41. Shutdown Mode Quiescent Current vs Supply
Voltage
20
40
60
80
Temperature (°C)
100
120
140
D45_
Figure 7-42. Shutdown Mode Quiescent Current vs Temperature
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7.8 Typical Characteristics (continued)
at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise
noted)
1
1
VOUT (V)
SHDN (V)
0.5
0
Amplitude (V)
0
Amplitude (V)
VOUT (V)
SHDN (V)
0.5
-0.5
-1
-1.5
-0.5
-1
-1.5
-2
-2
-2.5
-2.5
-3
-3
Time (20 µs/div)
Time (20 µs/div)
D49_
D48_
Figure 7-43. Amplifier Enable Response
Figure 7-44. Amplifier Disable Response
100
0
90
-20
80
-40
Crosstalk (dB)
EMIRR (dB)
70
60
50
40
30
-60
-80
-100
20
-120
10
0
1M
10M
100M
Frequency (Hz)
-140
100
1G
Figure 7-45. Electromagnetic Interference Rejection Ratio
Referred to Noninverting Input (EMIRR+) vs Frequency
18
1k
D42_
10k
100k
Frequency (Hz)
1M
10M
D50_
Figure 7-46. Channel Separation
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8 Detailed Description
8.1 Overview
The TLV904x is a family of low-power, rail-to-rail input and output operational amplifiers specifically designed
for battery powered applications. This family of amplifiers utilizes unique transistors that enable operation from
ultra low supply voltage of 1.2 V to a standard supply voltage of 5.5 V. These unity-gain stable amplifiers provide
350 kHz of GBW with an IQ of only 10 µA. TLV904x also has short circuit current capability of 40 mA at 5.5
V. This combination of low voltage, low IQ, and high output current capability makes this device quite unique
and suitable for suitable for a wide range of general-purpose applications. The input common-mode voltage
range includes both rails, and allows the TLV904x series to be used in many single-supply or dual supply
configurations. Rail-to-rail input and output swing significantly increases dynamic range, especially in low-supply
applications, and makes these devices ideal for driving low speed sampling analog-to-digital converters (ADCs).
Further, the class AB output stage is capable of driving resitive loads greater than 2-kΩ connected to any point
between V+ and ground.
The TLV904x can drive up to 100 pF with a typical phase margin of 45° and features 350-kHz gain bandwidth
product, 0.2-V/μs slew rate with 6.5-μVp-p integrated noise (0.1 to 10 Hz) while consuming only 10-μA supply
current per channel, thus providing a good AC performance at a very low power consumption. DC applications
are also well served with a low input bias current of 1 pA (typical), an input offset voltage of 0.6 mV (typical) and
a good PSRR, CMRR, and AOL.
8.2 Functional Block Diagram
V+
Reference
Current
VIN+
VINVBIAS1
Class AB
Control
Circuitry
VO
VBIAS2
V(Ground)
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8.3 Feature Description
8.3.1 Operating Voltage
The TLV904x series of operational amplifiers is fully specified and ensured for operation from 1.2 V to 5.5 V.
In addition, many specifications apply from –40°C to 125°C. Parameters that vary significantly with operating
voltages or temperature are provided in Section 7.8. It is highly recommended to bypass power-supply pins with
at least 0.01-μF ceramic capacitors.
8.3.2 Rail-to-Rail Input
The input common-mode voltage range of the TLV904x series extends to either supply rails. This is true even
when operating at the ultra-low supply voltage of 1.2 V, all the way up to the standard supply voltage of 5.5 V.
This performance is achieved with a complementary input stage: an N-channel input differential pair in parallel
with a P-channel differential pair. Refer to Section 8.2 for more details.
For most amplifiers with a complementary input stage, one of the input pairs, usually the P-channel input pair,
is designed to deliver slightly better performance in terms of input offset voltage, offset drift over the N-channel
pair. Consequently, the P-channel pair is designed to cover the majority of the common mode range with the
N-channel pair slated to slowly take over at a certain threshold voltage from the positive rail. Just after the
threshold voltage, both the input pairs are in operation for a small range referred to as the transition region.
Beyond this region, the N-channel pair completely takes over. Within the transition region, PSRR, CMRR, offset
voltage, offset drift, and THD can be degraded compared to device operation outside this region. Hence, most
applications generally prefer operating in the P-channel input range where the performance is slightly better.
For the TLV904x, the P-channel pair is typically active for input voltages from the negative rail to (V+) – 0.4
V and the N-channel pair is typically active for input voltages from the positive supply to (V+) – 0.4 V. The
transition region occurs typically from (V+) – 0.5 V to (V+) – 0.3 V, in which both pairs are on. These voltage
levels mentioned above can vary with process variations associated with threshold voltage of transistors. In
the TLV904x, 200-mV transition region mentioned above can vary up to 200 mV in either direction. Thus, the
transition region (both stages on) can range from (V+) – 0.7 V to (V+) – 0.5 V on the low end, up to (V+) – 0.3 V
to (V+) – 0.1 V on the high end.
Recollecting the fact that a P-channel input pair usually offers better performance over a N-channel input pair,
the TLV904x is designed to offer a much wider P-channel input pair range, in comparison to most complimentary
input amplifiers in the industry. A side by side comparison of the TLV904x and the TLV900x is provided below.
Note, that the TLV900x guarantees P-channel pair operation only until 1.4 V from the positive rail while the
TLV904x guarantees P-channel pair operation all the way till 0.7 V from the positive rail. This additional 700mV
of P-channel input pair range for the TLV904x is particularly useful when operating at lower supply voltages (1.2
V, 1.8 V etc) where the P-channel input range usually gets limited to a great extent.
Thus the wide common mode swing of input signal can be accommodated more easily within the P-channel
input pair of the TLV904x, while likely avoiding the transition region, thereby maintaining linearity.
20
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2000
2000
1600
1500
1200
1000
Offset Voltage (μV)
VOS (µV)
800
400
0
-400
-800
500
0
-500
-1000
-1200
-1500
-1600
-2000
-3 -2.5 -2 -1.5 -1 -0.5 0 0.5
VCM (V)
1
1.5
2
2.5
3
-2000
-4
-3
-2
D07_
V+ = 2.75 V, V– = –2.75 V
Figure 8-1. TLV904x Offset Voltage vs CommonMode
-1
0
1
2
Common-Mode Voltage (V)
3
4
D004
V+ = 2.75 V, V– = –2.75 V
Figure 8-2. TLV900x Offset Voltage vs CommonMode
8.3.3 Rail-to-Rail Output
Designed as a micro-power, low-noise operational amplifier, the TLV904x delivers a robust output drive
capability. A class AB output stage with common-source transistors is used to achieve full rail-to-rail output
swing capability. For resistive loads up to 5 kΩ, the output typically swings to within 20 mV of either supply rail
regardless of the power-supply voltage applied. Different load conditions change the ability of the amplifier to
swing close to the rails.
8.3.4 Common-Mode Rejection Ratio (CMRR)
The CMRR for the TLV904x is specified in several ways so the best match for a given application can be used;
see the Electrical Characteristics table. First, the CMRR of the device in the common-mode range below the
transition region [VCM < (V+) – 0.7 V] is given. This specification is the best indicator of the capability of the
device when the application requires using one of the differential input pairs. Second, the CMRR over the entire
common-mode range is specified at (VCM = 0 V to 5.5 V). This last value includes the variations measured
through the transition region.
8.3.5 Capacitive Load and Stability
The TLV904x is designed to be used in applications where driving a capacitive load is required. As with all
operational amplifiers, there may be specific instances where the TLV904x can become unstable. The particular
operational amplifier circuit configuration, layout, gain, and output loading are some of the factors to consider
when establishing whether or not an amplifier is stable in operation. An operational amplifier in the unity-gain
(1 V/V) buffer configuration that drives a capacitive load exhibits a greater tendency to be unstable than an
amplifier operated at a higher noise gain. The capacitive load, in conjunction with the operational amplifier output
resistance, creates a pole within the feedback loop that degrades the phase margin. The degradation of the
phase margin increases when capacitive loading increases. When operating in the unity-gain configuration, the
TLV904x remains stable with a pure capacitive load up to approximately 100 pF with a good phase margin of 45°
typical. The equivalent series resistance (ESR) of some very large capacitors (CL greater than 1 μF) is sufficient
to alter the phase characteristics in the feedback loop such that the amplifier remains stable. Increasing the
amplifier closed-loop gain allows the amplifier to drive increasingly larger capacitance. This increased capability
is evident when measuring the overshoot response of the amplifier at higher voltage gains.
One technique for increasing the capacitive load drive capability of the amplifier operating in a unity-gain
configuration is to insert a small resistor (typically 10 Ω to 20 Ω) in series with the output, as shown in Figure 8-3.
This resistor significantly reduces the overshoot and ringing associated with large capacitive loads. One possible
problem with this technique, however, is that a voltage divider is created with the added series resistor and any
resistor connected in parallel with the capacitive load. The voltage divider introduces a gain error at the output
that reduces the output swing.
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+Vs
Vout
Riso
+
Vin
Cload
+
±
-Vs
Figure 8-3. Improving Capacitive Load Drive
8.3.6 Overload Recovery
Overload recovery is defined as the time required for the operational amplifier output to recover from a saturated
state to a linear state. The output devices of the operational amplifier enter a saturation region when the
output voltage exceeds the rated operating voltage, because of the high input voltage or high gain. Once one
of the output devices enters the saturation region, the output stage requires additional time to return to the
linear operating state which is referred to as overload recovery time. After the output stage returns to its linear
operating state, the amplifier begins to slew at the specified slew rate. Therefore, the propagation delay (in case
of an overload condition) is the sum of the overload recovery time and the slew time. The overload recovery time
for the TLV904x family is approximately 13-µs typical.
8.3.7 EMI Rejection
The TLV904x uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI from
sources such as wireless communications and densely-populated boards with a mix of analog signal chain and
digital components. EMI immunity can be improved with circuit design techniques; the TLV904x benefits from
these design improvements. Texas Instruments has developed the ability to accurately measure and quantify the
immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz. Figure
8-4 shows the results of this testing on the TLV904x. Table 8-1 shows the EMIRR IN+ values for the TLV904x at
particular frequencies commonly encountered in real-world applications. The EMI Rejection Ratio of Operational
Amplifiers application report contains detailed information on the topic of EMIRR performance as it relates to op
amps and is available for download from www.ti.com.
100
90
80
EMIRR (dB)
70
60
50
40
30
20
10
0
1M
10M
100M
Frequency (Hz)
1G
D42_
Figure 8-4. EMIRR Testing
Table 8-1. TLV904x EMIRR IN+ for Frequencies of Interest
FREQUENCY
22
APPLICATION OR ALLOCATION
EMIRR IN+
400 MHz
Mobile radio, mobile satellite, space operation, weather, radar, ultra-high frequency (UHF)
applications
60 dB
900 MHz
Global system for mobile communications (GSM) applications, radio communication, navigation,
GPS (to 1.6 GHz), GSM, aeronautical mobile, UHF applications
70 dB
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Table 8-1. TLV904x EMIRR IN+ for Frequencies of Interest (continued)
FREQUENCY
APPLICATION OR ALLOCATION
EMIRR IN+
1.8 GHz
GSM applications, mobile personal communications, broadband, satellite, L-band (1 GHz to 2 GHz)
75 dB
Bluetooth®,
2.4 GHz
802.11b, 802.11g, 802.11n,
mobile personal communications, industrial, scientific and
medical (ISM) radio band, amateur radio and satellite, S-band (2 GHz to 4 GHz)
3.6 GHz
Radiolocation, aero communication and navigation, satellite, mobile, S-band
82 dB
802.11a, 802.11n, aero communication and navigation, mobile communication, space and satellite
operation, C-band (4 GHz to 8 GHz)
85 dB
5 GHz
79.0 dB
8.3.8 Electrical Overstress
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress.
These questions tend to focus on the device inputs, but can involve the supply voltage pins or even the output
pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown
characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.
Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from
accidental ESD events both before and during product assembly.
Having a good understanding of this basic ESD circuitry and its relevance to an electrical overstress event
is helpful. Figure 8-5 shows the ESD circuits contained in the TLV904x devices. The ESD protection circuitry
involves several current-steering diodes connected from the input and output pins and routed back to the internal
power supply lines, where they meet at an absorption device internal to the operational amplifier. This protection
circuitry is intended to remain inactive during normal circuit operation.
V+
Power Supply
ESD Cell
+IN
+
±
± IN
OUT
V±
Figure 8-5. Equivalent Internal ESD Circuitry
8.3.9 Input and ESD Protection
The TLV904x family incorporates internal ESD protection circuits on all pins. For input and output pins, this
protection primarily consists of current-steering diodes connected between the input and power-supply pins.
These ESD protection diodes provide in-circuit, input overdrive protection, as long as the current is limited to
10 mA. Figure 8-6 shows how a series input resistor can be added to the driven input to limit the input current.
The added resistor contributes thermal noise at the amplifier input and the value must be kept to a minimum in
noise-sensitive applications.
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V+
IOVERLOAD
10-mA maximum
Device
VOUT
VIN
5 kW
Figure 8-6. Input Current Protection
8.3.10 Shutdown Function
The TLV904xS devices feature SHDN pins that disable the op amp, placing it into a low-power standby mode.
In this mode, the op amp typically consumes less than 150 nA. The SHDN pins are active low, meaning that
shutdown mode is enabled when the input to the SHDN pin is a valid logic low.
The SHDN pins are referenced to the negative supply voltage of the op amp. The threshold of the shutdown
feature lies around 500 mV (typical) and does not change with respect to the supply voltage. Hysteresis has
been included in the switching threshold to ensure smooth switching characteristics. To ensure optimal shutdown
behavior, the SHDN pins should be driven with valid logic signals. A valid logic low is defined as a voltage
between V– and V– + 0.2 V. A valid logic high is defined as a voltage between V– + 1 V and V+. To enable the
amplifier, the SHDN pins must be driven to a valid logic high. To disable the amplifier, the SHDN pins must be
driven to a valid logic low. We highly recommend that the shutdown pin be connected to a valid high or a low
voltage or driven. The maximum voltage allowed at the SHDN pins is (V+) + 0.5 V. Exceeding this voltage level
will damage the device.
The SHDN pins are high-impedance CMOS inputs. Dual op amp versions are independently controlled and
quad op amp versions are controlled in pairs with logic inputs. For battery-operated applications, this feature
may be used to greatly reduce the average current and extend battery life. The enable time is 160 µs for
full shutdown of all channels; disable time is 10 µs. When disabled, the output assumes a high-impedance
state. This architecture allows the TLV904xS to be operated as a gated amplifier (or to have the device output
multiplexed onto a common analog output bus). Shutdown time (tOFF) depends on loading conditions and
increases as load resistance increases. To ensure shutdown (disable) within a specific shutdown time, the
specified 100-kΩ load to midsupply (VS / 2) is required. If using the TLV904xS without a load, the resulting turnoff
time is significantly increased.
8.3.11 Packages With an Exposed Thermal Pad
The TLV904x family is available in packages such as the WQFN-16 (RTE) which feature an exposed thermal
pad. Inside the package, the die is attached to this thermal pad using an electrically conductive compound. For
this reason, when using a package with an exposed thermal pad, the thermal pad must either be connected to
V– or left floating. Attaching the thermal pad to a potential other then V– is not allowed, and the performance of
the device is not assured when doing so.
8.4 Device Functional Modes
The TLV904x devices have a single functional mode. These devices are powered on as long as the powersupply voltage is between 1.2 V (±0.6 V) and 5.5 V (±2.75 V).
The TLV904xS devices feature a shutdown pin, which can be used to place the op amp into a low-power mode.
See Section 8.3.10 for more information.
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The TLV904x family of low-power, rail-to-rail input and output operational amplifiers is specifically designed for
portable applications. The devices operate from 1.2 V to 5.5 V, are unity-gain stable, and are suitable for a wide
range of general-purpose applications. The class AB output stage is capable of driving resitive loads greater
than 2-kΩ connected to any point between V+ and V–. The input common-mode voltage range includes both
rails and allows the TLV904x series to be used in many single-supply or dual supply configurations.
9.2 Typical Application
9.2.1 TLV904x Low-Side, Current Sensing Application
Figure 9-1 shows the TLV904x configured in a low-side current sensing application.
VBUS
ILOAD
ZLOAD
5V
+
Device
RSHUNT
0.1 Ÿ
VSHUNT
í
VOUT
í
+
RF
57.6 NŸ
RG
1.2 NŸ
Figure 9-1. TLV904x in a Low-Side, Current-Sensing Application
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9.2.1.1 Design Requirements
The design requirements for this design are:
• Load current: 0 A to 1 A
• Maximum output voltage: 4.9 V
• Maximum shunt voltage: 100 mV
9.2.1.2 Detailed Design Procedure
The transfer function of the circuit in Figure 9-1 is given in Equation 1.
VOUT
ILOAD u RSHUNT u Gain
(1)
The load current (ILOAD) produces a voltage drop across the shunt resistor (RSHUNT). The load current is set
from 0 A to 1 A. To keep the shunt voltage below 100 mV at maximum load current, the largest shunt resistor is
shown using Equation 2.
RSHUNT
VSHUNT _ MAX
ILOAD _ MAX
100mV
1A
100m:
(2)
Using Equation 2, RSHUNT is calculated to be 100 mΩ. The voltage drop produced by ILOAD and RSHUNT is
amplified by the TLV904x to produce an output voltage of approximately 0 V to 4.9 V. The gain needed by the
TLV904x to produce the necessary output voltage is calculated using Equation 3.
Gain
VOUT _ MAX
VIN _ MAX
VOUT _ MIN
VIN _ MIN
(3)
Using Equation 3, the required gain is calculated to be 49 V/V, which is set with resistors RF and RG. Equation 4
sizes the resistors RF and RG, to set the gain of the TLV904x to 49 V/V.
Gain 1
RF
RG
(4)
Selecting RF as 57.6 kΩ and RG as 1.2 kΩ provides a combination that equals 49 V/V. Figure 9-2 shows the
measured transfer function of the circuit shown in Figure 9-1. Notice that the gain is only a function of the
feedback and gain resistors. This gain is adjusted by varying the ratio of the resistors and the actual resistors
values are determined by the impedance levels that the designer wants to establish. The impedance level
determines the current drain, the effect that stray capacitance has, and a few other behaviors. There is no
optimal impedance selection that works for every system; you must choose an impedance that is ideal for your
system parameters.
26
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9.2.1.3 Application Curve
5
Output (V)
4
3
2
1
0
0
0.2
0.4
0.6
0.8
ILOAD (A)
1
C219
Figure 9-2. Low-Side, Current-Sense Transfer Function
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10 Power Supply Recommendations
The TLV904x family is specified for operation from 1.2 V to 5.5 V (±0.6 V to ±2.75 V); many specifications
apply from –40°C to 125°C. Section 7.7 presents parameters that may exhibit significant variance with regard to
operating voltage or temperature.
CAUTION
Supply voltages larger than 6 V may permanently damage the device; see the Absolute Maximum
Ratings table.
Place 0.1-µF bypass capacitors close to the power-supply pins to reduce coupling errors from noisy or highimpedance power supplies. For more detailed information on bypass capacitor placement, see Section 11.1.
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11 Layout
11.1 Layout Guidelines
For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:
•
•
•
•
•
•
•
•
Noise can propagate into analog circuitry through the power connections of the board and propagate to the
power pins of the op amp itself. Bypass capacitors are used to reduce the coupled noise by providing a
low-impedance path to ground.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is adequate for single-supply
applications.
Separate grounding for analog and digital portions of circuitry is one of the simplest and most effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise pickup. Take care
to physically separate digital and analog grounds, paying attention to the flow of the ground current.
To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible.
If these traces cannot be kept separate, crossing the sensitive trace at a 90 degree angle is much better as
opposed to running the traces in parallel with the noisy trace.
Place the external components as close to the device as possible, as shown in Figure 11-2. Keeping RF and
RG close to the inverting input minimizes parasitic capacitance.
Keep the length of input traces as short as possible. Remember that the input traces are the most sensitive
part of the circuit.
Consider a driven, low-impedance guard ring around the critical traces. A guard ring may significantly reduce
leakage currents from nearby traces that are at different potentials.
Cleaning the PCB following board assembly is recommended for best performance.
Any precision integrated circuit can experience performance shifts resulting from moisture ingress into the
plastic package. Following any aqueous PCB cleaning process, baking the PCB assembly is recommended
to remove moisture introduced into the device packaging during the cleaning process. A low-temperature,
post-cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
11.2 Layout Example
+
VIN 1
+
VIN 2
VOUT 1
RG
VOUT 2
RG
RF
RF
Figure 11-1. Schematic Representation
Place components
close to device and to
each other to reduce
parasitic errors .
OUT 1
VS+
OUT1
Use low-ESR,
ceramic bypass
capacitor . Place as
close to the device
as possible .
GND
V+
RF
OUT 2
GND
IN1 ±
OUT2
IN1 +
IN2 ±
RF
RG
VIN 1
GND
RG
V±
Use low-ESR,
ceramic bypass
capacitor . Place as
close to the device
as possible .
GND
VS±
IN2 +
Ground (GND) plane on another layer
VIN 2
Keep input traces short
and run the input traces
as far away from
the supply lines
as possible .
Figure 11-2. Layout Example
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OUTPUT A
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GND
GND
GND
V+
INPUT A
INPUT B
OUTPUT B
VGND
GND
GND
GND
V+
GND
OUT A
Figure 11-3. Example Layout for VSSOP-8 (DGK) Package
GND
OUT B
- +
+ -
+IN A
V-
+IN B
GND
GND
GND
Figure 11-4. Example Layout for WSON-8 (DSG) Package
30
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• EMI rejection ratio of operational amplifiers
• QFN/SON PCB attachment
• Quad flatpack no-lead logic packages
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
Trademarks
TI E2E™ is a trademark of Texas Instruments.
Bluetooth® is a registered trademark of Bluetooth SIG, Inc.
All trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
7-Feb-2023
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TLV9041IDBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
T041
Samples
TLV9041IDCKR
ACTIVE
SC70
DCK
5
3000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
1IV
Samples
TLV9041IDPWR
ACTIVE
X2SON
DPW
5
3000
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
(L, LE)
Samples
TLV9041SIDBVR
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
T41S
Samples
TLV9041UIDBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
U041
Samples
TLV9042IDDFR
ACTIVE
SOT-23-THIN
DDF
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
T042
Samples
TLV9042IDGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
2H7T
Samples
TLV9042IDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
T9042D
Samples
TLV9042IDSGR
ACTIVE
WSON
DSG
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
T42G
Samples
TLV9042IPWR
ACTIVE
TSSOP
PW
8
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
T9042P
Samples
TLV9042SIRUGR
ACTIVE
X2QFN
RUG
10
3000
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
HTF
Samples
TLV9044IDR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TLV9044D
Samples
TLV9044IDYYR
ACTIVE
SOT-23-THIN
DYY
14
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TL944DYY
Samples
TLV9044IPWR
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
T9044PW
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
7-Feb-2023
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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