TLV9051, TLV9052, TLV9054
ZHCSI62I – AUGUST 2018 – REVISED NOVEMBER 2022
TLV9051/TLV9052/TLV9054 5MHz 15V/µs 高压摆率 RRIO 运算放大器
器件信息(1)
1 特性
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高压摆率：15V/µs
低静态电流：330µA
轨至轨输入和输出
低输入失调电压：±0.33 mV
单位增益带宽：5MHz
低宽带噪声：15 nV/√Hz
低输入偏置电流：2pA
单位增益稳定
内置 RFI 和 EMI 滤波器
适用于低成本应用的可扩展 CMOS 运算放大器系列
可在电源电压低至 1.8V 的情况下运行
工作温度范围：–40°C 至 125°C
2 应用
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HVAC：暖通空调
光电二极管放大器
用于实现直流电机控制的电流分流监控
白色家电（冰箱、洗衣机等）
传感器信号调节
有源滤波器
低侧电流检测
3 说明
器件型号
TLV9051
TLV9051S
TLV9052
TLV9052S
TLV9054
TLV9054S
(1)
(2)
1.60mm × 2.90mm
SC70 (5)
1.25mm × 2.00mm
SOT553 (5)(2)
1.65mm × 1.20mm
X2SON (5)
0.80mm × 0.80mm
SOT-23 (6)
1.60mm × 2.90mm
SOIC (8)
3.91mm × 4.90mm
TSSOP (8)
3.00mm × 4.40mm
VSSOP (8)
3.00mm × 3.00mm
SOT-23 (8)
1.60mm × 2.90mm
WSON (8)
2.00mm × 2.00mm
VSSOP (10)
3.00mm × 3.00mm
X2QFN (10)
1.50mm x 2.00mm
SOIC (14)
8.65mm × 3.91mm
TSSOP (14)
4.40mm × 5.00mm
X2QFN (14)
2.00mm × 2.00mm
WQFN (16)
3.00mm × 3.00mm
WQFN (16)
3.00mm × 3.00mm
如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
封装仅为预发布版。
RG
TLV9051、TLV9052 和 TLV9054 器件分别为单通道、
双通道和四通道的运算放大器。这些器件旨在 1.8V 至
6.0V 的低电压下运行。它们可以在非常高的压摆率下
实现轨到轨输入和输出。这些器件非常适合需要低工作
电压、高压摆率和低静态电流的成本受限应用。
TLV905x 系列的容性负载驱动器具有 150pF 的电容，
而电阻式开环输出阻抗使其能够在更高的容性负载下更
轻松地实现稳定。
RF
R1
VOUT
VIN
C1
f-3 dB =
(
RF
VOUT
= 1+
RG
VIN
((
1
1 + sR1C1
1
2pR1C1
(
单极低通滤波器
TLV905xS 器件具有关断模式，允许放大器切换至典型
电流消耗低于 1µA 的待机模式。
17
16.5
16
Slew Rate (V/Ps)
TLV905x 系列易于使用，因为它具有稳定的单位增
益，集成了 RFI 和 EMI 滤波器，且不会在过驱动情况
下出现相位反转。
封装尺寸（标称值）
封装
SOT-23 (5)
15.5
15
14.5
14
13.5
13
50
100
150
200
250
Capacitive Load (pF)
300
350
D019
压摆率与负载电容间的关系
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBOS942
TLV9051, TLV9052, TLV9054
www.ti.com.cn
ZHCSI62I – AUGUST 2018 – REVISED NOVEMBER 2022
Table of Contents
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................4
6 Pin Configuration and Functions...................................5
7 Specifications................................................................ 11
7.1 绝对最大额定值......................................................... 11
7.2 ESD Ratings..............................................................11
7.3 Recommended Operating Conditions....................... 11
7.4 Thermal Information for Single Channel................... 11
7.5 Thermal Information for Dual Channel......................12
7.6 Thermal Information for Quad Channel.................... 12
7.7 电气特性：VS（总电源电压）= (V+) – (V-) =
1.8V 至 5.5V................................................................ 13
7.8 Typical Characteristics.............................................. 15
8 Detailed Description......................................................22
8.1 Overview................................................................... 22
8.2 Functional Block Diagram......................................... 22
8.3 Feature Description...................................................23
8.4 Device Functional Modes..........................................26
9 Application and Implementation.................................. 27
9.1 Application Information............................................. 27
9.2 Typical Low-Side Current Sense Application............ 27
9.3 Power Supply Recommendations.............................29
9.4 Layout....................................................................... 29
10 Device and Documentation Support..........................31
10.1 Documentation Support.......................................... 31
10.2 Related Links.......................................................... 31
10.3 Receiving Notification of Documentation Updates..31
10.4 支持资源..................................................................31
10.5 Trademarks............................................................. 31
10.6 Electrostatic Discharge Caution..............................31
10.7 术语表..................................................................... 31
11 Mechanical, Packaging, and Orderable
Information.................................................................... 32
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision H (October 2019) to Revision I (November 2022)
Page
• 将绝对最大额定值 中的最大电源电压从 6V 更改为 7V..................................................................................... 11
• 添加了输入偏置电流和输入失调电流的最大值..................................................................................................13
Changes from Revision G (September 2019) to Revision H (October 2019)
Page
• Added new human-body model and charged-device model ratings for TLV9051 X2SON package to the ESD
Ratings .............................................................................................................................................................11
• Added Packages With an Exposed Thermal Pad section to Feature Description section................................24
Changes from Revision F (June 2019) to Revision G (September 2019)
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Changes from Revision E (May 2019) to Revision F (June 2019)
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删除了所有 TLV9051 封装的预发布标记.............................................................................................................1
删除了 TLV9052 SOT-23 (8) - DDF 封装的预发布标记.......................................................................................1
Added link to Shutdown Function section in all of the SHDN pin function rows................................................. 5
Added EMI Rejection section to Feature Description section...........................................................................23
Added clarification to the Shutdown Function section...................................................................................... 25
Page
删除了器件信息 中 TLV9052S 器件的封装预发布标记....................................................................................... 1
Deleted package preview notation for TLV9052S devices under Device Comparison Table ............................ 4
Deleted preview notation for TLV9052S devices in Device Comparison Table ................................................. 4
Deleted package preview notation for TLV9052S in Pin Configuration and Functions section.......................... 5
Deleted package preview notation for TLV9052S under Thermal Information for Dual Channel .................... 12
Changes from Revision D (April 2019) to Revision E (May 2019)
Page
• Added DDF (SOT-23) information to Thermal Information for Dual Channel table.......................................... 12
Changes from Revision C (April 2019) to Revision D (April 2019)
Page
• 删除了器件信息 中 TLV9054/S 器件的预发布标记..............................................................................................1
2
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ZHCSI62I – AUGUST 2018 – REVISED NOVEMBER 2022
Deleted preview notations for TLV9054 devices in Device Comparison Table ..................................................4
Deleted preview notations for TLV9054S device in Device Comparison Table ................................................. 4
Deleted preview notations for TLV9054 packages in Pin Configurations and Functions section....................... 5
Deleted preview notation for TLV9054S RTE package in Pin Configurations and Functions section................ 5
Deleted preview notation for TLV9054/S packages in Thermal Information for Quad Channel ...................... 12
Changes from Revision B (March 2019) to Revision C (April 2019)
Page
• Added TLV9051 thermal information for DPW, DBV, and DCK packages........................................................ 11
Changes from Revision A (December 2018) to Revision B (March 2019)
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向说明 部分添加了关断器件说明........................................................................................................................ 1
向器件信息 中添加了 SOT-23 (8) 封装............................................................................................................... 1
向器件信息 中添加了关断器件............................................................................................................................ 1
向 TLV9054 器件信息 中添加了 X2QFN (RUC) 封装..........................................................................................1
Added DDF package information to Device Comparison Table .........................................................................4
Added Shutdown devices (TLV9051S/TLV9052S/TLV9054S) and packages (DGS/RUG/RTE) to Device
Comparison Table ..............................................................................................................................................4
Added DDF (SOT-23) package...........................................................................................................................5
Added TLV9051S pinout information to Pin Configurations and Functions section............................................5
Added TLV9052S pinout information to Pin Configurations and Functions section............................................5
Added TLV9054S and TLV9054 X2QFN (RUC) pinout information to Pin Configurations and Functions
section................................................................................................................................................................ 5
Added TLV9051 and TLV9051S thermal information to Thermal Information for Single Channel ................... 11
Added TLV9052S thermal info to Thermal Information for Dual Channel ........................................................12
Added DDF (SOT-23) package to Thermal Information for Dual Channel ...................................................... 12
Added TLV9054 and TLV9054S thermal information to Thermal Information for Quad Channel .................... 12
Added Shutdown Function information in Feature Description section............................................................ 25
Added "S" suffix to Related Links to reflect the addition of Shutdown devices.................................................31
Changes from Revision * (August 2018) to Revision A (December 2018)
Page
• 将器件状态从预告信息 更改为量产数据 .............................................................................................................1
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ZHCSI62I – AUGUST 2018 – REVISED NOVEMBER 2022
5 Device Comparison Table
PACKAGE LEADS
DEVICE
TLV9051
TLV9051S
TLV9052
TLV9052S
TLV9054
TLV9054S
(1)
4
NO. OF
CH.
1
2
4
SC70
DCK
SOT-23
DBV
SOT-553
(1)
DRL
X2SON
DPW
SOIC
D
WSON
DSG
VSSOP
DGK
TSSOP
PW
SOT-23
DDF
VSSOP
DGS
X2QFN
RUG
X2QFN
RUC
WQFN
RTE
5
5
5
5
—
—
—
—
—
—
—
—
—
—
6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
8
8
8
8
8
—
—
—
—
—
—
—
—
—
—
—
—
—
10
10
—
—
—
—
—
—
14
—
—
14
—
—
—
14
16
—
—
—
—
—
—
—
—
—
—
—
—
16
Package is for preview only.
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ZHCSI62I – AUGUST 2018 – REVISED NOVEMBER 2022
6 Pin Configuration and Functions
OUT
1
V±
2
IN+
3
5
V+
4
IN±
IN+
1
V±
2
IN±
3
Not to scale
5
V+
4
OUT
Not to scale
图 6-1. TLV9051 DBV, DRL Packages 5-Pin SOT-23, 图 6-2. TLV9051 DCK Package 5-Pin SC70 Top View
SOT-553 Top View
OUT
1
5
V+
4
IN+
3
V±
IN±
2
Not to scale
图 6-3. TLV9051 DPW Package 5-Pin X2SON Top View
表 6-1. Pin Functions: TLV9051
PIN
NAME
SOT-23,
SOT-553
SC-70
X2SON
I/O
DESCRIPTION
IN–
4
3
2
I
Inverting input
IN+
3
1
4
I
Noninverting input
OUT
1
4
1
O
Output
V–
2
2
3
—
Negative (low) supply or ground (for single-supply operation)
V+
5
5
5
—
Positive (high) supply
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ZHCSI62I – AUGUST 2018 – REVISED NOVEMBER 2022
+IN
1
6
V+
V±
2
5
SHDN
±IN
3
4
OUT
Not to scale
图 6-4. TLV9051S DBV Package 6-Pin SOT-23 Top View
表 6-2. Pin Functions: TLV9051S
PIN
NAME
6
NO.
I/O
DESCRIPTION
–IN
4
I
Inverting input
+IN
3
I
Noninverting input
OUT
1
O
Output
SHDN
5
I
Shutdown: low = amp disabled, high = amp enabled. See 节 8.3.9 for more information.
V–
2
—
Negative (lowest) supply or ground (for single-supply operation).
V+
6
—
Positive (highest) supply
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ZHCSI62I – AUGUST 2018 – REVISED NOVEMBER 2022
OUT1
1
8
V+
IN1±
2
7
OUT2
OUT1
1
IN1±
2
IN1+
3
6
IN2±
IN1+
3
V±
4
5
IN2+
V±
4
Not to scale
Thermal
Pad
8
V+
7
OUT2
6
IN2±
5
IN2+
Not to scale
图 6-5. TLV9052 D, DGK, PW, DDF Packages 8-Pin
SOIC, VSSOP, TSSOP, SOT-23 Top View
Connect exposed thermal pad to V–. See 节 8.3.6 for more
information.
图 6-6. TLV9052 DSG Package 8-Pin WSON With
Exposed Thermal Pad Top View
表 6-3. Pin Functions: TLV9052
PIN
NAME
NO.
I/O
DESCRIPTION
IN1–
2
I
Inverting input, channel 1
IN1+
3
I
Noninverting input, channel 1
IN2–
6
I
Inverting input, channel 2
IN2+
5
I
Noninverting input, channel 2
OUT1
1
O
Output, channel 1
OUT2
7
O
Output, channel 2
V–
4
—
Negative (low) supply or ground (for single-supply operation)
V+
8
—
Positive (high) supply
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IN1+
ZHCSI62I – AUGUST 2018 – REVISED NOVEMBER 2022
1
10
V+
IN1±
2
9
OUT2
IN1+
3
8
IN2±
V±
4
7
IN2+
SHDN1
5
6
SHDN2
V±
1
9
IN1±
SHDN1
2
8
OUT1
SHDN2
3
7
V+
IN2+
4
6
OUT2
10
OUT1
Not to scale
5
图 6-7. TLV9052S DGS Package 10-Pin VSSOP Top
View
IN2±
Not to scale
图 6-8. TLV9052S RUG Package 10-Pin X2QFN Top
View
表 6-4. Pin Functions: TLV9052S
PIN
NAME
8
VSSOP
X2QFN
I/O
DESCRIPTION
IN1–
2
9
I
Inverting input, channel 1
IN1+
3
10
I
Noninverting input, channel 1
IN2–
8
5
I
Inverting input, channel 2
IN2+
7
4
I
Noninverting input, channel 2
OUT1
1
8
O
Output, channel 1
OUT2
9
6
O
Output, channel 2
SHDN1
5
2
I
Shutdown: low = amp disabled, high = amp enabled, channel 1. See 节 8.3.9 for
more information.
SHDN2
6
3
I
Shutdown: low = amp disabled, high = amp enabled, channel 2. See 节 8.3.9 for
more information.
V–
4
1
—
Negative (low) supply or ground (for single-supply operation)
V+
10
7
—
Positive (high) supply
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3
12
IN4+
V+
4
11
V±
IN2+
5
10
IN3+
IN2±
6
9
IN3±
OUT2
7
8
OUT3
IN1±
1
IN1+
2
V+
OUT4
IN1+
12
IN4±
11
IN4+
3
10
V±
IN2+
4
9
IN3+
IN2±
5
8
IN3±
Not to scale
OUT2
图 6-9. TLV9054 D, PW Packages 14-Pin SOIC,
TSSOP Top View
13
IN4±
7
OUT4
13
OUT3
14
2
14
1
IN1±
6
OUT1
OUT1
ZHCSI62I – AUGUST 2018 – REVISED NOVEMBER 2022
Not to scale
IN1+
1
V+
2
IN2+
3
IN2±
4
IN1±
OUT1
OUT4
IN4±
16
15
14
13
图 6-10. TLV9054 RUC Package 14-Pin X2QFN Top
View
12
IN4+
11
V±
Thermal
5
6
7
8
OUT2
NC
NC
OUT3
Pad
10
IN3+
9
IN3±
Not to scale
Connect exposed thermal pad to V–. See 节 8.3.6 for more information.
图 6-11. TLV9054 RTE Package 16-Pin WQFN With Exposed Thermal Pad Top View
表 6-5. Pin Functions: TLV9054
PIN
I/O
DESCRIPTION
SOIC,
TSSOP
WQFN
X2QFN
IN1–
2
16
1
I
Inverting input, channel 1
IN1+
3
1
2
I
Noninverting input, channel 1
IN2–
6
4
5
I
Inverting input, channel 2
IN2+
5
3
4
I
Noninverting input, channel 2
NAME
IN3–
9
9
8
I
Inverting input, channel 3
IN3+
10
10
9
I
Noninverting input, channel 3
IN4–
13
13
12
I
Inverting input, channel 4
IN4+
12
12
11
I
Noninverting input, channel 4
NC
—
6, 7
—
—
No internal connection
OUT1
1
15
14
O
Output, channel 1
OUT2
7
5
6
O
Output, channel 2
OUT3
8
8
7
O
Output, channel 3
OUT4
14
14
13
O
Output, channel 4
V–
11
11
10
—
Negative (low) supply or ground (for single-supply operation)
V+
4
2
3
—
Positive (high) supply
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IN1+
1
V+
2
IN1±
OUT1
OUT4
IN4±
16
15
14
13
ZHCSI62I – AUGUST 2018 – REVISED NOVEMBER 2022
12
IN4+
11
V±
10
IN3+
9
IN3±
Thermal
6
7
8
SHDN34
OUT3
4
SHDN12
IN2±
Pad
5
3
OUT2
IN2+
Not to scale
Connect exposed thermal pad to V–. See 节 8.3.6 for more information.
图 6-12. TLV9054S RTE Package 16-Pin WQFN With Exposed Thermal Pad Top View
表 6-6. Pin Functions: TLV9054S
PIN
NAME
NO.
I/O
DESCRIPTION
IN1+
1
I
Noninverting input, channel 1
IN1–
16
I
Inverting input, channel 1
IN2+
3
I
Noninverting input, channel 2
IN2–
4
I
Inverting input, channel 2
IN3+
10
I
Noninverting input, channel 3
IN3–
9
I
Inverting input, channel 3
IN4+
12
I
Noninverting input, channel 4
IN4–
13
I
Inverting input, channel 4
SHDN12
6
I
Shutdown: low = amp disabled, high = amp enabled, channel 1 and 2. See 节 8.3.9 for more
information.
SHDN34
7
I
Shutdown: low = amp disabled, high = amp enabled, channel 3 and 4. See 节 8.3.9 for more
information.
OUT1
15
O
Output, channel 1
OUT2
5
O
Output, channel 2
OUT3
8
O
Output, channel 3
OUT4
14
O
Output, channel 4
V–
11
—
Negative (low) supply or ground (for single-supply operation)
V+
2
—
Positive (high) supply
10
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ZHCSI62I – AUGUST 2018 – REVISED NOVEMBER 2022
7 Specifications
7.1 绝对最大额定值
在自然通风温度下测得（除非另有说明）(1)
最小值
最大值
电压(2)
-10
输出短路(3)
10
-40
125
150
结温，TJ
-65
贮存温度，Tstg
mA
mA
连续
额定温度，TA
(2)
(3)
V
(V+) – (V–) + 0.2
差分
电流(2)
(1)
V
(V+) + 0.5
(V–) – 0.5
共模
信号输入引脚
温度
单位
7
电源电压
°C
150
应力超出绝对最大额定值 下所列的值可能会对器件造成永久损坏。这些仅为压力额定值，并不表示器件在这些条件下以及在建议运行条
件 以外的任何其他条件下能够正常运行。长时间处于绝对最大额定条件下可能会影响器件的可靠性。
输入引脚被二极管钳制至电源轨。对于摆幅能超过电源轨 0.5V 的输入信号，应将其电流限制在 10mA 或者更低。
接地短路，每个封装对应一个放大器。
7.2 ESD Ratings
VALUE
UNIT
TLV9051 X2SON PACKAGE
V(ESD)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±3000
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
±1500
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±4000
V
ALL OTHER PACKAGES
V(ESD)
(1)
(2)
Electrostatic discharge
Charged-device model (CDM), per JEDEC specification
JESD22-C101(2)
±1500
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted)
VS
Supply voltage, VS = (V+) – (V–)
VIN
Input pin voltage
MIN
MAX
UNIT
1.8
6.0
V
(V–) – 0.1
(V+) + 0.1
V
–40
125
°C
Specified temperature
7.4 Thermal Information for Single Channel
TLV9051, TLV9051S
THERMAL METRIC(1)
DPW (X2SON)
DBV (SOT-23)
DCK
(SC70)
DRL (SOT553)
(2)
UNIT
5 PINS
5 PINS
6 PINS
5 PINS
5 PINS
Junction-to-ambient thermal
resistance
470.0
228.1
210.8
231.2
TBD
°C/W
JC(top)
Junction-to-case(top) thermal
resistance
211.9
152.1
152.1
144.4
TBD
°C/W
RθJB
Junction-to-board thermal resistance
334.8
97.7
92.3
78.6
TBD
°C/W
ψJT
Junction-to-top characterization
parameter
29.8
74.1
76.2
51.3
TBD
°C/W
ψJB
Junction-to-board characterization
parameter
333.2
97.3
92.1
78.3
TBD
°C/W
RθJA
Rθ
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TLV9051, TLV9051S
THERMAL METRIC(1)
Rθ
JC(bot)
(1)
(2)
DPW (X2SON)
DBV (SOT-23)
DCK
(SC70)
DRL (SOT553)
(2)
5 PINS
5 PINS
6 PINS
5 PINS
5 PINS
N/A
N/A
N/A
N/A
TBD
Junction-to-case(bottom) thermal
resistance
UNIT
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
This package option is for preview only.
7.5 Thermal Information for Dual Channel
TLV9052, TLV9052S
THERMAL METRIC(1)
D
(SOIC)
DGK
(VSSOP)
DSG
(WSON)
PW
(TSSOP)
DDF
(SOT-23)
DGS
(VSSOP)
RUG
(X2QFN)
UNIT
8 PINS
8 PINS
8 PINS
8 PINS
8 PINS
10 PINS
10 PINS
Junction-to-ambient
thermal resistance
155.4
208.8
102.3
205.1
184.4
170.4
197.2
°C/W
Junction-to-case(top)
thermal resistance
95.5
93.3
120.0
93.7
112.8
84.9
93.3
°C/W
RθJB
Junction-to-board thermal
resistance
98.9
130.7
68.2
135.7
99.9
113.5
123.8
°C/W
ψJT
Junction-to-top
characterization parameter
41.9
26.1
15.1
25.0
18.7
16.4
3.7
°C/W
ψJB
Junction-to-board
characterization parameter
98.1
128.9
68.2
134.0
99.3
112.3
120.2
°C/W
Junction-to-case(bottom)
thermal resistance
N/A
N/A
43.6
N/A
N/A
N/A
N/A
°C/W
RθJA
Rθ
JC(top)
Rθ
JC(bot)
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.6 Thermal Information for Quad Channel
TLV9054, TLV9054S
THERMAL METRIC(1)
D (SOIC)
PW (TSSOP)
RTE (WQFN)
RUC (X2SQFN)
UNIT
14 PINS
14 PINS
14 PINS
16 PINS
14 PINS
Junction-to-ambient thermal
resistance
115.0
147.2
65.5
65.6
209.4
°C/W
JC(top)
Junction-to-case(top) thermal
resistance
71.1
67.2
70.6
70.6
68.8
°C/W
RθJB
Junction-to-board thermal resistance
71.0
91.6
40.5
40.5
153.3
°C/W
ψJT
Junction-to-top characterization
parameter
29.7
16.6
5.8
5.8
3.0
°C/W
ψJB
Junction-to-board characterization
parameter
70.6
90.7
40.5
40.5
152.8
°C/W
Junction-to-case(bottom) thermal
resistance
N/A
N/A
24.5
24.5
N/A
°C/W
RθJA
Rθ
Rθ
JC(bot)
(1)
12
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.7 电气特性：VS（总电源电压）= (V+) – (V-) = 1.8V 至 5.5V
TA = 25°C，RL = 10kΩ（连接至 VS/2），VCM = VS/2，VOUT = VS/2（除非另有说明）；
参数
测试条件
最小值
典型值
最大值
±0.33
±1.6
单位
失调电压
VOS
输入失调电压
dVOS/dT
漂移
PSRR
VS = 5V
±2
VS = 5V，TA = –40°C 至 +125°C
VS = 5V，TA = –40°C 至 +125°C
±0.5
电源抑制比
VS = 1.8V – 5.5V，VCM = (V–)
±13
通道分离，直流
在直流
115
mV
µV/°C
±80
µV/V
dB
输入电压范围
VCM
CMRR
VS = 1.8V 至 5.5V
共模电压
共模抑制比
(V+)+0.1
(V–) – 0.1
VS = 5.5 V，(V–) – 0.1V < VCM < (V+) – 1.4V，
TA = –40°C 至 +125°C
80
96
VS = 5.5V，VCM = -0.1V 至 5.6V，
TA = -40°C 至 +125°C
62
79
V
dB
VS = 1.8V，(V–) – 0.1V < VCM < (V+) – 1.4V，
TA = –40°C 至 +125°C
88
VS = 1.8V，VCM = -0.1V 至 1.9V，
TA = -40°C 至 +125°C
72
输入偏置电流
IB
IOS
±2
输入偏置电流
TA=-40°C 至 +125°C
±1
输入失调电流
TA=-40°C 至 +125°C
±18(2)
pA
±525(2)
pA
±15(2)
pA
±440(2)
pA
噪声
En
输入电压噪声（峰峰值）
en
输入电压噪声密度
in
输入电流噪声密度
6
µVPP
VS = 5V，f = 10kHz
15
nV/√Hz
VS = 5V，f = 1kHz
20
nV/√Hz
f = 1kHz
18
fA/√Hz
VS = 5V，f = 0.1Hz 至 10Hz
输入电容
CID
差分
2
pF
CIC
共模
4
pF
开环增益
VS = 1.8V，(V–) + 0.04V < VO < (V+) – 0.04V，
RL = 10kΩ
AOL
VS = 5.5V，(V–) + 0.05V < VO < (V+) – 0.05V，
RL = 10kΩ
开环电压增益
106
104
128
dB
VS = 1.8V，(V–) + 0.06V < VO < (V+) – 0.06V，
RL = 2kΩ
108
VS = 5.5V，(V–) + 0.15V < VO < (V+) – 0.15V，
RL = 2kΩ
130
频率响应
GBP
增益带宽积
VS = 5.5V，G = +1
5
φm
相位裕度
VS = 5.5V，G = +1
60
度
SR
压摆率
VS = 5.5V，G = +1，CL = 130pF
15
V/µs
tS
趋稳时间
tOR
THD + N
精度达到 0.1%，VS = 5.5V，2V 阶跃，G = +1，CL =
100pF
精度达到 0.01%，VS = 5.5V，2V 阶跃，G = +1，CL =
100pF
VS = 5.5V，VIN × 增益 > VS
过载恢复时间
总谐波失真 +
噪声(1)
VS = 5.5V，VCM = 2.5V，VO = 1VRMS，G = +1，f = 1kHz
MHz
0.75
µs
1
0.3
µs
0.0006%
输出
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ZHCSI62I – AUGUST 2018 – REVISED NOVEMBER 2022
7.7 电气特性：VS（总电源电压）= (V+) – (V-) = 1.8V 至 5.5V (continued)
TA = 25°C，RL = 10kΩ（连接至 VS/2），VCM = VS/2，VOUT = VS/2（除非另有说明）；
参数
VO
测试条件
最小值
典型值
S
最大值
16
相对于电源轨的电压输出摆 VS = 5.5V，RL = 10kΩ，
幅
V = 5.5V，R = 2kΩ，
40
L
单位
mV
ISC
短路电流
VS = 5V
±50
mA
ZO
开环输出阻抗
VS = 5V，f = 5 MHz
250
Ω
VS = 5.5V，IO = 0mA，
330
电源
IQ
(1)
(2)
14
每个放大器的静态电流
VS = 5.5V，IO = 0mA，TA = -40°C 至 +125°C
450
475
µA
三阶滤波器；–3dB 时的带宽 = 80kHz。
根据设计和特征确定；未经生产测试。
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ZHCSI62I – AUGUST 2018 – REVISED NOVEMBER 2022
7.8 Typical Characteristics
at TA = 25°C, VS = 5.5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
21
40
18
30
Devices (%)
Devices (%)
15
12
9
6
20
10
3
0
0
-1200
-900
-600
-300
0
300
600
900
Offset Voltage (µV)
1200
0
DC15
0.4
VS = 5.5 V
图 7-1. Offset Voltage Production Distribution
350
300
Offset Voltage (µV)
Offset Voltage (µV)
2
DC16
450
400
200
100
0
-100
-200
-300
250
150
50
-50
-150
-400
-250
-500
-25
-10
5
20 35 50 65
Temperature (°C)
80
95
-350
-3
110 125
Input Bias Current and Offset Current (pA)
400
300
200
100
0
-100
-200
-300
-400
2.5
3
3.5
4
Supply Voltage (V)
4.5
图 7-5. Offset Voltage vs Power Supply
-1
0
1
Common-Mode Voltage (V)
2
3
DC21
图 7-4. Offset Voltage vs Common-Mode Voltage
500
2
-2
DC08
图 7-3. Offset Voltage vs Temperature
Offset Voltage (µV)
1.6
图 7-2. Offset Voltage Drift Distribution
500
-500
1.5
1.2
VS = 5.5 V, TA = –40°C to 125°C
600
-600
-40
0.8
Offset Voltage Drift (µV/C)
5
5.5
120
110
100
IBIB+
IOS
90
80
70
60
50
40
30
20
10
0
-50
-25
DC23
0
25
50
Temperature (°C)
75
100
125
DC02
图 7-6. Input Bias Current vs Temperature
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ZHCSI62I – AUGUST 2018 – REVISED NOVEMBER 2022
7.8 Typical Characteristics
18
IBIB+
IOS
16
14
Voltage (1µV/div)
Input Bias Current and Offset Current (pA)
at TA = 25°C, VS = 5.5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
12
10
8
6
4
2
0
-3
-2
-1
0
1
Input Common-Mode Voltage (V)
2
Time (1s/div)
3
D008
DC03
图 7-8. 0.1-Hz to 10-Hz Input Voltage Noise
120
140
120
100
80
60
40
0
10
100
1k
Frequency (Hz)
10k
10k
100k
Frequency (Hz)
1M
D018
20
19
18
VS = 5.5 V, VCM = -0.1 V to (V+) - 1.4 V
VS = 5.5 V, VCM = -0.1 V to 5.6 V
VS = 1.8 V, VCM = -0.1 V to (V+) - 1.4 V
VS = 1.8 V, VCM = -0.1 V to 5.6 V
PSRR (µV/V)
17
120
100
80
16
15
14
60
13
40
12
20
0
-50
1k
图 7-10. CMRR and PSRR vs Frequency (Referred to Input)
200
CMRR (µV/V)
40
D024
220
140
60
0
100
100k
图 7-9. Input Voltage Noise Spectral Density vs Frequency
160
80
20
20
180
PSRR+
PSRRCMRR
100
PSRR and CMRR (dB)
Input Voltage Noise Spectral Density (nV/—Hz)
图 7-7. Input Bias Current and Offset Current vs Common-Mode
Voltage
11
-25
0
25
50
Temperature (°C)
75
100
125
10
-50
-25
0
DC17
图 7-11. CMRR vs Temperature
25
50
Temperature (°C)
75
100
125
DC18
VS = 1.8 V to 5.5 V
图 7-12. PSRR vs Temperature
16
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ZHCSI62I – AUGUST 2018 – REVISED NOVEMBER 2022
7.8 Typical Characteristics (continued)
120
80
100
60
80
40
60
20
40
0
130
20
Gain
Phase
-20
100
135
Open Loop Voltage Gain (dB)
100
Phase Margin (q)
Open Loop Voltage Gain (dB)
at TA = 25°C, VS = 5.5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
125
120
115
110
105
VS = 1.8V, RL = 2k:
VS = 5.5V, RL = 2k:
VS = 1.8V, RL = 10k:
VS = 5.5V, RL = 10k:
100
1k
10k
100k
Frequency (Hz)
0
10M
1M
95
-40
D004
-20
0
图 7-13. Open Loop Voltage Gain and Phase vs Frequency
20
40
60
80
Temperature (°C)
100
120
140
DC01
180
70
160
60
Closed Lopp Voltage Gain (dB)
Open Loop Voltage Gain (dB)
图 7-14. Open Loop Voltage Gain vs Temperature
140
120
100
80
60
40
20
0
-0.5
G=1
G = -1
G = 10
G = 100
G = 1000
50
40
30
20
10
0
-10
-20
0.5
1.5
2.5
3.5
Output Voltage (V)
4.5
-30
1k
5.5
10k
DC26
图 7-15. Open Loop Voltage Gain vs Output Voltage
100k
Frequency (Hz)
1M
D005
图 7-16. Closed Loop Voltage Gain vs Frequency
70
VOUT
VIN
60
50
Voltage (1 V/div)
Phase Margin (q)
10M
40
30
20
10
0
0
50
100
150
200
250
Capacitive Load (pF)
300
图 7-17. Phase Margin vs Capacitive Load
Time (100 Ps/div)
350
D013
D017
图 7-18. No Phase Reversal
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7.8 Typical Characteristics (continued)
at TA = 25°C, VS = 5.5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
60
60
Overshoot(+)
Overshoot(-)
Overshoot(+)
Overshoot(-)
50
50
Overshoot (%)
Overshoot (%)
40
30
20
40
30
20
10
10
0
0
50
100
150 200 250 300
Capacitive Load (pF)
350
400
0
450
50
100
D016
G = +1 V/V
VOUT step = 100 mVp-p
150 200 250 300
Capacitive Load (pF)
350
400
450
D015
G = –1 V/V
VOUT step = 100 mVp-p
图 7-19. Small-Signal Overshoot vs Load Capacitance
图 7-20. Small-Signal Overshoot vs Load Capacitance
17
Slew Rate (V/Ps)
16
15.5
15
14.5
14
Output
Input
Output Voltage (2 V/div)
Input Voltage (0.2 V/div)
16.5
13.5
13
50
100
150
200
250
Capacitive Load (pF)
300
350
Time (2 us/div)
D019
D014
图 7-21. Slew Rate vs Capacitive Load
G = –10 V/V
图 7-22. Overload Recovery
VIN
Voltage (2 mV/div)
VOUT
Voltage (2 mV/div)
VOUT
VIN
Time (1 Ps/div)
Time (1 Ps)
D021
D020
G = +1 V/V
VOUT step = 10
mVp-p
图 7-23. Small-Signal Step Response
18
G = –1 V/V
VOUT step = 10
mVp-p
图 7-24. Small-Signal Step Response
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ZHCSI62I – AUGUST 2018 – REVISED NOVEMBER 2022
7.8 Typical Characteristics (continued)
at TA = 25°C, VS = 5.5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
VOUT
VIN
Voltage (1 V/div)
VIN
Voltage (1 V/div)
VOUT
Time (1 Ps/div)
Time (1 Ps/div)
D012
D011
G = +1 V/V
VOUT step = 4 Vp-p
G = –1 V/V
VOUT step = 4 Vp-p
图 7-25. Large-Signal Step Response
图 7-26. Large-Signal Step Response
20
Output Delta from Final Value (mV)
Output Delta from Final Value (mV)
20
10
0
0.1% Settling = r 2 mV
-10
-20
-30
0.2
0.4
CL = 100 pF
0.6
0.8
Time (µs)
1
1.2
10
0
0.1% Settling = r 2 mV
-10
-20
-30
0.2
1.4
0.4
0.6
D010
CL = 100 pF
G = +1 V/V
0.8
Time (µs)
1
1.2
1.4
D009
G = +1 V/V
图 7-28. Negative Large-Signal Settling Time
图 7-27. Positive Large-Signal Settling Time
-10
-65
RL = 10 k:
RL = 2 k:
RL = 600 :
G = +1, RL = 10 k:
G = +1, RL = 2 k:
G = +1, RL = 600 :
-30
THD + N (dB)
THD + N (dB)
-75
-85
-50
-70
-95
-90
-105
100
1k
Frequency (Hz)
VOUT = 0.5 VRMS
-110
1m
10k
10m
100m
Output Voltage Amplitude (V RMS)
D023
G = +1
BW = 80 kHz
VCM = 2.5 V
图 7-29. THD + N vs Frequency
f = 1 kHz
G = +1
BW = 80 kHz
1
D022
VCM = 2.5 V
图 7-30. THD + N vs Amplitude
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ZHCSI62I – AUGUST 2018 – REVISED NOVEMBER 2022
7.8 Typical Characteristics (continued)
at TA = 25°C, VS = 5.5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
6
3
2.5
Maximum Output Voltage (V)
2
Output Voltage (V)
1.5
125qC
1
85qC
0.5
25qC
-40qC
0
-0.5
85qC
-1
25qC
-40qC
125qC
-1.5
-2
5
4
3
2
1
VS = 5.5 V
VS = 1.8 V
-2.5
-3
0
10
20
30
40
Output Current (mA)
50
0
60
1
图 7-31. Output Voltage Swing vs Output Current
100
1k
10k
100k
Frequency (Hz)
1M
10M
100M
DC25
图 7-32. Maximum Output Voltage vs Frequency and Supply
Voltage
330
100
Sinking
Sourcing
80
325
60
Quiescent Current (µA)
Short Circuit Current Limit (mA)
10
DC07
40
20
0
-20
-40
320
315
310
305
-60
-80
-40
-25
-10
5
20 35 50 65
Temperature (°C)
80
95
300
1.8
110 125
图 7-33. Short-Circuit Current vs Temperature
Open Loop Output Impedance (:)
Quiescent Current (µA)
325
320
315
310
305
0
20
40
60
Temperature (°C)
80
100
图 7-35. Quiescent Current vs Temperature
20
3.3
3.8
4.3
Supply Voltage (V)
4.8
5.3
DC05
500
400
VS = 1.8V
VS = 5.5V
-20
2.8
图 7-34. Quiescent Current vs Supply Voltage
330
300
-40
2.3
DC06
120
300
200
100
IOUT = 0 mA
IOUT = 5 mA
IOUT = -5 mA
70
50
40
30
20
10k
DC04
100k
Frequency (Hz)
1M
D025
图 7-36. Open-Loop Output Impedance vs Frequency
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7.8 Typical Characteristics (continued)
at TA = 25°C, VS = 5.5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
-70
120
-80
Channel Separation (dB)
140
EMIRR (dB)
100
80
60
40
-100
-110
-120
20
0
10M
-90
100M
Frequency (Hz)
-130
100
1G
1k
D007
1M
D006
PRF = –10 dBm
PRF = –10 dBm
图 7-37. Electromagnetic Interference Rejection Ratio Referred
to Noninverting Input (EMIRR+) vs Frequency
10k
100k
Frequency (Hz)
图 7-38. Channel Separation vs Frequency
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8 Detailed Description
8.1 Overview
The TLV905x devices are a 5-MHz family of low-power, rail-to-rail input and output op amps. These devices
operate from 1.8 V to 5.5 V, are unity-gain stable, and are designed for a wide range of general-purpose
applications. The input common-mode voltage range includes both rails and allows the TLV905x family to be
used in virtually any single-supply application. The unique combination of a high slew rate and low quiescent
current makes this family a potential choice for battery-powered motor-drive applications. Rail-to-rail input and
output swing significantly increase dynamic range, especially in low-supply applications.
8.2 Functional Block Diagram
22
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8.3 Feature Description
8.3.1 Operating Voltage
The TLV905x family of op amps is specified for operation from 1.8 V to 6.0 V. In addition, many specifications
apply from –40°C to 125°C. Parameters that vary significantly with operating voltages or temperature are
illustrated in the 节 7.8.
8.3.2 Rail-to-Rail Input
The input common-mode voltage range of the TLV905x family extends 100 mV beyond the supply rails for the
full supply voltage range of 1.8 V to 6.0 V. This performance is achieved with a complementary input stage: an
N-channel input differential pair in parallel with a P-channel differential pair, as shown in the 节 8.2. The Nchannel pair is active for input voltages close to the positive rail, typically (V+) – 1.4 V to 200 mV above the
positive supply, whereas the P-channel pair is active for inputs from 200 mV below the negative supply to
approximately (V+) – 1.4 V. There is a small transition region, typically (V+) – 1.2 V to (V+) – 1 V, in which
both pairs are on. This 200-mV transition region can vary up to 200 mV with process variation. Thus, the
transition region (with both stages on) can range from (V+) – 1.4 V to (V+) – 1.2 V on the low end, and up to
(V+) – 1 V to (V+) – 0.8 V on the high end. Within this transition region, PSRR, CMRR, offset voltage, offset
drift, and THD can degrade compared to device operation outside this region.
8.3.3 Rail-to-Rail Output
Designed as low-power, low-voltage operational amplifiers, the TLV905x family delivers a robust output drive
capability. A class AB output stage with common-source transistors achieves full rail-to-rail output swing
capability. For resistive loads of 10 kΩ, the output swings to within 16 mV of either supply rail, regardless of the
applied power-supply voltage. Different load conditions change the ability of the amplifier to swing close to the
rails.
8.3.4 EMI Rejection
The TLV905x uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI from
sources such as wireless communications and densely-populated boards with a mix of analog signal chain and
digital components. EMI immunity can be improved with circuit design techniques; the TLV905x benefits from
these design improvements. Texas Instruments has developed the ability to accurately measure and quantify the
immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz. 图 8-1
shows the results of this testing on the TLV905x. 表 8-1 shows the EMIRR IN+ values for the TLV905x at
particular frequencies commonly encountered in real-world applications. The EMI Rejection Ratio of Operational
Amplifiers application report contains detailed information on the topic of EMIRR performance as it relates to op
amps and is available for download from www.ti.com.
140
120
EMIRR (dB)
100
80
60
40
20
0
10M
100M
Frequency (Hz)
1G
D007
图 8-1. EMIRR Testing
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表 8-1. TLV905x EMIRR IN+ for Frequencies of Interest
FREQUENCY
APPLICATION OR ALLOCATION
EMIRR IN+
400 MHz
Mobile radio, mobile satellite, space operation, weather, radar, ultra-high frequency (UHF)
applications
41.8 dB
900 MHz
Global system for mobile communications (GSM) applications, radio communication, navigation,
GPS (to 1.6 GHz), GSM, aeronautical mobile, UHF applications
53.1 dB
1.8 GHz
GSM applications, mobile personal communications, broadband, satellite, L-band (1 GHz to 2 GHz)
71.8 dB
Bluetooth®,
2.4 GHz
802.11b, 802.11g, 802.11n,
mobile personal communications, industrial, scientific and
medical (ISM) radio band, amateur radio and satellite, S-band (2 GHz to 4 GHz)
70.0 dB
3.6 GHz
Radiolocation, aero communication and navigation, satellite, mobile, S-band
81.2 dB
802.11a, 802.11n, aero communication and navigation, mobile communication, space and satellite
operation, C-band (4 GHz to 8 GHz)
92.5 dB
5 GHz
8.3.5 Overload Recovery
Overload recovery is defined as the time required for the operational amplifier output to recover from a saturated
state to a linear state. The output devices of the operational amplifier enter a saturation region when the output
voltage exceeds the rated operating voltage, because of the high input voltage or high gain. After the device
enters the saturation region, the output devices require time to return to the linear operating state. After the
output devices return to their linear operating state, the device begins to slew at the specified slew rate.
Therefore, the propagation delay (in case of an overload condition) is the sum of the overload recovery time and
the slew time. The overload recovery time for the TLV905x family is approximately 300 ns.
8.3.6 Packages With an Exposed Thermal Pad
The TLV905x family is available in packages such as the WSON-8 (DSG) and WQFN-16 (RTE) which feature an
exposed thermal pad. Inside the package, the die is attached to this thermal pad using an electrically conductive
compound. For this reason, when using a package with an exposed thermal pad, the thermal pad must either be
connected to V– or left floating. Attaching the thermal pad to a potential other then V– is not allowed, and the
performance of the device is not verified when doing so.
8.3.7 Electrical Overstress
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress.
These questions tend to focus on the device inputs, but can involve the supply voltage pins or even the output
pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown
characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.
Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from
accidental ESD events both before and during product assembly.
Having a good understanding of this basic ESD circuitry and its relevance to an electrical overstress event is
helpful. 图 8-2 shows the ESD circuits contained in the TLV905x devices. The ESD protection circuitry involves
several current-steering diodes connected from the input and output pins and routed back to the internal power
supply lines, where they meet at an absorption device internal to the operational amplifier. This protection
circuitry is intended to remain inactive during normal circuit operation.
24
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V+
Power Supply
ESD Cell
+IN
+
±
± IN
OUT
V±
图 8-2. Equivalent Internal ESD Circuitry
8.3.8 Input Protection
The TLV905x family incorporates internal ESD protection circuits on all pins. For input and output pins, this
protection primarily consists of current-steering diodes connected between the input and power-supply pins.
These ESD protection diodes provide in-circuit, input overdrive protection, as long as the current is limited to 10
mA, as shown in the 节 7.1. 图 8-3 shows how a series input resistor can be added to the driven input to limit the
input current. The added resistor contributes thermal noise at the amplifier input and the value must be kept to a
minimum in noise-sensitive applications.
V+
IOVERLOAD
10-mA maximum
Device
VOUT
VIN
5 kW
图 8-3. Input Current Protection
8.3.9 Shutdown Function
The TLV905xS devices feature SHDN pins that disable the op amp, placing the device into a low-power standby
mode. In this mode, the op amp typically consumes less than 1 µA. The SHDN pins are active low, meaning that
shutdown mode is enabled when the input to the SHDN pin is a valid logic low.
The SHDN pins are referenced to the negative supply voltage of the op amp. The threshold of the shutdown
feature lies around 800 mV (typical) and does not change with respect to the supply voltage. Hysteresis has
been included in the switching threshold to ensure smooth switching characteristics. To ensure shutdown
behavior, the SHDN pins should be driven with valid logic signals. A valid logic low is defined as a voltage
between V– and V– + 0.4 V. A valid logic high is defined as a voltage between V– + 1.2 V and V+. The
shutdown pin circuitry includes a pull-up resistor, which will inherently pull the voltage of the pin to the positive
supply rail if not driven. Thus, to enable the amplifier, the SHDN pins must either be left floating or driven to a
valid logic high. To disable the amplifier, the SHDN pins must be driven to a valid logic low .While TI highly
recommends that the shutdown pin be connected to a valid high or a low voltage or driven, TI has included a
pull-up resistor connected to VCC. The maximum voltage allowed at the SHDN pins is (V+) + 0.5 V. Exceeding
this voltage level will damage the device.
The SHDN pins are high-impedance CMOS inputs. Dual op amp versions are independently controlled and quad
op amp versions are controlled in pairs with logic inputs. For battery-operated applications, this feature may be
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used to greatly reduce the average current and extend battery life. The enable time is 35 µs for full shutdown of
all channels; disable time is 6 µs. When disabled, the output assumes a high-impedance state. This architecture
allows the TLV905xS to be operated as a gated amplifier (or to have the device output multiplexed onto a
common analog output bus). Shutdown time (tOFF) depends on loading conditions and increases as load
resistance increases. To ensure shutdown (disable) within a specific shutdown time, the specified 10-kΩ load to
midsupply (VS / 2) is required. If using the TLV905xS without a load, the resulting turnoff time is significantly
increased.
8.4 Device Functional Modes
The TLV905x family is operational when the power-supply voltage is between 1.8 V (±0.9 V) and 6.0 V (±3.0 V).
The TLV905xS devices feature a shutdown mode and are shutdown when a valid logic low is applied to the
shutdown pin.
26
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9 Application and Implementation
备注
以下应用部分中的信息不属于 TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
9.1 Application Information
The TLV905x family features 5-MHz bandwidth and very high slew rate of 15 V/µs with only 330 µA of supply
current per channel, providing excellent AC performance at very low-power consumption. DC applications are
well served with a very low input noise voltage of 15 nV/√ Hz at 10 kHz, low input bias current, and a typical
input offset voltage of 0.33 mV.
9.2 Typical Low-Side Current Sense Application
图 9-1 shows the TLV905x configured in a low-side current sensing application.
VBUS
ILOAD
Z LOAD
5V
+
TLV905x
RSHUNT
0.1 Ÿ
VSHUNT
VOUT
í
+
í
RF
165 NŸ
RG
3.4 NŸ
图 9-1. TLV905x in a Low-Side, Current-Sensing Application
9.2.1 Design Requirements
The design requirements for this design are:
• Load current: 0 A to 1 A
• Output voltage: 4.95 V
• Maximum shunt voltage: 100 mV
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9.2.2 Detailed Design Procedure
The transfer function of the circuit in 图 9-1 is given in 方程式 1.
VOUT = ILOAD × RSHUNT × Gain
(1)
The load current (ILOAD) produces a voltage drop across the shunt resistor (RSHUNT). The load current is set from
0 A to 1 A. To keep the shunt voltage below 100 mV at maximum load current, the largest shunt resistor is
defined using 方程式 2.
V
RSHUNT = ISHUNT_MAX = 100 mV
1 A = 100 mΩ
(2)
LOAD_MAX
Using 方程式 2, RSHUNT equals 100 mΩ. The voltage drop produced by ILOAD and RSHUNT is amplified by the
TLV905x device to produce an output voltage of approximately 0 V to 4.95 V. 方程式 3 calculates the gain
required for the TLV905x device to produce the required output voltage.
Gain =
VOUT_MAX − VOUT
MIN
(3)
VIN_MAX − VIN_MIN
Using 方程式 3, the required gain equals 49.5 V/V, which is set with the RF and R G resistors. 方程式 4 sizes the
RF and RG, resistors to set the gain of the TLV905x device to 49.5 V/V.
Gain = 1 +
RF
RG
(4)
Selecting RF to equal 165 kΩ and RG to equal 3.4 kΩ provides a combination that equals approximately 49.5
V/V. 图 9-2 shows the measured transfer function of the circuit shown in 图 9-1.
9.2.3 Application Curve
5
Output (V)
4
3
2
1
0
0
0.2
0.4
0.6
0.8
ILOAD (A)
1
C219
图 9-2. Low-Side, Current-Sense Transfer Function
28
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9.3 Power Supply Recommendations
The TLV905x family is specified for operation from 1.8 V to 6.0 V (±0.9 V to ±3.0 V); many specifications apply
from –40°C to 125°C. The 节 7.8 section presents parameters that can exhibit significant variance with regard
to operating voltage or temperature.
CAUTION
Supply voltages larger than 7 V can permanently damage the device; see the 节 7.1 table.
Place 0.1-µF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or highimpedance power supplies. For more-detailed information on bypass capacitor placement, see the 节 9.4.2
section.
9.4 Layout
9.4.1 Layout Guidelines
For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and of the op amp
itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources
local to the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for singlesupply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise pickup. Take care
to physically separate digital and analog grounds, paying attention to the flow of the ground current. For more
detailed information, see Circuit Board Layout Techniques.
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If
these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as opposed
to in parallel with the noisy trace.
• Place the external components as close to the device as possible. As illustrated in 图 9-4, keeping RF and RG
close to the inverting input minimizes parasitic capacitance on the inverting input.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
• Cleaning the PCB following board assembly is recommended for best performance.
• Any precision integrated circuit can experience performance shifts resulting from moisture ingress into the
plastic package. Following any aqueous PCB cleaning process, baking the PCB assembly is recommended
to remove moisture introduced into the device packaging during the cleaning process. A low-temperature,
post-cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
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9.4.2 Layout Example
+
VIN 1
+
VIN 2
VOUT 1
RG
VOUT 2
RG
RF
RF
图 9-3. Schematic Representation for 图 9-4
Place components
close to device and to
each other to reduce
parasitic errors .
OUT 1
VS+
OUT1
Use low-ESR,
ceramic bypass
capacitor . Place as
close to the device
as possible .
GND
V+
RF
OUT 2
GND
IN1 ±
OUT2
IN1 +
IN2 ±
RF
RG
VIN 1
GND
RG
V±
Use low-ESR,
ceramic bypass
capacitor . Place as
close to the device
as possible .
GND
VS±
IN2 +
Ground (GND) plane on another layer
VIN 2
Keep input traces short
and run the input traces
as far away from
the supply lines
as possible .
图 9-4. Layout Example
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10 Device and Documentation Support
10.1 Documentation Support
10.1.1 Related Documentation
Texas Instruments, TLVx313 Low-Power, Rail-to-Rail In/Out, 500-µV Typical Offset, 1-MHz Operational Amplifier
for Cost-Sensitive Systems
Texas Instruments, TLVx314 3-MHz, Low-Power, Internal EMI Filter, RRIO, Operational Amplifier
Texas Instruments, EMI Rejection Ratio of Operational Amplifiers
Texas Instruments, QFN/SON PCB Attachment
Texas Instruments, Quad Flatpack No-Lead Logic Packages
Texas Instruments, Circuit Board Layout Techniques
Texas Instruments, Single-Ended Input to Differential Output Conversion Circuit Reference Design
10.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
表 10-1. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TLV9051/S
Click here
Click here
Click here
Click here
Click here
TLV9052/S
Click here
Click here
Click here
Click here
Click here
TLV9054/S
Click here
Click here
Click here
Click here
Click here
10.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
10.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
10.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
Bluetooth® is a registered trademark of Bluetooth SIG, Inc.
所有商标均为其各自所有者的财产。
10.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and without
revision of this document. For browser-based versions of this data sheet, see the left-hand navigation pane.
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PACKAGE OPTION ADDENDUM
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7-Jul-2023
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TLV9051IDBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
T51D
Samples
TLV9051IDCKR
ACTIVE
SC70
DCK
5
3000
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 125
T51
Samples
TLV9051IDPWR
ACTIVE
X2SON
DPW
5
3000
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
FH
Samples
TLV9051SIDBVR
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
T51S
Samples
TLV9052IDDFR
ACTIVE
SOT-23-THIN
DDF
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
T052
Samples
TLV9052IDGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAU | SN
| NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
1PWX
Samples
TLV9052IDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TL9052
Samples
TLV9052IDSGR
ACTIVE
WSON
DSG
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
9052
Samples
TLV9052IPWR
ACTIVE
TSSOP
PW
8
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TL9052
Samples
TLV9052SIDGSR
ACTIVE
VSSOP
DGS
10
2500
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
T052
Samples
TLV9052SIRUGR
ACTIVE
X2QFN
RUG
10
3000
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
FPF
Samples
TLV9054IDR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TLV9054D
Samples
TLV9054IPWR
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 125
T9054PW
Samples
TLV9054IRTER
ACTIVE
WQFN
RTE
16
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
T54RT
Samples
TLV9054IRUCR
ACTIVE
QFN
RUC
14
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
1FF
Samples
TLV9054SIRTER
ACTIVE
WQFN
RTE
16
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
T9054S
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
7-Jul-2023
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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