TLV9151-Q1, TLV9152-Q1, TLV9154-Q1
SBOSA23F – MAY 2020 – REVISED JUNE 2023
TLV915x-Q1 4.5-MHz, Rail-to-Rail Input or Output, Low Offset Voltage, Low Noise
Automotive Op Amp
1 Features
3 Description
•
The TLV915x-Q1 family (TLV9151-Q1, TLV9152-Q1,
and TLV9154-Q1) is a family of 16-V, general purpose
automotive operational amplifiers. These devices
offer exceptional DC precision and AC performance,
including rail-to-rail output, low offset (±125 µV,
typ), low offset drift (±0.3 µV/°C, typ), and 4.5-MHz
bandwidth.
•
•
•
•
•
•
•
•
•
•
•
AEC-Q100 qualified for automotive applications
– Temperature grade 1: –40°C to +125°C, TA
– Device HBM ESD classification level 3A
– Device CDM ESD classification level C6
Low offset voltage: ±125 µV
Low offset voltage drift: ±0.3 µV/°C
Low noise: 10.8 nV/√Hz at 1 kHz
High common-mode rejection: 120 dB
Low bias current: ±10 pA
Rail-to-rail input and output
Wide bandwidth: 4.5-MHz GBW
High slew rate: 21 V/µs
Low quiescent current: 560 µA per amplifier
Wide supply: ±1.35 V to ±8 V, 2.7 V to 16 V
Robust EMIRR performance: EMI/RFI filters on
input pins
Convenient features such as wide differential inputvoltage range, high output current (±75 mA), high
slew rate (21 V/µs), and low noise (10.8 nV/√Hz)
make the TLV915x-Q1 a robust, low-noise operational
amplifier for automotive applications.
The TLV915x-Q1 family of op amps is available in
standard packages and is specified from –40°C to
125°C.
Device Information
2 Applications
•
•
•
•
•
•
•
•
•
PART NUMBER
Optimized for AEC-Q100 grade 1 applications
Infotainment and cluster
Passive safety
Body electronics and lighting
HEV/EV inverter and motor control
On-board (OBC) and wireless charger
Powertrain current sensor
Advanced driver assistance systems (ADAS)
High-side and low-side current sensing
TLV9151-Q1
Single
TLV9152-Q1
Dual
TLV9154-Q1
(1)
(2)
RG
CHANNEL COUNT
Quad
PACKAGE(1)
PACKAGE SIZE(2)
DBV (SOT-23, 5)
2.90 mm × 2.80 mm
D (SOIC, 8)
4.90 mm × 6.00 mm
PW (TSSOP, 8)
3.00 mm × 6.40 mm
DGK (VSSOP, 8)
3.00 mm × 4.90 mm
D (SOIC, 14)
8.65 mm × 6.00 mm
DYY (SOT-23, 14)
4.20 mm × 3.26 mm
PW (TSSOP, 14)
5.00 mm × 6.40 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
The package size (length × width) is a nominal value and
includes pins, where applicable.
RF
R1
VOUT
VIN
C1
f-3 dB =
(
RF
VOUT
= 1+
RG
VIN
((
1
1 + sR1C1
1
2pR1C1
(
TLV915x-Q1 in a Single-Pole, Low-Pass Filter
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLV9151-Q1, TLV9152-Q1, TLV9154-Q1
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SBOSA23F – MAY 2020 – REVISED JUNE 2023
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 6
6.1 Absolute Maximum Ratings........................................ 6
6.2 ESD Ratings............................................................... 6
6.3 Recommended Operating Conditions.........................6
6.4 Thermal Information for Single Channel..................... 6
6.5 Thermal Information for Dual Channel........................7
6.6 Thermal Information for Quad Channel...................... 7
6.7 Electrical Characteristics.............................................8
6.8 Typical Characteristics.............................................. 10
7 Detailed Description......................................................17
7.1 Overview................................................................... 17
7.2 Functional Block Diagram......................................... 17
7.3 Feature Description...................................................18
7.4 Device Functional Modes..........................................24
8 Application and Implementation.................................. 25
8.1 Application Information............................................. 25
8.2 Typical Applications.................................................. 25
8.3 Power Supply Recommendations.............................26
8.4 Layout....................................................................... 27
9 Device and Documentation Support............................29
9.1 Device Support......................................................... 29
9.2 Documentation Support............................................ 29
9.3 Receiving Notification of Documentation Updates....29
9.4 Support Resources................................................... 29
9.5 Electrostatic Discharge Caution................................30
9.6 Glossary....................................................................30
10 Mechanical, Packaging, and Orderable
Information.................................................................... 30
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (March 2022) to Revision F (June 2023)
Page
• Changed the status of the (TSSOP, 14) package from: preview to: active.........................................................1
Changes from Revision D (September 2021) to Revision E (March 2022)
Page
• Changed maximum PSRR (2.7 V to 16 V) from ±8µV/V to ±10.6µV/V...............................................................8
• Changed minimum CMRR (at 16 V) from 100 dB to 99 dB ............................................................................... 8
Changes from Revision C (May 2021) to Revision D (September 2021)
Page
• Deleted preview note from SOIC (14) package in Device Information table...................................................... 1
• Deleted preview note from SOT-23 (14) package in Device Information table...................................................1
• Deleted preview note from SOIC (8) package in Device Information table........................................................ 1
• Deleted preview note from SOT-23 (5) package in Device Information table.....................................................1
• Deleted preview note from SOT-23 (14) Package, in Pin Configuration and Functions section.........................3
• Deleted preview note from SOIC (14) Package, in Pin Configuration and Functions section............................ 3
• Deleted preview note from SOIC (8) Package, in Pin Configuration and Functions section.............................. 3
• Deleted preview note from SOT-23 (5) Package, in Pin Configuration and Functions section...........................3
Changes from Revision B (March 2021) to Revision C (May 2021)
Page
• Deleted preview note from TSSOP (14) package in Device Information table...................................................1
• Deleted preview note from TSSOP (14) Package, in Pin Configuration and Functions section.........................3
• Deleted preview note from PW package in Thermal Information for Quad Channel table. ............................... 7
Changes from Revision A (January 2021) to Revision B (March 2021)
Page
• Changed device status from Advance Information to Production Data ............................................................. 1
2
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SBOSA23F – MAY 2020 – REVISED JUNE 2023
5 Pin Configuration and Functions
OUT
1
V±
2
IN+
3
5
V+
4
IN±
Not to scale
Figure 5-1. TLV9151-Q1 DBV Package,
5-Pin SOT-23
(Top View)
Table 5-1. Pin Functions: TLV9151-Q1
PIN
NAME
TYPE(1)
NO.
IN+
3
IN–
OUT
DESCRIPTION
I
Noninverting input
4
I
Inverting input
1
O
Output
V+
5
—
Positive (highest) power supply
V–
2
—
Negative (lowest) power supply
(1)
I = input, O = output
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SBOSA23F – MAY 2020 – REVISED JUNE 2023
OUT1
1
8
V+
IN1±
2
7
OUT2
IN1+
3
6
IN2±
V±
4
5
IN2+
Not to scale
Figure 5-2. TLV9152-Q1 D, PW and DGK Package,
8-Pin SOIC, TSSOP and VSSOP
(Top View)
Table 5-2. Pin Functions: TLV9152-Q1
PIN
NAME
TYPE(1)
DESCRIPTION
IN1+
3
I
Noninverting input, channel 1
IN2+
5
I
Noninverting input, channel 2
IN1–
2
I
Inverting input, channel 1
IN2–
6
I
Inverting input, channel 2
OUT1
1
O
Output, channel 1
OUT2
7
O
Output, channel 2
V+
8
—
Positive (highest) power supply
V–
4
—
Negative (lowest) power supply
(1)
4
NO.
I = input, O = output
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SBOSA23F – MAY 2020 – REVISED JUNE 2023
OUT1
1
14
OUT4
IN1±
2
13
IN4±
IN1+
3
12
IN4+
V+
4
11
V±
IN2+
5
10
IN3+
IN2±
6
9
IN3±
OUT2
7
8
OUT3
Not to scale
Figure 5-3. TLV9154-Q1 D, DYY, and PW Package,
14-Pin SOIC, SOT-23, and TSSOP
(Top View)
Table 5-3. Pin Functions: TLV9154-Q1
PIN
NAME
TYPE(1)
NO.
DESCRIPTION
IN1+
3
I
Noninverting input, channel 1
IN1–
2
I
Inverting input, channel 1
IN2+
5
I
Noninverting input, channel 2
IN2–
6
I
Inverting input, channel 2
IN3+
10
I
Noninverting input, channel 3
IN3–
9
I
Inverting input, channel 3
IN4+
12
I
Noninverting input, channel 4
IN4–
13
I
Inverting input, channel 4
OUT1
1
O
Output, channel 1
OUT2
7
O
Output, channel 2
OUT3
8
O
Output, channel 3
OUT4
14
O
Output, channel 4
V+
4
—
Positive (highest) power supply
V–
11
—
Negative (lowest) power supply
(1)
I = input, O = output
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SBOSA23F – MAY 2020 – REVISED JUNE 2023
6 Specifications
6.1 Absolute Maximum Ratings
over operating ambient temperature range (unless otherwise noted) (1)
MIN
MAX
0
20
V
(V–) – 0.5
(V+) + 0.5
V
Supply voltage, VS = (V+) – (V–)
Common-mode voltage
(3)
Differential voltage (3)
Signal input pins
VS + 0.2
Current (3)
–10
Output short-circuit (2)
–55
Junction temperature, TJ
Storage temperature, Tstg
(2)
(3)
V
10
mA
150
°C
150
°C
150
°C
Continuous
Operating ambient temperature, TA
(1)
UNIT
–65
Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
Short-circuit to ground, one amplifier per package.
Input pins are diode-clamped to the power-supply rails. Input signals that may swing more than 0.5 V beyond the supply rails must be
current limited to 10 mA or less.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human body model (HBM), per AEC
Q100-002(1)
UNIT
±2000
Charged device model (CDM), per AEC Q100-011
V
±1000
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
MIN
VS
Supply voltage, (V+) – (V–)
VI
Input voltage range
TA
Specified ambient temperature
MAX
UNIT
2.7
16
(V–) – 0.1
(V+) + 0.1
V
V
–40
125
°C
6.4 Thermal Information for Single Channel
TLV9151-Q1
DBV
(SOT-23)
THERMAL METRIC (1)
UNIT
5 PINS
RθJA
Junction-to-ambient thermal resistance
187.4
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
86.2
°C/W
RθJB
Junction-to-board thermal resistance
54.6
°C/W
ψJT
Junction-to-top characterization parameter
27.8
°C/W
ψJB
Junction-to-board characterization parameter
54.3
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
6
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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SBOSA23F – MAY 2020 – REVISED JUNE 2023
6.5 Thermal Information for Dual Channel
TLV9152-Q1
THERMAL METRIC (1)
D
(SOIC)
DGK
(VSSOP)
PW
(TSSOP)
8 PINS
8 PINS
8 PINS
Unit
RθJA
Junction-to-ambient thermal resistance
132.6
176.5
185.1
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
73.4
68.1
74.0
°C/W
RθJB
Junction-to-board thermal resistance
76.1
98.2
115.7
°C/W
ψJT
Junction-to-top characterization parameter
24.0
12.0
12.3
°C/W
ψJB
Junction-to-board characterization parameter
75.4
96.7
114.0
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.6 Thermal Information for Quad Channel
TLV9154-Q1
THERMAL METRIC (1)
D
(SOIC)
DYY
(SOT-23)
PW
(TSSOP)
UNIT
14 PINS
14 PINS
14 PINS
RθJA
Junction-to-ambient thermal resistance
101.4
110.7
118.0
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
57.6
55.9
47.6
°C/W
RθJB
Junction-to-board thermal resistance
57.3
35.3
60.9
°C/W
ψJT
Junction-to-top characterization parameter
18.5
2.3
6.0
°C/W
ψJB
Junction-to-board characterization parameter
56.9
35.1
60.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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Product Folder Links: TLV9151-Q1 TLV9152-Q1 TLV9154-Q1
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6.7 Electrical Characteristics
For VS = (V+) – (V–) = 2.7 V to 16 V (±1.35 V to ±8 V) at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and
VO UT = VS / 2, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
±125
±895
UNIT
OFFSET VOLTAGE
VOS
Input offset voltage
dVOS/dT
Input offset voltage drift
PSRR
VCM = V–
TA = –40°C to 125°C
±925
TA = –40°C to 125°C
Input offset voltage
versus power supply
VCM = V–, VS = 4 V to 16 V
Channel separation
f = 0 Hz
VCM = V–, VS = 2.7 V to 16 V(2)
±0.3
TA = –40°C to 125°C
µV
µV/℃
±0.3
±1.5
±1
±10.6
5
μV/V
µV/V
INPUT BIAS CURRENT
IB
±10
Input bias current
IOS
TA = –40°C to 125°C(2)
pA
±1
±10
Input offset current
TA = –40°C to
125°C(2)
nA
pA
±1
nA
NOISE
1.8
μVPP
0.3
µVRMS
EN
Input voltage noise
f = 0.1 Hz to 10 Hz
eN
Input voltage noise
density
f = 1 kHz
10.8
f = 10 kHz
9.4
iN
Input current noise
f = 1 kHz
nV/√Hz
2
fA/√Hz
INPUT VOLTAGE RANGE
Common-mode voltage
range
VCM
(V–) – 0.1
VS = 16 V, (V–) – 0.1 V < VCM < (V+)
– 2 V (Main input pair)
CMRR
VS = 4 V, (V–) – 0.1 V < VCM < (V+) –
Common-mode rejection 2 V (Main input pair)
TA = –40°C to 125°C
ratio
VS = 2.7 V, (V–) – 0.1 V < VCM < (V+)
(2)
– 2 V (Main input pair)
(V+) + 0.1
99
130
82
100
75
95
V
dB
VS = 2.7 V to 16 V, (V+) – 1 V < VCM
< (V+) + 0.1 V (Aux input pair)
85
INPUT CAPACITANCE
ZID
Differential
ZICM
Common-mode
100 || 9
MΩ || pF
6 || 1
TΩ || pF
OPEN-LOOP GAIN
AOL
8
Open-loop voltage gain
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120
VS = 16 V, VCM = V–
(V–) + 0.1 V < VO < (V+) – 0.1 V
TA = –40°C to 125°C
VS = 4 V, VCM = V–
(V–) + 0.1 V < VO < (V+) – 0.1 V
TA = –40°C to 125°C
VS = 2.7 V, VCM = V–
(V–) + 0.1 V < VO < (V+) – 0.1 V(2)
TA = –40°C to 125°C
145
142
104
130
125
101
dB
120
118
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SBOSA23F – MAY 2020 – REVISED JUNE 2023
6.7 Electrical Characteristics (continued)
For VS = (V+) – (V–) = 2.7 V to 16 V (±1.35 V to ±8 V) at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and
VO UT = VS / 2, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
FREQUENCY RESPONSE
GBW
Gain-bandwidth product
SR
Slew rate
tS
Settling time
4.5
MHz
VS = 16 V, G = +1, CL = 20 pF
21
V/μs
To 0.01%, VS = 16 V, VSTEP = 10 V , G = +1, CL = 20 pF
2.5
To 0.01%, VS = 16 V, VSTEP = 2 V , G = +1, CL = 20 pF
1.5
To 0.1%, VS = 16 V, VSTEP = 10 V , G = +1, CL = 20 pF
2
To 0.1%, VS = 16 V, VSTEP = 2 V , G = +1, CL = 20 pF
THD+N
Phase margin
G = +1, RL = 10 kΩ
Overload recovery time
VIN × gain > VS
Total harmonic distortion
+ noise (1)
VS = 16 V, VO = 3 VRMS, G = 1, f = 1 kHz
μs
1
60
°
400
ns
0.00021%
OUTPUT
VS = 16 V, RL = no load
VS = 16 V, RL = 10 kΩ
Voltage output swing
from rail (positive and
negative)
VS = 16 V, RL = 2 kΩ
VS = 2.7 V, RL = no load
VS = 2.7 V, RL = 10 kΩ
VS = 2.7 V, RL = 2 kΩ
5
TA = –40°C to 125°C(2)
10
15
50
55
200
250
TA = –40°C to 125°C(2)
75
TA = –40°C to 125°C(2)
350
1
TA = –40°C to 125°C(2)
6
mV
10
5
TA = –40°C to 125°C(2)
12
18
25
TA = –40°C to 125°C(2)
40
60
ISC
Short-circuit current
±75
mA
CLOAD
Capacitive load drive
1000
pF
ZO
Open-loop output
impedance
f = 1 MHz, IO = 0 A
525
Ω
IO = 0 A
560
685
IO = 0 A, (TLV9151-Q1)
560
691
POWER SUPPLY
IQ
Quiescent current per
amplifier
IO = 0 A
IO = 0 A, (TLV9151-Q1)
(1)
(2)
TA = –40°C to 125°C
750
µA
769
Third-order filter; bandwidth = 80 kHz at –3 dB.
Specified by characterization only.
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6.8 Typical Characteristics
at TA = 25°C, VS = ±8 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 10 pF (unless otherwise noted)
50
33
30
27
40
Population (%)
Population (%)
24
21
18
15
12
30
20
9
10
6
D001
Offset Voltage (µV)
Distribution from 15462 amplifiers, TA = 25°C
400
700
300
500
200
Offset Voltage (µV)
900
300
100
-100
-300
0.8
0.7
0.6
0.5
100
0
-100
-200
-300
-700
-900
-40
-20
0
20
40
60
80
Temperature (°C)
100
120
-400
-40
140
-20
0
20
40
60
80
Temperature (°C)
D004
VCM = V+
120
140
D003
Figure 6-4. Offset Voltage vs Temperature
800
600
600
400
400
Offset Voltage (µV)
800
200
0
-200
200
0
-200
-400
-400
-600
-600
-800
-8
100
VCM = V–
Figure 6-3. Offset Voltage vs Temperature
Offset Voltage (µV)
0.4
0.3
Figure 6-2. Offset Voltage Drift Distribution
-500
-800
-6
-4
-2
0
VCM
2
4
6
8
4
4.5
5
5.5
D005
TA = 25°C
Figure 6-5. Offset Voltage vs Common-Mode Voltage
10
D002
Offset Voltage Drift (µV/C)
Distribution from 60 amplifiers
Figure 6-1. Offset Voltage Production Distribution
Offset Voltage (µV)
0.2
600
480
360
240
120
0
-120
-240
-360
-480
-600
0.1
0
0
0
3
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VCM
6.5
7
7.5
8
D005
TA = 25°C
Figure 6-6. Offset Voltage vs Common-Mode Voltage (Transition
Region)
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SBOSA23F – MAY 2020 – REVISED JUNE 2023
6.8 Typical Characteristics (continued)
800
800
600
600
400
400
Offset Voltage (µV)
200
0
-200
200
0
-200
-400
-400
-600
-600
-800
-8
-6
-4
-2
0
VCM
2
4
6
-800
-8
8
-6
-4
-2
D006
TA = 125°C
4
6
8
D007
Figure 6-8. Offset Voltage vs Common-Mode Voltage
600
100
500
90
400
80
200
Gain (dB) 175
Phase ( )
150
300
70
125
200
60
100
50
75
40
50
30
25
-200
20
0
-300
10
-25
-400
0
-50
-500
-10
-75
-600
-20
100
Gain (dB)
Offset Voltage (µV)
2
TA = –40°C
Figure 6-7. Offset Voltage vs Common-Mode Voltage
100
0
-100
2
4
6
8
10
12
Supply Voltage (V)
14
16
18
D008
1k
10k
100k
Frequency (Hz)
.
-100
10M
1M
C002
CL = 20 pF
Figure 6-9. Offset Voltage vs Power Supply
Figure 6-10. Open-Loop Gain and Phase vs Frequency
80
6
60
50
Input Bias and Offset Current (pA)
G= 1
G=1
G = 10
G = 100
G = 1000
70
Closed-Loop Gain (dB)
0
VCM
Phase ( )
Offset Voltage (µV)
at TA = 25°C, VS = ±8 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 10 pF (unless otherwise noted)
40
30
20
10
0
-10
-20
100
1k
10k
100k
Frequency (Hz)
1M
10M
Figure 6-11. Closed-Loop Gain vs Frequency
C001
4.5
3
1.5
0
-1.5
-3
-4.5
IB
IB+
IOS
-6
-7.5
-8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4
Common Mode Voltage (V)
5
6
7
8
D010
Figure 6-12. Input Bias Current vs Common-Mode Voltage
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±8 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 10 pF (unless otherwise noted)
V+
IB
IB+
IOS
125
100
75
Output Voltage (V)
Input Bias and Offset Current (pA)
150
50
25
0
-25
V+
1V
V+
2V
V+
3V
V+
4V
V+
5V
V+
6V
V+
7V
-50
V+
8V
-75
V+
9V
-100
-40
V+
-20
0
20
40
60
80
Temperature (°C)
100
120
10 V
0
140
10
20
D011
Figure 6-13. Input Bias Current vs Temperature
30
40
50
60
70
Output Current (mA)
100
D012
CMRR
PSRR+
PSRR
120
CMRR and PSRR (dB)
V +6V
V +5V
V +4V
V +3V
V +2V
V +1V
105
90
75
60
45
30
15
0
100
V
0
10
20
30
40
50
60
70
Output Current (mA)
80
90
100
1k
10k
100k
Frequency (Hz)
D012
C003
170
135
Power Supply Rejection Ratio (dB)
130
125
120
115
PMOS (VCM
NMOS (VCM
V+
V+
1.5 V)
1.5 V)
105
100
95
90
85
-40
10M
Figure 6-16. CMRR and PSRR vs Frequency
Figure 6-15. Output Voltage Swing vs Output Current (Sinking)
110
1M
.
.
Common-Mode Rejection Ratio (dB)
90
135
-40°C
25°C
125°C
V +7V
-20
0
20
40
60
80
Temperature (°C)
100
120
140
D015
165
160
155
150
145
140
-40
-20
0
20
40
60
80
Temperature (°C)
f = 0 Hz
Figure 6-17. CMRR vs Temperature (dB)
12
80
Figure 6-14. Output Voltage Swing vs Output Current (Sourcing)
V +8V
Output Voltage (V)
-40°C
25°C
125°C
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100
120
140
D016
f = 0 Hz
Figure 6-18. PSRR vs Temperature (dB)
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6.8 Typical Characteristics (continued)
Input Voltage Noise Spectral Density (nV/ Hz)
at TA = 25°C, VS = ±8 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 10 pF (unless otherwise noted)
1
0.8
Amplitude (uV)
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
200
100
10
1
1
Time (1s/div)
10
100
1k
Frequency (Hz)
C019
-32
C017
-20
RL = 10 k
RL = 2 k
RL = 604
RL = 128
-40
-48
-30
-40
-50
THD+N (dB)
-56
THD+N (dB)
100k
Figure 6-20. Input Voltage Noise Spectral Density vs Frequency
Figure 6-19. 0.1-Hz to 10-Hz Noise
-64
-72
-80
-60
-70
-80
-88
-90
-96
-100
-104
-110
100
1k
Frequency (Hz)
RL = 10 k
RL = 2 k
RL = 604
RL = 128
-120
1m
-112
10k
10m
C012
700
570
675
560
650
Quiescent current (µA)
580
550
540
530
520
510
575
550
525
490
475
480
8
10
12
Supply Voltage (V)
14
C023
600
500
6
10
625
500
4
1
Figure 6-22. THD+N vs Output Amplitude
Figure 6-21. THD+N Ratio vs Frequency
2
100m
Amplitude (Vrms)
BW = 80 kHz, f = 1 kHz
BW = 80 kHz, VOUT = 1 VRMS
Quiescent current (µA)
10k
16
18
D021
450
-40
-20
0
20
40
60
80
Temperature (°C)
VCM = V–
Figure 6-23. Quiescent Current vs Supply Voltage
100
120
140
D022
.
Figure 6-24. Quiescent Current vs Temperature
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±8 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 10 pF (unless otherwise noted)
140
700
135
130
125
120
115
-40
-20
0
20
40
60
80
Temperature (°C)
100
120
650
Open-loop output impedance (ohms)
Open Loop Voltage Gain (dB)
VS = 4 V
VS = 16 V
600
550
500
450
400
350
300
250
200
150
100
140
D023
Figure 6-25. Open-Loop Voltage Gain vs Temperature (dB)
1k
10k
100k
Frequency (Hz)
1M
10M
C013
Figure 6-26. Open-Loop Output Impedance vs Frequency
80
60
70
50
Overshoot (%)
Overshoot (%)
60
40
30
20
40
30
20
RISO = 0 , Positive Overshoot
RISO = 0 , Negative Overshoot
RISO = 50 , Positive Overshoot
RISO = 50 , Negative Overshoot
10
50
RISO = 0 , Positive Overshoot
RISO = 0 , Negative Overshoot
RISO = 50 , Positive Overshoot
RISO = 50 , Negative Overshoot
10
0
0
0
500 1000 1500 2000 2500 3000 3500 4000 4500 5000
Cap Load (pF)
C007
0
G = –1, 10-mV output step
Figure 6-27. Small-Signal Overshoot vs Capacitive Load
500 1000 1500 2000 2500 3000 3500 4000 4500 5000
Cap Load (pF)
C008
G = 1, 10-mV output step
Figure 6-28. Small-Signal Overshoot vs Capacitive Load
60
Input
Output
Amplitude (2V/div)
Phase Margin (Degree)
50
40
30
20
10
0
500 1000 1500 2000 2500 3000 3500 4000 4500 5000
Cap Load (pF)
C009
Figure 6-29. Phase Margin vs Capacitive Load
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VIN = ±8 V; VS = VOUT = ±8 V
.
14
Time (20us/div)
Figure 6-30. No Phase Reversal
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±8 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 10 pF (unless otherwise noted)
Voltage (5V/div)
Input
Output
Voltage (5V/div)
Input
Output
Time (100ns/div)
Time (100ns/div)
C018
C018
G = –10
G = –10
Figure 6-31. Positive Overload Recovery
Figure 6-32. Negative Overload Recovery
Amplitude (5mV/div)
Amplitude (5mV/div)
Input
Output
Input
Output
Time (1µs/div)
Time (300ns/div)
C011
C010
CL = 20 pF, G = -1, 20-mV step response
CL = 20 pF, G = 1, 20-mV step response
Figure 6-34. Small-Signal Step Response
Figure 6-33. Small-Signal Step Response, Rising
Amplitude (2V/div)
Amplitude (2V/div)
Input
Output
Input
Output
Time (300ns/div)
Time (300ns/div)
C005
CL = 20 pF, G = 1
Figure 6-35. Large-Signal Step Response (Rising)
C005
CL = 20 pF, G = 1
Figure 6-36. Large-Signal Step Response (Falling)
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±8 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 10 pF (unless otherwise noted)
Large Signal Step Response (2V/div)
100
80
60
Output Current (mA)
Input
Output
40
20
Sourcing
Sinking
0
-20
-40
-60
-80
-100
-40
Time (2µs/div)
-20
0
C021
20
40
60
80
Temperature (°C)
140
D014
Figure 6-38. Short-Circuit Current vs Temperature
Figure 6-37. Large-Signal Step Response
-50
20
VS = 15 V
VS = 2.7 V
18
-60
16
Channel Seperation (dB)
Maximum Output Swing (V)
120
.
CL = 20 pF, G = –1
14
12
10
8
6
4
-70
-80
-90
-100
-110
-120
2
0
1k
100
10k
100k
Frequency (Hz)
1M
-130
100
10M
1k
C020
Figure 6-39. Maximum Output Voltage vs Frequency
10k
100k
Frequency (Hz)
1M
10M
C014
Figure 6-40. Channel Separation vs Frequency
110
100
Gain(dB)
90
80
70
60
50
40
1M
10M
100M
Frequency (Hz)
1G
C004
Figure 6-41. EMIRR (Electromagnetic Interference Rejection Ratio) at Inputs vs Frequency
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7 Detailed Description
7.1 Overview
The TLV915x-Q1 family (TLV9151-Q1, TLV9152-Q1, and TLV9154-Q1) is a family of 16-V general purpose
operational amplifiers.
These devices offer excellent DC precision and AC performance, including rail-to-rail input/output, low offset
(±125 µV, typ), low offset drift (±0.3 µV/°C, typ), and 4.5-MHz bandwidth.
Wide differential and common-mode input-voltage range, high output current (±75 mA), high slew rate (21
V/µs), and low power operation (560 µA, typ) make the TLV915x-Q1 a robust, high-speed, high-performance
operational amplifier for industrial applications.
7.2 Functional Block Diagram
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7.3 Feature Description
7.3.1 EMI Rejection
The TLV915x-Q1 uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI from
sources such as wireless communications and densely-populated boards with a mix of analog signal chain and
digital components. EMI immunity can be improved with circuit design techniques; the TLV915x-Q1 benefits
from these design improvements. Texas Instruments has developed the ability to accurately measure and
quantify the immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to
6 GHz. Figure 7-1 shows the results of this testing on the TLV915x-Q1. Table 7-1 provides the EMIRR IN+
values for the TLV915x-Q1 at particular frequencies commonly encountered in real-world applications. The EMI
Rejection Ratio of Operational Amplifiers application report contains detailed information on the topic of EMIRR
performance as it relates to op amps and is available for download from www.ti.com.
100
90
EMIRR (dB)
80
70
60
50
40
30
1M
10M
100M
Frequency (Hz)
1G
C004
Figure 7-1. EMIRR Testing
Table 7-1. TLV915x-Q1 EMIRR IN+ for Frequencies of Interest
FREQUENCY
EMIRR IN+
400 MHz
Mobile radio, mobile satellite, space operation, weather, radar, ultra-high frequency (UHF)
applications
59.5 dB
900 MHz
Global system for mobile communications (GSM) applications, radio communication, navigation,
GPS (to 1.6 GHz), GSM, aeronautical mobile, UHF applications
68.9 dB
1.8 GHz
GSM applications, mobile personal communications, broadband, satellite, L-band (1 GHz to 2 GHz)
77.8 dB
Bluetooth®,
2.4 GHz
802.11b, 802.11g, 802.11n,
mobile personal communications, industrial, scientific and
medical (ISM) radio band, amateur radio and satellite, S-band (2 GHz to 4 GHz)
78.0 dB
3.6 GHz
Radiolocation, aero communication and navigation, satellite, mobile, S-band
88.8 dB
802.11a, 802.11n, aero communication and navigation, mobile communication, space and satellite
operation, C-band (4 GHz to 8 GHz)
87.6 dB
5 GHz
18
APPLICATION OR ALLOCATION
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7.3.2 Thermal Protection
VOUT
The internal power dissipation of any amplifier causes its internal (junction) temperature to rise. This
phenomenon is called self heating. The absolute maximum junction temperature of the TLV915x-Q1 is 150°C.
Exceeding this temperature causes damage to the device. The TLV915x-Q1 has a thermal protection feature
that reduces damage from self heating. The protection works by monitoring the temperature of the device and
turning off the op amp output drive for temperatures above 170°C. Figure 7-2 shows an application example for
the TLV9151-Q1 that has significant self heating because of its power dissipation (0.81 W). Thermal calculations
indicate that for an ambient temperature of 65°C, the device junction temperature will reach 177°C. The actual
device, however, turns off the output drive to recover towards a safe junction temperature. Figure 7-2 shows how
the circuit behaves during thermal protection. During normal operation, the device acts as a buffer so the output
is 3 V. When self heating causes the device junction temperature to increase above the internal limit, the thermal
protection forces the output to a high-impedance state and the output is pulled to ground through resistor RL.
If the condition that caused excessive power dissipation is not removed, the amplifier will oscillate between a
shutdown and enabled state until the output fault is corrected.
Normal
Operation
3V
TA = 100°C
PD = 0.39W
JA = 138.7°C/W
0V
TJ = 138.7°C/W × 0.39W + 100°C
TJ = 154.1°C (expected)
16 V
Output
High-Z
150°C
TLV9151
+
–
+
RL
3V
100 –
VIN
3V
140ºC
Temperature
IOUT = 30 mA
Figure 7-2. Thermal Protection
7.3.3 Capacitive Load and Stability
55
33
50
30
45
27
40
24
Overshoot (%)
Overshoot (%)
The TLV915x-Q1 features a resistive output stage capable of driving moderate capacitive loads, and by
leveraging an isolation resistor, the device can easily be configured to drive large capacitive loads. Increasing
the gain enhances the ability of the amplifier to drive greater capacitive loads; see Figure 7-3 and Figure 7-4.
The particular op amp circuit configuration, layout, gain, and output loading are some of the factors to consider
when establishing whether an amplifier will be stable in operation.
35
30
25
21
18
15
12
20
RISO = 0 :, Positive Overshoot
RISO = 0 :, Negative Overshoot
RISO = 50 :, Positive Overshoot
RISO = 50 :, Negative Overshoot
15
10
RISO = 0 :, Positive Overshoot
RISO = 0 :, Negative Overshoot
RISO = 50 :, Positive Overshoot
RISO = 50 :, Negative Overshoot
9
6
3
5
0
40
80
120
160 200 240
Cap Load (pF)
280
320
360
0
40
80
120
C008
Figure 7-3. Small-Signal Overshoot vs Capacitive
Load (10-mV Output Step, G = 1)
160 200 240
Cap Load (pF)
280
320
360
C007
Figure 7-4. Small-Signal Overshoot vs Capacitive
Load (10-mV Output Step, G = –1)
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For additional drive capability in unity-gain configurations, improve capacitive load drive by inserting a small
resistor, RISO, in series with the output, as shown in Figure 7-5. This resistor significantly reduces ringing
and maintains DC performance for purely capacitive loads. However, if a resistive load is in parallel with the
capacitive load, then a voltage divider is created, thus introducing a gain error at the output and slightly reducing
the output swing. The error introduced is proportional to the ratio RISO / RL, and is generally negligible at low
output levels. A high capacitive load drive makes the TLV915x-Q1 well suited for applications such as reference
buffers, MOSFET gate drives, and cable-shield drives. The circuit shown in Figure 7-5 uses an isolation resistor,
RISO, to stabilize the output of an op amp. RISO modifies the open-loop gain of the system for increased phase
margin.
+Vs
Vout
Riso
+
Vin
+
±
Cload
-Vs
Figure 7-5. Extending Capacitive Load Drive With the TLV9151-Q1
7.3.4 Common-Mode Voltage Range
The TLV915x-Q1 is a 16-V, rail-to-rail input operational amplifier with an input common-mode range that extends
200 mV beyond either supply rail. This wide range is achieved with paralleled complementary N-channel and
P-channel differential input pairs, as shown in Figure 7-6. The N-channel pair is active for input voltages close to
the positive rail, typically (V+) – 1 V to 100 mV above the positive supply. The P-channel pair is active for inputs
from 100 mV below the negative supply to approximately (V+) – 2 V. There is a small transition region, typically
(V+) – 2 V to (V+) – 1 V in which both input pairs are on. This transition region can vary modestly with process
variation, and within this region PSRR, CMRR, offset voltage, offset drift, noise, and THD performance may be
degraded compared to operation outside this region.
Figure 6-5 shows this transition region for a typical device in terms of input voltage offset in more detail.
For more information on common-mode voltage range and PMOS/NMOS pair interaction, see Op Amps With
Complementary-Pair Input Stages application note.
V+
INPMOS
PMOS
IN+
NMOS
NMOS
V-
Figure 7-6. Rail-to-Rail Input Stage
20
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7.3.5 Phase Reversal Protection
The TLV915x-Q1 family has internal phase-reversal protection. Many op amps exhibit a phase reversal when the
input is driven beyond its linear common-mode range. This condition is most often encountered in non-inverting
circuits when the input is driven beyond the specified common-mode voltage range, causing the output to
reverse into the opposite rail. The TLV915x-Q1 is a rail-to-rail input op amp; therefore, the common-mode range
can extend up to the rails. Input signals beyond the rails do not cause phase reversal; instead, the output limits
into the appropriate rail. This performance is shown in Figure 7-7. For more information on phase reversal, see
Op Amps With Complementary-Pair Input Stages application note.
Amplitude (2V/div)
Input
Output
Time (20us/div)
C016
Figure 7-7. No Phase Reversal
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7.3.6 Electrical Overstress
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress
(EOS). These questions tend to focus on the device inputs, but may involve the supply voltage pins or even
the output pin. Each of these different pin functions have electrical stress limits determined by the voltage
breakdown characteristics of the particular semiconductor fabrication process and specific circuits connected to
the pin. Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them
from accidental ESD events both before and during product assembly.
Having a good understanding of this basic ESD circuitry and its relevance to an electrical overstress event
is helpful. Figure 7-8 shows an illustration of the ESD circuits contained in the TLV915x-Q1 (indicated by the
dashed line area). The ESD protection circuitry involves several current-steering diodes connected from the
input and output pins and routed back to the internal power-supply lines, where the diodes meet at an absorption
device or the power-supply ESD cell, internal to the operational amplifier. This protection circuitry is intended to
remain inactive during normal circuit operation.
TVS
+
–
RF
+VS
VDD
R1
RS
IN–
100
IN+
100
TLV915x
–
+
Power Supply
ESD Cell
ID
VIN
RL
+
–
VSS
+
–
–VS
TVS
Figure 7-8. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application
An ESD event is very short in duration and very high voltage (for example; 1 kV, 100 ns), whereas an EOS event
is long duration and lower voltage (for example; 50 V, 100 ms). The ESD diodes are designed for out-of-circuit
ESD protection (that is, during assembly, test, and storage of the device before being soldered to the PCB).
During an ESD event, the ESD signal is passed through the ESD steering diodes to an absorption circuit
(labeled ESD power-supply circuit). The ESD absorption circuit clamps the supplies to a safe level.
Although this behavior is necessary for out-of-circuit protection, excessive current and damage is caused if
activated in-circuit. A transient voltage suppressors (TVS) can be used to prevent against damage caused by
turning on the ESD absorption circuit during an in-circuit ESD event. Using the appropriate current limiting
resistors and TVS diodes allows for the use of device ESD diodes to protect against EOS events.
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7.3.7 Overload Recovery
Overload recovery is defined as the time required for the op amp output to recover from a saturated state to
a linear state. The output devices of the op amp enter a saturation region when the output voltage exceeds
the rated operating voltage, either due to the high input voltage or the high gain. After the device enters the
saturation region, the charge carriers in the output devices require time to return back to the linear state. After
the charge carriers return back to the linear state, the device begins to slew at the specified slew rate. Thus, the
propagation delay in case of an overload condition is the sum of the overload recovery time and the slew time.
The overload recovery time for the TLV915x-Q1 is approximately 400 ns.
7.3.8 Typical Specifications and Distributions
Designers often have questions about a typical specification of an amplifier in order to design a more robust
circuit. Due to natural variation in process technology and manufacturing procedures, every specification of an
amplifier will exhibit some amount of deviation from the ideal value, like an amplifier's input offset voltage. These
deviations often follow Gaussian (bell curve), or normal distributions, and circuit designers can leverage this
information to guardband their system, even when there is not a minimum or maximum specification in Section
6.7.
0.00002% 0.00312% 0.13185%
1
-61
1
-51
2.145% 13.59% 34.13% 34.13% 13.59% 2.145%
1
1
-41
-31
1
-21
1
-1
1
1
+1
0.13185% 0.00312% 0.00002%
1
1
1
1
+21 +31 +41 +51 +61
Figure 7-9. Ideal Gaussian Distribution
Figure 7-9 shows an example distribution, where µ, or mu, is the mean of the distribution, and where σ,
or sigma, is the standard deviation of a system. For a specification that exhibits this kind of distribution,
approximately two-thirds (68.26%) of all units can be expected to have a value within one standard deviation, or
one sigma, of the mean (from µ – σ to µ + σ).
Depending on the specification, values listed in the typical column of Section 6.7 are represented in different
ways. As a general rule, if a specification naturally has a nonzero mean (for example, like gain bandwidth), then
the typical value is equal to the mean (µ). However, if a specification naturally has a mean near zero (like input
offset voltage), then the typical value is equal to the mean plus one standard deviation (µ + σ) in order to most
accurately represent the typical value.
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This chart can be used to calculate approximate probability of a specification in a unit; for example, for TLV915xQ1 , the typical input voltage offset is 125 µV, so 68.2% of all TLV915x-Q1 devices are expected to have an
offset from –125 µV to 125 µV. At 4 σ (±500 µV), 99.9937% of the distribution has an offset voltage less than
±500 µV, which means 0.0063% of the population is outside of these limits, which corresponds to about 1 in
15,873 units.
Specifications with a value in the minimum or maximum column are assured by TI, and units outside these limits
will be removed from production material. For example, the TLV915x-Q1 family has a maximum offset voltage
of 675 µV at 25°C, and even though this corresponds to about 5 σ (≈1 in 1.7 million units), which is extremely
unlikely, TI assures that any unit with larger offset than 895 µV will be removed from production material.
For specifications with no value in the minimum or maximum column, consider selecting a sigma value of
sufficient guardband for the application, and design worst-case conditions using this value. For example, the
6-σ value corresponds to about 1 in 500 million units, which is an extremely unlikely chance, and could be an
option as a wide guardband to design a system around. In this case, the TLV915x-Q1 family does not have
a maximum or minimum for offset voltage drift, but based on Figure 6-2 and the typical value of 0.3 µV/°C in
Section 6.7, it can be calculated that the 6-σ value for offset voltage drift is about 1.8 µV/°C. When designing for
worst-case system conditions, this value can be used to estimate the worst possible offset across temperature
without having an actual minimum or maximum value.
However, process variation and adjustments over time can shift typical means and standard deviations, and
unless there is a value in the minimum or maximum specification column, TI cannot assure the performance of a
device. This information should be used only to estimate the performance of a device.
7.3.9 Packages With an Exposed Thermal Pad
The TLV915x-Q1 family is available in packages such as the WSON-8 (DSG) and WQFN-16 (RTE) which
feature an exposed thermal pad. Inside the package, the die is attached to this thermal pad using an electrically
conductive compound. For this reason, when using a package with an exposed thermal pad, the thermal pad
must either be connected to V– or left floating. Attaching the thermal pad to a potential other than V– is not
allowed, and performance of the device is not assured when doing so.
7.4 Device Functional Modes
The TLV915x-Q1 has a single functional mode and is operational when the power-supply voltage is greater than
2.7 V (±1.35 V). The maximum power supply voltage for the TLV915x-Q1 is 16 V (±8 V).
The TLV915x-Q1 S devices feature a shutdown pin, which can be used to place the op amp into a low-power
mode.
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and
TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
8.1 Application Information
The TLV915x-Q1 family offers excellent DC precision and DC performance. These devices operate up to 16-V
supply rails and offer true rail-to-rail input/output, low offset voltage and offset voltage drift, as well as 4.5-MHz
bandwidth and high output drive. These features make the TLV915x-Q1 a robust, high-performance operational
amplifier for high-voltage industrial applications.
8.2 Typical Applications
8.2.1 Low-Side Current Measurement
Figure 8-1 shows the TLV9151-Q1 configured in a low-side current sensing application. For a full analysis of
the circuit shown in Figure 8-1 including theory, calculations, simulations, and measured data, see TI Precision
Design TIPD129, 0-A to 1-A Single-Supply Low-Side Current-Sensing Solution.
VCC
12 V
LOAD
+
TLV9151
VOUT
–
ILOAD
RSHUNT
100 m
LM7705
RF
360 k
RG
7.5 k
Figure 8-1. TLV9151-Q1 in a Low-Side, Current-Sensing Application
8.2.1.1 Design Requirements
The design requirements for this design are:
•
•
•
Load current: 0 A to 1 A
Output voltage: 4.9 V
Maximum shunt voltage: 100 mV
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8.2.1.2 Detailed Design Procedure
The transfer function of the circuit in Figure 8-1 is given in Equation 1.
VOUT = ILOAD × RSHUNT × Gain
(1)
The load current (ILOAD) produces a voltage drop across the shunt resistor (RSHUNT). The load current is set
from 0 A to 1 A. To keep the shunt voltage below 100 mV at maximum load current, the largest shunt resistor is
defined using Equation 2.
V
RSHUNT = ISHUNT_MAX = 100 mV
1 A = 100 mΩ
(2)
LOAD_MAX
Using Equation 2, RSHUNT is calculated to be 100 mΩ. The voltage drop produced by ILOAD and RSHUNT is
amplified by the TLV9151-Q1 to produce an output voltage of 0 V to 4.9 V. The gain needed by the TLV9151-Q1
to produce the necessary output voltage is calculated using Equation 3.
Gain =
VOUT_MAX − VOUT_MIN
VIN_MAX − VIN_MIN
(3)
Using Equation 3, the required gain is calculated to be 49 V/V, which is set with resistors RF and RG. Equation 4
is used to size the resistors, RF and RG, to set the gain of the TLV9151-Q1 to 49 V/V.
Gain = 1 +
RF
RG
(4)
Choosing R F as 360 kΩ, R G is calculated to be 7.5 kΩ. R F and R G were chosen as 360 kΩ and 7.5 kΩ because
they are standard value resistors that create a 49:1 ratio. Other resistors that create a 49:1 ratio can also be
used. Figure 8-2 shows the measured transfer function of the circuit shown in Figure 8-1.
8.2.1.3 Application Curves
5
Output (V)
4
3
2
1
0
0
0.1
0.2
0.3
0.4
0.5 0.6
ILOAD (A)
0.7
0.8
0.9
1
Figure 8-2. Low-Side, Current-Sense, Transfer Function
8.3 Power Supply Recommendations
The TLV915x-Q1 is specified for operation from 2.7 V to 16 V (±1.35 V to ±8 V); many specifications apply from
–40°C to 125°C. Parameters that can exhibit significant variance with regard to operating voltage or temperature
are presented in Section 6.8.
CAUTION
Supply voltages larger than 16 V can permanently damage the device; see Section 6.1.
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Place 0.1-µF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or
high-impedance power supplies. For more detailed information on bypass capacitor placement, refer to Section
8.4.
8.4 Layout
8.4.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
•
•
•
•
•
•
•
•
Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp itself.
Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources local to
the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for singlesupply applications.
Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds paying attention to the flow of the ground current.
In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as
opposed to in parallel with the noisy trace.
Place the external components as close to the device as possible. As shown in Figure 8-4, keeping RF and
RG close to the inverting input minimizes parasitic capacitance.
Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
Cleaning the PCB following board assembly is recommended for best performance.
Any precision integrated circuit may experience performance shifts due to moisture ingress into the plastic
package. Following any aqueous PCB cleaning process, baking the PCB assembly is recommended to
remove moisture introduced into the device packaging during the cleaning process. A low temperature, post
cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
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8.4.2 Layout Example
+
VIN
VOUT
RG
RF
Figure 8-3. Schematic Representation
Run the input traces
as far away from
the supply lines
as possible
Place components close
to device and to each
other to reduce parasitic
errors
VS+
RF
NC
NC
Use a low-ESR,
ceramic bypass
capacitor
RG
GND
±IN
V+
VIN
+IN
OUTPUT
V±
NC
GND
VS±
GND
VOUT
Ground (GND) plane on another layer
Use low-ESR,
ceramic bypass
capacitor
Figure 8-4. Operational Amplifier Board Layout for Noninverting Configuration
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9 Device and Documentation Support
9.1 Device Support
9.1.1 Development Support
9.1.1.1 TINA-TI™ (Free Software Download)
TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI is a
free, fully-functional version of the TINA software, preloaded with a library of macro models in addition to a range
of both passive and active models. TINA-TI provides all the conventional dc, transient, and frequency domain
analysis of SPICE, as well as additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing
capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select
input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool.
Note
These files require that either the TINA software (from DesignSoft™) or TINA-TI software be installed.
Download the free TINA-TI software from the TINA-TI folder.
9.1.1.2 TI Precision Designs
The TLV915x-Q1 is featured in several TI Precision Designs, available online at http://www.ti.com/ww/en/analog/
precision-designs/. TI Precision Designs are analog solutions created by TI’s precision analog applications
experts and offer the theory of operation, component selection, simulation, complete PCB schematic and layout,
bill of materials, and measured performance of many useful circuits.
9.2 Documentation Support
9.2.1 Related Documentation
For related documentation, see the following:
•
•
•
•
•
Texas Instruments, Analog Engineer's Circuit Cookbook: Amplifiers e-book
Texas Instruments, AN31 amplifier circuit collection application note
Texas Instruments, 0-A to 1-A Single-Supply Low-Side Current-Sensing Solution TI Precision Design
Texas Instruments, The EMI Rejection Ratio of Operational Amplifiers application note
Texas Instruments, Op Amps With Complementary-Pair Input Stages analog design journal
9.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
9.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
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Trademarks
TINA-TI™ is a trademark of Texas Instruments, Inc and DesignSoft, Inc.
TINA™ and DesignSoft™ are trademarks of DesignSoft, Inc.
TI E2E™ is a trademark of Texas Instruments.
Bluetooth® is a registered trademark of Bluetooth SIG, Inc.
All trademarks are the property of their respective owners.
9.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
9.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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28-Jun-2023
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TLV9151QDBVRQ1
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
2JKF
Samples
TLV9152QDGKRQ1
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
27XT
Samples
TLV9152QDRQ1
ACTIVE
SOIC
D
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
T9152Q
Samples
TLV9152QPWRQ1
ACTIVE
TSSOP
PW
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TL9152
Samples
TLV9154QDRQ1
ACTIVE
SOIC
D
14
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TL9154QD
Samples
TLV9154QDYYRQ1
ACTIVE
SOT-23-THIN
DYY
14
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TLV9154Q
Samples
TLV9154QPWRQ1
ACTIVE
TSSOP
PW
14
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
T9154Q
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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