TLV9162QDRQ1

TLV9161-Q1, TLV9162-Q1, TLV9164-Q1 SBOSAD7 – APRIL 2023 TLV916x-Q1 Automotive 16-V, 11-MHz, Rail-to-Rail Input or Output, Low Offset Voltage, Low Noise Automotive Op Amp 1 Features 3 Description • The TLV916x-Q1 family (TLV9161-Q1, TLV9162-Q1, and TLV9164-Q1) is a family of 16-V, general-purpose automotive operational amplifiers. These devices offer exceptional DC precision and AC performance, including rail-to-rail input or output, low offset (±210 µV, typical), low-offset drift (±0.25 µV/°C, typical), and low noise (6.8 nV/√Hz at 1 kHz, 4.2 nV/√Hz at 10 kHz). • • • • • • • • • • • AEC-Q100 qualified for automotive applications – Temperature grade 1: –40°C to +125°C, TA – Device HBM ESD classification level 3A (≥2500 V) – Device CDM ESD classification level C3 (≥1500 V) Low offset voltage: ±210 µV Low offset voltage drift: ±0.25 µV/°C Low noise: 6.8 nV/√Hz at 1 kHz, 4.2 nV/√Hz broadband High common-mode rejection: 110 dB Low bias current: ±10 pA Rail-to-rail input and output Wide bandwidth: 11-MHz GBW, unity-gain stable High slew rate: 33 V/µs Low quiescent current: 2.4 mA per amplifier Wide supply: ±1.35 V to ±8 V, 2.7 V to 16 V Robust EMIRR performance 2 Applications • • • • • • • • • Features such as wide differential input voltage range, high short-circuit current (±73 mA), and high slew rate (33 V/µs) make the TLV916x-Q1 a flexible, robust, and high-performance op amp for automotive applications. The TLV916x-Q1 family of op amps is available in standard packages and is specified from –40°C to 125°C. Package Information PART Optimized for AEC-Q100 grade 1 applications Infotainment and cluster Passive safety Body electronics and lighting HEV/EV inverter and motor control On-board (OBC) and wireless charger Powertrain current sensor Advanced driver assistance systems (ADAS) High-side and low-side current sensing NUMBER(1) TLV9161-Q1 TLV9162-Q1 TLV9164-Q1 (1) PACKAGE BODY SIZE (NOM) DBV (SOT-23, 5) 2.90 mm × 1.60 mm DCK (SC70, 5) 2.00 mm × 1.25 mm D (SOIC, 8) 4.90 mm × 3.90 mm DGK (VSSOP, 8) 3.00 mm × 3.00 mm D (SOIC, 14) 8.65 mm × 3.90 mm PW (TSSOP, 14) 5.00 mm × 4.40 mm For all available packages, see the orderable addendum at the end of the data sheet. TLV916x + Vshunt System Load Rshunt MCU - + - + Vo - Iload Vbus + – Vbus Iload Vshunt - Rshunt + – GND TLV916x + GND + - System Load MCU + Vo - GND GND Low-Side Current Sense GND GND High-Side Current Sense TLV916x-Q1 in Current-Sensing Applications An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TLV9161-Q1, TLV9162-Q1, TLV9164-Q1 www.ti.com SBOSAD7 – APRIL 2023 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Pin Configuration and Functions...................................3 6 Specifications.................................................................. 6 6.1 Absolute Maximum Ratings........................................ 6 6.2 ESD Ratings............................................................... 6 6.3 Recommended Operating Conditions.........................6 6.4 Thermal Information for Single Channel..................... 7 6.5 Thermal Information for Dual Channel........................7 6.6 Thermal Information for Quad Channel...................... 7 6.7 Electrical Characteristics.............................................8 6.8 Typical Characteristics.............................................. 10 7 Detailed Description......................................................17 7.1 Overview................................................................... 17 7.2 Functional Block Diagram......................................... 17 7.3 Feature Description...................................................18 7.4 Device Functional Modes..........................................25 8 Application and Implementation.................................. 26 8.1 Application Information............................................. 26 8.2 Typical Applications.................................................. 26 8.3 Power Supply Recommendations.............................27 8.4 Layout....................................................................... 28 9 Device and Documentation Support............................31 9.1 Device Support......................................................... 31 9.2 Documentation Support............................................ 31 9.3 Receiving Notification of Documentation Updates....31 9.4 Support Resources................................................... 31 9.5 Trademarks............................................................... 32 9.6 Electrostatic Discharge Caution................................32 9.7 Glossary....................................................................32 10 Mechanical, Packaging, and Orderable Information.................................................................... 32 4 Revision History 2 DATE REVISION NOTES April 2023 * Initial Release Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLV9161-Q1 TLV9162-Q1 TLV9164-Q1 TLV9161-Q1, TLV9162-Q1, TLV9164-Q1 www.ti.com SBOSAD7 – APRIL 2023 5 Pin Configuration and Functions OUT 1 V± 2 IN+ 3 5 V+ 4 IN± IN+ 1 V± 2 IN± 3 Not to scale 5 V+ 4 OUT Not to scale Figure 5-1. TLV9161-Q1 DBV Package, 5-Pin SOT-23 (Top View) Figure 5-2. TLV9161-Q1 DCK Package, 5-Pin SC70 (Top View) Table 5-1. Pin Functions: TLV9161-Q1 PIN NAME SOT-23 (DBV) SC70 (DCK) IN+ 3 1 IN– 4 OUT 1 V+ V– (1) TYPE(1) DESCRIPTION I Noninverting input 3 I Inverting input 4 O Output 5 5 — Positive (highest) power supply 2 2 — Negative (lowest) power supply I = input, O = output Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLV9161-Q1 TLV9162-Q1 TLV9164-Q1 Submit Document Feedback 3 TLV9161-Q1, TLV9162-Q1, TLV9164-Q1 www.ti.com SBOSAD7 – APRIL 2023 OUT1 1 8 V+ IN1± 2 7 OUT2 IN1+ 3 6 IN2± V± 4 5 IN2+ Not to scale Figure 5-3. TLV9162-Q1 D and DGK Package, 8-Pin SOIC and VSSOP (Top View) Table 5-2. Pin Functions: TLV9162-Q1 PIN NAME TYPE(1) DESCRIPTION IN1+ 3 I Noninverting input, channel 1 IN1– 2 I Inverting input, channel 1 IN2+ 5 I Noninverting input, channel 2 IN2– 6 I Inverting input, channel 2 OUT1 1 O Output, channel 1 OUT2 7 O Output, channel 2 V+ 8 — Positive (highest) power supply V– 4 — Negative (lowest) power supply (1) 4 NO. I = input, O = output Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLV9161-Q1 TLV9162-Q1 TLV9164-Q1 TLV9161-Q1, TLV9162-Q1, TLV9164-Q1 www.ti.com SBOSAD7 – APRIL 2023 OUT1 1 14 OUT4 IN1± 2 13 IN4± IN1+ 3 12 IN4+ V+ 4 11 V± IN2+ 5 10 IN3+ IN2± 6 9 IN3± OUT2 7 8 OUT3 Not to scale Figure 5-4. TLV9164-Q1 D and PW Package, 14-Pin SOIC and TSSOP (Top View) Table 5-3. Pin Functions: TLV9164-Q1 PIN NAME NO. TYPE(1) DESCRIPTION IN1+ 3 I Noninverting input, channel 1 IN1– 2 I Inverting input, channel 1 IN2+ 5 I Noninverting input, channel 2 IN2– 6 I Inverting input, channel 2 IN3+ 10 I Noninverting input, channel 3 IN3– 9 I Inverting input, channel 3 IN4+ 12 I Noninverting input, channel 4 IN4– 13 I Inverting input, channel 4 OUT1 1 O Output, channel 1 OUT2 7 O Output, channel 2 OUT3 8 O Output, channel 3 OUT4 14 O Output, channel 4 V+ 4 — Positive (highest) power supply V– 11 — Negative (lowest) power supply (1) I = input, O = output Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLV9161-Q1 TLV9162-Q1 TLV9164-Q1 Submit Document Feedback 5 TLV9161-Q1, TLV9162-Q1, TLV9164-Q1 www.ti.com SBOSAD7 – APRIL 2023 6 Specifications 6.1 Absolute Maximum Ratings over operating ambient temperature range (unless otherwise noted)(1) MIN MAX 0 20 V (V–) – 0.5 (V+) + 0.5 V Supply voltage, VS = (V+) – (V–) Common-mode voltage(3) Differential voltage(3) Signal input pins VS + 0.2 Current(3) –10 10 V– V+ Shutdown pin voltage Output short-circuit(2) –55 Junction temperature, TJ Storage temperature, Tstg (2) (3) V mA Continuous Operating ambient temperature, TA (1) UNIT –65 150 °C 150 °C 150 °C Operating the device beyond the ratings listed under Absolute Maximum Ratings will cause permanent damage to the device. These are stress ratings only, based on process and design limitations, and this device has not been designed to function outside the conditions indicated under Recommended Operating Conditions. Exposure to any condition outside Recommended Operating Conditions for extended periods, including absolute-maximum-rated conditions, may affect device reliability and performance. Short-circuit to ground, one amplifier per package. Extended short-circuit current, especially with higher supply voltage, can cause excessive heating and eventual destruction. Input pins are diode-clamped to the power-supply rails. Input signals that may swing more than 0.5 V beyond the supply rails must be current limited to 10 mA or less. 6.2 ESD Ratings VALUE UNIT TLV9161-Q1 V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2) ±1500 Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2500 V TLV9162-Q1 and TLV9164-Q1 V(ESD) (1) (2) Electrostatic discharge Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2) V ±1500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating ambient temperature range (unless otherwise noted) MIN 6 MAX UNIT VS Supply voltage, (V+) – (V–) 2.7 16 VI Common mode voltage range V– V+ V TA Specified temperature –40 125 °C Submit Document Feedback V Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLV9161-Q1 TLV9162-Q1 TLV9164-Q1 TLV9161-Q1, TLV9162-Q1, TLV9164-Q1 www.ti.com SBOSAD7 – APRIL 2023 6.4 Thermal Information for Single Channel TLV9161-Q1 THERMAL METRIC(1) DBV (SOT-23) DCK (SC70) 5 PINS 5 PINS UNIT RθJA Junction-to-ambient thermal resistance 189.3 202.4 °C/W RθJC(top) Junction-to-case (top) thermal resistance 86.8 111.6 °C/W RθJB Junction-to-board thermal resistance 55.9 51.6 °C/W ψJT Junction-to-top characterization parameter 23.6 25.8 °C/W ψJB Junction-to-board characterization parameter 55.5 51.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. 6.5 Thermal Information for Dual Channel TLV9162-Q1 THERMAL METRIC(1) D (SOIC) DGK (VSSOP) Unit 8 PINS 8 PINS RθJA Junction-to-ambient thermal resistance 130.8 173.9 °C/W RθJC(top) Junction-to-case (top) thermal resistance 74.0 65.7 °C/W RθJB Junction-to-board thermal resistance 74.3 95.6 °C/W ψJT Junction-to-top characterization parameter 25.8 10.9 °C/W ψJB Junction-to-board characterization parameter 73.5 94.1 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. 6.6 Thermal Information for Quad Channel TLV9164-Q1 THERMAL METRIC(1) D (SOIC) PW (TSSOP) UNIT 14 PINS 14 PINS RθJA Junction-to-ambient thermal resistance 94.9 120.0 °C/W RθJC(top) Junction-to-case (top) thermal resistance 51.1 50.4 °C/W RθJB Junction-to-board thermal resistance 51.4 63.1 °C/W ψJT Junction-to-top characterization parameter 15.3 8.1 °C/W ψJB Junction-to-board characterization parameter 51.0 62.5 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLV9161-Q1 TLV9162-Q1 TLV9164-Q1 Submit Document Feedback 7 TLV9161-Q1, TLV9162-Q1, TLV9164-Q1 www.ti.com SBOSAD7 – APRIL 2023 6.7 Electrical Characteristics For VS = (V+) – (V–) = 2.7 V to 16 V (±1.35 V to ±8 V) at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX ±0.21 ±1.03 UNIT OFFSET VOLTAGE VOS Input offset voltage VCM = V– dVOS/dT Input offset voltage drift VCM = V– ±1.2 TA = –40°C to 125°C ±0.25 ±2 TA = –40°C to 125°C ±0.45 ±3 Input offset voltage versus TLV9164-Q1, VCM = V–, VS = 5 V to 16 V power supply TA = –40°C to 125°C ±0.45 ±2.2 ±0.45 ±3.8 ±2 ±12 TLV9161-Q1, TLV9162-Q1, TLV9164-Q1, VCM = V–, VS = TA = –40°C to 125°C 2.7 V to 16 V(1) DC channel separation mV µV/℃ ±0.45 TLV9161-Q1, TLV9162-Q1, VCM = V–, VS = 5 V to 16 V PSRR TA = –40°C to 125°C μV/V 0.4 µV/V INPUT BIAS CURRENT IB Input bias current ±10 pA IOS Input offset current ±10 pA 2.7 μVPP 0.49 µVRMS NOISE EN Input voltage noise f = 0.1 Hz to 10 Hz f = 1 kHz 6.8 f = 10 kHz 4.2 eN Input voltage noise density iN Input current noise density f = 1 kHz nV/√Hz 55 fA/√Hz INPUT VOLTAGE RANGE Common-mode voltage range VCM CMRR Common-mode rejection ratio (V–) (V+) VS = 16 V, V– < VCM < (V+) – 2 V (PMOS pair) 85 110 VS = 5 V, V– < VCM < (V+) – 2 V (PMOS pair)(1) 75 98 VS = 2.7 V, V– < VCM < (V+) – TA = –40°C to 125°C 2 V (PMOS pair) 90 VS = 2.7 – 16 V, (V+) – 1 V < VCM < V+ (NMOS pair) 78 (V+) – 2 V < VCM < (V+) – 1 V V dB See Figure 6-6 INPUT IMPEDANCE ZID Differential ZICM Common-mode 100 || 9 MΩ || pF 6 || 1 TΩ || pF OPEN-LOOP GAIN VS = 16 V, VCM = VS / 2, (V–) + 0.1 V < VO < (V+) – 0.1 V AOL 8 Open-loop voltage gain Submit Document Feedback 120 TA = –40°C to 125°C VS = 5 V, VCM = VS / 2, (V–) + 0.1 V < VO < (V+) – 0.1 V(1) TA = –40°C to 125°C VS = 2.7 V, VCM = VS / 2, (V–) + 0.1 V < VO < (V+) – 0.1 V(1) TA = –40°C to 125°C 136 136 104 125 125 90 dB 105 105 Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLV9161-Q1 TLV9162-Q1 TLV9164-Q1 TLV9161-Q1, TLV9162-Q1, TLV9164-Q1 www.ti.com SBOSAD7 – APRIL 2023 6.7 Electrical Characteristics (continued) For VS = (V+) – (V–) = 2.7 V to 16 V (±1.35 V to ±8 V) at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT FREQUENCY RESPONSE GBW Gain-bandwidth product SR Slew rate tS Settling time VS = 16 V, G = +1, VSTEP = 10 V, CL = 20 pF(2) MHz V/μs To 0.1%, VS = 16 V, VSTEP = 10 V, G = +1, CL = 20 pF 0.70 To 0.1%, VS = 16 V, VSTEP = 2 V, G = +1, CL = 20 pF 0.22 To 0.01%, VS = 16 V, VSTEP = 10 V, G = +1, CL = 20 pF 0.89 To 0.01%, VS = 16 V, VSTEP = 2 V, G = +1, CL = 20 pF 0.42 Phase margin G = +1, RL = 10 kΩ, CL = 20 pF Overload recovery time VIN × gain > VS VS = 16 V, VO = 3 VRMS, G = 1, f = 1 kHz THD+N 11 33 Total harmonic distortion + VS = 10 V, VO = 3 VRMS, G = 1, f = 1 kHz, RL = 128 Ω noise VS = 10 V, VO = 0.4 VRMS, G = 1, f = 1 kHz, RL = 32 Ω μs 64 ° 120 ns 0.00005% 126 dB 0.0032% 90 dB 0.00032% 110 dB OUTPUT VS = 16 V, RL = no load Voltage output swing from rail ISC Short-circuit current CLOAD Capacitive load drive ZO Open-loop output impedance Positive and negative rail headroom 6 VS = 16 V, RL = 10 kΩ 25 60 VS = 16 V, RL = 2 kΩ 85 300 VS = 2.7 V, RL = no load 0.5 VS = 2.7 V, RL = 10 kΩ 5 20 VS = 2.7 V, RL = 2 kΩ 20 50 ±73 IO = 0 A mV mA See Figure 6-33 pF See Figure 6-30 Ω POWER SUPPLY IQ Quiescent current per amplifier TLV9162-Q1, TLV9164-Q1, IO = 0 A TLV9161-Q1, IO = 0 A (1) (2) 2.4 TA = –40°C to 125°C 2.48 TA = –40°C to 125°C 2.8 2.84 2.92 mA 2.98 Specified by characterization only. See Slew Rate vs. Input Step Voltage for more information. Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLV9161-Q1 TLV9162-Q1 TLV9164-Q1 Submit Document Feedback 9 TLV9161-Q1, TLV9162-Q1, TLV9164-Q1 www.ti.com SBOSAD7 – APRIL 2023 6.8 Typical Characteristics at TA = 25°C, VS = ±8 V, VCM = VS / 2, RLOAD = 10 kΩ (unless otherwise noted) 30 45 40 25 30 Population (%) Population (%) 35 25 20 15 20 15 10 10 5 5 0 -675 0 -525 -375 -225 -75 75 225 Offset Voltage (µV) 375 525 0.1 675 0.2 D001 Distribution from 74 amplifiers, TA = 25°C 400 1600 300 1200 200 100 0 -100 -200 400 0 -400 -800 -300 -400 -1600 20 40 60 80 Temperature (°C) 100 120 -2000 -40 140 -20 0 20 2000 1600 1600 1200 1200 Offset Voltage (µV) Offset Voltage (µV) 120 140 D014 Figure 6-4. Offset Voltage vs Temperature 2000 800 400 0 -400 -800 800 400 0 -400 -800 -1200 -1200 -1600 -1600 -2000 5 6 7 TA = 25°C Data from 74 amplifiers Figure 6-5. Offset Voltage vs Common-Mode Voltage Submit Document Feedback 100 VCM = V+ Data from 74 amplifiers Figure 6-3. Offset Voltage vs Temperature 10 40 60 80 Temperature (°C) D013 VCM = V– Data from 74 amplifiers -2000 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 Common-Mode Voltage (V) D002 800 -1200 0 0.9 Figure 6-2. Offset Voltage Drift Distribution 2000 Offset Voltage (µV) Offset Voltage (µV) Figure 6-1. Offset Voltage Production Distribution -20 0.8 Distribution from 74 amplifiers 500 -500 -40 0.3 0.4 0.5 0.6 0.7 Offset Voltage Drift (µV/°C) 8 D015 4 4.5 5 5.5 6 6.5 7 Common-Mode Voltage (V) 7.5 8 D060 TA = 25°C Data from 74 amplifiers Figure 6-6. Offset Voltage vs Common-Mode Voltage (Transition Region) Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLV9161-Q1 TLV9162-Q1 TLV9164-Q1 TLV9161-Q1, TLV9162-Q1, TLV9164-Q1 www.ti.com SBOSAD7 – APRIL 2023 6.8 Typical Characteristics (continued) 2000 2000 1600 1600 1200 1200 800 800 Offset Voltage (µV) Offset Voltage (µV) at TA = 25°C, VS = ±8 V, VCM = VS / 2, RLOAD = 10 kΩ (unless otherwise noted) 400 0 -400 -800 400 0 -400 -800 -1200 -1200 -1600 -1600 -2000 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 Common-Mode Voltage (V) -2000 5 6 7 8 4 4.5 TA = 125°C Data from 74 amplifiers 2000 2000 1600 1600 1200 1200 800 800 400 0 -400 -800 8 400 0 -400 -800 -1200 -1200 -1600 -1600 -2000 5 6 7 8 4 4.5 TA = –40°C Data from 74 amplifiers 5 5.5 6 6.5 7 Common-Mode Voltage (V) 7.5 8 TA = –40°C Data from 74 amplifiers Figure 6-9. Offset Voltage vs Common-Mode Voltage Figure 6-10. Offset Voltage vs Common-Mode Voltage (Transition Region) 75 500 400 G=-1 G=1 G=11 G=101 G=1001 60 Closed-Loop Gain (dB) 300 Offset Voltage (µV) 7.5 Figure 6-8. Offset Voltage vs Common-Mode Voltage (Transition Region) Offset Voltage (µV) Offset Voltage (µV) 5.5 6 6.5 7 Common-Mode Voltage (V) TA = 125°C Data from 74 amplifiers Figure 6-7. Offset Voltage vs Common-Mode Voltage -2000 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 Common-Mode Voltage (V) 5 200 100 0 -100 -200 -300 -400 45 30 15 0 -15 -30 -500 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Supply Voltage (V) VCM = V– Data from 74 amplifiers Figure 6-11. Offset Voltage vs Power Supply -45 100 1k 10k 100k Frequency (Hz) 1M 10M D005 Figure 6-12. Closed-Loop Gain vs Frequency Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLV9161-Q1 TLV9162-Q1 TLV9164-Q1 Submit Document Feedback 11 TLV9161-Q1, TLV9162-Q1, TLV9164-Q1 www.ti.com SBOSAD7 – APRIL 2023 6.8 Typical Characteristics (continued) 20 Input Bias Current and Offset Current (pA) Input Bias Current and Offset Current (pA) at TA = 25°C, VS = ±8 V, VCM = VS / 2, RLOAD = 10 kΩ (unless otherwise noted) IBIB+ IOS 15 10 5 0 -5 -10 -15 -20 -8 -6 -4 -2 0 2 4 Common-Mode Voltage (V) 6 8 600 550 500 450 400 350 300 250 200 150 100 50 0 -50 -100 -40 IBIB+ IOS -20 0 20 40 60 80 Temperature (°C) 50 D020 V+ SR+ SR- 45 V+ - 1V 40 V+ - 2V 35 V+ - 3V Output Voltage (V) Slew Rate (V/Ps) 140 Figure 6-14. Input Bias Current and Offset Current vs Temperature Figure 6-13. Input Bias Current and Offset Current vs CommonMode Voltage 30 25 20 15 V+ - 4V V+ - 5V V+ - 6V V+ - 7V V+ - 8V 10 -40°C 25°C 125°C V+ - 9V 5 V+ - 10V 0 0 0 0.5 1 1.5 2 2.5 3 Input Step (V) 3.5 4 4.5 10 20 30 5 40 50 60 70 Output Current (mA) 80 90 100 D021 VS = 16 V D035 Figure 6-15. Slew Rate vs Input Step Voltage Figure 6-16. Output Voltage Swing vs Output Current (Sourcing) V+ V- + 10V -40°C 25°C 125°C V- + 9V V- + 8V V+ - 1V V- + 7V Output Voltage (V) Output Voltage (V) 120 No Load No Load V- + 6V V- + 5V V- + 4V V- + 3V V- + 2V V+ - 2V V+ - 3V V+ - 4V -40°C 25°C 125°C V- + 1V V- V+ - 5V 0 10 20 30 40 50 60 70 Output Current (mA) 80 90 100 0 10 20 30 D022 VS = 16 V Figure 6-17. Output Voltage Swing vs Output Current (Sinking) 12 100 D019 Submit Document Feedback 40 50 60 70 Output Current (mA) 80 90 100 D049 VS = 5 V Figure 6-18. Output Voltage Swing vs Output Current (Sourcing) Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLV9161-Q1 TLV9162-Q1 TLV9164-Q1 TLV9161-Q1, TLV9162-Q1, TLV9164-Q1 www.ti.com SBOSAD7 – APRIL 2023 6.8 Typical Characteristics (continued) at TA = 25°C, VS = ±8 V, VCM = VS / 2, RLOAD = 10 kΩ (unless otherwise noted) 120 V- + 5V -40°C 25°C 125°C CMRR & PSRR (dB) Output Voltage (V) V- + 4V CMRR PSRR+ PSRR- 105 V- + 3V V- + 2V V- + 1V 90 75 60 45 30 15 V20 30 40 50 60 70 Output Current (mA) 80 90 0 1k 100 D050 VS = 5 V 120 1 140 0.1 -40 -20 0 20 40 60 80 Temperature (°C) 100 120 Common-Mode Rejection Ratio (PV/V) 100 10 Common-Mode Rejection Ratio (dB) Common-Mode Rejection Ratio (PV/V) 1000 80 100k 1M Frequency (Hz) 60 100 80 10 100 1 120 0.1 -40 140 -20 0 20 D023 80 10 100 1 120 40 60 80 Temperature (°C) 100 120 VS = 2.7 V, VCM = V– 140 140 D052 Power-Supply Rejection Ratio (µV/V) 100 20 100 120 140 140 D051 Figure 6-22. CMRR vs Temperature 60 Common-Mode Rejection Ratio (dB) Common-Mode Rejection Ratio (PV/V) Figure 6-21. CMRR vs Temperature 0 40 60 80 Temperature (°C) VS = 5 V, VCM = V– 1000 -20 D006 1000 VS = 16 V, VCM = V– 0.1 -40 10M Figure 6-20. CMRR and PSRR vs Frequency Figure 6-19. Output Voltage Swing vs Output Current (Sinking) 100 10k Common-Mode Rejection Ratio (dB) 10 100 80 10 100 1 120 0.1 140 0.01 -40 -20 0 20 40 60 80 Temperature (°C) 100 120 Power-Supply Rejection Ratio (dB) 0 160 140 Figure 6-24. PSRR vs Temperature Figure 6-23. CMRR vs Temperature Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLV9161-Q1 TLV9162-Q1 TLV9164-Q1 Submit Document Feedback 13 TLV9161-Q1, TLV9162-Q1, TLV9164-Q1 www.ti.com SBOSAD7 – APRIL 2023 6.8 Typical Characteristics (continued) Input Voltage Noise Spectral Density (nV/rtHz) at TA = 25°C, VS = ±8 V, VCM = VS / 2, RLOAD = 10 kΩ (unless otherwise noted) 2 1.5 Amplitude (PV) 1 0.5 0 -0.5 -1 -1.5 -2 Time (1s/div) 100 10 1 10 100 1k Frequency (Hz) D025 Figure 6-25. 0.1-Hz to 10-Hz Noise Quiescent Current (mA) Quiescent Current (mA) 2.4 2 1.6 1.2 0.8 0.4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Supply Voltage (V) 2.6 2.55 2.5 2.45 2.4 2.35 2.3 2.25 2.2 2.15 2.1 2.05 2 1.95 1.9 1.85 1.8 -40 Vs=2.7V Vs=5V Vs=16V -20 0 20 40 60 80 Temperature (°C) 140 D027 1000 145 135 Open-Loop Output Impedance (:) VS = 2.7V VS = 5V VS = 16V 140 Open-Loop Gain (dB) 120 Figure 6-28. Quiescent Current vs Temperature Figure 6-27. Quiescent Current vs Supply Voltage 130 125 120 115 110 105 -20 0 20 40 60 80 Temperature (°C) 100 120 140 D028 Figure 6-29. Open-Loop Voltage Gain vs Temperature (dB) 14 100 VCM = V– VCM = V– 100 -40 D007 Figure 6-26. Input Voltage Noise Spectral Density vs Frequency 2.8 0 10k Submit Document Feedback 100 10 1 0.1 100 1k 10k 100k Frequency (Hz) 1M 10M D099 Figure 6-30. Open-Loop Output Impedance vs Frequency Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLV9161-Q1 TLV9162-Q1 TLV9164-Q1 TLV9161-Q1, TLV9162-Q1, TLV9164-Q1 www.ti.com SBOSAD7 – APRIL 2023 6.8 Typical Characteristics (continued) 70 70 60 60 50 50 Overshoot (%) Overshoot (%) at TA = 25°C, VS = ±8 V, VCM = VS / 2, RLOAD = 10 kΩ (unless otherwise noted) 40 30 20 40 30 20 RISO = 0:, Overshoot (+) RISO = 0:, Overshoot (-) RISO = 50:, Overshoot (+) RISO = 50:, Overshoot (-) 10 RISO = 0:, Overshoot (+) RISO = 0:, Overshoot (-) RISO = 50:, Overshoot (+) RISO = 50:, Overshoot (-) 10 0 0 0 80 160 240 320 400 Capacitive Load (pF) 480 560 0 D029 20-mVpp output step, G = –1 80 160 240 320 400 Capacitive Load (pF) 480 D030 20-mVpp output step, G = +1 Figure 6-31. Small-Signal Overshoot vs Capacitive Load Figure 6-32. Small-Signal Overshoot vs Capacitive Load 20 70 Input Output 65 60 10 55 Amplitude (mV) Phase Margin (°) 560 50 45 40 35 0 -10 30 25 -20 20 0 20 40 60 Time (2 µs/div) 80 100 120 140 160 180 200 220 Capacitive Load (pF) D004 D033 CL = 20 pF, G = 1, 20-mVpp step response G = +1 Figure 6-34. Small-Signal Step Response Figure 6-33. Phase Margin vs Capacitive Load 4 20 Input Output 10 2 Amplitude (V) Amplitude (mV) Input Output 3 0 -10 1 0 -1 -2 -3 -20 -4 Time (2 µs/div) Time (2 µs/div) D054 CL = 20 pF, G = –1, 20-mVpp step response Figure 6-35. Small-Signal Step Response D034 CL = 20 pF, G = 1, 5-Vpp step response Figure 6-36. Large-Signal Step Response Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLV9161-Q1 TLV9162-Q1 TLV9164-Q1 Submit Document Feedback 15 TLV9161-Q1, TLV9162-Q1, TLV9164-Q1 www.ti.com SBOSAD7 – APRIL 2023 6.8 Typical Characteristics (continued) at TA = 25°C, VS = ±8 V, VCM = VS / 2, RLOAD = 10 kΩ (unless otherwise noted) 4 20 Vs=16V Vs=2.7V Input Output 3 16 1 Output (V) Amplitude (V) 2 0 -1 12 8 -2 4 -3 -4 0 100 Time (2 µs/div) D055 1k 10k 100k 1M Frequency (Hz) 10M 100M Figure 6-38. Maximum Output Voltage vs Frequency CL = 20 pF, G = –1, 5-Vpp step response 120 -70 110 -80 100 -90 90 EMIRR (dB) Crosstalk (dB) Figure 6-37. Large-Signal Step Response -60 -100 -110 -120 70 60 -130 50 -140 40 -150 30 -160 100 1k 10k 100k Frequency (Hz) 1M Submit Document Feedback 20 10M 10M Figure 6-39. Channel Separation vs Frequency 16 80 D011 100M Frequency (Hz) 1G D012 Figure 6-40. EMIRR (Electromagnetic Interference Rejection Ratio) vs Frequency Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLV9161-Q1 TLV9162-Q1 TLV9164-Q1 TLV9161-Q1, TLV9162-Q1, TLV9164-Q1 www.ti.com SBOSAD7 – APRIL 2023 7 Detailed Description 7.1 Overview The TLV916x-Q1 family (TLV9161-Q1, TLV9162-Q1, and TLV9164-Q1) is a family of 16-V, general-purpose, automotive operational amplifiers. These devices offer excellent DC precision and AC performance, including rail-to-rail input or output, low offset (±210 µV, typical), low offset drift (±0.25 µV/°C, typical), and 11-MHz bandwidth. Features such as wide differential input range, high short-circuit current (±73 mA), and high slew rate (33 V/μs) make the TLV916x-Q1 a flexible, robust, and high-performance operational amplifier for 16-V automotive applications. 7.2 Functional Block Diagram + NCH Input Stage – IN+ + 16-V Differential MUX-Friendly Front End Slew Boost Gain Stage Shutdown Circuitry Output Stage OUT – IN- + PCH Input Stage – Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLV9161-Q1 TLV9162-Q1 TLV9164-Q1 Submit Document Feedback 17 TLV9161-Q1, TLV9162-Q1, TLV9164-Q1 www.ti.com SBOSAD7 – APRIL 2023 7.3 Feature Description 7.3.1 Input Protection Circuitry The TLV916x-Q1 uses a special input architecture to eliminate the requirement for input protection diodes but still provides robust input protection under transient conditions. Figure 7-1 shows conventional input diode protection schemes that are activated by fast transient step responses and introduce signal distortion and settling time delays because of alternate current paths, as shown in Figure 7-2. For low-gain circuits, these fast-ramping input signals forward-bias back-to-back diodes, causing an increase in input current and resulting in extended settling time. V+ V+ VIN+ VIN+ VOUT TLV916x 16 V VOUT ~0.7 V VIN VIN V TLV916x Provides Full 16-V Differential Input Range V Conventional Input Protection Limits Differential Input Range Figure 7-1. TLV916x-Q1 Input Protection Does Not Limit Differential Input Capability Vn = 8 V RFILT 8V 1 Ron_mux Sn 1 D 8V CFILT 2 ~–7.3 V CS CD Vn+1 = –8 V RFILT –8 V Ron_mux Sn+1 VIN– 2 ~0.7 V CS CFILT VOUT Idiode_transient –8 V Simplified Mux Model Input Low-Pass Filter VIN+ Buffer Amplifier Figure 7-2. Back-to-Back Diodes Create Settling Issues The TLV916x-Q1 family of operational amplifiers provides a true high-impedance differential input capability using a patented input protection architecture that does not introduce additional signal distortion or delayed settling time, making the device an optimal op amp for multichannel, high-switched, input applications. The TLV916x-Q1 tolerates a maximum differential swing (voltage between inverting and non-inverting pins of the op amp) of up to 16 V, making the device suitable for use as a comparator or in applications with fast-ramping input signals such as data-acquisition systems; see the TI TechNote MUX-Friendly Precision Operational Amplifiers for more information. 18 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLV9161-Q1 TLV9162-Q1 TLV9164-Q1 TLV9161-Q1, TLV9162-Q1, TLV9164-Q1 www.ti.com SBOSAD7 – APRIL 2023 7.3.2 EMI Rejection The TLV916x-Q1 uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI from sources such as wireless communications and densely-populated boards with a mix of analog signal chain and digital components. EMI immunity can be improved with circuit design techniques; the TLV916x-Q1 benefits from these design improvements. Texas Instruments has developed the ability to accurately measure and quantify the immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz. Figure 7-3 shows the results of this testing on the TLV916x-Q1. Table 7-1 provides the EMIRR IN+ values for the TLV916x-Q1 at particular frequencies commonly encountered in real-world applications. The EMI Rejection Ratio of Operational Amplifiers application report contains detailed information on the topic of EMIRR performance as it relates to op amps and is available for download from www.ti.com. 120 110 100 EMIRR (dB) 90 80 70 60 50 40 30 20 10M 100M Frequency (Hz) 1G D012 Figure 7-3. EMIRR Testing Table 7-1. TLV9161-Q1 EMIRR IN+ for Frequencies of Interest FREQUENCY APPLICATION OR ALLOCATION EMIRR IN+ 400 MHz Mobile radio, mobile satellite, space operation, weather, radar, ultra-high frequency (UHF) applications 50.0 dB 900 MHz Global system for mobile communications (GSM) applications, radio communication, navigation, GPS (to 1.6 GHz), GSM, aeronautical mobile, UHF applications 56.3 dB 1.8 GHz GSM applications, mobile personal communications, broadband, satellite, L-band (1 GHz to 2 GHz) 65.6 dB Bluetooth®, 2.4 GHz 802.11b, 802.11g, 802.11n, mobile personal communications, industrial, scientific and medical (ISM) radio band, amateur radio and satellite, S-band (2 GHz to 4 GHz) 70.0 dB 3.6 GHz Radiolocation, aero communication and navigation, satellite, mobile, S-band 78.9 dB 802.11a, 802.11n, aero communication and navigation, mobile communication, space and satellite operation, C-band (4 GHz to 8 GHz) 91.0 dB 5 GHz Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLV9161-Q1 TLV9162-Q1 TLV9164-Q1 Submit Document Feedback 19 TLV9161-Q1, TLV9162-Q1, TLV9164-Q1 www.ti.com SBOSAD7 – APRIL 2023 7.3.3 Thermal Protection One channel has load Consider IQ of two channels TA = 60°C PD = 0.627W JA = 183.4°C/W TJ = 183.4°C/W × 0.627W + 60°C TJ = 175°C (expected) 16 V
VOUT The internal power dissipation of any amplifier causes its internal (junction) temperature to rise. This phenomenon is called self heating. The absolute maximum junction temperature of the TLV916x-Q1 is 150°C. Exceeding this temperature causes damage to the device. The TLV916x-Q1 has a thermal protection feature that reduces damage from self heating. The protection works by monitoring the temperature of the device and turning off the op amp output drive for temperatures above 170°C. Figure 7-4 shows an application example for the TLV9162-Q1 that has significant self heating because of its power dissipation (0.627 W). In this example, both channels have a quiescent power dissipation while one of the channels has a significant load. Thermal calculations indicate that for an ambient temperature of 60°C, the device junction temperature reaches 175°C. The actual device, however, turns off the output drive to recover towards a safe junction temperature. Figure 7-4 shows how the circuit behaves during thermal protection. During normal operation, the device acts as a buffer so the output is 5 V. When self heating causes the device junction temperature to increase above the internal limit, the thermal protection forces the output to a high-impedance state and the output is pulled to ground through resistor RL. If the condition that caused excessive power dissipation is not removed, the amplifier will oscillate between a shutdown and enabled state until the output fault is corrected. Please note that thermal performance can vary greatly depending on the package selected and the PCB layout design. This example uses the thermal performance of the TSSOP (8) package. 5V 0V TLV9162 IOUT = 50 mA + – + RL 5V 100
– VIN 5V 170ºC Temperature  Figure 7-4. Thermal Protection 7.3.4 Capacitive Load and Stability The TLV916x-Q1 features an output stage capable of driving moderate capacitive loads, and by leveraging an isolation resistor, the device can easily be configured to drive larger capacitive loads. Increasing the gain enhances the ability of the amplifier to drive greater capacitive loads; see Figure 7-5 and Figure 7-6. The particular op amp circuit configuration, layout, gain, and output loading are some of the factors to consider when establishing whether an amplifier will be stable in operation. 70 70 RISO = 0:, Overshoot (+) RISO = 0:, Overshoot (-) RISO = 50:, Overshoot (+) RISO = 50:, Overshoot (-) 60 50 Overshoot (%) Overshoot (%) 50 60 40 30 30 20 20 10 10 0 RISO = 0:, Overshoot (+) RISO = 0:, Overshoot (-) RISO = 50:, Overshoot (+) RISO = 50:, Overshoot (-) 0 0 80 160 240 320 400 Capacitive Load (pF) 480 560 D030 Figure 7-5. Small-Signal Overshoot vs Capacitive Load (20-mVpp Output Step, G = +1) 20 40 Submit Document Feedback 0 80 160 240 320 400 Capacitive Load (pF) 480 560 D029 Figure 7-6. Small-Signal Overshoot vs Capacitive Load (20-mVpp Output Step, G = -1) Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLV9161-Q1 TLV9162-Q1 TLV9164-Q1 TLV9161-Q1, TLV9162-Q1, TLV9164-Q1 www.ti.com SBOSAD7 – APRIL 2023 For additional drive capability in unity-gain configurations, improve capacitive load drive by inserting a small resistor, RISO, in series with the output, as shown in Figure 7-7. This resistor significantly reduces ringing and maintains DC performance for purely capacitive loads. However, if a resistive load is in parallel with the capacitive load, then a voltage divider is created, thus introducing a gain error at the output and slightly reducing the output swing. The error introduced is proportional to the ratio RISO / RL, and is generally negligible at low output levels. A high capacitive load drive makes the TLV916x-Q1 well suited for applications such as reference buffers, MOSFET gate drives, and cable-shield drives. The circuit shown in Figure 7-7 uses an isolation resistor, RISO, to stabilize the output of an op amp. RISO modifies the open-loop gain of the system for increased phase margin. +Vs Vout Riso + Vin + ± Cload -Vs Figure 7-7. Extending Capacitive Load Drive With the TLV9161-Q1 Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLV9161-Q1 TLV9162-Q1 TLV9164-Q1 Submit Document Feedback 21 TLV9161-Q1, TLV9162-Q1, TLV9164-Q1 www.ti.com SBOSAD7 – APRIL 2023 7.3.5 Common-Mode Voltage Range The TLV916x-Q1 is a 16-V, rail-to-rail input operational amplifier with an input common-mode range that extends to both supply rails. This wide range is achieved with paralleled complementary N-channel and P-channel differential input pairs, as shown in Figure 7-8. The N-channel pair is active for input voltages close to the positive rail, typically from (V+) – 1 V to the positive supply. The P-channel pair is active for inputs from the negative supply to approximately (V+) – 2 V. There is a small transition region, typically (V+) – 2 V to (V+) – 1 V in which both input pairs are on. This transition region can vary modestly with process variation. Within this region PSRR, CMRR, offset voltage, offset drift, noise, and THD performance may be degraded compared to operation outside this region. Figure 6-5 shows this transition region for a typical device in terms of input voltage offset in more detail. For more information on common-mode voltage range and PMOS/NMOS pair interaction, see Op Amps With Complementary-Pair Input Stages application note. V+ INPMOS PMOS NMOS IN+ NMOS V- Figure 7-8. Rail-to-Rail Input Stage 7.3.6 Phase Reversal Protection The TLV916x-Q1 family has internal phase-reversal protection. Many op amps exhibit a phase reversal when the input is driven beyond its linear common-mode range. This condition is most often encountered in non-inverting circuits when the input is driven beyond the specified common-mode voltage range, causing the output to reverse into the opposite rail. The TLV916x-Q1 is a rail-to-rail input op amp; therefore, the common-mode range can extend up to the rails. Input signals beyond the rails do not cause phase reversal; instead, the output limits into the appropriate rail. For more information on phase reversal, see Op Amps With Complementary-Pair Input Stages application note. 22 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLV9161-Q1 TLV9162-Q1 TLV9164-Q1 TLV9161-Q1, TLV9162-Q1, TLV9164-Q1 www.ti.com SBOSAD7 – APRIL 2023 7.3.7 Electrical Overstress Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress (EOS). These questions tend to focus on the device inputs, but may involve the supply voltage pins or even the output pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin. Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from accidental ESD events both before and during product assembly. Having a good understanding of this basic ESD circuitry and its relevance to an electrical overstress event is helpful. Figure 7-9 shows an illustration of the ESD circuits contained in the TLV916x-Q1 (indicated by the dashed line area). The ESD protection circuitry involves several current-steering diodes connected from the input and output pins and routed back to the internal power-supply lines, where the diodes meet at an absorption device or the power-supply ESD cell, internal to the operational amplifier. This protection circuitry is intended to remain inactive during normal circuit operation. TVS + – RF +VS VDD R1 RS IN– 50
IN+ 50 – + Power-Supply ESD Cell ID VIN RL + – VSS + – –VS TVS Figure 7-9. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application An ESD event is very short in duration and very high voltage (for example; 1 kV, 100 ns), whereas an EOS event is long duration and lower voltage (for example; 50 V, 100 ms). The ESD diodes are designed for out-of-circuit ESD protection (that is, during assembly, test, and storage of the device before being soldered to the PCB). During an ESD event, the ESD signal is passed through the ESD steering diodes to an absorption circuit (labeled ESD power-supply circuit). The ESD absorption circuit clamps the supplies to a safe level. Although this behavior is necessary for out-of-circuit protection, excessive current and damage is caused if activated in-circuit. A transient voltage suppressors (TVS) can be used to prevent against damage caused by turning on the ESD absorption circuit during an in-circuit ESD event. Using the appropriate current limiting resistors and TVS diodes allows for the use of device ESD diodes to protect against EOS events. Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLV9161-Q1 TLV9162-Q1 TLV9164-Q1 Submit Document Feedback 23 TLV9161-Q1, TLV9162-Q1, TLV9164-Q1 www.ti.com SBOSAD7 – APRIL 2023 7.3.8 Overload Recovery Overload recovery is defined as the time required for the op amp output to recover from a saturated state to a linear state. The output devices of the op amp enter a saturation region when the output voltage exceeds the rated operating voltage, either due to the high input voltage or the high gain. After the device enters the saturation region, the charge carriers in the output devices require time to return back to the linear state. After the charge carriers return back to the linear state, the device begins to slew at the specified slew rate. Thus, the propagation delay in case of an overload condition is the sum of the overload recovery time and the slew time. The overload recovery time for the TLV916x-Q1 is approximately 120 ns. 7.3.9 Typical Specifications and Distributions Designers often have questions about a typical specification of an amplifier in order to design a more robust circuit. Due to natural variation in process technology and manufacturing procedures, every specification of an amplifier will exhibit some amount of deviation from the ideal value, like an amplifier's input offset voltage. These deviations often follow Gaussian (bell curve), or normal distributions, and circuit designers can leverage this information to guardband their system, even when there is not a minimum or maximum specification in the Electrical Characteristics table. 0.00002% 0.00312% 0.13185% 1 -61 1 -51 1 -41 2.145% 13.59% 34.13% 34.13% 13.59% 2.145% 1 -31 1 -21 1 -1 1 1 +1 0.13185% 0.00312% 0.00002% 1 1 1 1 +21 +31 +41 +51 +61 Figure 7-10. Ideal Gaussian Distribution Figure 7-10 shows an example distribution, where µ, or mu, is the mean of the distribution, and where σ, or sigma, is the standard deviation of a system. For a specification that exhibits this kind of distribution, approximately two-thirds (68.26%) of all units can be expected to have a value within one standard deviation, or one sigma, of the mean (from µ – σ to µ + σ). Depending on the specification, values listed in the typical column of the Electrical Characteristics table are represented in different ways. As a general rule of thumb, if a specification naturally has a nonzero mean (for example, like gain bandwidth), then the typical value is equal to the mean (µ). However, if a specification naturally has a mean near zero (like input offset voltage), then the typical value is equal to the mean plus one standard deviation (µ + σ) in order to most accurately represent the typical value. 24 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLV9161-Q1 TLV9162-Q1 TLV9164-Q1 TLV9161-Q1, TLV9162-Q1, TLV9164-Q1 www.ti.com SBOSAD7 – APRIL 2023 This chart can be used to calculate approximate probability of a specification in a unit; for example, for TLV916xQ1, the typical input voltage offset is 210 µV, so 68.2% of all TLV916x-Q1 devices are expected to have an offset from –210 µV to 210 µV. At 4 σ (±840 µV), 99.9937% of the distribution has an offset voltage less than ±840 µV, which means 0.0063% of the population is outside of these limits, which corresponds to about 1 in 15,873 units. Specifications with a value in the minimum or maximum column are assured by TI, and units outside these limits will be removed from production material. For example, the TLV916x-Q1 family has a maximum offset voltage of 1 mV at 25°C, and even though this corresponds to about 5-σ (≈1 in 1.7 million units), which is extremely unlikely, TI assures that any unit with larger offset than 1 mV will be removed from production material. For specifications with no value in the minimum or maximum column, consider selecting a sigma value of sufficient guardband for the application, and design worst-case conditions using this value. For example, the 6-σ value corresponds to about 1 in 500 million units, which is an extremely unlikely chance, and could be an option as a wide guardband to design a system around. In this case, the TLV916x-Q1 family does not have a maximum or minimum for offset voltage drift, but based on the typical value of 0.25 µV/°C in the Electrical Characteristics table, it can be calculated that the 6-σ value for offset voltage drift is about 1.5 µV/°C. When designing for worst-case system conditions, this value can be used to estimate the worst possible offset across temperature without having an actual minimum or maximum value. However, process variation and adjustments over time can shift typical means and standard deviations, and unless there is a value in the minimum or maximum specification column, TI cannot assure the performance of a device. This information should be used only to estimate the performance of a device. 7.4 Device Functional Modes The TLV916x-Q1 has a single functional mode and is operational when the power-supply voltage is greater than 2.7 V (±1.35 V). The maximum power supply voltage for the TLV916x-Q1 is 16 V (±8 V). Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLV9161-Q1 TLV9162-Q1 TLV9164-Q1 Submit Document Feedback 25 TLV9161-Q1, TLV9162-Q1, TLV9164-Q1 www.ti.com SBOSAD7 – APRIL 2023 8 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. 8.1 Application Information The TLV916x-Q1 family offers excellent DC precision and AC performance. These devices operate up to 16-V supply rails and offer true rail-to-rail input/output, low offset voltage and offset voltage drift, as well as 11-MHz bandwidth and high output drive. These features make the TLV916x-Q1 a robust, high-performance operational amplifier for 16-V industrial applications. 8.2 Typical Applications 8.2.1 Low-Side Current Measurement Figure 8-1 shows the TLV9161-Q1 configured in a low-side current sensing application. For a full analysis of the circuit shown in Figure 8-1 including theory, calculations, simulations, and measured data, see TI Precision Design TIPD129, 0-A to 1-A Single-Supply Low-Side Current-Sensing Solution. VCC 5V LOAD + TLV9161 VOUT – ILOAD RSHUNT 100 m LM7705 RF 5.76 k RG 120
Figure 8-1. TLV9161-Q1 in a Low-Side, Current-Sensing Application 8.2.1.1 Design Requirements The design requirements for this design are: • • • 26 Load current: 0 A to 1 A Output voltage: 4.9 V Maximum shunt voltage: 100 mV Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLV9161-Q1 TLV9162-Q1 TLV9164-Q1 TLV9161-Q1, TLV9162-Q1, TLV9164-Q1 www.ti.com SBOSAD7 – APRIL 2023 8.2.1.2 Detailed Design Procedure The transfer function of the circuit in Figure 8-1 is given in Equation 1: VOUT  = ILOAD ×  RSHUNT × Gain (1) The load current (ILOAD) produces a voltage drop across the shunt resistor (RSHUNT). The load current is set from 0 A to 1 A. To keep the shunt voltage below 100 mV at maximum load current, the largest shunt resistor is defined using Equation 2: V   RSHUNT  = ISHUNT_MAX   =   100 mV 1 A   =  100 mΩ (2) LOAD_MAX Using Equation 2, RSHUNT is calculated to be 100 mΩ. The voltage drop produced by ILOAD and RSHUNT is amplified by the TLV916x-Q1 to produce an output voltage of 0 V to 4.9 V. The gain needed by the TLV916x-Q1 to produce the necessary output voltage is calculated using Equation 3: Gain  = VOUT_MAX  −  VOUT_MIN VIN_MAX  −  VIN_MIN (3) Using Equation 3, the required gain is calculated to be 49 V/V, which is set with resistors RF and RG. Equation 4 is used to size the resistors, RF and RG, to set the gain of the TLV916x-Q1 to 49 V/V. Gain  =  1  +   RF RG (4) Choosing RF as 5.76 kΩ, RG is calculated to be 120 Ω. RF and RG were chosen as 5.76 kΩ and 120 Ω because the values are standard value resistors that create a 49:1 ratio. Other resistors that create a 49:1 ratio can also be used. However, excessively large resistors generate thermal noise that exceeds the intrinsic noise of the op amp. Figure 8-2 shows the measured transfer function of the circuit shown in Figure 8-1. 8.2.1.3 Application Curves 5 Output (V) 4 3 2 1 0 0 0.1 0.2 0.3 0.4 0.5 0.6 ILOAD (A) 0.7 0.8 0.9 1 Figure 8-2. Low-Side, Current-Sense, Transfer Function 8.3 Power Supply Recommendations The TLV916x-Q1 is specified for operation from 2.7 V to 16 V (±1.35 V to ±8 V); many specifications apply from –40°C to 125°C or with specific supply voltage and test conditions. Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLV9161-Q1 TLV9162-Q1 TLV9164-Q1 Submit Document Feedback 27 TLV9161-Q1, TLV9162-Q1, TLV9164-Q1 www.ti.com SBOSAD7 – APRIL 2023 CAUTION Supply voltages larger than 20 V can permanently damage the device; see the Absolute Maximum Ratings section. Place 0.1-µF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-impedance power supplies. For more detailed information on bypass capacitor placement, refer to the Layout section. 8.4 Layout 8.4.1 Layout Guidelines For best operational performance of the device, use good PCB layout practices, including: • • • • • • • • 28 Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources local to the analog circuitry. – Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as close to the device as possible. A single bypass capacitor from V+ to ground is applicable for singlesupply applications. Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital and analog grounds paying attention to the flow of the ground current. To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as opposed to in parallel with the noisy trace. Place the external components as close to the device as possible. As shown in Figure 8-4, keeping RF and RG close to the inverting input minimizes parasitic capacitance. Keep the length of input traces as short as possible. Always remember that the input traces are the most sensitive part of the circuit. Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce leakage currents from nearby traces that are at different potentials. Cleaning the PCB following board assembly is recommended for best performance. Any precision integrated circuit may experience performance shifts due to moisture ingress into the plastic package. Following any aqueous PCB cleaning process, baking the PCB assembly is recommended to remove moisture introduced into the device packaging during the cleaning process. A low temperature, post cleaning bake at 85°C for 30 minutes is sufficient for most circumstances. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLV9161-Q1 TLV9162-Q1 TLV9164-Q1 TLV9161-Q1, TLV9162-Q1, TLV9164-Q1 www.ti.com SBOSAD7 – APRIL 2023 8.4.2 Layout Example VC3 INPUT OUTPUT 1 + 3 2 – R3 4 C4 C2 V+ R1 C1 R2 GND V+ INPUT Figure 8-3. Schematic for Non-inverting Configuration Layout Example GND OUTPUT V- GND Figure 8-4. Operational Amplifier Board Layout for Non-inverting Configuration - SC70 (DCK) Package Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLV9161-Q1 TLV9162-Q1 TLV9164-Q1 Submit Document Feedback 29 TLV9161-Q1, TLV9162-Q1, TLV9164-Q1 www.ti.com GND OUTPUT A SBOSAD7 – APRIL 2023 GND GND V+ INPUT A VGND GND INPUT B OUTPUT B GND Figure 8-5. Example Layout for VSSOP-8 (DGK) Package 30 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLV9161-Q1 TLV9162-Q1 TLV9164-Q1 TLV9161-Q1, TLV9162-Q1, TLV9164-Q1 www.ti.com SBOSAD7 – APRIL 2023 9 Device and Documentation Support 9.1 Device Support 9.1.1 Development Support 9.1.1.1 TINA-TI™ (Free Software Download) TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI is a free, fully-functional version of the TINA software, preloaded with a library of macro models in addition to a range of both passive and active models. TINA-TI provides all the conventional dc, transient, and frequency domain analysis of SPICE, as well as additional design capabilities. Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool. Note These files require that either the TINA software (from DesignSoft™) or TINA-TI software be installed. Download the free TINA-TI software from the TINA-TI folder. 9.2 Documentation Support 9.2.1 Related Documentation For related documentation, see the following: 1. 2. 3. 4. 5. Texas Instruments, Analog Engineer's Circuit Cookbook: Amplifiers Texas Instruments, AN31 amplifier circuit collection application note Texas Instruments, MUX-Friendly, Precision Operational Amplifiers application brief Texas Instruments, EMI Rejection Ratio of Operational Amplifiers application note Texas Instruments, Op Amps With Complementary-Pair Input Stages application note 9.3 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 9.4 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLV9161-Q1 TLV9162-Q1 TLV9164-Q1 Submit Document Feedback 31 TLV9161-Q1, TLV9162-Q1, TLV9164-Q1 www.ti.com SBOSAD7 – APRIL 2023 9.5 Trademarks TINA-TI™ is a trademark of Texas Instruments, Inc and DesignSoft, Inc. TINA™ and DesignSoft™ are trademarks of DesignSoft, Inc. TI E2E™ is a trademark of Texas Instruments. Bluetooth® is a registered trademark of Bluetooth SIG, Inc. All trademarks are the property of their respective owners. 9.6 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 9.7 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 10 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 32 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLV9161-Q1 TLV9162-Q1 TLV9164-Q1 PACKAGE OPTION ADDENDUM www.ti.com 23-Jul-2023 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) TLV9161QDBVRQ1 ACTIVE SOT-23 DBV 5 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 2W2H Samples TLV9161QDCKRQ1 ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 1NJ Samples TLV9162QDGKRQ1 ACTIVE VSSOP DGK 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 2S5T Samples TLV9162QDRQ1 ACTIVE SOIC D 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 T9162Q Samples TLV9164QDRQ1 ACTIVE SOIC D 14 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 TLV9164QD Samples TLV9164QPWRQ1 ACTIVE TSSOP PW 14 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 T9164PW Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of