TLV9354QDRQ1

TLV9351-Q1, TLV9352-Q1, TLV9354-Q1 SBOSA34D – JANUARY 2021 – REVISED JUNE 2023 TLV935x-Q1 3.5-MHz, 40-V, RRO, MUX-Friendly Automotive Operational Amplifier for Cost-Sensitive Systems 1 Features 3 Description • • • • • • • The TLV935x-Q1 family (TLV9351-Q1, TLV9352-Q1, and TLV9354-Q1) is a family of 40-V cost-optimized automotive operational amplifiers. • • • • • Low offset voltage: ±350 µV Low offset voltage drift: ±1.5 µV/°C Low noise: 15 nV/√Hz at 1 kHz High common-mode rejection: 110 dB Low bias current: ±10 pA Rail-to-rail output MUX-friendly/comparator inputs – Amplifier operates with differential inputs up to supply rail – Amplifier can be used in open-loop or as comparator Wide bandwidth: 3.5-MHz GBW High slew rate: 20 V/µs Low quiescent current: 600 µA per amplifier Wide supply: ±2.25 V to ±20 V, 4.5 V to 40 V Robust EMIRR performance: EMI/RFI filters on input pins These devices offer strong DC and AC specifications, including rail-to-rail output, low offset (±350 µV, typ), low offset drift (±1.5 µV/°C, typ), and 3.5-MHz bandwidth. Unique features such as differential input-voltage range to the supply rail, high output current (±60 mA), and high slew rate (20 V/µs) make the TLV935x-Q1 a robust operational amplifier for high-voltage, costsensitive applications. The TLV935x-Q1 family of op amps is available in standard packages and is specified from –40°C to 125°C. Device Information 2 Applications • • • • • • • • • PART NUMBER Optimized for AEC-Q100 grade 1 applications Infotainment and cluster Passive safety Body electronics and lighting HEV/EV inverter and motor control On-board (OBC) and wireless changer Powertrain current sensor Advanced driver assistance systems (ADAS) Single-supply, low-side current sensing TLV9351-Q1 TLV9352-Q1 TLV9354-Q1 (1) (2) RG CHANNEL COUNT Single Dual Quad PACKAGE(1) PACKAGE SIZE(2) DBV (SOT-23 , 5) 2.90 mm × 2.80 mm D (SOIC, 8) 4.90 mm × 6.00 mm PW (TSSOP, 8) 3.00 mm × 6.40 mm DGK (VSSOP, 8) 3.00 mm × 4.90 mm D (SOIC, 14) 8.65 mm × 6.00 mm DYY (SOT-23, 14) 4.20 mm × 3.26 mm PW (TSSOP, 14) 5.00 mm × 6.40 mm For all available packages, see the orderable addendum at the end of the data sheet. The package size (length × width) is a nominal value and includes pins, where applicable. RF R1 VOUT VIN C1 f-3 dB = ( RF VOUT = 1+ RG VIN (( 1 1 + sR1C1 1 2pR1C1 ( TLV935x-Q1 in a Single-Pole, Low-Pass Filter An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TLV9351-Q1, TLV9352-Q1, TLV9354-Q1 www.ti.com SBOSA34D – JANUARY 2021 – REVISED JUNE 2023 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Pin Configuration and Functions...................................3 6 Specifications.................................................................. 6 6.1 Absolute Maximum Ratings........................................ 6 6.2 ESD Ratings............................................................... 6 6.3 Recommended Operating Conditions.........................6 6.4 Thermal Information for Single Channel..................... 6 6.5 Thermal Information for Dual Channel........................7 6.6 Thermal Information for Quad Channel...................... 7 6.7 Electrical Characteristics.............................................8 6.8 Typical Characteristics.............................................. 10 7 Detailed Description......................................................17 7.1 Overview................................................................... 17 7.2 Functional Block Diagram......................................... 17 7.3 Feature Description...................................................18 7.4 Device Functional Modes..........................................25 8 Application and Implementation.................................. 26 8.1 Application Information............................................. 26 8.2 Typical Applications.................................................. 26 8.3 Power Supply Recommendations.............................27 8.4 Layout....................................................................... 27 9 Device and Documentation Support............................30 9.1 Device Support......................................................... 30 9.2 Documentation Support............................................ 30 9.3 Receiving Notification of Documentation Updates....30 9.4 Support Resources................................................... 30 9.5 Trademarks............................................................... 30 9.6 Electrostatic Discharge Caution................................31 9.7 Glossary....................................................................31 10 Mechanical, Packaging, and Orderable Information.................................................................... 31 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (September 2021) to Revision D (June 2023) Page • Add the 8-pin TSSOP (PW) package throughout data sheet............................................................................. 1 Changes from Revision B (May 2021) to Revision C (September 2021) Page • Deleted preview note from SOIC (14) package throughout data sheet. ............................................................1 • Deleted preview note from SOT-23 (14) package throughout data sheet. ........................................................ 1 • Deleted preview note from SOIC (8) package throughout data sheet. ..............................................................1 • Deleted preview note from SOT-23 (5) package throughout data sheet. .......................................................... 1 Changes from Revision A (March 2021) to Revision B (May 2021) Page • Deleted preview note from TSSOP (14) package throughout data sheet. ........................................................ 1 • Deleted preview note from PW package in Thermal Information for Quad Channel table................................. 7 Changes from Revision * (January 2021) to Revision A (March 2021) Page • Changed device status from Advance Information to Production Data ............................................................. 1 2 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLV9351-Q1 TLV9352-Q1 TLV9354-Q1 TLV9351-Q1, TLV9352-Q1, TLV9354-Q1 www.ti.com SBOSA34D – JANUARY 2021 – REVISED JUNE 2023 5 Pin Configuration and Functions OUT 1 V± 2 IN+ 3 5 V+ 4 IN± Not to scale Figure 5-1. TLV9351-Q1 DBV Package, 5-Pin SOT-23 (Top View) Table 5-1. Pin Functions: TLV9351-Q1 PIN NAME TYPE(1) NO. IN+ 3 IN– OUT DESCRIPTION I Noninverting input 4 I Inverting input 1 O Output V+ 5 — Positive (highest) power supply V– 2 — Negative (lowest) power supply (1) I = input, O = output Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLV9351-Q1 TLV9352-Q1 TLV9354-Q1 Submit Document Feedback 3 TLV9351-Q1, TLV9352-Q1, TLV9354-Q1 www.ti.com SBOSA34D – JANUARY 2021 – REVISED JUNE 2023 OUT1 1 8 V+ IN1± 2 7 OUT2 IN1+ 3 6 IN2± V± 4 5 IN2+ Not to scale Figure 5-2. TLV9352-Q1 D, PW and DGK Package, 8-Pin SOIC, TSSOP and VSSOP (Top View) Table 5-2. Pin Functions: TLV9352-Q1 PIN NAME TYPE(1) DESCRIPTION IN1+ 3 I Noninverting input, channel 1 IN2+ 5 I Noninverting input, channel 1 IN1– 2 I Inverting input, channel 1 IN2– 6 I Inverting input, channel 2 OUT1 1 O Output, channel 1 OUT2 7 O Output, channel 2 V+ 8 — Positive (highest) power supply V– 4 — Negative (lowest) power supply (1) 4 NO. I = input, O = output Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLV9351-Q1 TLV9352-Q1 TLV9354-Q1 TLV9351-Q1, TLV9352-Q1, TLV9354-Q1 www.ti.com SBOSA34D – JANUARY 2021 – REVISED JUNE 2023 OUT1 1 14 OUT4 IN1± 2 13 IN4± IN1+ 3 12 IN4+ V+ 4 11 V± IN2+ 5 10 IN3+ IN2± 6 9 IN3± OUT2 7 8 OUT3 Not to scale Figure 5-3. TLV9354-Q1 D, DYY, and PW Package, 14-Pin SOIC, SOT-23, and TSSOP (Top View) Table 5-3. Pin Functions: TLV9354-Q1 PIN NAME TYPE(1) NO. DESCRIPTION IN1+ 3 I Noninverting input, channel 1 IN2+ 5 I Noninverting input, channel 2 IN3+ 10 I Noninverting input, channel 3 IN4+ 12 I Noninverting input, channel 4 IN1– 2 I Inverting input, channel 1 IN2– 6 I Inverting input, channel 2 IN3– 9 I Inverting input, channel 3 IN4– 13 I Inverting input, channel 4 OUT1 1 O Output, channel 1 OUT2 7 O Output, channel 2 OUT3 8 O Output, channel 3 OUT4 14 O Output, channel 4 V+ 4 — Positive (highest) power supply V– 11 — Negative (lowest) power supply (1) I = input, O = output Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLV9351-Q1 TLV9352-Q1 TLV9354-Q1 Submit Document Feedback 5 TLV9351-Q1, TLV9352-Q1, TLV9354-Q1 www.ti.com SBOSA34D – JANUARY 2021 – REVISED JUNE 2023 6 Specifications 6.1 Absolute Maximum Ratings over operating ambient temperature range (unless otherwise noted) (1) MIN MAX 0 42 V (V–) – 0.5 (V+) + 0.5 V Supply voltage, VS = (V+) – (V–) Common-mode voltage (3) Differential voltage(3) Signal input pins VS + 0.2 Current (3) –10 Output short-circuit (2) –55 Junction temperature, TJ Storage temperature, Tstg (2) (3) V 10 mA 150 °C 150 °C 150 °C Continuous Operating ambient temperature, TA (1) UNIT –65 Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. Short-circuit to ground, one amplifier per package. Input pins are diode-clamped to the power-supply rails. Input signals that may swing more than 0.5 V beyond the supply rails must be current limited to 10 mA or less. 6.2 ESD Ratings VALUE V(ESD) (1) Electrostatic discharge Human body model (HBM), per AEC Q100-002(1) UNIT ±2000 Charged device model (CDM), per AEC Q100-011 V ±1000 AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification. 6.3 Recommended Operating Conditions over operating ambient temperature range (unless otherwise noted) MIN VS Supply voltage, (V+) – (V–) VI Input voltage range TA Specified ambient temperature MAX UNIT 4.5 40 (V–) – 0.1 (V+) – 2 V V –40 125 °C 6.4 Thermal Information for Single Channel TLV9351-Q1 DBV (SOT-23) THERMAL METRIC (1) UNIT 5 PINS RθJA Junction-to-ambient thermal resistance 187.4 °C/W RθJC(top) Junction-to-case (top) thermal resistance 86.2 °C/W RθJB Junction-to-board thermal resistance 54.6 °C/W ψJT Junction-to-top characterization parameter 27.8 °C/W ψJB Junction-to-board characterization parameter 54.3 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W (1) 6 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLV9351-Q1 TLV9352-Q1 TLV9354-Q1 TLV9351-Q1, TLV9352-Q1, TLV9354-Q1 www.ti.com SBOSA34D – JANUARY 2021 – REVISED JUNE 2023 6.5 Thermal Information for Dual Channel TLV9352-Q1 THERMAL METRIC (1) D (SOIC) DGK (VSSOP) PW (TSSOP) 8 PINS 8 PINS 8 PINS UNIT RθJA Junction-to-ambient thermal resistance 132.6 176.5 185.1 °C/W RθJC(top) Junction-to-case (top) thermal resistance 73.4 68.1 74.0 °C/W RθJB Junction-to-board thermal resistance 76.1 98.2 115.7 °C/W ψJT Junction-to-top characterization parameter 24.0 12.0 12.3 °C/W ψJB Junction-to-board characterization parameter 75.4 96.7 114.0 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. 6.6 Thermal Information for Quad Channel TLV9354-Q1 THERMAL METRIC (1) D (SOIC) DYY (SOT-23) PW (TSSOP) 14 PINS UNIT 14 PINS 14 PINS RθJA Junction-to-ambient thermal resistance 101.4 110.7 118 °C/W RθJC(top) Junction-to-case (top) thermal resistance 57.6 55.9 47.6 °C/W RθJB Junction-to-board thermal resistance 57.3 35.3 60.9 °C/W ψJT Junction-to-top characterization parameter 18.5 2.3 6 °C/W ψJB Junction-to-board characterization parameter 56.9 35.1 60.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLV9351-Q1 TLV9352-Q1 TLV9354-Q1 Submit Document Feedback 7 TLV9351-Q1, TLV9352-Q1, TLV9354-Q1 www.ti.com SBOSA34D – JANUARY 2021 – REVISED JUNE 2023 6.7 Electrical Characteristics For VS = (V+) – (V–) = 4.5 V to 40 V (±2.25 V to ±20 V) at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VO UT = VS / 2, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX ±0.35 ±1.8 UNIT OFFSET VOLTAGE VOS Input offset voltage VCM = V– dVOS/dT Input offset voltage drift PSRR Input offset voltage versus power supply VCM = V– Channel separation f = 0 Hz TA = –40°C to 125°C ±2 TA = –40°C to 125°C ±1.5 TA = –40°C to 125°C ±2 mV µV/℃ ±5 5 μV/V µV/V INPUT BIAS CURRENT IB Input bias current ±10 pA IOS Input offset current ±10 pA NOISE 2 EN Input voltage noise f = 0.1 Hz to 10 Hz eN Input voltage noise density f = 1 kHz 15 f = 10 kHz 14 iN Input current noise f = 1 kHz 2 μVPP 0.33 µVRMS nV/√Hz fA/√Hz INPUT VOLTAGE RANGE VCM Common-mode voltage range CMRR VS = 40 V, (V–) – 0.1 V < VCM < (V+) Common-mode rejection – 2 V (Main input pair) TA = –40°C to 125°C ratio VS = 4.5 V, (V–) – 0.1 V < VCM < (V+) – 2 V (Main input pair) (V–) – 0.2 (V+) – 2 95 110 82 90 V dB INPUT CAPACITANCE ZID Differential ZICM Common-mode 100 || 3 MΩ || pF 6 || 1 TΩ || pF OPEN-LOOP GAIN AOL 8 Open-loop voltage gain Submit Document Feedback VS = 40 V, VCM = V– (V–) + 0.1 V < VO < (V+) – 0.1 V 120 TA = –40°C to 125°C 130 127 dB Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLV9351-Q1 TLV9352-Q1 TLV9354-Q1 TLV9351-Q1, TLV9352-Q1, TLV9354-Q1 www.ti.com SBOSA34D – JANUARY 2021 – REVISED JUNE 2023 6.7 Electrical Characteristics (continued) For VS = (V+) – (V–) = 4.5 V to 40 V (±2.25 V to ±20 V) at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VO UT = VS / 2, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT FREQUENCY RESPONSE GBW Gain-bandwidth product SR Slew rate tS Settling time VS = 40 V, G = +1, CL = 20 pF MHz 20 V/μs To 0.01%, VS = 40 V, VSTEP = 10 V , G = +1, CL = 20 pF 5 To 0.01%, VS = 40 V, VSTEP = 2 V , G = +1, CL = 20 pF 4 To 0.1%, VS = 40 V, VSTEP = 10 V , G = +1, CL = 20 pF 4 To 0.1%, VS = 40 V, VSTEP = 2 V , G = +1, CL = 20 pF THD+N 3.5 Phase margin G = +1, RL = 10 kΩ Overload recovery time VIN × gain > VS Total harmonic distortion + noise (1) VS = 40 V, VO = 1 VRMS, G = 1, f = 1 kHz μs 3 60 ° 600 ns 0.001% OUTPUT VS = 40 V, RL = no load(2) Voltage output swing from rail Positive and negative rail headroom 5 10 VS = 40 V, RL = 10 kΩ 50 55 VS = 40 V, RL = 2 kΩ 200 250 VS = 4.5 V, RL = no load(2) VS = 4.5 V, RL = 10 kΩ VS = 4.5 V, RL = 2 kΩ 1 20 30 40 75 mV ISC Short-circuit current ±60 mA CLOAD Capacitive load drive 300 pF ZO Open-loop output impedance 600 Ω f = 1 MHz, IO = 0 A POWER SUPPLY IQ (1) (2) Quiescent current per amplifier VCM = V–, IO = 0 A 650 TA = –40°C to 125°C 800 850 µA Third-order filter; bandwidth = 80 kHz at –3 dB. Specified by characterization only. Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLV9351-Q1 TLV9352-Q1 TLV9354-Q1 Submit Document Feedback 9 TLV9351-Q1, TLV9352-Q1, TLV9354-Q1 www.ti.com SBOSA34D – JANUARY 2021 – REVISED JUNE 2023 6.8 Typical Characteristics at TA = 25°C, VS = ±20 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 10 pF (unless otherwise noted) 50 33 30 27 40 Population (%) Population (%) 24 21 18 15 12 30 20 9 10 6 D001 Offset Voltage (µV) 900 400 700 300 Offset Voltage (µV) 100 -100 -300 0.8 0.7 0.6 100 0 -100 -200 -300 -700 -20 0 20 40 60 80 Temperature (°C) 100 120 -400 -40 140 -20 0 D004 20 40 60 80 Temperature (°C) 800 600 600 400 400 Offset Voltage (µV) 800 200 0 -200 -200 -600 -600 0 VCM 5 10 15 20 -800 16 16.5 17 17.5 D005 TA = 25°C Figure 6-5. Offset Voltage vs Common-Mode Voltage Submit Document Feedback D003 0 -400 -5 140 200 -400 -10 120 Figure 6-4. Offset Voltage vs Temperature Figure 6-3. Offset Voltage vs Temperature -15 100 VCM = V– VCM = V+ Offset Voltage (µV) 0.5 200 300 -500 10 0.4 Figure 6-2. Offset Voltage Drift Distribution 500 Offset Voltage (µV) 0.3 Distribution from 60 amplifiers Distribution from 15462 amplifiers, TA = 25°C -800 -20 D002 Offset Voltage Drift (µV/C) Figure 6-1. Offset Voltage Production Distribution -900 -40 0.2 600 480 360 240 120 0 -120 -240 -360 -480 -600 0.1 0 0 0 3 18 VCM 18.5 19 19.5 20 D005 TA = 25°C Figure 6-6. Offset Voltage vs Common-Mode Voltage (Transition Region) Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLV9351-Q1 TLV9352-Q1 TLV9354-Q1 TLV9351-Q1, TLV9352-Q1, TLV9354-Q1 www.ti.com SBOSA34D – JANUARY 2021 – REVISED JUNE 2023 6.8 Typical Characteristics (continued) 800 800 600 600 400 400 Offset Voltage (µV) 200 0 -200 200 0 -200 -400 -400 -600 -600 -800 -20 -15 -10 -5 0 VCM 5 10 15 -800 -20 20 -15 -10 -5 D006 TA = 125°C 10 15 20 D007 Figure 6-8. Offset Voltage vs Common-Mode Voltage 600 100 500 90 400 80 200 Gain (dB) 175 Phase ( ) 150 300 70 125 200 60 100 50 75 40 50 30 25 -200 20 0 -300 10 -25 -400 0 -50 -500 -10 -75 -600 -20 100 Gain (dB) Offset Voltage (µV) 5 TA = –40°C Figure 6-7. Offset Voltage vs Common-Mode Voltage 100 0 -100 0 5 10 15 20 25 30 Supply Voltage (V) 35 40 45 1k D008 10k 100k Frequency (Hz) -100 10M 1M C002 CL = 20 pF . Figure 6-10. Open-Loop Gain and Phase vs Frequency Figure 6-9. Offset Voltage vs Power Supply 80 6 60 50 Input Bias and Offset Current (pA) G= 1 G=1 G = 10 G = 100 G = 1000 70 Closed-Loop Gain (dB) 0 VCM Phase ( ) Offset Voltage (µV) at TA = 25°C, VS = ±20 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 10 pF (unless otherwise noted) 40 30 20 10 0 -10 -20 100 1k 10k 100k Frequency (Hz) 1M 3 1.5 0 -1.5 -3 -4.5 C001 IB IB+ IOS -6 -7.5 -20 10M Figure 6-11. Closed-Loop Gain vs Frequency 4.5 -16 -12 -8 -4 0 4 8 Common Mode Voltage (V) 12 16 20 D010 Figure 6-12. Input Bias Current vs Common-Mode Voltage Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLV9351-Q1 TLV9352-Q1 TLV9354-Q1 Submit Document Feedback 11 TLV9351-Q1, TLV9352-Q1, TLV9354-Q1 www.ti.com SBOSA34D – JANUARY 2021 – REVISED JUNE 2023 6.8 Typical Characteristics (continued) at TA = 25°C, VS = ±20 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 10 pF (unless otherwise noted) V+ IB IB+ IOS 125 100 75 Output Voltage (V) Input Bias and Offset Current (pA) 150 50 25 0 -25 V+ 1V V+ 2V V+ 3V V+ 4V V+ 5V V+ 6V V+ 7V -50 V+ 8V -75 V+ 9V -100 -40 V+ -20 0 20 40 60 80 Temperature (°C) 100 120 10 V 140 0 10 20 D011 Figure 6-13. Input Bias Current vs Temperature 30 40 50 60 70 Output Current (mA) 100 D012 CMRR PSRR+ PSRR 120 CMRR and PSRR (dB) V +6V V +5V V +4V V +3V V +2V V +1V 105 90 75 60 45 30 15 V 0 10 20 30 40 50 60 70 Output Current (mA) 80 90 0 100 100 1k 10k 100k Frequency (Hz) D012 . C003 Figure 6-16. CMRR and PSRR vs Frequency Power Supply Rejection Ratio (dB) 130 125 120 115 PMOS (VCM NMOS (VCM V+ V+ 1.5 V) 1.5 V) 105 100 95 90 85 -40 10M 170 135 110 1M . Figure 6-15. Output Voltage Swing vs Output Current (Sinking) Common-Mode Rejection Ratio (dB) 90 135 -40°C 25°C 125°C V +7V -20 0 20 40 60 80 Temperature (°C) 100 120 140 D015 165 160 155 150 145 140 -40 -20 0 20 40 60 80 Temperature (°C) f = 0 Hz Figure 6-17. CMRR vs Temperature (dB) 12 80 Figure 6-14. Output Voltage Swing vs Output Current (Sourcing) V +8V Output Voltage (V) -40°C 25°C 125°C Submit Document Feedback 100 120 140 D016 f = 0 Hz Figure 6-18. PSRR vs Temperature (dB) Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLV9351-Q1 TLV9352-Q1 TLV9354-Q1 TLV9351-Q1, TLV9352-Q1, TLV9354-Q1 www.ti.com SBOSA34D – JANUARY 2021 – REVISED JUNE 2023 6.8 Typical Characteristics (continued) Input Voltage Noise Spectral Density (nV/ Hz) at TA = 25°C, VS = ±20 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 10 pF (unless otherwise noted) 1 0.8 Amplitude (uV) 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 200 100 10 1 1 Time (1s/div) 10 C019 -32 100k C017 -32 RL = 10 k RL = 2 k RL = 604 RL = 128 -40 -48 RL = 128 RL = 604 RL = 2 k RL = 10 k -40 -48 -56 THD+N (dB) -56 THD+N (dB) 10k Figure 6-20. Input Voltage Noise Spectral Density vs Frequency Figure 6-19. 0.1-Hz to 10-Hz Noise -64 -72 -80 -88 -64 -72 -80 -88 -96 -96 -104 -104 -112 0.001 -112 100 1k Frequency (Hz) 10k 0.01 C012 BW = 80 kHz, VOUT = 1 VRMS 675 560 650 Quiescent current (µA) 700 570 550 540 530 520 510 575 550 525 500 475 480 12 16 20 24 28 Supply Voltage (V) C023 600 490 8 10 20 625 500 4 1 Figure 6-22. THD+N vs Output Amplitude 580 0 0.1 Amplitude (Vrms) BW = 80 kHz, f = 1 kHz Figure 6-21. THD+N Ratio vs Frequency Quiescent current (µA) 100 1k Frequency (Hz) 32 36 40 D021 450 -40 -20 0 20 40 60 80 Temperature (°C) VCM = V– Figure 6-23. Quiescent Current vs Supply Voltage 100 120 140 D022 . Figure 6-24. Quiescent Current vs Temperature Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLV9351-Q1 TLV9352-Q1 TLV9354-Q1 Submit Document Feedback 13 TLV9351-Q1, TLV9352-Q1, TLV9354-Q1 www.ti.com SBOSA34D – JANUARY 2021 – REVISED JUNE 2023 6.8 Typical Characteristics (continued) at TA = 25°C, VS = ±20 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 10 pF (unless otherwise noted) 140 700 135 130 125 120 115 -40 -20 0 20 40 60 80 Temperature (°C) 100 120 650 Open-loop output impedance (ohms) Open Loop Voltage Gain (dB) VS = 4 V VS = 40 V 600 550 500 450 400 350 300 250 200 150 100 140 D023 Figure 6-25. Open-Loop Voltage Gain vs Temperature (dB) 1k 10k 100k Frequency (Hz) 1M 10M C013 Figure 6-26. Open-Loop Output Impedance vs Frequency 80 60 70 50 Overshoot (%) Overshoot (%) 60 40 30 20 40 30 20 RISO = 0 , Positive Overshoot RISO = 0 , Negative Overshoot RISO = 50 , Positive Overshoot RISO = 50 , Negative Overshoot 10 50 RISO = 0 , Positive Overshoot RISO = 0 , Negative Overshoot RISO = 50 , Positive Overshoot RISO = 50 , Negative Overshoot 10 0 0 0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 Cap Load (pF) C007 0 G = –1, 10-mV output step Figure 6-27. Small-Signal Overshoot vs Capacitive Load 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 Cap Load (pF) C008 G = 1, 10-mV output step Figure 6-28. Small-Signal Overshoot vs Capacitive Load 60 Input Output Amplitude (4V/div) Phase Margin (Degree) 50 40 30 20 10 0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 Cap Load (pF) C009 Figure 6-29. Phase Margin vs Capacitive Load Submit Document Feedback C016 VIN = ±20 V; VS = VOUT = ±17 V . 14 Time (20us/div) Figure 6-30. No Phase Reversal Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLV9351-Q1 TLV9352-Q1 TLV9354-Q1 TLV9351-Q1, TLV9352-Q1, TLV9354-Q1 www.ti.com SBOSA34D – JANUARY 2021 – REVISED JUNE 2023 6.8 Typical Characteristics (continued) at TA = 25°C, VS = ±20 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 10 pF (unless otherwise noted) Voltage (5V/div) Input Output Voltage (5V/div) Input Output Time (100ns/div) Time (100ns/div) C018 C018 G = –10 G = –10 Figure 6-31. Positive Overload Recovery Figure 6-32. Negative Overload Recovery Amplitude (5mV/div) Amplitude (5mV/div) Input Output Input Output Time (1µs/div) Time (300ns/div) C011 C010 CL = 20 pF, G = –1, 20-mV step response CL = 20 pF, G = 1, 20-mV step response Figure 6-34. Small-Signal Step Response Figure 6-33. Small-Signal Step Response, Rising Amplitude (2V/div) Amplitude (2V/div) Input Output Input Output Time (300ns/div) Time (300ns/div) C005 CL = 20 pF, G = 1 Figure 6-35. Large-Signal Step Response (Rising) C005 CL = 20 pF, G = 1 Figure 6-36. Large-Signal Step Response (Falling) Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLV9351-Q1 TLV9352-Q1 TLV9354-Q1 Submit Document Feedback 15 TLV9351-Q1, TLV9352-Q1, TLV9354-Q1 www.ti.com SBOSA34D – JANUARY 2021 – REVISED JUNE 2023 6.8 Typical Characteristics (continued) at TA = 25°C, VS = ±20 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 10 pF (unless otherwise noted) Large Signal Step Response (2V/div) 100 80 60 Output Current (mA) Input Output 40 20 Sourcing Sinking 0 -20 -40 -60 -80 -100 -40 Time (2µs/div) -20 0 C021 20 40 60 80 Temperature (°C) 140 D014 Figure 6-38. Short-Circuit Current vs Temperature Figure 6-37. Large-Signal Step Response 45 -50 VS = 40 V VS = 30 V VS = 15 V VS = 2.7 V 35 -60 Channel Seperation (dB) 40 Maximum Output Swing (V) 120 . CL = 20 pF, G = –1 30 25 20 15 10 -70 -80 -90 -100 -110 -120 5 0 1k 100 10k 100k Frequency (Hz) 1M -130 100 10M 1k C020 Figure 6-39. Maximum Output Voltage vs Frequency 10k 100k Frequency (Hz) 1M 10M C014 Figure 6-40. Channel Separation vs Frequency 110 100 Gain(dB) 90 80 70 60 50 40 1M 10M 100M Frequency (Hz) 1G C004 Figure 6-41. EMIRR (Electromagnetic Interference Rejection Ratio) at Inputs vs Frequency 16 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLV9351-Q1 TLV9352-Q1 TLV9354-Q1 TLV9351-Q1, TLV9352-Q1, TLV9354-Q1 www.ti.com SBOSA34D – JANUARY 2021 – REVISED JUNE 2023 7 Detailed Description 7.1 Overview The TLV935x-Q1 family (TLV9351-Q1, TLV9352-Q1, and TLV9354-Q1) is a family of 40-V, cost-optimized automotive operational amplifiers. These devices offer strong general-purpose DC and AC specifications, including rail-to-rail output, low offset (±350 µV, typ), low offset drift (±1.5 µV/°C, typ), and 3.5-MHz bandwidth. Convenient features such as wide differential input-voltage range, high output current (±60 mA), and high slew rate (20 V/μs) make the TLV935x-Q1 a robust operational amplifier for high-voltage, cost-sensitive applications. The TLV935x-Q1 family of op amps is available in standard packages and is specified from –40°C to 125°C. 7.2 Functional Block Diagram V+ Reference Current V V INÛ IN+ V BIAS1 Class AB Control Circuitry V O V BIAS2 VÛ (Ground) Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLV9351-Q1 TLV9352-Q1 TLV9354-Q1 Submit Document Feedback 17 TLV9351-Q1, TLV9352-Q1, TLV9354-Q1 www.ti.com SBOSA34D – JANUARY 2021 – REVISED JUNE 2023 7.3 Feature Description 7.3.1 Input Protection Circuitry The TLV935x-Q1 uses a patented input architecture to eliminate the requirement for input protection diodes but still provides robust input protection under transient conditions. Figure 7-1 shows conventional input diode protection schemes that are activated by fast transient step responses and introduce signal distortion and settling time delays because of alternate current paths, as shown in Figure 7-2. For low-gain circuits, these fast-ramping input signals forward-bias back-to-back diodes, causing an increase in input current and resulting in extended settling time. V+ V+ VIN+ VIN+ VOUT TLV935x-Q1 40 V VOUT ~0.7 V VIN VIN V OPAx990 Provides Full 40-V Differential Input Range V Conventional Input Protection Limits Differential Input Range Figure 7-1. TLV935x-Q1 Input Protection Does Not Limit Differential Input Capability Vn = 10 V RFILT 10 V 1 Ron_mux Sn 1 D 10 V CFILT 2 ~±9.3 V CS CD Vn+1 = ±10 V RFILT ±10 V Ron_mux Sn+1 VIN± 2 ~0.7 V CS CFILT VOUT Idiode_transient ±10 V Input Low-Pass Filter VIN+ Buffer Amplifier Simplified Mux Model Figure 7-2. Back-to-Back Diodes Create Settling Issues The TLV935x-Q1 family of operational amplifiers provides a true high-impedance differential input capability for high-voltage applications. This patented input protection architecture does not introduce additional signal distortion or delayed settling time, making the device an optimal op amp for multichannel, high-switched, input applications. The TLV935x-Q1 tolerates a maximum differential swing (voltage between inverting and noninverting pins of the op amp) of up to 40 V, making the device suitable for use as a comparator or in applications with fast-ramping input signals. 18 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLV9351-Q1 TLV9352-Q1 TLV9354-Q1 TLV9351-Q1, TLV9352-Q1, TLV9354-Q1 www.ti.com SBOSA34D – JANUARY 2021 – REVISED JUNE 2023 7.3.2 EMI Rejection The TLV935x-Q1 uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI from sources such as wireless communications and densely-populated boards with a mix of analog signal chain and digital components. EMI immunity can be improved with circuit design techniques; the TLV935x-Q1 benefits from these design improvements. Texas Instruments has developed the ability to accurately measure and quantify the immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz. Figure 7-3 shows the results of this testing on the TLV935x-Q1. Table 7-1 provides the EMIRR IN+ values for the TLV935x-Q1 at particular frequencies commonly encountered in real-world applications. Table 7-1 lists applications that may be centered on or operated near the particular frequency shown. The EMI Rejection Ratio of Operational Amplifiers application report contains detailed information on the topic of EMIRR performance as it relates to op amps and is available for download from www.ti.com. 110 100 Gain(dB) 90 80 70 60 50 40 1M 10M 100M Frequency (Hz) 1G C004 Figure 7-3. EMIRR Testing Table 7-1. TLV935x-Q1 EMIRR IN+ for Frequencies of Interest FREQUENCY APPLICATION OR ALLOCATION EMIRR IN+ 400 MHz Mobile radio, mobile satellite, space operation, weather, radar, ultra-high frequency (UHF) applications 71 dB 900 MHz Global system for mobile communications (GSM) applications, radio communication, navigation, GPS (to 1.6 GHz), GSM, aeronautical mobile, UHF applications 80 dB 1.8 GHz GSM applications, mobile personal communications, broadband, satellite, L-band (1 GHz to 2 GHz) 87 dB 2.4 GHz 802.11b, 802.11g, 802.11n, Bluetooth®, mobile personal communications, industrial, scientific and medical (ISM) radio band, amateur radio and satellite, S-band (2 GHz to 4 GHz) 90 dB 3.6 GHz Radiolocation, aero communication and navigation, satellite, mobile, S-band 92 dB 802.11a, 802.11n, aero communication and navigation, mobile communication, space and satellite operation, C-band (4 GHz to 8 GHz) 94 dB 5 GHz Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLV9351-Q1 TLV9352-Q1 TLV9354-Q1 Submit Document Feedback 19 TLV9351-Q1, TLV9352-Q1, TLV9354-Q1 www.ti.com SBOSA34D – JANUARY 2021 – REVISED JUNE 2023 7.3.3 Phase Reversal Protection The TLV935x-Q1 family has internal phase-reversal protection. Many op amps exhibit a phase reversal when the input is driven beyond its linear common-mode range. This condition is most often encountered in noninverting circuits when the input is driven beyond the specified common-mode voltage range, causing the output to reverse into the opposite rail. The TLV935x-Q1 is a rail-to-rail input op amp; therefore, the common-mode range can extend up to the rails. Input signals beyond the rails do not cause phase reversal; instead, the output limits into the appropriate rail. 7.3.4 Thermal Protection VOUT The internal power dissipation of any amplifier causes its internal (junction) temperature to rise. This phenomenon is called self heating. The absolute maximum junction temperature of the TLV935x-Q1 is 150°C. Exceeding this temperature causes damage to the device. The TLV935x-Q1 has a thermal protection feature that prevents damage from self heating. The protection works by monitoring the temperature of the device and turning off the op amp output drive for temperatures above 140°C. Figure 7-4 shows an application example for the TLV9351-Q1 that has significant self heating (159°C) because of its power dissipation (0.81 W). Thermal calculations indicate that for an ambient temperature of 65°C the device junction temperature will reach 187°C. The actual device, however, turns off the output drive to maintain a safe junction temperature. Figure 7-4 shows how the circuit behaves during thermal protection. During normal operation, the device acts as a buffer so the output is 3 V. When self heating causes the device junction temperature to increase above 140°C, the thermal protection forces the output to a high-impedance state and the output is pulled to ground through resistor RL. 3V TA = 65°C PD = 0.81W JA = 138.7°C/W 0V TJ = 138.7°C/W × 0.81W + 65°C TJ = 177.3°C (expected) 30 V 150°C TLV9351 + – VIN 3V + RL 3V 100
– 140ºC Temperature IOUT = 30 mA Figure 7-4. Thermal Protection 20 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLV9351-Q1 TLV9352-Q1 TLV9354-Q1 TLV9351-Q1, TLV9352-Q1, TLV9354-Q1 www.ti.com SBOSA34D – JANUARY 2021 – REVISED JUNE 2023 7.3.5 Capacitive Load and Stability The TLV935x-Q1 features a resistive output stage capable of driving smaller capacitive loads, and by leveraging an isolation resistor, the device can easily be configured to drive large capacitive loads. Increasing the gain enhances the ability of the amplifier to drive greater capacitive loads; see Figure 7-5 and Figure 7-6. The particular op amp circuit configuration, layout, gain, and output loading are some of the factors to consider when establishing whether an amplifier is stable in operation. 80 60 70 50 Overshoot (%) Overshoot (%) 60 50 40 30 20 RISO = 0 , Positive Overshoot RISO = 0 , Negative Overshoot RISO = 50 , Positive Overshoot RISO = 50 , Negative Overshoot 10 40 30 20 RISO = 0 , Positive Overshoot RISO = 0 , Negative Overshoot RISO = 50 , Positive Overshoot RISO = 50 , Negative Overshoot 10 0 0 0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 Cap Load (pF) C008 0 Figure 7-5. Small-Signal Overshoot vs Capacitive Load (100-mV Output Step, G = 1) 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 Cap Load (pF) C007 Figure 7-6. Small-Signal Overshoot vs Capacitive Load (100-mV Output Step, G = –1) For additional drive capability in unity-gain configurations, improve capacitive load drive by inserting a small (10 Ω to 20 Ω) resistor, RISO, in series with the output, as shown in Figure 7-7. This resistor significantly reduces ringing and maintains DC performance for purely capacitive loads. However, if a resistive load is in parallel with the capacitive load, then a voltage divider is created, thus introducing a gain error at the output and slightly reducing the output swing. The error introduced is proportional to the ratio RISO / RL, and is generally negligible at low output levels. A high capacitive load drive makes the TLV935x-Q1 well suited for applications such as reference buffers, MOSFET gate drives, and cable-shield drives. The circuit shown in Figure 7-7 uses an isolation resistor, RISO, to stabilize the output of an op amp. RISO modifies the open-loop gain of the system for increased phase margin. For additional information on techniques to optimize and design using this circuit, TI Precision Design TIDU032 details complete design goals, simulation, and test results. +Vs Vout Riso + Vin + ± Cload -Vs Figure 7-7. Extending Capacitive Load Drive With the TLV9351-Q1 Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLV9351-Q1 TLV9352-Q1 TLV9354-Q1 Submit Document Feedback 21 TLV9351-Q1, TLV9352-Q1, TLV9354-Q1 www.ti.com SBOSA34D – JANUARY 2021 – REVISED JUNE 2023 7.3.6 Common-Mode Voltage Range The TLV935x-Q1 is a 40-V, rail-to-rail output operational amplifier with an input common-mode range that extends 100 mV beyond V– and within 2 V of V+ for normal operation. The device accomplishes this performance through a complementary input stage, using a P-channel differential pair. Additionally, a complementary N-channel differential pair has been included in parallel with the P-channel pair to eliminate common undesirable op amp behaviors, such as phase reversal. The TLV935x-Q1 can operate with common mode ranges beyond 100 mV of the top rail, but with reduced performance above (V+) – 2 V. The N-channel pair is active for input voltages close to the positive rail, typically (V+) – 1 V to 100 mV above the positive supply. The P-channel pair is active for inputs from 100 mV below the negative supply to approximately (V+) – 2 V. There is a small transition region, typically (V+) –2 V to (V+) – 1 V in which both input pairs are on. This transition region can vary modestly with process variation, and within the transition region and N-channel region, many specifications of the op amp, including PSRR, CMRR, offset voltage, offset drift, noise and THD performance may be degraded compared to operation within the P-channel region. Table 7-2. Typical Performance for Common-Mode Voltages Within 2 V of the Positive Supply PARAMETER Input common-mode voltage MIN TYP (V+) – 2 MAX (V+) + 0.1 Offset voltage 1.5 Offset voltage drift Common-mode rejection UNIT V mV 2 µV/°C 75 dB Open-loop gain 75 dB Gain-bandwidth product 1.5 MHz 22 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLV9351-Q1 TLV9352-Q1 TLV9354-Q1 TLV9351-Q1, TLV9352-Q1, TLV9354-Q1 www.ti.com SBOSA34D – JANUARY 2021 – REVISED JUNE 2023 7.3.7 Electrical Overstress Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress (EOS). These questions tend to focus on the device inputs, but may involve the supply voltage pins or even the output pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin. Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from accidental ESD events both before and during product assembly. Having a good understanding of this basic ESD circuitry and its relevance to an electrical overstress event is helpful. Figure 7-8 shows an illustration of the ESD circuits contained in the TLV935x-Q1 (indicated by the dashed line area). The ESD protection circuitry involves several current-steering diodes connected from the input and output pins and routed back to the internal power-supply lines, where the diodes meet at an absorption device or the power-supply ESD cell, internal to the operational amplifier. This protection circuitry is intended to remain inactive during normal circuit operation. TVS + – RF +VS VDD R1 RS IN– 100
IN+ 100 TLV935x-Q1 – + Power Supply ESD Cell ID VIN RL + – VSS + – –VS TVS Figure 7-8. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application An ESD event is very short in duration and very high voltage (for example, 1 kV, 100 ns), whereas an EOS event is long duration and lower voltage (for example, 50 V, 100 ms). The ESD diodes are designed for out-of-circuit ESD protection (that is, during assembly, test, and storage of the device before being soldered to the PCB). During an ESD event, the ESD signal is passed through the ESD steering diodes to an absorption circuit (labeled ESD power-supply circuit). The ESD absorption circuit clamps the supplies to a safe level. Although this behavior is necessary for out-of-circuit protection, excessive current and damage is caused if activated in-circuit. A transient voltage suppressors (TVS) can be used to prevent against damage caused by turning on the ESD absorption circuit during an in-circuit ESD event. Using the appropriate current limiting resistors and TVS diodes allows for the use of device ESD diodes to protect against EOS events. Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLV9351-Q1 TLV9352-Q1 TLV9354-Q1 Submit Document Feedback 23 TLV9351-Q1, TLV9352-Q1, TLV9354-Q1 www.ti.com SBOSA34D – JANUARY 2021 – REVISED JUNE 2023 7.3.8 Overload Recovery Overload recovery is defined as the time required for the op amp output to recover from a saturated state to a linear state. The output devices of the op amp enter a saturation region when the output voltage exceeds the rated operating voltage, either due to the high input voltage or the high gain. After the device enters the saturation region, the charge carriers in the output devices require time to return back to the linear state. After the charge carriers return back to the linear state, the device begins to slew at the specified slew rate. Thus, the propagation delay in case of an overload condition is the sum of the overload recovery time and the slew time. The overload recovery time for the TLV935x-Q1 is approximately 600 ns. 7.3.9 Typical Specifications and Distributions Designers often have questions about a typical specification of an amplifier to design a more robust circuit. Due to natural variation in process technology and manufacturing procedures, every specification of an amplifier will exhibit some amount of deviation from the ideal value, like an amplifier's input offset voltage. These deviations often follow Gaussian (bell curve), or normal distributions, and circuit designers can leverage this information to guardband their system, even when there is not a minimum or maximum specification in Section 6.7. 0.00002% 0.00312% 0.13185% 1 -61 1 -51 1 -41 2.145% 13.59% 34.13% 34.13% 13.59% 2.145% 1 -31 1 -21 1 -1 1 1 +1 0.13185% 0.00312% 0.00002% 1 1 1 1 +21 +31 +41 +51 +61 Figure 7-9. Ideal Gaussian Distribution Figure 7-9 shows an example distribution, where µ, or mu, is the mean of the distribution, and where σ, or sigma, is the standard deviation of a system. For a specification that exhibits this kind of distribution, approximately two-thirds (68.26%) of all units can be expected to have a value within one standard deviation, or one sigma, of the mean (from µ – σ to µ + σ). Depending on the specification, values listed in the typical column of Section 6.7 are represented in different ways. As a general rule, if a specification naturally has a nonzero mean (for example, like gain bandwidth), then the typical value is equal to the mean (µ). However, if a specification naturally has a mean near zero (like input offset voltage), then the typical value is equal to the mean plus one standard deviation (µ + σ) to most accurately represent the typical value. 24 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLV9351-Q1 TLV9352-Q1 TLV9354-Q1 TLV9351-Q1, TLV9352-Q1, TLV9354-Q1 www.ti.com SBOSA34D – JANUARY 2021 – REVISED JUNE 2023 This chart can be used to calculate approximate probability of a specification in a unit; for example, for TLV935xQ1, the typical input voltage offset is 350 µV, so 68.2% of all TLV935x-Q1 devices are expected to have an offset from –350 µV to 350 µV. At 4 σ (±1400 µV), 99.9937% of the distribution has an offset voltage less than ±1400 µV, which means 0.0063% of the population is outside of these limits, which corresponds to about 1 in 15,873 units. Specifications with a value in the minimum or maximum column are assured by TI, and units outside these limits will be removed from production material. For example, the TLV935x-Q1 family has a maximum offset voltage of 1.8 mV at 125°C, and even though this corresponds to about 5 σ (≈1 in 1.7 million units), which is extremely unlikely, TI assures that any unit with larger offset than 1.8 mV will be removed from production material. For specifications with no value in the minimum or maximum column, consider selecting a sigma value of sufficient guardband for the application, and design worst-case conditions using this value. For example, the 6-σ value corresponds to about 1 in 500 million units, which is an extremely unlikely chance, and could be an option as a wide guardband to design a system around. In this case, the TLV935x-Q1 family does not have a maximum or minimum for offset voltage drift, but based on the typical value of 1.5 µV/°C in Section 6.7, it can be calculated that the 6-σ value for offset voltage drift is about 9 µV/°C. When designing for worst-case system conditions, this value can be used to estimate the worst possible offset across temperature without having an actual minimum or maximum value. However, process variation and adjustments over time can shift typical means and standard deviations, and unless there is a value in the minimum or maximum specification column, TI cannot assure the performance of a device. This information should be used only to estimate the performance of a device. 7.4 Device Functional Modes The TLV935x-Q1 has a single functional mode and is operational when the power-supply voltage is greater than 4.5 V (±2.25 V). The maximum power supply voltage for the TLV935x-Q1 is 40 V (±20 V). Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLV9351-Q1 TLV9352-Q1 TLV9354-Q1 Submit Document Feedback 25 TLV9351-Q1, TLV9352-Q1, TLV9354-Q1 www.ti.com SBOSA34D – JANUARY 2021 – REVISED JUNE 2023 8 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. 8.1 Application Information The TLV935x-Q1 family offers excellent DC precision and DC performance. These devices operate up to 40-V supply rails and offer true rail-to-rail output, low offset voltage and offset voltage drift, as well as 3.5-MHz bandwidth and high output drive. These features make the TLV935x-Q1 a robust, high-performance operational amplifier for high-voltage cost-sensitive applications. 8.2 Typical Applications 8.2.1 High Voltage Precision Comparator Many different systems require controlled voltages across numerous system nodes for robust operation. A comparator can be used to monitor and control voltages by comparing a reference threshold voltage with an input voltage and providing an output when the input crosses this threshold. The TLV935x-Q1 family of op amps make excellent high voltage comparators due to their MUX-friendly input stage (for more information, see Section 7.3.1). Previous generation high-voltage op amps often use back-toback diodes across the inputs to prevent damage to the op amp which greatly limits these op amps to be used as comparators, but the TLV935x-Q1's patented input stage allows the device to have a wide differential voltage between the inputs. V+ + VIN VOUT VTH V+ R1 R2 Figure 8-1. Typical Comparator Application 8.2.1.1 Design Requirements The primary objective is to design a 40-V precision comparator. • • • • • • 26 System supply voltage (V+): 40 V Resistor 1 value: 100 kΩ Resistor 2 value: 100 kΩ Reference threshold voltage (VTH): 20 V Input voltage range (VIN): 0 V – 40 V Output voltage range (VOUT): 0 V – 40 V Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLV9351-Q1 TLV9352-Q1 TLV9354-Q1 TLV9351-Q1, TLV9352-Q1, TLV9354-Q1 www.ti.com SBOSA34D – JANUARY 2021 – REVISED JUNE 2023 8.2.1.2 Detailed Design Procedure This noninverting comparator circuit applies the input voltage (VIN) to the noninverting terminal of the op amp. Two resistors (R1 and R2) divide the supply voltage (V+) to create a mid-supply threshold voltage (VTH) as calculated in Equation 1. The circuit is shown in Figure 8-1. When VIN is less then VTH, the output voltage transitions to the negative supply and equals the low-level output voltage. When VIN is greater than VTH, the output voltage transitions to the positive supply and equals the high-level output voltage. In this example, resistor 1 and 2 have been selected to be 100 kΩ, which sets the reference threshold at 20 V. However, resistor 1 and 2 can be adjusted to modify the threshold using Equation 1. Resistor 1 and 2's values have also been selected to reduce power consumption, but these values can be further increased to reduce power consumption, or reduced to improve noise performance. R VTH  =   R +2 R   ×  V+  1  2 (1) 8.2.1.3 Application Curve 45 Input Output 40 35 Voltage (V) 30 25 20 15 10 5 0 -5 0 0.2 0.4 0.6 0.8 1 1.2 Time (ms) 1.4 1.6 1.8 2 comp Figure 8-2. Comparator Output Response to Input Voltage 8.3 Power Supply Recommendations The TLV935x-Q1 is specified for operation from 4.5 V to 40 V (±2.25 V to ±20 V); many specifications apply from –40°C to 125°C. CAUTION Supply voltages larger than 40 V can permanently damage the device; see Section 6.1. Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-impedance power supplies. For more detailed information on bypass capacitor placement, refer to Section 8.4. 8.4 Layout 8.4.1 Layout Guidelines For best operational performance of the device, use good PCB layout practices, including: • Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources local to the analog circuitry. – Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as close to the device as possible. A single bypass capacitor from V+ to ground is applicable for singlesupply applications. Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLV9351-Q1 TLV9352-Q1 TLV9354-Q1 Submit Document Feedback 27 TLV9351-Q1, TLV9352-Q1, TLV9354-Q1 www.ti.com SBOSA34D – JANUARY 2021 – REVISED JUNE 2023 • • • • • • • Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital and analog grounds paying attention to the flow of the ground current. In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as opposed to in parallel with the noisy trace. Place the external components as close to the device as possible. As shown in Figure 8-4, keeping RF and RG close to the inverting input minimizes parasitic capacitance. Keep the length of input traces as short as possible. Always remember that the input traces are the most sensitive part of the circuit. Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce leakage currents from nearby traces that are at different potentials. Cleaning the PCB following board assembly is recommended for best performance. Any precision integrated circuit may experience performance shifts due to moisture ingress into the plastic package. Following any aqueous PCB cleaning process, baking the PCB assembly is recommended to remove moisture introduced into the device packaging during the cleaning process. A low temperature, post cleaning bake at 85°C for 30 minutes is sufficient for most circumstances. 8.4.2 Layout Example + VIN VOUT RG RF Figure 8-3. Schematic Representation Run the input traces as far away from the supply lines as possible Place components close to device and to each other to reduce parasitic errors VS+ RF NC NC GND ±IN V+ VIN +IN OUTPUT V± NC Use a low-ESR, ceramic bypass capacitor RG GND VS± GND VOUT Ground (GND) plane on another layer Use low-ESR, ceramic bypass capacitor Figure 8-4. Operational Amplifier Board Layout for Noninverting Configuration 28 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLV9351-Q1 TLV9352-Q1 TLV9354-Q1 TLV9351-Q1, TLV9352-Q1, TLV9354-Q1 www.ti.com V+ INPUT SBOSA34D – JANUARY 2021 – REVISED JUNE 2023 GND GND OUT V- GND OUTPUT A Figure 8-5. Example Layout for SC70 (DCK) Package GND GND GND V+ INPUT A VGND GND INPUT B OUTPUT B GND Figure 8-6. Example Layout for VSSOP-8 (DGK) Package Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLV9351-Q1 TLV9352-Q1 TLV9354-Q1 Submit Document Feedback 29 TLV9351-Q1, TLV9352-Q1, TLV9354-Q1 www.ti.com SBOSA34D – JANUARY 2021 – REVISED JUNE 2023 9 Device and Documentation Support 9.1 Device Support 9.1.1 Development Support 9.1.1.1 TINA-TI™ (Free Software Download) TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI is a free, fully-functional version of the TINA software, preloaded with a library of macro models in addition to a range of both passive and active models. TINA-TI provides all the conventional dc, transient, and frequency domain analysis of SPICE, as well as additional design capabilities. Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool. Note These files require that either the TINA software (from DesignSoft™) or TINA-TI software be installed. Download the free TINA-TI software from the TINA-TI folder. 9.1.1.2 TI Precision Designs The TLV935x-Q1 is featured in several TI Precision Designs, available online at http://www.ti.com/ww/en/analog/ precision-designs/. TI Precision Designs are analog solutions created by TI’s precision analog applications experts and offer the theory of operation, component selection, simulation, complete PCB schematic and layout, bill of materials, and measured performance of many useful circuits. 9.2 Documentation Support 9.2.1 Related Documentation For related documentation, see the following: • • • • Texas Instruments, EMI Rejection Ratio of Operational Amplifiers application note Texas Instruments, Capacitive Load Drive Solution using an Isolation Resistor reference guide Texas Instruments, Analog Engineer's Circuit Cookbook: Amplifiers e-book Texas Instruments, AN31 amplifier circuit collection application note 9.3 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 9.4 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 9.5 Trademarks TINA-TI™ is a trademark of Texas Instruments, Inc and DesignSoft, Inc. TINA™ and DesignSoft™ are trademarks of DesignSoft, Inc. TI E2E™ is a trademark of Texas Instruments. Bluetooth® is a registered trademark of Bluetooth SIG, Inc. All trademarks are the property of their respective owners. 30 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLV9351-Q1 TLV9352-Q1 TLV9354-Q1 TLV9351-Q1, TLV9352-Q1, TLV9354-Q1 www.ti.com SBOSA34D – JANUARY 2021 – REVISED JUNE 2023 9.6 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 9.7 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 10 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLV9351-Q1 TLV9352-Q1 TLV9354-Q1 Submit Document Feedback 31 PACKAGE OPTION ADDENDUM www.ti.com 12-Dec-2023 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) TLV9351QDBVRQ1 ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 2JMF Samples TLV9352QDGKRQ1 ACTIVE VSSOP DGK 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 27ST Samples TLV9352QDRQ1 ACTIVE SOIC D 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 T9352Q Samples TLV9352QPWRQ1 ACTIVE TSSOP PW 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM TL9352 Samples TLV9354QDRQ1 ACTIVE SOIC D 14 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 TL9354QD Samples TLV9354QDYYRQ1 ACTIVE SOT-23-THIN DYY 14 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 TLV9354Q Samples TLV9354QPWRQ1 ACTIVE TSSOP PW 14 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 T9354Q Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of