TLVM23625RDNR

TLVM23615, TLVM23625 SNVSCI2A – FEBRUARY 2023 – REVISED MARCH 2023 TLVM236x5, 3-V to 36-V Input, 1-V to 6-V Output, 1.5-A, 2.5-A Synchronous Buck Converter Power Module in a HotRod™ QFN Package 1 Features 3 Description • The TLVM236x5 is a 1.5-A or 2.5-A, 36-V input synchronous step-down DC/DC power module that combines flip chip on lead (FCOL) packaging, power MOSFETs, integrated inductor and boot capacitor in a compact and easy-to-use 3.5-mm × 4.5-mm × 2-mm, 11-pin QFN package. The small HotRod™ QFN package technology enhances the thermal performance, ensuring high ambient temperature operation. Devices can be configured for 1-V up to 6-V output with a resistor feedback divider. • • • • • 2 Applications • • • The TLVM236x5 is specifically designed to meet low standby power requirements for always on, industrial applications. Auto mode enables frequency fold back when operating at light loads, allowing a no load current consumption of 1.5 µA at 13.5-V VIN and high light load efficiency. A seamless transition between PWM and PFM modes along with low MOSFET on resistances provide exceptional efficiency across the entire load range. The TLVM236x5 uses peak current mode architecture with internal compensation to maintain stable operation with minimal output capacitance. The RT pin can be used to set the frequency between 200 kHz and 2.2 MHz to avoid noise sensitive frequency bands. Device Information PART NUMBER TLVM23615 TLVM23625 (1) Factory automation Test and measurement Grid infrastructure PACKAGE (1) BODY SIZE (NOM) RDN (QFN-FCMOD, 11) 3.50 mm × 4.50 mm For all available packages, see the orderable addendum at the end of the data sheet. 95 VIN CIN VIN SW EN BOOT 90 TLVM236x5 VOUT VOUT RFBT VCC FB CVCC RFBB RT GND PGOOD Typical Schematic COUT Efficiency (%) • Functional Safety-Capable – Documentation available to aid functional safety system design Versatile synchronous buck DC/DC module: – Integrated MOSFETs, inductor, CBOOT capacitor and controller – Wide input voltage range of 3 V to 36 V – Input transient protection up to 40 V – Junction temperature range –40°C to +125°C – Overmolded package of 4.5 mm × 3.5 mm × 2 mm – Frequency adjustable from 200 kHz to 2.2 MHz using the RT pin Ultra-high efficiency across the full load range: – Greater than 88% efficiency at 12 V VIN, 5-V VOUT,1 MHz, IOUT = 2.5 A – Greater than 87% efficiency at 24 VIN, 5-VOUT, 1 MHz, IOUT = 2.5 A – As low as 1.5-µA standby IQ at 13.5 VIN Optimized for ultra-low EMI requirements: – Flip-chip on lead package - FCOL – Inductor and boot capacitor integration – CISPR 11, Class B compliant-capable Output voltage and current options: – Adjustable output voltage from 1 V to 6 V Suitable for scalable power supplies: – Pin compatible with: • TPSM365R6 (65 V, 600 mA) Create a custom design using the TLVM236x5 with the WEBENCH® Power Designer 85 80 75 70 65 60 1.8V, 300kHz 2.5V, 800kHz 3.3V, 1MHz 5V, 1MHz 5V, 2MHz 55 50 0.001 0.01 0.1 Load Current (A) 1 2.5 Efficiency vs Output Current VIN = 24 V An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TLVM23615, TLVM23625 www.ti.com SNVSCI2A – FEBRUARY 2023 – REVISED MARCH 2023 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Device Comparison Table...............................................3 6 Pin Configuration and Functions...................................4 7 Specifications.................................................................. 5 7.1 Absolute Maximum Ratings........................................ 5 7.2 ESD Ratings............................................................... 5 7.3 Recommended Operating Conditions.........................6 7.4 Thermal Information....................................................6 7.5 Electrical Characteristics.............................................7 7.6 System Characteristics............................................... 9 7.7 Typical Characteristics.............................................. 10 8 Detailed Description...................................................... 11 8.1 Overview................................................................... 11 8.2 Functional Block Diagram......................................... 12 8.3 Feature Description...................................................13 8.4 Device Functional Modes..........................................21 9 Application and Implementation.................................. 27 9.1 Application Information............................................. 27 9.2 Typical Application.................................................... 28 9.3 Best Design Practices...............................................37 9.4 Power Supply Recommendations.............................37 9.5 Layout....................................................................... 37 10 Device and Documentation Support..........................40 10.1 Device Support....................................................... 40 10.2 Documentation Support.......................................... 40 10.3 Support Resources................................................. 41 10.4 Trademarks............................................................. 41 10.5 Electrostatic Discharge Caution..............................41 10.6 Glossary..................................................................41 11 Mechanical, Packaging, and Orderable Information.................................................................... 42 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision * (February 2023) to Revision A (March 2023) Page • Removed product preview note from TLVM23615..............................................................................................1 2 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLVM23615 TLVM23625 TLVM23615, TLVM23625 www.ti.com SNVSCI2A – FEBRUARY 2023 – REVISED MARCH 2023 5 Device Comparison Table (1) DEVICE ORDERABLE PART NUMBER (1) FSW OUTPUT VOLTAGE OUTPUT CURRENT EXTERNAL SYNC (MODE Configuration) SPREAD SPECTRUM TLVM23615 TLVM23615RDNR Adjustable with RT resistor Adjustable (1 V to 6 V) 1.5 A No (Default PFM at light load) No TLVM23625 TLVM23625RDNR Adjustable with RT resistor Adjustable (1 V to 6 V) 2.5 A No (Default PFM at light load) No For more information on device orderable part numbers, see Section 10.1.3. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLVM23615 TLVM23625 3 TLVM23615, TLVM23625 www.ti.com SNVSCI2A – FEBRUARY 2023 – REVISED MARCH 2023 6 Pin Configuration and Functions PGOOD A. B. MODE/SYNC (A) RT (B) GND 1 11 10 FB 9 8 VCC EN 2 7 BOOT VIN 3 6 SW VOUT 4 5 SW Pin 11 factory-set for fixed switching frequency MODE/SYNC variants only. See Device Comparison Table for more details. Pin 11 trimmed and factory-set for externally adjustable switching frequency RT variants only. Figure 6-1. RDN Package, 11-Pin QFN-FCMOD , Top View (All Variants) Table 6-1. Pin Functions PIN NO. 1 NAME PGOOD I/O DESCRIPTION A Power-good monitor. Open-drain output that asserts low if the feedback voltage is not within the specified window thresholds. A 10-kΩ to 100-kΩ pullup resistor is required to a suitable pullup voltage. If not used, this pin can be left open or connected to GND. High = power OK, Low = power bad. PGOOD pin goes low when EN = Low. 2 EN A Precision enable input pin. High = ON, Low = OFF. Can be connected to VIN. Precision enable allows the pin to be used as an adjustable UVLO. Can be connected directly to VIN. The module can be turned off by using an open-drain or collector device to connect this pin to GND. An external voltage divider can be placed between this pin, GND, and VIN to create an external UVLO.Do not float this pin. 3 VIN P Input supply voltage. Connect the input supply to these pins. Connect a high-quality bypass capacitor or capacitors directly to this pin and GND in close proximity to the module. Refer to Section 9.5.2 for input capacitor placement example. 4 VOUT P 5, 6 SW P Power module switch node. Do not place any external component on this pin or connect to any signal. The amount of copper placed on these pins must be kept to a minimum to prevent issues with noise and EMI. 7 BOOT P Bootstrap pin for internal high-side driver circuitry. A 100-nF bootstrap capacitor is internally connected from this pin to SW within the module to provide the bootstrap voltage. 8 VCC P Internal LDO output. Used as supply to internal control circuits. Do not connect to external loads. Can be used as logic supply for power-good flag. Connect a high-quality 1-µF capacitor from this pin to GND. Output voltage. The pin is connected to the internal output inductor. Connect the pin to the output load and connect external output capacitors between the pin and GND. 9 FB A Feedback input. For the adjustable output, connect the mid-point of the feedback resistor divider to this pin. Connect the upper resistor (RFBT) of the feedback divider to VOUT at the desired point of regulation. Connect the lower resistor (RFBB) of the feedback divider to GND. When connecting with feedback resistor divider, keep this FB trace short and as small as possible to avoid noise coupling. See Section 9.5.2 for a feedback resistor placement. 10 GND G Power ground terminal. Connect to system ground. Connect to CIN with short, wide traces. 11 RT A When the part is configured as the RT pin variant, the switching frequency in the part can be adjusted from 200 kHz to 2.2 MHz based on the resistor value connected between RT and GND. A = Analog, P = Power, G = Ground 4 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLVM23615 TLVM23625 TLVM23615, TLVM23625 www.ti.com SNVSCI2A – FEBRUARY 2023 – REVISED MARCH 2023 7 Specifications 7.1 Absolute Maximum Ratings Limits apply over TJ = –40°C to 125°C (unless otherwise noted). (1) Input voltage MIN MAX VIN to GND –0.3 40 V CBOOT to SW –0.3 5.5 V RT to GND –0.3 5.5 V EN to GND –0.3 40 V FB to GND –0.3 16 V PG to GND 0 20 V –0.3 5.5 V –0.3 40 V –0.3 16 V – 10 mA VCC to GND Output voltage SW to GND(2) VOUT to GND UNIT Input current PG TJ Junction temperature –40 125 °C TA Ambient temperature –40 105 °C Tstg Storage temperature –55 150 °C (1) (2) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. A voltage of 2 V below PGND and 2 V above VIN can appear on this pin for ≤ 200 ns with a duty cycle of ≤ 0.01%. 7.2 ESD Ratings V(ESD) (1) (2) Electrostatic discharge VALUE UNIT Human-body model (HBM), per ANSI/ESDA/ JEDEC JS-001(1) ±2000 V Charged-device model (CDM), per ANSI/ESDA/ JEDEC JS-002(2) ±1000 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLVM23615 TLVM23625 5 TLVM23615, TLVM23625 www.ti.com SNVSCI2A – FEBRUARY 2023 – REVISED MARCH 2023 7.3 Recommended Operating Conditions Limits apply over TJ = –40°C to 125°C (unless otherwise noted). MIN NOM MAX UNIT Input voltage VIN (Input voltage range after start-up) 3 36 V Output voltage Output Adjustment Range(1) 1 6 V Output current TLVM23625 IOUT(2) 0 2.5 A Output current TLVM23615 IOUT(2) 0 1.5 A Frequency FSW set by RT 200 2200 kHz TJ Operating junction temperature –40 125 °C TA Operating ambient temperature –40 105 °C (1) (2) Under no conditions should the output voltage be allowed to fall below zero volts. Maximum continuous DC current may be derated when operating with high switching frequency or high ambient temperature. Refer to the Typical Characteristics section for details. 7.4 Thermal Information TLVM23615 / TLVM23625 THERMAL METRIC (1) RDN UNIT 11 Pins RθJA Junction-to-ambient thermal resistance (TLM23625EVM ) 22 °C/W RθJA Junction-to-ambient thermal resistance (JESD 51-7) 54.1 °C/W RθJC(top) Junction-to-case (top) thermal resistance 52.1 °C/W RθJB Junction-to-board thermal resistance 16.6 °C/W ΨJT Junction-to-top characterization parameter 8.1 °C/W ΨJB Junction-to-board characterization parameter 16.3 °C/W (1) 6 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. The value of RΘJA given in this table is only valid for comparison with other packages and can not be used for design purposes. This value was calculated in accordance with JESD 51-7, and simulated on a 4-layer JEDEC board. It does not represent the performance obtained in an actual application. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLVM23615 TLVM23625 TLVM23615, TLVM23625 www.ti.com SNVSCI2A – FEBRUARY 2023 – REVISED MARCH 2023 7.5 Electrical Characteristics Limits apply over TJ = –40°C to 125°C, VIN = 24 V, VOUT = 3.3 V, FSW = 1000 kHz (unless otherwise noted). Minimum and maximum limits are specified through production test or by design. Typical values represent the most likely parametric norm and are provided for reference only. PARAMETER TEST CONDITIONS MIN TYP MAX Before Start-up 3.2 3.35 3.5 Once Operating 2.45 2.7 3 UNIT SUPPLY VOLTAGE V VIN Input voltage rising threshold IQ_VIN Input operating quiescent current (non-switching) TA = 25°C, VEN = 3.3 V, VFB = 1.5 V 1.2 µA ISDN_VIN VIN shutdown quiescent current VEN = 0 V, TA = 25°C 0.3 µA V ENABLE VEN_RISE EN voltage rising threshold 1.16 1.23 1.3 V VEN_HYS VEN_WAKE EN voltage hysteresis 0.275 0.353 0.404 V EN wake-up threshold 0.5 0.7 1 ILKG-EN Enable pin input leakage current VEN = VIN = 24 V 10 V nA INTERNAL LDO VCC VCC Internal LDO VCC output voltage VFB = 0 V, IVCC = 1 mA 3.1 3.3 3.5 V Feedback voltage TA = 25°C, IOUT = 0 A VFB_ACC Feedback voltage accuracy Over the VIN range, VOUT = 1 V, IOUT = 0 A, FSW = 200 kHz IFB Input current into FB pin Adjustable configuration, VFB = 1.0 V IL_HS High-side switch current limit (TLVM23625) Duty cycle approaches 0% IL_LS Low-side switch current limit (TLVM23625) IL_NEG Negative current limit (TLVM23625) IPEAKMIN Minimum peak current limit (TLVM23625) Auto mode IL_HS High-side switch current limit (TLVM23615) Duty cycle approaches 0% IL_LS Low-side switch current limit (TLVM23615) IL_NEG Negative current limit (TLVM23615) IPEAKMIN Minimum peak current limit (TLVM23615) Auto mode 0.4 A IZC Zero-cross current limit Auto mode 80 mA VHICCUP Ratio of FB voltage to in-regulation FB voltage to enter hiccup Not during soft start 40 % FEEDBACK VFB 1.0 –1 V +1 10 % nA CURRENT tW 4.2 4.9 5.5 A 2.38 2.9 3.42 A –2 A 0.6 A 2.58 3 3.42 A 1.44 1.75 2.06 A –2 Short circuit wait time ("hiccup" time before soft start) (1) A 30 50 75 ms 2 3.5 4.6 ms SOFT-START tSS Time from first SW pulse to VREF at 90% VIN ≥ 4.2 V Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLVM23615 TLVM23625 7 TLVM23615, TLVM23625 www.ti.com SNVSCI2A – FEBRUARY 2023 – REVISED MARCH 2023 7.5 Electrical Characteristics (continued) Limits apply over TJ = –40°C to 125°C, VIN = 24 V, VOUT = 3.3 V, FSW = 1000 kHz (unless otherwise noted). Minimum and maximum limits are specified through production test or by design. Typical values represent the most likely parametric norm and are provided for reference only. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 104 108 111 % 89 91 94.2 % POWER GOOD PGOV PG upper threshold - rising PGUV PG lower threshold - falling % of VOUT setting (adjustable output) % of VOUT setting (adjustable output) PG upper threshold hysteresis for OV % of VOUT setting 2 2.4 2.8 % PG upper threshold hysteresis for UV % of VOUT setting 2 3.3 4.6 % VIN_PG_VALID Input voltage for valid PG output RPGD_PU = 10 kΩ, VEN = 0 V 1.5 V VPG_LOW Low level PG function output voltage 2 mA pullup to PG pin, VEN = 3.3 V 0.4 V VPG_LOW Low level PG function output voltage 2 mA pullup to PG pin, VEN = 3.3 V tPG_FLT_RISE Delay time to PG high signal tRESET_FILTER PGOOD deglitch delay at falling edge RPGD PGOOD ON resistance VEN = 3.3 V, 200 uA pullup current RPGD PGOOD ON resistance VEN = 0 V, 200 uA pullup current 100 Ω 2500 kHz 2200 kHz 2300 kHz PGHYS 0.4 1.35 2.5 25 40 V 4 ms 75 µs 100 Ω SWITCHING FREQUENCY fSYNC_RANGE Switching frequency range by SYNC(Mode/Sync variant) fADJ_RANGE Switching frequency range by RT (RT variant) fSW_RT1 2.2 MHZ switching frequency programmed by RT 200 200 RRT = 0 kΩ (RT pin tied to GND) 2000 2200 SYNCHRONIZATION Blanking of EN after rising or falling edges(1) tB 4 28 µs POWER STAGE VBOOT_UVLO Voltage on CBOOT pin compared to SW which will turn off high-side switch tON_MIN Minimum ON pulse width(1) FPWM mode, VOUT = 1 V, IOUT = 1 A tON_MAX Maximum ON pulse width(1) HS timeout in dropout tOFF_MIN Minimum OFF pulse width VIN = 4 V, IOUT = 1 A (1) 8 2.1 6 V 65 75 ns 9 13 µs 60 85 ns Parameter specified by design, statistical analysis and production testing of correlated parameters. Not production tested. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLVM23615 TLVM23625 TLVM23615, TLVM23625 www.ti.com SNVSCI2A – FEBRUARY 2023 – REVISED MARCH 2023 7.6 System Characteristics The following specifications apply only to the typical applications circuit, with nominal component values. Specifications in the typical (TYP) column apply to TJ = 25°C only. These specifications are not ensured by production testing. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY IIN Input supply current when in regulation VIN = 24 V, VOUT = 3.3 V(RFBT = 23.2 kΩ), VEN = VIN, FSW = 1000 kHz, IOUT = 0 A,PFM IIN Input supply current when in regulation VIN = 24 V, VOUT = 5 V(RFBT = 40.2 kΩ), VEN = VIN, FSW = 1000 kHz, IOUT = 0 A,PFM 6.9 μA 7 μA OUTPUT VOLTAGE VFB Load regulation VOUT = 3.3 V, VIN = 24 V, IOUT = 0.4 A to full load(FPWM) VFB Line regulation VOUT = 3.3 V, VIN = 4 V to 36 V, IOUT = 2.5 A VOUT Load transient VOUT = 3.3 V, VIN = 24 V, IOUT = 1 A to 2.5 A @ 2 A/μs, COUT(derated) = 32 uF 3 mV 10 mV 100 mV EFFICIENCY 86 VOUT = 3.3 V, VIN = 12 V, IOUT = 2.5 A, VLDOIN = VOUT, FSW = 1 MHz 84 VOUT = 3.3 V, VIN = 24 V, IOUT = 2.5 A, VLDOIN = VOUT, FSW = 1 MHz η % Efficiency % 88 VOUT = 5 V, VIN = 24 V, IOUT = 2.5 A, VLDOIN = VOUT, FSW = 1 MHz % 86 VOUT = 5 V, VIN = 36 V, IOUT = 2.5 A, VLDOIN = VOUT, FSW = 1 MHz % Thermal Shutdown TSDN Thermal shutdown threshold THYST Thermal shutdown hysteresis Temperature rising 158 168 186 °C 15 20 °C Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLVM23615 TLVM23625 9 TLVM23615, TLVM23625 www.ti.com SNVSCI2A – FEBRUARY 2023 – REVISED MARCH 2023 7.7 Typical Characteristics Unless otherwise specified, the following conditions apply: TA = 25°C , VIN = 13.5 V. 0.7 1 Voltage Reference Voltage (V) VIN = 13.5V VIN = 24V Shutdown Current (µA) 0.6 0.5 0.4 0.3 0.2 -40 -10 20 50 Temperature (°C) 80 105 Figure 7-1. Shutdown Supply Current (ISDN_VIN) Versus Temperature 10 0.9995 0.999 0.9985 0.998 0.9975 -40 -10 20 50 Temperature (°C) 80 105 Figure 7-2. Feedback Voltage (VFB) Accuracy Versus Temperature Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLVM23615 TLVM23625 www.ti.com TLVM23615, TLVM23625 SNVSCI2A – FEBRUARY 2023 – REVISED MARCH 2023 8 Detailed Description 8.1 Overview The TLVM236x5 is an easy-to-use, synchronous buck, DC-DC power module that operates from a 3-V to 36-V supply voltage. The device is intended for step-down conversions from 5-V, 12-V, 24-V, and 36-V supply rails. With an integrated buck converter, inductor, and boot capacitor, the TLVM236x5 delivers up to 2.5-A DC load current with high efficiency and ultra-low input quiescent current in a compact solution size. Control-loop compensation is not required, reducing design time and external component count. The TLVM236x5 operates over a wide range of switching frequencies and duty ratios. If the minimum ON-time or OFF-time cannot support the desired duty ratio, the switching frequency is reduced automatically, maintaining the output voltage regulation. In addition, the PGOOD output feature with built-in delayed release allows the elimination of the reset supervisor in many applications. With a programmable switching frequency from 200 kHz to 2.2 MHz using its RT pin or an external clock signal, the TLVM236x5 incorporates specific features to improve EMI performance in noise-sensitive applications: • An optimized package that incorporates flip chip on lead (FCOL) technology and pinout design enables a shielded switch-node layout that mitigates radiated EMI. • Clock synchronization and FPWM mode enable constant switching frequency across the load current range. • Inductor and boot capacitor integration The TLVM236x5 module also includes inherent protection features for robust system requirements: • An open-drain PGOOD indicator for power-rail sequencing and fault reporting • Precision enable input with hysteresis, providing: – Programmable line undervoltage lockout (UVLO) – Remote ON and OFF capability • Internally fixed output-voltage soft start with monotonic start-up into pre-biased loads • Hiccup-mode overcurrent protection with cycle-by-cycle peak and valley current limits • Thermal shutdown with automatic recovery These features enable a flexible and easy-to-use platform for a wide range of applications. The pin arrangement is designed for a simple layout, requiring few external components. See Layout for a layout example. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLVM23615 TLVM23625 11 TLVM23615, TLVM23625 www.ti.com SNVSCI2A – FEBRUARY 2023 – REVISED MARCH 2023 8.2 Functional Block Diagram VCC MODE/SYNC VARIANTS ONLY MODE /SYNC CLOCK OSCILLATOR SLOPE COMPENSATION RT RT VARIANTS ONLY LDO VCC UVLO VIN THERMAL SHUTDOWN FSW FOLDBACK ENABLE EN TSD SYS ENABLE BOOT 0.1 F HS CURRENT SENSE ERROR AMPLIFIER – FB + + – COMP + VIN TSD CLOCK MAX and MIN LIMITS SW SW + HS CURRENT LIMIT SYS ENABLE VOUT SYS ENABLE CONTROL LOGIC and DRIVER SOFTSTART and BANDGAP TSD GND 2.2
H – VREF VCC UVLO LS CURRENT LIMIT – + MIN LS CURRENT LIMIT FB PGOOD FPWM or AUTO PGOOD LOGIC 12 VOUT UV/OV – + VOUT UV/OV LS CURRENT SENSE Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLVM23615 TLVM23625 TLVM23615, TLVM23625 www.ti.com SNVSCI2A – FEBRUARY 2023 – REVISED MARCH 2023 8.3 Feature Description 8.3.1 Input Voltage Range With a steady-state input voltage range from 3 V to 36 V, the TLVM236x5 module is intended for step-down conversions from typical 12-V to 36-V input supply rails, as example. The schematic circuit in Figure 8-1 shows all the necessary components to implement a TLVM236x5-based buck regulator using a single input supply. SW VIN VIN = 3 V to 36 V CIN BOOT EN TLVM236x5 VOUT = 1 V to 6 V IOUT(max) = 2.5 A VOUT RFBT FB VCC CVCC COUT VCC RFBB RPGOOD RT RRT GND PGOOD PGOOD indicator Figure 8-1. TLVM236x5 Schematic Diagram with Input Voltage Operating Range of 3 V to 36 V Take extra care to ensure that the voltage at the VIN pin does not exceed the absolute maximum voltage rating of 40 V during line or load transient events. Voltage ringing at the VIN pins that exceeds the absolute maximum ratings can damage the IC. 8.3.2 Output Voltage Selection The TLVM236x5 output voltage can be set by two external resistors, RFBT and RFBB. Connect RFBT between VOUT at the regulation point and the FB pin. Connect RFBB between the FB pin and AGND. The TLVM236x5 has an adjustable output voltage range from 1.0 V to 6 V. To ensure that the power module regulates to the desired output voltage, the typical minimum value for the parallel combination of RFBT and RFBB is 5 kΩ while the typical maximum value is 10 kΩ as shown in Equation 3. Equation 2 and Equation 3 can be used as a starting point to determine the value of RFBT. Reference Table 8-1 for a list of acceptable resistor values for various output voltages. 5 kΩ < RFBT RFBB ≤ 10 kΩ RFBT kΩ = RFBB kΩ × V RFBT ≤ 10 kΩ × 1OUT V (1) VOUT V –1 1V (2) (3) For adjustable output options, an addition feedforward capacitor, CFF, in parallel with the RFBT can be needed to optimize the transient response. See CFF Selection for additional information. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLVM23615 TLVM23625 13 TLVM23615, TLVM23625 www.ti.com SNVSCI2A – FEBRUARY 2023 – REVISED MARCH 2023 VOUT RFBT FB RFBB AGND Figure 8-2. Setting Output Voltage for Adjustable Output Variant Table 8-1. Standard RFBT Values, Recommended FSW and Minimum COUT (1) VOUT (V) RFBT (kΩ) (1) RECOMMENED FSW (kHz) COUT(MIN) (µF) (EFFECTIVE) 1.0 Short 400 300 1.2 2 500 200 1.5 4.99 500 160 1.8 8.06 600 120 2.0 10 600 100 2.5 15 750 65 3.0 20 750 50 3.3 23.2 800 40 5.0 40.2 1000 25 RFBB = 10 kΩ 8.3.3 Input Capacitors Input capacitors are required to limit the input ripple voltage to the module due to switching-frequency AC currents. TI recommends using ceramic capacitors to provide low impedance and high RMS current rating over a wide temperature range. Equation 4 gives the input capacitor RMS current. The highest input capacitor RMS current occurs at D = 0.5, at which point, the RMS current rating of the capacitors must be greater than half the output current. ∆ I2 where • ICIN, rms = D × I2OUT × 1 − D + 12L (4) D = VOUT / VIN is the module duty cycle. Ideally, the DC and AC components of the input current to the buck stage are provided by the input voltage source and the input capacitors, respectively. Neglecting inductor ripple current, the input capacitors source current of amplitude (IOUT – IIN) during the D interval and sink IIN during the 1 – D interval. Thus, the input capacitors conduct a square-wave current of peak-to-peak amplitude equal to the output current. The resulting capacitive component of the AC ripple voltage is a triangular waveform. Together with the ESR-related ripple component, Equation 5 gives the peak-to-peak ripple voltage amplitude. 14 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLVM23615 TLVM23625 TLVM23615, TLVM23625 www.ti.com SNVSCI2A – FEBRUARY 2023 – REVISED MARCH 2023 I ×D× 1−D ∆ VIN = OUTF × C + IOUT × RESR SW IN (5) Equation 6 gives the input capacitance required for a particular load current. where • CIN ≥ D × 1 − D × IOUT FSW × ∆ VIN − RESR × IOUT (6) ΔVIN is the input voltage ripple specification. The TLVM236x5 requires a minimum of a 4.7-µF ceramic type input capacitance. Only use high-quality ceramic type capacitors with sufficient voltage and temperature rating. The ceramic input capacitors provide a low impedance source to the power module in addition to supplying the ripple current and isolating switching noise from other circuits. Additional capacitance can be required for applications with transient load requirements. The voltage rating of the input capacitors must be greater than the maximum input voltage. To compensate for the derating of ceramic capacitors, TI recommends a voltage rating of twice the maximum input voltage or placing multiple capacitors in parallel. Table 8-2 includes a preferred list of capacitors by vendor. Table 8-2. Recommended Input Capacitors VENDOR (1) DIELECTRIC PART NUMBER CASE SIZE TDK X7R C3225X7R1H475K2 50AB (1) (2) CAPACITOR CHARACTERISTICS VOLTAGE RATING (V) CAPACITANCE (µF) (2) 1210 50 4.7 4.7 Wurth X7R 885012209048 1210 50 Murata X5R GRM155R61H104M E14D 0402 50 0.1 Chemi-Con Electrolytic EMVY500ADA101M HA0G HA0 50 100 Consult capacitor suppliers regarding availability, material composition, RoHS and lead-free status, and manufacturing process requirements for any capacitors identified in this table. See the Third-Party Products Disclaimer. Nameplate capacitance values (the effective values are lower based on the applied DC voltage and temperature). 8.3.4 Output Capacitors Table 8-1 lists the TLVM236x5 minimum amount of required output capacitance. The effects of DC bias and temperature variation must be considered when using ceramic capacitance. For ceramic capacitors, the package size, voltage rating, and dielectric material contribute to differences between the standard rated value and the actual effective value of the capacitance. When adding additional capacitance above COUT(MIN), the capacitance can be ceramic type, low-ESR polymer type, or a combination of the two. See Table 8-3 for a preferred list of output capacitors by vendor. Table 8-3. Recommended Output Capacitors (1) (2) VENDOR (1) TEMPERATURE COEFFICIENT TDK TDK PART NUMBER CASE SIZE X7R CNA6P1X7R1E226M250AE X7R CGA6P1X7R1C226 M250AC Wurth X7R Wurth X7R CAPACITOR CHARACTERISTICS VOLTAGE (V) CAPACITANCE (µF) (2) 1210 25 22 1210 16 22 885012209028 1210 25 10 885012209014 1210 16 10 Consult capacitor suppliers regarding availability, material composition, RoHS and lead-free status, and manufacturing process requirements for any capacitors identified in this table. See the Third-Party Products Disclaimer. Nameplate capacitance values (the effective values are lower based on the applied DC voltage and temperature). Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLVM23615 TLVM23625 15 TLVM23615, TLVM23625 www.ti.com SNVSCI2A – FEBRUARY 2023 – REVISED MARCH 2023 8.3.5 Enable, Start-Up, and Shutdown Voltage at the EN pin controls the start-up or remote shutdown of the TLVM236x5. The part stays shut down as long as the EN pin voltage is less than VEN-WAKE.With the voltage at the EN pin greater than VEN-WAKE, the device enters device standby mode and the internal LDO powers up to generate VCC. As the EN voltage increases further, approaching VEN-RISE, the device finally starts to switch, entering start-up mode with a soft start. During the device shutdown process, when the EN input voltage measures less than (VEN-RISE–VEN-HYST), the regulator stops switching and re-enters device standby mode. Any further decrease in the EN pin voltage, below VEN-WAKE, and the device is then firmly shut down. The high-voltage compliant EN input pin can be connected directly to the VIN input pin if remote precision control is not needed. The EN input pin must not be allowed to float. The various EN threshold parameters and their values are listed in the Section 7.5. Figure 8-3 shows the precision enable behavior and Figure 8-4 shows a typical remote EN start-up waveform in an application. After EN goes high, after a delay of about 1 ms, the output voltage begins to rise with a soft start and reaches close to the final value in about 3.5 ms (tss). After a delay of about 2.5 ms (tPG_FLT_RISE), the PGOOD flag goes high. During start-up, the device is not allowed to enter FPWM mode until the soft-start time has elapsed. This time is measured from the rising edge of EN. EN VEN_RISE VEN_HYS VEN-WAKE VCC 3.3V 0 VOUT VOUT 0 Figure 8-3. Precision Enable Behavior VOUT (1 V/DIV) PGOOD (1 V/DIV) EN (5 V/DIV) 2 ms/DIV Figure 8-4. Enable Start-Up VIN = 24 V, VOUT = 3.3 V, IOUT = 2.5 A 16 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLVM23615 TLVM23625 TLVM23615, TLVM23625 www.ti.com SNVSCI2A – FEBRUARY 2023 – REVISED MARCH 2023 External UVLO through EN Pin In some cases, an input UVLO level different than that provided internal to the device is needed. This can be accomplished by using the circuit shown in Figure 8-5. The input voltage at which the device turns on is designated as VON while the turn-off voltage is VOFF. First, a value for RENB is chosen in the range of 10 kΩ to 100 kΩ, then Equation 7and Equation 8 are used to calculate RENT and VOFF, respectively. VIN RENT EN RENB AGND Figure 8-5. Setup for External UVLO Application RENT = VON VEN_RISE − 1 × RENB (7) V VOFF = VON × 1 − V EN_HYS (8) EN_RISE where • VON is the VIN turn-on voltage. • VOFF is the VIN turn-off voltage. • Refer to electrical characteristics table for other terms. 8.3.6 Switching Frequency (RT) The select orderables in the TLVM236x5 family with the RT pin allow power designers to set any desired operating frequency between 200 kHz and 2.2 MHz in their applications. See Figure 8-6 to determine the resistor value needed for the desired switching frequency or simply select from Table 8-5. The RT pin and the MODE/SYNC pin variants share the same pin location. The power supply designer can either use the RT pin variant and adjust the switching frequency of operation as warranted by the application or use the MODE/SYNC variant and synchronize to an external clock signal. See Table 8-4 for selection on programming the RT pin. Table 8-4. RT Pin Setting RT INPUT SWITCHING FREQUENCY VCC 1 MHz GND 2.2 MHz RT to GND Adjustable according to Figure 8-6 Float (Not Recommended) No Switching 18286 RT = Fsw1.021 (9) where • RT is the frequency setting resistor value (kΩ). • FSW is the switching frequency (kHz). Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLVM23615 TLVM23625 17 TLVM23615, TLVM23625 www.ti.com SNVSCI2A – FEBRUARY 2023 – REVISED MARCH 2023 80 RT resistor (k) 70 60 50 40 30 20 10 0 200 400 600 800 1000 1200 1400 1600 1800 2000 2200 Switching Frequency (kHz) Figure 8-6. RT Values vs Frequency The switching frequency must be selected based on the output voltage setting of the device. See Table 8-5 for RRT resistor values and the allowable output voltage range for a given switching frequency for common input voltages. Table 8-5. Switching Frequency Versus Output Voltage (IOUT = 2.5 A) FSW (kHz) RRT (kΩ) VIN = 5 V VIN = 12 V VIN = 24 V VIN = 36 V VOUT RANGE (V) VOUT RANGE (V) VOUT RANGE (V) VOUT RANGE (V) MIN MAX MIN MAX MIN MAX MIN MAX 200 81.6 1 1.75 1 1.5 1 1.25 1 1.25 400 40.2 1 2 1 4 1 3 1.25 2.5 600 26.7 1 2.5 1 5 1.25 5 2 4 800 19.8 1 3 1 5.5 1.5 6 2.25 6 1000 15.8 1 3.5 1 6 2 6 2.5 6 1200 13.2 1 3.5 1.5 6 2.5 6 3 6 1400 11.3 1 3.5 1.5 6 3 6 3.5 6 1600 9.76 1 3.5 1.5 6 3 6 4 6 1800 8.66 1 3 1.5 6 3.5 6 5 6 2000 7.77 1 3 1.5 6 3.5 6 5.5 6 2200 7.06 1 3 1.5 6 4.5 6 6 6 8.3.7 Power-Good Output Operation The power-good feature using the PGOOD pin of the TLVM236x5 can be used to reset a system microprocessor whenever the output voltage is out of regulation. This open-drain output remains low under device fault conditions, such as current limit and thermal shutdown, as well as during normal start-up. A glitch filter prevents false flag operation for any short duration excursions in the output voltage, such as during line and load transients. Output voltage excursions lasting less than tRESET_FILTER do not trip the power-good flag. Power-good operation can best be understood in reference to Figure 8-7. Table 8-6 gives a more detailed breakdown of the PGOOD operation. Here, VPGUV is defined as the PGUV scaled version of VOUT (target regulated output voltage) and VPGHYS as the PGHYS scaled version of VOUT, where both PGUV and PGHYS are listed in Section 7.5. During the initial power up, a total delay of 6 ms (typical) is encountered from the time VEN_RISE is triggered to the time that the power-good is flagged high. This delay only occurs during the device start-up and is not encountered 18 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLVM23615 TLVM23625 TLVM23615, TLVM23625 www.ti.com SNVSCI2A – FEBRUARY 2023 – REVISED MARCH 2023 during any other normal operation of the power-good function. When EN is pulled low, the power-good flag output is also forced low. With EN low, power-good remains valid as long as the input voltage (VIN_PG_VALID is ≥ 1.5 V (max)). The power-good output scheme consists of an open-drain n-channel MOSFET, which requires an external pullup resistor connected to a suitable logic supply. It can also be pulled up to either VCC or VOUT through an appropriate resistor, as desired. If this function is not needed, the PGOOD pin can be open or grounded. Limit the current into this pin to ≤ 4 mA. Input Voltage Output Voltage Input Voltage tRESET_FILTER tPG_FLT_RISE tPG_FLT_RISE VPG HYS tRESET_FILTER tRESET_FILTER tRESET_FILTER VPGUV (falling) VIN (rising) VIN_HYS VIN_PG_VALID GND VOUT PGOOD PG may not be valid if input is below VIN_PG-VALID Small glitches do not cause reset to signal a fault Small glitches do not reset tPG_FLT_RISE timer Startup delay PG may not be valid if input is below VIN_PG-VALID Figure 8-7. Power-Good Operation (OV Events Not Included) Table 8-6. Fault Conditions for PGOOD (Pull Low) FAULT CONDITION INITIATED FAULT CONDITION ENDS (AFTER WHICH tPGOOD_ACT MUST PASS BEFORE PGOOD OUTPUT IS RELEASED) VOUT < VPGUV AND t > tRESET_FILTER Output voltage in regulation: VPGUV + VPGHYS < VOUT < VPGOV - VPGHYS VOUT > VPGOV AND t > tRESET_FILTER Output voltage in regulation TJ > TSDN TJ < TSDN-THYST AND output voltage in regulation EN < VEN_RISE - VEN_HYS EN > VEN_RISE AND output voltage in regulation 8.3.8 Internal LDO, VCC and VOUT/FB Input The TLVM236x5 uses the internal LDO output and the VCC pin for all internal power supply. The VCC rail typically measures 3.3 V. During start-up, VCC momentarily exceeds the normal operating voltage, then drops to the normal operating voltage. 8.3.9 Bootstrap Voltage and VBOOT-UVLO (BOOT Terminal) The high-side switch driver circuit requires a bias voltage higher than VIN to ensure the HS switch is turned ON. There is an internal 0.1-μF capacitor connected between BOOT and SW that operates as a charge pump to boost the voltage on the BOOT terminal to (SW + VCC). The boot diode is integrated on the TLVM236x5 die to minimize physical solution size. The BOOT rail has an UVLO setting. This UVLO has a threshold of VBOOT-UVLO and is typically set at 2.1 V. If the BOOT capacitor is not charged above this voltage with respect to the SW pin, then the part initiates a charging sequence, turning on the low-side switch before attempting to turn on the high-side device. 8.3.10 Soft Start and Recovery from Dropout When designing with the TLVM236x5, slow rise in output voltage due to recovery from dropout and soft start must be considered as a two separate operating conditions, as shown in Figure 8-8 and Figure 8-9. Soft start is triggered by any of the following conditions: • Power is applied to the VIN pin of the device, releasing undervoltage lockout. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLVM23615 TLVM23625 19 TLVM23615, TLVM23625 www.ti.com SNVSCI2A – FEBRUARY 2023 – REVISED MARCH 2023 • • EN is used to turn on the device. Recovery from shutdown due to overtemperature protection After soft start is triggered, the power module takes the following actions: • The reference used in the power module to regulate the output voltage is slowly ramped up. The net result is that output voltage, if previously 0 V, takes tSS to reach 90% of the desired value. Operating mode is set to auto mode of operation, activating the diode emulation mode for the low-side MOSFET. This allows start-up without pulling the output low. This is true even when there is a voltage already present at the output during a pre-bias start-up. If selected, FPWM is enabled only after completion of tSS Triggering event EN and Output Voltages tEN V tSS VEN VOUT Set Point VOUT 90% of VOUT Set Point 0V t Time Triggering event tEN EN and Output Voltages • V tSS If selected, FPWM is enabled only after completion of tSS VEN VOUT Set Point VOUT 90% of VOUT Set Point 0V Time t Figure 8-8. Soft Start With and Without Pre-bias Voltage 8.3.10.1 Recovery from Dropout Any time the output voltage falls more than a few percent, output voltage ramps up slowly. This condition, called graceful recovery from dropout in this document, differs from soft start in two important ways: • • The reference voltage is set to approximately 1% above what is needed to achieve the existing output voltage. If the device is set to FPWM, it continues to operate in that mode during its recovery from dropout. If output voltage were to suddenly be pulled up by an external supply, the TLVM236x5 can pull down on the output. Note that all protections that are present during normal operation are in place, preventing any catastrophic failure if output is shorted to a high voltage or ground. Output Voltage and Current V Load current VOUT Set Point and max output current VOUT Slope the same as during soft start Time t Figure 8-9. Recovery from Dropout Whether output voltage falls due to high load or low input voltage, after the condition that causes output to fall below its set point is removed, the output climbs at the same speed as during start-up. Figure 8-9 shows an example of this behavior. 8.3.11 Overcurrent Protection (Hiccup Mode) The TLVM236x5 is protected from overcurrent conditions by using cycle-by-cycle current limiting circuitry on both the high-side (HS) and low-side (LS) MOSFETs. The current is compared every switching cycle to the current limit threshold. During an overcurrent condition, the output voltage decreases with reduced switching frequency. High-side MOSFET overcurrent protection is implemented by the typical peak-current mode control scheme. The HS switch current is sensed when the HS is turned on after a short blanking time. The HS switch current is compared to the minimum of a fixed current set point or the output of the internal error amplifier loop minus the slope compensation every switching cycle. Because the output of the internal error amplifier loop has a 20 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLVM23615 TLVM23625 www.ti.com TLVM23615, TLVM23625 SNVSCI2A – FEBRUARY 2023 – REVISED MARCH 2023 maximum value and slope compensation increases with duty cycle, HS current limit decreases with increased duty factor if duty cycle is above 35%. When the LS switch is turned on, the current going through it is also sensed and monitored. Like the high-side device, the low-side device has a turn-off commanded by the internal error amplifier loop. In the case of the low-side device, turn-off is prevented if the current exceeds this value, even if the oscillator normally starts a new switching cycle. Also like the high-side device, there is a limit on how high the turn-off current is allowed to be. This is called the low-side current limit. If the LS current limit is exceeded, the LS MOSFET stays on and the HS switch is not to be turned on. The LS switch is turned off after the LS current falls below this limit and the HS switch is turned on again as long as at least one clock period has passed since the last time the HS device has turned on. If, during current limit, the voltage on the FB input falls below about 0.4 V (VHICCUP) due to a short circuit, the device enters hiccup mode. In this mode, the device stops switching for tW or about 50 ms, and then goes through a normal re-start with soft start. If the short-circuit condition remains, the device runs in current limit for about 5 ms (typical) and then shuts down again. This cycle repeats as long as the short-circuit condition persists. 8.3.12 Thermal Shutdown Thermal shutdown limits total power dissipation by turning off the internal switches when the device junction temperature exceeds 168°C (typical). Thermal shutdown does not trigger below 158°C (minimum). After thermal shutdown occurs, hysteresis prevents the part from switching until the junction temperature drops to approximately 153°C (typical). When the junction temperature falls below 153°C (typical), the TLVM236x5 attempts another soft start. While the TLVM236x5 is shut down due to high junction temperature, power continues to be provided to VCC. To prevent overheating due to a short circuit applied to VCC, the LDO that provides power for VCC has reduced current limit while the part is disabled due to high junction temperature. The LDO only provides a few milliamperes during thermal shutdown. 8.4 Device Functional Modes 8.4.1 Shutdown Mode The EN pin provides electrical ON and OFF control of the device. When the EN pin voltage is below 0.7 V (typical), the power module does not have any output voltage and the device is in shutdown mode. In shutdown mode, the quiescent current drops to typically 250 nA. 8.4.2 Standby Mode The internal LDO has a lower EN threshold than the output EN threshold. When the EN pin voltage is above 1 V (maximum) and below the precision enable threshold for the output voltage, the internal LDO regulates the VCC voltage at 3.3 V typical. The internal power MOSFETs of the SW node remain off unless the voltage on EN pin goes above its precision enable threshold. The TLVM236x5 also employs UVLO protection. 8.4.3 Active Mode The TLVM236x5 is in active mode whenever the EN pin is above VEN_RISE, VIN is greater than VIN (min), and no other fault conditions are present. The simplest way to enable the operation is to connect the EN pin to VIN, which allows self start-up when the applied input voltage exceeds the minimum VIN (min). Depending on the load current, input voltage, and output voltage, the TLVM236x5 is in one of five modes: • • • • • Continuous conduction mode (CCM) with fixed switching frequency (fSW) when load current is above half of the inductor current ripple Auto mode - Light Load Operation: PFM where fSW is decreased at very light load FPWM mode - Light Load Operation: Continuous conduction mode (CCM) when the load current is lower than half of the inductor current ripple Minimum on time: At high input voltage and low output voltages, the fSW is reduced to maintain regulation Dropout mode: When fSW is reduced to minimize voltage dropout Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLVM23615 TLVM23625 21 TLVM23615, TLVM23625 SNVSCI2A – FEBRUARY 2023 – REVISED MARCH 2023 www.ti.com 8.4.3.1 CCM Mode The following operating description of the TLVM236x5 refers to Functional Block Diagram. In CCM, the TLVM236x5 supplies a regulated output voltage by turning on the internal high-side (HS) and low-side (LS) switches with varying duty cycle (D). During the HS switch on time, the SW pin voltage, VSW, swings up to approximately VIN, and the inductor current increases with a linear slope. The HS switch is turned off by the control logic. During the HS switch off time, tOFF, the LS switch is turned on. Inductor current discharges through the LS switch, which forces the VSW to swing below ground by the voltage drop across the LS switch. The buck module converter loop adjusts the duty cycle to maintain a constant output voltage. D is defined by the on time of the HS switch over the switching period: D = TON / TSW (10) In an ideal buck module converter where losses are ignored, D is proportional to the output voltage and inversely proportional to the input voltage: D = VOUT / VIN (11) 8.4.3.2 Auto Mode – Light-Load Operation The TLVM236x5 can have two behaviors while lightly loaded. One behavior, called auto mode operation, allows for seamless transition between normal current mode operation while heavily loaded and highly efficient light-load operation. The other behavior, called FPWM mode, maintains full frequency even when unloaded. Which mode the TLVM236x5 operates in depends on which variant from this family is selected. Note that all parts operate in FPWM mode when synchronizing frequency to an external signal. The light-load operation is employed in the TLVM236x5 only in auto mode. The light load operation employs two techniques to improve efficiency: • • Diode emulation, which allows DCM operation (See Figure 8-10) Frequency reduction (See Figure 8-11) Note that while these two features operate together to improve light load efficiency, they operate independently of each other. 8.4.3.2.1 Diode Emulation Diode emulation prevents reverse current through the inductor which potentially requires a lower frequency needed to regulate given a fixed peak inductor current. Diode emulation also limits ripple current as frequency is reduced. With a fixed peak current, as output current is reduced to zero, frequency must be reduced to near zero to maintain regulation. 22 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLVM23615 TLVM23625 TLVM23615, TLVM23625 www.ti.com SNVSCI2A – FEBRUARY 2023 – REVISED MARCH 2023 VOUT tON < VIN tSW D= VSW SW Voltage VIN tON tOFF tHIGHZ 0 t tSW Inductor Current iL ILPK IOUT 0 t In auto mode, the low-side device is turned off after SW node current is near zero. As a result, after output current is less than half of what inductor ripple can be in CCM, the part operates in DCM which is equivalent to the statement that diode emulation is active. Figure 8-10. PFM Operation The TLVM236x5 has a minimum peak inductor current setting (see IPEAKMIN in Electrical Characteristics) while in auto mode. After current is reduced to a low value with fixed input voltage, on time is constant. Regulation is then achieved by adjusting frequency. This mode of operation is called PFM mode regulation. 8.4.3.2.2 Frequency Reduction The TLVM236x5 reduces frequency whenever output voltage is high. This function is enabled whenever the internal error amplifier compensation output, COMP, an internal signal, is low and there is an offset between the regulation set point of VOUT/FB and the voltage applied to VOUT/FB. The net effect is that there is larger output impedance while lightly loaded in auto mode than in normal operation. Output voltage must be approximately 1% high when the part is completely unloaded. Output Voltage VOUT Current Limit 1% Above Set point VOUT Set Point 0 Output Current IOUT In auto mode, after output current drops below approximately 1/10th the rated current of the part, output resistance increases so that output voltage is 1% high while the buck is completely unloaded. Figure 8-11. Steady State Output Voltage Versus Output Current in Auto Mode In PFM operation, a small DC positive offset is required on the output voltage to activate the PFM detector. The lower the frequency in PFM, the more DC offset is needed on VOUT. If the DC offset on VOUT is not acceptable, a dummy load at VOUT or FPWM mode can be used to reduce or eliminate this offset. 8.4.3.3 FPWM Mode – Light-Load Operation In FPWM mode, frequency is maintained while the output is lightly loaded. To maintain frequency, a limited reverse current is allowed to flow through the inductor. Reverse current is limited by negative current limit circuitry, see Electrical Characteristics for negative current limit values. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLVM23615 TLVM23625 23 TLVM23615, TLVM23625 www.ti.com SNVSCI2A – FEBRUARY 2023 – REVISED MARCH 2023 VSW D= SW Voltage VIN tON VOUT § tSW VIN tOFF tON 0 t Inductor Current tSW iL ILPK IOUT 0 Iripple t In FPWM mode, Continuous Conduction (CCM) is possible even if IOUT is less than half of Iripple. Figure 8-12. FPWM Mode Operation For all devices, in FPWM mode, frequency reduction is still available if output voltage is high enough to command minimum on time even while lightly loaded, allowing good behavior during faults which involve output being pulled up. 8.4.3.4 Minimum On-Time (High Input Voltage) Operation The TLVM236x5 continues to regulate output voltage even if the input-to-output voltage ratio requires an on time less than the minimum on time of the chip with a given clock setting. This is accomplished using valley current control. At all times, the compensation circuit dictates both a maximum peak inductor current and a maximum valley inductor current. If for any reason, valley current is exceeded, the clock cycle is extended until valley current falls below that determined by the compensation circuit. If the power module is not operating in current limit, the maximum valley current is set above the peak inductor current, preventing valley control from being used unless there is a failure to regulate using peak current only. If the input-to-output voltage ratio is too high, such that the inductor current peak value exceeds the peak command dictated by compensation, the high-side device cannot be turned off quickly enough to regulate output voltage. As a result, the compensation circuit reduces both peak and valley current. After a low enough current is selected by the compensation circuit, valley current matches that being commanded by the compensation circuit. Under these conditions, the low-side device is kept on and the next clock cycle is prevented from starting until inductor current drops below the desired valley current. Because on time is fixed at its minimum value, this type of operation resembles that of a device using a Constant On-Time (COT) control scheme; see Figure 8-13. 24 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLVM23615 TLVM23625 TLVM23615, TLVM23625 www.ti.com SNVSCI2A – FEBRUARY 2023 – REVISED MARCH 2023 SW Voltage VSW D= VIN tON VOUT § tSW VIN tON = tON_MIN tOFF 0 - IOUTÂ5DSLS t Inductor Current tSW > Clock setting iL IOUT Iripple ILVLY t 0 In valley control mode, minimum inductor current is regulated, not peak inductor current. Figure 8-13. Valley Current Mode Operation 8.4.3.5 Dropout Dropout operation is defined as any input-to-output voltage ratio that requires frequency to drop to achieve the required duty cycle. At a given clock frequency, duty cycle is limited by minimum off time. After this limit is reached as shown in Figure 8-15 if clock frequency was to be maintained, the output voltage can fall. Instead of allowing the output voltage to drop, the TLVM236x5 extends the high-side switch on time past the end of the clock cycle until the needed peak inductor current is achieved. The clock is allowed to start a new cycle after peak inductor current is achieved or after a pre-determined maximum on time, tON-MAX, of approximately 9 µs passes. As a result, after the needed duty cycle cannot be achieved at the selected clock frequency due to the existence of a minimum off time, frequency drops to maintain regulation. As shown in Figure 8-14, if input voltage is low enough so that output voltage cannot be regulated even with an on time of tON-MAX, output voltage drops to slightly below the input voltage by VDROP. For additional information on recovery from dropout, refer to Section 8.3.10.1. Input Voltage Output Voltage VOUT VDROP Output Setting Switching Frequency 0 Output Voltage Input Voltage VIN FSW FSW-NOM ≅110kHz 0 Input Voltage VIN Output voltage and frequency versus input voltage: If there is little difference between input voltage and output voltage setting, the IC reduces frequency to maintain regulation. If input voltage is too low to provide the desired output voltage at approximately 110 kHz, input voltage tracks output voltage. Figure 8-14. Frequency and Output Voltage in Dropout Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLVM23615 TLVM23625 25 TLVM23615, TLVM23625 www.ti.com SNVSCI2A – FEBRUARY 2023 – REVISED MARCH 2023 SW Voltage VSW VIN D= tON VOUT § tSW VIN tOFF = tOFF_MIN tON < tON_MAX 0 - IOUTÂ5DSLS t Inductor Current tSW > Clock setting iL ILPK IOUT 0 Iripple t Switching waveforms while in dropout. Inductor current takes longer than a normal clock to reach the desired peak value. As a result, frequency drops. This frequency drop is limited by tON-MAX. Figure 8-15. Dropout Waveforms 26 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLVM23615 TLVM23625 TLVM23615, TLVM23625 www.ti.com SNVSCI2A – FEBRUARY 2023 – REVISED MARCH 2023 9 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. 9.1 Application Information The TLVM236x5 only requires a few external components to convert from a wide range of supply voltages to a fixed output voltage. To expedite and streamline the process of designing of a TLVM236x5, WEBENCH online software is available to generate complete designs, leveraging iterative design procedures and access to comprehensive component databases. The following section describes the design procedure to configure the TLVM236x5 power module. As mentioned previously, the TLVM236x5 also integrates several optional features to meet system design requirements, including precision enable, UVLO, and PGOOD indicator. The application circuit detailed below shows TLVM236x5 configuration options suitable for several application use cases. Refer to the TLVM23625EVM User's Guide for more detail. Note All of the capacitance values given in the following application information refer to effective values unless otherwise stated. The effective value is defined as the actual capacitance under DC bias and temperature, not the rated or nameplate values. Use high-quality, low-ESR, ceramic capacitors with an X7R or better dielectric throughout. All high value ceramic capacitors have a large voltage coefficient in addition to normal tolerances and temperature effects. Under DC bias the capacitance drops considerably. Large case sizes and higher voltage ratings are better in this regard. To help mitigate these effects, multiple capacitors can be used in parallel to bring the minimum effective capacitance up to the required value. This can also ease the RMS current requirements on a single capacitor. A careful study of bias and temperature variation of any capacitor bank must be made to ensure that the minimum value of effective capacitance is provided. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLVM23615 TLVM23625 27 TLVM23615, TLVM23625 www.ti.com SNVSCI2A – FEBRUARY 2023 – REVISED MARCH 2023 9.2 Typical Application Figure 9-1 shows a typical application circuit for the TLVM236x5. This device is designed to function over a wide range of external components and system parameters. However, the internal compensation is optimized for a certain range of switching frequencies and output capacitance. VIN CIN VOUT VOUT VIN CHF SW 4.7 µF COUT EN BOOT RFBT RT A B PGOOD C FB VCC A = 200 kHz to 2.2 MHz or B = 2.2 MHz or C = 1 MHz A. CVCC 1 µF GND RFBB The RT pin is factory-set for externally adjustable switching frequency RT variants only. See Switching Frequency (RT) for details. Figure 9-1. Example Application Circuit (TLVM236x5) 28 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLVM23615 TLVM23625 TLVM23615, TLVM23625 www.ti.com SNVSCI2A – FEBRUARY 2023 – REVISED MARCH 2023 9.2.1 Design Requirements Detailed Design Procedure provides instructions to design and select components according to Table 9-1. Table 9-1. Detailed Design Parameters DESIGN PARAMETER EXAMPLE VALUE Input voltage 5.5 V to 36 V Output voltage 5V Maximum output current 0 A to 2.5 A Switching frequency 1 MHz 9.2.2 Detailed Design Procedure The design procedure that follows and the resulting component selection is illustrated in Figure 9-2. 5V 5.5 V to 36 V VOUT VIN 4.7 µF 50 VDC 0.1 µF 50 VDC SW 2 × 22 µF 16VDC EN BOOT RT PGOOD FB VCC 1 µF 16 VDC 40.2 k
GND 10 k Figure 9-2. 5-V VOUT Design Example 9.2.2.1 Custom Design With WEBENCH® Tools Click here to create a custom design using the TLVM236x5 devices with the WEBENCH® Power Designer. 1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements. 2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial 3. Compare the generated design with other possible solutions from Texas Instruments. The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricing and component availability. In most cases, these actions are available: • Run electrical simulations to see important waveforms and circuit performance • Run thermal simulations to understand board thermal performance • Export customized schematic and layout into popular CAD formats • Print PDF reports for the design, and share the design with colleagues Get more information about WEBENCH tools at www.ti.com/WEBENCH. 9.2.2.2 Choosing the Switching Frequency The recommended switching frequency for standard output voltages can be found in Table 8-1. For a 5-V output, the recommended switching frequency is 1 MHz. To set the switching frequency to 1 MHz, connect the RT pin to VCC. 9.2.2.3 Setting the Output Voltage Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLVM23615 TLVM23625 29 TLVM23615, TLVM23625 SNVSCI2A – FEBRUARY 2023 – REVISED MARCH 2023 www.ti.com The adjustable output voltage is externally set with a resistor divider. For more information on how to choose the feedback resistor values, please see Output Voltage Selection. The recommended value of RFBB is 10 kΩ. For more information The value for RFBT can be selected from Table 8-1 or calculated using Equation 12: RFBT kΩ = RFBB kΩ × VOUT V −1 1V (12) For the desired output voltage of 5 V, the formula yields a value of 40.2 kΩ. Choose the closest available standard value of 40.2 kΩ for RFBT. 9.2.2.4 Input Capacitor Selection The TLVM236x5 requires a minimum input capacitance of 4.7 μF. TI recommends an additional 0.1-μF capacitor in parallel for improved bypassing. High-quality ceramic type capacitors with sufficient voltage and temperature rating are required. The voltage rating of input capacitors must be greater than the maximum input voltage. For this design, a 4.7 μF and a 0.1 μF, 50-V rated capacitor are used. Using an electrolytic capacitor on the input in parallel with the ceramics is often desirable. This fact is especially true if long leads or traces are used to connect the input supply to the regulator. The moderate ESR of this capacitor can help damp any ringing on the input supply caused by the long power leads. The use of this additional capacitor also helps with voltage dips caused by input supplies with unusually high impedance. Refer to Table 8-2 for example input capacitor part numbers to consider. 9.2.2.5 Output Capacitor Selection For a 5 V output, the TLVM236x5 requires a minimum of 25 µF effective output capacitance for proper operation (see Table 8-1). High-quality ceramic type capacitors with sufficient voltage and temperature rating are required. Additional output capacitance can be added to reduce ripple voltage or for applications with transient load requirements. In practice, the output capacitor has the most influence on the transient response and loop-phase margin. Load transient testing and bode plots are the best way to validate any given design and must always be completed before the application goes into production. Limit the maximum value of total output capacitance to about 10 times the design value, or 1000 µF, whichever is smaller. Large values of output capacitance can adversely affect the start-up behavior of the regulator as well as the loop stability. If values larger than noted here must be used, then a careful study of start-up at full load and loop stability must be performed. For this design example, select 2 x 22 µF, 16 V, 1210 case size, ceramic capacitors, which have a total effective capacitance of approximately 40 µF at 5 V. Review Table 8-3 for example output capacitor selection. 9.2.2.6 VCC The VCC pin is the output of the internal LDO used to supply the control circuits of the regulator. This output requires a 1 µF, 16 V ceramic capacitor connected from VCC to GND for proper operation. In general, this output must not be loaded with any external circuitry. However, this output can be used to supply the pullup for the power-good function (see Power-Good Output Operation). A value in the range of 10 kΩ to 100 kΩ is a good choice in this case. The nominal output voltage on VCC is 3.3 V; see Electrical Characteristics for limits. 9.2.2.7 CFF Selection In some cases, a feedforward capacitor can be used across RFBT to improve the load transient response or improve the loop-phase margin. Optimizing Transient Response of Internally Compensated DC-DC Converters with Feedforward Capacitor application report is helpful when experimenting with a feedforward capacitor. Due to the nature of the feedback detect circuitry, the value of CFF must be limited to ensure that the desired output voltage is established when configuring for adjustable output voltages. Equation 13 must be followed to ensure CFF remains below the maximum value. 30 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLVM23615 TLVM23625 TLVM23615, TLVM23625 www.ti.com SNVSCI2A – FEBRUARY 2023 – REVISED MARCH 2023 CFF < COUT × VOUT 1.2 × 106 (13) 9.2.2.8 Power-Good Signal Applications requiring a power-good signal to indicate that the output voltage is present and in regulation must use a pullup resistor between the PGOOD pin and a valid voltage source. This voltage source can be VCC or VOUT, as example. 9.2.2.9 Maximum Ambient Temperature As with any power conversion device, the TLVM236x5 dissipates internal power while operating. The effect of this power dissipation is to raise the internal temperature of the power module above ambient. The internal die and inductor temperature (TJ) is a function of the ambient temperature, the power loss, and the effective thermal resistance, RθJA, of the module and PCB combination. The maximum junction temperature for the TLVM236x5 must be limited to 125°C. This limit establishes a limit on the maximum module power dissipation and, therefore, the load current. Equation 14 shows the relationships between the important parameters. Seeing that larger ambient temperatures (TA) and larger values of RθJA reduce the maximum available output current is easy. The power module efficiency can be estimated by using the curves provided in this data sheet. If the desired operating conditions cannot be found in one of the curves, interpolation can be used to estimate the efficiency. Alternatively, the EVM can be adjusted to match the desired application requirements and the efficiency can be measured directly. The correct value of RθJA is more difficult to estimate. Lastly, safe-operation-area curves and module thermal captures developed through bench analysis on the EVM can be used to provide insights on the output power capability. These curves can be found in the Application Curves section of the data sheet. As stated in the Semiconductor and IC Package Thermal Metrics application report the values given in Thermal Information section are not valid for design purposes and must not be used to estimate the thermal performance of the application. The values reported in that table were measured under a specific set of conditions that are rarely obtained in an actual application. where • IOUT, max = TJ − TA η 1 RθJA × 1 − η × η (14) η is the efficiency. The effective RθJA (TLVM23625EVM = 22°C/W) is a critical parameter and depends on many factors such as the following: • • • • • • Power dissipation Air temperature/flow PCB area Copper heat-sink area Adjacent component placement Number of thermal vias under the package The IC Power loss mentioned above is the overall power loss minus the loss that comes from the inductor DC resistance. The overall power loss can be approximated by using WEBENCH for a specific operating condition and temperature. Use the following resources as guides to optimal thermal PCB design and estimating RθJA for a given application environment: • • • • • • Thermal Design by Insight not Hindsight Application Report A Guide to Board Layout for Best Thermal Resistance for Exposed Pad Packages Application Report Semiconductor and IC Package Thermal Metrics Application Report Thermal Design Made Simple with LM43603 and LM43602 Application Report PowerPAD™ Thermally Enhanced Package Application Report PowerPAD™ Made Easy Application Report Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLVM23615 TLVM23625 31 TLVM23615, TLVM23625 SNVSCI2A – FEBRUARY 2023 – REVISED MARCH 2023 • • www.ti.com Using New Thermal Metrics Application Report PCB Thermal Calculator 9.2.2.10 Other Connections • • • • • 32 The RT pin can be connected to AGND for a switching frequency of 2.2 MHz or tied to VCC for a switching frequency of 1 MHz. A resistor connected between the RT pin and GND can be used to set the desired operating frequency between 200 kHz and 2.2 MHz. For the MODE/SYNC pin variant, connecting this pin to an external clock forces the device into SYNC operation. Connecting the MODE/SYNC pin low allows the device to operate in PFM mode at light load. Connecting the MODE/SYNC pin high puts the device into FPWM mode and allows full frequency operation independent of load current. A resistor divider network on the EN pin can be added for a precision input undervoltage lockout (UVLO) Place a 1-µF capacitor between the VCC pin and PGND, located near to the device. A pullup resistor between the PGOOD pin and a valid voltage source to generate a power-good signal. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLVM23615 TLVM23625 TLVM23615, TLVM23625 www.ti.com SNVSCI2A – FEBRUARY 2023 – REVISED MARCH 2023 9.2.3 Application Curves 100 100 95 95 90 90 Efficiency (%) Efficiency (%) COUT = 2 × 22 uF (1210,16VDC) 85 80 1.8V, 300kHz 2.5V, 800kHz 3.3V, 1MHz 5V, 1MHz 5V, 2MHz 75 70 65 60 0.001 85 80 70 65 0.01 0.1 Load Current (A) 1 60 0.001 2.5 110 95 105 90 100 85 95 90 85 80 70 65 0.5 1.8V, 300kHz 2.5V, 800kHz 5V/3.3V, 1MHz 5V/3.3V, 2MHz 0.75 1 0.501 1.001 1.501 2.001 Load Current (A) 2.5 Figure 9-4. 12VIN Efficiency (Linear) Efficiency (%) Ambient Temperature (°C) Figure 9-3. 12VIN Efficiency (Log) 75 1.8V, 300kHz 2.5V, 800kHz 3.3V, 1MHz 5V, 1MHz 5V, 2MHz 75 80 75 1.8V, 300kHz 2.5V, 800kHz 3.3V, 1MHz 5V, 1MHz 5V, 2MHz 70 65 60 55 50 0.001 1.25 1.5 1.75 Load Current (A) 2 2.25 2.5 0.01 0.1 Load Current (A) 1 2.5 2.25 2.5 Figure 9-6. 24VIN Efficiency (Log) 95 110 90 105 85 Ambient Temperarture (°C) Efficiency (%) Figure 9-5. 12VIN: Max Ambient Temperature vs Load Current (Analysis on TLVM23625EVM) 80 75 70 65 60 55 50 0.001 1.8V, 300kHz 2.5V, 800kHz 3.3V, 1MHz 5V, 1MHz 5V, 2MHz 0.501 100 95 90 85 80 75 70 65 60 1.001 1.501 2.001 Load Current (A) Figure 9-7. 24VIN Efficiency (Linear) 2.5 55 0.5 1.8V, 300kHz 2.5V, 800kHz 5V/3.3V, 1MHz 5V/3.3V, 2MHz 0.75 1 1.25 1.5 1.75 Load Current (A) 2 Figure 9-8. 24VIN: Max Ambient Temperature vs Load Current (Analysis on TLVM23625EVM) Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLVM23615 TLVM23625 33 TLVM23615, TLVM23625 www.ti.com SNVSCI2A – FEBRUARY 2023 – REVISED MARCH 2023 9.2.3 Application Curves (continued) 95 90 85 80 75 70 65 60 55 50 45 40 0.001 Efficiency (%) Efficiency (%) COUT = 2 × 22 uF (1210,16VDC) 1.8V, 300kHz 2.5V, 800kHz 3.3V, 1MHz 5V, 1MHz 5V, 2MHz 0.01 0.1 Load Current (A) 1 2.5 Ambient Temperarture (°C) 1.8V, 300kHz 2.5V, 800kHz 3.3V, 1MHz 5V, 1MHz 5V, 2MHz 0.501 1.001 1.501 2.001 Load Current (A) 2.5 Figure 9-10. 36VIN Efficiency (Linear) Figure 9-9. 36VIN Efficiency (Log) 110 105 100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 0.5 95 90 85 80 75 70 65 60 55 50 45 40 0.001 1.8V, 300kHz 2.5V, 800kHz 5V/3.3V, 1MHz 5V/3.3V, 2MHz 0.75 1 1.25 1.5 1.75 Load Current (A) 2 2.25 2.5 Figure 9-11. 36VIN: Maximum Ambient Temperature vs Load Current (Analysis on TLVM23625EVM) VIN = 24 V 0 A to 2.5 A,1 A/µs VOUT = 5 V COUT = 2 × 22 uF (1210,16VDC) 1 MHz (FPWM) Figure 9-12. Load Transient VIN = 24 V 1.25 A to 2.5 A,1 A/µs VOUT = 5 V 1 MHz (FPWM) VIN = 12 V VOUT = 3.3 V 2 A, 500 kHz Figure 9-14. EVM Thermal Performance Figure 9-13. Load Transient 34 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLVM23615 TLVM23625 TLVM23615, TLVM23625 www.ti.com SNVSCI2A – FEBRUARY 2023 – REVISED MARCH 2023 9.2.3 Application Curves (continued) COUT = 2 × 22 uF (1210,16VDC) VIN = 12 V VOUT = 3.3 V 2 A, 1 MHz Figure 9-15. EVM Thermal Performance VIN = 24 V VOUT = 3.3 V 2 A, 500 kHz Figure 9-17. EVM Thermal Performance VIN = 24 V VOUT = 3.3 V VIN = 12 V VOUT = 3.3 V 2 A, 2.2 MHz Figure 9-16. EVM Thermal Performance VIN = 24 V VOUT = 3.3 V 2 A, 1 MHz Figure 9-18. EVM Thermal Performance 2 A, 2.2 MHz Figure 9-19. EVM Thermal Performance VIN = 24 V VOUT = 5 V Board = TLVM23625EVM Fsw = 1 MHz Load = 2.5 A Figure 9-20. CISPR 11, Class B, CE Scan 150 kHz–30 MHz Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLVM23615 TLVM23625 35 TLVM23615, TLVM23625 www.ti.com SNVSCI2A – FEBRUARY 2023 – REVISED MARCH 2023 9.2.3 Application Curves (continued) COUT = 2 × 22 uF (1210,16VDC) CISPR 11 Class B QPk Radiated Emmissions 60 55 Amplitude (dBuV/m) 50 Horizontal Amplitude Vertical Amplitude Class B (3M) QPk Limit 45 40 35 30 25 20 15 10 5 30 40 50 6070 100 200 300 400500 700 1000 Frequency (MHz) VIN = 24 V VOUT = 5 V Board = TLVM23625EVM (No Filter) Fsw = 1 MHz Load = 2.5 A Figure 9-21. CISPR 11 RE, 3-Meter, Scan 30 MHz–1 GHz 36 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLVM23615 TLVM23625 TLVM23615, TLVM23625 www.ti.com SNVSCI2A – FEBRUARY 2023 – REVISED MARCH 2023 9.3 Best Design Practices • • • • • • Do not exceed the Absolute Maximum Ratings. Do not exceed the Recommended Operating Conditions. Do not exceed the ESD Ratings. Do not allow the EN input to float. Do not allow the output voltage to exceed the input voltage, nor go below ground. Follow all the guidelines and suggestions found in this data sheet before committing the design to production. TI application engineers are ready to help critique your design and PCB layout to help make your project a success. 9.4 Power Supply Recommendations The TLVM236x5 buck module is designed to operate over a wide input voltage range of 3 V to 36 V. The characteristics of the input supply must be compatible with the Absolute Maximum Ratings and Recommended Operating Conditions in this data sheet. In addition, the input supply must be capable of delivering the required input current to the loaded regulator circuit. Estimate the average input current with Equation 15. where • V × IOUT IIN = OUT VIN × η (15) η is the efficiency If the module is connected to an input supply through long wires or PCB traces with a large impedance, take special care to achieve stable performance. The parasitic inductance and resistance of the input cables can have an adverse affect on module operation. More specifically, the parasitic inductance in combination with the low-ESR ceramic input capacitors form an underdamped resonant circuit, possibly resulting in instability, voltage transients, or both, each time the input supply is cycled ON and OFF. The parasitic resistance causes the input voltage to dip during a load transient. If the module is operating close to the minimum input voltage, this dip can cause false UVLO triggering and a system reset. The best way to solve such issues is to reduce the distance from the input supply to the module and use an electrolytic input capacitor in parallel with the ceramics. The moderate ESR of the electrolytic capacitor helps damp the input resonant circuit and reduce any overshoot or undershoot at the input. A capacitance in the range of 47 μF to 100 μF is usually sufficient to provide input parallel damping and helps hold the input voltage steady during large load transients. A typical ESR of 0.1 Ω to 0.4 Ω provides enough damping for most input circuit configurations. 9.5 Layout The performance of any switching power supply depends as much upon the layout of the PCB as the component selection. Use the following guidelines to design a PCB with the best power conversion performance, optimal thermal performance, and minimal generation of unwanted EMI. 9.5.1 Layout Guidelines The PCB layout of any DC/DC module is critical to the optimal performance of the design. Poor PCB layout can disrupt the operation of an otherwise good schematic design. Even if the module regulates correctly, bad PCB layout can mean the difference between a robust design and one that cannot be mass produced. Furthermore, to a great extent, the EMI performance of the regulator is dependent on the PCB layout. In a buck converter module, the most critical PCB feature is the loop formed by the input capacitor or capacitors and power ground, as shown in Figure 9-22. This loop carries large transient currents that can cause large transient voltages when reacting with the trace inductance. These unwanted transient voltages disrupt the proper operation of the power module. Because of this, the traces in this loop must be wide and short, and the loop area as small as possible to reduce the parasitic inductance. Section 9.5.2 shows a recommended layout for the critical components of the TLVM236x5. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLVM23615 TLVM23625 37 TLVM23615, TLVM23625 www.ti.com SNVSCI2A – FEBRUARY 2023 – REVISED MARCH 2023 1. Place the input capacitors as close as possible to the VIN and GND terminals. VIN and GND pins are adjacent, simplifying the input capacitor placement. 2. Place bypass capacitor for VCC close to the VCC pin. This capacitor must be placed close to the device and routed with short, wide traces to the VCC and GND pins. 3. Place the feedback divider as close as possible to the FB pin of the device. Place RFBB, RFBT, and CFF, if used, physically close to the device. The connections to FB and GND must be short and close to those pins on the device. The connection to VOUT can be somewhat longer. However, the latter trace must not be routed near any noise source (such as the SW node) that can capacitively couple into the feedback path of the regulator. 4. Use at least one ground plane in one of the middle layers. This plane acts as a noise shield and as a heat dissipation path. 5. Provide wide paths for VIN, VOUT, and GND. Making these paths as wide and direct as possible reduces any voltage drops on the input or output paths of the power module and maximizes efficiency. 6. Provide enough PCB area for proper heat-sinking. Sufficient amount of copper area must be used to ensure a low RθJA, commensurate with the maximum load current and ambient temperature. The top and bottom PCB layers must be made with two ounce copper and no less than one ounce. If the PCB design uses multiple copper layers (recommended), these thermal vias can also be connected to the inner layer heat-spreading ground planes. 7. Use multiple vias to connect the power planes to internal layers. See the following PCB layout resources for additional important guidelines: • • • • Layout Guidelines for Switching Power Supplies Application Report Simple Switcher PCB Layout Guidelines Application Report Construction Your Power Supply- Layout Considerations Seminar Low Radiated EMI Layout Made Simple with LM4360x and LM4600x Application Report VIN SW GND Figure 9-22. Current Loops with Fast Edges 9.5.1.1 Ground and Thermal Considerations As previously mentioned, TI recommends using one of the middle layers as a solid ground plane. A ground plane provides shielding for sensitive circuits and traces as well as a quiet reference potential for the control circuitry. Connect the GND pin to the ground planes using vias next to the bypass capacitors. The GND trace, as well as the VIN and SW traces, must be constrained to one side of the ground planes. The other side of the ground plane contains much less noise; use for sensitive routes. TI recommends providing adequate device heat-sinking by having enough copper near the GND pin. See Figure 9-23 for example layout. Use as much copper as possible, for system ground plane, on the top and bottom layers for the best heat dissipation. Use a four-layer board with the copper thickness for the four layers, starting from the top as: 2 oz / 1 oz / 1 oz / 2 oz. A four-layer board with enough copper thickness, and proper layout, provides low current conduction impedance, proper shielding and lower thermal resistance. 38 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLVM23615 TLVM23625 TLVM23615, TLVM23625 www.ti.com SNVSCI2A – FEBRUARY 2023 – REVISED MARCH 2023 9.5.2 Layout Example Keep FB, RT, VCC trace small Maintain continuous ground pours VCC Top Layer FB GND RT Mid layer VOUT VOUT ~100nF, 0402/0603 capacitor nearest to Vin pin VIN Keep output cap close Keep input cap close Large VOUT pour for cooling Figure 9-23. Example Layout Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLVM23615 TLVM23625 39 TLVM23615, TLVM23625 www.ti.com SNVSCI2A – FEBRUARY 2023 – REVISED MARCH 2023 10 Device and Documentation Support 10.1 Device Support 10.1.1 Third-Party Products Disclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE. 10.1.2 Development Support 10.1.2.1 Custom Design With WEBENCH® Tools Click here to create a custom design using the TLVM236x5 devices with the WEBENCH® Power Designer. 1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements. 2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial 3. Compare the generated design with other possible solutions from Texas Instruments. The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricing and component availability. In most cases, these actions are available: • Run electrical simulations to see important waveforms and circuit performance • Run thermal simulations to understand board thermal performance • Export customized schematic and layout into popular CAD formats • Print PDF reports for the design, and share the design with colleagues Get more information about WEBENCH tools at www.ti.com/WEBENCH. 10.1.3 Device Nomenclature Figure 10-1 shows the device naming nomenclature of the TLVM236x5. See Section 5 for the availability of each variant. Contact TI sales representatives or on TI's E2E forum for detail and availability of other options; minimum order quantities apply. TLVM X 236 XX X RDNR SPREAD SPECTRUM 2: No 3: Yes OUTPUT CURRENT MAX FSW MODE OPTION PACKAGE 15: 1.5 A F: MODE/SYNC Trim RDNR = QFN 11-pin large reel 25: 2.5 A * (Fixed Frequency FSW = 1 MHz) * No alpha character means FSW is set by the RT pin Figure 10-1. Device Naming Nomenclature 10.2 Documentation Support 10.2.1 Related Documentation For related documentation see the following: • Texas Instruments, Thermal Design by Insight not Hindsight Application Report • Texas Instruments, A Guide to Board Layout for Best Thermal Resistance for Exposed Pad Packages Application Report • Texas Instruments, Semiconductor and IC Package Thermal Metrics Application Report • Texas Instruments, Thermal Design Made Simple with LM43603 and LM43602 Application Report • Texas Instruments, PowerPAD™ Thermally Enhanced Package Application Report • Texas Instruments, PowerPAD™ Made Easy Application Report • Texas Instruments, Using New Thermal Metrics Application Report 40 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLVM23615 TLVM23625 TLVM23615, TLVM23625 www.ti.com • • • • SNVSCI2A – FEBRUARY 2023 – REVISED MARCH 2023 Texas Instruments, Layout Guidelines for Switching Power Supplies Application Report Texas Instruments, Simple Switcher PCB Layout Guidelines Application Report Texas Instruments, Construction Your Power Supply- Layout Considerations Seminar Texas Instruments, Low Radiated EMI Layout Made Simple with LM4360x and LM4600x Application Report 10.3 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 10.4 Trademarks HotRod™, PowerPAD™, and TI E2E™ are trademarks of Texas Instruments. WEBENCH® is a registered trademark of Texas Instruments. All trademarks are the property of their respective owners. 10.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 10.6 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLVM23615 TLVM23625 41 TLVM23615, TLVM23625 SNVSCI2A – FEBRUARY 2023 – REVISED MARCH 2023 www.ti.com 11 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 42 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLVM23615 TLVM23625 PACKAGE OPTION ADDENDUM www.ti.com 16-Mar-2023 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) TLVM23615RDNR ACTIVE QFN-FCMOD RDN 11 3000 RoHS & Green SN Level-3-260C-168 HR -40 to 125 23615 Samples TLVM23625RDNR ACTIVE QFN-FCMOD RDN 11 3000 RoHS & Green SN Level-3-260C-168 HR -40 to 125 23625 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of