TE X AS I NS TRUM E NTS - P RO DUCTION D ATA
Tiva™ TM4C1237H6PZ Microcontroller
D ATA SHE E T
D S -T M 4C 1237 H6 P Z - 1 5 8 4 2 . 2 7 4 1
S P M S 362E
C o p yri g h t © 2 0 07-2014
Te xa s In stru me n ts In co rporated
Copyright
Copyright © 2007-2014 Texas Instruments Incorporated. Tiva and TivaWare are trademarks of Texas Instruments Incorporated. ARM and Thumb are
registered trademarks and Cortex is a trademark of ARM Limited. All other trademarks are the property of others.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard
warranty. Production processing does not necessarily include testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor
products and disclaimers thereto appears at the end of this data sheet.
Texas Instruments Incorporated
108 Wild Basin, Suite 350
Austin, TX 78746
http://www.ti.com/tm4c
http://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm
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Tiva™ TM4C1237H6PZ Microcontroller
Table of Contents
Revision History ............................................................................................................................. 36
About This Document .................................................................................................................... 40
Audience ..............................................................................................................................................
About This Manual ................................................................................................................................
Related Documents ...............................................................................................................................
Documentation Conventions ..................................................................................................................
40
40
40
41
1
Architectural Overview .......................................................................................... 43
1.1
1.2
1.3
1.3.1
1.3.2
1.3.3
1.3.4
1.3.5
1.3.6
1.3.7
1.4
1.5
1.6
Tiva™ C Series Overview .............................................................................................. 43
TM4C1237H6PZ Microcontroller Overview ..................................................................... 44
TM4C1237H6PZ Microcontroller Features ...................................................................... 46
ARM Cortex-M4F Processor Core .................................................................................. 46
On-Chip Memory ........................................................................................................... 48
Serial Communications Peripherals ................................................................................ 50
System Integration ........................................................................................................ 54
Analog .......................................................................................................................... 60
JTAG and ARM Serial Wire Debug ................................................................................ 62
Packaging and Temperature .......................................................................................... 62
TM4C1237H6PZ Microcontroller Hardware Details .......................................................... 62
Kits .............................................................................................................................. 63
Support Information ....................................................................................................... 63
2
The Cortex-M4F Processor ................................................................................... 64
2.1
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.3
2.3.1
2.3.2
2.3.3
2.3.4
2.3.5
2.3.6
2.4
2.4.1
2.4.2
2.4.3
2.4.4
2.4.5
2.4.6
2.4.7
2.5
2.5.1
2.5.2
Block Diagram .............................................................................................................. 65
Overview ...................................................................................................................... 66
System-Level Interface .................................................................................................. 66
Integrated Configurable Debug ...................................................................................... 66
Trace Port Interface Unit (TPIU) ..................................................................................... 67
Cortex-M4F System Component Details ......................................................................... 67
Programming Model ...................................................................................................... 68
Processor Mode and Privilege Levels for Software Execution ........................................... 68
Stacks .......................................................................................................................... 69
Register Map ................................................................................................................ 69
Register Descriptions .................................................................................................... 71
Exceptions and Interrupts .............................................................................................. 87
Data Types ................................................................................................................... 87
Memory Model .............................................................................................................. 87
Memory Regions, Types and Attributes ........................................................................... 90
Memory System Ordering of Memory Accesses .............................................................. 90
Behavior of Memory Accesses ....................................................................................... 90
Software Ordering of Memory Accesses ......................................................................... 91
Bit-Banding ................................................................................................................... 92
Data Storage ................................................................................................................ 94
Synchronization Primitives ............................................................................................. 95
Exception Model ........................................................................................................... 96
Exception States ........................................................................................................... 97
Exception Types ............................................................................................................ 97
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2.5.3
2.5.4
2.5.5
2.5.6
2.5.7
2.6
2.6.1
2.6.2
2.6.3
2.6.4
2.7
2.7.1
2.7.2
2.8
Exception Handlers .....................................................................................................
Vector Table ................................................................................................................
Exception Priorities ......................................................................................................
Interrupt Priority Grouping ............................................................................................
Exception Entry and Return .........................................................................................
Fault Handling .............................................................................................................
Fault Types .................................................................................................................
Fault Escalation and Hard Faults ..................................................................................
Fault Status Registers and Fault Address Registers ......................................................
Lockup .......................................................................................................................
Power Management ....................................................................................................
Entering Sleep Modes .................................................................................................
Wake Up from Sleep Mode ..........................................................................................
Instruction Set Summary ..............................................................................................
101
101
102
103
103
106
107
107
108
108
109
109
109
110
3
Cortex-M4 Peripherals ......................................................................................... 117
3.1
3.1.1
3.1.2
3.1.3
3.1.4
3.1.5
3.2
3.3
3.4
3.5
3.6
3.7
Functional Description ................................................................................................. 117
System Timer (SysTick) ............................................................................................... 118
Nested Vectored Interrupt Controller (NVIC) .................................................................. 119
System Control Block (SCB) ........................................................................................ 120
Memory Protection Unit (MPU) ..................................................................................... 120
Floating-Point Unit (FPU) ............................................................................................. 125
Register Map .............................................................................................................. 129
System Timer (SysTick) Register Descriptions .............................................................. 132
NVIC Register Descriptions .......................................................................................... 136
System Control Block (SCB) Register Descriptions ........................................................ 151
Memory Protection Unit (MPU) Register Descriptions .................................................... 180
Floating-Point Unit (FPU) Register Descriptions ............................................................ 189
4
JTAG Interface ...................................................................................................... 195
4.1
4.2
4.3
4.3.1
4.3.2
4.3.3
4.3.4
4.4
4.5
4.5.1
4.5.2
Block Diagram ............................................................................................................
Signal Description .......................................................................................................
Functional Description .................................................................................................
JTAG Interface Pins .....................................................................................................
JTAG TAP Controller ...................................................................................................
Shift Registers ............................................................................................................
Operational Considerations ..........................................................................................
Initialization and Configuration .....................................................................................
Register Descriptions ..................................................................................................
Instruction Register (IR) ...............................................................................................
Data Registers ............................................................................................................
196
196
197
197
199
199
200
202
203
203
205
5
System Control ..................................................................................................... 207
5.1
5.2
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
5.2.6
Signal Description .......................................................................................................
Functional Description .................................................................................................
Device Identification ....................................................................................................
Reset Control ..............................................................................................................
Non-Maskable Interrupt ...............................................................................................
Power Control .............................................................................................................
Clock Control ..............................................................................................................
System Control ...........................................................................................................
4
207
207
207
208
213
213
214
221
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5.3
5.4
5.5
5.6
Initialization and Configuration .....................................................................................
Register Map ..............................................................................................................
System Control Register Descriptions ...........................................................................
System Control Legacy Register Descriptions ...............................................................
226
226
231
410
6
System Exception Module ................................................................................... 470
6.1
6.2
6.3
Functional Description ................................................................................................. 470
Register Map .............................................................................................................. 470
Register Descriptions .................................................................................................. 470
7
Hibernation Module .............................................................................................. 478
7.1
7.2
7.3
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.3.6
7.3.7
7.3.8
7.3.9
7.3.10
7.3.11
7.3.12
7.4
7.4.1
7.4.2
7.4.3
7.4.4
7.4.5
7.5
7.6
Block Diagram ............................................................................................................
Signal Description .......................................................................................................
Functional Description .................................................................................................
Register Access Timing ...............................................................................................
Hibernation Clock Source ............................................................................................
System Implementation ...............................................................................................
Battery Management ...................................................................................................
Real-Time Clock ..........................................................................................................
Battery-Backed Memory ..............................................................................................
Power Control Using HIB .............................................................................................
Power Control Using VDD3ON Mode ...........................................................................
Initiating Hibernate ......................................................................................................
Waking from Hibernate ................................................................................................
Arbitrary Power Removal .............................................................................................
Interrupts and Status ...................................................................................................
Initialization and Configuration .....................................................................................
Initialization .................................................................................................................
RTC Match Functionality (No Hibernation) ....................................................................
RTC Match/Wake-Up from Hibernation .........................................................................
External Wake-Up from Hibernation ..............................................................................
RTC or External Wake-Up from Hibernation ..................................................................
Register Map ..............................................................................................................
Register Descriptions ..................................................................................................
479
479
480
480
481
482
483
484
486
486
486
486
486
487
487
488
488
489
489
489
490
490
491
8
Internal Memory ................................................................................................... 509
8.1
8.2
8.2.1
8.2.2
8.2.3
8.2.4
8.3
8.4
8.5
8.6
Block Diagram ............................................................................................................ 509
Functional Description ................................................................................................. 510
SRAM ........................................................................................................................ 510
ROM .......................................................................................................................... 511
Flash Memory ............................................................................................................. 513
EEPROM .................................................................................................................... 519
Register Map .............................................................................................................. 525
Flash Memory Register Descriptions (Flash Control Offset) ............................................ 526
EEPROM Register Descriptions (EEPROM Offset) ........................................................ 544
Memory Register Descriptions (System Control Offset) .................................................. 561
9
Micro Direct Memory Access (μDMA) ................................................................ 570
9.1
9.2
9.2.1
Block Diagram ............................................................................................................ 571
Functional Description ................................................................................................. 571
Channel Assignments .................................................................................................. 572
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9.2.2
9.2.3
9.2.4
9.2.5
9.2.6
9.2.7
9.2.8
9.2.9
9.2.10
9.3
9.3.1
9.3.2
9.3.3
9.3.4
9.3.5
9.4
9.5
9.6
Priority ........................................................................................................................ 573
Arbitration Size ............................................................................................................ 573
Request Types ............................................................................................................ 573
Channel Configuration ................................................................................................. 574
Transfer Modes ........................................................................................................... 576
Transfer Size and Increment ........................................................................................ 584
Peripheral Interface ..................................................................................................... 584
Software Request ........................................................................................................ 584
Interrupts and Errors .................................................................................................... 585
Initialization and Configuration ..................................................................................... 585
Module Initialization ..................................................................................................... 585
Configuring a Memory-to-Memory Transfer ................................................................... 586
Configuring a Peripheral for Simple Transmit ................................................................ 587
Configuring a Peripheral for Ping-Pong Receive ............................................................ 589
Configuring Channel Assignments ................................................................................ 591
Register Map .............................................................................................................. 591
μDMA Channel Control Structure ................................................................................. 593
μDMA Register Descriptions ........................................................................................ 600
10
General-Purpose Input/Outputs (GPIOs) ........................................................... 634
10.1
10.2
10.2.1
10.2.2
10.2.3
10.2.4
10.2.5
10.2.6
10.3
10.4
10.5
Signal Description ....................................................................................................... 634
Functional Description ................................................................................................. 637
Data Control ............................................................................................................... 639
Interrupt Control .......................................................................................................... 640
Mode Control .............................................................................................................. 641
Commit Control ........................................................................................................... 642
Pad Control ................................................................................................................. 642
Identification ............................................................................................................... 642
Initialization and Configuration ..................................................................................... 642
Register Map .............................................................................................................. 644
Register Descriptions .................................................................................................. 647
11
General-Purpose Timers ...................................................................................... 693
11.1
11.2
11.3
11.3.1
11.3.2
11.3.3
11.3.4
11.3.5
11.3.6
11.3.7
11.4
11.4.1
11.4.2
11.4.3
11.4.4
11.4.5
11.5
Block Diagram ............................................................................................................ 694
Signal Description ....................................................................................................... 695
Functional Description ................................................................................................. 697
GPTM Reset Conditions .............................................................................................. 697
Timer Modes ............................................................................................................... 698
Wait-for-Trigger Mode .................................................................................................. 707
Synchronizing GP Timer Blocks ................................................................................... 708
DMA Operation ........................................................................................................... 709
Accessing Concatenated 16/32-Bit GPTM Register Values ............................................ 709
Accessing Concatenated 32/64-Bit Wide GPTM Register Values .................................... 709
Initialization and Configuration ..................................................................................... 711
One-Shot/Periodic Timer Mode .................................................................................... 711
Real-Time Clock (RTC) Mode ...................................................................................... 712
Input Edge-Count Mode ............................................................................................... 712
Input Edge Time Mode ................................................................................................. 713
PWM Mode ................................................................................................................. 713
Register Map .............................................................................................................. 714
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11.6
Register Descriptions .................................................................................................. 715
12
Watchdog Timers ................................................................................................. 763
12.1
12.2
12.2.1
12.3
12.4
12.5
Block Diagram ............................................................................................................
Functional Description .................................................................................................
Register Access Timing ...............................................................................................
Initialization and Configuration .....................................................................................
Register Map ..............................................................................................................
Register Descriptions ..................................................................................................
764
764
765
765
765
766
13
Analog-to-Digital Converter (ADC) ..................................................................... 788
13.1
13.2
13.3
13.3.1
13.3.2
13.3.3
13.3.4
13.3.5
13.3.6
13.3.7
13.4
13.4.1
13.4.2
13.5
13.6
Block Diagram ............................................................................................................ 789
Signal Description ....................................................................................................... 790
Functional Description ................................................................................................. 791
Sample Sequencers .................................................................................................... 791
Module Control ............................................................................................................ 792
Hardware Sample Averaging Circuit ............................................................................. 796
Analog-to-Digital Converter .......................................................................................... 797
Differential Sampling ................................................................................................... 799
Internal Temperature Sensor ........................................................................................ 801
Digital Comparator Unit ............................................................................................... 802
Initialization and Configuration ..................................................................................... 806
Module Initialization ..................................................................................................... 806
Sample Sequencer Configuration ................................................................................. 807
Register Map .............................................................................................................. 807
Register Descriptions .................................................................................................. 809
14
Universal Asynchronous Receivers/Transmitters (UARTs) ............................. 884
14.1
Block Diagram ............................................................................................................
14.2
Signal Description .......................................................................................................
14.3
Functional Description .................................................................................................
14.3.1 Transmit/Receive Logic ...............................................................................................
14.3.2 Baud-Rate Generation .................................................................................................
14.3.3 Data Transmission ......................................................................................................
14.3.4 Serial IR (SIR) .............................................................................................................
14.3.5 ISO 7816 Support .......................................................................................................
14.3.6 Modem Handshake Support .........................................................................................
14.3.7 9-Bit UART Mode ........................................................................................................
14.3.8 FIFO Operation ...........................................................................................................
14.3.9 Interrupts ....................................................................................................................
14.3.10 Loopback Operation ....................................................................................................
14.3.11 DMA Operation ...........................................................................................................
14.4
Initialization and Configuration .....................................................................................
14.5
Register Map ..............................................................................................................
14.6
Register Descriptions ..................................................................................................
885
885
886
887
887
888
888
889
890
891
892
892
893
893
894
895
897
15
Synchronous Serial Interface (SSI) .................................................................... 945
15.1
15.2
15.3
15.3.1
Block Diagram ............................................................................................................
Signal Description .......................................................................................................
Functional Description .................................................................................................
Bit Rate Generation .....................................................................................................
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946
947
948
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15.3.2
15.3.3
15.3.4
15.3.5
15.4
15.5
15.6
FIFO Operation ...........................................................................................................
Interrupts ....................................................................................................................
Frame Formats ...........................................................................................................
DMA Operation ...........................................................................................................
Initialization and Configuration .....................................................................................
Register Map ..............................................................................................................
Register Descriptions ..................................................................................................
948
948
949
957
958
960
961
16
Inter-Integrated Circuit (I2C) Interface ................................................................ 990
16.1
16.2
16.3
16.3.1
16.3.2
16.3.3
16.3.4
16.3.5
16.4
16.4.1
16.4.2
16.5
16.6
16.7
16.8
Block Diagram ............................................................................................................ 991
Signal Description ....................................................................................................... 991
Functional Description ................................................................................................. 992
I2C Bus Functional Overview ........................................................................................ 992
Available Speed Modes ............................................................................................... 997
Interrupts .................................................................................................................... 999
Loopback Operation .................................................................................................. 1000
Command Sequence Flow Charts .............................................................................. 1000
Initialization and Configuration .................................................................................... 1008
Configure the I2C Module to Transmit a Single Byte as a Master .................................. 1008
Configure the I2C Master to High Speed Mode ............................................................ 1009
Register Map ............................................................................................................ 1010
Register Descriptions (I2C Master) .............................................................................. 1011
Register Descriptions (I2C Slave) ............................................................................... 1028
Register Descriptions (I2C Status and Control) ............................................................ 1038
17
Controller Area Network (CAN) Module ........................................................... 1041
17.1
Block Diagram ........................................................................................................... 1042
17.2
Signal Description ..................................................................................................... 1042
17.3
Functional Description ............................................................................................... 1043
17.3.1 Initialization ............................................................................................................... 1044
17.3.2 Operation .................................................................................................................. 1044
17.3.3 Transmitting Message Objects ................................................................................... 1045
17.3.4 Configuring a Transmit Message Object ...................................................................... 1046
17.3.5 Updating a Transmit Message Object ......................................................................... 1047
17.3.6 Accepting Received Message Objects ........................................................................ 1047
17.3.7 Receiving a Data Frame ............................................................................................ 1048
17.3.8 Receiving a Remote Frame ........................................................................................ 1048
17.3.9 Receive/Transmit Priority ........................................................................................... 1049
17.3.10 Configuring a Receive Message Object ...................................................................... 1049
17.3.11 Handling of Received Message Objects ...................................................................... 1050
17.3.12 Handling of Interrupts ................................................................................................ 1052
17.3.13 Test Mode ................................................................................................................. 1053
17.3.14 Bit Timing Configuration Error Considerations ............................................................. 1055
17.3.15 Bit Time and Bit Rate ................................................................................................. 1055
17.3.16 Calculating the Bit Timing Parameters ........................................................................ 1057
17.4
Register Map ............................................................................................................ 1060
17.5
CAN Register Descriptions ......................................................................................... 1061
18
Universal Serial Bus (USB) Controller ............................................................. 1091
18.1
Block Diagram ........................................................................................................... 1092
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18.2
18.3
18.3.1
18.3.2
18.3.3
18.3.4
18.4
18.4.1
18.4.2
18.5
18.6
Signal Description ..................................................................................................... 1092
Functional Description ............................................................................................... 1093
Operation as a Device ............................................................................................... 1093
Operation as a Host ................................................................................................... 1099
OTG Mode ................................................................................................................ 1102
DMA Operation ......................................................................................................... 1104
Initialization and Configuration .................................................................................... 1105
Pin Configuration ....................................................................................................... 1105
Endpoint Configuration .............................................................................................. 1106
Register Map ............................................................................................................ 1106
Register Descriptions ................................................................................................. 1112
19
Analog Comparators .......................................................................................... 1207
19.1
19.2
19.3
19.3.1
19.4
19.5
19.6
Block Diagram ...........................................................................................................
Signal Description .....................................................................................................
Functional Description ...............................................................................................
Internal Reference Programming ................................................................................
Initialization and Configuration ....................................................................................
Register Map ............................................................................................................
Register Descriptions .................................................................................................
20
Pin Diagram ........................................................................................................ 1223
1208
1208
1209
1210
1212
1213
1213
21
Signal Tables ...................................................................................................... 1224
21.1
21.2
21.3
21.4
21.5
21.6
Signals by Pin Number ..............................................................................................
Signals by Signal Name .............................................................................................
Signals by Function, Except for GPIO .........................................................................
GPIO Pins and Alternate Functions ............................................................................
Possible Pin Assignments for Alternate Functions .......................................................
Connections for Unused Signals .................................................................................
1225
1233
1242
1249
1252
1255
22
Electrical Characteristics .................................................................................. 1256
22.1
22.2
22.3
22.4
22.5
22.6
22.6.1
22.6.2
22.6.3
22.6.4
22.6.5
22.7
22.8
22.9
22.9.1
22.9.2
22.9.3
22.9.4
22.9.5
Maximum Ratings ...................................................................................................... 1256
Operating Characteristics ........................................................................................... 1257
Recommended Operating Conditions ......................................................................... 1258
Load Conditions ........................................................................................................ 1260
JTAG and Boundary Scan .......................................................................................... 1261
Power and Brown-Out ............................................................................................... 1263
VDDA Levels ............................................................................................................ 1263
VDD Levels ............................................................................................................... 1264
VDDC Levels ............................................................................................................ 1265
VDD Glitches ............................................................................................................ 1266
VDD Droop Response ............................................................................................... 1266
Reset ........................................................................................................................ 1268
On-Chip Low Drop-Out (LDO) Regulator ..................................................................... 1271
Clocks ...................................................................................................................... 1272
PLL Specifications ..................................................................................................... 1272
PIOSC Specifications ................................................................................................ 1273
Low-Frequency Internal Oscillator (LFIOSC) Specifications .......................................... 1273
Hibernation Clock Source Specifications ..................................................................... 1273
Main Oscillator Specifications ..................................................................................... 1274
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22.9.6 System Clock Specification with ADC Operation .......................................................... 1278
22.9.7 System Clock Specification with USB Operation .......................................................... 1278
22.10 Sleep Modes ............................................................................................................. 1279
22.11 Hibernation Module ................................................................................................... 1281
22.12 Flash Memory and EEPROM ..................................................................................... 1282
22.13 Input/Output Pin Characteristics ................................................................................. 1283
22.13.1 GPIO Module Characteristics ..................................................................................... 1283
22.13.2 Types of I/O Pins and ESD Protection ......................................................................... 1283
22.14 Analog-to-Digital Converter (ADC) .............................................................................. 1287
22.15 Synchronous Serial Interface (SSI) ............................................................................. 1291
22.16 Inter-Integrated Circuit (I2C) Interface ......................................................................... 1294
22.17 Universal Serial Bus (USB) Controller ......................................................................... 1295
22.18 Analog Comparator ................................................................................................... 1296
22.19 Current Consumption ................................................................................................. 1298
A
Package Information .......................................................................................... 1301
A.1
A.2
A.3
A.4
Orderable Devices .....................................................................................................
Device Nomenclature ................................................................................................
Device Markings ........................................................................................................
Packaging Diagram ...................................................................................................
10
1301
1301
1302
1303
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Tiva™ TM4C1237H6PZ Microcontroller
List of Figures
Figure 1-1.
Figure 2-1.
Figure 2-2.
Figure 2-3.
Figure 2-4.
Figure 2-5.
Figure 2-6.
Figure 2-7.
Figure 3-1.
Figure 3-2.
Figure 4-1.
Figure 4-2.
Figure 4-3.
Figure 4-4.
Figure 4-5.
Figure 5-1.
Figure 5-2.
Figure 5-3.
Figure 5-4.
Figure 5-5.
Figure 5-6.
Figure 7-1.
Figure 7-2.
Figure 7-3.
Figure 7-4.
Figure 7-5.
Figure 7-6.
Figure 8-1.
Figure 8-2.
Figure 9-1.
Figure 9-2.
Figure 9-3.
Figure 9-4.
Figure 9-5.
Figure 9-6.
Figure 10-1.
Figure 10-2.
Figure 10-3.
Figure 10-4.
Figure 11-1.
Figure 11-2.
Figure 11-3.
Figure 11-4.
Figure 11-5.
Figure 11-6.
Tiva™ TM4C1237H6PZ Microcontroller High-Level Block Diagram .......................... 45
CPU Block Diagram ............................................................................................. 66
TPIU Block Diagram ............................................................................................ 67
Cortex-M4F Register Set ...................................................................................... 70
Bit-Band Mapping ................................................................................................ 94
Data Storage ....................................................................................................... 95
Vector Table ...................................................................................................... 102
Exception Stack Frame ...................................................................................... 105
SRD Use Example ............................................................................................. 123
FPU Register Bank ............................................................................................ 126
JTAG Module Block Diagram .............................................................................. 196
Test Access Port State Machine ......................................................................... 199
IDCODE Register Format ................................................................................... 205
BYPASS Register Format ................................................................................... 205
Boundary Scan Register Format ......................................................................... 206
Basic RST Configuration .................................................................................... 210
External Circuitry to Extend Power-On Reset ....................................................... 210
Reset Circuit Controlled by Switch ...................................................................... 211
Power Architecture ............................................................................................ 214
Main Clock Tree ................................................................................................ 217
Module Clock Selection ...................................................................................... 224
Hibernation Module Block Diagram ..................................................................... 479
Using a Crystal as the Hibernation Clock Source with a Single Battery Source ...... 481
Using a Dedicated Oscillator as the Hibernation Clock Source with VDD3ON
Mode ................................................................................................................ 482
Using a Regulator for Both VDD and VBAT ............................................................ 483
Counter Behavior with a TRIM Value of 0x8002 ................................................... 485
Counter Behavior with a TRIM Value of 0x7FFC .................................................. 485
Internal Memory Block Diagram .......................................................................... 509
EEPROM Block Diagram ................................................................................... 510
μDMA Block Diagram ......................................................................................... 571
Example of Ping-Pong μDMA Transaction ........................................................... 577
Memory Scatter-Gather, Setup and Configuration ................................................ 579
Memory Scatter-Gather, μDMA Copy Sequence .................................................. 580
Peripheral Scatter-Gather, Setup and Configuration ............................................. 582
Peripheral Scatter-Gather, μDMA Copy Sequence ............................................... 583
Digital I/O Pads ................................................................................................. 638
Analog/Digital I/O Pads ...................................................................................... 639
GPIODATA Write Example ................................................................................. 640
GPIODATA Read Example ................................................................................. 640
GPTM Module Block Diagram ............................................................................ 694
Reading the RTC Value ...................................................................................... 701
Input Edge-Count Mode Example, Counting Down ............................................... 703
16-Bit Input Edge-Time Mode Example ............................................................... 704
16-Bit PWM Mode Example ................................................................................ 706
CCP Output, GPTMTnMATCHR > GPTMTnILR ................................................... 706
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Table of Contents
Figure 11-7.
Figure 11-8.
Figure 11-9.
Figure 12-1.
Figure 13-1.
Figure 13-2.
Figure 13-3.
Figure 13-4.
Figure 13-5.
Figure 13-6.
Figure 13-7.
Figure 13-8.
Figure 13-9.
Figure 13-10.
Figure 13-11.
Figure 13-12.
Figure 13-13.
Figure 13-14.
Figure 14-1.
Figure 14-2.
Figure 14-3.
Figure 15-1.
Figure 15-2.
Figure 15-3.
Figure 15-4.
Figure 15-5.
Figure 15-6.
Figure 15-7.
Figure 15-8.
Figure 15-9.
Figure 15-10.
Figure 15-11.
Figure 15-12.
Figure 16-1.
Figure 16-2.
Figure 16-3.
Figure 16-4.
Figure 16-5.
Figure 16-6.
Figure 16-7.
Figure 16-8.
Figure 16-9.
Figure 16-10.
Figure 16-11.
Figure 16-12.
Figure 16-13.
Figure 16-14.
Figure 16-15.
CCP Output, GPTMTnMATCHR = GPTMTnILR ................................................... 707
CCP Output, GPTMTnILR > GPTMTnMATCHR ................................................... 707
Timer Daisy Chain ............................................................................................. 708
WDT Module Block Diagram .............................................................................. 764
Implementation of Two ADC Blocks .................................................................... 789
ADC Module Block Diagram ............................................................................... 790
ADC Sample Phases ......................................................................................... 794
Doubling the ADC Sample Rate .......................................................................... 794
Skewed Sampling .............................................................................................. 795
Sample Averaging Example ............................................................................... 796
ADC Input Equivalency ...................................................................................... 797
ADC Voltage Reference ..................................................................................... 798
ADC Conversion Result ..................................................................................... 799
Differential Voltage Representation ..................................................................... 801
Internal Temperature Sensor Characteristic ......................................................... 802
Low-Band Operation (CIC=0x0) .......................................................................... 804
Mid-Band Operation (CIC=0x1) .......................................................................... 805
High-Band Operation (CIC=0x3) ......................................................................... 806
UART Module Block Diagram ............................................................................. 885
UART Character Frame ..................................................................................... 887
IrDA Data Modulation ......................................................................................... 889
SSI Module Block Diagram ................................................................................. 946
TI Synchronous Serial Frame Format (Single Transfer) ........................................ 950
TI Synchronous Serial Frame Format (Continuous Transfer) ................................ 951
Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 .......................... 952
Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .................. 952
Freescale SPI Frame Format with SPO=0 and SPH=1 ......................................... 953
Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ............... 954
Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ........ 954
Freescale SPI Frame Format with SPO=1 and SPH=1 ......................................... 955
MICROWIRE Frame Format (Single Frame) ........................................................ 956
MICROWIRE Frame Format (Continuous Transfer) ............................................. 957
MICROWIRE Frame Format, SSInFss Input Setup and Hold Requirements .......... 957
I2C Block Diagram ............................................................................................. 991
I2C Bus Configuration ........................................................................................ 992
START and STOP Conditions ............................................................................. 993
Complete Data Transfer with a 7-Bit Address ....................................................... 993
R/S Bit in First Byte ............................................................................................ 994
Data Validity During Bit Transfer on the I2C Bus ................................................... 994
High-Speed Data Format ................................................................................... 999
Master Single TRANSMIT ................................................................................ 1001
Master Single RECEIVE ................................................................................... 1002
Master TRANSMIT of Multiple Data Bytes ......................................................... 1003
Master RECEIVE of Multiple Data Bytes ............................................................ 1004
Master RECEIVE with Repeated START after Master TRANSMIT ....................... 1005
Master TRANSMIT with Repeated START after Master RECEIVE ....................... 1006
Standard High Speed Mode Master Transmit ..................................................... 1007
Slave Command Sequence .............................................................................. 1008
12
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Tiva™ TM4C1237H6PZ Microcontroller
Figure 17-1.
Figure 17-2.
Figure 17-3.
Figure 17-4.
Figure 18-1.
Figure 19-1.
Figure 19-2.
Figure 19-3.
Figure 20-1.
Figure 22-1.
Figure 22-2.
Figure 22-3.
Figure 22-4.
Figure 22-5.
Figure 22-6.
Figure 22-7.
Figure 22-8.
Figure 22-9.
Figure 22-10.
Figure 22-11.
Figure 22-12.
Figure 22-13.
Figure 22-14.
Figure 22-15.
Figure 22-16.
Figure 22-17.
Figure 22-18.
Figure 22-19.
Figure 22-20.
Figure 22-21.
Figure 22-22.
Figure 22-23.
Figure 22-24.
Figure A-1.
Figure A-2.
CAN Controller Block Diagram .......................................................................... 1042
CAN Data/Remote Frame ................................................................................. 1043
Message Objects in a FIFO Buffer .................................................................... 1052
CAN Bit Time ................................................................................................... 1056
USB Module Block Diagram ............................................................................. 1092
Analog Comparator Module Block Diagram ....................................................... 1208
Structure of Comparator Unit ............................................................................ 1209
Comparator Internal Reference Structure .......................................................... 1210
100-Pin LQFP Package Pin Diagram ................................................................ 1223
Load Conditions ............................................................................................... 1260
JTAG Test Clock Input Timing ........................................................................... 1261
JTAG Test Access Port (TAP) Timing ................................................................ 1262
Power Assertions versus VDDA Levels ............................................................. 1264
Power and Brown-Out Assertions versus VDD Levels ........................................ 1265
POK assertion vs VDDC ................................................................................... 1266
POR-BOR0-BOR1 VDD Glitch Response .......................................................... 1266
POR-BOR0-BOR1 VDD Droop Response ......................................................... 1267
Digital Power-On Reset Timing ......................................................................... 1268
Brown-Out Reset Timing .................................................................................. 1269
External Reset Timing (RST) ............................................................................ 1269
Software Reset Timing ..................................................................................... 1269
Watchdog Reset Timing ................................................................................... 1269
MOSC Failure Reset Timing ............................................................................. 1270
Hibernation Module Timing ............................................................................... 1281
ESD Protection on Fail-Safe Pins ...................................................................... 1284
ESD Protection on Non-Fail-Safe Pins .............................................................. 1285
ADC External Reference Filtering ..................................................................... 1289
ADC Input Equivalency Diagram ....................................................................... 1290
SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing
Measurement .................................................................................................. 1292
SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............... 1292
Master Mode SSI Timing for SPI Frame Format (FRF=00), with SPH=1 .............. 1293
Slave Mode SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................ 1293
I2C Timing ....................................................................................................... 1294
Key to Part Numbers ........................................................................................ 1301
TM4C1237H6PZ 100-Pin LQFP Package Diagram ............................................ 1303
June 12, 2014
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Texas Instruments-Production Data
Table of Contents
List of Tables
Table 1.
Table 2.
Table 1-1.
Table 2-1.
Table 2-2.
Table 2-3.
Table 2-4.
Table 2-5.
Table 2-6.
Table 2-7.
Table 2-8.
Table 2-9.
Table 2-10.
Table 2-11.
Table 2-12.
Table 2-13.
Table 3-1.
Table 3-2.
Table 3-3.
Table 3-4.
Table 3-5.
Table 3-6.
Table 3-7.
Table 3-8.
Table 3-9.
Table 3-10.
Table 4-1.
Table 4-2.
Table 4-3.
Table 5-1.
Table 5-2.
Table 5-3.
Table 5-4.
Table 5-5.
Table 5-6.
Table 5-7.
Table 5-8.
Table 6-1.
Table 7-1.
Table 7-2.
Table 7-3.
Table 8-1.
Table 8-2.
Table 8-3.
Table 9-1.
Table 9-2.
Revision History .................................................................................................. 36
Documentation Conventions ................................................................................ 41
TM4C1237H6PZ Microcontroller Features ............................................................. 44
Summary of Processor Mode, Privilege Level, and Stack Use ................................ 69
Processor Register Map ....................................................................................... 70
PSR Register Combinations ................................................................................. 76
Memory Map ....................................................................................................... 87
Memory Access Behavior ..................................................................................... 90
SRAM Memory Bit-Banding Regions .................................................................... 92
Peripheral Memory Bit-Banding Regions ............................................................... 93
Exception Types .................................................................................................. 98
Interrupts ............................................................................................................ 99
Exception Return Behavior ................................................................................. 106
Faults ............................................................................................................... 107
Fault Status and Fault Address Registers ............................................................ 108
Cortex-M4F Instruction Summary ....................................................................... 110
Core Peripheral Register Regions ....................................................................... 117
Memory Attributes Summary .............................................................................. 121
TEX, S, C, and B Bit Field Encoding ................................................................... 123
Cache Policy for Memory Attribute Encoding ....................................................... 124
AP Bit Field Encoding ........................................................................................ 124
Memory Region Attributes for Tiva™ C Series Microcontrollers ............................. 125
QNaN and SNaN Handling ................................................................................. 128
Peripherals Register Map ................................................................................... 129
Interrupt Priority Levels ...................................................................................... 159
Example SIZE Field Values ................................................................................ 187
JTAG_SWD_SWO Signals (100LQFP) ................................................................ 196
JTAG Port Pins State after Power-On Reset or RST assertion .............................. 197
JTAG Instruction Register Commands ................................................................. 203
System Control & Clocks Signals (100LQFP) ...................................................... 207
Reset Sources ................................................................................................... 208
Clock Source Options ........................................................................................ 215
Possible System Clock Frequencies Using the SYSDIV Field ............................... 218
Examples of Possible System Clock Frequencies Using the SYSDIV2 Field .......... 218
Examples of Possible System Clock Frequencies with DIV400=1 ......................... 219
System Control Register Map ............................................................................. 226
RCC2 Fields that Override RCC Fields ............................................................... 255
System Exception Register Map ......................................................................... 470
Hibernate Signals (100LQFP) ............................................................................. 479
Hibernation Module Clock Operation ................................................................... 488
Hibernation Module Register Map ....................................................................... 490
Flash Memory Protection Policy Combinations .................................................... 514
User-Programmable Flash Memory Resident Registers ....................................... 518
Flash Register Map ............................................................................................ 525
μDMA Channel Assignments .............................................................................. 572
Request Type Support ....................................................................................... 574
14
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Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Table 9-3.
Table 9-4.
Table 9-5.
Table 9-6.
Table 9-7.
Table 9-8.
Table 9-9.
Table 9-10.
Table 9-11.
Table 9-12.
Control Structure Memory Map ........................................................................... 575
Channel Control Structure .................................................................................. 575
μDMA Read Example: 8-Bit Peripheral ................................................................ 584
μDMA Interrupt Assignments .............................................................................. 585
Channel Control Structure Offsets for Channel 30 ................................................ 586
Channel Control Word Configuration for Memory Transfer Example ...................... 587
Channel Control Structure Offsets for Channel 7 .................................................. 588
Channel Control Word Configuration for Peripheral Transmit Example .................. 588
Primary and Alternate Channel Control Structure Offsets for Channel 8 ................. 589
Channel Control Word Configuration for Peripheral Ping-Pong Receive
Example ............................................................................................................ 590
Table 9-13.
μDMA Register Map .......................................................................................... 592
Table 10-1.
GPIO Pins With Special Considerations .............................................................. 635
Table 10-2.
GPIO Pins and Alternate Functions (100LQFP) ................................................... 635
Table 10-3.
GPIO Pad Configuration Examples ..................................................................... 643
Table 10-4.
GPIO Interrupt Configuration Example ................................................................ 644
Table 10-5.
GPIO Pins With Special Considerations .............................................................. 645
Table 10-6.
GPIO Register Map ........................................................................................... 646
Table 10-7.
GPIO Pins With Special Considerations .............................................................. 659
Table 10-8.
GPIO Pins With Special Considerations .............................................................. 665
Table 10-9.
GPIO Pins With Special Considerations .............................................................. 667
Table 10-10. GPIO Pins With Special Considerations .............................................................. 670
Table 10-11. GPIO Pins With Special Considerations .............................................................. 677
Table 11-1.
Available CCP Pins ............................................................................................ 695
Table 11-2.
General-Purpose Timers Signals (100LQFP) ....................................................... 695
Table 11-3.
General-Purpose Timer Capabilities .................................................................... 697
Table 11-4.
Counter Values When the Timer is Enabled in Periodic or One-Shot Modes .......... 698
Table 11-5.
16-Bit Timer With Prescaler Configurations ......................................................... 700
Table 11-6.
32-Bit Timer (configured in 32/64-bit mode) With Prescaler Configurations ............ 700
Table 11-7.
Counter Values When the Timer is Enabled in RTC Mode .................................... 700
Table 11-8.
Counter Values When the Timer is Enabled in Input Edge-Count Mode ................. 702
Table 11-9.
Counter Values When the Timer is Enabled in Input Event-Count Mode ................ 703
Table 11-10. Counter Values When the Timer is Enabled in PWM Mode ................................... 705
Table 11-11. Timeout Actions for GPTM Modes ...................................................................... 708
Table 11-12. Timers Register Map .......................................................................................... 715
Table 12-1.
Watchdog Timers Register Map .......................................................................... 766
Table 13-1.
ADC Signals (100LQFP) .................................................................................... 790
Table 13-2.
Samples and FIFO Depth of Sequencers ............................................................ 792
Table 13-3.
Differential Sampling Pairs ................................................................................. 799
Table 13-4.
ADC Register Map ............................................................................................. 807
Table 14-1.
UART Signals (100LQFP) .................................................................................. 886
Table 14-2.
Flow Control Mode ............................................................................................. 891
Table 14-3.
UART Register Map ........................................................................................... 896
Table 15-1.
SSI Signals (100LQFP) ...................................................................................... 947
Table 15-2.
SSI Register Map .............................................................................................. 960
Table 16-1.
I2C Signals (100LQFP) ...................................................................................... 991
Table 16-2.
Examples of I2C Master Timer Period Versus Speed Mode ................................... 997
Table 16-3.
Examples of I2C Master Timer Period in High-Speed Mode .................................. 998
June 12, 2014
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Table of Contents
Table 16-4.
Table 16-5.
Table 17-1.
Table 17-2.
Table 17-3.
Table 17-4.
Table 17-5.
Table 18-1.
Table 18-2.
Table 18-3.
Table 18-4.
Table 18-5.
Table 19-1.
Table 19-2.
Table 19-3.
Table 19-4.
Table 19-5.
Table 21-1.
Table 21-2.
Table 21-3.
Table 21-4.
Table 21-5.
Table 21-6.
Table 21-7.
Table 22-1.
Table 22-2.
Table 22-3.
Table 22-4.
Table 22-5.
Table 22-6.
Table 22-7.
Table 22-8.
Table 22-9.
Table 22-10.
Table 22-11.
Table 22-12.
Table 22-13.
Table 22-14.
Table 22-15.
Table 22-16.
Table 22-17.
Table 22-18.
Table 22-19.
Table 22-20.
Table 22-21.
Table 22-22.
Inter-Integrated Circuit (I2C) Interface Register Map ........................................... 1010
Write Field Decoding for I2CMCS[3:0] Field ....................................................... 1016
Controller Area Network Signals (100LQFP) ...................................................... 1043
Message Object Configurations ........................................................................ 1048
CAN Protocol Ranges ...................................................................................... 1056
CANBIT Register Values .................................................................................. 1056
CAN Register Map ........................................................................................... 1060
USB Signals (100LQFP) ................................................................................... 1093
Remainder (MAXLOAD/4) ................................................................................ 1104
Actual Bytes Read ........................................................................................... 1104
Packet Sizes That Clear RXRDY ...................................................................... 1105
Universal Serial Bus (USB) Controller Register Map ........................................... 1106
Analog Comparators Signals (100LQFP) ........................................................... 1208
Internal Reference Voltage and ACREFCTL Field Values ................................... 1210
Analog Comparator Voltage Reference Characteristics, VDDA = 3.3V, EN= 1, and
RNG = 0 .......................................................................................................... 1211
Analog Comparator Voltage Reference Characteristics, VDDA = 3.3V, EN= 1, and
RNG = 1 .......................................................................................................... 1212
Analog Comparators Register Map ................................................................... 1213
GPIO Pins With Special Considerations ............................................................ 1224
Signals by Pin Number ..................................................................................... 1225
Signals by Signal Name ................................................................................... 1233
Signals by Function, Except for GPIO ............................................................... 1242
GPIO Pins and Alternate Functions ................................................................... 1249
Possible Pin Assignments for Alternate Functions .............................................. 1252
Connections for Unused Signals (100-Pin LQFP) .............................................. 1255
Absolute Maximum Ratings .............................................................................. 1256
ESD Absolute Maximum Ratings ...................................................................... 1256
Temperature Characteristics ............................................................................. 1257
Thermal Characteristics ................................................................................... 1257
Recommended DC Operating Conditions .......................................................... 1258
Recommended GPIO Pad Operating Conditions ................................................ 1258
GPIO Current Restrictions ................................................................................ 1258
GPIO Package Side Assignments ..................................................................... 1259
JTAG Characteristics ....................................................................................... 1261
Power-On and Brown-Out Levels ...................................................................... 1263
Reset Characteristics ....................................................................................... 1268
LDO Regulator Characteristics ......................................................................... 1271
Phase Locked Loop (PLL) Characteristics ......................................................... 1272
Actual PLL Frequency ...................................................................................... 1272
PIOSC Clock Characteristics ............................................................................ 1273
Low-Frequency internal Oscillator Characteristics .............................................. 1273
Hibernation Oscillator Input Characteristics ........................................................ 1273
Main Oscillator Input Characteristics ................................................................. 1274
Crystal Parameters .......................................................................................... 1276
Supported MOSC Crystal Frequencies .............................................................. 1277
System Clock Characteristics with ADC Operation ............................................. 1278
System Clock Characteristics with USB Operation ............................................. 1278
16
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Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Table 22-23.
Table 22-24.
Table 22-25.
Table 22-26.
Table 22-27.
Table 22-28.
Table 22-29.
Table 22-30.
Table 22-31.
Table 22-32.
Table 22-33.
Table 22-34.
Table 22-35.
Table 22-36.
Table 22-37.
Table 22-38.
Sleep Modes AC Characteristics ....................................................................... 1279
Time to Wake with Respect to Low-Power Modes .............................................. 1279
Hibernation Module Battery Characteristics ....................................................... 1281
Hibernation Module AC Characteristics ............................................................. 1281
Flash Memory Characteristics ........................................................................... 1282
EEPROM Characteristics ................................................................................. 1282
GPIO Module Characteristics ............................................................................ 1283
Pad Voltage/Current Characteristics for Fail-Safe Pins ....................................... 1284
Fail-Safe GPIOs that Require an External Pull-up .............................................. 1285
Non-Fail-Safe I/O Pad Voltage/Current Characteristics ....................................... 1285
ADC Electrical Characteristics .......................................................................... 1287
SSI Characteristics .......................................................................................... 1291
I2C Characteristics ........................................................................................... 1294
Analog Comparator Characteristics ................................................................... 1296
Analog Comparator Voltage Reference Characteristics ...................................... 1296
Analog Comparator Voltage Reference Characteristics, VDDA = 3.3V, EN= 1, and
RNG = 0 .......................................................................................................... 1296
Table 22-39. Analog Comparator Voltage Reference Characteristics, VDDA = 3.3V, EN= 1, and
RNG = 1 .......................................................................................................... 1297
Table 22-40. Current Consumption ....................................................................................... 1298
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Table of Contents
List of Registers
The Cortex-M4F Processor ........................................................................................................... 64
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Cortex General-Purpose Register 0 (R0) ........................................................................... 72
Cortex General-Purpose Register 1 (R1) ........................................................................... 72
Cortex General-Purpose Register 2 (R2) ........................................................................... 72
Cortex General-Purpose Register 3 (R3) ........................................................................... 72
Cortex General-Purpose Register 4 (R4) ........................................................................... 72
Cortex General-Purpose Register 5 (R5) ........................................................................... 72
Cortex General-Purpose Register 6 (R6) ........................................................................... 72
Cortex General-Purpose Register 7 (R7) ........................................................................... 72
Cortex General-Purpose Register 8 (R8) ........................................................................... 72
Cortex General-Purpose Register 9 (R9) ........................................................................... 72
Cortex General-Purpose Register 10 (R10) ....................................................................... 72
Cortex General-Purpose Register 11 (R11) ........................................................................ 72
Cortex General-Purpose Register 12 (R12) ....................................................................... 72
Stack Pointer (SP) ........................................................................................................... 73
Link Register (LR) ............................................................................................................ 74
Program Counter (PC) ..................................................................................................... 75
Program Status Register (PSR) ........................................................................................ 76
Priority Mask Register (PRIMASK) .................................................................................... 80
Fault Mask Register (FAULTMASK) .................................................................................. 81
Base Priority Mask Register (BASEPRI) ............................................................................ 82
Control Register (CONTROL) ........................................................................................... 83
Floating-Point Status Control (FPSC) ................................................................................ 85
Cortex-M4 Peripherals ................................................................................................................. 117
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
SysTick Control and Status Register (STCTRL), offset 0x010 ........................................... 133
SysTick Reload Value Register (STRELOAD), offset 0x014 .............................................. 135
SysTick Current Value Register (STCURRENT), offset 0x018 ........................................... 136
Interrupt 0-31 Set Enable (EN0), offset 0x100 .................................................................. 137
Interrupt 32-63 Set Enable (EN1), offset 0x104 ................................................................ 137
Interrupt 64-95 Set Enable (EN2), offset 0x108 ................................................................ 137
Interrupt 96-127 Set Enable (EN3), offset 0x10C ............................................................. 137
Interrupt 128-138 Set Enable (EN4), offset 0x110 ............................................................ 138
Interrupt 0-31 Clear Enable (DIS0), offset 0x180 .............................................................. 139
Interrupt 32-63 Clear Enable (DIS1), offset 0x184 ............................................................ 139
Interrupt 64-95 Clear Enable (DIS2), offset 0x188 ............................................................ 139
Interrupt 96-127 Clear Enable (DIS3), offset 0x18C .......................................................... 139
Interrupt 128-138 Clear Enable (DIS4), offset 0x190 ........................................................ 140
Interrupt 0-31 Set Pending (PEND0), offset 0x200 ........................................................... 141
Interrupt 32-63 Set Pending (PEND1), offset 0x204 ......................................................... 141
Interrupt 64-95 Set Pending (PEND2), offset 0x208 ......................................................... 141
Interrupt 96-127 Set Pending (PEND3), offset 0x20C ....................................................... 141
Interrupt 128-138 Set Pending (PEND4), offset 0x210 ...................................................... 142
Interrupt 0-31 Clear Pending (UNPEND0), offset 0x280 ................................................... 143
Interrupt 32-63 Clear Pending (UNPEND1), offset 0x284 .................................................. 143
Interrupt 64-95 Clear Pending (UNPEND2), offset 0x288 .................................................. 143
18
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Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
Register 29:
Register 30:
Register 31:
Register 32:
Register 33:
Register 34:
Register 35:
Register 36:
Register 37:
Register 38:
Register 39:
Register 40:
Register 41:
Register 42:
Register 43:
Register 44:
Register 45:
Register 46:
Register 47:
Register 48:
Register 49:
Register 50:
Register 51:
Register 52:
Register 53:
Register 54:
Register 55:
Register 56:
Register 57:
Register 58:
Register 59:
Register 60:
Register 61:
Register 62:
Register 63:
Register 64:
Register 65:
Register 66:
Register 67:
Register 68:
Register 69:
Interrupt 96-127 Clear Pending (UNPEND3), offset 0x28C ............................................... 143
Interrupt 128-138 Clear Pending (UNPEND4), offset 0x290 .............................................. 144
Interrupt 0-31 Active Bit (ACTIVE0), offset 0x300 ............................................................. 145
Interrupt 32-63 Active Bit (ACTIVE1), offset 0x304 ........................................................... 145
Interrupt 64-95 Active Bit (ACTIVE2), offset 0x308 ........................................................... 145
Interrupt 96-127 Active Bit (ACTIVE3), offset 0x30C ........................................................ 145
Interrupt 128-138 Active Bit (ACTIVE4), offset 0x310 ....................................................... 146
Interrupt 0-3 Priority (PRI0), offset 0x400 ......................................................................... 147
Interrupt 4-7 Priority (PRI1), offset 0x404 ......................................................................... 147
Interrupt 8-11 Priority (PRI2), offset 0x408 ....................................................................... 147
Interrupt 12-15 Priority (PRI3), offset 0x40C .................................................................... 147
Interrupt 16-19 Priority (PRI4), offset 0x410 ..................................................................... 147
Interrupt 20-23 Priority (PRI5), offset 0x414 ..................................................................... 147
Interrupt 24-27 Priority (PRI6), offset 0x418 ..................................................................... 147
Interrupt 28-31 Priority (PRI7), offset 0x41C .................................................................... 147
Interrupt 32-35 Priority (PRI8), offset 0x420 ..................................................................... 147
Interrupt 36-39 Priority (PRI9), offset 0x424 ..................................................................... 147
Interrupt 40-43 Priority (PRI10), offset 0x428 ................................................................... 147
Interrupt 44-47 Priority (PRI11), offset 0x42C ................................................................... 147
Interrupt 48-51 Priority (PRI12), offset 0x430 ................................................................... 147
Interrupt 52-55 Priority (PRI13), offset 0x434 ................................................................... 147
Interrupt 56-59 Priority (PRI14), offset 0x438 ................................................................... 147
Interrupt 60-63 Priority (PRI15), offset 0x43C .................................................................. 147
Interrupt 64-67 Priority (PRI16), offset 0x440 ................................................................... 149
Interrupt 68-71 Priority (PRI17), offset 0x444 ................................................................... 149
Interrupt 72-75 Priority (PRI18), offset 0x448 ................................................................... 149
Interrupt 76-79 Priority (PRI19), offset 0x44C .................................................................. 149
Interrupt 80-83 Priority (PRI20), offset 0x450 ................................................................... 149
Interrupt 84-87 Priority (PRI21), offset 0x454 ................................................................... 149
Interrupt 88-91 Priority (PRI22), offset 0x458 ................................................................... 149
Interrupt 92-95 Priority (PRI23), offset 0x45C .................................................................. 149
Interrupt 96-99 Priority (PRI24), offset 0x460 ................................................................... 149
Interrupt 100-103 Priority (PRI25), offset 0x464 ............................................................... 149
Interrupt 104-107 Priority (PRI26), offset 0x468 ............................................................... 149
Interrupt 108-111 Priority (PRI27), offset 0x46C ............................................................... 149
Interrupt 112-115 Priority (PRI28), offset 0x470 ................................................................ 149
Interrupt 116-119 Priority (PRI29), offset 0x474 ................................................................ 149
Interrupt 120-123 Priority (PRI30), offset 0x478 ............................................................... 149
Interrupt 124-127 Priority (PRI31), offset 0x47C ............................................................... 149
Interrupt 128-131 Priority (PRI32), offset 0x480 ............................................................... 149
Interrupt 132-135 Priority (PRI33), offset 0x484 ............................................................... 149
Interrupt 136-138 Priority (PRI34), offset 0x488 ............................................................... 149
Software Trigger Interrupt (SWTRIG), offset 0xF00 .......................................................... 151
Auxiliary Control (ACTLR), offset 0x008 .......................................................................... 152
CPU ID Base (CPUID), offset 0xD00 ............................................................................... 154
Interrupt Control and State (INTCTRL), offset 0xD04 ........................................................ 155
Vector Table Offset (VTABLE), offset 0xD08 .................................................................... 158
Application Interrupt and Reset Control (APINT), offset 0xD0C ......................................... 159
June 12, 2014
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Table of Contents
Register 70:
Register 71:
Register 72:
Register 73:
Register 74:
Register 75:
Register 76:
Register 77:
Register 78:
Register 79:
Register 80:
Register 81:
Register 82:
Register 83:
Register 84:
Register 85:
Register 86:
Register 87:
Register 88:
Register 89:
Register 90:
Register 91:
Register 92:
Register 93:
Register 94:
System Control (SYSCTRL), offset 0xD10 ....................................................................... 161
Configuration and Control (CFGCTRL), offset 0xD14 ....................................................... 163
System Handler Priority 1 (SYSPRI1), offset 0xD18 ......................................................... 165
System Handler Priority 2 (SYSPRI2), offset 0xD1C ........................................................ 166
System Handler Priority 3 (SYSPRI3), offset 0xD20 ......................................................... 167
System Handler Control and State (SYSHNDCTRL), offset 0xD24 .................................... 168
Configurable Fault Status (FAULTSTAT), offset 0xD28 ..................................................... 172
Hard Fault Status (HFAULTSTAT), offset 0xD2C .............................................................. 178
Memory Management Fault Address (MMADDR), offset 0xD34 ........................................ 179
Bus Fault Address (FAULTADDR), offset 0xD38 .............................................................. 180
MPU Type (MPUTYPE), offset 0xD90 ............................................................................. 181
MPU Control (MPUCTRL), offset 0xD94 .......................................................................... 182
MPU Region Number (MPUNUMBER), offset 0xD98 ....................................................... 184
MPU Region Base Address (MPUBASE), offset 0xD9C ................................................... 185
MPU Region Base Address Alias 1 (MPUBASE1), offset 0xDA4 ....................................... 185
MPU Region Base Address Alias 2 (MPUBASE2), offset 0xDAC ...................................... 185
MPU Region Base Address Alias 3 (MPUBASE3), offset 0xDB4 ....................................... 185
MPU Region Attribute and Size (MPUATTR), offset 0xDA0 ............................................... 187
MPU Region Attribute and Size Alias 1 (MPUATTR1), offset 0xDA8 .................................. 187
MPU Region Attribute and Size Alias 2 (MPUATTR2), offset 0xDB0 .................................. 187
MPU Region Attribute and Size Alias 3 (MPUATTR3), offset 0xDB8 .................................. 187
Coprocessor Access Control (CPAC), offset 0xD88 .......................................................... 190
Floating-Point Context Control (FPCC), offset 0xF34 ........................................................ 191
Floating-Point Context Address (FPCA), offset 0xF38 ...................................................... 193
Floating-Point Default Status Control (FPDSC), offset 0xF3C ........................................... 194
System Control ............................................................................................................................ 207
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Device Identification 0 (DID0), offset 0x000 ..................................................................... 232
Device Identification 1 (DID1), offset 0x004 ..................................................................... 234
Brown-Out Reset Control (PBORCTL), offset 0x030 ........................................................ 237
Raw Interrupt Status (RIS), offset 0x050 .......................................................................... 238
Interrupt Mask Control (IMC), offset 0x054 ...................................................................... 241
Masked Interrupt Status and Clear (MISC), offset 0x058 .................................................. 243
Reset Cause (RESC), offset 0x05C ................................................................................ 246
Run-Mode Clock Configuration (RCC), offset 0x060 ......................................................... 248
GPIO High-Performance Bus Control (GPIOHBCTL), offset 0x06C ................................... 252
Run-Mode Clock Configuration 2 (RCC2), offset 0x070 .................................................... 255
Main Oscillator Control (MOSCCTL), offset 0x07C ........................................................... 258
Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 ........................................ 259
System Properties (SYSPROP), offset 0x14C .................................................................. 261
Precision Internal Oscillator Calibration (PIOSCCAL), offset 0x150 ................................... 263
Precision Internal Oscillator Statistics (PIOSCSTAT), offset 0x154 .................................... 265
PLL Frequency 0 (PLLFREQ0), offset 0x160 ................................................................... 266
PLL Frequency 1 (PLLFREQ1), offset 0x164 ................................................................... 267
PLL Status (PLLSTAT), offset 0x168 ............................................................................... 268
Sleep Power Configuration (SLPPWRCFG), offset 0x188 ................................................. 269
Deep-Sleep Power Configuration (DSLPPWRCFG), offset 0x18C ..................................... 271
LDO Sleep Power Control (LDOSPCTL), offset 0x1B4 ..................................................... 273
LDO Sleep Power Calibration (LDOSPCAL), offset 0x1B8 ................................................ 275
20
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Tiva™ TM4C1237H6PZ Microcontroller
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
Register 29:
Register 30:
Register 31:
Register 32:
Register 33:
Register 34:
Register 35:
Register 36:
Register 37:
Register 38:
Register 39:
Register 40:
Register 41:
Register 42:
Register 43:
Register 44:
Register 45:
Register 46:
Register 47:
Register 48:
Register 49:
Register 50:
Register 51:
Register 52:
Register 53:
Register 54:
Register 55:
Register 56:
Register 57:
Register 58:
Register 59:
Register 60:
Register 61:
Register 62:
Register 63:
Register 64:
Register 65:
LDO Deep-Sleep Power Control (LDODPCTL), offset 0x1BC ........................................... 276
LDO Deep-Sleep Power Calibration (LDODPCAL), offset 0x1C0 ...................................... 278
Sleep / Deep-Sleep Power Mode Status (SDPMST), offset 0x1CC .................................... 279
Watchdog Timer Peripheral Present (PPWD), offset 0x300 ............................................... 282
16/32-Bit General-Purpose Timer Peripheral Present (PPTIMER), offset 0x304 ................. 283
General-Purpose Input/Output Peripheral Present (PPGPIO), offset 0x308 ........................ 285
Micro Direct Memory Access Peripheral Present (PPDMA), offset 0x30C .......................... 288
Hibernation Peripheral Present (PPHIB), offset 0x314 ...................................................... 289
Universal Asynchronous Receiver/Transmitter Peripheral Present (PPUART), offset
0x318 ........................................................................................................................... 290
Synchronous Serial Interface Peripheral Present (PPSSI), offset 0x31C ............................ 292
Inter-Integrated Circuit Peripheral Present (PPI2C), offset 0x320 ...................................... 294
Universal Serial Bus Peripheral Present (PPUSB), offset 0x328 ........................................ 296
Controller Area Network Peripheral Present (PPCAN), offset 0x334 .................................. 297
Analog-to-Digital Converter Peripheral Present (PPADC), offset 0x338 ............................. 298
Analog Comparator Peripheral Present (PPACMP), offset 0x33C ...................................... 299
Pulse Width Modulator Peripheral Present (PPPWM), offset 0x340 ................................... 300
Quadrature Encoder Interface Peripheral Present (PPQEI), offset 0x344 ........................... 301
EEPROM Peripheral Present (PPEEPROM), offset 0x358 ................................................ 302
32/64-Bit Wide General-Purpose Timer Peripheral Present (PPWTIMER), offset 0x35C ..... 303
Watchdog Timer Software Reset (SRWD), offset 0x500 ................................................... 305
16/32-Bit General-Purpose Timer Software Reset (SRTIMER), offset 0x504 ...................... 307
General-Purpose Input/Output Software Reset (SRGPIO), offset 0x508 ............................ 309
Micro Direct Memory Access Software Reset (SRDMA), offset 0x50C ............................... 312
Hibernation Software Reset (SRHIB), offset 0x514 ........................................................... 313
Universal Asynchronous Receiver/Transmitter Software Reset (SRUART), offset 0x518 .... 314
Synchronous Serial Interface Software Reset (SRSSI), offset 0x51C ................................ 316
Inter-Integrated Circuit Software Reset (SRI2C), offset 0x520 ........................................... 318
Universal Serial Bus Software Reset (SRUSB), offset 0x528 ............................................ 320
Controller Area Network Software Reset (SRCAN), offset 0x534 ....................................... 321
Analog-to-Digital Converter Software Reset (SRADC), offset 0x538 .................................. 322
Analog Comparator Software Reset (SRACMP), offset 0x53C .......................................... 324
EEPROM Software Reset (SREEPROM), offset 0x558 .................................................... 325
32/64-Bit Wide General-Purpose Timer Software Reset (SRWTIMER), offset 0x55C .......... 326
Watchdog Timer Run Mode Clock Gating Control (RCGCWD), offset 0x600 ...................... 328
16/32-Bit General-Purpose Timer Run Mode Clock Gating Control (RCGCTIMER), offset
0x604 ........................................................................................................................... 329
General-Purpose Input/Output Run Mode Clock Gating Control (RCGCGPIO), offset
0x608 ........................................................................................................................... 331
Micro Direct Memory Access Run Mode Clock Gating Control (RCGCDMA), offset
0x60C ........................................................................................................................... 334
Hibernation Run Mode Clock Gating Control (RCGCHIB), offset 0x614 ............................. 335
Universal Asynchronous Receiver/Transmitter Run Mode Clock Gating Control (RCGCUART),
offset 0x618 .................................................................................................................. 336
Synchronous Serial Interface Run Mode Clock Gating Control (RCGCSSI), offset
0x61C ........................................................................................................................... 338
Inter-Integrated Circuit Run Mode Clock Gating Control (RCGCI2C), offset 0x620 ............. 340
Universal Serial Bus Run Mode Clock Gating Control (RCGCUSB), offset 0x628 ............... 342
Controller Area Network Run Mode Clock Gating Control (RCGCCAN), offset 0x634 ......... 343
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Register 66:
Register 67:
Register 68:
Register 69:
Register 70:
Register 71:
Register 72:
Register 73:
Register 74:
Register 75:
Register 76:
Register 77:
Register 78:
Register 79:
Register 80:
Register 81:
Register 82:
Register 83:
Register 84:
Register 85:
Register 86:
Register 87:
Register 88:
Register 89:
Register 90:
Register 91:
Register 92:
Register 93:
Register 94:
Register 95:
Register 96:
Analog-to-Digital Converter Run Mode Clock Gating Control (RCGCADC), offset 0x638 .... 344
Analog Comparator Run Mode Clock Gating Control (RCGCACMP), offset 0x63C ............. 345
EEPROM Run Mode Clock Gating Control (RCGCEEPROM), offset 0x658 ....................... 346
32/64-Bit Wide General-Purpose Timer Run Mode Clock Gating Control (RCGCWTIMER),
offset 0x65C .................................................................................................................. 347
Watchdog Timer Sleep Mode Clock Gating Control (SCGCWD), offset 0x700 .................... 349
16/32-Bit General-Purpose Timer Sleep Mode Clock Gating Control (SCGCTIMER), offset
0x704 ........................................................................................................................... 350
General-Purpose Input/Output Sleep Mode Clock Gating Control (SCGCGPIO), offset
0x708 ........................................................................................................................... 352
Micro Direct Memory Access Sleep Mode Clock Gating Control (SCGCDMA), offset
0x70C ........................................................................................................................... 355
Hibernation Sleep Mode Clock Gating Control (SCGCHIB), offset 0x714 ........................... 356
Universal Asynchronous Receiver/Transmitter Sleep Mode Clock Gating Control
(SCGCUART), offset 0x718 ............................................................................................ 357
Synchronous Serial Interface Sleep Mode Clock Gating Control (SCGCSSI), offset
0x71C ........................................................................................................................... 359
Inter-Integrated Circuit Sleep Mode Clock Gating Control (SCGCI2C), offset 0x720 ........... 361
Universal Serial Bus Sleep Mode Clock Gating Control (SCGCUSB), offset 0x728 ............. 363
Controller Area Network Sleep Mode Clock Gating Control (SCGCCAN), offset 0x734 ....... 364
Analog-to-Digital Converter Sleep Mode Clock Gating Control (SCGCADC), offset
0x738 ........................................................................................................................... 365
Analog Comparator Sleep Mode Clock Gating Control (SCGCACMP), offset 0x73C .......... 366
EEPROM Sleep Mode Clock Gating Control (SCGCEEPROM), offset 0x758 ..................... 367
32/64-Bit Wide General-Purpose Timer Sleep Mode Clock Gating Control (SCGCWTIMER),
offset 0x75C .................................................................................................................. 368
Watchdog Timer Deep-Sleep Mode Clock Gating Control (DCGCWD), offset 0x800 .......... 370
16/32-Bit General-Purpose Timer Deep-Sleep Mode Clock Gating Control (DCGCTIMER),
offset 0x804 .................................................................................................................. 371
General-Purpose Input/Output Deep-Sleep Mode Clock Gating Control (DCGCGPIO), offset
0x808 ........................................................................................................................... 373
Micro Direct Memory Access Deep-Sleep Mode Clock Gating Control (DCGCDMA), offset
0x80C ........................................................................................................................... 376
Hibernation Deep-Sleep Mode Clock Gating Control (DCGCHIB), offset 0x814 .................. 377
Universal Asynchronous Receiver/Transmitter Deep-Sleep Mode Clock Gating Control
(DCGCUART), offset 0x818 ............................................................................................ 378
Synchronous Serial Interface Deep-Sleep Mode Clock Gating Control (DCGCSSI), offset
0x81C ........................................................................................................................... 380
Inter-Integrated Circuit Deep-Sleep Mode Clock Gating Control (DCGCI2C), offset
0x820 ........................................................................................................................... 382
Universal Serial Bus Deep-Sleep Mode Clock Gating Control (DCGCUSB), offset
0x828 ........................................................................................................................... 384
Controller Area Network Deep-Sleep Mode Clock Gating Control (DCGCCAN), offset
0x834 ........................................................................................................................... 385
Analog-to-Digital Converter Deep-Sleep Mode Clock Gating Control (DCGCADC), offset
0x838 ........................................................................................................................... 386
Analog Comparator Deep-Sleep Mode Clock Gating Control (DCGCACMP), offset
0x83C ........................................................................................................................... 387
EEPROM Deep-Sleep Mode Clock Gating Control (DCGCEEPROM), offset 0x858 ........... 388
22
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Tiva™ TM4C1237H6PZ Microcontroller
Register 97:
Register 98:
Register 99:
Register 100:
Register 101:
Register 102:
Register 103:
Register 104:
Register 105:
Register 106:
Register 107:
Register 108:
Register 109:
Register 110:
Register 111:
Register 112:
Register 113:
Register 114:
Register 115:
Register 116:
Register 117:
Register 118:
Register 119:
Register 120:
Register 121:
Register 122:
Register 123:
Register 124:
Register 125:
Register 126:
Register 127:
Register 128:
Register 129:
Register 130:
Register 131:
Register 132:
Register 133:
Register 134:
32/64-Bit Wide General-Purpose Timer Deep-Sleep Mode Clock Gating Control
(DCGCWTIMER), offset 0x85C ...................................................................................... 389
Watchdog Timer Peripheral Ready (PRWD), offset 0xA00 ................................................ 391
16/32-Bit General-Purpose Timer Peripheral Ready (PRTIMER), offset 0xA04 ................... 392
General-Purpose Input/Output Peripheral Ready (PRGPIO), offset 0xA08 ......................... 394
Micro Direct Memory Access Peripheral Ready (PRDMA), offset 0xA0C ........................... 396
Hibernation Peripheral Ready (PRHIB), offset 0xA14 ....................................................... 397
Universal Asynchronous Receiver/Transmitter Peripheral Ready (PRUART), offset
0xA18 ........................................................................................................................... 398
Synchronous Serial Interface Peripheral Ready (PRSSI), offset 0xA1C ............................. 400
Inter-Integrated Circuit Peripheral Ready (PRI2C), offset 0xA20 ....................................... 402
Universal Serial Bus Peripheral Ready (PRUSB), offset 0xA28 ......................................... 404
Controller Area Network Peripheral Ready (PRCAN), offset 0xA34 ................................... 405
Analog-to-Digital Converter Peripheral Ready (PRADC), offset 0xA38 ............................... 406
Analog Comparator Peripheral Ready (PRACMP), offset 0xA3C ....................................... 407
EEPROM Peripheral Ready (PREEPROM), offset 0xA58 ................................................. 408
32/64-Bit Wide General-Purpose Timer Peripheral Ready (PRWTIMER), offset 0xA5C ...... 409
Device Capabilities 0 (DC0), offset 0x008 ........................................................................ 411
Device Capabilities 1 (DC1), offset 0x010 ........................................................................ 413
Device Capabilities 2 (DC2), offset 0x014 ........................................................................ 416
Device Capabilities 3 (DC3), offset 0x018 ........................................................................ 419
Device Capabilities 4 (DC4), offset 0x01C ....................................................................... 423
Device Capabilities 5 (DC5), offset 0x020 ........................................................................ 426
Device Capabilities 6 (DC6), offset 0x024 ........................................................................ 428
Device Capabilities 7 (DC7), offset 0x028 ........................................................................ 429
Device Capabilities 8 (DC8), offset 0x02C ....................................................................... 432
Software Reset Control 0 (SRCR0), offset 0x040 ............................................................. 435
Software Reset Control 1 (SRCR1), offset 0x044 ............................................................. 437
Software Reset Control 2 (SRCR2), offset 0x048 ............................................................. 440
Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 ................................... 442
Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 ................................... 445
Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 ................................... 448
Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 ................................. 451
Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 ................................. 453
Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 ................................. 456
Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 ....................... 459
Deep-Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 ....................... 461
Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 ....................... 464
Device Capabilities 9 (DC9), offset 0x190 ........................................................................ 467
Non-Volatile Memory Information (NVMSTAT), offset 0x1A0 ............................................. 469
System Exception Module .......................................................................................................... 470
Register 1:
Register 2:
Register 3:
Register 4:
System Exception Raw Interrupt Status (SYSEXCRIS), offset 0x000 ................................
System Exception Interrupt Mask (SYSEXCIM), offset 0x004 ...........................................
System Exception Masked Interrupt Status (SYSEXCMIS), offset 0x008 ...........................
System Exception Interrupt Clear (SYSEXCIC), offset 0x00C ...........................................
471
473
475
477
Hibernation Module ..................................................................................................................... 478
Register 1:
Register 2:
Hibernation RTC Counter (HIBRTCC), offset 0x000 ......................................................... 492
Hibernation RTC Match 0 (HIBRTCM0), offset 0x004 ....................................................... 493
June 12, 2014
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Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Hibernation RTC Load (HIBRTCLD), offset 0x00C ...........................................................
Hibernation Control (HIBCTL), offset 0x010 .....................................................................
Hibernation Interrupt Mask (HIBIM), offset 0x014 .............................................................
Hibernation Raw Interrupt Status (HIBRIS), offset 0x018 ..................................................
Hibernation Masked Interrupt Status (HIBMIS), offset 0x01C ............................................
Hibernation Interrupt Clear (HIBIC), offset 0x020 .............................................................
Hibernation RTC Trim (HIBRTCT), offset 0x024 ...............................................................
Hibernation RTC Sub Seconds (HIBRTCSS), offset 0x028 ...............................................
Hibernation Data (HIBDATA), offset 0x030-0x06F ............................................................
494
495
499
501
503
505
506
507
508
Internal Memory ........................................................................................................................... 509
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
Register 29:
Register 30:
Register 31:
Register 32:
Register 33:
Register 34:
Register 35:
Register 36:
Register 37:
Register 38:
Flash Memory Address (FMA), offset 0x000 .................................................................... 527
Flash Memory Data (FMD), offset 0x004 ......................................................................... 528
Flash Memory Control (FMC), offset 0x008 ..................................................................... 529
Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ............................................ 531
Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................ 534
Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 ..................... 536
Flash Memory Control 2 (FMC2), offset 0x020 ................................................................. 539
Flash Write Buffer Valid (FWBVAL), offset 0x030 ............................................................. 540
Flash Write Buffer n (FWBn), offset 0x100 - 0x17C .......................................................... 541
Flash Size (FSIZE), offset 0xFC0 .................................................................................... 542
SRAM Size (SSIZE), offset 0xFC4 .................................................................................. 543
ROM Software Map (ROMSWMAP), offset 0xFCC ........................................................... 544
EEPROM Size Information (EESIZE), offset 0x000 .......................................................... 545
EEPROM Current Block (EEBLOCK), offset 0x004 .......................................................... 546
EEPROM Current Offset (EEOFFSET), offset 0x008 ........................................................ 547
EEPROM Read-Write (EERDWR), offset 0x010 .............................................................. 548
EEPROM Read-Write with Increment (EERDWRINC), offset 0x014 .................................. 549
EEPROM Done Status (EEDONE), offset 0x018 .............................................................. 550
EEPROM Support Control and Status (EESUPP), offset 0x01C ........................................ 552
EEPROM Unlock (EEUNLOCK), offset 0x020 .................................................................. 554
EEPROM Protection (EEPROT), offset 0x030 ................................................................. 555
EEPROM Password (EEPASS0), offset 0x034 ................................................................. 557
EEPROM Password (EEPASS1), offset 0x038 ................................................................. 557
EEPROM Password (EEPASS2), offset 0x03C ................................................................ 557
EEPROM Interrupt (EEINT), offset 0x040 ........................................................................ 558
EEPROM Block Hide (EEHIDE), offset 0x050 .................................................................. 559
EEPROM Debug Mass Erase (EEDBGME), offset 0x080 ................................................. 560
EEPROM Peripheral Properties (EEPROMPP), offset 0xFC0 ........................................... 561
ROM Control (RMCTL), offset 0x0F0 .............................................................................. 562
Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 ................... 563
Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 .................................... 563
Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208 .................................... 563
Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C ................................... 563
Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400 ............... 564
Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404 ............................... 564
Flash Memory Protection Program Enable 2 (FMPPE2), offset 0x408 ............................... 564
Flash Memory Protection Program Enable 3 (FMPPE3), offset 0x40C ............................... 564
Boot Configuration (BOOTCFG), offset 0x1D0 ................................................................. 566
24
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Register 39:
Register 40:
Register 41:
Register 42:
User Register 0 (USER_REG0), offset 0x1E0 ..................................................................
User Register 1 (USER_REG1), offset 0x1E4 ..................................................................
User Register 2 (USER_REG2), offset 0x1E8 ..................................................................
User Register 3 (USER_REG3), offset 0x1EC .................................................................
569
569
569
569
Micro Direct Memory Access (μDMA) ........................................................................................ 570
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
Register 29:
Register 30:
Register 31:
Register 32:
Register 33:
Register 34:
Register 35:
DMA Channel Source Address End Pointer (DMASRCENDP), offset 0x000 ...................... 594
DMA Channel Destination Address End Pointer (DMADSTENDP), offset 0x004 ................ 595
DMA Channel Control Word (DMACHCTL), offset 0x008 .................................................. 596
DMA Status (DMASTAT), offset 0x000 ............................................................................ 601
DMA Configuration (DMACFG), offset 0x004 ................................................................... 603
DMA Channel Control Base Pointer (DMACTLBASE), offset 0x008 .................................. 604
DMA Alternate Channel Control Base Pointer (DMAALTBASE), offset 0x00C .................... 605
DMA Channel Wait-on-Request Status (DMAWAITSTAT), offset 0x010 ............................. 606
DMA Channel Software Request (DMASWREQ), offset 0x014 ......................................... 607
DMA Channel Useburst Set (DMAUSEBURSTSET), offset 0x018 .................................... 608
DMA Channel Useburst Clear (DMAUSEBURSTCLR), offset 0x01C ................................. 609
DMA Channel Request Mask Set (DMAREQMASKSET), offset 0x020 .............................. 610
DMA Channel Request Mask Clear (DMAREQMASKCLR), offset 0x024 ........................... 611
DMA Channel Enable Set (DMAENASET), offset 0x028 ................................................... 612
DMA Channel Enable Clear (DMAENACLR), offset 0x02C ............................................... 613
DMA Channel Primary Alternate Set (DMAALTSET), offset 0x030 .................................... 614
DMA Channel Primary Alternate Clear (DMAALTCLR), offset 0x034 ................................. 615
DMA Channel Priority Set (DMAPRIOSET), offset 0x038 ................................................. 616
DMA Channel Priority Clear (DMAPRIOCLR), offset 0x03C .............................................. 617
DMA Bus Error Clear (DMAERRCLR), offset 0x04C ........................................................ 618
DMA Channel Assignment (DMACHASGN), offset 0x500 ................................................. 619
DMA Channel Interrupt Status (DMACHIS), offset 0x504 .................................................. 620
DMA Channel Map Select 0 (DMACHMAP0), offset 0x510 ............................................... 621
DMA Channel Map Select 1 (DMACHMAP1), offset 0x514 ............................................... 622
DMA Channel Map Select 2 (DMACHMAP2), offset 0x518 ............................................... 623
DMA Channel Map Select 3 (DMACHMAP3), offset 0x51C .............................................. 624
DMA Peripheral Identification 0 (DMAPeriphID0), offset 0xFE0 ......................................... 625
DMA Peripheral Identification 1 (DMAPeriphID1), offset 0xFE4 ......................................... 626
DMA Peripheral Identification 2 (DMAPeriphID2), offset 0xFE8 ......................................... 627
DMA Peripheral Identification 3 (DMAPeriphID3), offset 0xFEC ........................................ 628
DMA Peripheral Identification 4 (DMAPeriphID4), offset 0xFD0 ......................................... 629
DMA PrimeCell Identification 0 (DMAPCellID0), offset 0xFF0 ........................................... 630
DMA PrimeCell Identification 1 (DMAPCellID1), offset 0xFF4 ........................................... 631
DMA PrimeCell Identification 2 (DMAPCellID2), offset 0xFF8 ........................................... 632
DMA PrimeCell Identification 3 (DMAPCellID3), offset 0xFFC ........................................... 633
General-Purpose Input/Outputs (GPIOs) ................................................................................... 634
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
GPIO Data (GPIODATA), offset 0x000 ............................................................................
GPIO Direction (GPIODIR), offset 0x400 .........................................................................
GPIO Interrupt Sense (GPIOIS), offset 0x404 ..................................................................
GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 ........................................................
GPIO Interrupt Event (GPIOIEV), offset 0x40C ................................................................
GPIO Interrupt Mask (GPIOIM), offset 0x410 ...................................................................
GPIO Raw Interrupt Status (GPIORIS), offset 0x414 ........................................................
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650
651
652
654
655
656
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Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
Register 29:
Register 30:
Register 31:
Register 32:
Register 33:
Register 34:
Register 35:
Register 36:
GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 ................................................... 657
GPIO Interrupt Clear (GPIOICR), offset 0x41C ................................................................ 658
GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 ............................................ 659
GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 ........................................................ 661
GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 ........................................................ 662
GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 ........................................................ 663
GPIO Open Drain Select (GPIOODR), offset 0x50C ......................................................... 664
GPIO Pull-Up Select (GPIOPUR), offset 0x510 ................................................................ 665
GPIO Pull-Down Select (GPIOPDR), offset 0x514 ........................................................... 667
GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 ................................................ 669
GPIO Digital Enable (GPIODEN), offset 0x51C ................................................................ 670
GPIO Lock (GPIOLOCK), offset 0x520 ............................................................................ 672
GPIO Commit (GPIOCR), offset 0x524 ............................................................................ 673
GPIO Analog Mode Select (GPIOAMSEL), offset 0x528 ................................................... 675
GPIO Port Control (GPIOPCTL), offset 0x52C ................................................................. 677
GPIO ADC Control (GPIOADCCTL), offset 0x530 ............................................................ 679
GPIO DMA Control (GPIODMACTL), offset 0x534 ........................................................... 680
GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 ....................................... 681
GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 ....................................... 682
GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 ....................................... 683
GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC ...................................... 684
GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 ....................................... 685
GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4 ....................................... 686
GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 ....................................... 687
GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC ...................................... 688
GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 .......................................... 689
GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 .......................................... 690
GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 .......................................... 691
GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC ......................................... 692
General-Purpose Timers ............................................................................................................. 693
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
GPTM Configuration (GPTMCFG), offset 0x000 .............................................................. 716
GPTM Timer A Mode (GPTMTAMR), offset 0x004 ........................................................... 718
GPTM Timer B Mode (GPTMTBMR), offset 0x008 ........................................................... 722
GPTM Control (GPTMCTL), offset 0x00C ........................................................................ 726
GPTM Synchronize (GPTMSYNC), offset 0x010 .............................................................. 730
GPTM Interrupt Mask (GPTMIMR), offset 0x018 .............................................................. 734
GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C ..................................................... 737
GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 ................................................ 740
GPTM Interrupt Clear (GPTMICR), offset 0x024 .............................................................. 743
GPTM Timer A Interval Load (GPTMTAILR), offset 0x028 ................................................ 745
GPTM Timer B Interval Load (GPTMTBILR), offset 0x02C ................................................ 746
GPTM Timer A Match (GPTMTAMATCHR), offset 0x030 .................................................. 747
GPTM Timer B Match (GPTMTBMATCHR), offset 0x034 ................................................. 748
GPTM Timer A Prescale (GPTMTAPR), offset 0x038 ....................................................... 749
GPTM Timer B Prescale (GPTMTBPR), offset 0x03C ...................................................... 750
GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 ........................................... 751
GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ........................................... 752
GPTM Timer A (GPTMTAR), offset 0x048 ....................................................................... 753
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Tiva™ TM4C1237H6PZ Microcontroller
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
GPTM Timer B (GPTMTBR), offset 0x04C ....................................................................... 754
GPTM Timer A Value (GPTMTAV), offset 0x050 ............................................................... 755
GPTM Timer B Value (GPTMTBV), offset 0x054 .............................................................. 756
GPTM RTC Predivide (GPTMRTCPD), offset 0x058 ........................................................ 757
GPTM Timer A Prescale Snapshot (GPTMTAPS), offset 0x05C ........................................ 758
GPTM Timer B Prescale Snapshot (GPTMTBPS), offset 0x060 ........................................ 759
GPTM Timer A Prescale Value (GPTMTAPV), offset 0x064 .............................................. 760
GPTM Timer B Prescale Value (GPTMTBPV), offset 0x068 .............................................. 761
GPTM Peripheral Properties (GPTMPP), offset 0xFC0 ..................................................... 762
Watchdog Timers ......................................................................................................................... 763
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Watchdog Load (WDTLOAD), offset 0x000 ...................................................................... 767
Watchdog Value (WDTVALUE), offset 0x004 ................................................................... 768
Watchdog Control (WDTCTL), offset 0x008 ..................................................................... 769
Watchdog Interrupt Clear (WDTICR), offset 0x00C .......................................................... 771
Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 .................................................. 772
Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 ............................................. 773
Watchdog Test (WDTTEST), offset 0x418 ....................................................................... 774
Watchdog Lock (WDTLOCK), offset 0xC00 ..................................................................... 775
Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 ................................. 776
Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 ................................. 777
Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 ................................. 778
Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC ................................ 779
Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ................................. 780
Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ................................. 781
Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ................................. 782
Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC ................................. 783
Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 .................................... 784
Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 .................................... 785
Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 .................................... 786
Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC .................................. 787
Analog-to-Digital Converter (ADC) ............................................................................................. 788
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
ADC Active Sample Sequencer (ADCACTSS), offset 0x000 ............................................. 810
ADC Raw Interrupt Status (ADCRIS), offset 0x004 ........................................................... 812
ADC Interrupt Mask (ADCIM), offset 0x008 ..................................................................... 814
ADC Interrupt Status and Clear (ADCISC), offset 0x00C .................................................. 817
ADC Overflow Status (ADCOSTAT), offset 0x010 ............................................................ 820
ADC Event Multiplexer Select (ADCEMUX), offset 0x014 ................................................. 822
ADC Underflow Status (ADCUSTAT), offset 0x018 ........................................................... 827
ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020 ............................................. 828
ADC Sample Phase Control (ADCSPC), offset 0x024 ...................................................... 830
ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028 ................................. 832
ADC Sample Averaging Control (ADCSAC), offset 0x030 ................................................. 834
ADC Digital Comparator Interrupt Status and Clear (ADCDCISC), offset 0x034 ................. 835
ADC Control (ADCCTL), offset 0x038 ............................................................................. 837
ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0), offset 0x040 ............... 838
ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044 ........................................ 840
ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048 ................................ 847
ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068 ................................ 847
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Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
Register 29:
Register 30:
Register 31:
Register 32:
Register 33:
Register 34:
Register 35:
Register 36:
Register 37:
Register 38:
Register 39:
Register 40:
Register 41:
Register 42:
Register 43:
Register 44:
Register 45:
Register 46:
Register 47:
Register 48:
Register 49:
Register 50:
Register 51:
Register 52:
Register 53:
Register 54:
Register 55:
Register 56:
Register 57:
Register 58:
Register 59:
Register 60:
Register 61:
ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088 ................................ 847
ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset 0x0A8 ............................... 847
ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset 0x04C ............................. 848
ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset 0x06C ............................. 848
ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset 0x08C ............................ 848
ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset 0x0AC ............................ 848
ADC Sample Sequence 0 Operation (ADCSSOP0), offset 0x050 ...................................... 850
ADC Sample Sequence 0 Digital Comparator Select (ADCSSDC0), offset 0x054 .............. 852
ADC Sample Sequence Extended Input Multiplexer Select 0 (ADCSSEMUX0), offset
0x058 ........................................................................................................................... 854
ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1), offset 0x060 ............... 856
ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2), offset 0x080 ............... 856
ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064 ........................................ 857
ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084 ........................................ 857
ADC Sample Sequence 1 Operation (ADCSSOP1), offset 0x070 ...................................... 861
ADC Sample Sequence 2 Operation (ADCSSOP2), offset 0x090 ..................................... 861
ADC Sample Sequence 1 Digital Comparator Select (ADCSSDC1), offset 0x074 .............. 862
ADC Sample Sequence 2 Digital Comparator Select (ADCSSDC2), offset 0x094 .............. 862
ADC Sample Sequence Extended Input Multiplexer Select 1 (ADCSSEMUX1), offset
0x078 ........................................................................................................................... 864
ADC Sample Sequence Extended Input Multiplexer Select 2 (ADCSSEMUX2), offset 0x098
..................................................................................................................................... 864
ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3), offset 0x0A0 ............... 866
ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4 ........................................ 867
ADC Sample Sequence 3 Operation (ADCSSOP3), offset 0x0B0 ..................................... 869
ADC Sample Sequence 3 Digital Comparator Select (ADCSSDC3), offset 0x0B4 .............. 870
ADC Sample Sequence Extended Input Multiplexer Select 3 (ADCSSEMUX3), offset
0x0B8 ........................................................................................................................... 871
ADC Digital Comparator Reset Initial Conditions (ADCDCRIC), offset 0xD00 ..................... 872
ADC Digital Comparator Control 0 (ADCDCCTL0), offset 0xE00 ....................................... 877
ADC Digital Comparator Control 1 (ADCDCCTL1), offset 0xE04 ....................................... 877
ADC Digital Comparator Control 2 (ADCDCCTL2), offset 0xE08 ....................................... 877
ADC Digital Comparator Control 3 (ADCDCCTL3), offset 0xE0C ...................................... 877
ADC Digital Comparator Control 4 (ADCDCCTL4), offset 0xE10 ....................................... 877
ADC Digital Comparator Control 5 (ADCDCCTL5), offset 0xE14 ....................................... 877
ADC Digital Comparator Control 6 (ADCDCCTL6), offset 0xE18 ....................................... 877
ADC Digital Comparator Control 7 (ADCDCCTL7), offset 0xE1C ...................................... 877
ADC Digital Comparator Range 0 (ADCDCCMP0), offset 0xE40 ....................................... 879
ADC Digital Comparator Range 1 (ADCDCCMP1), offset 0xE44 ....................................... 879
ADC Digital Comparator Range 2 (ADCDCCMP2), offset 0xE48 ....................................... 879
ADC Digital Comparator Range 3 (ADCDCCMP3), offset 0xE4C ...................................... 879
ADC Digital Comparator Range 4 (ADCDCCMP4), offset 0xE50 ....................................... 879
ADC Digital Comparator Range 5 (ADCDCCMP5), offset 0xE54 ....................................... 879
ADC Digital Comparator Range 6 (ADCDCCMP6), offset 0xE58 ....................................... 879
ADC Digital Comparator Range 7 (ADCDCCMP7), offset 0xE5C ...................................... 879
ADC Peripheral Properties (ADCPP), offset 0xFC0 .......................................................... 880
ADC Peripheral Configuration (ADCPC), offset 0xFC4 ..................................................... 882
ADC Clock Configuration (ADCCC), offset 0xFC8 ............................................................ 883
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Tiva™ TM4C1237H6PZ Microcontroller
Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 884
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
Register 29:
Register 30:
UART Data (UARTDR), offset 0x000 ............................................................................... 898
UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... 900
UART Flag (UARTFR), offset 0x018 ................................................................................ 903
UART IrDA Low-Power Register (UARTILPR), offset 0x020 ............................................. 906
UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ 907
UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... 908
UART Line Control (UARTLCRH), offset 0x02C ............................................................... 909
UART Control (UARTCTL), offset 0x030 ......................................................................... 911
UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 915
UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 917
UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 920
UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 923
UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 926
UART DMA Control (UARTDMACTL), offset 0x048 .......................................................... 928
UART 9-Bit Self Address (UART9BITADDR), offset 0x0A4 ............................................... 929
UART 9-Bit Self Address Mask (UART9BITAMASK), offset 0x0A8 .................................... 930
UART Peripheral Properties (UARTPP), offset 0xFC0 ...................................................... 931
UART Clock Configuration (UARTCC), offset 0xFC8 ........................................................ 932
UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 933
UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 934
UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 935
UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 936
UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 937
UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 938
UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... 939
UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 940
UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 941
UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 942
UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 943
UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 944
Synchronous Serial Interface (SSI) ............................................................................................ 945
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 962
SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 964
SSI Data (SSIDR), offset 0x008 ...................................................................................... 966
SSI Status (SSISR), offset 0x00C ................................................................................... 967
SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 969
SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 970
SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 971
SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 973
SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 975
SSI DMA Control (SSIDMACTL), offset 0x024 ................................................................. 976
SSI Clock Configuration (SSICC), offset 0xFC8 ............................................................... 977
SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 978
SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 979
SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 980
SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 981
SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 982
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Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 .............................................
SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 .............................................
SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................
SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ...............................................
SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ...............................................
SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ...............................................
SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ...............................................
983
984
985
986
987
988
989
Inter-Integrated Circuit (I2C) Interface ........................................................................................ 990
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
I2C Master Slave Address (I2CMSA), offset 0x000 ......................................................... 1012
I2C Master Control/Status (I2CMCS), offset 0x004 ......................................................... 1013
I2C Master Data (I2CMDR), offset 0x008 ....................................................................... 1018
I2C Master Timer Period (I2CMTPR), offset 0x00C ......................................................... 1019
I2C Master Interrupt Mask (I2CMIMR), offset 0x010 ....................................................... 1020
I2C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ............................................... 1021
I2C Master Masked Interrupt Status (I2CMMIS), offset 0x018 .......................................... 1022
I2C Master Interrupt Clear (I2CMICR), offset 0x01C ....................................................... 1023
I2C Master Configuration (I2CMCR), offset 0x020 .......................................................... 1024
I2C Master Clock Low Timeout Count (I2CMCLKOCNT), offset 0x024 ............................. 1026
I2C Master Bus Monitor (I2CMBMON), offset 0x02C ....................................................... 1027
I2C Master Configuration 2 (I2CMCR2), offset 0x038 ...................................................... 1028
I2C Slave Own Address (I2CSOAR), offset 0x800 .......................................................... 1029
I2C Slave Control/Status (I2CSCSR), offset 0x804 ......................................................... 1030
I2C Slave Data (I2CSDR), offset 0x808 ......................................................................... 1032
I2C Slave Interrupt Mask (I2CSIMR), offset 0x80C ......................................................... 1033
I2C Slave Raw Interrupt Status (I2CSRIS), offset 0x810 ................................................. 1034
I2C Slave Masked Interrupt Status (I2CSMIS), offset 0x814 ............................................ 1035
I2C Slave Interrupt Clear (I2CSICR), offset 0x818 .......................................................... 1036
I2C Slave Own Address 2 (I2CSOAR2), offset 0x81C ..................................................... 1037
I2C Slave ACK Control (I2CSACKCTL), offset 0x820 ...................................................... 1038
I2C Peripheral Properties (I2CPP), offset 0xFC0 ............................................................ 1039
I2C Peripheral Configuration (I2CPC), offset 0xFC4 ....................................................... 1040
Controller Area Network (CAN) Module ................................................................................... 1041
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
CAN Control (CANCTL), offset 0x000 ............................................................................ 1062
CAN Status (CANSTS), offset 0x004 ............................................................................. 1064
CAN Error Counter (CANERR), offset 0x008 ................................................................. 1067
CAN Bit Timing (CANBIT), offset 0x00C ........................................................................ 1068
CAN Interrupt (CANINT), offset 0x010 ........................................................................... 1069
CAN Test (CANTST), offset 0x014 ................................................................................ 1070
CAN Baud Rate Prescaler Extension (CANBRPE), offset 0x018 ..................................... 1072
CAN IF1 Command Request (CANIF1CRQ), offset 0x020 .............................................. 1073
CAN IF2 Command Request (CANIF2CRQ), offset 0x080 .............................................. 1073
CAN IF1 Command Mask (CANIF1CMSK), offset 0x024 ................................................ 1074
CAN IF2 Command Mask (CANIF2CMSK), offset 0x084 ................................................ 1074
CAN IF1 Mask 1 (CANIF1MSK1), offset 0x028 .............................................................. 1077
CAN IF2 Mask 1 (CANIF2MSK1), offset 0x088 .............................................................. 1077
CAN IF1 Mask 2 (CANIF1MSK2), offset 0x02C .............................................................. 1078
CAN IF2 Mask 2 (CANIF2MSK2), offset 0x08C .............................................................. 1078
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Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
Register 29:
Register 30:
Register 31:
Register 32:
Register 33:
Register 34:
Register 35:
Register 36:
Register 37:
CAN IF1 Arbitration 1 (CANIF1ARB1), offset 0x030 ....................................................... 1080
CAN IF2 Arbitration 1 (CANIF2ARB1), offset 0x090 ....................................................... 1080
CAN IF1 Arbitration 2 (CANIF1ARB2), offset 0x034 ....................................................... 1081
CAN IF2 Arbitration 2 (CANIF2ARB2), offset 0x094 ....................................................... 1081
CAN IF1 Message Control (CANIF1MCTL), offset 0x038 ................................................ 1083
CAN IF2 Message Control (CANIF2MCTL), offset 0x098 ................................................ 1083
CAN IF1 Data A1 (CANIF1DA1), offset 0x03C ............................................................... 1086
CAN IF1 Data A2 (CANIF1DA2), offset 0x040 ................................................................ 1086
CAN IF1 Data B1 (CANIF1DB1), offset 0x044 ................................................................ 1086
CAN IF1 Data B2 (CANIF1DB2), offset 0x048 ................................................................ 1086
CAN IF2 Data A1 (CANIF2DA1), offset 0x09C ............................................................... 1086
CAN IF2 Data A2 (CANIF2DA2), offset 0x0A0 ............................................................... 1086
CAN IF2 Data B1 (CANIF2DB1), offset 0x0A4 ............................................................... 1086
CAN IF2 Data B2 (CANIF2DB2), offset 0x0A8 ............................................................... 1086
CAN Transmission Request 1 (CANTXRQ1), offset 0x100 .............................................. 1087
CAN Transmission Request 2 (CANTXRQ2), offset 0x104 .............................................. 1087
CAN New Data 1 (CANNWDA1), offset 0x120 ............................................................... 1088
CAN New Data 2 (CANNWDA2), offset 0x124 ............................................................... 1088
CAN Message 1 Interrupt Pending (CANMSG1INT), offset 0x140 ................................... 1089
CAN Message 2 Interrupt Pending (CANMSG2INT), offset 0x144 ................................... 1089
CAN Message 1 Valid (CANMSG1VAL), offset 0x160 ..................................................... 1090
CAN Message 2 Valid (CANMSG2VAL), offset 0x164 ..................................................... 1090
Universal Serial Bus (USB) Controller ..................................................................................... 1091
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
USB Device Functional Address (USBFADDR), offset 0x000 .......................................... 1114
USB Power (USBPOWER), offset 0x001 ....................................................................... 1115
USB Transmit Interrupt Status (USBTXIS), offset 0x002 ................................................. 1118
USB Receive Interrupt Status (USBRXIS), offset 0x004 ................................................. 1120
USB Transmit Interrupt Enable (USBTXIE), offset 0x006 ................................................ 1121
USB Receive Interrupt Enable (USBRXIE), offset 0x008 ................................................. 1123
USB General Interrupt Status (USBIS), offset 0x00A ...................................................... 1124
USB Interrupt Enable (USBIE), offset 0x00B .................................................................. 1127
USB Frame Value (USBFRAME), offset 0x00C .............................................................. 1130
USB Endpoint Index (USBEPIDX), offset 0x00E ............................................................ 1131
USB Test Mode (USBTEST), offset 0x00F ..................................................................... 1132
USB FIFO Endpoint 0 (USBFIFO0), offset 0x020 ........................................................... 1134
USB FIFO Endpoint 1 (USBFIFO1), offset 0x024 ........................................................... 1134
USB FIFO Endpoint 2 (USBFIFO2), offset 0x028 ........................................................... 1134
USB FIFO Endpoint 3 (USBFIFO3), offset 0x02C ........................................................... 1134
USB FIFO Endpoint 4 (USBFIFO4), offset 0x030 ........................................................... 1134
USB FIFO Endpoint 5 (USBFIFO5), offset 0x034 ........................................................... 1134
USB FIFO Endpoint 6 (USBFIFO6), offset 0x038 ........................................................... 1134
USB FIFO Endpoint 7 (USBFIFO7), offset 0x03C ........................................................... 1134
USB Device Control (USBDEVCTL), offset 0x060 .......................................................... 1135
USB Transmit Dynamic FIFO Sizing (USBTXFIFOSZ), offset 0x062 ................................ 1137
USB Receive Dynamic FIFO Sizing (USBRXFIFOSZ), offset 0x063 ................................ 1137
USB Transmit FIFO Start Address (USBTXFIFOADD), offset 0x064 ................................ 1138
USB Receive FIFO Start Address (USBRXFIFOADD), offset 0x066 ................................ 1138
USB Connect Timing (USBCONTIM), offset 0x07A ........................................................ 1139
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Register 38:
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Register 40:
Register 41:
Register 42:
Register 43:
Register 44:
Register 45:
Register 46:
Register 47:
Register 48:
Register 49:
Register 50:
Register 51:
Register 52:
Register 53:
Register 54:
Register 55:
Register 56:
Register 57:
Register 58:
Register 59:
Register 60:
Register 61:
Register 62:
Register 63:
Register 64:
Register 65:
Register 66:
Register 67:
Register 68:
Register 69:
Register 70:
Register 71:
Register 72:
Register 73:
USB OTG VBUS Pulse Timing (USBVPLEN), offset 0x07B ............................................ 1140
USB Full-Speed Last Transaction to End of Frame Timing (USBFSEOF), offset 0x07D .... 1141
USB Low-Speed Last Transaction to End of Frame Timing (USBLSEOF), offset 0x07E .... 1142
USB Transmit Functional Address Endpoint 0 (USBTXFUNCADDR0), offset 0x080 ......... 1143
USB Transmit Functional Address Endpoint 1 (USBTXFUNCADDR1), offset 0x088 ......... 1143
USB Transmit Functional Address Endpoint 2 (USBTXFUNCADDR2), offset 0x090 ......... 1143
USB Transmit Functional Address Endpoint 3 (USBTXFUNCADDR3), offset 0x098 ......... 1143
USB Transmit Functional Address Endpoint 4 (USBTXFUNCADDR4), offset 0x0A0 ......... 1143
USB Transmit Functional Address Endpoint 5 (USBTXFUNCADDR5), offset 0x0A8 ......... 1143
USB Transmit Functional Address Endpoint 6 (USBTXFUNCADDR6), offset 0x0B0 ......... 1143
USB Transmit Functional Address Endpoint 7 (USBTXFUNCADDR7), offset 0x0B8 ......... 1143
USB Transmit Hub Address Endpoint 0 (USBTXHUBADDR0), offset 0x082 ..................... 1144
USB Transmit Hub Address Endpoint 1 (USBTXHUBADDR1), offset 0x08A .................... 1144
USB Transmit Hub Address Endpoint 2 (USBTXHUBADDR2), offset 0x092 ..................... 1144
USB Transmit Hub Address Endpoint 3 (USBTXHUBADDR3), offset 0x09A .................... 1144
USB Transmit Hub Address Endpoint 4 (USBTXHUBADDR4), offset 0x0A2 .................... 1144
USB Transmit Hub Address Endpoint 5 (USBTXHUBADDR5), offset 0x0AA .................... 1144
USB Transmit Hub Address Endpoint 6 (USBTXHUBADDR6), offset 0x0B2 .................... 1144
USB Transmit Hub Address Endpoint 7 (USBTXHUBADDR7), offset 0x0BA .................... 1144
USB Transmit Hub Port Endpoint 0 (USBTXHUBPORT0), offset 0x083 ........................... 1145
USB Transmit Hub Port Endpoint 1 (USBTXHUBPORT1), offset 0x08B ........................... 1145
USB Transmit Hub Port Endpoint 2 (USBTXHUBPORT2), offset 0x093 ........................... 1145
USB Transmit Hub Port Endpoint 3 (USBTXHUBPORT3), offset 0x09B ........................... 1145
USB Transmit Hub Port Endpoint 4 (USBTXHUBPORT4), offset 0x0A3 ........................... 1145
USB Transmit Hub Port Endpoint 5 (USBTXHUBPORT5), offset 0x0AB .......................... 1145
USB Transmit Hub Port Endpoint 6 (USBTXHUBPORT6), offset 0x0B3 ........................... 1145
USB Transmit Hub Port Endpoint 7 (USBTXHUBPORT7), offset 0x0BB .......................... 1145
USB Receive Functional Address Endpoint 1 (USBRXFUNCADDR1), offset 0x08C ......... 1146
USB Receive Functional Address Endpoint 2 (USBRXFUNCADDR2), offset 0x094 ......... 1146
USB Receive Functional Address Endpoint 3 (USBRXFUNCADDR3), offset 0x09C ......... 1146
USB Receive Functional Address Endpoint 4 (USBRXFUNCADDR4), offset 0x0A4 ......... 1146
USB Receive Functional Address Endpoint 5 (USBRXFUNCADDR5), offset 0x0AC ......... 1146
USB Receive Functional Address Endpoint 6 (USBRXFUNCADDR6), offset 0x0B4 ......... 1146
USB Receive Functional Address Endpoint 7 (USBRXFUNCADDR7), offset 0x0BC ......... 1146
USB Receive Hub Address Endpoint 1 (USBRXHUBADDR1), offset 0x08E ..................... 1147
USB Receive Hub Address Endpoint 2 (USBRXHUBADDR2), offset 0x096 ..................... 1147
USB Receive Hub Address Endpoint 3 (USBRXHUBADDR3), offset 0x09E ..................... 1147
USB Receive Hub Address Endpoint 4 (USBRXHUBADDR4), offset 0x0A6 ..................... 1147
USB Receive Hub Address Endpoint 5 (USBRXHUBADDR5), offset 0x0AE .................... 1147
USB Receive Hub Address Endpoint 6 (USBRXHUBADDR6), offset 0x0B6 ..................... 1147
USB Receive Hub Address Endpoint 7 (USBRXHUBADDR7), offset 0x0BE .................... 1147
USB Receive Hub Port Endpoint 1 (USBRXHUBPORT1), offset 0x08F ........................... 1148
USB Receive Hub Port Endpoint 2 (USBRXHUBPORT2), offset 0x097 ........................... 1148
USB Receive Hub Port Endpoint 3 (USBRXHUBPORT3), offset 0x09F ........................... 1148
USB Receive Hub Port Endpoint 4 (USBRXHUBPORT4), offset 0x0A7 ........................... 1148
USB Receive Hub Port Endpoint 5 (USBRXHUBPORT5), offset 0x0AF ........................... 1148
USB Receive Hub Port Endpoint 6 (USBRXHUBPORT6), offset 0x0B7 ........................... 1148
USB Receive Hub Port Endpoint 7 (USBRXHUBPORT7), offset 0x0BF ........................... 1148
32
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Tiva™ TM4C1237H6PZ Microcontroller
Register 74:
Register 75:
Register 76:
Register 77:
Register 78:
Register 79:
Register 80:
Register 81:
Register 82:
Register 83:
Register 84:
Register 85:
Register 86:
Register 87:
Register 88:
Register 89:
Register 90:
Register 91:
Register 92:
Register 93:
Register 94:
Register 95:
Register 96:
Register 97:
Register 98:
Register 99:
Register 100:
Register 101:
Register 102:
Register 103:
Register 104:
Register 105:
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Register 108:
Register 109:
Register 110:
Register 111:
Register 112:
Register 113:
Register 114:
Register 115:
Register 116:
Register 117:
Register 118:
Register 119:
Register 120:
Register 121:
USB Maximum Transmit Data Endpoint 1 (USBTXMAXP1), offset 0x110 ......................... 1149
USB Maximum Transmit Data Endpoint 2 (USBTXMAXP2), offset 0x120 ........................ 1149
USB Maximum Transmit Data Endpoint 3 (USBTXMAXP3), offset 0x130 ........................ 1149
USB Maximum Transmit Data Endpoint 4 (USBTXMAXP4), offset 0x140 ........................ 1149
USB Maximum Transmit Data Endpoint 5 (USBTXMAXP5), offset 0x150 ........................ 1149
USB Maximum Transmit Data Endpoint 6 (USBTXMAXP6), offset 0x160 ........................ 1149
USB Maximum Transmit Data Endpoint 7 (USBTXMAXP7), offset 0x170 ........................ 1149
USB Control and Status Endpoint 0 Low (USBCSRL0), offset 0x102 ............................... 1150
USB Control and Status Endpoint 0 High (USBCSRH0), offset 0x103 ............................. 1154
USB Receive Byte Count Endpoint 0 (USBCOUNT0), offset 0x108 ................................. 1156
USB Type Endpoint 0 (USBTYPE0), offset 0x10A .......................................................... 1157
USB NAK Limit (USBNAKLMT), offset 0x10B ................................................................ 1158
USB Transmit Control and Status Endpoint 1 Low (USBTXCSRL1), offset 0x112 ............. 1159
USB Transmit Control and Status Endpoint 2 Low (USBTXCSRL2), offset 0x122 ............. 1159
USB Transmit Control and Status Endpoint 3 Low (USBTXCSRL3), offset 0x132 ............. 1159
USB Transmit Control and Status Endpoint 4 Low (USBTXCSRL4), offset 0x142 ............. 1159
USB Transmit Control and Status Endpoint 5 Low (USBTXCSRL5), offset 0x152 ............. 1159
USB Transmit Control and Status Endpoint 6 Low (USBTXCSRL6), offset 0x162 ............. 1159
USB Transmit Control and Status Endpoint 7 Low (USBTXCSRL7), offset 0x172 ............. 1159
USB Transmit Control and Status Endpoint 1 High (USBTXCSRH1), offset 0x113 ............ 1163
USB Transmit Control and Status Endpoint 2 High (USBTXCSRH2), offset 0x123 ........... 1163
USB Transmit Control and Status Endpoint 3 High (USBTXCSRH3), offset 0x133 ........... 1163
USB Transmit Control and Status Endpoint 4 High (USBTXCSRH4), offset 0x143 ........... 1163
USB Transmit Control and Status Endpoint 5 High (USBTXCSRH5), offset 0x153 ........... 1163
USB Transmit Control and Status Endpoint 6 High (USBTXCSRH6), offset 0x163 ........... 1163
USB Transmit Control and Status Endpoint 7 High (USBTXCSRH7), offset 0x173 ........... 1163
USB Maximum Receive Data Endpoint 1 (USBRXMAXP1), offset 0x114 ......................... 1167
USB Maximum Receive Data Endpoint 2 (USBRXMAXP2), offset 0x124 ......................... 1167
USB Maximum Receive Data Endpoint 3 (USBRXMAXP3), offset 0x134 ......................... 1167
USB Maximum Receive Data Endpoint 4 (USBRXMAXP4), offset 0x144 ......................... 1167
USB Maximum Receive Data Endpoint 5 (USBRXMAXP5), offset 0x154 ......................... 1167
USB Maximum Receive Data Endpoint 6 (USBRXMAXP6), offset 0x164 ......................... 1167
USB Maximum Receive Data Endpoint 7 (USBRXMAXP7), offset 0x174 ......................... 1167
USB Receive Control and Status Endpoint 1 Low (USBRXCSRL1), offset 0x116 ............. 1168
USB Receive Control and Status Endpoint 2 Low (USBRXCSRL2), offset 0x126 ............. 1168
USB Receive Control and Status Endpoint 3 Low (USBRXCSRL3), offset 0x136 ............. 1168
USB Receive Control and Status Endpoint 4 Low (USBRXCSRL4), offset 0x146 ............. 1168
USB Receive Control and Status Endpoint 5 Low (USBRXCSRL5), offset 0x156 ............. 1168
USB Receive Control and Status Endpoint 6 Low (USBRXCSRL6), offset 0x166 ............. 1168
USB Receive Control and Status Endpoint 7 Low (USBRXCSRL7), offset 0x176 ............. 1168
USB Receive Control and Status Endpoint 1 High (USBRXCSRH1), offset 0x117 ............ 1173
USB Receive Control and Status Endpoint 2 High (USBRXCSRH2), offset 0x127 ............ 1173
USB Receive Control and Status Endpoint 3 High (USBRXCSRH3), offset 0x137 ............ 1173
USB Receive Control and Status Endpoint 4 High (USBRXCSRH4), offset 0x147 ............ 1173
USB Receive Control and Status Endpoint 5 High (USBRXCSRH5), offset 0x157 ............ 1173
USB Receive Control and Status Endpoint 6 High (USBRXCSRH6), offset 0x167 ............ 1173
USB Receive Control and Status Endpoint 7 High (USBRXCSRH7), offset 0x177 ............ 1173
USB Receive Byte Count Endpoint 1 (USBRXCOUNT1), offset 0x118 ............................. 1177
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Table of Contents
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Register 123:
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Register 134:
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Register 136:
Register 137:
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Register 140:
Register 141:
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Register 144:
Register 145:
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Register 149:
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Register 152:
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Register 154:
Register 155:
Register 156:
Register 157:
Register 158:
Register 159:
Register 160:
Register 161:
Register 162:
Register 163:
USB Receive Byte Count Endpoint 2 (USBRXCOUNT2), offset 0x128 ............................ 1177
USB Receive Byte Count Endpoint 3 (USBRXCOUNT3), offset 0x138 ............................ 1177
USB Receive Byte Count Endpoint 4 (USBRXCOUNT4), offset 0x148 ............................ 1177
USB Receive Byte Count Endpoint 5 (USBRXCOUNT5), offset 0x158 ............................ 1177
USB Receive Byte Count Endpoint 6 (USBRXCOUNT6), offset 0x168 ............................ 1177
USB Receive Byte Count Endpoint 7 (USBRXCOUNT7), offset 0x178 ............................ 1177
USB Host Transmit Configure Type Endpoint 1 (USBTXTYPE1), offset 0x11A ................. 1178
USB Host Transmit Configure Type Endpoint 2 (USBTXTYPE2), offset 0x12A ................. 1178
USB Host Transmit Configure Type Endpoint 3 (USBTXTYPE3), offset 0x13A ................. 1178
USB Host Transmit Configure Type Endpoint 4 (USBTXTYPE4), offset 0x14A ................. 1178
USB Host Transmit Configure Type Endpoint 5 (USBTXTYPE5), offset 0x15A ................. 1178
USB Host Transmit Configure Type Endpoint 6 (USBTXTYPE6), offset 0x16A ................. 1178
USB Host Transmit Configure Type Endpoint 7 (USBTXTYPE7), offset 0x17A ................. 1178
USB Host Transmit Interval Endpoint 1 (USBTXINTERVAL1), offset 0x11B ..................... 1180
USB Host Transmit Interval Endpoint 2 (USBTXINTERVAL2), offset 0x12B ..................... 1180
USB Host Transmit Interval Endpoint 3 (USBTXINTERVAL3), offset 0x13B ..................... 1180
USB Host Transmit Interval Endpoint 4 (USBTXINTERVAL4), offset 0x14B ..................... 1180
USB Host Transmit Interval Endpoint 5 (USBTXINTERVAL5), offset 0x15B ..................... 1180
USB Host Transmit Interval Endpoint 6 (USBTXINTERVAL6), offset 0x16B ..................... 1180
USB Host Transmit Interval Endpoint 7 (USBTXINTERVAL7), offset 0x17B ..................... 1180
USB Host Configure Receive Type Endpoint 1 (USBRXTYPE1), offset 0x11C ................. 1181
USB Host Configure Receive Type Endpoint 2 (USBRXTYPE2), offset 0x12C ................. 1181
USB Host Configure Receive Type Endpoint 3 (USBRXTYPE3), offset 0x13C ................. 1181
USB Host Configure Receive Type Endpoint 4 (USBRXTYPE4), offset 0x14C ................. 1181
USB Host Configure Receive Type Endpoint 5 (USBRXTYPE5), offset 0x15C ................. 1181
USB Host Configure Receive Type Endpoint 6 (USBRXTYPE6), offset 0x16C ................. 1181
USB Host Configure Receive Type Endpoint 7 (USBRXTYPE7), offset 0x17C ................. 1181
USB Host Receive Polling Interval Endpoint 1 (USBRXINTERVAL1), offset 0x11D ........... 1183
USB Host Receive Polling Interval Endpoint 2 (USBRXINTERVAL2), offset 0x12D ........... 1183
USB Host Receive Polling Interval Endpoint 3 (USBRXINTERVAL3), offset 0x13D ........... 1183
USB Host Receive Polling Interval Endpoint 4 (USBRXINTERVAL4), offset 0x14D ........... 1183
USB Host Receive Polling Interval Endpoint 5 (USBRXINTERVAL5), offset 0x15D ........... 1183
USB Host Receive Polling Interval Endpoint 6 (USBRXINTERVAL6), offset 0x16D ........... 1183
USB Host Receive Polling Interval Endpoint 7 (USBRXINTERVAL7), offset 0x17D ........... 1183
USB Request Packet Count in Block Transfer Endpoint 1 (USBRQPKTCOUNT1), offset
0x304 .......................................................................................................................... 1184
USB Request Packet Count in Block Transfer Endpoint 2 (USBRQPKTCOUNT2), offset
0x308 .......................................................................................................................... 1184
USB Request Packet Count in Block Transfer Endpoint 3 (USBRQPKTCOUNT3), offset
0x30C ......................................................................................................................... 1184
USB Request Packet Count in Block Transfer Endpoint 4 (USBRQPKTCOUNT4), offset
0x310 .......................................................................................................................... 1184
USB Request Packet Count in Block Transfer Endpoint 5 (USBRQPKTCOUNT5), offset
0x314 .......................................................................................................................... 1184
USB Request Packet Count in Block Transfer Endpoint 6 (USBRQPKTCOUNT6), offset
0x318 .......................................................................................................................... 1184
USB Request Packet Count in Block Transfer Endpoint 7 (USBRQPKTCOUNT7), offset
0x31C ......................................................................................................................... 1184
USB Receive Double Packet Buffer Disable (USBRXDPKTBUFDIS), offset 0x340 ........... 1185
34
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Tiva™ TM4C1237H6PZ Microcontroller
Register 164:
Register 165:
Register 166:
Register 167:
Register 168:
Register 169:
Register 170:
Register 171:
Register 172:
Register 173:
Register 174:
Register 175:
Register 176:
Register 177:
Register 178:
Register 179:
Register 180:
Register 181:
USB Transmit Double Packet Buffer Disable (USBTXDPKTBUFDIS), offset 0x342 .......... 1186
USB External Power Control (USBEPC), offset 0x400 .................................................... 1187
USB External Power Control Raw Interrupt Status (USBEPCRIS), offset 0x404 ............... 1190
USB External Power Control Interrupt Mask (USBEPCIM), offset 0x408 .......................... 1191
USB External Power Control Interrupt Status and Clear (USBEPCISC), offset 0x40C ....... 1192
USB Device RESUME Raw Interrupt Status (USBDRRIS), offset 0x410 .......................... 1193
USB Device RESUME Interrupt Mask (USBDRIM), offset 0x414 ..................................... 1194
USB Device RESUME Interrupt Status and Clear (USBDRISC), offset 0x418 .................. 1195
USB General-Purpose Control and Status (USBGPCS), offset 0x41C ............................. 1196
USB VBUS Droop Control (USBVDC), offset 0x430 ....................................................... 1197
USB VBUS Droop Control Raw Interrupt Status (USBVDCRIS), offset 0x434 .................. 1198
USB VBUS Droop Control Interrupt Mask (USBVDCIM), offset 0x438 ............................. 1199
USB VBUS Droop Control Interrupt Status and Clear (USBVDCISC), offset 0x43C .......... 1200
USB ID Valid Detect Raw Interrupt Status (USBIDVRIS), offset 0x444 ............................. 1201
USB ID Valid Detect Interrupt Mask (USBIDVIM), offset 0x448 ........................................ 1202
USB ID Valid Detect Interrupt Status and Clear (USBIDVISC), offset 0x44C .................... 1203
USB DMA Select (USBDMASEL), offset 0x450 .............................................................. 1204
USB Peripheral Properties (USBPP), offset 0xFC0 ........................................................ 1206
Analog Comparators ................................................................................................................. 1207
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Analog Comparator Masked Interrupt Status (ACMIS), offset 0x000 ................................ 1214
Analog Comparator Raw Interrupt Status (ACRIS), offset 0x004 ..................................... 1215
Analog Comparator Interrupt Enable (ACINTEN), offset 0x008 ....................................... 1216
Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x010 ..................... 1217
Analog Comparator Status 0 (ACSTAT0), offset 0x020 ................................................... 1218
Analog Comparator Status 1 (ACSTAT1), offset 0x040 ................................................... 1218
Analog Comparator Status 2 (ACSTAT2), offset 0x060 ................................................... 1218
Analog Comparator Control 0 (ACCTL0), offset 0x024 ................................................... 1219
Analog Comparator Control 1 (ACCTL1), offset 0x044 ................................................... 1219
Analog Comparator Control 2 (ACCTL2), offset 0x064 ................................................... 1219
Analog Comparator Peripheral Properties (ACMPPP), offset 0xFC0 ................................ 1221
June 12, 2014
35
Texas Instruments-Production Data
Revision History
Revision History
The revision history table notes changes made between the indicated revisions of the
TM4C1237H6PZ data sheet.
Table 1. Revision History
Date
June 2014
March 2014
November 2013
Revision
Description
15842.2741 ■
In System Control Chapter, corrected description for MINSYSDIV bitfield in Device Capabilities 1
(DC1) legacy register.
■
In Timers chapter, removed erroneous references to TCACT bit field.
■
In SSI chapter, corrected that during idle periods the transmit data line SSInTx is tristated.
■
In Package Information appendix:
– Corrected Key to Part Numbers diagram.
– Moved Orderable Part Numbers table to addendum.
– Deleted Packaging Materials section and put into separate packaging document.
■
Additional minor data sheet clarifications and corrections.
15741.2722 ■
In the Internal Memory chapter, in the EEPROM section:
– Added section on soft reset handling.
– Added important information on EEPROM initialization and configuration.
■
In the DMA chapter, added information regarding interrupts and transfers from the UART or SSI
modules.
■
In the Hibernation chapter, noted that the EXTW bit is set in the HIBRIS register regardless of the
PINWEN setting in the HIBCTL register.
■
In the GPIO chapter:
– Corrected table GPIO Pins with Special Considerations.
– Added information on preventing false interrupts.
■
In the Timer chapter:
– Clarified initialization and configuration for Input-Edge Count mode.
– Clarified behavior of TnMIE and TnCINTD bits in the GPTM Timer n Mode (GPTMTnMR)
register.
■
In the USB chapter, added note to SUSPEND section regarding bus-powered devices.
■
In the Electrical Characteristics chapter:
– In table Reset Characteristics, clarified internal reset time parameter values.
– In table Hibernation Oscillator Input Characteristics, added parameter CINSE Input capacitance.
– In tables Hibernation Oscillator Input Characteristics and Main Oscillator Input Characteristics,
removed parameter C0 Crystal shunt capacitance.
– Updated table Crystal Parameters.
– In table GPIO Module Characteristics, added parameter CGPIO GPIO Digital Input Capacitance.
– Added table PWM Timing Characteristics.
■
In the Package Information appendix:
– Updated Orderable Devices section to reflect silicon revision 7 part numbers.
– Added Tape and Reel pin 1 location.
■
Additional minor data sheet clarifications and corrections.
15553.2700 ■
■
In System Control chapter, clarified PIOSC features and accuracy.
In Hibernation Module chapter:
36
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Table 1. Revision History (continued)
Date
Revision
Description
Corrected figures "Using a Crystal as the Hibernation Clock Source with a Single Battery Source"
and "Using a Regulator for Both VDD and VBAT".
–
Replaced RTC Trim tables with two new figures "Counter Behavior with a TRIM Value of 0x8002"
and "Counter Behavior with a TRIM Value of 0x7FFC".
–
Clarified Hibernation Data (HIBDATA) register description.
■
In Watchdog Timers chapter, clarified Watchdog Control (WDTCTL) register description.
■
In ADC chapter:
–
Clarified functionality when using an ADC digital comparator as a fault source.
–
Clarified signals used for ADC voltage reference.
–
Corrected VREF bit in ADC Control (ADCCTL) register from 2-bit field [1:0] to 1-bit field [0].
■
In UART chapter, clarified DMA operation.
■
In SSI chapter:
■
■
■
July 16, 2013
–
15033.2672 ■
–
Corrected timing guidelines in figures "Freescale SPI Frame Format (Continuous Transfer) with
SPO=1 and SPH=0" and "Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0".
–
Clarified SSI Initialization and Configuration.
–
Corrected bit 3 in SSI Control 1 (SSICR1) register from SOD (SSI Slave Mode Output Disable)
to reserved.
In Signal Tables chapter:
–
In Unused Signals table, corrected preferred and acceptable practices for RST pin.
–
Clarified GNDX pin description.
In Electrical Characteristics chapter:
–
In Power-On and Brown-Out Levels table, corrected TVDDC_RISE parameter min and max values.
–
In PIOSC Clock Characteristics table, clarified FPIOSC parameter values by defining values for
both factory calibration and recalibration. Also added PIOSC startup time parameter to table.
–
In Main Oscillator Specifications section, corrected minimum value for External load capacitance
on OSC0, OSC1 pins. Also added two 25-MHz crystals to Crystal Parameters table.
–
Corrected figure "Master Mode SSI Timing for SPI Frame Format (FRF=00), with SPH=1".
–
In I2C Characteristics table, clarified TDH data hold time parameter values by defining values
for both slave and master. In addition, added parameter I10 TDV data valid.
–
Modified figure "I2C Timing" to add new parameter I10.
In Packaging Information appendix, added Packaging Materials figures.
In the Electrical Characteristics chapter:
–
Added maximum junction temperature to Maximum Ratings table. Also moved Unpowered
storage temperature range parameter to this table.
–
In SSI Characteristics table, corrected values for TRXDMS, TRXDMH, and TRXDSSU. Also clarified
footnotes to table.
June 12, 2014
37
Texas Instruments-Production Data
Revision History
Table 1. Revision History (continued)
Date
Revision
Description
–
■
July 2013
14995.2667 ■
■
Corrected parameter numbers in figures "Master Mode SSI Timing for SPI Frame Format
(FRF=00), with SPH=1" and "Slave Mode SSI Timing for SPI Frame Format (FRF=00), with
SPH=1".
Additional minor data sheet clarifications and corrections.
In the System Control chapter, corrected resets for bits [7:4] in System Properties (SYSPROP)
register.
In the Hibernation Module chapter:
–
Corrected figures "Using a Crystal as the Hibernation Clock Source with a Single Battery Source"
and "Using a Dedicated Oscillator as the Hibernation Clock Source with VDD3ON Mode".
–
Clarified when the Hibernation module can generate interrupts.
■
In the Internal Memory chapter, removed the INVPL bit from the EEPROM Done Status (EEDONE)
register.
■
In the uDMA chapter, in the µDMA Channel Assignments table, corrected names of timers 6-11 to
wide timers 0-5.
■
In the Timers chapter:
–
Clarified that the timer must be configured for one-shot or periodic time-out mode to produce
an ADC trigger assertion and that the GPTM does not generate triggers for match, compare
events or compare match events.
–
Added a step in the RTC Mode initialization and configuration: If the timer has been operating
in a different mode prior to this, clear any residual set bits in the GPTM Timer n Mode
(GPTMTnMR) register before reconfiguring.
■
In the Watchdog Timer chapter, added a note that locking the watchdog registers using the
WDTLOCK register does not affect the WDTICR register and allows interrupts to always be serviced.
■
In the SSI chapter, clarified note in Bit Rate Generation section to indicate that the System Clock
or the PIOSC can be used as the source for SSIClk. Also corrected to indicate maximum SSIClk
limit in SSI slave mode as well as the fact that SYSCLK has to be at least 12 times that of SSICLk.
■
In the Electrical Characteristics chapter:
–
Moved Maximum Ratings and ESD Absolute Maximum Ratings to the front of the chapter.
–
Added VBATRMP parameter to Maximum Ratings and Hibernation Module Battery Characteristics
tables.
–
Added ambient and junction temperatures to Temperature Characteristics table and clarified
values in Thermal Characteristics table.
–
Added clarifying footnote to VVDD_POK parameter in Power-On and Brown-Out Levels table.
–
Corrected GPIO Package Side Assignments table.
–
In the Flash Memory and EEPROM Characteristics tables, added a parameter for page/mass
erase times for 10k cycles and corrected existing values for all page and mass erase parameters.
–
Corrected DNL max value in ADC Electrical Characteristics table.
–
In the SSI Characteristics table, changed parameter names for S7-S14, provided a max number
instead of a min for S7, and corrected values for S9-S14.
–
Replaced figure "SSI Timing for SPI Frame Format (FRF=00), with SPH=1" with two figures,
one for Master Mode and one for Slave Mode.
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Table 1. Revision History (continued)
Date
Revision
Description
–
Updated and added values to the table Table 22-40 on page 1298.
■
In the Package Information appendix, moved orderable devices table from addendum to appendix,
clarified part markings and moved packaging diagram from addendum to appendix.
■
Additional minor data sheet clarifications and corrections.
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About This Document
About This Document
This data sheet provides reference information for the TM4C1237H6PZ microcontroller, describing
the functional blocks of the system-on-chip (SoC) device designed around the ARM® Cortex™-M4F
core.
Audience
This manual is intended for system software developers, hardware designers, and application
developers.
About This Manual
This document is organized into sections that correspond to each major feature.
Related Documents
The following related documents are available on the Tiva™ C Series web site at
http://www.ti.com/tiva-c:
■ Tiva™ C Series TM4C123x Silicon Errata (literature number SPMZ849)
■ TivaWare™ Boot Loader for C Series User's Guide (literature number SPMU301)
■ TivaWare™ Graphics Library for C Series User's Guide (literature number SPMU300)
■ TivaWare™ for C Series Release Notes (literature number SPMU299)
■ TivaWare™ Peripheral Driver Library for C Series User's Guide (literature number SPMU298)
■ TivaWare™ USB Library for C Series User's Guide (literature number SPMU297)
■ Tiva™ C Series TM4C123x ROM User’s Guide (literature number SPMU367)
The following related documents may also be useful:
■ ARM® Cortex™-M4 Errata (literature number SPMZ637)
■ ARM® Cortex™-M4 Technical Reference Manual
■ ARM® Debug Interface V5 Architecture Specification
■ ARM® Embedded Trace Macrocell Architecture Specification
■ Cortex™-M4 instruction set chapter in the ARM® Cortex™-M4 Devices Generic User Guide
(literature number ARM DUI 0553A)
■ IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture
This documentation list was current as of publication date. Please check the web site for additional
documentation, including application notes and white papers.
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Documentation Conventions
This document uses the conventions shown in Table 2 on page 41.
Table 2. Documentation Conventions
Notation
Meaning
General Register Notation
REGISTER
APB registers are indicated in uppercase bold. For example, PBORCTL is the Power-On and
Brown-Out Reset Control register. If a register name contains a lowercase n, it represents more
than one register. For example, SRCRn represents any (or all) of the three Software Reset Control
registers: SRCR0, SRCR1 , and SRCR2.
bit
A single bit in a register.
bit field
Two or more consecutive and related bits.
offset 0xnnn
A hexadecimal increment to a register's address, relative to that module's base address as specified
in Table 2-4 on page 87.
Register N
Registers are numbered consecutively throughout the document to aid in referencing them. The
register number has no meaning to software.
reserved
Register bits marked reserved are reserved for future use. In most cases, reserved bits are set to
0; however, user software should not rely on the value of a reserved bit. To provide software
compatibility with future products, the value of a reserved bit should be preserved across a
read-modify-write operation.
yy:xx
The range of register bits inclusive from xx to yy. For example, 31:15 means bits 15 through 31 in
that register.
Register Bit/Field
Types
This value in the register bit diagram indicates whether software running on the controller can
change the value of the bit field.
RC
Software can read this field. The bit or field is cleared by hardware after reading the bit/field.
RO
Software can read this field. Always write the chip reset value.
RW
Software can read or write this field.
RWC
Software can read or write this field. Writing to it with any value clears the register.
RW1C
Software can read or write this field. A write of a 0 to a W1C bit does not affect the bit value in the
register. A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged.
This register type is primarily used for clearing interrupt status bits where the read operation provides
the interrupt status and the write of the read value clears only the interrupts being reported at the
time the register was read.
RW1S
Software can read or write a 1 to this field. A write of a 0 to a RW1S bit does not affect the bit value
in the register.
W1C
Software can write this field. A write of a 0 to a W1C bit does not affect the bit value in the register.
A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. A
read of the register returns no meaningful data.
This register is typically used to clear the corresponding bit in an interrupt register.
WO
Only a write by software is valid; a read of the register returns no meaningful data.
Register Bit/Field
Reset Value
This value in the register bit diagram shows the bit/field value after any reset, unless noted.
0
Bit cleared to 0 on chip reset.
1
Bit set to 1 on chip reset.
-
Nondeterministic.
Pin/Signal Notation
[]
Pin alternate function; a pin defaults to the signal without the brackets.
pin
Refers to the physical connection on the package.
signal
Refers to the electrical signal encoding of a pin.
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About This Document
Table 2. Documentation Conventions (continued)
Notation
Meaning
assert a signal
Change the value of the signal from the logically False state to the logically True state. For active
High signals, the asserted signal value is 1 (High); for active Low signals, the asserted signal value
is 0 (Low). The active polarity (High or Low) is defined by the signal name (see SIGNAL and SIGNAL
below).
deassert a signal
Change the value of the signal from the logically True state to the logically False state.
SIGNAL
Signal names are in uppercase and in the Courier font. An overbar on a signal name indicates that
it is active Low. To assert SIGNAL is to drive it Low; to deassert SIGNAL is to drive it High.
SIGNAL
Signal names are in uppercase and in the Courier font. An active High signal has no overbar. To
assert SIGNAL is to drive it High; to deassert SIGNAL is to drive it Low.
Numbers
X
An uppercase X indicates any of several values is allowed, where X can be any legal pattern. For
example, a binary value of 0X00 can be either 0100 or 0000, a hex value of 0xX is 0x0 or 0x1, and
so on.
0x
Hexadecimal numbers have a prefix of 0x. For example, 0x00FF is the hexadecimal number FF.
All other numbers within register tables are assumed to be binary. Within conceptual information,
binary numbers are indicated with a b suffix, for example, 1011b, and decimal numbers are written
without a prefix or suffix.
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1
Architectural Overview
®
Texas Instrument's Tiva™ C Series microcontrollers provide designers a high-performance ARM
Cortex™-M-based architecture with a broad set of integration capabilities and a strong ecosystem
of software and development tools. Targeting performance and flexibility, the Tiva™ C Series
architecture offers a 80 MHz Cortex-M with FPU, a variety of integrated memories and multiple
programmable GPIO. Tiva™ C Series devices offer consumers compelling cost-effective solutions
by integrating application-specific peripherals and providing a comprehensive library of software
tools which minimize board costs and design-cycle time. Offering quicker time-to-market and cost
savings, the Tiva™ C Series microcontrollers are the leading choice in high-performance 32-bit
applications.
This chapter contains an overview of the Tiva™ C Series microcontrollers as well as details on the
TM4C1237H6PZ microcontroller:
■
■
■
■
■
■
1.1
“Tiva™ C Series Overview” on page 43
“TM4C1237H6PZ Microcontroller Overview” on page 44
“TM4C1237H6PZ Microcontroller Features” on page 46
“TM4C1237H6PZ Microcontroller Hardware Details” on page 62
“Kits” on page 63
“Support Information” on page 63
Tiva™ C Series Overview
The Tiva™ C Series ARM Cortex-M4 microcontrollers provide top performance and advanced
integration. The product family is positioned for cost-conscious applications requiring significant
control processing and connectivity capabilities such as:
■
■
■
■
■
■
■
■
■
■
■
Low power, hand-held smart devices
Gaming equipment
Home and commercial site monitoring and control
Motion control
Medical instrumentation
Test and measurement equipment
Factory automation
Fire and security
Smart Energy/Smart Grid solutions
Intelligent lighting control
Transportation
For applications requiring extreme conservation of power, the TM4C1237H6PZ microcontroller
features a battery-backed Hibernation module to efficiently power down the TM4C1237H6PZ to a
low-power state during extended periods of inactivity. With a power-up/power-down sequencer, a
real-time counter (RTC), multiple wake-from-hibernate options, and dedicated battery-backed
memory, the Hibernation module positions the TM4C1237H6PZ microcontroller perfectly for battery
applications.
In addition, the TM4C1237H6PZ microcontroller offers the advantages of ARM's widely available
development tools, System-on-Chip (SoC) infrastructure IP applications, and a large user community.
Additionally, the microcontroller uses ARM's Thumb®-compatible Thumb-2 instruction set to reduce
memory requirements and, thereby, cost. Finally, much of the TM4C1237H6PZ microcontroller code
is compatible to the Tiva™ C Series product line, providing flexibility across designs.
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Architectural Overview
Texas Instruments offers a complete solution to get to market quickly, with evaluation and
development boards, white papers and application notes, an easy-to-use peripheral driver library,
and a strong support, sales, and distributor network.
1.2
TM4C1237H6PZ Microcontroller Overview
The TM4C1237H6PZ microcontroller combines complex integration and high performance with the
features shown in Table 1-1.
Table 1-1. TM4C1237H6PZ Microcontroller Features
Feature
Description
Performance
Core
ARM Cortex-M4F processor core
Performance
80-MHz operation; 100 DMIPS performance
Flash
256 KB single-cycle Flash memory
System SRAM
32 KB single-cycle SRAM
EEPROM
2KB of EEPROM
Internal ROM
Internal ROM loaded with TivaWare™ for C Series software
Security
Communication Interfaces
Universal Asynchronous Receivers/Transmitter (UART) Eight UARTs
Synchronous Serial Interface (SSI)
Four SSI modules
Inter-Integrated Circuit (I2C)
Six I2C modules with four transmission speeds including high-speed
mode
Controller Area Network (CAN)
CAN 2.0 A/B controllers
Universal Serial Bus (USB)
USB 2.0 OTG/Host/Device
System Integration
Micro Direct Memory Access (µDMA)
ARM® PrimeCell® 32-channel configurable μDMA controller
General-Purpose Timer (GPTM)
Six 16/32-bit GPTM blocks and six 32/64-bit Wide GPTM blocks
Watchdog Timer (WDT)
Two watchdog timers
Hibernation Module (HIB)
Low-power battery-backed Hibernation module
General-Purpose Input/Output (GPIO)
10 physical GPIO blocks
Analog Support
Analog-to-Digital Converter (ADC)
Two 12-bit ADC modules, each with a maximum sample rate of one
million samples/second
Analog Comparator Controller
Three independent integrated analog comparators
Digital Comparator
16 digital comparators
JTAG and Serial Wire Debug (SWD)
One JTAG module with integrated ARM SWD
Package Information
Package
100-pin LQFP
Operating Range (Ambient)
Industrial (-40°C to 85°C) temperature range
Figure 1-1 on page 45 shows the features on the TM4C1237H6PZ microcontroller. Note that there
are two on-chip buses that connect the core to the peripherals. The Advanced Peripheral Bus (APB)
bus is the legacy bus. The Advanced High-Performance Bus (AHB) bus provides better back-to-back
access performance than the APB bus.
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Figure 1-1. Tiva™ TM4C1237H6PZ Microcontroller High-Level Block Diagram
JTAG/SWD
ARM®
Cortex™-M4F
ROM
(80MHz)
System
Control and
Clocks
(w/ Precis. Osc.)
ETM
FPU
NVIC
MPU
Boot Loader
DriverLib
AES & CRC
Flash
(256KB)
DCode bus
ICode bus
System Bus
TM4C1237H6PZ
Bus Matrix
SRAM
(32KB)
SYSTEM PERIPHERALS
EEPROM
(2K)
Hibernation
Module
GPIOs
(69)
GeneralPurpose
Timer (12)
USB OTG
(FS PHY)
SSI
(4)
Advanced Peripheral Bus (APB)
Watchdog
Timer
(2)
Advanced High-Performance Bus (AHB)
DMA
SERIAL PERIPHERALS
UART
(8)
I2C
(6)
CAN
Controller
(1)
ANALOG PERIPHERALS
Analog
Comparator
(3)
12- Bit ADC
Channels
(22)
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1.3
TM4C1237H6PZ Microcontroller Features
The TM4C1237H6PZ microcontroller component features and general function are discussed in
more detail in the following section.
1.3.1
ARM Cortex-M4F Processor Core
All members of the Tiva™ C Series, including the TM4C1237H6PZ microcontroller, are designed
around an ARM Cortex-M processor core. The ARM Cortex-M processor provides the core for a
high-performance, low-cost platform that meets the needs of minimal memory implementation,
reduced pin count, and low power consumption, while delivering outstanding computational
performance and exceptional system response to interrupts.
1.3.1.1
Processor Core (see page 64)
■ 32-bit ARM Cortex-M4F architecture optimized for small-footprint embedded applications
■ 80-MHz operation; 100 DMIPS performance
■ Outstanding processing performance combined with fast interrupt handling
■ Thumb-2 mixed 16-/32-bit instruction set delivers the high performance expected of a 32-bit
ARM core in a compact memory size usually associated with 8- and 16-bit devices, typically in
the range of a few kilobytes of memory for microcontroller-class applications
– Single-cycle multiply instruction and hardware divide
– Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined
peripheral control
– Unaligned data access, enabling data to be efficiently packed into memory
■ IEEE754-compliant single-precision Floating-Point Unit (FPU)
■ 16-bit SIMD vector processing unit
■ Fast code execution permits slower processor clock or increases sleep mode time
■ Harvard architecture characterized by separate buses for instruction and data
■ Efficient processor core, system and memories
■ Hardware division and fast digital-signal-processing orientated multiply accumulate
■ Saturating arithmetic for signal processing
■ Deterministic, high-performance interrupt handling for time-critical applications
■ Memory protection unit (MPU) to provide a privileged mode for protected operating system
functionality
■ Enhanced system debug with extensive breakpoint and trace capabilities
■ Serial Wire Debug and Serial Wire Trace reduce the number of pins required for debugging and
tracing
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■ Migration from the ARM7™ processor family for better performance and power efficiency
■ Optimized for single-cycle Flash memory usage up to specific frequencies; see “Internal
Memory” on page 509 for more information.
■ Ultra-low power consumption with integrated sleep modes
1.3.1.2
System Timer (SysTick) (see page 118)
ARM Cortex-M4F includes an integrated system timer, SysTick. SysTick provides a simple, 24-bit,
clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter
can be used in several different ways, for example:
■ An RTOS tick timer that fires at a programmable rate (for example, 100 Hz) and invokes a SysTick
routine
■ A high-speed alarm timer using the system clock
■ A variable rate alarm or signal timer—the duration is range-dependent on the reference clock
used and the dynamic range of the counter
■ A simple counter used to measure time to completion and time used
■ An internal clock-source control based on missing/meeting durations
1.3.1.3
Nested Vectored Interrupt Controller (NVIC) (see page 119)
The TM4C1237H6PZ controller includes the ARM Nested Vectored Interrupt Controller (NVIC). The
NVIC and Cortex-M4F prioritize and handle all exceptions in Handler Mode. The processor state is
automatically stored to the stack on an exception and automatically restored from the stack at the
end of the Interrupt Service Routine (ISR). The interrupt vector is fetched in parallel to the state
saving, enabling efficient interrupt entry. The processor supports tail-chaining, meaning that
back-to-back interrupts can be performed without the overhead of state saving and restoration.
Software can set eight priority levels on 7 exceptions (system handlers) and 72 interrupts.
■ Deterministic, fast interrupt processing: always 12 cycles, or just 6 cycles with tail-chaining (these
values reflect no FPU stacking)
■ External non-maskable interrupt signal (NMI) available for immediate execution of NMI handler
for safety critical applications
■ Dynamically reprioritizable interrupts
■ Exceptional interrupt handling via hardware implementation of required register manipulations
1.3.1.4
System Control Block (SCB) (see page 120)
The SCB provides system implementation information and system control, including configuration,
control, and reporting of system exceptions.
1.3.1.5
Memory Protection Unit (MPU) (see page 120)
The MPU supports the standard ARM7 Protected Memory System Architecture (PMSA) model. The
MPU provides full support for protection regions, overlapping protection regions, access permissions,
and exporting memory attributes to the system.
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1.3.1.6
Floating-Point Unit (FPU) (see page 125)
The FPU fully supports single-precision add, subtract, multiply, divide, multiply and accumulate,
and square root operations. It also provides conversions between fixed-point and floating-point data
formats, and floating-point constant instructions.
■ 32-bit instructions for single-precision (C float) data-processing operations
■ Combined multiply and accumulate instructions for increased precision (Fused MAC)
■ Hardware support for conversion, addition, subtraction, multiplication with optional accumulate,
division, and square-root
■ Hardware support for denormals and all IEEE rounding modes
■ 32 dedicated 32-bit single-precision registers, also addressable as 16 double-word registers
■ Decoupled three stage pipeline
1.3.2
On-Chip Memory
The TM4C1237H6PZ microcontroller is integrated with the following set of on-chip memory and
features:
■ 32 KB single-cycle SRAM
■ 256 KB Flash memory
■ 2KB EEPROM
■ Internal ROM loaded with TivaWare™ for C Series software:
– TivaWare™ Peripheral Driver Library
– TivaWare Boot Loader
– Advanced Encryption Standard (AES) cryptography tables
– Cyclic Redundancy Check (CRC) error detection functionality
1.3.2.1
SRAM (see page 510)
The TM4C1237H6PZ microcontroller provides 32 KB of single-cycle on-chip SRAM. The internal
SRAM of the device is located at offset 0x2000.0000 of the device memory map.
Because read-modify-write (RMW) operations are very time consuming, ARM has introduced
bit-banding technology in the Cortex-M4F processor. With a bit-band-enabled processor, certain
regions in the memory map (SRAM and peripheral space) can use address aliases to access
individual bits in a single, atomic operation.
Data can be transferred to and from SRAM by the following masters:
■ µDMA
■ USB
1.3.2.2
Flash Memory (see page 513)
The TM4C1237H6PZ microcontroller provides 256 KB of single-cycle on-chip Flash memory. The
Flash memory is organized as a set of 1-KB blocks that can be individually erased. Erasing a block
causes the entire contents of the block to be reset to all 1s. These blocks are paired into a set of
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2-KB blocks that can be individually protected. The blocks can be marked as read-only or
execute-only, providing different levels of code protection. Read-only blocks cannot be erased or
programmed, protecting the contents of those blocks from being modified. Execute-only blocks
cannot be erased or programmed, and can only be read by the controller instruction fetch mechanism,
protecting the contents of those blocks from being read by either the controller or by a debugger.
1.3.2.3
ROM (see page 511)
The TM4C1237H6PZ ROM is preprogrammed with the following software and programs:
■ TivaWare Peripheral Driver Library
■ TivaWare Boot Loader
■ Advanced Encryption Standard (AES) cryptography tables
■ Cyclic Redundancy Check (CRC) error-detection functionality
The TivaWare Peripheral Driver Library is a royalty-free software library for controlling on-chip
peripherals with a boot-loader capability. The library performs both peripheral initialization and
control functions, with a choice of polled or interrupt-driven peripheral support. In addition, the library
is designed to take full advantage of the stellar interrupt performance of the ARM Cortex-M4F core.
No special pragmas or custom assembly code prologue/epilogue functions are required. For
applications that require in-field programmability, the royalty-free TivaWare Boot Loader can act as
an application loader and support in-field firmware updates.
The Advanced Encryption Standard (AES) is a publicly defined encryption standard used by the
U.S. Government. AES is a strong encryption method with reasonable performance and size. In
addition, it is fast in both hardware and software, is fairly easy to implement, and requires little
memory. The Texas Instruments encryption package is available with full source code, and is based
on Lesser General Public License (LGPL) source. An LGPL means that the code can be used within
an application without any copyleft implications for the application (the code does not automatically
become open source). Modifications to the package source, however, must be open source.
CRC (Cyclic Redundancy Check) is a technique to validate a span of data has the same contents
as when previously checked. This technique can be used to validate correct receipt of messages
(nothing lost or modified in transit), to validate data after decompression, to validate that Flash
memory contents have not been changed, and for other cases where the data needs to be validated.
A CRC is preferred over a simple checksum (for example, XOR all bits) because it catches changes
more readily.
1.3.2.4
EEPROM (see page 519)
The TM4C1237H6PZ microcontroller includes an EEPROM with the following features:
■ 2Kbytes of memory accessible as 512 32-bit words
■ 32 blocks of 16 words (64 bytes) each
■ Built-in wear leveling
■ Access protection per block
■ Lock protection option for the whole peripheral as well as per block using 32-bit to 96-bit unlock
codes (application selectable)
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■ Interrupt support for write completion to avoid polling
■ Endurance of 500K writes (when writing at fixed offset in every alternate page in circular fashion)
to 15M operations (when cycling through two pages ) per each 2-page block.
1.3.3
Serial Communications Peripherals
The TM4C1237H6PZ controller supports both asynchronous and synchronous serial communications
with:
■ CAN 2.0 A/B controller
■ USB 2.0 OTG/Host/Device
■ Eight UARTs with IrDA, 9-bit and ISO 7816 support.
■ Six I2C modules with four transmission speeds including high-speed mode
■ Four Synchronous Serial Interface modules (SSI)
The following sections provide more detail on each of these communications functions.
1.3.3.1
Controller Area Network (CAN) (see page 1041)
Controller Area Network (CAN) is a multicast shared serial-bus standard for connecting electronic
control units (ECUs). CAN was specifically designed to be robust in electromagnetically noisy
environments and can utilize a differential balanced line like RS-485 or twisted-pair wire. Originally
created for automotive purposes, it is now used in many embedded control applications (for example,
industrial or medical). Bit rates up to 1 Mbps are possible at network lengths below 40 meters.
Decreased bit rates allow longer network distances (for example, 125 Kbps at 500m).
A transmitter sends a message to all CAN nodes (broadcasting). Each node decides on the basis
of the identifier received whether it should process the message. The identifier also determines the
priority that the message enjoys in competition for bus access. Each CAN message can transmit
from 0 to 8 bytes of user information.
The TM4C1237H6PZ microcontroller includes one CAN unit with the following features:
■ CAN protocol version 2.0 part A/B
■ Bit rates up to 1 Mbps
■ 32 message objects with individual identifier masks
■ Maskable interrupt
■ Disable Automatic Retransmission mode for Time-Triggered CAN (TTCAN) applications
■ Programmable loopback mode for self-test operation
■ Programmable FIFO mode enables storage of multiple message objects
■ Gluelessly attaches to an external CAN transceiver through the CANnTX and CANnRX signals
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1.3.3.2
Universal Serial Bus (USB) (see page 1091)
Universal Serial Bus (USB) is a serial bus standard designed to allow peripherals to be connected
and disconnected using a standardized interface without rebooting the system.
The TM4C1237H6PZ microcontroller supports three configurations in USB 2.0 full and low speed:
USB Device, USB Host, and USB On-The-Go (negotiated on-the-go as host or device when
connected to other USB-enabled systems).
The USB module has the following features:
■ Complies with USB-IF (Implementer's Forum) certification standards
■ USB 2.0 full-speed (12 Mbps) and low-speed (1.5 Mbps) operation with integrated PHY
■ 4 transfer types: Control, Interrupt, Bulk, and Isochronous
■ 16 endpoints
– 1 dedicated control IN endpoint and 1 dedicated control OUT endpoint
– 7 configurable IN endpoints and 7 configurable OUT endpoints
■ 4 KB dedicated endpoint memory: one endpoint may be defined for double-buffered 1023-byte
isochronous packet size
■ VBUS droop and valid ID detection and interrupt
■ Efficient transfers using Micro Direct Memory Access Controller (µDMA)
– Separate channels for transmit and receive for up to three IN endpoints and three OUT
endpoints
– Channel requests asserted when FIFO contains required amount of data
1.3.3.3
UART (see page 884)
A Universal Asynchronous Receiver/Transmitter (UART) is an integrated circuit used for RS-232C
serial communications, containing a transmitter (parallel-to-serial converter) and a receiver
(serial-to-parallel converter), each clocked separately.
The TM4C1237H6PZ microcontroller includes eight fully programmable 16C550-type UARTs.
Although the functionality is similar to a 16C550 UART, this UART design is not register compatible.
The UART can generate individually masked interrupts from the Rx, Tx, modem flow control, modem
status, and error conditions. The module generates a single combined interrupt when any of the
interrupts are asserted and are unmasked.
The eight UARTs have the following features:
■ Programmable baud-rate generator allowing speeds up to 5 Mbps for regular speed (divide by
16) and 10 Mbps for high speed (divide by 8)
■ Separate 16x8 transmit (TX) and receive (RX) FIFOs to reduce CPU interrupt service loading
■ Programmable FIFO length, including 1-byte deep operation providing conventional
double-buffered interface
■ FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8
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■ Standard asynchronous communication bits for start, stop, and parity
■ Line-break generation and detection
■ Fully programmable serial interface characteristics
– 5, 6, 7, or 8 data bits
– Even, odd, stick, or no-parity bit generation/detection
– 1 or 2 stop bit generation
■ IrDA serial-IR (SIR) encoder/decoder providing
– Programmable use of IrDA Serial Infrared (SIR) or UART input/output
– Support of IrDA SIR encoder/decoder functions for data rates up to 115.2 Kbps half-duplex
– Support of normal 3/16 and low-power (1.41-2.23 μs) bit durations
– Programmable internal clock generator enabling division of reference clock by 1 to 256 for
low-power mode bit duration
■ Support for communication with ISO 7816 smart cards
■ Modem flow control and status (on UART1)
■ EIA-485 9-bit support
■ Standard FIFO-level and End-of-Transmission interrupts
■ Efficient transfers using Micro Direct Memory Access Controller (µDMA)
– Separate channels for transmit and receive
– Receive single request asserted when data is in the FIFO; burst request asserted at
programmed FIFO level
– Transmit single request asserted when there is space in the FIFO; burst request asserted at
programmed FIFO level
1.3.3.4
I2C (see page 990)
The Inter-Integrated Circuit (I2C) bus provides bi-directional data transfer through a two-wire design
(a serial data line SDA and a serial clock line SCL). The I2C bus interfaces to external I2C devices
such as serial memory (RAMs and ROMs), networking devices, LCDs, tone generators, and so on.
The I2C bus may also be used for system testing and diagnostic purposes in product development
and manufacture.
Each device on the I2C bus can be designated as either a master or a slave. I2C module supports
both sending and receiving data as either a master or a slave and can operate simultaneously as
both a master and a slave. Both the I2C master and slave can generate interrupts.
The TM4C1237H6PZ microcontroller includes six I2C modules with the following features:
■ Devices on the I2C bus can be designated as either a master or a slave
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– Supports both transmitting and receiving data as either a master or a slave
– Supports simultaneous master and slave operation
■ Four I2C modes
– Master transmit
– Master receive
– Slave transmit
– Slave receive
■ Four transmission speeds:
– Standard (100 Kbps)
– Fast-mode (400 Kbps)
– Fast-mode plus (1 Mbps)
– High-speed mode (3.33 Mbps)
■ Clock low timeout interrupt
■ Dual slave address capability
■ Glitch suppression
■ Master and slave interrupt generation
– Master generates interrupts when a transmit or receive operation completes (or aborts due
to an error)
– Slave generates interrupts when data has been transferred or requested by a master or when
a START or STOP condition is detected
■ Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing
mode
1.3.3.5
SSI (see page 945)
Synchronous Serial Interface (SSI) is a four-wire bi-directional communications interface that converts
data between parallel and serial. The SSI module performs serial-to-parallel conversion on data
received from a peripheral device, and parallel-to-serial conversion on data transmitted to a peripheral
device. The SSI module can be configured as either a master or slave device. As a slave device,
the SSI module can also be configured to disable its output, which allows a master device to be
coupled with multiple slave devices. The TX and RX paths are buffered with separate internal FIFOs.
The SSI module also includes a programmable bit rate clock divider and prescaler to generate the
output serial clock derived from the SSI module's input clock. Bit rates are generated based on the
input clock and the maximum bit rate is determined by the connected peripheral.
The TM4C1237H6PZ microcontroller includes four SSI modules with the following features:
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■ Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments
synchronous serial interfaces
■ Master or slave operation
■ Programmable clock bit rate and prescaler
■ Separate transmit and receive FIFOs, each 16 bits wide and 8 locations deep
■ Programmable data frame size from 4 to 16 bits
■ Internal loopback test mode for diagnostic/debug testing
■ Standard FIFO-based interrupts and End-of-Transmission interrupt
■ Efficient transfers using Micro Direct Memory Access Controller (µDMA)
– Separate channels for transmit and receive
– Receive single request asserted when data is in the FIFO; burst request asserted when FIFO
contains 4 entries
– Transmit single request asserted when there is space in the FIFO; burst request asserted
when four or more entries are available to be written in the FIFO
1.3.4
System Integration
The TM4C1237H6PZ microcontroller provides a variety of standard system functions integrated
into the device, including:
■ Direct Memory Access Controller (DMA)
■ System control and clocks including on-chip precision 16-MHz oscillator
■ Six 32-bit timers (up to twelve 16-bit)
■ Six wide 64-bit timers (up to twelve 32-bit)
■ Twelve 32/64-bit Capture Compare PWM (CCP) pins
■ Lower-power battery-backed Hibernation module
■ Real-Time Clock in Hibernation module
■ Two Watchdog Timers
– One timer runs off the main oscillator
– One timer runs off the precision internal oscillator
■ Up to 69 GPIOs, depending on configuration
– Highly flexible pin muxing allows use as GPIO or one of several peripheral functions
– Independently configurable to 2-, 4- or 8-mA drive capability
– Up to 4 GPIOs can have 18-mA drive capability
The following sections provide more detail on each of these functions.
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1.3.4.1
Direct Memory Access (see page 570)
The TM4C1237H6PZ microcontroller includes a Direct Memory Access (DMA) controller, known as
micro-DMA (μDMA). The μDMA controller provides a way to offload data transfer tasks from the
Cortex-M4F processor, allowing for more efficient use of the processor and the available bus
bandwidth. The μDMA controller can perform transfers between memory and peripherals. It has
dedicated channels for each supported on-chip module and can be programmed to automatically
perform transfers between peripherals and memory as the peripheral is ready to transfer more data.
The μDMA controller provides the following features:
®
■ ARM PrimeCell 32-channel configurable µDMA controller
■ Support for memory-to-memory, memory-to-peripheral, and peripheral-to-memory in multiple
transfer modes
– Basic for simple transfer scenarios
– Ping-pong for continuous data flow
– Scatter-gather for a programmable list of up to 256 arbitrary transfers initiated from a single
request
■ Highly flexible and configurable channel operation
– Independently configured and operated channels
– Dedicated channels for supported on-chip modules
– Flexible channel assignments
– One channel each for receive and transmit path for bidirectional modules
– Dedicated channel for software-initiated transfers
– Per-channel configurable priority scheme
– Optional software-initiated requests for any channel
■ Two levels of priority
■ Design optimizations for improved bus access performance between µDMA controller and the
processor core
– µDMA controller access is subordinate to core access
– RAM striping
– Peripheral bus segmentation
■ Data sizes of 8, 16, and 32 bits
■ Transfer size is programmable in binary steps from 1 to 1024
■ Source and destination address increment size of byte, half-word, word, or no increment
■ Maskable peripheral requests
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■ Interrupt on transfer completion, with a separate interrupt per channel
1.3.4.2
System Control and Clocks (see page 207)
System control determines the overall operation of the device. It provides information about the
device, controls power-saving features, controls the clocking of the device and individual peripherals,
and handles reset detection and reporting.
■ Device identification information: version, part number, SRAM size, Flash memory size, and so
on
■ Power control
– On-chip fixed Low Drop-Out (LDO) voltage regulator
– Hibernation module handles the power-up/down 3.3 V sequencing and control for the core
digital logic and analog circuits
– Low-power options for microcontroller: Sleep and Deep-Sleep modes with clock gating
– Low-power options for on-chip modules: software controls shutdown of individual peripherals
and memory
– 3.3-V supply brown-out detection and reporting via interrupt or reset
■ Multiple clock sources for microcontroller system clock. The following clock sources are provided
to the TM4C1237H6PZ microcontroller:
– Precision Internal Oscillator (PIOSC) providing a 16-MHz frequency
• 16 MHz ±3% across temperature and voltage
• Can be recalibrated with 7-bit trim resolution to achieve better accuracy (16 MHz ±1%)
• Software power down control for low power modes
– Main Oscillator (MOSC): A frequency-accurate clock source by one of two means: an external
single-ended clock source is connected to the OSC0 input pin, or an external crystal is
connected across the OSC0 input and OSC1 output pins.
– Low Frequency Internal Oscillator (LFIOSC): On-chip resource used during power-saving
modes
– Hibernate RTC oscillator (RTCOSC) clock that can be configured to be the 32.768-kHz
external oscillator source from the Hibernation (HIB) module or the HIB Low Frequency clock
source (HIB LFIOSC), which is located within the Hibernation Module.
■ Flexible reset sources
– Power-on reset (POR)
– Reset pin assertion
– Brown-out reset (BOR) detector alerts to system power drops
– Software reset
– Watchdog timer reset
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– MOSC failure
1.3.4.3
Programmable Timers (see page 693)
Programmable timers can be used to count or time external events that drive the Timer input pins.
Each 16/32-bit GPTM block provides two 16-bit timers/counters that can be configured to operate
independently as timers or event counters, or configured to operate as one 32-bit timer or one 32-bit
Real-Time Clock (RTC). Each 32/64-bit Wide GPTM block provides two 32-bit timers/counters that
can be configured to operate independently as timersor event counters, or configured to operate
as one 64-bit timer or one 64-bit Real-Time Clock (RTC). Timers can also be used to trigger
analog-to-digital (ADC) conversions and DMA transfers.
The General-Purpose Timer Module (GPTM) contains six 16/32-bit GPTM blocks and six 32/64-bit
Wide GPTM blocks with the following functional options:
■ 16/32-bit operating modes:
– 16- or 32-bit programmable one-shot timer
– 16- or 32-bit programmable periodic timer
– 16-bit general-purpose timer with an 8-bit prescaler
– 32-bit Real-Time Clock (RTC) when using an external 32.768-KHz clock as the input
– 16-bit input-edge count- or time-capture modes with an 8-bit prescaler
– 16-bit PWM mode with an 8-bit prescaler and software-programmable output inversion of the
PWM signal
■ 32/64-bit operating modes:
– 32- or 64-bit programmable one-shot timer
– 32- or 64-bit programmable periodic timer
– 32-bit general-purpose timer with a 16-bit prescaler
– 64-bit Real-Time Clock (RTC) when using an external 32.768-KHz clock as the input
– 32-bit input-edge count- or time-capture modes with a16-bit prescaler
– 32-bit PWM mode with a 16-bit prescaler and software-programmable output inversion of the
PWM signal
■ Count up or down
■ Twelve 16/32-bit Capture Compare PWM pins (CCP)
■ Twelve 32/64-bit Capture Compare PWM pins (CCP)
■ Daisy chaining of timer modules to allow a single timer to initiate multiple timing events
■ Timer synchronization allows selected timers to start counting on the same clock cycle
■ ADC event trigger
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Architectural Overview
■ User-enabled stalling when the microcontroller asserts CPU Halt flag during debug (excluding
RTC mode)
■ Ability to determine the elapsed time between the assertion of the timer interrupt and entry into
the interrupt service routine
■ Efficient transfers using Micro Direct Memory Access Controller (µDMA)
– Dedicated channel for each timer
– Burst request generated on timer interrupt
1.3.4.4
CCP Pins (see page 702)
Capture Compare PWM pins (CCP) can be used by the General-Purpose Timer Module to time/count
external events using the CCP pin as an input. Alternatively, the GPTM can generate a simple PWM
output on the CCP pin.
The TM4C1237H6PZ microcontroller includes twelve 16/32-bit CCP pins that can be programmed
to operate in the following modes:
■ Capture: The GP Timer is incremented/decremented by programmed events on the CCP input.
The GP Timer captures and stores the current timer value when a programmed event occurs.
■ Compare: The GP Timer is incremented/decremented by programmed events on the CCP input.
The GP Timer compares the current value with a stored value and generates an interrupt when
a match occurs.
■ PWM: The GP Timer is incremented/decremented by the system clock. A PWM signal is generated
based on a match between the counter value and a value stored in a match register and is output
on the CCP pin.
1.3.4.5
Hibernation Module (HIB) (see page 478)
The Hibernation module provides logic to switch power off to the main processor and peripherals
and to wake on external or time-based events. The Hibernation module includes power-sequencing
logic and has the following features:
■ 32-bit real-time seconds counter (RTC) with 1/32,768 second resolution and a 15-bit sub-seconds
counter
– 32-bit RTC seconds match register and a 15-bit sub seconds match for timed wake-up and
interrupt generation with 1/32,768 second resolution
– RTC predivider trim for making fine adjustments to the clock rate
■ Two mechanisms for power control
– System power control using discrete external regulator
– On-chip power control using internal switches under register control
■ Dedicated pin for waking using an external signal
■ RTC operational and hibernation memory valid as long as VDD or VBAT is valid
■ Low-battery detection, signaling, and interrupt generation, with optional wake on low battery
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■ GPIO pin state can be retained during hibernation
■ Clock source from a 32.768-kHz external crystal or oscillator
■ Sixteen 32-bit words of battery-backed memory to save state during hibernation
■ Programmable interrupts for:
– RTC match
– External wake
– Low battery
1.3.4.6
Watchdog Timers (see page 763)
A watchdog timer is used to regain control when a system has failed due to a software error or to
the failure of an external device to respond in the expected way. The TM4C1237H6PZ Watchdog
Timer can generate an interrupt, a non-maskable interrupt, or a reset when a time-out value is
reached. In addition, the Watchdog Timer is ARM FiRM-compliant and can be configured to generate
an interrupt to the microcontroller on its first time-out, and to generate a reset signal on its second
timeout. Once the Watchdog Timer has been configured, the lock register can be written to prevent
the timer configuration from being inadvertently altered.
The TM4C1237H6PZ microcontroller has two Watchdog Timer modules: Watchdog Timer 0 uses
the system clock for its timer clock; Watchdog Timer 1 uses the PIOSC as its timer clock. The
Watchdog Timer module has the following features:
■ 32-bit down counter with a programmable load register
■ Separate watchdog clock with an enable
■ Programmable interrupt generation logic with interrupt masking and optional NMI function
■ Lock register protection from runaway software
■ Reset generation logic with an enable/disable
■ User-enabled stalling when the microcontroller asserts the CPU Halt flag during debug
1.3.4.7
Programmable GPIOs (see page 634)
General-purpose input/output (GPIO) pins offer flexibility for a variety of connections. The
TM4C1237H6PZ GPIO module is comprised of ten physical GPIO blocks, each corresponding to
an individual GPIO port. The GPIO module is FiRM-compliant (compliant to the ARM Foundation
IP for Real-Time Microcontrollers specification) and supports 0-69 programmable input/output pins.
The number of GPIOs available depends on the peripherals being used (see “Signal
Tables” on page 1224 for the signals available to each GPIO pin).
■ Up to 69 GPIOs, depending on configuration
■ Highly flexible pin muxing allows use as GPIO or one of several peripheral functions
■ 5-V-tolerant in input configuration
■ Fast toggle capable of a change every clock cycle for ports on AHB, every two clock cycles for
ports on APB
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■ Programmable control for GPIO interrupts
– Interrupt generation masking
– Edge-triggered on rising, falling, or both
– Level-sensitive on High or Low values
■ Bit masking in both read and write operations through address lines
■ Can be used to initiate an ADC sample sequence or a μDMA transfer
■ Pin state can be retained during Hibernation mode
■ Pins configured as digital inputs are Schmitt-triggered
■ Programmable control for GPIO pad configuration
– Weak pull-up or pull-down resistors
– 2-mA, 4-mA, and 8-mA pad drive for digital communication; up to four pads can sink 18-mA
for high-current applications
– Slew rate control for 8-mA pad drive
– Open drain enables
– Digital input enables
1.3.5
Analog
The TM4C1237H6PZ microcontroller provides analog functions integrated into the device, including:
■ Two 12-bit Analog-to-Digital Converters (ADC), with a total of 22 analog input channels and each
with a sample rate of one million samples/second
■ Three analog comparators
■ On-chip voltage regulator
The following provides more detail on these analog functions.
1.3.5.1
ADC (see page 788)
An analog-to-digital converter (ADC) is a peripheral that converts a continuous analog voltage to a
discrete digital number. The TM4C1237H6PZ ADC module features 12-bit conversion resolution
and supports 22 input channels plus an internal temperature sensor. Four buffered sample
sequencers allow rapid sampling of up to 22 analog input sources without controller intervention.
Each sample sequencer provides flexible programming with fully configurable input source, trigger
events, interrupt generation, and sequencer priority. Each ADC module has a digital comparator
function that allows the conversion value to be diverted to a comparison unit that provides eight
digital comparators.
The TM4C1237H6PZ microcontroller provides two ADC modules, each with the following features:
■ 22 shared analog input channels
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■ 12-bit precision ADC
■ Single-ended and differential-input configurations
■ On-chip internal temperature sensor
■ Maximum sample rate of one million samples/second
■ Optional phase shift in sample time programmable from 22.5º to 337.5º
■ Four programmable sample conversion sequencers from one to eight entries long, with
corresponding conversion result FIFOs
■ Flexible trigger control
– Controller (software)
– Timers
– Analog Comparators
– GPIO
■ Hardware averaging of up to 64 samples
■ Eight digital comparators
■ Converter uses two external reference signals (VREFA+ and VREFA-) or VDDA and GNDA as the
voltage reference
■ Power and ground for the analog circuitry is separate from the digital power and ground
■ Efficient transfers using Micro Direct Memory Access Controller (µDMA)
– Dedicated channel for each sample sequencer
– ADC module uses burst requests for DMA
1.3.5.2
Analog Comparators (see page 1207)
An analog comparator is a peripheral that compares two analog voltages and provides a logical
output that signals the comparison result. The TM4C1237H6PZ microcontroller provides three
independent integrated analog comparators that can be configured to drive an output or generate
an interrupt or ADC event.
The comparator can provide its output to a device pin, acting as a replacement for an analog
comparator on the board, or it can be used to signal the application via interrupts or triggers to the
ADC to cause it to start capturing a sample sequence. The interrupt generation and ADC triggering
logic is separate. This means, for example, that an interrupt can be generated on a rising edge and
the ADC triggered on a falling edge.
The TM4C1237H6PZ microcontroller provides three independent integrated analog comparators
with the following functions:
■ Compare external pin input to external pin input or to internal programmable voltage reference
■ Compare a test voltage against any one of the following voltages:
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– An individual external reference voltage
– A shared single external reference voltage
– A shared internal reference voltage
1.3.6
JTAG and ARM Serial Wire Debug (see page 195)
The Joint Test Action Group (JTAG) port is an IEEE standard that defines a Test Access Port and
Boundary Scan Architecture for digital integrated circuits and provides a standardized serial interface
for controlling the associated test logic. The TAP, Instruction Register (IR), and Data Registers (DR)
can be used to test the interconnections of assembled printed circuit boards and obtain manufacturing
information on the components. The JTAG Port also provides a means of accessing and controlling
design-for-test features such as I/O pin observation and control, scan testing, and debugging. Texas
Instruments replaces the ARM SW-DP and JTAG-DP with the ARM Serial Wire JTAG Debug Port
(SWJ-DP) interface. The SWJ-DP interface combines the SWD and JTAG debug ports into one
module providing all the normal JTAG debug and test functionality plus real-time access to system
memory without halting the core or requiring any target resident code. The SWJ-DP interface has
the following features:
■ IEEE 1149.1-1990 compatible Test Access Port (TAP) controller
■ Four-bit Instruction Register (IR) chain for storing JTAG instructions
■ IEEE standard instructions: BYPASS, IDCODE, SAMPLE/PRELOAD, and EXTEST
■ ARM additional instructions: APACC, DPACC and ABORT
■ Integrated ARM Serial Wire Debug (SWD)
– Serial Wire JTAG Debug Port (SWJ-DP)
– Flash Patch and Breakpoint (FPB) unit for implementing breakpoints
– Data Watchpoint and Trace (DWT) unit for implementing watchpoints, trigger resources, and
system profiling
– Instrumentation Trace Macrocell (ITM) for support of printf style debugging
– Embedded Trace Macrocell (ETM) for instruction trace capture
– Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer
1.3.7
Packaging and Temperature
■ 100-pin RoHS-compliant LQFP package
■ Industrial (-40°C to 85°C) ambient temperature range
1.4
TM4C1237H6PZ Microcontroller Hardware Details
Details on the pins and package can be found in the following sections:
■ “Pin Diagram” on page 1223
■ “Signal Tables” on page 1224
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■ “Electrical Characteristics” on page 1256
■ “Package Information” on page 1301
1.5
Kits
The Tiva™ C Series provides the hardware and software tools that engineers need to begin
development quickly.
■ Reference Design Kits accelerate product development by providing ready-to-run hardware and
comprehensive documentation including hardware design files
■ Evaluation Kits provide a low-cost and effective means of evaluating TM4C1237H6PZ
microcontrollers before purchase
■ Development Kits provide you with all the tools you need to develop and prototype embedded
applications right out of the box
See the Tiva series website at http://www.ti.com/tiva-c for the latest tools available, or ask your
distributor.
1.6
Support Information
For support on Tiva™ C Series products, contact the TI Worldwide Product Information Center
nearest you.
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The Cortex-M4F Processor
2
The Cortex-M4F Processor
The ARM® Cortex™-M4F processor provides a high-performance, low-cost platform that meets the
system requirements of minimal memory implementation, reduced pin count, and low power
consumption, while delivering outstanding computational performance and exceptional system
response to interrupts. Features include:
®
■ 32-bit ARM Cortex™-M4F architecture optimized for small-footprint embedded applications
■ 80-MHz operation; 100 DMIPS performance
■ Outstanding processing performance combined with fast interrupt handling
■ Thumb-2 mixed 16-/32-bit instruction set delivers the high performance expected of a 32-bit
ARM core in a compact memory size usually associated with 8- and 16-bit devices, typically in
the range of a few kilobytes of memory for microcontroller-class applications
– Single-cycle multiply instruction and hardware divide
– Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined
peripheral control
– Unaligned data access, enabling data to be efficiently packed into memory
■ IEEE754-compliant single-precision Floating-Point Unit (FPU)
■ 16-bit SIMD vector processing unit
■ Fast code execution permits slower processor clock or increases sleep mode time
■ Harvard architecture characterized by separate buses for instruction and data
■ Efficient processor core, system and memories
■ Hardware division and fast digital-signal-processing orientated multiply accumulate
■ Saturating arithmetic for signal processing
■ Deterministic, high-performance interrupt handling for time-critical applications
■ Memory protection unit (MPU) to provide a privileged mode for protected operating system
functionality
■ Enhanced system debug with extensive breakpoint and trace capabilities
■ Serial Wire Debug and Serial Wire Trace reduce the number of pins required for debugging and
tracing
■ Migration from the ARM7™ processor family for better performance and power efficiency
■ Optimized for single-cycle Flash memory usage up to specific frequencies; see “Internal
Memory” on page 509 for more information.
■ Ultra-low power consumption with integrated sleep modes
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The Tiva™ C Series microcontrollers builds on this core to bring high-performance 32-bit computing
to
This chapter provides information on the Tiva™ C Series implementation of the Cortex-M4F
processor, including the programming model, the memory model, the exception model, fault handling,
and power management.
For technical details on the instruction set, see the Cortex™-M4 instruction set chapter in the ARM®
Cortex™-M4 Devices Generic User Guide (literature number ARM DUI 0553A).
2.1
Block Diagram
The Cortex-M4F processor is built on a high-performance processor core, with a 3-stage pipeline
Harvard architecture, making it ideal for demanding embedded applications. The processor delivers
exceptional power efficiency through an efficient instruction set and extensively optimized design,
providing high-end processing hardware including IEEE754-compliant single-precision floating-point
computation, a range of single-cycle and SIMD multiplication and multiply-with-accumulate
capabilities, saturating arithmetic and dedicated hardware division.
To facilitate the design of cost-sensitive devices, the Cortex-M4F processor implements tightly
coupled system components that reduce processor area while significantly improving interrupt
handling and system debug capabilities. The Cortex-M4F processor implements a version of the
Thumb® instruction set based on Thumb-2 technology, ensuring high code density and reduced
program memory requirements. The Cortex-M4F instruction set provides the exceptional performance
expected of a modern 32-bit architecture, with the high code density of 8-bit and 16-bit
microcontrollers.
The Cortex-M4F processor closely integrates a nested interrupt controller (NVIC), to deliver
industry-leading interrupt performance. The TM4C1237H6PZ NVIC includes a non-maskable interrupt
(NMI) and provides eight interrupt priority levels. The tight integration of the processor core and
NVIC provides fast execution of interrupt service routines (ISRs), dramatically reducing interrupt
latency. The hardware stacking of registers and the ability to suspend load-multiple and store-multiple
operations further reduce interrupt latency. Interrupt handlers do not require any assembler stubs
which removes code overhead from the ISRs. Tail-chaining optimization also significantly reduces
the overhead when switching from one ISR to another. To optimize low-power designs, the NVIC
integrates with the sleep modes, including Deep-sleep mode, which enables the entire device to be
rapidly powered down.
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The Cortex-M4F Processor
Figure 2-1. CPU Block Diagram
Nested
Vectored
Interrupt
Controller
FPU
Interrupts
Sleep
ARM
Cortex-M4F
CM4 Core
Debug
Instructions
Data
Embedded
Trace
Macrocell
Memory
Protection
Unit
Flash
Patch and
Breakpoint
Instrumentation
Data
Watchpoint Trace Macrocell
and Trace
ROM
Table
Private Peripheral
Bus
(internal)
Adv. Peripheral
Bus
Bus
Matrix
Serial Wire JTAG
Debug Port
Debug
Access Port
2.2
Overview
2.2.1
System-Level Interface
Trace
Port
Interface
Unit
Serial
Wire
Output
Trace
Port
(SWO)
I-code bus
D-code bus
System bus
The Cortex-M4F processor provides multiple interfaces using AMBA® technology to provide
high-speed, low-latency memory accesses. The core supports unaligned data accesses and
implements atomic bit manipulation that enables faster peripheral controls, system spinlocks, and
thread-safe Boolean data handling.
The Cortex-M4F processor has a memory protection unit (MPU) that provides fine-grain memory
control, enabling applications to implement security privilege levels and separate code, data and
stack on a task-by-task basis.
2.2.2
Integrated Configurable Debug
The Cortex-M4F processor implements a complete hardware debug solution, providing high system
visibility of the processor and memory through either a traditional JTAG port or a 2-pin Serial Wire
Debug (SWD) port that is ideal for microcontrollers and other small package devices. The Tiva™
C Series implementation replaces the ARM SW-DP and JTAG-DP with the ARM
CoreSight™-compliant Serial Wire JTAG Debug Port (SWJ-DP) interface. The SWJ-DP interface
combines the SWD and JTAG debug ports into one module. See the ARM® Debug Interface V5
Architecture Specification for details on SWJ-DP.
For system trace, the processor integrates an Instrumentation Trace Macrocell (ITM) alongside data
watchpoints and a profiling unit. To enable simple and cost-effective profiling of the system trace
events, a Serial Wire Viewer (SWV) can export a stream of software-generated messages, data
trace, and profiling information through a single pin.
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The Embedded Trace Macrocell (ETM) delivers unrivaled instruction trace capture in an area smaller
than traditional trace units, enabling full instruction trace. For more details on the ARM ETM, see
the ARM® Embedded Trace Macrocell Architecture Specification.
The Flash Patch and Breakpoint Unit (FPB) provides up to eight hardware breakpoint comparators
that debuggers can use. The comparators in the FPB also provide remap functions for up to eight
words of program code in the code memory region. This FPB enables applications stored in a
read-only area of Flash memory to be patched in another area of on-chip SRAM or Flash memory.
If a patch is required, the application programs the FPB to remap a number of addresses. When
those addresses are accessed, the accesses are redirected to a remap table specified in the FPB
configuration.
For more information on the Cortex-M4F debug capabilities, see theARM® Debug Interface V5
Architecture Specification.
2.2.3
Trace Port Interface Unit (TPIU)
The TPIU acts as a bridge between the Cortex-M4F trace data from the ITM, and an off-chip Trace
Port Analyzer, as shown in Figure 2-2 on page 67.
Figure 2-2. TPIU Block Diagram
2.2.4
Debug
ATB
Slave
Port
ARM® Trace
Bus (ATB)
Interface
APB
Slave
Port
Advance
Peripheral
Bus (APB)
Interface
Asynchronous FIFO
Trace Out
(serializer)
Serial Wire
Trace Port
(SWO)
Cortex-M4F System Component Details
The Cortex-M4F includes the following system components:
■ SysTick
A 24-bit count-down timer that can be used as a Real-Time Operating System (RTOS) tick timer
or as a simple counter (see “System Timer (SysTick)” on page 118).
■ Nested Vectored Interrupt Controller (NVIC)
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An embedded interrupt controller that supports low latency interrupt processing (see “Nested
Vectored Interrupt Controller (NVIC)” on page 119).
■ System Control Block (SCB)
The programming model interface to the processor. The SCB provides system implementation
information and system control, including configuration, control, and reporting of system exceptions
(see “System Control Block (SCB)” on page 120).
■ Memory Protection Unit (MPU)
Improves system reliability by defining the memory attributes for different memory regions. The
MPU provides up to eight different regions and an optional predefined background region (see
“Memory Protection Unit (MPU)” on page 120).
■ Floating-Point Unit (FPU)
Fully supports single-precision add, subtract, multiply, divide, multiply and accumulate, and
square-root operations. It also provides conversions between fixed-point and floating-point data
formats, and floating-point constant instructions (see “Floating-Point Unit (FPU)” on page 125).
2.3
Programming Model
This section describes the Cortex-M4F programming model. In addition to the individual core register
descriptions, information about the processor modes and privilege levels for software execution and
stacks is included.
2.3.1
Processor Mode and Privilege Levels for Software Execution
The Cortex-M4F has two modes of operation:
■ Thread mode
Used to execute application software. The processor enters Thread mode when it comes out of
reset.
■ Handler mode
Used to handle exceptions. When the processor has finished exception processing, it returns to
Thread mode.
In addition, the Cortex-M4F has two privilege levels:
■ Unprivileged
In this mode, software has the following restrictions:
– Limited access to the MSR and MRS instructions and no use of the CPS instruction
– No access to the system timer, NVIC, or system control block
– Possibly restricted access to memory or peripherals
■ Privileged
In this mode, software can use all the instructions and has access to all resources.
In Thread mode, the CONTROL register (see page 83) controls whether software execution is
privileged or unprivileged. In Handler mode, software execution is always privileged.
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Only privileged software can write to the CONTROL register to change the privilege level for software
execution in Thread mode. Unprivileged software can use the SVC instruction to make a supervisor
call to transfer control to privileged software.
2.3.2
Stacks
The processor uses a full descending stack, meaning that the stack pointer indicates the last stacked
item on the memory. When the processor pushes a new item onto the stack, it decrements the stack
pointer and then writes the item to the new memory location. The processor implements two stacks:
the main stack and the process stack, with a pointer for each held in independent registers (see the
SP register on page 73).
In Thread mode, the CONTROL register (see page 83) controls whether the processor uses the
main stack or the process stack. In Handler mode, the processor always uses the main stack. The
options for processor operations are shown in Table 2-1 on page 69.
Table 2-1. Summary of Processor Mode, Privilege Level, and Stack Use
Processor Mode
Use
Privilege Level
Thread
Applications
Privileged or unprivileged
Handler
Exception handlers
Always privileged
Stack Used
a
Main stack or process stack
a
Main stack
a. See CONTROL (page 83).
2.3.3
Register Map
Figure 2-3 on page 70 shows the Cortex-M4F register set. Table 2-2 on page 70 lists the Core
registers. The core registers are not memory mapped and are accessed by register name, so the
base address is n/a (not applicable) and there is no offset.
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Figure 2-3. Cortex-M4F Register Set
R0
R1
R2
R3
Low registers
R4
R5
General-purpose registers
R6
R7
R8
R9
High registers
R10
R11
R12
Stack Pointer
SP (R13)
Link Register
LR (R14)
Program Counter
PC (R15)
PSP‡
PSR
MSP‡
‡
Banked version of SP
Program status register
PRIMASK
FAULTMASK
Exception mask registers
Special registers
BASEPRI
CONTROL
CONTROL register
Table 2-2. Processor Register Map
Offset
Name
Type
Reset
Description
See
page
-
R0
RW
-
Cortex General-Purpose Register 0
72
-
R1
RW
-
Cortex General-Purpose Register 1
72
-
R2
RW
-
Cortex General-Purpose Register 2
72
-
R3
RW
-
Cortex General-Purpose Register 3
72
-
R4
RW
-
Cortex General-Purpose Register 4
72
-
R5
RW
-
Cortex General-Purpose Register 5
72
-
R6
RW
-
Cortex General-Purpose Register 6
72
-
R7
RW
-
Cortex General-Purpose Register 7
72
-
R8
RW
-
Cortex General-Purpose Register 8
72
-
R9
RW
-
Cortex General-Purpose Register 9
72
-
R10
RW
-
Cortex General-Purpose Register 10
72
-
R11
RW
-
Cortex General-Purpose Register 11
72
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Table 2-2. Processor Register Map (continued)
Offset
Name
Type
Reset
Description
See
page
-
R12
RW
-
Cortex General-Purpose Register 12
72
-
SP
RW
-
Stack Pointer
73
-
LR
RW
0xFFFF.FFFF
Link Register
74
-
PC
RW
-
Program Counter
75
-
PSR
RW
0x0100.0000
Program Status Register
76
-
PRIMASK
RW
0x0000.0000
Priority Mask Register
80
-
FAULTMASK
RW
0x0000.0000
Fault Mask Register
81
-
BASEPRI
RW
0x0000.0000
Base Priority Mask Register
82
-
CONTROL
RW
0x0000.0000
Control Register
83
-
FPSC
RW
-
Floating-Point Status Control
85
2.3.4
Register Descriptions
This section lists and describes the Cortex-M4F registers, in the order shown in Figure
2-3 on page 70. The core registers are not memory mapped and are accessed by register name
rather than offset.
Note:
The register type shown in the register descriptions refers to type during program execution
in Thread mode and Handler mode. Debug access can differ.
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Register 1: Cortex General-Purpose Register 0 (R0)
Register 2: Cortex General-Purpose Register 1 (R1)
Register 3: Cortex General-Purpose Register 2 (R2)
Register 4: Cortex General-Purpose Register 3 (R3)
Register 5: Cortex General-Purpose Register 4 (R4)
Register 6: Cortex General-Purpose Register 5 (R5)
Register 7: Cortex General-Purpose Register 6 (R6)
Register 8: Cortex General-Purpose Register 7 (R7)
Register 9: Cortex General-Purpose Register 8 (R8)
Register 10: Cortex General-Purpose Register 9 (R9)
Register 11: Cortex General-Purpose Register 10 (R10)
Register 12: Cortex General-Purpose Register 11 (R11)
Register 13: Cortex General-Purpose Register 12 (R12)
The Rn registers are 32-bit general-purpose registers for data operations and can be accessed
from either privileged or unprivileged mode.
Cortex General-Purpose Register 0 (R0)
Type RW, reset 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
DATA
Type
Reset
DATA
Type
Reset
Bit/Field
Name
Type
Reset
31:0
DATA
RW
-
Description
Register data.
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Register 14: Stack Pointer (SP)
The Stack Pointer (SP) is register R13. In Thread mode, the function of this register changes
depending on the ASP bit in the Control Register (CONTROL) register. When the ASP bit is clear,
this register is the Main Stack Pointer (MSP). When the ASP bit is set, this register is the Process
Stack Pointer (PSP). On reset, the ASP bit is clear, and the processor loads the MSP with the value
from address 0x0000.0000. The MSP can only be accessed in privileged mode; the PSP can be
accessed in either privileged or unprivileged mode.
Stack Pointer (SP)
Type RW, reset 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
SP
Type
Reset
SP
Type
Reset
Bit/Field
Name
Type
Reset
31:0
SP
RW
-
Description
This field is the address of the stack pointer.
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Register 15: Link Register (LR)
The Link Register (LR) is register R14, and it stores the return information for subroutines, function
calls, and exceptions. The Link Register can be accessed from either privileged or unprivileged
mode.
EXC_RETURN is loaded into the LR on exception entry. See Table 2-10 on page 106 for the values
and description.
Link Register (LR)
Type RW, reset 0xFFFF.FFFF
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
7
6
5
4
3
2
1
0
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
LINK
Type
Reset
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
15
14
13
12
11
10
9
8
LINK
Type
Reset
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
Bit/Field
Name
Type
31:0
LINK
RW
RW
1
Reset
RW
1
Description
0xFFFF.FFFF This field is the return address.
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Register 16: Program Counter (PC)
The Program Counter (PC) is register R15, and it contains the current program address. On reset,
the processor loads the PC with the value of the reset vector, which is at address 0x0000.0004. Bit
0 of the reset vector is loaded into the THUMB bit of the EPSR at reset and must be 1. The PC register
can be accessed in either privileged or unprivileged mode.
Program Counter (PC)
Type RW, reset 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
PC
Type
Reset
PC
Type
Reset
Bit/Field
Name
Type
Reset
31:0
PC
RW
-
Description
This field is the current program address.
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Register 17: Program Status Register (PSR)
Note:
This register is also referred to as xPSR.
The Program Status Register (PSR) has three functions, and the register bits are assigned to the
different functions:
■ Application Program Status Register (APSR), bits 31:27, bits 19:16
■ Execution Program Status Register (EPSR), bits 26:24, 15:10
■ Interrupt Program Status Register (IPSR), bits 7:0
The PSR, IPSR, and EPSR registers can only be accessed in privileged mode; the APSR register
can be accessed in either privileged or unprivileged mode.
APSR contains the current state of the condition flags from previous instruction executions.
EPSR contains the Thumb state bit and the execution state bits for the If-Then (IT) instruction or
the Interruptible-Continuable Instruction (ICI) field for an interrupted load multiple or store multiple
instruction. Attempts to read the EPSR directly through application software using the MSR instruction
always return zero. Attempts to write the EPSR using the MSR instruction in application software
are always ignored. Fault handlers can examine the EPSR value in the stacked PSR to determine
the operation that faulted (see “Exception Entry and Return” on page 103).
IPSR contains the exception type number of the current Interrupt Service Routine (ISR).
These registers can be accessed individually or as a combination of any two or all three registers,
using the register name as an argument to the MSR or MRS instructions. For example, all of the
registers can be read using PSR with the MRS instruction, or APSR only can be written to using
APSR with the MSR instruction. page 76 shows the possible register combinations for the PSR. See
the MRS and MSR instruction descriptions in the Cortex™-M4 instruction set chapter in the ARM®
Cortex™-M4 Devices Generic User Guide (literature number ARM DUI 0553A) for more information
about how to access the program status registers.
Table 2-3. PSR Register Combinations
Register
Type
PSR
RW
Combination
APSR, EPSR, and IPSR
IEPSR
RO
EPSR and IPSR
a, b
a
APSR and IPSR
b
APSR and EPSR
IAPSR
RW
EAPSR
RW
a. The processor ignores writes to the IPSR bits.
b. Reads of the EPSR bits return zero, and the processor ignores writes to these bits.
Program Status Register (PSR)
Type RW, reset 0x0100.0000
Type
Reset
31
30
29
28
27
N
Z
C
V
Q
26
RW
0
RW
0
RW
0
RW
0
RW
0
RO
0
RO
0
RO
1
RO
0
RO
0
RO
0
RO
0
RW
0
15
14
13
12
11
10
9
8
7
6
5
4
ICI / IT
Type
Reset
RO
0
RO
0
RO
0
25
ICI / IT
24
23
22
THUMB
21
RO
0
RO
0
RO
0
RO
0
19
18
17
16
RW
0
RW
0
RW
0
3
2
1
0
RO
0
RO
0
RO
0
RO
0
GE
reserved
RO
0
20
reserved
ISRNUM
RO
0
RO
0
76
RO
0
RO
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Bit/Field
Name
Type
Reset
31
N
RW
0
Description
APSR Negative or Less Flag
Value Description
1
The previous operation result was negative or less than.
0
The previous operation result was positive, zero, greater than,
or equal.
The value of this bit is only meaningful when accessing PSR or APSR.
30
Z
RW
0
APSR Zero Flag
Value Description
1
The previous operation result was zero.
0
The previous operation result was non-zero.
The value of this bit is only meaningful when accessing PSR or APSR.
29
C
RW
0
APSR Carry or Borrow Flag
Value Description
1
The previous add operation resulted in a carry bit or the previous
subtract operation did not result in a borrow bit.
0
The previous add operation did not result in a carry bit or the
previous subtract operation resulted in a borrow bit.
The value of this bit is only meaningful when accessing PSR or APSR.
28
V
RW
0
APSR Overflow Flag
Value Description
1
The previous operation resulted in an overflow.
0
The previous operation did not result in an overflow.
The value of this bit is only meaningful when accessing PSR or APSR.
27
Q
RW
0
APSR DSP Overflow and Saturation Flag
Value Description
1
DSP Overflow or saturation has occurred when using a SIMD
instruction.
0
DSP overflow or saturation has not occurred since reset or since
the bit was last cleared.
The value of this bit is only meaningful when accessing PSR or APSR.
This bit is cleared by software using an MRS instruction.
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Bit/Field
Name
Type
Reset
26:25
ICI / IT
RO
0x0
Description
EPSR ICI / IT status
These bits, along with bits 15:10, contain the Interruptible-Continuable
Instruction (ICI) field for an interrupted load multiple or store multiple
instruction or the execution state bits of the IT instruction.
When EPSR holds the ICI execution state, bits 26:25 are zero.
The If-Then block contains up to four instructions following an IT
instruction. Each instruction in the block is conditional. The conditions
for the instructions are either all the same, or some can be the inverse
of others. See the Cortex™-M4 instruction set chapter in the ARM®
Cortex™-M4 Devices Generic User Guide (literature number ARM DUI
0553A) for more information.
The value of this field is only meaningful when accessing PSR or EPSR.
Note that these EPSR bits cannot be accessed using MRS and MSR
instructions but the definitions are provided to allow the stacked (E)PSR
value to be decoded within an exception handler.
24
THUMB
RO
1
EPSR Thumb State
This bit indicates the Thumb state and should always be set.
The following can clear the THUMB bit:
■
The BLX, BX and POP{PC} instructions
■
Restoration from the stacked xPSR value on an exception return
■
Bit 0 of the vector value on an exception entry or reset
Attempting to execute instructions when this bit is clear results in a fault
or lockup. See “Lockup” on page 108 for more information.
The value of this bit is only meaningful when accessing PSR or EPSR.
23:20
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
19:16
GE
RW
0x0
Greater Than or Equal Flags
See the description of the SEL instruction in the Cortex™-M4 instruction
set chapter in the ARM® Cortex™-M4 Devices Generic User Guide
(literature number ARM DUI 0553A) for more information.
The value of this field is only meaningful when accessing PSR or APSR.
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Bit/Field
Name
Type
Reset
15:10
ICI / IT
RO
0x0
Description
EPSR ICI / IT status
These bits, along with bits 26:25, contain the Interruptible-Continuable
Instruction (ICI) field for an interrupted load multiple or store multiple
instruction or the execution state bits of the IT instruction.
When an interrupt occurs during the execution of an LDM, STM, PUSH
POP, VLDM, VSTM, VPUSH, or VPOP instruction, the processor stops the
load multiple or store multiple instruction operation temporarily and
stores the next register operand in the multiple operation to bits 15:12.
After servicing the interrupt, the processor returns to the register pointed
to by bits 15:12 and resumes execution of the multiple load or store
instruction. When EPSR holds the ICI execution state, bits 11:10 are
zero.
The If-Then block contains up to four instructions following a 16-bit IT
instruction. Each instruction in the block is conditional. The conditions
for the instructions are either all the same, or some can be the inverse
of others. See the Cortex™-M4 instruction set chapter in the ARM®
Cortex™-M4 Devices Generic User Guide (literature number ARM DUI
0553A) for more information.
The value of this field is only meaningful when accessing PSR or EPSR.
9:8
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
ISRNUM
RO
0x00
IPSR ISR Number
This field contains the exception type number of the current Interrupt
Service Routine (ISR).
Value
Description
0x00
Thread mode
0x01
Reserved
0x02
NMI
0x03
Hard fault
0x04
Memory management fault
0x05
Bus fault
0x06
Usage fault
0x07-0x0A Reserved
0x0B
SVCall
0x0C
Reserved for Debug
0x0D
Reserved
0x0E
PendSV
0x0F
SysTick
0x10
Interrupt Vector 0
0x11
Interrupt Vector 1
...
...
0x9A
Interrupt Vector 138
See “Exception Types” on page 97 for more information.
The value of this field is only meaningful when accessing PSR or IPSR.
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Register 18: Priority Mask Register (PRIMASK)
The PRIMASK register prevents activation of all exceptions with programmable priority. Reset,
non-maskable interrupt (NMI), and hard fault are the only exceptions with fixed priority. Exceptions
should be disabled when they might impact the timing of critical tasks. This register is only accessible
in privileged mode. The MSR and MRS instructions are used to access the PRIMASK register, and
the CPS instruction may be used to change the value of the PRIMASK register. See the Cortex™-M4
instruction set chapter in the ARM® Cortex™-M4 Devices Generic User Guide (literature number
ARM DUI 0553A) for more information on these instructions. For more information on exception
priority levels, see “Exception Types” on page 97.
Priority Mask Register (PRIMASK)
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:1
reserved
RO
0x0000.000
0
PRIMASK
RW
0
RO
0
PRIMASK
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Priority Mask
Value Description
1
Prevents the activation of all exceptions with configurable
priority.
0
No effect.
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Register 19: Fault Mask Register (FAULTMASK)
The FAULTMASK register prevents activation of all exceptions except for the Non-Maskable Interrupt
(NMI). Exceptions should be disabled when they might impact the timing of critical tasks. This register
is only accessible in privileged mode. The MSR and MRS instructions are used to access the
FAULTMASK register, and the CPS instruction may be used to change the value of the FAULTMASK
register. See the Cortex™-M4 instruction set chapter in the ARM® Cortex™-M4 Devices Generic
User Guide (literature number ARM DUI 0553A) for more information on these instructions. For
more information on exception priority levels, see “Exception Types” on page 97.
Fault Mask Register (FAULTMASK)
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:1
reserved
RO
0x0000.000
0
FAULTMASK
RW
0
RO
0
FAULTMASK
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Fault Mask
Value Description
1
Prevents the activation of all exceptions except for NMI.
0
No effect.
The processor clears the FAULTMASK bit on exit from any exception
handler except the NMI handler.
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Register 20: Base Priority Mask Register (BASEPRI)
The BASEPRI register defines the minimum priority for exception processing. When BASEPRI is
set to a nonzero value, it prevents the activation of all exceptions with the same or lower priority
level as the BASEPRI value. Exceptions should be disabled when they might impact the timing of
critical tasks. This register is only accessible in privileged mode. For more information on exception
priority levels, see “Exception Types” on page 97.
Base Priority Mask Register (BASEPRI)
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RW
0
RW
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
BASEPRI
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:5
BASEPRI
RW
0x0
RW
0
reserved
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Base Priority
Any exception that has a programmable priority level with the same or
lower priority as the value of this field is masked. The PRIMASK register
can be used to mask all exceptions with programmable priority levels.
Higher priority exceptions have lower priority levels.
Value Description
4:0
reserved
RO
0x0
0x0
All exceptions are unmasked.
0x1
All exceptions with priority level 1-7 are masked.
0x2
All exceptions with priority level 2-7 are masked.
0x3
All exceptions with priority level 3-7 are masked.
0x4
All exceptions with priority level 4-7 are masked.
0x5
All exceptions with priority level 5-7 are masked.
0x6
All exceptions with priority level 6-7 are masked.
0x7
All exceptions with priority level 7 are masked.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Register 21: Control Register (CONTROL)
The CONTROL register controls the stack used and the privilege level for software execution when
the processor is in Thread mode, and indicates whether the FPU state is active. This register is only
accessible in privileged mode.
Handler mode always uses the MSP, so the processor ignores explicit writes to the ASP bit of the
CONTROL register when in Handler mode. The exception entry and return mechanisms automatically
update the CONTROL register based on the EXC_RETURN value (see Table 2-10 on page 106).
In an OS environment, threads running in Thread mode should use the process stack and the kernel
and exception handlers should use the main stack. By default, Thread mode uses the MSP. To
switch the stack pointer used in Thread mode to the PSP, either use the MSR instruction to set the
ASP bit, as detailed in the Cortex™-M4 instruction set chapter in the ARM® Cortex™-M4 Devices
Generic User Guide (literature number ARM DUI 0553A), or perform an exception return to Thread
mode with the appropriate EXC_RETURN value, as shown in Table 2-10 on page 106.
Note:
When changing the stack pointer, software must use an ISB instruction immediately after
the MSR instruction, ensuring that instructions after the ISB execute use the new stack
pointer. See the Cortex™-M4 instruction set chapter in the ARM® Cortex™-M4 Devices
Generic User Guide (literature number ARM DUI 0553A).
Control Register (CONTROL)
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
FPCA
ASP
TMPL
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
RW
0
RW
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
Bit/Field
Name
Type
Reset
31:3
reserved
RO
0x0000.000
2
FPCA
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Floating-Point Context Active
Value Description
1
Floating-point context active
0
No floating-point context active
The Cortex-M4F uses this bit to determine whether to preserve
floating-point state when processing an exception.
Important:
Two bits control when FPCA can be enabled: the ASPEN
bit in the Floating-Point Context Control (FPCC)
register and the DISFPCA bit in the Auxiliary Control
(ACTLR) register.
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Bit/Field
Name
Type
Reset
1
ASP
RW
0
Description
Active Stack Pointer
Value Description
1
The PSP is the current stack pointer.
0
The MSP is the current stack pointer
In Handler mode, this bit reads as zero and ignores writes. The
Cortex-M4F updates this bit automatically on exception return.
0
TMPL
RW
0
Thread Mode Privilege Level
Value Description
1
Unprivileged software can be executed in Thread mode.
0
Only privileged software can be executed in Thread mode.
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Register 22: Floating-Point Status Control (FPSC)
The FPSC register provides all necessary user-level control of the floating-point system.
Floating-Point Status Control (FPSC)
Type RW, reset 31
Type
Reset
30
29
28
27
26
25
24
22
21
20
19
RMODE
18
17
16
N
Z
C
V
reserved
AHP
DN
FZ
RW
-
RW
-
RW
-
RW
-
RO
0
RW
-
RW
-
RW
-
RW
-
RW
-
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
IXC
UFC
OFC
DZC
IOC
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW
-
RW
-
RW
-
RW
-
RW
-
reserved
Type
Reset
23
IDC
RO
0
Bit/Field
Name
Type
Reset
31
N
RW
-
RW
-
reserved
reserved
RO
0
RO
0
Description
Negative Condition Code Flag
Floating-point comparison operations update this condition code flag.
30
Z
RW
-
Zero Condition Code Flag
Floating-point comparison operations update this condition code flag.
29
C
RW
-
Carry Condition Code Flag
Floating-point comparison operations update this condition code flag.
28
V
RW
-
Overflow Condition Code Flag
Floating-point comparison operations update this condition code flag.
27
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
26
AHP
RW
-
Alternative Half-Precision
When set, alternative half-precision format is selected. When clear,
IEEE half-precision format is selected.
The AHP bit in the FPDSC register holds the default value for this bit.
25
DN
RW
-
Default NaN Mode
When set, any operation involving one or more NaNs returns the Default
NaN. When clear, NaN operands propagate through to the output of a
floating-point operation.
The DN bit in the FPDSC register holds the default value for this bit.
24
FZ
RW
-
Flush-to-Zero Mode
When set, Flush-to-Zero mode is enabled. When clear, Flush-to-Zero
mode is disabled and the behavior of the floating-point system is fully
compliant with the IEEE 754 standard.
The FZ bit in the FPDSC register holds the default value for this bit.
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Bit/Field
Name
Type
Reset
23:22
RMODE
RW
-
Description
Rounding Mode
The specified rounding mode is used by almost all floating-point
instructions.
The RMODE bit in the FPDSC register holds the default value for this bit.
Value Description
21:8
reserved
RO
0x0
7
IDC
RW
-
0x0
Round to Nearest (RN) mode
0x1
Round towards Plus Infinity (RP) mode
0x2
Round towards Minus Infinity (RM) mode
0x3
Round towards Zero (RZ) mode
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Input Denormal Cumulative Exception
When set, indicates this exception has occurred since 0 was last written
to this bit.
6:5
reserved
RO
0x0
4
IXC
RW
-
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Inexact Cumulative Exception
When set, indicates this exception has occurred since 0 was last written
to this bit.
3
UFC
RW
-
Underflow Cumulative Exception
When set, indicates this exception has occurred since 0 was last written
to this bit.
2
OFC
RW
-
Overflow Cumulative Exception
When set, indicates this exception has occurred since 0 was last written
to this bit.
1
DZC
RW
-
Division by Zero Cumulative Exception
When set, indicates this exception has occurred since 0 was last written
to this bit.
0
IOC
RW
-
Invalid Operation Cumulative Exception
When set, indicates this exception has occurred since 0 was last written
to this bit.
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2.3.5
Exceptions and Interrupts
The Cortex-M4F processor supports interrupts and system exceptions. The processor and the
Nested Vectored Interrupt Controller (NVIC) prioritize and handle all exceptions. An exception
changes the normal flow of software control. The processor uses Handler mode to handle all
exceptions except for reset. See “Exception Entry and Return” on page 103 for more information.
The NVIC registers control interrupt handling. See “Nested Vectored Interrupt Controller
(NVIC)” on page 119 for more information.
2.3.6
Data Types
The Cortex-M4F supports 32-bit words, 16-bit halfwords, and 8-bit bytes. The processor also supports
64-bit data transfer instructions. All instruction and data memory accesses are little endian. See
“Memory Regions, Types and Attributes” on page 90 for more information.
2.4
Memory Model
This section describes the processor memory map, the behavior of memory accesses, and the
bit-banding features. The processor has a fixed memory map that provides up to 4 GB of addressable
memory.
The memory map for the TM4C1237H6PZ controller is provided in Table 2-4 on page 87. In this
manual, register addresses are given as a hexadecimal increment, relative to the module's base
address as shown in the memory map.
The regions for SRAM and peripherals include bit-band regions. Bit-banding provides atomic
operations to bit data (see “Bit-Banding” on page 92).
The processor reserves regions of the Private peripheral bus (PPB) address range for core peripheral
registers (see “Cortex-M4 Peripherals” on page 117).
Note:
Within the memory map, attempts to read or write addresses in reserved spaces result in
a bus fault. In addition, attempts to write addresses in the flash range also result in a bus
fault.
Table 2-4. Memory Map
Start
End
Description
For details,
see page ...
0x0000.0000
0x0003.FFFF
On-chip Flash
525
0x0004.0000
0x1FFF.FFFF
Reserved
-
0x2000.0000
0x2000.7FFF
Bit-banded on-chip SRAM
510
0x2000.8000
0x21FF.FFFF
Reserved
-
0x2200.0000
0x220F.FFFF
Bit-band alias of bit-banded on-chip SRAM starting at
0x2000.0000
510
0x2210.0000
0x3FFF.FFFF
Reserved
-
0x4000.0000
0x4000.0FFF
Watchdog timer 0
765
0x4000.1000
0x4000.1FFF
Watchdog timer 1
765
0x4000.2000
0x4000.3FFF
Reserved
-
0x4000.4000
0x4000.4FFF
GPIO Port A
644
0x4000.5000
0x4000.5FFF
GPIO Port B
644
Memory
Peripherals
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Table 2-4. Memory Map (continued)
Start
End
Description
For details,
see page ...
0x4000.6000
0x4000.6FFF
GPIO Port C
644
0x4000.7000
0x4000.7FFF
GPIO Port D
644
0x4000.8000
0x4000.8FFF
SSI0
960
0x4000.9000
0x4000.9FFF
SSI1
960
0x4000.A000
0x4000.AFFF
SSI2
960
0x4000.B000
0x4000.BFFF
SSI3
960
0x4000.C000
0x4000.CFFF
UART0
895
0x4000.D000
0x4000.DFFF
UART1
895
0x4000.E000
0x4000.EFFF
UART2
895
0x4000.F000
0x4000.FFFF
UART3
895
0x4001.0000
0x4001.0FFF
UART4
895
0x4001.1000
0x4001.1FFF
UART5
895
0x4001.2000
0x4001.2FFF
UART6
895
0x4001.3000
0x4001.3FFF
UART7
895
0x4001.4000
0x4001.FFFF
Reserved
-
0x4002.0FFF
I2C 0
1010
0x4002.1FFF
I2C
1
1010
0x4002.2000
0x4002.2FFF
I2C
2
1010
0x4002.3000
0x4002.3FFF
I2C 3
1010
0x4002.4000
0x4002.4FFF
GPIO Port E
644
0x4002.5000
0x4002.5FFF
GPIO Port F
644
0x4002.6000
0x4002.6FFF
GPIO Port G
644
0x4002.7000
0x4002.7FFF
GPIO Port H
644
0x4002.8000
0x4002.FFFF
Reserved
-
0x4003.0000
0x4003.0FFF
16/32-bit Timer 0
714
0x4003.1000
0x4003.1FFF
16/32-bit Timer 1
714
0x4003.2000
0x4003.2FFF
16/32-bit Timer 2
714
0x4003.3000
0x4003.3FFF
16/32-bit Timer 3
714
0x4003.4000
0x4003.4FFF
16/32-bit Timer 4
714
0x4003.5000
0x4003.5FFF
16/32-bit Timer 5
714
0x4003.6000
0x4003.6FFF
32/64-bit Timer 0
714
0x4003.7000
0x4003.7FFF
32/64-bit Timer 1
714
0x4003.8000
0x4003.8FFF
ADC0
807
0x4003.9000
0x4003.9FFF
ADC1
807
0x4003.A000
0x4003.BFFF
Reserved
-
0x4003.C000
0x4003.CFFF
Analog Comparators
1213
0x4003.D000
0x4003.DFFF
GPIO Port J
644
0x4003.E000
0x4003.FFFF
Reserved
-
0x4004.0000
0x4004.0FFF
CAN0 Controller
1060
0x4004.1000
0x4004.BFFF
Reserved
-
Peripherals
0x4002.0000
0x4002.1000
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Table 2-4. Memory Map (continued)
Start
End
Description
For details,
see page ...
0x4004.C000
0x4004.CFFF
32/64-bit Timer 2
714
0x4004.D000
0x4004.DFFF
32/64-bit Timer 3
714
0x4004.E000
0x4004.EFFF
32/64-bit Timer 4
714
0x4004.F000
0x4004.FFFF
32/64-bit Timer 5
714
0x4005.0000
0x4005.0FFF
USB
1106
0x4005.1000
0x4005.7FFF
Reserved
-
0x4005.8000
0x4005.8FFF
GPIO Port A (AHB aperture)
644
0x4005.9000
0x4005.9FFF
GPIO Port B (AHB aperture)
644
0x4005.A000
0x4005.AFFF
GPIO Port C (AHB aperture)
644
0x4005.B000
0x4005.BFFF
GPIO Port D (AHB aperture)
644
0x4005.C000
0x4005.CFFF
GPIO Port E (AHB aperture)
644
0x4005.D000
0x4005.DFFF
GPIO Port F (AHB aperture)
644
0x4005.E000
0x4005.EFFF
GPIO Port G (AHB aperture)
644
0x4005.F000
0x4005.FFFF
GPIO Port H (AHB aperture)
644
0x4006.0000
0x4006.0FFF
GPIO Port J (AHB aperture)
644
0x4006.1000
0x4006.1FFF
GPIO Port K (AHB aperture)
644
0x4006.2000
0x400A.EFFF
Reserved
-
0x400A.F000
0x400A.FFFF
EEPROM and Key Locker
525
0x400B.0000
0x400B.FFFF
Reserved
-
0x400C.0FFF
I2C
4
1010
5
1010
0x400C.0000
0x400C.1000
0x400C.1FFF
I2C
0x400C.2000
0x400F.8FFF
Reserved
-
0x400F.9000
0x400F.9FFF
System Exception Module
470
0x400F.A000
0x400F.BFFF
Reserved
-
0x400F.C000
0x400F.CFFF
Hibernation Module
490
0x400F.D000
0x400F.DFFF
Flash memory control
525
0x400F.E000
0x400F.EFFF
System control
226
0x400F.F000
0x400F.FFFF
µDMA
591
0x4010.0000
0x41FF.FFFF
Reserved
-
0x4200.0000
0x43FF.FFFF
Bit-banded alias of 0x4000.0000 through 0x400F.FFFF
-
0x4400.0000
0xDFFF.FFFF
Reserved
-
0xE000.0000
0xE000.0FFF
Instrumentation Trace Macrocell (ITM)
66
0xE000.1000
0xE000.1FFF
Data Watchpoint and Trace (DWT)
66
0xE000.2000
0xE000.2FFF
Flash Patch and Breakpoint (FPB)
66
0xE000.3000
0xE000.DFFF
Reserved
-
0xE000.E000
0xE000.EFFF
Cortex-M4F Peripherals (SysTick, NVIC, MPU, FPU and SCB) 129
0xE000.F000
0xE003.FFFF
Reserved
-
0xE004.0000
0xE004.0FFF
Trace Port Interface Unit (TPIU)
67
0xE004.1000
0xE004.1FFF
Embedded Trace Macrocell (ETM)
66
0xE004.2000
0xFFFF.FFFF
Reserved
-
Private Peripheral Bus
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2.4.1
Memory Regions, Types and Attributes
The memory map and the programming of the MPU split the memory map into regions. Each region
has a defined memory type, and some regions have additional memory attributes. The memory
type and attributes determine the behavior of accesses to the region.
The memory types are:
■ Normal: The processor can re-order transactions for efficiency and perform speculative reads.
■ Device: The processor preserves transaction order relative to other transactions to Device or
Strongly Ordered memory.
■ Strongly Ordered: The processor preserves transaction order relative to all other transactions.
The different ordering requirements for Device and Strongly Ordered memory mean that the memory
system can buffer a write to Device memory but must not buffer a write to Strongly Ordered memory.
An additional memory attribute is Execute Never (XN), which means the processor prevents
instruction accesses. A fault exception is generated only on execution of an instruction executed
from an XN region.
2.4.2
Memory System Ordering of Memory Accesses
For most memory accesses caused by explicit memory access instructions, the memory system
does not guarantee that the order in which the accesses complete matches the program order of
the instructions, providing the order does not affect the behavior of the instruction sequence. Normally,
if correct program execution depends on two memory accesses completing in program order,
software must insert a memory barrier instruction between the memory access instructions (see
“Software Ordering of Memory Accesses” on page 91).
However, the memory system does guarantee ordering of accesses to Device and Strongly Ordered
memory. For two memory access instructions A1 and A2, if both A1 and A2 are accesses to either
Device or Strongly Ordered memory, and if A1 occurs before A2 in program order, A1 is always
observed before A2.
2.4.3
Behavior of Memory Accesses
Table 2-5 on page 90 shows the behavior of accesses to each region in the memory map. See
“Memory Regions, Types and Attributes” on page 90 for more information on memory types and
the XN attribute. Tiva™ C Series devices may have reserved memory areas within the address
ranges shown below (refer to Table 2-4 on page 87 for more information).
Table 2-5. Memory Access Behavior
Address Range
Memory Region
Memory Type
Execute
Never
(XN)
Description
0x0000.0000 - 0x1FFF.FFFF Code
Normal
-
This executable region is for program code.
Data can also be stored here.
0x2000.0000 - 0x3FFF.FFFF SRAM
Normal
-
This executable region is for data. Code
can also be stored here. This region
includes bit band and bit band alias areas
(see Table 2-6 on page 92).
0x4000.0000 - 0x5FFF.FFFF Peripheral
Device
XN
This region includes bit band and bit band
alias areas (see Table 2-7 on page 93).
0x6000.0000 - 0x9FFF.FFFF External RAM
Normal
-
This executable region is for data.
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Table 2-5. Memory Access Behavior (continued)
Address Range
Memory Region
Memory Type
Execute
Never
(XN)
Description
0xA000.0000 - 0xDFFF.FFFF External device
Device
XN
This region is for external device memory.
0xE000.0000- 0xE00F.FFFF Private peripheral
bus
Strongly
Ordered
XN
This region includes the NVIC, system
timer, and system control block.
0xE010.0000- 0xFFFF.FFFF Reserved
-
-
-
The Code, SRAM, and external RAM regions can hold programs. However, it is recommended that
programs always use the Code region because the Cortex-M4F has separate buses that can perform
instruction fetches and data accesses simultaneously.
The MPU can override the default memory access behavior described in this section. For more
information, see “Memory Protection Unit (MPU)” on page 120.
The Cortex-M4F prefetches instructions ahead of execution and speculatively prefetches from
branch target addresses.
2.4.4
Software Ordering of Memory Accesses
The order of instructions in the program flow does not always guarantee the order of the
corresponding memory transactions for the following reasons:
■ The processor can reorder some memory accesses to improve efficiency, providing this does
not affect the behavior of the instruction sequence.
■ The processor has multiple bus interfaces.
■ Memory or devices in the memory map have different wait states.
■ Some memory accesses are buffered or speculative.
“Memory System Ordering of Memory Accesses” on page 90 describes the cases where the memory
system guarantees the order of memory accesses. Otherwise, if the order of memory accesses is
critical, software must include memory barrier instructions to force that ordering. The Cortex-M4F
has the following memory barrier instructions:
■ The Data Memory Barrier (DMB) instruction ensures that outstanding memory transactions
complete before subsequent memory transactions.
■ The Data Synchronization Barrier (DSB) instruction ensures that outstanding memory transactions
complete before subsequent instructions execute.
■ The Instruction Synchronization Barrier (ISB) instruction ensures that the effect of all completed
memory transactions is recognizable by subsequent instructions.
Memory barrier instructions can be used in the following situations:
■ MPU programming
– If the MPU settings are changed and the change must be effective on the very next instruction,
use a DSB instruction to ensure the effect of the MPU takes place immediately at the end of
context switching.
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– Use an ISB instruction to ensure the new MPU setting takes effect immediately after
programming the MPU region or regions, if the MPU configuration code was accessed using
a branch or call. If the MPU configuration code is entered using exception mechanisms, then
an ISB instruction is not required.
■ Vector table
If the program changes an entry in the vector table and then enables the corresponding exception,
use a DMB instruction between the operations. The DMB instruction ensures that if the exception
is taken immediately after being enabled, the processor uses the new exception vector.
■ Self-modifying code
If a program contains self-modifying code, use an ISB instruction immediately after the code
modification in the program. The ISB instruction ensures subsequent instruction execution uses
the updated program.
■ Memory map switching
If the system contains a memory map switching mechanism, use a DSB instruction after switching
the memory map in the program. The DSB instruction ensures subsequent instruction execution
uses the updated memory map.
■ Dynamic exception priority change
When an exception priority has to change when the exception is pending or active, use DSB
instructions after the change. The change then takes effect on completion of the DSB instruction.
Memory accesses to Strongly Ordered memory, such as the System Control Block, do not require
the use of DMB instructions.
For more information on the memory barrier instructions, see the Cortex™-M4 instruction set chapter
in the ARM® Cortex™-M4 Devices Generic User Guide (literature number ARM DUI 0553A).
2.4.5
Bit-Banding
A bit-band region maps each word in a bit-band alias region to a single bit in the bit-band region.
The bit-band regions occupy the lowest 1 MB of the SRAM and peripheral memory regions. Accesses
to the 32-MB SRAM alias region map to the 1-MB SRAM bit-band region, as shown in Table
2-6 on page 92. Accesses to the 32-MB peripheral alias region map to the 1-MB peripheral bit-band
region, as shown in Table 2-7 on page 93. For the specific address range of the bit-band regions,
see Table 2-4 on page 87.
Note:
A word access to the SRAM or the peripheral bit-band alias region maps to a single bit in
the SRAM or peripheral bit-band region.
A word access to a bit band address results in a word access to the underlying memory,
and similarly for halfword and byte accesses. This allows bit band accesses to match the
access requirements of the underlying peripheral.
Table 2-6. SRAM Memory Bit-Banding Regions
Address Range
Memory Region
Start
End
0x2000.0000
0x2000.7FFF
Instruction and Data Accesses
SRAM bit-band region Direct accesses to this memory range behave as SRAM
memory accesses, but this region is also bit addressable
through bit-band alias.
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Table 2-6. SRAM Memory Bit-Banding Regions (continued)
Address Range
Start
End
0x2200.0000
0x220F.FFFF
Memory Region
Instruction and Data Accesses
SRAM bit-band alias
Data accesses to this region are remapped to bit band
region. A write operation is performed as
read-modify-write. Instruction accesses are not remapped.
Table 2-7. Peripheral Memory Bit-Banding Regions
Address Range
Memory Region
Instruction and Data Accesses
0x400F.FFFF
Peripheral bit-band
region
Direct accesses to this memory range behave as
peripheral memory accesses, but this region is also bit
addressable through bit-band alias.
0x43FF.FFFF
Peripheral bit-band alias Data accesses to this region are remapped to bit band
region. A write operation is performed as
read-modify-write. Instruction accesses are not permitted.
Start
End
0x4000.0000
0x4200.0000
The following formula shows how the alias region maps onto the bit-band region:
bit_word_offset = (byte_offset x 32) + (bit_number x 4)
bit_word_addr = bit_band_base + bit_word_offset
where:
bit_word_offset
The position of the target bit in the bit-band memory region.
bit_word_addr
The address of the word in the alias memory region that maps to the targeted bit.
bit_band_base
The starting address of the alias region.
byte_offset
The number of the byte in the bit-band region that contains the targeted bit.
bit_number
The bit position, 0-7, of the targeted bit.
Figure 2-4 on page 94 shows examples of bit-band mapping between the SRAM bit-band alias
region and the SRAM bit-band region:
■ The alias word at 0x23FF.FFE0 maps to bit 0 of the bit-band byte at 0x200F.FFFF:
0x23FF.FFE0 = 0x2200.0000 + (0x000F.FFFF*32) + (0*4)
■ The alias word at 0x23FF.FFFC maps to bit 7 of the bit-band byte at 0x200F.FFFF:
0x23FF.FFFC = 0x2200.0000 + (0x000F.FFFF*32) + (7*4)
■ The alias word at 0x2200.0000 maps to bit 0 of the bit-band byte at 0x2000.0000:
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0x2200.0000 = 0x2200.0000 + (0*32) + (0*4)
■ The alias word at 0x2200.001C maps to bit 7 of the bit-band byte at 0x2000.0000:
0x2200.001C = 0x2200.0000+ (0*32) + (7*4)
Figure 2-4. Bit-Band Mapping
32-MB Alias Region
0x23FF.FFFC
0x23FF.FFF8
0x23FF.FFF4
0x23FF.FFF0
0x23FF.FFEC
0x23FF.FFE8
0x23FF.FFE4
0x23FF.FFE0
0x2200.001C
0x2200.0018
0x2200.0014
0x2200.0010
0x2200.000C
0x2200.0008
0x2200.0004
0x2200.0000
7
3
1-MB SRAM Bit-Band Region
7
6
5
4
3
2
1
0
7
6
0x200F.FFFF
7
6
5
4
3
2
0x2000.0003
2.4.5.1
5
4
3
2
1
0
7
6
0x200F.FFFE
1
0
7
6
5
4
3
2
5
4
3
2
1
0
6
0x200F.FFFD
1
0
0x2000.0002
7
6
5
4
3
2
0x2000.0001
5
4
2
1
0
1
0
0x200F.FFFC
1
0
7
6
5
4
3
2
0x2000.0000
Directly Accessing an Alias Region
Writing to a word in the alias region updates a single bit in the bit-band region.
Bit 0 of the value written to a word in the alias region determines the value written to the targeted
bit in the bit-band region. Writing a value with bit 0 set writes a 1 to the bit-band bit, and writing a
value with bit 0 clear writes a 0 to the bit-band bit.
Bits 31:1 of the alias word have no effect on the bit-band bit. Writing 0x01 has the same effect as
writing 0xFF. Writing 0x00 has the same effect as writing 0x0E.
When reading a word in the alias region, 0x0000.0000 indicates that the targeted bit in the bit-band
region is clear and 0x0000.0001 indicates that the targeted bit in the bit-band region is set.
2.4.5.2
Directly Accessing a Bit-Band Region
“Behavior of Memory Accesses” on page 90 describes the behavior of direct byte, halfword, or word
accesses to the bit-band regions.
2.4.6
Data Storage
The processor views memory as a linear collection of bytes numbered in ascending order from zero.
For example, bytes 0-3 hold the first stored word, and bytes 4-7 hold the second stored word. Data
is stored in little-endian format, with the least-significant byte (lsbyte) of a word stored at the
lowest-numbered byte, and the most-significant byte (msbyte) stored at the highest-numbered byte.
Figure 2-5 on page 95 illustrates how data is stored.
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Figure 2-5. Data Storage
Memory
7
Register
0
31
2.4.7
Address A
B0
A+1
B1
A+2
B2
A+3
B3
lsbyte
24 23
B3
16 15
B2
8 7
B1
0
B0
msbyte
Synchronization Primitives
The Cortex-M4F instruction set includes pairs of synchronization primitives which provide a
non-blocking mechanism that a thread or process can use to obtain exclusive access to a memory
location. Software can use these primitives to perform a guaranteed read-modify-write memory
update sequence or for a semaphore mechanism.
A pair of synchronization primitives consists of:
■ A Load-Exclusive instruction, which is used to read the value of a memory location and requests
exclusive access to that location.
■ A Store-Exclusive instruction, which is used to attempt to write to the same memory location and
returns a status bit to a register. If this status bit is clear, it indicates that the thread or process
gained exclusive access to the memory and the write succeeds; if this status bit is set, it indicates
that the thread or process did not gain exclusive access to the memory and no write was
performed.
The pairs of Load-Exclusive and Store-Exclusive instructions are:
■ The word instructions LDREX and STREX
■ The halfword instructions LDREXH and STREXH
■ The byte instructions LDREXB and STREXB
Software must use a Load-Exclusive instruction with the corresponding Store-Exclusive instruction.
To perform an exclusive read-modify-write of a memory location, software must:
1. Use a Load-Exclusive instruction to read the value of the location.
2. Modify the value, as required.
3. Use a Store-Exclusive instruction to attempt to write the new value back to the memory location.
4. Test the returned status bit.
If the status bit is clear, the read-modify-write completed successfully. If the status bit is set, no
write was performed, which indicates that the value returned at step 1 might be out of date. The
software must retry the entire read-modify-write sequence.
Software can use the synchronization primitives to implement a semaphore as follows:
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1. Use a Load-Exclusive instruction to read from the semaphore address to check whether the
semaphore is free.
2. If the semaphore is free, use a Store-Exclusive to write the claim value to the semaphore
address.
3. If the returned status bit from step 2 indicates that the Store-Exclusive succeeded, then the
software has claimed the semaphore. However, if the Store-Exclusive failed, another process
might have claimed the semaphore after the software performed step 1.
The Cortex-M4F includes an exclusive access monitor that tags the fact that the processor has
executed a Load-Exclusive instruction. The processor removes its exclusive access tag if:
■ It executes a CLREX instruction.
■ It executes a Store-Exclusive instruction, regardless of whether the write succeeds.
■ An exception occurs, which means the processor can resolve semaphore conflicts between
different threads.
For more information about the synchronization primitive instructions, see the Cortex™-M4 instruction
set chapter in the ARM® Cortex™-M4 Devices Generic User Guide (literature number ARM DUI
0553A).
2.5
Exception Model
The ARM Cortex-M4F processor and the Nested Vectored Interrupt Controller (NVIC) prioritize and
handle all exceptions in Handler Mode. The processor state is automatically stored to the stack on
an exception and automatically restored from the stack at the end of the Interrupt Service Routine
(ISR). The vector is fetched in parallel to the state saving, enabling efficient interrupt entry. The
processor supports tail-chaining, which enables back-to-back interrupts to be performed without the
overhead of state saving and restoration.
Table 2-8 on page 98 lists all exception types. Software can set eight priority levels on seven of
these exceptions (system handlers) as well as on 72 interrupts (listed in Table 2-9 on page 99).
Priorities on the system handlers are set with the NVIC System Handler Priority n (SYSPRIn)
registers. Interrupts are enabled through the NVIC Interrupt Set Enable n (ENn) register and
prioritized with the NVIC Interrupt Priority n (PRIn) registers. Priorities can be grouped by splitting
priority levels into preemption priorities and subpriorities. All the interrupt registers are described in
“Nested Vectored Interrupt Controller (NVIC)” on page 119.
Internally, the highest user-programmable priority (0) is treated as fourth priority, after a Reset,
Non-Maskable Interrupt (NMI), and a Hard Fault, in that order. Note that 0 is the default priority for
all the programmable priorities.
Important: After a write to clear an interrupt source, it may take several processor cycles for the
NVIC to see the interrupt source deassert. Thus if the interrupt clear is done as the last
action in an interrupt handler, it is possible for the interrupt handler to complete while
the NVIC sees the interrupt as still asserted, causing the interrupt handler to be
re-entered errantly. This situation can be avoided by either clearing the interrupt source
at the beginning of the interrupt handler or by performing a read or write after the write
to clear the interrupt source (and flush the write buffer).
See “Nested Vectored Interrupt Controller (NVIC)” on page 119 for more information on exceptions
and interrupts.
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2.5.1
Exception States
Each exception is in one of the following states:
■ Inactive. The exception is not active and not pending.
■ Pending. The exception is waiting to be serviced by the processor. An interrupt request from a
peripheral or from software can change the state of the corresponding interrupt to pending.
■ Active. An exception that is being serviced by the processor but has not completed.
Note:
An exception handler can interrupt the execution of another exception handler. In this
case, both exceptions are in the active state.
■ Active and Pending. The exception is being serviced by the processor, and there is a pending
exception from the same source.
2.5.2
Exception Types
The exception types are:
■ Reset. Reset is invoked on power up or a warm reset. The exception model treats reset as a
special form of exception. When reset is asserted, the operation of the processor stops, potentially
at any point in an instruction. When reset is deasserted, execution restarts from the address
provided by the reset entry in the vector table. Execution restarts as privileged execution in
Thread mode.
■ NMI. A non-maskable Interrupt (NMI) can be signaled using the NMI signal or triggered by
software using the Interrupt Control and State (INTCTRL) register. This exception has the
highest priority other than reset. NMI is permanently enabled and has a fixed priority of -2. NMIs
cannot be masked or prevented from activation by any other exception or preempted by any
exception other than reset.
■ Hard Fault. A hard fault is an exception that occurs because of an error during exception
processing, or because an exception cannot be managed by any other exception mechanism.
Hard faults have a fixed priority of -1, meaning they have higher priority than any exception with
configurable priority.
■ Memory Management Fault. A memory management fault is an exception that occurs because
of a memory protection related fault, including access violation and no match. The MPU or the
fixed memory protection constraints determine this fault, for both instruction and data memory
transactions. This fault is used to abort instruction accesses to Execute Never (XN) memory
regions, even if the MPU is disabled.
■ Bus Fault. A bus fault is an exception that occurs because of a memory-related fault for an
instruction or data memory transaction such as a prefetch fault or a memory access fault. This
fault can be enabled or disabled.
■ Usage Fault. A usage fault is an exception that occurs because of a fault related to instruction
execution, such as:
– An undefined instruction
– An illegal unaligned access
– Invalid state on instruction execution
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– An error on exception return
An unaligned address on a word or halfword memory access or division by zero can cause a
usage fault when the core is properly configured.
■ SVCall. A supervisor call (SVC) is an exception that is triggered by the SVC instruction. In an
OS environment, applications can use SVC instructions to access OS kernel functions and device
drivers.
■ Debug Monitor. This exception is caused by the debug monitor (when not halting). This exception
is only active when enabled. This exception does not activate if it is a lower priority than the
current activation.
■ PendSV. PendSV is a pendable, interrupt-driven request for system-level service. In an OS
environment, use PendSV for context switching when no other exception is active. PendSV is
triggered using the Interrupt Control and State (INTCTRL) register.
■ SysTick. A SysTick exception is an exception that the system timer generates when it reaches
zero when it is enabled to generate an interrupt. Software can also generate a SysTick exception
using the Interrupt Control and State (INTCTRL) register. In an OS environment, the processor
can use this exception as system tick.
■ Interrupt (IRQ). An interrupt, or IRQ, is an exception signaled by a peripheral or generated by
a software request and fed through the NVIC (prioritized). All interrupts are asynchronous to
instruction execution. In the system, peripherals use interrupts to communicate with the processor.
Table 2-9 on page 99 lists the interrupts on the TM4C1237H6PZ controller.
For an asynchronous exception, other than reset, the processor can execute another instruction
between when the exception is triggered and when the processor enters the exception handler.
Privileged software can disable the exceptions that Table 2-8 on page 98 shows as having
configurable priority (see the SYSHNDCTRL register on page 168 and the DIS0 register on page 139).
For more information about hard faults, memory management faults, bus faults, and usage faults,
see “Fault Handling” on page 106.
Table 2-8. Exception Types
Exception Type
a
Vector
Number
Priority
Vector Address or
b
Offset
-
0
-
0x0000.0000
Stack top is loaded from the first
entry of the vector table on reset.
Reset
1
-3 (highest)
0x0000.0004
Asynchronous
Non-Maskable Interrupt
(NMI)
2
-2
0x0000.0008
Asynchronous
Hard Fault
3
-1
0x0000.000C
-
c
0x0000.0010
Synchronous
c
0x0000.0014
Synchronous when precise and
asynchronous when imprecise
c
Synchronous
Memory Management
4
programmable
Bus Fault
5
programmable
Usage Fault
6
programmable
0x0000.0018
7-10
-
-
-
Activation
c
c
Reserved
SVCall
11
programmable
0x0000.002C
Synchronous
Debug Monitor
12
programmable
0x0000.0030
Synchronous
-
13
-
-
98
Reserved
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Table 2-8. Exception Types (continued)
Exception Type
PendSV
SysTick
a
Vector
Number
Priority
14
programmable
15
Interrupts
Vector Address or
b
Offset
c
0x0000.0038
Asynchronous
c
0x0000.003C
Asynchronous
programmable
16 and above
Activation
d
programmable
0x0000.0040 and above Asynchronous
a. 0 is the default priority for all the programmable priorities.
b. See “Vector Table” on page 101.
c. See SYSPRI1 on page 165.
d. See PRIn registers on page 147.
Table 2-9. Interrupts
Vector Number
Interrupt Number (Bit
in Interrupt Registers)
Vector Address or
Offset
Description
0-15
-
0x0000.0000 0x0000.003C
16
0
0x0000.0040
GPIO Port A
17
1
0x0000.0044
GPIO Port B
18
2
0x0000.0048
GPIO Port C
19
3
0x0000.004C
GPIO Port D
20
4
0x0000.0050
GPIO Port E
21
5
0x0000.0054
UART0
22
6
0x0000.0058
UART1
23
7
0x0000.005C
SSI0
24
8
0x0000.0060
I2C0
25-29
9-13
-
30
14
0x0000.0078
ADC0 Sequence 0
31
15
0x0000.007C
ADC0 Sequence 1
32
16
0x0000.0080
ADC0 Sequence 2
33
17
0x0000.0084
ADC0 Sequence 3
34
18
0x0000.0088
Watchdog Timers 0 and 1
35
19
0x0000.008C
16/32-Bit Timer 0A
36
20
0x0000.0090
16/32-Bit Timer 0B
37
21
0x0000.0094
16/32-Bit Timer 1A
38
22
0x0000.0098
16/32-Bit Timer 1B
39
23
0x0000.009C
16/32-Bit Timer 2A
40
24
0x0000.00A0
16/32-Bit Timer 2B
41
25
0x0000.00A4
Analog Comparator 0
42
26
0x0000.00A8
Analog Comparator 1
43
27
0x0000.00AC
Analog Comparator 2
44
28
0x0000.00B0
System Control
45
29
0x0000.00B4
Flash Memory Control and EEPROM Control
46
30
0x0000.00B8
GPIO Port F
47
31
0x0000.00BC
GPIO Port G
48
32
0x0000.00C0
GPIO Port H
Processor exceptions
Reserved
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Table 2-9. Interrupts (continued)
Vector Number
Interrupt Number (Bit
in Interrupt Registers)
Vector Address or
Offset
Description
49
33
0x0000.00C4
UART2
50
34
0x0000.00C8
SSI1
51
35
0x0000.00CC
16/32-Bit Timer 3A
52
36
0x0000.00D0
16/32-Bit Timer 3B
53
37
0x0000.00D4
I2C1
54
38
-
Reserved
55
39
0x0000.00DC
56-58
40-42
-
CAN0
59
43
0x0000.00EC
Hibernation Module
60
44
0x0000.00F0
USB
61
45
-
62
46
0x0000.00F8
µDMA Software
63
47
0x0000.00FC
µDMA Error
64
48
0x0000.0100
ADC1 Sequence 0
65
49
0x0000.0104
ADC1 Sequence 1
66
50
0x0000.0108
ADC1 Sequence 2
67
51
0x0000.010C
ADC1 Sequence 3
68-69
52-53
-
70
54
0x0000.0118
GPIO Port J
71
55
0x0000.011C
GPIO Port K
72
56
-
73
57
0x0000.0124
SSI2
74
58
0x0000.0128
SSI3
75
59
0x0000.012C
UART3
76
60
0x0000.0130
UART4
77
61
0x0000.0134
UART5
78
62
0x0000.0138
UART6
79
63
0x0000.013C
UART7
80-83
64-67
0x0000.0140 0x0000.014C
Reserved
84
68
0x0000.0150
I2C2
85
69
0x0000.0154
I2C3
86
70
0x0000.0158
16/32-Bit Timer 4A
87
71
0x0000.015C
16/32-Bit Timer 4B
88-107
72-91
0x0000.0160 0x0000.01AC
Reserved
108
92
0x0000.01B0
16/32-Bit Timer 5A
109
93
0x0000.01B4
16/32-Bit Timer 5B
110
94
0x0000.01B8
32/64-Bit Timer 0A
111
95
0x0000.01BC
32/64-Bit Timer 0B
112
96
0x0000.01C0
32/64-Bit Timer 1A
113
97
0x0000.01C4
32/64-Bit Timer 1B
Reserved
Reserved
Reserved
Reserved
100
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Table 2-9. Interrupts (continued)
2.5.3
Vector Number
Interrupt Number (Bit
in Interrupt Registers)
Vector Address or
Offset
Description
114
98
0x0000.01C8
32/64-Bit Timer 2A
115
99
0x0000.01CC
32/64-Bit Timer 2B
116
100
0x0000.01D0
32/64-Bit Timer 3A
117
101
0x0000.01D4
32/64-Bit Timer 3B
118
102
0x0000.01D8
32/64-Bit Timer 4A
119
103
0x0000.01DC
32/64-Bit Timer 4B
120
104
0x0000.01E0
32/64-Bit Timer 5A
121
105
0x0000.01E4
32/64-Bit Timer 5B
System Exception (imprecise)
122
106
0x0000.01E8
123-124
107-108
-
125
109
0x0000.01F4
I2C4
126
110
0x0000.01F8
I2C5
127-154
111-138
-
Reserved
Reserved
Exception Handlers
The processor handles exceptions using:
■ Interrupt Service Routines (ISRs). Interrupts (IRQx) are the exceptions handled by ISRs.
■ Fault Handlers. Hard fault, memory management fault, usage fault, and bus fault are fault
exceptions handled by the fault handlers.
■ System Handlers. NMI, PendSV, SVCall, SysTick, and the fault exceptions are all system
exceptions that are handled by system handlers.
2.5.4
Vector Table
The vector table contains the reset value of the stack pointer and the start addresses, also called
exception vectors, for all exception handlers. The vector table is constructed using the vector address
or offset shown in Table 2-8 on page 98. Figure 2-6 on page 102 shows the order of the exception
vectors in the vector table. The least-significant bit of each vector must be 1, indicating that the
exception handler is Thumb code
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Figure 2-6. Vector Table
Exception number IRQ number
154
138
.
.
.
18
2
17
1
16
0
15
-1
14
-2
13
Offset
0x0268
.
.
.
0x004C
0x0048
0x0044
0x0040
0x003C
0x0038
12
11
Vector
IRQ131
.
.
.
IRQ2
IRQ1
IRQ0
Systick
PendSV
Reserved
Reserved for Debug
-5
10
0x002C
9
SVCall
Reserved
8
7
6
-10
5
-11
4
-12
3
-13
2
-14
1
0x0018
0x0014
0x0010
0x000C
0x0008
0x0004
0x0000
Usage fault
Bus fault
Memory management fault
Hard fault
NMI
Reset
Initial SP value
On system reset, the vector table is fixed at address 0x0000.0000. Privileged software can write to
the Vector Table Offset (VTABLE) register to relocate the vector table start address to a different
memory location, in the range 0x0000.0400 to 0x3FFF.FC00 (see “Vector Table” on page 101). Note
that when configuring the VTABLE register, the offset must be aligned on a 1024-byte boundary.
2.5.5
Exception Priorities
As Table 2-8 on page 98 shows, all exceptions have an associated priority, with a lower priority
value indicating a higher priority and configurable priorities for all exceptions except Reset, Hard
fault, and NMI. If software does not configure any priorities, then all exceptions with a configurable
priority have a priority of 0. For information about configuring exception priorities, see page 165 and
page 147.
Note:
Configurable priority values for the Tiva™ C Series implementation are in the range 0-7.
This means that the Reset, Hard fault, and NMI exceptions, with fixed negative priority
values, always have higher priority than any other exception.
For example, assigning a higher priority value to IRQ[0] and a lower priority value to IRQ[1] means
that IRQ[1] has higher priority than IRQ[0]. If both IRQ[1] and IRQ[0] are asserted, IRQ[1] is processed
before IRQ[0].
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If multiple pending exceptions have the same priority, the pending exception with the lowest exception
number takes precedence. For example, if both IRQ[0] and IRQ[1] are pending and have the same
priority, then IRQ[0] is processed before IRQ[1].
When the processor is executing an exception handler, the exception handler is preempted if a
higher priority exception occurs. If an exception occurs with the same priority as the exception being
handled, the handler is not preempted, irrespective of the exception number. However, the status
of the new interrupt changes to pending.
2.5.6
Interrupt Priority Grouping
To increase priority control in systems with interrupts, the NVIC supports priority grouping. This
grouping divides each interrupt priority register entry into two fields:
■ An upper field that defines the group priority
■ A lower field that defines a subpriority within the group
Only the group priority determines preemption of interrupt exceptions. When the processor is
executing an interrupt exception handler, another interrupt with the same group priority as the
interrupt being handled does not preempt the handler.
If multiple pending interrupts have the same group priority, the subpriority field determines the order
in which they are processed. If multiple pending interrupts have the same group priority and
subpriority, the interrupt with the lowest IRQ number is processed first.
For information about splitting the interrupt priority fields into group priority and subpriority, see
page 159.
2.5.7
Exception Entry and Return
Descriptions of exception handling use the following terms:
■ Preemption. When the processor is executing an exception handler, an exception can preempt
the exception handler if its priority is higher than the priority of the exception being handled. See
“Interrupt Priority Grouping” on page 103 for more information about preemption by an interrupt.
When one exception preempts another, the exceptions are called nested exceptions. See
“Exception Entry” on page 104 more information.
■ Return. Return occurs when the exception handler is completed, and there is no pending
exception with sufficient priority to be serviced and the completed exception handler was not
handling a late-arriving exception. The processor pops the stack and restores the processor
state to the state it had before the interrupt occurred. See “Exception Return” on page 105 for
more information.
■ Tail-Chaining. This mechanism speeds up exception servicing. On completion of an exception
handler, if there is a pending exception that meets the requirements for exception entry, the
stack pop is skipped and control transfers to the new exception handler.
■ Late-Arriving. This mechanism speeds up preemption. If a higher priority exception occurs
during state saving for a previous exception, the processor switches to handle the higher priority
exception and initiates the vector fetch for that exception. State saving is not affected by late
arrival because the state saved is the same for both exceptions. Therefore, the state saving
continues uninterrupted. The processor can accept a late arriving exception until the first instruction
of the exception handler of the original exception enters the execute stage of the processor. On
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return from the exception handler of the late-arriving exception, the normal tail-chaining rules
apply.
2.5.7.1
Exception Entry
Exception entry occurs when there is a pending exception with sufficient priority and either the
processor is in Thread mode or the new exception is of higher priority than the exception being
handled, in which case the new exception preempts the original exception.
When one exception preempts another, the exceptions are nested.
Sufficient priority means the exception has more priority than any limits set by the mask registers
(see PRIMASK on page 80, FAULTMASK on page 81, and BASEPRI on page 82). An exception
with less priority than this is pending but is not handled by the processor.
When the processor takes an exception, unless the exception is a tail-chained or a late-arriving
exception, the processor pushes information onto the current stack. This operation is referred to as
stacking and the structure of eight data words is referred to as stack frame.
When using floating-point routines, the Cortex-M4F processor automatically stacks the architected
floating-point state on exception entry. Figure 2-7 on page 105 shows the Cortex-M4F stack frame
layout when floating-point state is preserved on the stack as the result of an interrupt or an exception.
Note:
Where stack space for floating-point state is not allocated, the stack frame is the same as
that of ARMv7-M implementations without an FPU. Figure 2-7 on page 105 shows this stack
frame also.
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Figure 2-7. Exception Stack Frame
...
{aligner}
FPSCR
S15
S14
S13
S12
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
xPSR
PC
LR
R12
R3
R2
R1
R0
Exception frame with
floating-point storage
Pre-IRQ top of stack
Decreasing
memory
address
IRQ top of stack
...
{aligner}
xPSR
PC
LR
R12
R3
R2
R1
R0
Pre-IRQ top of stack
IRQ top of stack
Exception frame without
floating-point storage
Immediately after stacking, the stack pointer indicates the lowest address in the stack frame.
The stack frame includes the return address, which is the address of the next instruction in the
interrupted program. This value is restored to the PC at exception return so that the interrupted
program resumes.
In parallel with the stacking operation, the processor performs a vector fetch that reads the exception
handler start address from the vector table. When stacking is complete, the processor starts executing
the exception handler. At the same time, the processor writes an EXC_RETURN value to the LR,
indicating which stack pointer corresponds to the stack frame and what operation mode the processor
was in before the entry occurred.
If no higher-priority exception occurs during exception entry, the processor starts executing the
exception handler and automatically changes the status of the corresponding pending interrupt to
active.
If another higher-priority exception occurs during exception entry, known as late arrival, the processor
starts executing the exception handler for this exception and does not change the pending status
of the earlier exception.
2.5.7.2
Exception Return
Exception return occurs when the processor is in Handler mode and executes one of the following
instructions to load the EXC_RETURN value into the PC:
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■ An LDM or POP instruction that loads the PC
■ A BX instruction using any register
■ An LDR instruction with the PC as the destination
EXC_RETURN is the value loaded into the LR on exception entry. The exception mechanism relies
on this value to detect when the processor has completed an exception handler. The lowest five
bits of this value provide information on the return stack and processor mode. Table 2-10 on page 106
shows the EXC_RETURN values with a description of the exception return behavior.
EXC_RETURN bits 31:5 are all set. When this value is loaded into the PC, it indicates to the processor
that the exception is complete, and the processor initiates the appropriate exception return sequence.
Table 2-10. Exception Return Behavior
EXC_RETURN[31:0]
Description
0xFFFF.FFE0
Reserved
0xFFFF.FFE1
Return to Handler mode.
Exception return uses floating-point state from MSP.
Execution uses MSP after return.
0xFFFF.FFE2 - 0xFFFF.FFE8
Reserved
0xFFFF.FFE9
Return to Thread mode.
Exception return uses floating-point state from MSP.
Execution uses MSP after return.
0xFFFF.FFEA - 0xFFFF.FFEC
Reserved
0xFFFF.FFED
Return to Thread mode.
Exception return uses floating-point state from PSP.
Execution uses PSP after return.
0xFFFF.FFEE - 0xFFFF.FFF0
Reserved
0xFFFF.FFF1
Return to Handler mode.
Exception return uses non-floating-point state from MSP.
Execution uses MSP after return.
0xFFFF.FFF2 - 0xFFFF.FFF8
Reserved
0xFFFF.FFF9
Return to Thread mode.
Exception return uses non-floating-point state from MSP.
Execution uses MSP after return.
0xFFFF.FFFA - 0xFFFF.FFFC
Reserved
0xFFFF.FFFD
Return to Thread mode.
Exception return uses non-floating-point state from PSP.
Execution uses PSP after return.
0xFFFF.FFFE - 0xFFFF.FFFF
2.6
Reserved
Fault Handling
Faults are a subset of the exceptions (see “Exception Model” on page 96). The following conditions
generate a fault:
■ A bus error on an instruction fetch or vector table load or a data access.
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■ An internally detected error such as an undefined instruction or an attempt to change state with
a BX instruction.
■ Attempting to execute an instruction from a memory region marked as Non-Executable (XN).
■ An MPU fault because of a privilege violation or an attempt to access an unmanaged region.
2.6.1
Fault Types
Table 2-11 on page 107 shows the types of fault, the handler used for the fault, the corresponding
fault status register, and the register bit that indicates the fault has occurred. See page 172 for more
information about the fault status registers.
Table 2-11. Faults
Fault
Handler
Fault Status Register
Bit Name
Bus error on a vector read
Hard fault
Hard Fault Status (HFAULTSTAT)
VECT
Fault escalated to a hard fault
Hard fault
Hard Fault Status (HFAULTSTAT)
FORCED
MPU or default memory mismatch on
instruction access
Memory management
fault
Memory Management Fault Status
(MFAULTSTAT)
IERR
MPU or default memory mismatch on
data access
Memory management
fault
Memory Management Fault Status
(MFAULTSTAT)
DERR
MPU or default memory mismatch on
exception stacking
Memory management
fault
Memory Management Fault Status
(MFAULTSTAT)
MSTKE
MPU or default memory mismatch on
exception unstacking
Memory management
fault
Memory Management Fault Status
(MFAULTSTAT)
MUSTKE
MPU or default memory mismatch
during lazy floating-point state
preservation
Memory management
fault
Memory Management Fault Status
(MFAULTSTAT)
MLSPERR
Bus error during exception stacking
Bus fault
Bus Fault Status (BFAULTSTAT)
BSTKE
Bus error during exception unstacking Bus fault
Bus Fault Status (BFAULTSTAT)
BUSTKE
Bus error during instruction prefetch
Bus fault
Bus Fault Status (BFAULTSTAT)
IBUS
Bus error during lazy floating-point state Bus fault
preservation
Bus Fault Status (BFAULTSTAT)
BLSPE
Precise data bus error
Bus fault
Bus Fault Status (BFAULTSTAT)
PRECISE
Imprecise data bus error
Bus fault
Bus Fault Status (BFAULTSTAT)
IMPRE
Attempt to access a coprocessor
Usage fault
Usage Fault Status (UFAULTSTAT)
NOCP
Undefined instruction
Usage fault
Usage Fault Status (UFAULTSTAT)
UNDEF
Attempt to enter an invalid instruction
b
set state
Usage fault
Usage Fault Status (UFAULTSTAT)
INVSTAT
Invalid EXC_RETURN value
Usage fault
Usage Fault Status (UFAULTSTAT)
INVPC
Illegal unaligned load or store
Usage fault
Usage Fault Status (UFAULTSTAT)
UNALIGN
Divide by 0
Usage fault
Usage Fault Status (UFAULTSTAT)
DIV0
a
a. Occurs on an access to an XN region even if the MPU is disabled.
b. Attempting to use an instruction set other than the Thumb instruction set, or returning to a non load-store-multiply instruction
with ICI continuation.
2.6.2
Fault Escalation and Hard Faults
All fault exceptions except for hard fault have configurable exception priority (see SYSPRI1 on
page 165). Software can disable execution of the handlers for these faults (see SYSHNDCTRL on
page 168).
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Usually, the exception priority, together with the values of the exception mask registers, determines
whether the processor enters the fault handler, and whether a fault handler can preempt another
fault handler as described in “Exception Model” on page 96.
In some situations, a fault with configurable priority is treated as a hard fault. This process is called
priority escalation, and the fault is described as escalated to hard fault. Escalation to hard fault
occurs when:
■ A fault handler causes the same kind of fault as the one it is servicing. This escalation to hard
fault occurs because a fault handler cannot preempt itself because it must have the same priority
as the current priority level.
■ A fault handler causes a fault with the same or lower priority as the fault it is servicing. This
situation happens because the handler for the new fault cannot preempt the currently executing
fault handler.
■ An exception handler causes a fault for which the priority is the same as or lower than the currently
executing exception.
■ A fault occurs and the handler for that fault is not enabled.
If a bus fault occurs during a stack push when entering a bus fault handler, the bus fault does not
escalate to a hard fault. Thus if a corrupted stack causes a fault, the fault handler executes even
though the stack push for the handler failed. The fault handler operates but the stack contents are
corrupted.
Note:
2.6.3
Only Reset and NMI can preempt the fixed priority hard fault. A hard fault can preempt any
exception other than Reset, NMI, or another hard fault.
Fault Status Registers and Fault Address Registers
The fault status registers indicate the cause of a fault. For bus faults and memory management
faults, the fault address register indicates the address accessed by the operation that caused the
fault, as shown in Table 2-12 on page 108.
Table 2-12. Fault Status and Fault Address Registers
Handler
Status Register Name
Address Register Name
Register Description
Hard fault
Hard Fault Status (HFAULTSTAT)
-
page 178
Memory management Memory Management Fault Status
fault
(MFAULTSTAT)
Memory Management Fault
Address (MMADDR)
page 172
Bus fault
Bus Fault Address
(FAULTADDR)
page 172
-
page 172
Bus Fault Status (BFAULTSTAT)
Usage fault
2.6.4
Usage Fault Status (UFAULTSTAT)
page 179
page 180
Lockup
The processor enters a lockup state if a hard fault occurs when executing the NMI or hard fault
handlers. When the processor is in the lockup state, it does not execute any instructions. The
processor remains in lockup state until it is reset, an NMI occurs, or it is halted by a debugger.
Note:
If the lockup state occurs from the NMI handler, a subsequent NMI does not cause the
processor to leave the lockup state.
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2.7
Power Management
The Cortex-M4F processor sleep modes reduce power consumption:
■ Sleep mode stops the processor clock.
■ Deep-sleep mode stops the system clock and switches off the PLL and Flash memory.
The SLEEPDEEP bit of the System Control (SYSCTRL) register selects which sleep mode is used
(see page 161). For more information about the behavior of the sleep modes, see “System
Control” on page 221.
This section describes the mechanisms for entering sleep mode and the conditions for waking up
from sleep mode, both of which apply to Sleep mode and Deep-sleep mode.
2.7.1
Entering Sleep Modes
This section describes the mechanisms software can use to put the processor into one of the sleep
modes.
The system can generate spurious wake-up events, for example a debug operation wakes up the
processor. Therefore, software must be able to put the processor back into sleep mode after such
an event. A program might have an idle loop to put the processor back to sleep mode.
2.7.1.1
Wait for Interrupt
The wait for interrupt instruction, WFI, causes immediate entry to sleep mode unless the wake-up
condition is true (see “Wake Up from WFI or Sleep-on-Exit” on page 110). When the processor
executes a WFI instruction, it stops executing instructions and enters sleep mode. See the
Cortex™-M4 instruction set chapter in the ARM® Cortex™-M4 Devices Generic User Guide (literature
number ARM DUI 0553A) for more information.
2.7.1.2
Wait for Event
The wait for event instruction, WFE, causes entry to sleep mode conditional on the value of a one-bit
event register. When the processor executes a WFE instruction, it checks the event register. If the
register is 0, the processor stops executing instructions and enters sleep mode. If the register is 1,
the processor clears the register and continues executing instructions without entering sleep mode.
If the event register is 1, the processor must not enter sleep mode on execution of a WFE instruction.
Typically, this situation occurs if an SEV instruction has been executed. Software cannot access
this register directly.
See the Cortex™-M4 instruction set chapter in the ARM® Cortex™-M4 Devices Generic User Guide
(literature number ARM DUI 0553A) for more information.
2.7.1.3
Sleep-on-Exit
If the SLEEPEXIT bit of the SYSCTRL register is set, when the processor completes the execution
of all exception handlers, it returns to Thread mode and immediately enters sleep mode. This
mechanism can be used in applications that only require the processor to run when an exception
occurs.
2.7.2
Wake Up from Sleep Mode
The conditions for the processor to wake up depend on the mechanism that caused it to enter sleep
mode.
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2.7.2.1
Wake Up from WFI or Sleep-on-Exit
Normally, the processor wakes up only when the NVIC detects an exception with sufficient priority
to cause exception entry. Some embedded systems might have to execute system restore tasks
after the processor wakes up and before executing an interrupt handler. Entry to the interrupt handler
can be delayed by setting the PRIMASK bit and clearing the FAULTMASK bit. If an interrupt arrives
that is enabled and has a higher priority than current exception priority, the processor wakes up but
does not execute the interrupt handler until the processor clears PRIMASK. For more information
about PRIMASK and FAULTMASK, see page 80 and page 81.
2.7.2.2
Wake Up from WFE
The processor wakes up if it detects an exception with sufficient priority to cause exception entry.
In addition, if the SEVONPEND bit in the SYSCTRL register is set, any new pending interrupt triggers
an event and wakes up the processor, even if the interrupt is disabled or has insufficient priority to
cause exception entry. For more information about SYSCTRL, see page 161.
2.8
Instruction Set Summary
The processor implements a version of the Thumb instruction set. Table 2-13 on page 110 lists the
supported instructions.
Note:
In Table 2-13 on page 110:
■
■
■
■
■
Angle brackets, , enclose alternative forms of the operand
Braces, {}, enclose optional operands
The Operands column is not exhaustive
Op2 is a flexible second operand that can be either a register or a constant
Most instructions can use an optional condition code suffix
For more information on the instructions and operands, see the instruction descriptions in
the ARM® Cortex™-M4 Technical Reference Manual.
Table 2-13. Cortex-M4F Instruction Summary
Mnemonic
Operands
Brief Description
Flags
ADC, ADCS
{Rd,} Rn, Op2
Add with carry
N,Z,C,V
ADD, ADDS
{Rd,} Rn, Op2
Add
N,Z,C,V
ADD, ADDW
{Rd,} Rn , #imm12
Add
-
ADR
Rd, label
Load PC-relative address
-
AND, ANDS
{Rd,} Rn, Op2
Logical AND
N,Z,C
ASR, ASRS
Rd, Rm,
Arithmetic shift right
N,Z,C
B
label
Branch
-
BFC
Rd, #lsb, #width
Bit field clear
-
BFI
Rd, Rn, #lsb, #width
Bit field insert
-
BIC, BICS
{Rd,} Rn, Op2
Bit clear
N,Z,C
BKPT
#imm
Breakpoint
-
BL
label
Branch with link
-
BLX
Rm
Branch indirect with link
-
BX
Rm
Branch indirect
-
CBNZ
Rn, label
Compare and branch if non-zero
-
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Table 2-13. Cortex-M4F Instruction Summary (continued)
Mnemonic
Operands
Brief Description
Flags
CBZ
Rn, label
Compare and branch if zero
-
CLREX
-
Clear exclusive
-
CLZ
Rd, Rm
Count leading zeros
-
CMN
Rn, Op2
Compare negative
N,Z,C,V
CMP
Rn, Op2
Compare
N,Z,C,V
CPSID
i
Change processor state, disable
interrupts
-
CPSIE
i
Change processor state, enable
interrupts
-
DMB
-
Data memory barrier
-
DSB
-
Data synchronization barrier
-
EOR, EORS
{Rd,} Rn, Op2
Exclusive OR
N,Z,C
ISB
-
Instruction synchronization barrier
-
IT
-
If-Then condition block
-
LDM
Rn{!}, reglist
Load multiple registers, increment after -
LDMDB, LDMEA
Rn{!}, reglist
Load multiple registers, decrement
before
LDMFD, LDMIA
Rn{!}, reglist
Load multiple registers, increment after -
LDR
Rt, [Rn, #offset]
Load register with word
-
LDRB, LDRBT
Rt, [Rn, #offset]
Load register with byte
-
LDRD
Rt, Rt2, [Rn, #offset]
Load register with two bytes
-
LDREX
Rt, [Rn, #offset]
Load register exclusive
-
LDREXB
Rt, [Rn]
Load register exclusive with byte
-
LDREXH
Rt, [Rn]
Load register exclusive with halfword
-
LDRH, LDRHT
Rt, [Rn, #offset]
Load register with halfword
-
LDRSB, LDRSBT
Rt, [Rn, #offset]
Load register with signed byte
-
LDRSH, LDRSHT
Rt, [Rn, #offset]
Load register with signed halfword
-
LDRT
Rt, [Rn, #offset]
Load register with word
-
LSL, LSLS
Rd, Rm,
Logical shift left
N,Z,C
LSR, LSRS
Rd, Rm,
Logical shift right
N,Z,C
MLA
Rd, Rn, Rm, Ra
Multiply with accumulate, 32-bit result
-
MLS
Rd, Rn, Rm, Ra
Multiply and subtract, 32-bit result
-
MOV, MOVS
Rd, Op2
Move
N,Z,C
MOV, MOVW
Rd, #imm16
Move 16-bit constant
N,Z,C
MOVT
Rd, #imm16
Move top
-
MRS
Rd, spec_reg
Move from special register to general
register
-
MSR
spec_reg, Rm
Move from general register to special
register
N,Z,C,V
MUL, MULS
{Rd,} Rn, Rm
Multiply, 32-bit result
N,Z
MVN, MVNS
Rd, Op2
Move NOT
N,Z,C
NOP
-
No operation
-
ORN, ORNS
{Rd,} Rn, Op2
Logical OR NOT
N,Z,C
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Table 2-13. Cortex-M4F Instruction Summary (continued)
Mnemonic
Operands
Brief Description
Flags
ORR, ORRS
{Rd,} Rn, Op2
Logical OR
N,Z,C
PKHTB, PKHBT
{Rd,} Rn, Rm, Op2
Pack halfword
-
POP
reglist
Pop registers from stack
-
PUSH
reglist
Push registers onto stack
-
QADD
{Rd,} Rn, Rm
Saturating add
Q
QADD16
{Rd,} Rn, Rm
Saturating add 16
-
QADD8
{Rd,} Rn, Rm
Saturating add 8
-
QASX
{Rd,} Rn, Rm
Saturating add and subtract with
exchange
-
QDADD
{Rd,} Rn, Rm
Saturating double and add
Q
QDSUB
{Rd,} Rn, Rm
Saturating double and subtract
Q
QSAX
{Rd,} Rn, Rm
Saturating subtract and add with
exchange
-
QSUB
{Rd,} Rn, Rm
Saturating subtract
Q
QSUB16
{Rd,} Rn, Rm
Saturating subtract 16
-
QSUB8
{Rd,} Rn, Rm
Saturating subtract 8
-
RBIT
Rd, Rn
Reverse bits
-
REV
Rd, Rn
Reverse byte order in a word
-
REV16
Rd, Rn
Reverse byte order in each halfword
-
REVSH
Rd, Rn
Reverse byte order in bottom halfword
and sign extend
-
ROR, RORS
Rd, Rm,
Rotate right
N,Z,C
RRX, RRXS
Rd, Rm
Rotate right with extend
N,Z,C
RSB, RSBS
{Rd,} Rn, Op2
Reverse subtract
N,Z,C,V
SADD16
{Rd,} Rn, Rm
Signed add 16
GE
SADD8
{Rd,} Rn, Rm
Signed add 8
GE
SASX
{Rd,} Rn, Rm
Signed add and subtract with exchange GE
SBC, SBCS
{Rd,} Rn, Op2
Subtract with carry
N,Z,C,V
SBFX
Rd, Rn, #lsb, #width
Signed bit field extract
-
SDIV
{Rd,} Rn, Rm
Signed divide
-
SEL
{Rd,} Rn, Rm
Select bytes
-
SEV
-
Send event
-
SHADD16
{Rd,} Rn, Rm
Signed halving add 16
-
SHADD8
{Rd,} Rn, Rm
Signed halving add 8
-
SHASX
{Rd,} Rn, Rm
Signed halving add and subtract with
exchange
-
SHSAX
{Rd,} Rn, Rm
Signed halving add and subtract with
exchange
-
SHSUB16
{Rd,} Rn, Rm
Signed halving subtract 16
-
SHSUB8
{Rd,} Rn, Rm
Signed halving subtract 8
-
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Table 2-13. Cortex-M4F Instruction Summary (continued)
Mnemonic
Operands
Brief Description
Flags
SMLABB,
Rd, Rn, Rm, Ra
Signed multiply accumulate long
(halfwords)
Q
Rd, Rn, Rm, Ra
Signed multiply accumulate dual
Q
SMLAL
RdLo, RdHi, Rn, Rm
Signed multiply with accumulate
(32x32+64), 64-bit result
-
SMLALBB,
RdLo, RdHi, Rn, Rm
Signed multiply accumulate long
(halfwords)
-
SMLALD, SMLALDX
RdLo, RdHi, Rn, Rm
Signed multiply accumulate long dual
-
SMLAWB,SMLAWT
Rd, Rn, Rm, Ra
Signed multiply accumulate, word by
halfword
Q
SMLSD
Rd, Rn, Rm, Ra
Signed multiply subtract dual
Q
RdLo, RdHi, Rn, Rm
Signed multiply subtract long dual
SMMLA
Rd, Rn, Rm, Ra
Signed most significant word multiply
accumulate
-
SMMLS,
Rd, Rn, Rm, Ra
Signed most significant word multiply
subtract
-
{Rd,} Rn, Rm
Signed most significant word multiply
-
{Rd,} Rn, Rm
Signed dual multiply add
Q
{Rd,} Rn, Rm
Signed multiply halfwords
-
SMULL
RdLo, RdHi, Rn, Rm
Signed multiply (32x32), 64-bit result
-
SMULWB,
{Rd,} Rn, Rm
Signed multiply by halfword
-
{Rd,} Rn, Rm
Signed dual multiply subtract
-
SSAT
Rd, #n, Rm {,shift #s}
Signed saturate
Q
SSAT16
Rd, #n, Rm
Signed saturate 16
Q
SSAX
{Rd,} Rn, Rm
Saturating subtract and add with
exchange
GE
SSUB16
{Rd,} Rn, Rm
Signed subtract 16
-
SSUB8
{Rd,} Rn, Rm
Signed subtract 8
-
STM
Rn{!}, reglist
Store multiple registers, increment after -
SMLABT,
SMLATB,
SMLATT
SMLAD,
SMLADX
SMLALBT,
SMLALTB,
SMLALTT
SMLSDX
SMLSLD
SMLSLDX
SMMLR
SMMUL,
SMMULR
SMUAD
SMUADX
SMULBB,
SMULBT,
SMULTB,
SMULTT
SMULWT
SMUSD,
SMUSDX
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Table 2-13. Cortex-M4F Instruction Summary (continued)
Mnemonic
Operands
Brief Description
Flags
STMDB, STMEA
Rn{!}, reglist
Store multiple registers, decrement
before
-
STMFD, STMIA
Rn{!}, reglist
Store multiple registers, increment after -
STR
Rt, [Rn {, #offset}]
Store register word
-
STRB, STRBT
Rt, [Rn {, #offset}]
Store register byte
-
STRD
Rt, Rt2, [Rn {, #offset}]
Store register two words
-
STREX
Rt, Rt, [Rn {, #offset}]
Store register exclusive
-
STREXB
Rd, Rt, [Rn]
Store register exclusive byte
-
STREXH
Rd, Rt, [Rn]
Store register exclusive halfword
-
STRH, STRHT
Rt, [Rn {, #offset}]
Store register halfword
-
STRSB, STRSBT
Rt, [Rn {, #offset}]
Store register signed byte
-
STRSH, STRSHT
Rt, [Rn {, #offset}]
Store register signed halfword
-
STRT
Rt, [Rn {, #offset}]
Store register word
-
SUB, SUBS
{Rd,} Rn, Op2
Subtract
N,Z,C,V
SUB, SUBW
{Rd,} Rn, #imm12
Subtract 12-bit constant
N,Z,C,V
SVC
#imm
Supervisor call
-
SXTAB
{Rd,} Rn, Rm, {,ROR #}
Extend 8 bits to 32 and add
-
SXTAB16
{Rd,} Rn, Rm,{,ROR #}
Dual extend 8 bits to 16 and add
-
SXTAH
{Rd,} Rn, Rm,{,ROR #}
Extend 16 bits to 32 and add
-
SXTB16
{Rd,} Rm {,ROR #n}
Signed extend byte 16
-
SXTB
{Rd,} Rm {,ROR #n}
Sign extend a byte
-
SXTH
{Rd,} Rm {,ROR #n}
Sign extend a halfword
-
TBB
[Rn, Rm]
Table branch byte
-
TBH
[Rn, Rm, LSL #1]
Table branch halfword
-
TEQ
Rn, Op2
Test equivalence
N,Z,C
TST
Rn, Op2
Test
N,Z,C
UADD16
{Rd,} Rn, Rm
Unsigned add 16
GE
UADD8
{Rd,} Rn, Rm
Unsigned add 8
GE
UASX
{Rd,} Rn, Rm
Unsigned add and subtract with
exchange
GE
UHADD16
{Rd,} Rn, Rm
Unsigned halving add 16
-
UHADD8
{Rd,} Rn, Rm
Unsigned halving add 8
-
UHASX
{Rd,} Rn, Rm
Unsigned halving add and subtract with exchange
UHSAX
{Rd,} Rn, Rm
Unsigned halving subtract and add with exchange
UHSUB16
{Rd,} Rn, Rm
Unsigned halving subtract 16
-
UHSUB8
{Rd,} Rn, Rm
Unsigned halving subtract 8
-
UBFX
Rd, Rn, #lsb, #width
Unsigned bit field extract
-
UDIV
{Rd,} Rn, Rm
Unsigned divide
-
UMAAL
RdLo, RdHi, Rn, Rm
Unsigned multiply accumulate
accumulate long (32x32+64), 64-bit
result
-
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Table 2-13. Cortex-M4F Instruction Summary (continued)
Mnemonic
Operands
Brief Description
Flags
UMLAL
RdLo, RdHi, Rn, Rm
Unsigned multiply with accumulate
(32x32+32+32), 64-bit result
-
UMULL
RdLo, RdHi, Rn, Rm
Unsigned multiply (32x 2), 64-bit result -
UQADD16
{Rd,} Rn, Rm
Unsigned Saturating Add 16
-
UQADD8
{Rd,} Rn, Rm
Unsigned Saturating Add 8
-
UQASX
{Rd,} Rn, Rm
Unsigned Saturating Add and Subtract with Exchange
UQSAX
{Rd,} Rn, Rm
Unsigned Saturating Subtract and Add with Exchange
UQSUB16
{Rd,} Rn, Rm
Unsigned Saturating Subtract 16
-
UQSUB8
{Rd,} Rn, Rm
Unsigned Saturating Subtract 8
-
USAD8
{Rd,} Rn, Rm
Unsigned Sum of Absolute Differences -
USADA8
{Rd,} Rn, Rm, Ra
Unsigned Sum of Absolute Differences and Accumulate
USAT
Rd, #n, Rm {,shift #s}
Unsigned Saturate
Q
USAT16
Rd, #n, Rm
Unsigned Saturate 16
Q
USAX
{Rd,} Rn, Rm
Unsigned Subtract and add with
Exchange
GE
USUB16
{Rd,} Rn, Rm
Unsigned Subtract 16
GE
USUB8
{Rd,} Rn, Rm
Unsigned Subtract 8
GE
UXTAB
{Rd,} Rn, Rm, {,ROR #}
Rotate, extend 8 bits to 32 and Add
-
UXTAB16
{Rd,} Rn, Rm, {,ROR #}
Rotate, dual extend 8 bits to 16 and Add -
UXTAH
{Rd,} Rn, Rm, {,ROR #}
Rotate, unsigned extend and Add
Halfword
-
UXTB
{Rd,} Rm, {,ROR #n}
Zero extend a Byte
-
UXTB16
{Rd,} Rm, {,ROR #n}
Unsigned Extend Byte 16
-
UXTH
{Rd,} Rm, {,ROR #n}
Zero extend a Halfword
-
VABS.F32
Sd, Sm
Floating-point Absolute
-
VADD.F32
{Sd,} Sn, Sm
Floating-point Add
-
VCMP.F32
Sd,
Compare two floating-point registers, or FPSCR
one floating-point register and zero
VCMPE.F32
Sd,
Compare two floating-point registers, or FPSCR
one floating-point register and zero with
Invalid Operation check
VCVT.S32.F32
Sd, Sm
Convert between floating-point and
integer
VCVT.S16.F32
Sd, Sd, #fbits
Convert between floating-point and fixed point
VCVTR.S32.F32
Sd, Sm
Convert between floating-point and
integer with rounding
-
VCVT.F32.F16
Sd, Sm
Converts half-precision value to
single-precision
-
VCVTT.F32.F16
Sd, Sm
Converts single-precision register to
half-precision
-
VDIV.F32
{Sd,} Sn, Sm
Floating-point Divide
-
VFMA.F32
{Sd,} Sn, Sm
Floating-point Fused Multiply Accumulate -
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Table 2-13. Cortex-M4F Instruction Summary (continued)
Mnemonic
Operands
Brief Description
Flags
VFNMA.F32
{Sd,} Sn, Sm
Floating-point Fused Negate Multiply
Accumulate
-
VFMS.F32
{Sd,} Sn, Sm
Floating-point Fused Multiply Subtract
-
VFNMS.F32
{Sd,} Sn, Sm
Floating-point Fused Negate Multiply
Subtract
-
VLDM.F
Rn{!}, list
Load Multiple extension registers
-
VLDR.F
, [Rn]
Load an extension register from memory -
VLMA.F32
{Sd,} Sn, Sm
Floating-point Multiply Accumulate
-
VLMS.F32
{Sd,} Sn, Sm
Floating-point Multiply Subtract
-
VMOV.F32
Sd, #imm
Floating-point Move immediate
-
VMOV
Sd, Sm
Floating-point Move register
-
VMOV
Sn, Rt
Copy ARM core register to single
precision
-
VMOV
Sm, Sm1, Rt, Rt2
Copy 2 ARM core registers to 2 single
precision
-
VMOV
Dd[x], Rt
Copy ARM core register to scalar
-
VMOV
Rt, Dn[x]
Copy scalar to ARM core register
-
VMRS
Rt, FPSCR
Move FPSCR to ARM core register or
APSR
N,Z,C,V
VMSR
FPSCR, Rt
Move to FPSCR from ARM Core register FPSCR
VMUL.F32
{Sd,} Sn, Sm
Floating-point Multiply
-
VNEG.F32
Sd, Sm
Floating-point Negate
-
VNMLA.F32
{Sd,} Sn, Sm
Floating-point Multiply and Add
-
VNMLS.F32
{Sd,} Sn, Sm
Floating-point Multiply and Subtract
-
VNMUL
{Sd,} Sn, Sm
Floating-point Multiply
-
VPOP
list
Pop extension registers
-
VPUSH
list
Push extension registers
-
VSQRT.F32
Sd, Sm
Calculates floating-point Square Root
-
VSTM
Rn{!}, list
Floating-point register Store Multiple
-
VSTR.F3
Sd, [Rn]
Stores an extension register to memory -
VSUB.F
{Sd,} Sn, Sm
Floating-point Subtract
-
WFE
-
Wait for event
-
WFI
-
Wait for interrupt
-
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3
Cortex-M4 Peripherals
This chapter provides information on the Tiva™ C Series implementation of the Cortex-M4 processor
peripherals, including:
■ SysTick (see page 118)
Provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible
control mechanism.
■ Nested Vectored Interrupt Controller (NVIC) (see page 119)
– Facilitates low-latency exception and interrupt handling
– Controls power management
– Implements system control registers
■ System Control Block (SCB) (see page 120)
Provides system implementation information and system control, including configuration, control,
and reporting of system exceptions.
■ Memory Protection Unit (MPU) (see page 120)
Supports the standard ARMv7 Protected Memory System Architecture (PMSA) model. The MPU
provides full support for protection regions, overlapping protection regions, access permissions,
and exporting memory attributes to the system.
■ Floating-Point Unit (FPU) (see page 125)
Fully supports single-precision add, subtract, multiply, divide, multiply and accumulate, and
square root operations. It also provides conversions between fixed-point and floating-point data
formats, and floating-point constant instructions.
Table 3-1 on page 117 shows the address map of the Private Peripheral Bus (PPB). Some peripheral
register regions are split into two address regions, as indicated by two addresses listed.
Table 3-1. Core Peripheral Register Regions
Address
Core Peripheral
Description (see page ...)
0xE000.E010-0xE000.E01F
System Timer
118
0xE000.E100-0xE000.E4EF
Nested Vectored Interrupt Controller
119
System Control Block
120
0xE000.ED90-0xE000.EDB8
Memory Protection Unit
120
0xE000.EF30-0xE000.EF44
Floating Point Unit
125
0xE000.EF00-0xE000.EF03
0xE000.E008-0xE000.E00F
0xE000.ED00-0xE000.ED3F
3.1
Functional Description
This chapter provides information on the Tiva™ C Series implementation of the Cortex-M4 processor
peripherals: SysTick, NVIC, SCB, MPU, FPU.
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3.1.1
System Timer (SysTick)
Cortex-M4 includes an integrated system timer, SysTick, which provides a simple, 24-bit
clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter
can be used in several different ways, for example as:
■ An RTOS tick timer that fires at a programmable rate (for example, 100 Hz) and invokes a SysTick
routine.
■ A high-speed alarm timer using the system clock.
■ A variable rate alarm or signal timer—the duration is range-dependent on the reference clock
used and the dynamic range of the counter.
■ A simple counter used to measure time to completion and time used.
■ An internal clock source control based on missing/meeting durations. The COUNT bit in the
STCTRL control and status register can be used to determine if an action completed within a
set duration, as part of a dynamic clock management control loop.
The timer consists of three registers:
■ SysTick Control and Status (STCTRL): A control and status counter to configure its clock,
enable the counter, enable the SysTick interrupt, and determine counter status.
■ SysTick Reload Value (STRELOAD): The reload value for the counter, used to provide the
counter's wrap value.
■ SysTick Current Value (STCURRENT): The current value of the counter.
When enabled, the timer counts down on each clock from the reload value to zero, reloads (wraps)
to the value in the STRELOAD register on the next clock edge, then decrements on subsequent
clocks. Clearing the STRELOAD register disables the counter on the next wrap. When the counter
reaches zero, the COUNT status bit is set. The COUNT bit clears on reads.
Writing to the STCURRENT register clears the register and the COUNT status bit. The write does
not trigger the SysTick exception logic. On a read, the current value is the value of the register at
the time the register is accessed.
The SysTick counter runs on either the system clock or the precision internal oscillator (PIOSC)
divided by 4. If this clock signal is stopped for low power mode, the SysTick counter stops. SysTick
can be kept running during Deep-sleep mode by setting the CLK_SRC bit in the SysTick Control
and Status Register (STCTRL) register and ensuring that the PIOSCPD bit in the Deep Sleep
Clock Configuration (DSLPCLKCFG) register is clear. Ensure software uses aligned word accesses
to access the SysTick registers.
The SysTick counter reload and current value are undefined at reset; the correct initialization
sequence for the SysTick counter is:
1. Program the value in the STRELOAD register.
2. Clear the STCURRENT register by writing to it with any value.
3. Configure the STCTRL register for the required operation.
Note:
When the processor is halted for debugging, the counter does not decrement.
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3.1.2
Nested Vectored Interrupt Controller (NVIC)
This section describes the Nested Vectored Interrupt Controller (NVIC) and the registers it uses.
The NVIC supports:
■ 72 interrupts.
■ A programmable priority level of 0-7 for each interrupt. A higher level corresponds to a lower
priority, so level 0 is the highest interrupt priority.
■ Low-latency exception and interrupt handling.
■ Level and pulse detection of interrupt signals.
■ Dynamic reprioritization of interrupts.
■ Grouping of priority values into group priority and subpriority fields.
■ Interrupt tail-chaining.
■ An external Non-maskable interrupt (NMI).
The processor automatically stacks its state on exception entry and unstacks this state on exception
exit, with no instruction overhead, providing low latency exception handling.
3.1.2.1
Level-Sensitive and Pulse Interrupts
The processor supports both level-sensitive and pulse interrupts. Pulse interrupts are also described
as edge-triggered interrupts.
A level-sensitive interrupt is held asserted until the peripheral deasserts the interrupt signal. Typically
this happens because the ISR accesses the peripheral, causing it to clear the interrupt request. A
pulse interrupt is an interrupt signal sampled synchronously on the rising edge of the processor
clock. To ensure the NVIC detects the interrupt, the peripheral must assert the interrupt signal for
at least one clock cycle, during which the NVIC detects the pulse and latches the interrupt.
When the processor enters the ISR, it automatically removes the pending state from the interrupt
(see “Hardware and Software Control of Interrupts” on page 119 for more information). For a
level-sensitive interrupt, if the signal is not deasserted before the processor returns from the ISR,
the interrupt becomes pending again, and the processor must execute its ISR again. As a result,
the peripheral can hold the interrupt signal asserted until it no longer needs servicing.
3.1.2.2
Hardware and Software Control of Interrupts
The Cortex-M4 latches all interrupts. A peripheral interrupt becomes pending for one of the following
reasons:
■ The NVIC detects that the interrupt signal is High and the interrupt is not active.
■ The NVIC detects a rising edge on the interrupt signal.
■ Software writes to the corresponding interrupt set-pending register bit, or to the Software Trigger
Interrupt (SWTRIG) register to make a Software-Generated Interrupt pending. See the INT bit
in the PEND0 register on page 141 or SWTRIG on page 151.
A pending interrupt remains pending until one of the following:
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■ The processor enters the ISR for the interrupt, changing the state of the interrupt from pending
to active. Then:
– For a level-sensitive interrupt, when the processor returns from the ISR, the NVIC samples
the interrupt signal. If the signal is asserted, the state of the interrupt changes to pending,
which might cause the processor to immediately re-enter the ISR. Otherwise, the state of the
interrupt changes to inactive.
– For a pulse interrupt, the NVIC continues to monitor the interrupt signal, and if this is pulsed
the state of the interrupt changes to pending and active. In this case, when the processor
returns from the ISR the state of the interrupt changes to pending, which might cause the
processor to immediately re-enter the ISR.
If the interrupt signal is not pulsed while the processor is in the ISR, when the processor
returns from the ISR the state of the interrupt changes to inactive.
■ Software writes to the corresponding interrupt clear-pending register bit
– For a level-sensitive interrupt, if the interrupt signal is still asserted, the state of the interrupt
does not change. Otherwise, the state of the interrupt changes to inactive.
– For a pulse interrupt, the state of the interrupt changes to inactive, if the state was pending
or to active, if the state was active and pending.
3.1.3
System Control Block (SCB)
The System Control Block (SCB) provides system implementation information and system control,
including configuration, control, and reporting of the system exceptions.
3.1.4
Memory Protection Unit (MPU)
This section describes the Memory protection unit (MPU). The MPU divides the memory map into
a number of regions and defines the location, size, access permissions, and memory attributes of
each region. The MPU supports independent attribute settings for each region, overlapping regions,
and export of memory attributes to the system.
The memory attributes affect the behavior of memory accesses to the region. The Cortex-M4 MPU
defines eight separate memory regions, 0-7, and a background region.
When memory regions overlap, a memory access is affected by the attributes of the region with the
highest number. For example, the attributes for region 7 take precedence over the attributes of any
region that overlaps region 7.
The background region has the same memory access attributes as the default memory map, but is
accessible from privileged software only.
The Cortex-M4 MPU memory map is unified, meaning that instruction accesses and data accesses
have the same region settings.
If a program accesses a memory location that is prohibited by the MPU, the processor generates
a memory management fault, causing a fault exception and possibly causing termination of the
process in an OS environment. In an OS environment, the kernel can update the MPU region setting
dynamically based on the process to be executed. Typically, an embedded OS uses the MPU for
memory protection.
Configuration of MPU regions is based on memory types (see “Memory Regions, Types and
Attributes” on page 90 for more information).
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Table 3-2 on page 121 shows the possible MPU region attributes. See the section called “MPU
Configuration for a Tiva™ C Series Microcontroller” on page 125 for guidelines for programming a
microcontroller implementation.
Table 3-2. Memory Attributes Summary
Memory Type
Description
Strongly Ordered
All accesses to Strongly Ordered memory occur in program order.
Device
Memory-mapped peripherals
Normal
Normal memory
To avoid unexpected behavior, disable the interrupts before updating the attributes of a region that
the interrupt handlers might access.
Ensure software uses aligned accesses of the correct size to access MPU registers:
■ Except for the MPU Region Attribute and Size (MPUATTR) register, all MPU registers must
be accessed with aligned word accesses.
■ The MPUATTR register can be accessed with byte or aligned halfword or word accesses.
The processor does not support unaligned accesses to MPU registers.
When setting up the MPU, and if the MPU has previously been programmed, disable unused regions
to prevent any previous region settings from affecting the new MPU setup.
3.1.4.1
Updating an MPU Region
To update the attributes for an MPU region, the MPU Region Number (MPUNUMBER), MPU
Region Base Address (MPUBASE) and MPUATTR registers must be updated. Each register can
be programmed separately or with a multiple-word write to program all of these registers. You can
use the MPUBASEx and MPUATTRx aliases to program up to four regions simultaneously using
an STM instruction.
Updating an MPU Region Using Separate Words
This example simple code configures one region:
; R1 = region number
; R2 = size/enable
; R3 = attributes
; R4 = address
LDR R0,=MPUNUMBER
STR R1, [R0, #0x0]
STR R4, [R0, #0x4]
STRH R2, [R0, #0x8]
STRH R3, [R0, #0xA]
;
;
;
;
;
0xE000ED98, MPU region number register
Region Number
Region Base Address
Region Size and Enable
Region Attribute
Disable a region before writing new region settings to the MPU if you have previously enabled the
region being changed. For example:
; R1 = region number
; R2 = size/enable
; R3 = attributes
; R4 = address
LDR R0,=MPUNUMBER
; 0xE000ED98, MPU region number register
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STR R1, [R0, #0x0]
BIC R2, R2, #1
STRH R2, [R0, #0x8]
STR R4, [R0, #0x4]
STRH R3, [R0, #0xA]
ORR R2, #1
STRH R2, [R0, #0x8]
;
;
;
;
;
;
;
Region Number
Disable
Region Size and Enable
Region Base Address
Region Attribute
Enable
Region Size and Enable
Software must use memory barrier instructions:
■ Before MPU setup, if there might be outstanding memory transfers, such as buffered writes, that
might be affected by the change in MPU settings.
■ After MPU setup, if it includes memory transfers that must use the new MPU settings.
However, memory barrier instructions are not required if the MPU setup process starts by entering
an exception handler, or is followed by an exception return, because the exception entry and
exception return mechanism cause memory barrier behavior.
Software does not need any memory barrier instructions during MPU setup, because it accesses
the MPU through the Private Peripheral Bus (PPB), which is a Strongly Ordered memory region.
For example, if all of the memory access behavior is intended to take effect immediately after the
programming sequence, then a DSB instruction and an ISB instruction should be used. A DSB is
required after changing MPU settings, such as at the end of context switch. An ISB is required if
the code that programs the MPU region or regions is entered using a branch or call. If the
programming sequence is entered using a return from exception, or by taking an exception, then
an ISB is not required.
Updating an MPU Region Using Multi-Word Writes
The MPU can be programmed directly using multi-word writes, depending how the information is
divided. Consider the following reprogramming:
; R1 = region number
; R2 = address
; R3 = size, attributes in one
LDR R0, =MPUNUMBER ; 0xE000ED98, MPU region number register
STR R1, [R0, #0x0] ; Region Number
STR R2, [R0, #0x4] ; Region Base Address
STR R3, [R0, #0x8] ; Region Attribute, Size and Enable
An STM instruction can be used to optimize this:
; R1 = region number
; R2 = address
; R3 = size, attributes in one
LDR R0, =MPUNUMBER ; 0xE000ED98, MPU region number register
STM R0, {R1-R3}
; Region number, address, attribute, size and enable
This operation can be done in two words for prepacked information, meaning that the MPU Region
Base Address (MPUBASE) register (see page 185) contains the required region number and has
the VALID bit set. This method can be used when the data is statically packed, for example in a
boot loader:
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; R1 = address and region number in one
; R2 = size and attributes in one
LDR R0, =MPUBASE
; 0xE000ED9C, MPU Region Base register
STR R1, [R0, #0x0] ; Region base address and region number combined
; with VALID (bit 4) set
STR R2, [R0, #0x4] ; Region Attribute, Size and Enable
Subregions
Regions of 256 bytes or more are divided into eight equal-sized subregions. Set the corresponding
bit in the SRD field of the MPU Region Attribute and Size (MPUATTR) register (see page 187) to
disable a subregion. The least-significant bit of the SRD field controls the first subregion, and the
most-significant bit controls the last subregion. Disabling a subregion means another region
overlapping the disabled range matches instead. If no other enabled region overlaps the disabled
subregion, the MPU issues a fault.
Regions of 32, 64, and 128 bytes do not support subregions. With regions of these sizes, the SRD
field must be configured to 0x00, otherwise the MPU behavior is unpredictable.
Example of SRD Use
Two regions with the same base address overlap. Region one is 128 KB, and region two is 512 KB.
To ensure the attributes from region one apply to the first 128 KB region, configure the SRD field for
region two to 0x03 to disable the first two subregions, as Figure 3-1 on page 123 shows.
Figure 3-1. SRD Use Example
Region 2, with
subregions
Region 1
Base address of both regions
3.1.4.2
Offset from
base address
512KB
448KB
384KB
320KB
256KB
192KB
128KB
Disabled subregion
64KB
Disabled subregion
0
MPU Access Permission Attributes
The access permission bits, TEX, S, C, B, AP, and XN of the MPUATTR register, control access to
the corresponding memory region. If an access is made to an area of memory without the required
permissions, then the MPU generates a permission fault.
Table 3-3 on page 123 shows the encodings for the TEX, C, B, and S access permission bits. All
encodings are shown for completeness, however the current implementation of the Cortex-M4 does
not support the concept of cacheability or shareability. Refer to the section called “MPU Configuration
for a Tiva™ C Series Microcontroller” on page 125 for information on programming the MPU for
TM4C1237H6PZ implementations.
Table 3-3. TEX, S, C, and B Bit Field Encoding
TEX
S
000b
x
000
B
Memory Type
Shareability
Other Attributes
0
0
Strongly Ordered
Shareable
-
a
0
1
Device
Shareable
-
x
C
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Table 3-3. TEX, S, C, and B Bit Field Encoding (continued)
TEX
S
C
B
Memory Type
Shareability
000
0
1
0
Normal
Not shareable
000
1
1
0
Normal
Shareable
000
0
1
1
Normal
Not shareable
000
1
1
1
Normal
Shareable
Other Attributes
Outer and inner
write-through. No write
allocate.
001
0
0
0
Normal
Not shareable
001
1
0
0
Normal
Shareable
Outer and inner
non-cacheable.
001
x
a
0
1
Reserved encoding
-
-
a
001
x
1
0
Reserved encoding
-
-
001
0
1
1
Normal
Not shareable
001
1
1
1
Normal
Shareable
Outer and inner
write-back. Write and
read allocate.
010
x
a
0
0
Device
Not shareable
Nonshared Device.
a
a
010
x
0
1
Reserved encoding
-
-
010
x
1
x
Reserved encoding
-
-
1BB
0
A
A
Normal
Not shareable
1BB
1
A
A
Normal
Shareable
Cached memory (BB =
outer policy, AA = inner
policy).
a
See Table 3-4 for the
encoding of the AA and
BB bits.
a. The MPU ignores the value of this bit.
Table 3-4 on page 124 shows the cache policy for memory attribute encodings with a TEX value in
the range of 0x4-0x7.
Table 3-4. Cache Policy for Memory Attribute Encoding
Encoding, AA or BB
Corresponding Cache Policy
00
Non-cacheable
01
Write back, write and read allocate
10
Write through, no write allocate
11
Write back, no write allocate
Table 3-5 on page 124 shows the AP encodings in the MPUATTR register that define the access
permissions for privileged and unprivileged software.
Table 3-5. AP Bit Field Encoding
AP Bit Field
Privileged
Permissions
Unprivileged
Permissions
Description
000
No access
No access
All accesses generate a permission fault.
001
RW
No access
Access from privileged software only.
010
RW
RO
Writes by unprivileged software generate a
permission fault.
011
RW
RW
Full access.
100
Unpredictable
Unpredictable
Reserved.
101
RO
No access
Reads by privileged software only.
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Table 3-5. AP Bit Field Encoding (continued)
AP Bit Field
Privileged
Permissions
Unprivileged
Permissions
Description
110
RO
RO
Read-only, by privileged or unprivileged software.
111
RO
RO
Read-only, by privileged or unprivileged software.
MPU Configuration for a Tiva™ C Series Microcontroller
Tiva™ C Series microcontrollers have only a single processor and no caches. As a result, the MPU
should be programmed as shown in Table 3-6 on page 125.
Table 3-6. Memory Region Attributes for Tiva™ C Series Microcontrollers
Memory Region
TEX
S
C
B
Memory Type and Attributes
Flash memory
000b
0
1
0
Normal memory, non-shareable, write-through
Internal SRAM
000b
1
1
0
Normal memory, shareable, write-through
External SRAM
000b
1
1
1
Normal memory, shareable, write-back,
write-allocate
Peripherals
000b
1
0
1
Device memory, shareable
In current Tiva™ C Series microcontroller implementations, the shareability and cache policy
attributes do not affect the system behavior. However, using these settings for the MPU regions
can make the application code more portable. The values given are for typical situations.
3.1.4.3
MPU Mismatch
When an access violates the MPU permissions, the processor generates a memory management
fault (see “Exceptions and Interrupts” on page 87 for more information). The MFAULTSTAT register
indicates the cause of the fault. See page 172 for more information.
3.1.5
Floating-Point Unit (FPU)
This section describes the Floating-Point Unit (FPU) and the registers it uses. The FPU provides:
■ 32-bit instructions for single-precision (C float) data-processing operations
■ Combined multiply and accumulate instructions for increased precision (Fused MAC)
■ Hardware support for conversion, addition, subtraction, multiplication with optional accumulate,
division, and square-root
■ Hardware support for denormals and all IEEE rounding modes
■ 32 dedicated 32-bit single-precision registers, also addressable as 16 double-word registers
■ Decoupled three stage pipeline
The Cortex-M4F FPU fully supports single-precision add, subtract, multiply, divide, multiply and
accumulate, and square root operations. It also provides conversions between fixed-point and
floating-point data formats, and floating-point constant instructions. The FPU provides floating-point
computation functionality that is compliant with the ANSI/IEEE Std 754-2008, IEEE Standard for
Binary Floating-Point Arithmetic, referred to as the IEEE 754 standard. The FPU's single-precision
extension registers can also be accessed as 16 doubleword registers for load, store, and move
operations.
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3.1.5.1
FPU Views of the Register Bank
The FPU provides an extension register file containing 32 single-precision registers. These can be
viewed as:
■ Sixteen 64-bit doubleword registers, D0-D15
■ Thirty-two 32-bit single-word registers, S0-S31
■ A combination of registers from the above views
Figure 3-2. FPU Register Bank
S0
S1
S2
S3
S4
S5
S6
S7
...
S28
S29
S30
S31
D0
D1
D2
D3
...
D14
D15
The mapping between the registers is as follows:
■ S maps to the least significant half of D
■ S maps to the most significant half of D
For example, you can access the least significant half of the value in D6 by accessing S12, and the
most significant half of the elements by accessing S13.
3.1.5.2
Modes of Operation
The FPU provides three modes of operation to accommodate a variety of applications.
Full-Compliance mode. In Full-Compliance mode, the FPU processes all operations according to
the IEEE 754 standard in hardware.
Flush-to-Zero mode. Setting the FZ bit of the Floating-Point Status and Control (FPSC) register
enables Flush-to-Zero mode. In this mode, the FPU treats all subnormal input operands of arithmetic
CDP operations as zeros in the operation. Exceptions that result from a zero operand are signalled
appropriately. VABS, VNEG, and VMOV are not considered arithmetic CDP operations and are not
affected by Flush-to-Zero mode. A result that is tiny, as described in the IEEE 754 standard, where
the destination precision is smaller in magnitude than the minimum normal value before rounding,
is replaced with a zero. The IDC bit in FPSC indicates when an input flush occurs. The UFC bit in
FPSC indicates when a result flush occurs.
Default NaN mode. Setting the DN bit in the FPSC register enables default NaN mode. In this mode,
the result of any arithmetic data processing operation that involves an input NaN, or that generates
a NaN result, returns the default NaN. Propagation of the fraction bits is maintained only by VABS,
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VNEG, and VMOV operations. All other CDP operations ignore any information in the fraction bits
of an input NaN.
3.1.5.3
Compliance with the IEEE 754 standard
When Default NaN (DN) and Flush-to-Zero (FZ) modes are disabled, FPv4 functionality is compliant
with the IEEE 754 standard in hardware. No support code is required to achieve this compliance.
3.1.5.4
Complete Implementation of the IEEE 754 standard
The Cortex-M4F floating point instruction set does not support all operations defined in the IEEE
754-2008 standard. Unsupported operations include, but are not limited to the following:
■ Remainder
■ Round floating-point number to integer-valued floating-point number
■ Binary-to-decimal conversions
■ Decimal-to-binary conversions
■ Direct comparison of single-precision and double-precision values
The Cortex-M4 FPU supports fused MAC operations as described in the IEEE standard. For complete
implementation of the IEEE 754-2008 standard, floating-point functionality must be augmented with
library functions.
3.1.5.5
IEEE 754 standard implementation choices
NaN handling
All single-precision values with the maximum exponent field value and a nonzero fraction field are
valid NaNs. A most-significant fraction bit of zero indicates a Signaling NaN (SNaN). A one indicates
a Quiet NaN (QNaN). Two NaN values are treated as different NaNs if they differ in any bit. The
below table shows the default NaN values.
Sign
Fraction
Fraction
0
0xFF
bit [22] = 1, bits [21:0] are all zeros
Processing of input NaNs for ARM floating-point functionality and libraries is defined as follows:
■ In full-compliance mode, NaNs are handled as described in the ARM Architecture Reference
Manual. The hardware processes the NaNs directly for arithmetic CDP instructions. For data
transfer operations, NaNs are transferred without raising the Invalid Operation exception. For
the non-arithmetic CDP instructions, VABS, VNEG, and VMOV, NaNs are copied, with a change
of sign if specified in the instructions, without causing the Invalid Operation exception.
■ In default NaN mode, arithmetic CDP instructions involving NaN operands return the default
NaN regardless of the fractions of any NaN operands. SNaNs in an arithmetic CDP operation
set the IOC flag, FPSCR[0]. NaN handling by data transfer and non-arithmetic CDP instructions
is the same as in full-compliance mode.
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Table 3-7. QNaN and SNaN Handling
Instruction Type
Default NaN
Mode
With QNaN Operand
With SNaN Operand
Off
The QNaN or one of the QNaN operands,
if there is more than one, is returned
according to the rules given in the ARM
Architecture Reference Manual.
IOC set. The SNaN is quieted and the
result NaN is determined by the rules
given in the ARM Architecture Reference
Manual.
On
Default NaN returns.
IOC set. Default NaN returns.
Arithmetic CDP
Non-arithmetic CDP Off/On
a
a
NaN passes to destination with sign changed as appropriate.
FCMP(Z)
-
Unordered compare.
IOC set. Unordered compare.
FCMPE(Z)
-
IOC set. Unordered compare.
IOC set. Unordered compare.
Load/store
Off/On
All NaNs transferred.
a. IOC is the Invalid Operation exception flag, FPSCR[0].
Comparisons
Comparison results modify the flags in the FPSCR. You can use the MVRS APSR_nzcv instruction
(formerly FMSTAT) to transfer the current flags from the FPSCR to the APSR. See the ARM
Architecture Reference Manual for mapping of IEEE 754-2008 standard predicates to ARM conditions.
The flags used are chosen so that subsequent conditional execution of ARM instructions can test
the predicates defined in the IEEE standard.
Underflow
The Cortex-M4F FPU uses the before rounding form of tininess and the inexact result form of loss
of accuracy as described in the IEEE 754-2008 standard to generate Underflow exceptions.
In flush-to-zero mode, results that are tiny before rounding, as described in the IEEE standard, are
flushed to a zero, and the UFC flag, FPSCR[3], is set. See the ARM Architecture Reference Manual
for information on flush-to-zero mode.
When the FPU is not in flush-to-zero mode, operations are performed on subnormal operands. If
the operation does not produce a tiny result, it returns the computed result, and the UFC flag,
FPSCR[3], is not set. The IXC flag, FPSCR[4], is set if the operation is inexact. If the operation
produces a tiny result, the result is a subnormal or zero value, and the UFC flag, FPSCR[3], is set
if the result was also inexact.
3.1.5.6
Exceptions
The FPU sets the cumulative exception status flag in the FPSCR register as required for each
instruction, in accordance with the FPv4 architecture. The FPU does not support user-mode traps.
The exception enable bits in the FPSCR read-as-zero, and writes are ignored. The processor also
has six output pins, FPIXC, FPUFC, FPOFC, FPDZC, FPIDC, and FPIOC, that each reflect the
status of one of the cumulative exception flags. For a description of these outputs, see the ARM
Cortex-M4 Integration and Implementation Manual (ARM DII 0239, available from ARM).
The processor can reduce the exception latency by using lazy stacking. See Auxiliary Control
Register, ACTLR on page 4-5. This means that the processor reserves space on the stack for the
FP state, but does not save that state information to the stack. See the ARMv7-M Architecture
Reference Manual (available from ARM) for more information.
3.1.5.7
Enabling the FPU
The FPU is disabled from reset. You must enable it before you can use any floating-point instructions.
The processor must be in privileged mode to read from and write to the Coprocessor Access
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Control (CPAC) register. The below example code sequence enables the FPU in both privileged
and user modes.
; CPACR is located at address 0xE000ED88
LDR.W R0, =0xE000ED88
; Read CPACR
LDR R1, [R0]
; Set bits 20-23 to enable CP10 and CP11 coprocessors
ORR R1, R1, #(0xF GPTMTnILR
GPTMnMATCHR
CounterValue
GPTMnILR
CCP
CCP set if GPTMnMATCHR ≠ GPTMnILR
Figure 11-7 on page 707 shows how the CCP output operates when the PLO and MRSU bits are set
and the GPTMTnMATCHR value is the same as the GPTMTnILR value. In this situation, if the PLO
bit is 0, the CCP signal goes high when the GPTMTnILR value is loaded and the match would be
essentially ignored.
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Figure 11-7. CCP Output, GPTMTnMATCHR = GPTMTnILR
GPTMnMATCHR
CounterValue
GPTMnILR
CCP
CCP not set if GPTMnMATCHR = GPTMnILR
Figure 11-8 on page 707 shows how the CCP output operates when the PLO and MRSU bits are set
and the GPTMTnILR is greater than the GPTMTnMATCHR value.
Figure 11-8. CCP Output, GPTMTnILR > GPTMTnMATCHR
GPTMnILR
GPTMnMATCHR = GPTMnILR-1
GPTMnMATCHR = GPTMnILR-2
GPTMnMATCHR == 0
11.3.3
CCP
Pulse width is 1 clock when GPTMnMATCHR = GPTMnILR - 1
CCP
Pulse width is 2 clocks when GPTMnMATCHR = GPTMnILR - 2
CCP
Pulse width is GPTMnILR clocks when GPTMnMATCHR= 0
Wait-for-Trigger Mode
The Wait-for-Trigger mode allows daisy chaining of the timer modules such that once configured,
a single timer can initiate multiple timing events using the Timer triggers. Wait-for-Trigger mode is
enabled by setting the TnWOT bit in the GPTMTnMR register. When the TnWOT bit is set, Timer N+1
does not begin counting until the timer in the previous position in the daisy chain (Timer N) reaches
its time-out event. The daisy chain is configured such that GPTM1 always follows GPTM0, GPTM2
follows GPTM1, and so on. If Timer A is configured as a 32-bit (16/32-bit mode) or 64-bit (32/64-bit
wide mode) timer (controlled by the GPTMCFG field in the GPTMCFG register), it triggers Timer A
in the next module. If Timer A is configured as a 16-bit (16/32-bit mode) or 32-bit (32/64-bit wide
mode) timer, it triggers Timer B in the same module, and Timer B triggers Timer A in the next module.
Care must be taken that the TAWOT bit is never set in GPTM0. Figure 11-9 on page 708 shows how
the GPTMCFG bit affects the daisy chain. This function is valid for one-shot, periodic, and PWM
modes.
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Figure 11-9. Timer Daisy Chain
GP Timer N+1
1
0
GPTMTnMR.TnWOT
Timer B ADC Trigger
Timer B
Timer A
Timer A ADC Trigger
GP Timer N
1
0
GPTMTnMR.TnWOT
Timer B ADC Trigger
Timer B
Timer A
11.3.4
Timer A ADC Trigger
Synchronizing GP Timer Blocks
The GPTM Synchronizer Control (GPTMSYNC) register in the GPTM0 block can be used to
synchronize selected timers to begin counting at the same time. Setting a bit in the GPTMSYNC
register causes the associated timer to perform the actions of a timeout event. An interrupt is not
generated when the timers are synchronized. If a timer is being used in concatenated mode, only
the bit for Timer A must be set in the GPTMSYNC register.
Note:
All timers must use the same clock source for this feature to work correctly.
Table 11-11 on page 708 shows the actions for the timeout event performed when the timers are
synchronized in the various timer modes.
Table 11-11. Timeout Actions for GPTM Modes
Mode
Count Dir
Time Out Action
32- and 64-bit One-Shot ─
(concatenated timers)
N/A
32- and 64-bit Periodic
(concatenated timers)
Down
Count value = ILR
Up
Count value = 0
32- and 64-bit RTC
(concatenated timers)
Up
Count value = 0
16- and 32- bit One Shot ─
(individual/split timers)
N/A
16- and 32- bit Periodic Down
(individual/split timers)
Up
Count value = ILR
16- and 32- bit
Edge-Count
(individual/split timers)
Down
Count value = ILR
Up
Count value = 0
16- and 32- bit
Edge-Time
(individual/split timers)
Down
Count value = ILR
Up
Count value = 0
16- and 32-bit PWM
Down
Count value = ILR
Count value = 0
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11.3.5
DMA Operation
The timers each have a dedicated μDMA channel and can provide a request signal to the μDMA
controller. The request is a burst type and occurs whenever a timer raw interrupt condition occurs.
The arbitration size of the μDMA transfer should be set to the amount of data that should be
transferred whenever a timer event occurs.
For example, to transfer 256 items, 8 items at a time every 10 ms, configure a timer to generate a
periodic timeout at 10 ms. Configure the μDMA transfer for a total of 256 items, with a burst size of
8 items. Each time the timer times out, the μDMA controller transfers 8 items, until all 256 items
have been transferred.
No other special steps are needed to enable Timers for μDMA operation. Refer to “Micro Direct
Memory Access (μDMA)” on page 570 for more details about programming the μDMA controller.
11.3.6
Accessing Concatenated 16/32-Bit GPTM Register Values
The GPTM is placed into concatenated mode by writing a 0x0 or a 0x1 to the GPTMCFG bit field in
the GPTM Configuration (GPTMCFG) register. In both configurations, certain 16/32-bit GPTM
registers are concatenated to form pseudo 32-bit registers. These registers include:
■ GPTM Timer A Interval Load (GPTMTAILR) register [15:0], see page 745
■ GPTM Timer B Interval Load (GPTMTBILR) register [15:0], see page 746
■ GPTM Timer A (GPTMTAR) register [15:0], see page 753
■ GPTM Timer B (GPTMTBR) register [15:0], see page 754
■ GPTM Timer A Value (GPTMTAV) register [15:0], see page 755
■ GPTM Timer B Value (GPTMTBV) register [15:0], see page 756
■ GPTM Timer A Match (GPTMTAMATCHR) register [15:0], see page 747
■ GPTM Timer B Match (GPTMTBMATCHR) register [15:0], see page 748
In the 32-bit modes, the GPTM translates a 32-bit write access to GPTMTAILR into a write access
to both GPTMTAILR and GPTMTBILR. The resulting word ordering for such a write operation is:
GPTMTBILR[15:0]:GPTMTAILR[15:0]
Likewise, a 32-bit read access to GPTMTAR returns the value:
GPTMTBR[15:0]:GPTMTAR[15:0]
A 32-bit read access to GPTMTAV returns the value:
GPTMTBV[15:0]:GPTMTAV[15:0]
11.3.7
Accessing Concatenated 32/64-Bit Wide GPTM Register Values
On the 32/64-bit wide GPTM blocks, concatenated register values (64-bits and 48-bits) are not
readily available as the bit width for these accesses is greater than the bus width of the processor
core. In the concatenated timer modes and the individual timer modes when using the prescaler,
software must perform atomic accesses for the value to be coherent. When reading timer values
that are greater than 32 bits, software should follow these steps:
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1. Read the appropriate Timer B register or prescaler register.
2. Read the corresponding Timer A register.
3. Re-read the Timer B register or prescaler register.
4. Compare the Timer B or prescaler values from the first and second reads. If they are the same,
the timer value is coherent. If they are not the same, repeat steps 1-4 once more so that they
are the same.
The following pseudo code illustrates this process:
high = timer_high;
low = timer_low;
if (high != timer_high);
//low overflowed into high
{
high = timer_high;
low = timer_low;
}
The registers that must be read in this manner are shown below:
■ 64-bit reads
– GPTMTAV and GPTMTBV
– GPTMTAR and GPTMTBR
■ 48-bit reads
– GPTMTAR and GPTMTAPS
– GPTMTBR and GPTMTBPS
– GPTMTAV and GPTMTAPV
– GPTMTBV and GPTMTBPV
Similarly, write accesses must also be performed by writing the upper bits prior to writing the lower
bits as follows:
1. Write the appropriate Timer B register or prescaler register.
2. Write the corresponding Timer A register.
The registers that must be written in this manner are shown below:
■ 64-bit writes
– GPTMTAV and GPTMTBV
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– GPTMTAMATCHR and GPTMTBMATCHR
– GPTMTAILR and GPTMTBILR
■ 48-bit writes
– GPTMTAV and GPTMTAPV
– GPTMTBV and GPTMTBPV
– GPTMTAMATCHR and GPTMTAPMR
– GPTMTBMATCHR and GPTMTBPMR
– GPTMTAILR and GPTMTAPR
– GPTMTBILR and GPTMTBPR
When writing a 64-bit value, If there are two consecutive writes to any of the registers listed above
under the "64-bit writes" heading, whether the register is in Timer A or Timer B, or if a register Timer
A is written prior to writing the corresponding register in Timer B, then an error is reported using the
WUERIS bit in the GPTMRIS register. This error can be promoted to interrupt if it is not masked.
Note that this error is not reported for the prescaler registers because use of the prescaler is optional.
As a result, programmers must take care to follow the protocol outlined above.
11.4
Initialization and Configuration
To use a GPTM, the appropriate TIMERn bit must be set in the RCGCTIMER or RCGCWTIMER
register (see page 329 and page 347). If using any CCP pins, the clock to the appropriate GPIO
module must be enabled via the RCGCGPIO register (see page 331). To find out which GPIO port
to enable, refer to Table 21-4 on page 1242. Configure the PMCn fields in the GPIOPCTL register to
assign the CCP signals to the appropriate pins (see page 677 and Table 21-5 on page 1249).
This section shows module initialization and configuration examples for each of the supported timer
modes.
11.4.1
One-Shot/Periodic Timer Mode
The GPTM is configured for One-Shot and Periodic modes by the following sequence:
1. Ensure the timer is disabled (the TnEN bit in the GPTMCTL register is cleared) before making
any changes.
2. Write the GPTM Configuration Register (GPTMCFG) with a value of 0x0000.0000.
3. Configure the TnMR field in the GPTM Timer n Mode Register (GPTMTnMR):
a. Write a value of 0x1 for One-Shot mode.
b. Write a value of 0x2 for Periodic mode.
4. Optionally configure the TnSNAPS, TnWOT, TnMTE, and TnCDIR bits in the GPTMTnMR register
to select whether to capture the value of the free-running timer at time-out, use an external
trigger to start counting, configure an additional trigger or interrupt, and count up or down.
5. Load the start value into the GPTM Timer n Interval Load Register (GPTMTnILR).
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6. If interrupts are required, set the appropriate bits in the GPTM Interrupt Mask Register
(GPTMIMR).
7. Set the TnEN bit in the GPTMCTL register to enable the timer and start counting.
8. Poll the GPTMRIS register or wait for the interrupt to be generated (if enabled). In both cases,
the status flags are cleared by writing a 1 to the appropriate bit of the GPTM Interrupt Clear
Register (GPTMICR).
If the TnMIE bit in the GPTMTnMR register is set, the RTCRIS bit in the GPTMRIS register is set,
and the timer continues counting. In One-Shot mode, the timer stops counting after the time-out
event. To re-enable the timer, repeat the sequence. A timer configured in Periodic mode reloads
the timer and continues counting after the time-out event.
11.4.2
Real-Time Clock (RTC) Mode
To use the RTC mode, the timer must have a 32.768-KHz input signal on an even CCP input. To
enable the RTC feature, follow these steps:
1. Ensure the timer is disabled (the TAEN bit is cleared) before making any changes.
2. If the timer has been operating in a different mode prior to this, clear any residual set bits in the
GPTM Timer n Mode (GPTMTnMR) register before reconfiguring.
3. Write the GPTM Configuration Register (GPTMCFG) with a value of 0x0000.0001.
4. Write the match value to the GPTM Timer n Match Register (GPTMTnMATCHR).
5. Set/clear the RTCEN and TnSTALL bit in the GPTM Control Register (GPTMCTL) as needed.
6. If interrupts are required, set the RTCIM bit in the GPTM Interrupt Mask Register (GPTMIMR).
7. Set the TAEN bit in the GPTMCTL register to enable the timer and start counting.
When the timer count equals the value in the GPTMTnMATCHR register, the GPTM asserts the
RTCRIS bit in the GPTMRIS register and continues counting until Timer A is disabled or a hardware
reset. The interrupt is cleared by writing the RTCCINT bit in the GPTMICR register. Note that if the
GPTMTnILR register is loaded with a new value, the timer begins counting at this new value and
continues until it reaches 0xFFFF.FFFF, at which point it rolls over.
11.4.3
Input Edge-Count Mode
A timer is configured to Input Edge-Count mode by the following sequence:
1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes.
2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x0000.0004.
3. In the GPTM Timer Mode (GPTMTnMR) register, write the TnCMR field to 0x0 and the TnMR
field to 0x3.
4. Configure the type of event(s) that the timer captures by writing the TnEVENT field of the GPTM
Control (GPTMCTL) register.
5. Program registers according to count direction:
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■ In down-count mode, the GPTMTnMATCHR and GPTMTnPMR registers are configured so
that the difference between the value in the GPTMTnILR and GPTMTnPR registers and the
GPTMTnMATCHR and GPTMTnPMR registers equals the number of edge events that must
be counted.
■ In up-count mode, the timer counts from 0x0 to the value in the GPTMTnMATCHR and
GPTMTnPMR registers. Note that when executing an up-count, the value of the GPTMTnPR
and GPTMTnILR must be greater than the value of GPTMTnPMR and GPTMTnMATCHR.
6. If interrupts are required, set the CnMIM bit in the GPTM Interrupt Mask (GPTMIMR) register.
7. Set the TnEN bit in the GPTMCTL register to enable the timer and begin waiting for edge events.
8. Poll the CnMRIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled).
In both cases, the status flags are cleared by writing a 1 to the CnMCINT bit of the GPTM
Interrupt Clear (GPTMICR) register.
When counting down in Input Edge-Count Mode, the timer stops after the programmed number of
edge events has been detected. To re-enable the timer, ensure that the TnEN bit is cleared and
repeat steps 4 through 8.
11.4.4
Input Edge Time Mode
A timer is configured to Input Edge Time mode by the following sequence:
1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes.
2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x0000.0004.
3. In the GPTM Timer Mode (GPTMTnMR) register, write the TnCMR field to 0x1 and the TnMR
field to 0x3 and select a count direction by programming the TnCDIR bit.
4. Configure the type of event that the timer captures by writing the TnEVENT field of the GPTM
Control (GPTMCTL) register.
5. If a prescaler is to be used, write the prescale value to the GPTM Timer n Prescale Register
(GPTMTnPR).
6. Load the timer start value into the GPTM Timer n Interval Load (GPTMTnILR) register.
7. If interrupts are required, set the CnEIM bit in the GPTM Interrupt Mask (GPTMIMR) register.
8. Set the TnEN bit in the GPTM Control (GPTMCTL) register to enable the timer and start counting.
9. Poll the CnERIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled).
In both cases, the status flags are cleared by writing a 1 to the CnECINT bit of the GPTM
Interrupt Clear (GPTMICR) register. The time at which the event happened can be obtained
by reading the GPTM Timer n (GPTMTnR) register.
In Input Edge Timing mode, the timer continues running after an edge event has been detected,
but the timer interval can be changed at any time by writing the GPTMTnILR register and clearing
the TnILD bit in the GPTMTnMR register. The change takes effect at the next cycle after the write.
11.4.5
PWM Mode
A timer is configured to PWM mode using the following sequence:
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1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes.
2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x0000.0004.
3. In the GPTM Timer Mode (GPTMTnMR) register, set the TnAMS bit to 0x1, the TnCMR bit to
0x0, and the TnMR field to 0x2.
4. Configure the output state of the PWM signal (whether or not it is inverted) in the TnPWML field
of the GPTM Control (GPTMCTL) register.
5. If a prescaler is to be used, write the prescale value to the GPTM Timer n Prescale Register
(GPTMTnPR).
6. If PWM interrupts are used, configure the interrupt condition in the TnEVENT field in the
GPTMCTL register and enable the interrupts by setting the TnPWMIE bit in the GPTMTnMR
register. Note that edge detect interrupt behavior is reversed when the PWM output is inverted
(see page 726).
7. Load the timer start value into the GPTM Timer n Interval Load (GPTMTnILR) register.
8. Load the GPTM Timer n Match (GPTMTnMATCHR) register with the match value.
9. Set the TnEN bit in the GPTM Control (GPTMCTL) register to enable the timer and begin
generation of the output PWM signal.
In PWM Time mode, the timer continues running after the PWM signal has been generated. The
PWM period can be adjusted at any time by writing the GPTMTnILR register, and the change takes
effect at the next cycle after the write.
11.5
Register Map
Table 11-12 on page 715 lists the GPTM registers. The offset listed is a hexadecimal increment to
the register's address, relative to that timer's base address:
■
■
■
■
■
■
■
■
■
■
■
■
16/32-bit Timer 0: 0x4003.0000
16/32-bit Timer 1: 0x4003.1000
16/32-bit Timer 2: 0x4003.2000
16/32-bit Timer 3: 0x4003.3000
16/32-bit Timer 4: 0x4003.4000
16/32-bit Timer 5: 0x4003.5000
32/64-bit Wide Timer 0: 0x4003.6000
32/64-bit Wide Timer 1: 0x4003.7000
32/64-bit Wide Timer 2: 0x4004.C000
32/64-bit Wide Timer 3: 0x4004.D000
32/64-bit Wide Timer 4: 0x4004.E000
32/64-bit Wide Timer 5: 0x4004.F000
The SIZE field in the GPTM Peripheral Properties (GPTMPP) register identifies whether a module
has a 16/32-bit or 32/64-bit wide timer.
Note that the GP Timer module clock must be enabled before the registers can be programmed
(see page 329 or page 347). There must be a delay of 3 system clocks after the Timer module clock
is enabled before any Timer module registers are accessed.
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Table 11-12. Timers Register Map
Offset
Name
0x000
Reset
GPTMCFG
RW
0x0000.0000
GPTM Configuration
716
0x004
GPTMTAMR
RW
0x0000.0000
GPTM Timer A Mode
718
0x008
GPTMTBMR
RW
0x0000.0000
GPTM Timer B Mode
722
0x00C
GPTMCTL
RW
0x0000.0000
GPTM Control
726
0x010
GPTMSYNC
RW
0x0000.0000
GPTM Synchronize
730
0x018
GPTMIMR
RW
0x0000.0000
GPTM Interrupt Mask
734
0x01C
GPTMRIS
RO
0x0000.0000
GPTM Raw Interrupt Status
737
0x020
GPTMMIS
RO
0x0000.0000
GPTM Masked Interrupt Status
740
0x024
GPTMICR
W1C
0x0000.0000
GPTM Interrupt Clear
743
0x028
GPTMTAILR
RW
0xFFFF.FFFF
GPTM Timer A Interval Load
745
0x02C
GPTMTBILR
RW
-
GPTM Timer B Interval Load
746
0x030
GPTMTAMATCHR
RW
0xFFFF.FFFF
GPTM Timer A Match
747
0x034
GPTMTBMATCHR
RW
-
GPTM Timer B Match
748
0x038
GPTMTAPR
RW
0x0000.0000
GPTM Timer A Prescale
749
0x03C
GPTMTBPR
RW
0x0000.0000
GPTM Timer B Prescale
750
0x040
GPTMTAPMR
RW
0x0000.0000
GPTM TimerA Prescale Match
751
0x044
GPTMTBPMR
RW
0x0000.0000
GPTM TimerB Prescale Match
752
0x048
GPTMTAR
RO
0xFFFF.FFFF
GPTM Timer A
753
0x04C
GPTMTBR
RO
-
GPTM Timer B
754
0x050
GPTMTAV
RW
0xFFFF.FFFF
GPTM Timer A Value
755
0x054
GPTMTBV
RW
-
GPTM Timer B Value
756
0x058
GPTMRTCPD
RO
0x0000.7FFF
GPTM RTC Predivide
757
0x05C
GPTMTAPS
RO
0x0000.0000
GPTM Timer A Prescale Snapshot
758
0x060
GPTMTBPS
RO
0x0000.0000
GPTM Timer B Prescale Snapshot
759
0x064
GPTMTAPV
RO
0x0000.0000
GPTM Timer A Prescale Value
760
0x068
GPTMTBPV
RO
0x0000.0000
GPTM Timer B Prescale Value
761
0xFC0
GPTMPP
RO
0x0000.0000
GPTM Peripheral Properties
762
11.6
Description
See
page
Type
Register Descriptions
The remainder of this section lists and describes the GPTM registers, in numerical order by address
offset.
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Register 1: GPTM Configuration (GPTMCFG), offset 0x000
This register configures the global operation of the GPTM module. The value written to this register
determines whether the GPTM is in 32- or 64-bit mode (concatenated timers) or in 16- or 32-bit
mode (individual, split timers).
Important: Bits in this register should only be changed when the TAEN and TBEN bits in the
GPTMCTL register are cleared.
GPTM Configuration (GPTMCFG)
16/32-bit Timer 0 base: 0x4003.0000
16/32-bit Timer 1 base: 0x4003.1000
16/32-bit Timer 2 base: 0x4003.2000
16/32-bit Timer 3 base: 0x4003.3000
16/32-bit Timer 4 base: 0x4003.4000
16/32-bit Timer 5 base: 0x4003.5000
32/64-bit Wide Timer 0 base: 0x4003.6000
32/64-bit Wide Timer 1 base: 0x4003.7000
32/64-bit Wide Timer 2 base: 0x4004.C000
32/64-bit Wide Timer 3 base: 0x4004.D000
32/64-bit Wide Timer 4 base: 0x4004.E000
32/64-bit Wide Timer 5 base: 0x4004.F000
Offset 0x000
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
1
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
9
8
7
6
5
4
3
2
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:3
reserved
RO
0x0000.000
GPTMCFG
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
RW
0
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Bit/Field
Name
Type
Reset
2:0
GPTMCFG
RW
0x0
Description
GPTM Configuration
The GPTMCFG values are defined as follows:
Value
Description
0x0
For a 16/32-bit timer, this value selects the 32-bit timer
configuration.
For a 32/64-bit wide timer, this value selects the 64-bit timer
configuration.
0x1
For a 16/32-bit timer, this value selects the 32-bit real-time
clock (RTC) counter configuration.
For a 32/64-bit wide timer, this value selects the 64-bit
real-time clock (RTC) counter configuration.
0x2-0x3 Reserved
0x4
For a 16/32-bit timer, this value selects the 16-bit timer
configuration.
For a 32/64-bit wide timer, this value selects the 32-bit timer
configuration.
The function is controlled by bits 1:0 of GPTMTAMR and
GPTMTBMR.
0x5-0x7 Reserved
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Register 2: GPTM Timer A Mode (GPTMTAMR), offset 0x004
This register configures the GPTM based on the configuration selected in the GPTMCFG register.
When in PWM mode, set the TAAMS bit, clear the TACMR bit, and configure the TAMR field to 0x1 or
0x2.
This register controls the modes for Timer A when it is used individually. When Timer A and Timer
B are concatenated, this register controls the modes for both Timer A and Timer B, and the contents
of GPTMTBMR are ignored.
Important: Bits in this register should only be changed when the TAEN bit in the GPTMCTL register
is cleared.
GPTM Timer A Mode (GPTMTAMR)
16/32-bit Timer 0 base: 0x4003.0000
16/32-bit Timer 1 base: 0x4003.1000
16/32-bit Timer 2 base: 0x4003.2000
16/32-bit Timer 3 base: 0x4003.3000
16/32-bit Timer 4 base: 0x4003.4000
16/32-bit Timer 5 base: 0x4003.5000
32/64-bit Wide Timer 0 base: 0x4003.6000
32/64-bit Wide Timer 1 base: 0x4003.7000
32/64-bit Wide Timer 2 base: 0x4004.C000
32/64-bit Wide Timer 3 base: 0x4004.D000
32/64-bit Wide Timer 4 base: 0x4004.E000
32/64-bit Wide Timer 5 base: 0x4004.F000
Offset 0x004
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
TAMIE
TACDIR
TAAMS
TACMR
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
reserved
Type
Reset
TAPLO
RO
0
RO
0
TAMRSU TAPWMIE
RW
0
RW
0
RW
0
Bit/Field
Name
Type
Reset
31:12
reserved
RO
0x0000.00
11
TAPLO
RW
0
TAILD
RW
0
TASNAPS TAWOT
RW
0
RW
0
TAMR
RW
0
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPTM Timer A PWM Legacy Operation
Value Description
0
Legacy operation with CCP pin driven Low when the
GPTMTAILR is reloaded after the timer reaches 0.
1
CCP is driven High when the GPTMTAILR is reloaded after the
timer reaches 0.
This bit is only valid in PWM mode.
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Bit/Field
Name
Type
Reset
10
TAMRSU
RW
0
Description
GPTM Timer A Match Register Update
Value Description
0
Update the GPTMTAMATCHR register and the GPTMTAPR
register, if used, on the next cycle.
1
Update the GPTMTAMATCHR register and the GPTMTAPR
register, if used, on the next timeout.
If the timer is disabled (TAEN is clear) when this bit is set,
GPTMTAMATCHR and GPTMTAPR are updated when the timer is
enabled. If the timer is stalled (TASTALL is set), GPTMTAMATCHR and
GPTMTAPR are updated according to the configuration of this bit.
9
TAPWMIE
RW
0
GPTM Timer A PWM Interrupt Enable
This bit enables interrupts in PWM mode on rising, falling, or both edges
of the CCP output, as defined by the TAEVENT field in the GPTMCTL
register.
Value Description
0
Capture event interrupt is disabled.
1
Capture event interrupt is enabled.
This bit is only valid in PWM mode.
8
TAILD
RW
0
GPTM Timer A Interval Load Write
Value Description
0
Update the GPTMTAR and GPTMTAV registers with the value
in the GPTMTAILR register on the next cycle. Also update the
GPTMTAPS and GPTMTAPV registers with the value in the
GPTMTAPR register on the next cycle.
1
Update the GPTMTAR and GPTMTAV registers with the value
in the GPTMTAILR register on the next timeout. Also update
the GPTMTAPS and GPTMTAPV registers with the value in
the GPTMTAPR register on the next timeout.
Note the state of this bit has no effect when counting up.
The bit descriptions above apply if the timer is enabled and running. If
the timer is disabled (TAEN is clear) when this bit is set, GPTMTAR,
GPTMTAV and GPTMTAPs, and GPTMTAPV are updated when the
timer is enabled. If the timer is stalled (TASTALL is set), GPTMTAR and
GPTMTAPS are updated according to the configuration of this bit.
7
TASNAPS
RW
0
GPTM Timer A Snap-Shot Mode
Value Description
0
Snap-shot mode is disabled.
1
If Timer A is configured in the periodic mode, the actual
free-running, capture or snapshot value of Timer A is loaded at
the time-out event/capture or snapshot event into the GPTM
Timer A (GPTMTAR) register. If the timer prescaler is used,
the prescaler snapshot is loaded into the GPTM Timer A
(GPTMTAPR).
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Bit/Field
Name
Type
Reset
6
TAWOT
RW
0
Description
GPTM Timer A Wait-on-Trigger
Value Description
0
Timer A begins counting as soon as it is enabled.
1
If Timer A is enabled (TAEN is set in the GPTMCTL register),
Timer A does not begin counting until it receives a trigger from
the timer in the previous position in the daisy chain, see Figure
11-9 on page 708. This function is valid for one-shot, periodic,
and PWM modes.
This bit must be clear for GP Timer Module 0, Timer A.
5
TAMIE
RW
0
GPTM Timer A Match Interrupt Enable
Value Description
0
The match interrupt is disabled for match events.
Note:
1
4
TACDIR
RW
0
Clearing the TAMIE bit in the GPTMTAMR register
prevents assertion of µDMA or ADC requests
generated on a match event. Even if the TATODMAEN
bit is set in the GPTMDMAEV register or the
TATOADCEN bit is set in the GPTMADCEV register,
a µDMA or ADC match trigger is not sent to the µDMA
or ADC, respectively, when the TAMIE bit is clear.
An interrupt is generated when the match value in the
GPTMTAMATCHR register is reached in the one-shot and
periodic modes.
GPTM Timer A Count Direction
Value Description
0
The timer counts down.
1
The timer counts up. When counting up, the timer starts from a
value of 0x0.
When in PWM or RTC mode, the status of this bit is ignored. PWM mode
always counts down and RTC mode always counts up.
3
TAAMS
RW
0
GPTM Timer A Alternate Mode Select
The TAAMS values are defined as follows:
Value Description
0
Capture or compare mode is enabled.
1
PWM mode is enabled.
Note:
2
TACMR
RW
0
To enable PWM mode, you must also clear the TACMR
bit and configure the TAMR field to 0x1 or 0x2.
GPTM Timer A Capture Mode
The TACMR values are defined as follows:
Value Description
0
Edge-Count mode
1
Edge-Time mode
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Bit/Field
Name
Type
Reset
1:0
TAMR
RW
0x0
Description
GPTM Timer A Mode
The TAMR values are defined as follows:
Value Description
0x0
Reserved
0x1
One-Shot Timer mode
0x2
Periodic Timer mode
0x3
Capture mode
The Timer mode is based on the timer configuration defined by bits 2:0
in the GPTMCFG register.
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Register 3: GPTM Timer B Mode (GPTMTBMR), offset 0x008
This register configures the GPTM based on the configuration selected in the GPTMCFG register.
When in PWM mode, set the TBAMS bit, clear the TBCMR bit, and configure the TBMR field to 0x1 or
0x2.
This register controls the modes for Timer B when it is used individually. When Timer A and Timer
B are concatenated, this register is ignored and GPTMTAMR controls the modes for both Timer A
and Timer B.
Important: Bits in this register should only be changed when the TBEN bit in the GPTMCTL register
is cleared.
GPTM Timer B Mode (GPTMTBMR)
16/32-bit Timer 0 base: 0x4003.0000
16/32-bit Timer 1 base: 0x4003.1000
16/32-bit Timer 2 base: 0x4003.2000
16/32-bit Timer 3 base: 0x4003.3000
16/32-bit Timer 4 base: 0x4003.4000
16/32-bit Timer 5 base: 0x4003.5000
32/64-bit Wide Timer 0 base: 0x4003.6000
32/64-bit Wide Timer 1 base: 0x4003.7000
32/64-bit Wide Timer 2 base: 0x4004.C000
32/64-bit Wide Timer 3 base: 0x4004.D000
32/64-bit Wide Timer 4 base: 0x4004.E000
32/64-bit Wide Timer 5 base: 0x4004.F000
Offset 0x008
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
TBMIE
TBCDIR
TBAMS
TBCMR
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
reserved
Type
Reset
TBPLO
RO
0
RO
0
TBMRSU TBPWMIE
RW
0
RW
0
RW
0
Bit/Field
Name
Type
Reset
31:12
reserved
RO
0x0000.00
11
TBPLO
RW
0
TBILD
RW
0
TBSNAPS TBWOT
RW
0
RW
0
TBMR
RW
0
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPTM Timer B PWM Legacy Operation
Value Description
0
Legacy operation with CCP pin driven Low when the
GPTMTAILR is reloaded after the timer reaches 0.
1
CCP is driven High when the GPTMTAILR is reloaded after the
timer reaches 0.
This bit is only valid in PWM mode.
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Bit/Field
Name
Type
Reset
10
TBMRSU
RW
0
Description
GPTM Timer B Match Register Update
Value Description
0
Update the GPTMTBMATCHR register and the GPTMTBPR
register, if used, on the next cycle.
1
Update the GPTMTBMATCHR register and the GPTMTBPR
register, if used, on the next timeout.
If the timer is disabled (TBEN is clear) when this bit is set,
GPTMTBMATCHR and GPTMTBPR are updated when the timer is
enabled. If the timer is stalled (TBSTALL is set), GPTMTBMATCHR and
GPTMTBPR are updated according to the configuration of this bit.
9
TBPWMIE
RW
0
GPTM Timer B PWM Interrupt Enable
This bit enables interrupts in PWM mode on rising, falling, or both edges
of the CCP output as defined by the TBEVENT field in the GPTMCTL
register.
Value Description
0
Capture event interrupt is disabled.
1
Capture event is enabled.
This bit is only valid in PWM mode.
8
TBILD
RW
0
GPTM Timer B Interval Load Write
Value Description
0
Update the GPTMTBR and GPTMTBV registers with the value
in the GPTMTBILR register on the next cycle. Also update the
GPTMTBPS and GPTMTBPV registers with the value in the
GPTMTBPR register on the next cycle.
1
Update the GPTMTBR and GPTMTBV registers with the value
in the GPTMTBILR register on the next timeout. Also update
the GPTMTBPS and GPTMTBPV registers with the value in
the GPTMTBPR register on the next timeout.
Note the state of this bit has no effect when counting up.
The bit descriptions above apply if the timer is enabled and running. If
the timer is disabled (TBEN is clear) when this bit is set, GPTMTBR,
GPTMTBV and, GPTMTBPS, and GPTMTBPV are updated when the
timer is enabled. If the timer is stalled (TBSTALL is set), GPTMTBR and
GPTMTBPS are updated according to the configuration of this bit.
7
TBSNAPS
RW
0
GPTM Timer B Snap-Shot Mode
Value Description
0
Snap-shot mode is disabled.
1
If Timer B is configured in the periodic mode, the actual
free-running value of Timer B is loaded at the time-out event
into the GPTM Timer B (GPTMTBR) register. If the timer
prescaler is used, the prescaler snapshot is loaded into the
GPTM Timer B (GPTMTBPR).
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Bit/Field
Name
Type
Reset
6
TBWOT
RW
0
Description
GPTM Timer B Wait-on-Trigger
Value Description
5
TBMIE
RW
0
0
Timer B begins counting as soon as it is enabled.
1
If Timer B is enabled (TBEN is set in the GPTMCTL register),
Timer B does not begin counting until it receives a trigger from
the timer in the previous position in the daisy chain, see Figure
11-9 on page 708. This function is valid for one-shot, periodic,
and PWM modes.
GPTM Timer B Match Interrupt Enable
Value Description
0
The match interrupt is disabled for match events.
1
An interrupt is generated when the match value in the
GPTMTBMATCHR register is reached in the one-shot and
periodic modes.
Note:
4
TBCDIR
RW
0
Clearing the TBMIE bit in the GPTMTBMR register
prevents assertion of µDMA or ADC requests
generated on a match event. Even if the TBTODMAEN
bit is set in the GPTMDMAEV register or the
TBTOADCEN bit is set in the GPTMADCEV register,
a µDMA or ADC match trigger is not sent to the µDMA
or ADC, respectively, when the TBMIE bit is clear.
GPTM Timer B Count Direction
Value Description
0
The timer counts down.
1
The timer counts up. When counting up, the timer starts from a
value of 0x0.
When in PWM or RTC mode, the status of this bit is ignored. PWM mode
always counts down and RTC mode always counts up.
3
TBAMS
RW
0
GPTM Timer B Alternate Mode Select
The TBAMS values are defined as follows:
Value Description
0
Capture or compare mode is enabled.
1
PWM mode is enabled.
Note:
2
TBCMR
RW
0
To enable PWM mode, you must also clear the TBCMR
bit and configure the TBMR field to 0x1 or 0x2.
GPTM Timer B Capture Mode
The TBCMR values are defined as follows:
Value Description
0
Edge-Count mode
1
Edge-Time mode
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Bit/Field
Name
Type
Reset
1:0
TBMR
RW
0x0
Description
GPTM Timer B Mode
The TBMR values are defined as follows:
Value Description
0x0
Reserved
0x1
One-Shot Timer mode
0x2
Periodic Timer mode
0x3
Capture mode
The timer mode is based on the timer configuration defined by bits 2:0
in the GPTMCFG register.
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General-Purpose Timers
Register 4: GPTM Control (GPTMCTL), offset 0x00C
This register is used alongside the GPTMCFG and GMTMTnMR registers to fine-tune the timer
configuration, and to enable other features such as timer stall and the output trigger. The output
trigger can be used to initiate transfers on the ADC module.
Important: Bits in this register should only be changed when the TnEN bit for the respective timer
is cleared.
GPTM Control (GPTMCTL)
16/32-bit Timer 0 base: 0x4003.0000
16/32-bit Timer 1 base: 0x4003.1000
16/32-bit Timer 2 base: 0x4003.2000
16/32-bit Timer 3 base: 0x4003.3000
16/32-bit Timer 4 base: 0x4003.4000
16/32-bit Timer 5 base: 0x4003.5000
32/64-bit Wide Timer 0 base: 0x4003.6000
32/64-bit Wide Timer 1 base: 0x4003.7000
32/64-bit Wide Timer 2 base: 0x4004.C000
32/64-bit Wide Timer 3 base: 0x4004.D000
32/64-bit Wide Timer 4 base: 0x4004.E000
32/64-bit Wide Timer 5 base: 0x4004.F000
Offset 0x00C
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
3
2
reserved
Type
Reset
RO
0
RO
0
15
14
reserved TBPWML
Type
Reset
RO
0
RW
0
RO
0
RO
0
RO
0
RO
0
11
10
13
12
TBOTE
reserved
RW
0
RO
0
TBEVENT
RW
0
RW
0
RO
0
RO
0
9
8
TBSTALL
TBEN
RW
0
RW
0
Bit/Field
Name
Type
Reset
31:15
reserved
RO
0x0000
14
TBPWML
RW
0
reserved TAPWML
RO
0
5
4
TAOTE
RTCEN
RW
0
RW
0
RW
0
TAEVENT
RW
0
RW
0
1
0
TASTALL
TAEN
RW
0
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPTM Timer B PWM Output Level
The TBPWML values are defined as follows:
Value Description
0
Output is unaffected.
1
Output is inverted.
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Bit/Field
Name
Type
Reset
13
TBOTE
RW
0
Description
GPTM Timer B Output Trigger Enable
The TBOTE values are defined as follows:
Value Description
0
The output Timer B ADC trigger is disabled.
1
The output Timer B ADC trigger is enabled.
Note:
The timer must be configured for one-shot or periodic
time-out mode to produce an ADC trigger assertion.
The GPTM does not generate triggers for match,
compare events or compare match events.
In addition, the ADC must be enabled and the timer selected as a trigger
source with the EMn bit in the ADCEMUX register (see page 822).
12
reserved
RO
0
11:10
TBEVENT
RW
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPTM Timer B Event Mode
The TBEVENT values are defined as follows:
Value Description
0x0
Positive edge
0x1
Negative edge
0x2
Reserved
0x3
Both edges
Note:
9
TBSTALL
RW
0
If PWM output inversion is enabled, edge detection interrupt
behavior is reversed. Thus, if a positive-edge interrupt trigger
has been set and the PWM inversion generates a postive
edge, no event-trigger interrupt asserts. Instead, the interrupt
is generated on the negative edge of the PWM signal.
GPTM Timer B Stall Enable
The TBSTALL values are defined as follows:
Value Description
0
Timer B continues counting while the processor is halted by the
debugger.
1
Timer B freezes counting while the processor is halted by the
debugger.
If the processor is executing normally, the TBSTALL bit is ignored.
8
TBEN
RW
0
GPTM Timer B Enable
The TBEN values are defined as follows:
Value Description
0
Timer B is disabled.
1
Timer B is enabled and begins counting or the capture logic is
enabled based on the GPTMCFG register.
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Bit/Field
Name
Type
Reset
Description
7
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
6
TAPWML
RW
0
GPTM Timer A PWM Output Level
The TAPWML values are defined as follows:
Value Description
5
TAOTE
RW
0
0
Output is unaffected.
1
Output is inverted.
GPTM Timer A Output Trigger Enable
The TAOTE values are defined as follows:
Value Description
0
The output Timer A ADC trigger is disabled.
1
The output Timer A ADC trigger is enabled.
Note:
The timer must be configured for one-shot or periodic
time-out mode to produce an ADC trigger assertion.
The GPTM does not generate triggers for match,
compare events or compare match events.
In addition, the ADC must be enabled and the timer selected as a trigger
source with the EMn bit in the ADCEMUX register (see page 822).
4
RTCEN
RW
0
GPTM RTC Stall Enable
The RTCEN values are defined as follows:
Value Description
0
RTC counting freezes while the processor is halted by the
debugger.
1
RTC counting continues while the processor is halted by the
debugger.
If the RTCEN bit is set, it prevents the timer from stalling in all operating
modes, even if TnSTALL is set.
3:2
TAEVENT
RW
0x0
GPTM Timer A Event Mode
The TAEVENT values are defined as follows:
Value Description
0x0
Positive edge
0x1
Negative edge
0x2
Reserved
0x3
Both edges
Note:
If PWM output inversion is enabled, edge detection interrupt
behavior is reversed. Thus, if a positive-edge interrupt trigger
has been set and the PWM inversion generates a postive
edge, no event-trigger interrupt asserts. Instead, the interrupt
is generated on the negative edge of the PWM signal.
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Bit/Field
Name
Type
Reset
1
TASTALL
RW
0
Description
GPTM Timer A Stall Enable
The TASTALL values are defined as follows:
Value Description
0
Timer A continues counting while the processor is halted by the
debugger.
1
Timer A freezes counting while the processor is halted by the
debugger.
If the processor is executing normally, the TASTALL bit is ignored.
0
TAEN
RW
0
GPTM Timer A Enable
The TAEN values are defined as follows:
Value Description
0
Timer A is disabled.
1
Timer A is enabled and begins counting or the capture logic is
enabled based on the GPTMCFG register.
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Register 5: GPTM Synchronize (GPTMSYNC), offset 0x010
Note:
This register is only implemented on GPTM Module 0 only.
This register allows software to synchronize a number of timers.
GPTM Synchronize (GPTMSYNC)
16/32-bit Timer 0 base: 0x4003.0000
16/32-bit Timer 1 base: 0x4003.1000
16/32-bit Timer 2 base: 0x4003.2000
16/32-bit Timer 3 base: 0x4003.3000
16/32-bit Timer 4 base: 0x4003.4000
16/32-bit Timer 5 base: 0x4003.5000
32/64-bit Wide Timer 0 base: 0x4003.6000
32/64-bit Wide Timer 1 base: 0x4003.7000
32/64-bit Wide Timer 2 base: 0x4004.C000
32/64-bit Wide Timer 3 base: 0x4004.D000
32/64-bit Wide Timer 4 base: 0x4004.E000
32/64-bit Wide Timer 5 base: 0x4004.F000
Offset 0x010
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
reserved
Type
Reset
22
SYNCWT5
21
20
SYNCWT4
19
18
SYNCWT3
17
16
SYNCWT2
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SYNCWT1
Type
Reset
23
RW
0
RW
0
SYNCWT0
RW
0
RW
0
SYNCT5
RW
0
RW
0
SYNCT4
RW
0
SYNCT3
RW
0
RW
0
RW
0
SYNCT2
RW
0
RW
0
SYNCT1
RW
0
RW
0
SYNCT0
RW
0
RW
0
Bit/Field
Name
Type
Reset
Description
31:24
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
23:22
SYNCWT5
RW
0x0
Synchronize GPTM 32/64-Bit Timer 5
The SYNCWT5 values are defined as follows:
Value Description
0x0
GPTM 32/64-Bit Timer 5 is not affected.
0x1
A timeout event for Timer A of GPTM 32/64-Bit Timer 5 is
triggered.
0x2
A timeout event for Timer B of GPTM 32/64-Bit Timer 5 is
triggered.
0x3
A timeout event for both Timer A and Timer B of GPTM 32/64-Bit
Timer 5 is triggered.
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Tiva™ TM4C1237H6PZ Microcontroller
Bit/Field
Name
Type
Reset
21:20
SYNCWT4
RW
0x0
Description
Synchronize GPTM 32/64-Bit Timer 4
The SYNCWT4 values are defined as follows:
Value Description
19:18
SYNCWT3
RW
0x0
0x0
GPTM 32/64-Bit Timer 4 is not affected.
0x1
A timeout event for Timer A of GPTM 32/64-Bit Timer 4 is
triggered.
0x2
A timeout event for Timer B of GPTM 32/64-Bit Timer 4 is
triggered.
0x3
A timeout event for both Timer A and Timer B of GPTM 32/64-Bit
Timer 4 is triggered.
Synchronize GPTM 32/64-Bit Timer 3
The SYNCWT3 values are defined as follows:
Value Description
17:16
SYNCWT2
RW
0x0
0x0
GPTM 32/64-Bit Timer 3 is not affected.
0x1
A timeout event for Timer A of GPTM 32/64-Bit Timer 3 is
triggered.
0x2
A timeout event for Timer B of GPTM 32/64-Bit Timer 3 is
triggered.
0x3
A timeout event for both Timer A and Timer B of GPTM 32/64-Bit
Timer 3 is triggered.
Synchronize GPTM 32/64-Bit Timer 2
The SYNCWT2 values are defined as follows:
Value Description
15:14
SYNCWT1
RW
0x0
0x0
GPTM 32/64-Bit Timer 2 is not affected.
0x1
A timeout event for Timer A of GPTM 32/64-Bit Timer 2 is
triggered.
0x2
A timeout event for Timer B of GPTM 32/64-Bit Timer 2 is
triggered.
0x3
A timeout event for both Timer A and Timer B of GPTM 32/64-Bit
Timer 2 is triggered.
Synchronize GPTM 32/64-Bit Timer 1
The SYNCWT1 values are defined as follows:
Value Description
0x0
GPTM 32/64-Bit Timer 1 is not affected.
0x1
A timeout event for Timer A of GPTM 32/64-Bit Timer 1 is
triggered.
0x2
A timeout event for Timer B of GPTM 32/64-Bit Timer 1 is
triggered.
0x3
A timeout event for both Timer A and Timer B of GPTM 32/64-Bit
Timer 1 is triggered.
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General-Purpose Timers
Bit/Field
Name
Type
Reset
13:12
SYNCWT0
RW
0x0
Description
Synchronize GPTM 32/64-Bit Timer 0
The SYNCWT0 values are defined as follows:
Value Description
11:10
SYNCT5
RW
0x0
0x0
GPTM 32/64-Bit Timer 0 is not affected.
0x1
A timeout event for Timer A of GPTM 32/64-Bit Timer 0 is
triggered.
0x2
A timeout event for Timer B of GPTM 32/64-Bit Timer 0 is
triggered.
0x3
A timeout event for both Timer A and Timer B of GPTM 32/64-Bit
Timer 0 is triggered.
Synchronize GPTM 16/32-Bit Timer 5
The SYNCT5 values are defined as follows:
Value Description
9:8
SYNCT4
RW
0x0
0x0
GPTM 16/32-Bit Timer 5 is not affected.
0x1
A timeout event for Timer A of GPTM 16/32-Bit Timer 5 is
triggered.
0x2
A timeout event for Timer B of GPTM 16/32-Bit Timer 5 is
triggered.
0x3
A timeout event for both Timer A and Timer B of GPTM 16/32-Bit
Timer 5 is triggered.
Synchronize GPTM 16/32-Bit Timer 4
The SYNCT4 values are defined as follows:
Value Description
7:6
SYNCT3
RW
0x0
0x0
GPTM 16/32-Bit Timer 4 is not affected.
0x1
A timeout event for Timer A of GPTM 16/32-Bit Timer 4 is
triggered.
0x2
A timeout event for Timer B of GPTM 16/32-Bit Timer 4 is
triggered.
0x3
A timeout event for both Timer A and Timer B of GPTM 16/32-Bit
Timer 4 is triggered.
Synchronize GPTM 16/32-Bit Timer 3
The SYNCT3 values are defined as follows:
Value Description
0x0
GPTM 16/32-Bit Timer 3 is not affected.
0x1
A timeout event for Timer A of GPTM 16/32-Bit Timer 3 is
triggered.
0x2
A timeout event for Timer B of GPTM 16/32-Bit Timer 3 is
triggered.
0x3
A timeout event for both Timer A and Timer B of GPTM 16/32-Bit
Timer 3 is triggered.
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Tiva™ TM4C1237H6PZ Microcontroller
Bit/Field
Name
Type
Reset
5:4
SYNCT2
RW
0x0
Description
Synchronize GPTM 16/32-Bit Timer 2
The SYNCT2 values are defined as follows:
Value Description
3:2
SYNCT1
RW
0x0
0x0
GPTM 16/32-Bit Timer 2 is not affected.
0x1
A timeout event for Timer A of GPTM 16/32-Bit Timer 2 is
triggered.
0x2
A timeout event for Timer B of GPTM 16/32-Bit Timer 2 is
triggered.
0x3
A timeout event for both Timer A and Timer B of GPTM 16/32-Bit
Timer 2 is triggered.
Synchronize GPTM 16/32-Bit Timer 1
The SYNCT1 values are defined as follows:
Value Description
1:0
SYNCT0
RW
0x0
0x0
GPTM 16/32-Bit Timer 1 is not affected.
0x1
A timeout event for Timer A of GPTM 16/32-Bit Timer 1 is
triggered.
0x2
A timeout event for Timer B of GPTM 16/32-Bit Timer 1 is
triggered.
0x3
A timeout event for both Timer A and Timer B of GPTM 16/32-Bit
Timer 1 is triggered.
Synchronize GPTM 16/32-Bit Timer 0
The SYNCT0 values are defined as follows:
Value Description
0x0
GPTM 16/32-Bit Timer 0 is not affected.
0x1
A timeout event for Timer A of GPTM 16/32-Bit Timer 0 is
triggered.
0x2
A timeout event for Timer B of GPTM 16/32-Bit Timer 0 is
triggered.
0x3
A timeout event for both Timer A and Timer B of GPTM 16/32-Bit
Timer 0 is triggered.
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General-Purpose Timers
Register 6: GPTM Interrupt Mask (GPTMIMR), offset 0x018
This register allows software to enable/disable GPTM controller-level interrupts. Setting a bit enables
the corresponding interrupt, while clearing a bit disables it.
GPTM Interrupt Mask (GPTMIMR)
16/32-bit Timer 0 base: 0x4003.0000
16/32-bit Timer 1 base: 0x4003.1000
16/32-bit Timer 2 base: 0x4003.2000
16/32-bit Timer 3 base: 0x4003.3000
16/32-bit Timer 4 base: 0x4003.4000
16/32-bit Timer 5 base: 0x4003.5000
32/64-bit Wide Timer 0 base: 0x4003.6000
32/64-bit Wide Timer 1 base: 0x4003.7000
32/64-bit Wide Timer 2 base: 0x4004.C000
32/64-bit Wide Timer 3 base: 0x4004.D000
32/64-bit Wide Timer 4 base: 0x4004.E000
32/64-bit Wide Timer 5 base: 0x4004.F000
Offset 0x018
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
TBMIM
RO
0
RO
0
RW
0
24
23
22
21
20
19
18
17
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
9
8
7
6
5
4
3
2
1
0
CBEIM
CBMIM
TBTOIM
TAMIM
RTCIM
CAEIM
CAMIM
TATOIM
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:17
reserved
RO
0x0000
16
WUEIM
RW
0
16
WUEIM
reserved
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
32/64-Bit Wide GPTM Write Update Error Interrupt Mask
The WUEIM values are defined as follows:
Value Description
0
Interrupt is disabled.
1
Interrupt is enabled.
15:12
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
11
TBMIM
RW
0
GPTM Timer B Match Interrupt Mask
The TBMIM values are defined as follows:
Value Description
0
Interrupt is disabled.
1
Interrupt is enabled.
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Bit/Field
Name
Type
Reset
10
CBEIM
RW
0
Description
GPTM Timer B Capture Mode Event Interrupt Mask
The CBEIM values are defined as follows:
Value Description
9
CBMIM
RW
0
0
Interrupt is disabled.
1
Interrupt is enabled.
GPTM Timer B Capture Mode Match Interrupt Mask
The CBMIM values are defined as follows:
Value Description
8
TBTOIM
RW
0
0
Interrupt is disabled.
1
Interrupt is enabled.
GPTM Timer B Time-Out Interrupt Mask
The TBTOIM values are defined as follows:
Value Description
0
Interrupt is disabled.
1
Interrupt is enabled.
7:5
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
4
TAMIM
RW
0
GPTM Timer A Match Interrupt Mask
The TAMIM values are defined as follows:
Value Description
3
RTCIM
RW
0
0
Interrupt is disabled.
1
Interrupt is enabled.
GPTM RTC Interrupt Mask
The RTCIM values are defined as follows:
Value Description
2
CAEIM
RW
0
0
Interrupt is disabled.
1
Interrupt is enabled.
GPTM Timer A Capture Mode Event Interrupt Mask
The CAEIM values are defined as follows:
Value Description
0
Interrupt is disabled.
1
Interrupt is enabled.
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General-Purpose Timers
Bit/Field
Name
Type
Reset
1
CAMIM
RW
0
Description
GPTM Timer A Capture Mode Match Interrupt Mask
The CAMIM values are defined as follows:
Value Description
0
TATOIM
RW
0
0
Interrupt is disabled.
1
Interrupt is enabled.
GPTM Timer A Time-Out Interrupt Mask
The TATOIM values are defined as follows:
Value Description
0
Interrupt is disabled.
1
Interrupt is enabled.
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Tiva™ TM4C1237H6PZ Microcontroller
Register 7: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C
This register shows the state of the GPTM's internal interrupt signal. These bits are set whether or
not the interrupt is masked in the GPTMIMR register. Each bit can be cleared by writing a 1 to its
corresponding bit in GPTMICR.
Note:
The state of the GPTMRIS register is not affected by disabling and then re-enabling the
timer using the TnEN bits in the GPTM Control (GPTMCTL) register. If an application
requires that all or certain status bits should not carry over after re-enabling the timer, then
the appropriate bits in the GPTMRIS register should be cleared using the GPTMICR register
prior to re-enabling the timer. If this is not done, any status bits set in the GPTMRIS register
and unmasked in the GPTMIMR register generate an interrupt once the timer is re-enabled.
GPTM Raw Interrupt Status (GPTMRIS)
16/32-bit Timer 0 base: 0x4003.0000
16/32-bit Timer 1 base: 0x4003.1000
16/32-bit Timer 2 base: 0x4003.2000
16/32-bit Timer 3 base: 0x4003.3000
16/32-bit Timer 4 base: 0x4003.4000
16/32-bit Timer 5 base: 0x4003.5000
32/64-bit Wide Timer 0 base: 0x4003.6000
32/64-bit Wide Timer 1 base: 0x4003.7000
32/64-bit Wide Timer 2 base: 0x4004.C000
32/64-bit Wide Timer 3 base: 0x4004.D000
32/64-bit Wide Timer 4 base: 0x4004.E000
32/64-bit Wide Timer 5 base: 0x4004.F000
Offset 0x01C
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
15
14
13
12
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
11
10
TBMRIS
CBERIS
RO
0
RO
0
RO
0
RO
0
RO
0
9
8
7
CBMRIS TBTORIS
RO
0
Bit/Field
Name
Type
Reset
31:17
reserved
RO
0x0000
16
WUERIS
RW
0
RO
0
16
WUERIS
RO
0
RO
0
6
5
reserved
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
4
3
2
TAMRIS
RTCRIS
CAERIS
RO
0
RO
0
RO
0
RO
0
RW
0
1
0
CAMRIS TATORIS
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
32/64-Bit Wide GPTM Write Update Error Raw Interrupt Status
Value Description
15:12
reserved
RO
0
0
No error.
1
Either a Timer A register or a Timer B register was written twice
in a row or a Timer A register was written before the
corresponding Timer B register was written.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Bit/Field
Name
Type
Reset
11
TBMRIS
RO
0
Description
GPTM Timer B Match Raw Interrupt
Value Description
0
The match value has not been reached.
1
The TBMIE bit is set in the GPTMTBMR register, and the match
values in the GPTMTBMATCHR and (optionally) GPTMTBPMR
registers have been reached when configured in one-shot or
periodic mode.
This bit is cleared by writing a 1 to the TBMCINT bit in the GPTMICR
register.
10
CBERIS
RO
0
GPTM Timer B Capture Mode Event Raw Interrupt
Value Description
0
The capture mode event for Timer B has not occurred.
1
A capture mode event has occurred for Timer B. This interrupt
asserts when the subtimer is configured in Input Edge-Time
mode or when configured in PWM mode with the PWM interrupt
enabled by setting the TBPWMIE bit in the GPTMTBMR.
This bit is cleared by writing a 1 to the CBECINT bit in the GPTMICR
register.
9
CBMRIS
RO
0
GPTM Timer B Capture Mode Match Raw Interrupt
Value Description
0
The capture mode match for Timer B has not occurred.
1
The capture mode match has occurred for Timer B. This interrupt
asserts when the values in the GPTMTBR and GPTMTBPR
match the values in the GPTMTBMATCHR and GPTMTBPMR
when configured in Input Edge-Time mode.
This bit is cleared by writing a 1 to the CBMCINT bit in the GPTMICR
register.
8
TBTORIS
RO
0
GPTM Timer B Time-Out Raw Interrupt
Value Description
0
Timer B has not timed out.
1
Timer B has timed out. This interrupt is asserted when a
one-shot or periodic mode timer reaches it's count limit (0 or
the value loaded into GPTMTBILR, depending on the count
direction).
This bit is cleared by writing a 1 to the TBTOCINT bit in the GPTMICR
register.
7:5
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Tiva™ TM4C1237H6PZ Microcontroller
Bit/Field
Name
Type
Reset
4
TAMRIS
RO
0
Description
GPTM Timer A Match Raw Interrupt
Value Description
0
The match value has not been reached.
1
The TAMIE bit is set in the GPTMTAMR register, and the match
value in the GPTMTAMATCHR and (optionally) GPTMTAPMR
registers have been reached when configured in one-shot or
periodic mode.
This bit is cleared by writing a 1 to the TAMCINT bit in the GPTMICR
register.
3
RTCRIS
RO
0
GPTM RTC Raw Interrupt
Value Description
0
The RTC event has not occurred.
1
The RTC event has occurred.
This bit is cleared by writing a 1 to the RTCCINT bit in the GPTMICR
register.
2
CAERIS
RO
0
GPTM Timer A Capture Mode Event Raw Interrupt
Value Description
0
The capture mode event for Timer A has not occurred.
1
A capture mode event has occurred for Timer A. This interrupt
asserts when the subtimer is configured in Input Edge-Time
mode or when configured in PWM mode with the PWM interrupt
enabled by setting the TAPWMIE bit in the GPTMTAMR.
This bit is cleared by writing a 1 to the CAECINT bit in the GPTMICR
register.
1
CAMRIS
RO
0
GPTM Timer A Capture Mode Match Raw Interrupt
Value Description
0
The capture mode match for Timer A has not occurred.
1
A capture mode match has occurred for Timer A. This interrupt
asserts when the values in the GPTMTAR and GPTMTAPR
match the values in the GPTMTAMATCHR and GPTMTAPMR
when configured in Input Edge-Time mode.
This bit is cleared by writing a 1 to the CAMCINT bit in the GPTMICR
register.
0
TATORIS
RO
0
GPTM Timer A Time-Out Raw Interrupt
Value Description
0
Timer A has not timed out.
1
Timer A has timed out. This interrupt is asserted when a
one-shot or periodic mode timer reaches it's count limit (0 or
the value loaded into GPTMTAILR, depending on the count
direction).
This bit is cleared by writing a 1 to the TATOCINT bit in the GPTMICR
register.
June 12, 2014
739
Texas Instruments-Production Data
General-Purpose Timers
Register 8: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020
This register show the state of the GPTM's controller-level interrupt. If an interrupt is unmasked in
GPTMIMR, and there is an event that causes the interrupt to be asserted, the corresponding bit is
set in this register. All bits are cleared by writing a 1 to the corresponding bit in GPTMICR.
GPTM Masked Interrupt Status (GPTMMIS)
16/32-bit Timer 0 base: 0x4003.0000
16/32-bit Timer 1 base: 0x4003.1000
16/32-bit Timer 2 base: 0x4003.2000
16/32-bit Timer 3 base: 0x4003.3000
16/32-bit Timer 4 base: 0x4003.4000
16/32-bit Timer 5 base: 0x4003.5000
32/64-bit Wide Timer 0 base: 0x4003.6000
32/64-bit Wide Timer 1 base: 0x4003.7000
32/64-bit Wide Timer 2 base: 0x4004.C000
32/64-bit Wide Timer 3 base: 0x4004.D000
32/64-bit Wide Timer 4 base: 0x4004.E000
32/64-bit Wide Timer 5 base: 0x4004.F000
Offset 0x020
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
24
23
22
21
20
19
18
17
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
TAMMIS
RTCMIS
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
TBMMIS
RO
0
RO
0
WUEMIS
CBEMIS CBMMIS TBTOMIS
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:17
reserved
RO
0x0000
16
WUEMIS
RO
0
RO
0
16
reserved
RO
0
RO
0
RO
0
CAEMIS CAMMIS TATOMIS
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
32/64-Bit Wide GPTM Write Update Error Masked Interrupt Status
Value Description
0
An unmasked Write Update Error has not occurred.
1
An unmasked Write Update Error has occurred.
15:12
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
11
TBMMIS
RO
0
GPTM Timer B Match Masked Interrupt
Value Description
0
A Timer B Mode Match interrupt has not occurred or is masked.
1
An unmasked Timer B Mode Match interrupt
has occurred.
This bit is cleared by writing a 1 to the TBMCINT bit in the GPTMICR
register.
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Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Bit/Field
Name
Type
Reset
10
CBEMIS
RO
0
Description
GPTM Timer B Capture Mode Event Masked Interrupt
Value Description
0
A Capture B event interrupt has not occurred or is masked.
1
An unmasked Capture B event interrupt
has occurred.
This bit is cleared by writing a 1 to the CBECINT bit in the GPTMICR
register.
9
CBMMIS
RO
0
GPTM Timer B Capture Mode Match Masked Interrupt
Value Description
0
A Capture B Mode Match interrupt has not occurred or is
masked.
1
An unmasked Capture B Match interrupt
has occurred.
This bit is cleared by writing a 1 to the CBMCINT bit in the GPTMICR
register.
8
TBTOMIS
RO
0
GPTM Timer B Time-Out Masked Interrupt
Value Description
0
A Timer B Time-Out interrupt has not occurred or is masked.
1
An unmasked Timer B Time-Out interrupt
has occurred.
This bit is cleared by writing a 1 to the TBTOCINT bit in the GPTMICR
register.
7:5
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
4
TAMMIS
RO
0
GPTM Timer A Match Masked Interrupt
Value Description
0
A Timer A Mode Match interrupt has not occurred or is masked.
1
An unmasked Timer A Mode Match interrupt
has occurred.
This bit is cleared by writing a 1 to the TAMCINT bit in the GPTMICR
register.
3
RTCMIS
RO
0
GPTM RTC Masked Interrupt
Value Description
0
An RTC event interrupt has not occurred or is masked.
1
An unmasked RTC event interrupt
has occurred.
This bit is cleared by writing a 1 to the RTCCINT bit in the GPTMICR
register.
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General-Purpose Timers
Bit/Field
Name
Type
Reset
2
CAEMIS
RO
0
Description
GPTM Timer A Capture Mode Event Masked Interrupt
Value Description
0
A Capture A event interrupt has not occurred or is masked.
1
An unmasked Capture A event interrupt
has occurred.
This bit is cleared by writing a 1 to the CAECINT bit in the GPTMICR
register.
1
CAMMIS
RO
0
GPTM Timer A Capture Mode Match Masked Interrupt
Value Description
0
A Capture A Mode Match interrupt has not occurred or is
masked.
1
An unmasked Capture A Match interrupt
has occurred.
This bit is cleared by writing a 1 to the CAMCINT bit in the GPTMICR
register.
0
TATOMIS
RO
0
GPTM Timer A Time-Out Masked Interrupt
Value Description
0
A Timer A Time-Out interrupt has not occurred or is masked.
1
An unmasked Timer A Time-Out interrupt
has occurred.
This bit is cleared by writing a 1 to the TATOCINT bit in the GPTMICR
register.
742
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Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Register 9: GPTM Interrupt Clear (GPTMICR), offset 0x024
This register is used to clear the status bits in the GPTMRIS and GPTMMIS registers. Writing a 1
to a bit clears the corresponding bit in the GPTMRIS and GPTMMIS registers.
GPTM Interrupt Clear (GPTMICR)
16/32-bit Timer 0 base: 0x4003.0000
16/32-bit Timer 1 base: 0x4003.1000
16/32-bit Timer 2 base: 0x4003.2000
16/32-bit Timer 3 base: 0x4003.3000
16/32-bit Timer 4 base: 0x4003.4000
16/32-bit Timer 5 base: 0x4003.5000
32/64-bit Wide Timer 0 base: 0x4003.6000
32/64-bit Wide Timer 1 base: 0x4003.7000
32/64-bit Wide Timer 2 base: 0x4004.C000
32/64-bit Wide Timer 3 base: 0x4004.D000
32/64-bit Wide Timer 4 base: 0x4004.E000
32/64-bit Wide Timer 5 base: 0x4004.F000
Offset 0x024
Type W1C, reset 0x0000.0000
31
30
29
28
27
26
25
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
24
23
22
21
20
19
18
17
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
8
7
6
5
4
3
2
1
0
reserved
Type
Reset
reserved
Type
Reset
WUECINT
TBMCINT CBECINT CBMCINT TBTOCINT
RO
0
RO
0
W1C
0
W1C
0
W1C
0
Bit/Field
Name
Type
Reset
31:17
reserved
RO
0x0000
16
WUECINT
RW
0
W1C
0
16
reserved
RO
0
RO
0
TAMCINT RTCCINT CAECINT CAMCINT TATOCINT
RO
0
W1C
0
W1C
0
W1C
0
W1C
0
W1C
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
32/64-Bit Wide GPTM Write Update Error Interrupt Clear
Writing a 1 to this bit clears the WUERIS bit in the GPTMRIS register
and the WUEMIS bit in the GPTMMIS register.
15:12
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
11
TBMCINT
W1C
0
GPTM Timer B Match Interrupt Clear
Writing a 1 to this bit clears the TBMRIS bit in the GPTMRIS register
and the TBMMIS bit in the GPTMMIS register.
10
CBECINT
W1C
0
GPTM Timer B Capture Mode Event Interrupt Clear
Writing a 1 to this bit clears the CBERIS bit in the GPTMRIS register
and the CBEMIS bit in the GPTMMIS register.
9
CBMCINT
W1C
0
GPTM Timer B Capture Mode Match Interrupt Clear
Writing a 1 to this bit clears the CBMRIS bit in the GPTMRIS register
and the CBMMIS bit in the GPTMMIS register.
8
TBTOCINT
W1C
0
GPTM Timer B Time-Out Interrupt Clear
Writing a 1 to this bit clears the TBTORIS bit in the GPTMRIS register
and the TBTOMIS bit in the GPTMMIS register.
June 12, 2014
743
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General-Purpose Timers
Bit/Field
Name
Type
Reset
Description
7:5
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
4
TAMCINT
W1C
0
GPTM Timer A Match Interrupt Clear
Writing a 1 to this bit clears the TAMRIS bit in the GPTMRIS register
and the TAMMIS bit in the GPTMMIS register.
3
RTCCINT
W1C
0
GPTM RTC Interrupt Clear
Writing a 1 to this bit clears the RTCRIS bit in the GPTMRIS register
and the RTCMIS bit in the GPTMMIS register.
2
CAECINT
W1C
0
GPTM Timer A Capture Mode Event Interrupt Clear
Writing a 1 to this bit clears the CAERIS bit in the GPTMRIS register
and the CAEMIS bit in the GPTMMIS register.
1
CAMCINT
W1C
0
GPTM Timer A Capture Mode Match Interrupt Clear
Writing a 1 to this bit clears the CAMRIS bit in the GPTMRIS register
and the CAMMIS bit in the GPTMMIS register.
0
TATOCINT
W1C
0
GPTM Timer A Time-Out Raw Interrupt
Writing a 1 to this bit clears the TATORIS bit in the GPTMRIS register
and the TATOMIS bit in the GPTMMIS register.
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Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Register 10: GPTM Timer A Interval Load (GPTMTAILR), offset 0x028
When the timer is counting down, this register is used to load the starting count value into the timer.
When the timer is counting up, this register sets the upper bound for the timeout event.
When a 16/32-bit GPTM is configured to one of the 32-bit modes, GPTMTAILR appears as a 32-bit
register (the upper 16-bits correspond to the contents of the GPTM Timer B Interval Load
(GPTMTBILR) register). In a 16-bit mode, the upper 16 bits of this register read as 0s and have no
effect on the state of GPTMTBILR.
When a 32/64-bit Wide GPTM is configured to one of the 64-bit modes, GPTMTAILR contains bits
31:0 of the 64-bit count and the GPTM Timer B Interval Load (GPTMTBILR) register contains bits
63:32.
GPTM Timer A Interval Load (GPTMTAILR)
16/32-bit Timer 0 base: 0x4003.0000
16/32-bit Timer 1 base: 0x4003.1000
16/32-bit Timer 2 base: 0x4003.2000
16/32-bit Timer 3 base: 0x4003.3000
16/32-bit Timer 4 base: 0x4003.4000
16/32-bit Timer 5 base: 0x4003.5000
32/64-bit Wide Timer 0 base: 0x4003.6000
32/64-bit Wide Timer 1 base: 0x4003.7000
32/64-bit Wide Timer 2 base: 0x4004.C000
32/64-bit Wide Timer 3 base: 0x4004.D000
32/64-bit Wide Timer 4 base: 0x4004.E000
32/64-bit Wide Timer 5 base: 0x4004.F000
Offset 0x028
Type RW, reset 0xFFFF.FFFF
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
TAILR
Type
Reset
TAILR
Type
Reset
Bit/Field
Name
Type
31:0
TAILR
RW
Reset
Description
0xFFFF.FFFF GPTM Timer A Interval Load Register
Writing this field loads the counter for Timer A. A read returns the current
value of GPTMTAILR.
June 12, 2014
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Texas Instruments-Production Data
General-Purpose Timers
Register 11: GPTM Timer B Interval Load (GPTMTBILR), offset 0x02C
When the timer is counting down, this register is used to load the starting count value into the timer.
When the timer is counting up, this register sets the upper bound for the timeout event.
When a 16/32-bit GPTM is configured to one of the 32-bit modes, the contents of bits 15:0 in this
register are loaded into the upper 16 bits of the GPTMTAILR register. Reads from this register return
the current value of Timer B and writes are ignored. In a 16-bit mode, bits 15:0 are used for the load
value. Bits 31:16 are reserved in both cases.
When a 32/64-bit Wide GPTM is configured to one of the 64-bit modes, GPTMTAILR contains bits
31:0 of the 64-bit count and the GPTMTBILR register contains bits 63:32.
GPTM Timer B Interval Load (GPTMTBILR)
16/32-bit Timer 0 base: 0x4003.0000
16/32-bit Timer 1 base: 0x4003.1000
16/32-bit Timer 2 base: 0x4003.2000
16/32-bit Timer 3 base: 0x4003.3000
16/32-bit Timer 4 base: 0x4003.4000
16/32-bit Timer 5 base: 0x4003.5000
32/64-bit Wide Timer 0 base: 0x4003.6000
32/64-bit Wide Timer 1 base: 0x4003.7000
32/64-bit Wide Timer 2 base: 0x4004.C000
32/64-bit Wide Timer 3 base: 0x4004.D000
32/64-bit Wide Timer 4 base: 0x4004.E000
32/64-bit Wide Timer 5 base: 0x4004.F000
Offset 0x02C
Type RW, reset 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
0
RW
0
RW
1
RW
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RW
0
RW
0
RW
1
RW
0
RW
0
RW
1
RW
1
RW
0
RW
0
RW
1
RW
0
RW
0
RW
1
RW
0
RW
1
RW
1
TBILR
Type
Reset
TBILR
Type
Reset
Bit/Field
Name
Type
31:0
TBILR
RW
Reset
Description
0x0000.FFFF GPTM Timer B Interval Load Register
(for 16/32-bit) Writing this field loads the counter for Timer B. A read returns the current
0xFFFF.FFFF value of GPTMTBILR.
(for 32/64-bit)
When a 16/32-bit GPTM is in 32-bit mode, writes are ignored, and reads
return the current value of GPTMTBILR.
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Tiva™ TM4C1237H6PZ Microcontroller
Register 12: GPTM Timer A Match (GPTMTAMATCHR), offset 0x030
This register is loaded with a match value. Interrupts can be generated when the timer value is equal
to the value in this register in one-shot or periodic mode.
In Edge-Count mode, this register along with GPTMTAILR, determines how many edge events are
counted. The total number of edge events counted is equal to the value in GPTMTAILR minus this
value. Note that in edge-count mode, when executing an up-count, the value of GPTMTnPR and
GPTMTnILR must be greater than the value of GPTMTnPMR and GPTMTnMATCHR.
In PWM mode, this value along with GPTMTAILR, determines the duty cycle of the output PWM
signal.
When a 16/32-bit GPTM is configured to one of the 32-bit modes, GPTMTAMATCHR appears as
a 32-bit register (the upper 16-bits correspond to the contents of the GPTM Timer B Match
(GPTMTBMATCHR) register). In a 16-bit mode, the upper 16 bits of this register read as 0s and
have no effect on the state of GPTMTBMATCHR.
When a 32/64-bit Wide GPTM is configured to one of the 64-bit modes, GPTMTAMATCHR contains
bits 31:0 of the 64-bit match value and the GPTM Timer B Match (GPTMTBMATCHR) register
contains bits 63:32.
GPTM Timer A Match (GPTMTAMATCHR)
16/32-bit Timer 0 base: 0x4003.0000
16/32-bit Timer 1 base: 0x4003.1000
16/32-bit Timer 2 base: 0x4003.2000
16/32-bit Timer 3 base: 0x4003.3000
16/32-bit Timer 4 base: 0x4003.4000
16/32-bit Timer 5 base: 0x4003.5000
32/64-bit Wide Timer 0 base: 0x4003.6000
32/64-bit Wide Timer 1 base: 0x4003.7000
32/64-bit Wide Timer 2 base: 0x4004.C000
32/64-bit Wide Timer 3 base: 0x4004.D000
32/64-bit Wide Timer 4 base: 0x4004.E000
32/64-bit Wide Timer 5 base: 0x4004.F000
Offset 0x030
Type RW, reset 0xFFFF.FFFF
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
TAMR
Type
Reset
TAMR
Type
Reset
Bit/Field
Name
Type
31:0
TAMR
RW
Reset
Description
0xFFFF.FFFF GPTM Timer A Match Register
This value is compared to the GPTMTAR register to determine match
events.
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747
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General-Purpose Timers
Register 13: GPTM Timer B Match (GPTMTBMATCHR), offset 0x034
This register is loaded with a match value. Interrupts can be generated when the timer value is equal
to the value in this register in one-shot or periodic mode.
In Edge-Count mode, this register along with GPTMTBILR determines how many edge events are
counted. The total number of edge events counted is equal to the value in GPTMTBILR minus this
value. Note that in edge-count mode, when executing an up-count, the value of GPTMTnPR and
GPTMTnILR must be greater than the value of GPTMTnPMR and GPTMTnMATCHR.
In PWM mode, this value along with GPTMTBILR, determines the duty cycle of the output PWM
signal.
When a 16/32-bit GPTM is configured to one of the 32-bit modes, the contents of bits 15:0 in this
register are loaded into the upper 16 bits of the GPTMTAMATCHR register. Reads from this register
return the current match value of Timer B and writes are ignored. In a 16-bit mode, bits 15:0 are
used for the match value. Bits 31:16 are reserved in both cases.
When a 32/64-bit Wide GPTM is configured to one of the 64-bit modes, GPTMTAMATCHR contains
bits 31:0 of the 64-bit match value and the GPTMTBMATCHR register contains bits 63:32.
GPTM Timer B Match (GPTMTBMATCHR)
16/32-bit Timer 0 base: 0x4003.0000
16/32-bit Timer 1 base: 0x4003.1000
16/32-bit Timer 2 base: 0x4003.2000
16/32-bit Timer 3 base: 0x4003.3000
16/32-bit Timer 4 base: 0x4003.4000
16/32-bit Timer 5 base: 0x4003.5000
32/64-bit Wide Timer 0 base: 0x4003.6000
32/64-bit Wide Timer 1 base: 0x4003.7000
32/64-bit Wide Timer 2 base: 0x4004.C000
32/64-bit Wide Timer 3 base: 0x4004.D000
32/64-bit Wide Timer 4 base: 0x4004.E000
32/64-bit Wide Timer 5 base: 0x4004.F000
Offset 0x034
Type RW, reset 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
0
RW
0
RW
1
RW
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RW
0
RW
0
RW
1
RW
0
RW
0
RW
1
RW
1
RW
0
RW
0
RW
1
RW
0
RW
0
RW
1
RW
0
RW
1
RW
1
TBMR
Type
Reset
TBMR
Type
Reset
Bit/Field
Name
Type
31:0
TBMR
RW
Reset
Description
0x0000.FFFF GPTM Timer B Match Register
(for 16/32-bit) This value is compared to the GPTMTBR register to determine match
0xFFFF.FFFF events.
(for 32/64-bit)
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Register 14: GPTM Timer A Prescale (GPTMTAPR), offset 0x038
This register allows software to extend the range of the timers when they are used individually.
When in one-shot or periodic down count modes, this register acts as a true prescaler for the timer
counter. When acting as a true prescaler, the prescaler counts down to 0 before the value in the
GPTMTAR and GPTMTAV registers are incremented. In all other individual/split modes, this register
is a linear extension of the upper range of the timer counter, holding bits 23:16 in the 16-bit modes
of the 16/32-bit GPTM and bits 47:32 in the 32-bit modes of the 32/64-bit Wide GPTM.
GPTM Timer A Prescale (GPTMTAPR)
16/32-bit Timer 0 base: 0x4003.0000
16/32-bit Timer 1 base: 0x4003.1000
16/32-bit Timer 2 base: 0x4003.2000
16/32-bit Timer 3 base: 0x4003.3000
16/32-bit Timer 4 base: 0x4003.4000
16/32-bit Timer 5 base: 0x4003.5000
32/64-bit Wide Timer 0 base: 0x4003.6000
32/64-bit Wide Timer 1 base: 0x4003.7000
32/64-bit Wide Timer 2 base: 0x4004.C000
32/64-bit Wide Timer 3 base: 0x4004.D000
32/64-bit Wide Timer 4 base: 0x4004.E000
32/64-bit Wide Timer 5 base: 0x4004.F000
Offset 0x038
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
TAPSRH
Type
Reset
TAPSR
RW
0
Bit/Field
Name
Type
Reset
31:16
reserved
RO
0
15:8
TAPSRH
RW
0x00
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPTM Timer A Prescale High Byte
The register loads this value on a write. A read returns the current value
of the register.
For the 16/32-bit GPTM, this field is reserved. For the 32/64-bit Wide
GPTM, this field contains the upper 8-bits of the 16-bit prescaler.
Refer to Table 11-5 on page 700 for more details and an example.
7:0
TAPSR
RW
0x00
GPTM Timer A Prescale
The register loads this value on a write. A read returns the current value
of the register.
For the 16/32-bit GPTM, this field contains the entire 8-bit prescaler.
For the 32/64-bit Wide GPTM, this field contains the lower 8-bits of the
16-bit prescaler.
Refer to Table 11-5 on page 700 for more details and an example.
June 12, 2014
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General-Purpose Timers
Register 15: GPTM Timer B Prescale (GPTMTBPR), offset 0x03C
This register allows software to extend the range of the timers when they are used individually.
When in one-shot or periodic down count modes, this register acts as a true prescaler for the timer
counter. When acting as a true prescaler, the prescaler counts down to 0 before the value in the
GPTMTBR and GPTMTBV registers are incremented. In all other individual/split modes, this register
is a linear extension of the upper range of the timer counter, holding bits 23:16 in the 16-bit modes
of the 16/32-bit GPTM and bits 47:32 in the 32-bit modes of the 32/64-bit Wide GPTM.
GPTM Timer B Prescale (GPTMTBPR)
16/32-bit Timer 0 base: 0x4003.0000
16/32-bit Timer 1 base: 0x4003.1000
16/32-bit Timer 2 base: 0x4003.2000
16/32-bit Timer 3 base: 0x4003.3000
16/32-bit Timer 4 base: 0x4003.4000
16/32-bit Timer 5 base: 0x4003.5000
32/64-bit Wide Timer 0 base: 0x4003.6000
32/64-bit Wide Timer 1 base: 0x4003.7000
32/64-bit Wide Timer 2 base: 0x4004.C000
32/64-bit Wide Timer 3 base: 0x4004.D000
32/64-bit Wide Timer 4 base: 0x4004.E000
32/64-bit Wide Timer 5 base: 0x4004.F000
Offset 0x03C
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
TBPSRH
Type
Reset
TBPSR
RW
0
Bit/Field
Name
Type
Reset
31:16
reserved
RO
0
15:8
TBPSRH
RW
0x00
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPTM Timer B Prescale High Byte
The register loads this value on a write. A read returns the current value
of the register.
For the 16/32-bit GPTM, this field is reserved. For the 32/64-bit Wide
GPTM, this field contains the upper 8-bits of the 16-bit prescaler.
Refer to Table 11-5 on page 700 for more details and an example.
7:0
TBPSR
RW
0x00
GPTM Timer B Prescale
The register loads this value on a write. A read returns the current value
of this register.
For the 16/32-bit GPTM, this field contains the entire 8-bit prescaler.
For the 32/64-bit Wide GPTM, this field contains the lower 8-bits of the
16-bit prescaler.
Refer to Table 11-5 on page 700 for more details and an example.
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Tiva™ TM4C1237H6PZ Microcontroller
Register 16: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040
This register allows software to extend the range of the GPTMTAMATCHR when the timers are
used individually. This register holds bits 23:16 in the 16-bit modes of the 16/32-bit GPTM and bits
47:32 in the 32-bit modes of the 32/64-bit Wide GPTM.
GPTM TimerA Prescale Match (GPTMTAPMR)
16/32-bit Timer 0 base: 0x4003.0000
16/32-bit Timer 1 base: 0x4003.1000
16/32-bit Timer 2 base: 0x4003.2000
16/32-bit Timer 3 base: 0x4003.3000
16/32-bit Timer 4 base: 0x4003.4000
16/32-bit Timer 5 base: 0x4003.5000
32/64-bit Wide Timer 0 base: 0x4003.6000
32/64-bit Wide Timer 1 base: 0x4003.7000
32/64-bit Wide Timer 2 base: 0x4004.C000
32/64-bit Wide Timer 3 base: 0x4004.D000
32/64-bit Wide Timer 4 base: 0x4004.E000
32/64-bit Wide Timer 5 base: 0x4004.F000
Offset 0x040
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
TAPSMRH
Type
Reset
TAPSMR
RW
0
Bit/Field
Name
Type
Reset
31:16
reserved
RO
0x0000
15:8
TAPSMRH
RW
0x00
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPTM Timer A Prescale Match High Byte
This value is used alongside GPTMTAMATCHR to detect timer match
events while using a prescaler.
For the 16/32-bit GPTM, this field is reserved. For the 32/64-bit Wide
GPTM, this field contains the upper 8-bits of the 16-bit prescale match
value.
7:0
TAPSMR
RW
0x00
GPTM TimerA Prescale Match
This value is used alongside GPTMTAMATCHR to detect timer match
events while using a prescaler.
For the 16/32-bit GPTM, this field contains the entire 8-bit prescaler
match value. For the 32/64-bit Wide GPTM, this field contains the lower
8-bits of the 16-bit prescaler match value.
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Register 17: GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044
This register allows software to extend the range of the GPTMTBMATCHR when the timers are
used individually. This register holds bits 23:16 in the 16-bit modes of the 16/32-bit GPTM and bits
47:32 in the 32-bit modes of the 32/64-bit Wide GPTM.
GPTM TimerB Prescale Match (GPTMTBPMR)
16/32-bit Timer 0 base: 0x4003.0000
16/32-bit Timer 1 base: 0x4003.1000
16/32-bit Timer 2 base: 0x4003.2000
16/32-bit Timer 3 base: 0x4003.3000
16/32-bit Timer 4 base: 0x4003.4000
16/32-bit Timer 5 base: 0x4003.5000
32/64-bit Wide Timer 0 base: 0x4003.6000
32/64-bit Wide Timer 1 base: 0x4003.7000
32/64-bit Wide Timer 2 base: 0x4004.C000
32/64-bit Wide Timer 3 base: 0x4004.D000
32/64-bit Wide Timer 4 base: 0x4004.E000
32/64-bit Wide Timer 5 base: 0x4004.F000
Offset 0x044
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
TBPSMRH
Type
Reset
TBPSMR
RW
0
Bit/Field
Name
Type
Reset
31:16
reserved
RO
0x0000
15:8
TBPSMRH
RW
0x00
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPTM Timer B Prescale Match High Byte
This value is used alongside GPTMTBMATCHR to detect timer match
events while using a prescaler.
For the 16/32-bit GPTM, this field is reserved. For the 32/64-bit Wide
GPTM, this field contains the upper 8-bits of the 16-bit prescale match
value.
7:0
TBPSMR
RW
0x00
GPTM TimerB Prescale Match
This value is used alongside GPTMTBMATCHR to detect timer match
events while using a prescaler.
For the 16/32-bit GPTM, this field contains the entire 8-bit prescaler
match value. For the 32/64-bit Wide GPTM, this field contains the lower
8-bits of the 16-bit prescaler match value.
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Register 18: GPTM Timer A (GPTMTAR), offset 0x048
This register shows the current value of the Timer A counter in all cases except for Input Edge Count
and Time modes. In the Input Edge Count mode, this register contains the number of edges that
have occurred. In the Input Edge Time mode, this register contains the time at which the last edge
event took place.
When a 16/32-bit GPTM is configured to one of the 32-bit modes, GPTMTAR appears as a 32-bit
register (the upper 16-bits correspond to the contents of the GPTM Timer B (GPTMTBR) register).
In the16-bit Input Edge Count, Input Edge Time, and PWM modes, bits 15:0 contain the value of
the counter and bits 23:16 contain the value of the prescaler, which is the upper 8 bits of the count.
Bits 31:24 always read as 0. To read the value of the prescaler in 16-bit One-Shot and Periodic
modes, read bits [23:16] in the GPTMTAV register. To read the value of the prescalar in periodic
snapshot mode, read the Timer A Prescale Snapshot (GPTMTAPS) register.
When a 32/64-bit Wide GPTM is configured to one of the 64-bit modes, GPTMTAR contains bits
31:0 of the 64-bit timer value and the GPTM Timer B (GPTMTBR) register contains bits 63:32. In
a 32-bit mode, the value of the prescaler is stored in the GPTM Timer A Prescale Snapshot
(GPTMTAPS) register.
GPTM Timer A (GPTMTAR)
16/32-bit Timer 0 base: 0x4003.0000
16/32-bit Timer 1 base: 0x4003.1000
16/32-bit Timer 2 base: 0x4003.2000
16/32-bit Timer 3 base: 0x4003.3000
16/32-bit Timer 4 base: 0x4003.4000
16/32-bit Timer 5 base: 0x4003.5000
32/64-bit Wide Timer 0 base: 0x4003.6000
32/64-bit Wide Timer 1 base: 0x4003.7000
32/64-bit Wide Timer 2 base: 0x4004.C000
32/64-bit Wide Timer 3 base: 0x4004.D000
32/64-bit Wide Timer 4 base: 0x4004.E000
32/64-bit Wide Timer 5 base: 0x4004.F000
Offset 0x048
Type RO, reset 0xFFFF.FFFF
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
TAR
Type
Reset
TAR
Type
Reset
Bit/Field
Name
Type
31:0
TAR
RO
Reset
Description
0xFFFF.FFFF GPTM Timer A Register
A read returns the current value of the GPTM Timer A Count Register,
in all cases except for Input Edge Count and Time modes. In the Input
Edge Count mode, this register contains the number of edges that have
occurred. In the Input Edge Time mode, this register contains the time
at which the last edge event took place.
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General-Purpose Timers
Register 19: GPTM Timer B (GPTMTBR), offset 0x04C
This register shows the current value of the Timer B counter in all cases except for Input Edge Count
and Time modes. In the Input Edge Count mode, this register contains the number of edges that
have occurred. In the Input Edge Time mode, this register contains the time at which the last edge
event took place.
When a 16/32-bit GPTM is configured to one of the 32-bit modes, the contents of bits 15:0 in this
register are loaded into the upper 16 bits of the GPTMTAR register. Reads from this register return
the current value of Timer B. In a 16-bit mode, bits 15:0 contain the value of the counter and bits
23:16 contain the value of the prescaler in Input Edge Count, Input Edge Time, and PWM modes,
which is the upper 8 bits of the count. Bits 31:24 always read as 0. To read the value of the prescaler
in 16-bit One-Shot and Periodic modes, read bits [23:16] in the GPTMTBV register. To read the
value of the prescalar in periodic snapshot mode, read the Timer B Prescale Snapshot
(GPTMTBPS) register.
When a 32/64-bit Wide GPTM is configured to one of the 64-bit modes, GPTMTAR contains bits
31:0 of the 64-bit timer value and the GPTM Timer B (GPTMTBR) register contains bits 63:32. In
a 32-bit mode, the value of the prescaler is stored in the GPTM Timer B Prescale Snapshot
(GPTMTBPS) register.
GPTM Timer B (GPTMTBR)
16/32-bit Timer 0 base: 0x4003.0000
16/32-bit Timer 1 base: 0x4003.1000
16/32-bit Timer 2 base: 0x4003.2000
16/32-bit Timer 3 base: 0x4003.3000
16/32-bit Timer 4 base: 0x4003.4000
16/32-bit Timer 5 base: 0x4003.5000
32/64-bit Wide Timer 0 base: 0x4003.6000
32/64-bit Wide Timer 1 base: 0x4003.7000
32/64-bit Wide Timer 2 base: 0x4004.C000
32/64-bit Wide Timer 3 base: 0x4004.D000
32/64-bit Wide Timer 4 base: 0x4004.E000
32/64-bit Wide Timer 5 base: 0x4004.F000
Offset 0x04C
Type RO, reset 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
0
RO
0
RO
1
RO
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
1
RO
0
RO
0
RO
1
RO
1
RO
0
RO
0
RO
1
RO
0
RO
0
RO
1
RO
0
RO
1
RO
1
TBR
Type
Reset
TBR
Type
Reset
Bit/Field
Name
Type
Reset
31:0
TBR
RO
0x0000.FFFF
(for 16/32-bit)
0xFFFF.FFFF
(for 32/64-bit)
Description
GPTM Timer B Register
A read returns the current value of the GPTM Timer B Count Register,
in all cases except for Input Edge Count and Time modes. In the Input
Edge Count mode, this register contains the number of edges that have
occurred. In the Input Edge Time mode, this register contains the time
at which the last edge event took place.
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Tiva™ TM4C1237H6PZ Microcontroller
Register 20: GPTM Timer A Value (GPTMTAV), offset 0x050
When read, this register shows the current, free-running value of Timer A in all modes. Software
can use this value to determine the time elapsed between an interrupt and the ISR entry when using
the snapshot feature with the periodic operating mode. When written, the value written into this
register is loaded into the GPTMTAR register on the next clock cycle.
When a 16/32-bit GPTM is configured to one of the 32-bit modes, GPTMTAV appears as a 32-bit
register (the upper 16-bits correspond to the contents of the GPTM Timer B Value (GPTMTBV)
register). In a 16-bit mode, bits 15:0 contain the value of the counter and bits 23:16 contain the
current, free-running value of the prescaler, which is the upper 8 bits of the count in Input Edge
Count, Input Edge Time, PWM and one-shot or periodic up count modes. In one-shot or periodic
down count modes, the prescaler stored in 23:16 is a true prescaler, meaning bits 23:16 count down
before decrementing the value in bits 15:0. The prescaler in bits 31:24 always reads as 0.
When a 32/64-bit Wide GPTM is configured to one of the 64-bit modes, GPTMTAV contains bits
31:0 of the 64-bit timer value and the GPTM Timer B Value (GPTMTBV) register contains bits
63:32. In a 32-bit mode, the current, free-running value of the prescaler is stored in the GPTM Timer
A Prescale Value (GPTMTAPV) register.mint
GPTM Timer A Value (GPTMTAV)
16/32-bit Timer 0 base: 0x4003.0000
16/32-bit Timer 1 base: 0x4003.1000
16/32-bit Timer 2 base: 0x4003.2000
16/32-bit Timer 3 base: 0x4003.3000
16/32-bit Timer 4 base: 0x4003.4000
16/32-bit Timer 5 base: 0x4003.5000
32/64-bit Wide Timer 0 base: 0x4003.6000
32/64-bit Wide Timer 1 base: 0x4003.7000
32/64-bit Wide Timer 2 base: 0x4004.C000
32/64-bit Wide Timer 3 base: 0x4004.D000
32/64-bit Wide Timer 4 base: 0x4004.E000
32/64-bit Wide Timer 5 base: 0x4004.F000
Offset 0x050
Type RW, reset 0xFFFF.FFFF
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
TAV
Type
Reset
TAV
Type
Reset
Bit/Field
Name
Type
31:0
TAV
RW
Reset
Description
0xFFFF.FFFF GPTM Timer A Value
A read returns the current, free-running value of Timer A in all modes.
When written, the value written into this register is loaded into the
GPTMTAR register on the next clock cycle.
Note:
In 16-bit mode, only the lower 16-bits of the GPTMTAV
register can be written with a new value. Writes to the
prescaler bits have no effect.
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Register 21: GPTM Timer B Value (GPTMTBV), offset 0x054
When read, this register shows the current, free-running value of Timer B in all modes. Software
can use this value to determine the time elapsed between an interrupt and the ISR entry. When
written, the value written into this register is loaded into the GPTMTBR register on the next clock
cycle.
When a 16/32-bit GPTM is configured to one of the 32-bit modes, the contents of bits 15:0 in this
register are loaded into the upper 16 bits of the GPTMTAV register. Reads from this register return
the current free-running value of Timer B. In a 16-bit mode, bits 15:0 contain the value of the counter
and bits 23:16 contain the current, free-running value of the prescaler, which is the upper 8 bits of
the count in Input Edge Count, Input Edge Time, PWM and one-shot or periodic up count modes.
In one-shot or periodic down count modes, the prescaler stored in 23:16 is a true prescaler, meaning
bits 23:16 count down before decrementing the value in bits 15:0. The prescaler in bits 31:24 always
reads as 0.
When a 32/64-bit Wide GPTM is configured to one of the 64-bit modes, GPTMTBV contains bits
63:32 of the 64-bit timer value and the GPTM Timer A Value (GPTMTAV) register contains bits
31:0. In a 32-bit mode, the current, free-running value of the prescaler is stored in the GPTM Timer
B Prescale Value (GPTMTBPV) register.
GPTM Timer B Value (GPTMTBV)
16/32-bit Timer 0 base: 0x4003.0000
16/32-bit Timer 1 base: 0x4003.1000
16/32-bit Timer 2 base: 0x4003.2000
16/32-bit Timer 3 base: 0x4003.3000
16/32-bit Timer 4 base: 0x4003.4000
16/32-bit Timer 5 base: 0x4003.5000
32/64-bit Wide Timer 0 base: 0x4003.6000
32/64-bit Wide Timer 1 base: 0x4003.7000
32/64-bit Wide Timer 2 base: 0x4004.C000
32/64-bit Wide Timer 3 base: 0x4004.D000
32/64-bit Wide Timer 4 base: 0x4004.E000
32/64-bit Wide Timer 5 base: 0x4004.F000
Offset 0x054
Type RW, reset 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
0
RW
0
RW
1
RW
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RW
0
RW
0
RW
1
RW
0
RW
0
RW
1
RW
1
RW
0
RW
0
RW
1
RW
0
RW
0
RW
1
RW
0
RW
1
RW
1
TBV
Type
Reset
TBV
Type
Reset
Bit/Field
Name
Type
Reset
31:0
TBV
RW
0x0000.FFFF
(for 16/32-bit)
0xFFFF.FFFF
(for 32/64-bit)
Description
GPTM Timer B Value
A read returns the current, free-running value of Timer A in all modes.
When written, the value written into this register is loaded into the
GPTMTAR register on the next clock cycle.
Note:
In 16-bit mode, only the lower 16-bits of the GPTMTBV
register can be written with a new value. Writes to the
prescaler bits have no effect.
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Register 22: GPTM RTC Predivide (GPTMRTCPD), offset 0x058
This register provides the current RTC predivider value when the timer is operating in RTC mode.
Software must perform an atomic access with consecutive reads of the GPTMTAR, GPTMTBR,
and GPTMRTCPD registers, see Figure 11-2 on page 701 for more information.
GPTM RTC Predivide (GPTMRTCPD)
16/32-bit Timer 0 base: 0x4003.0000
16/32-bit Timer 1 base: 0x4003.1000
16/32-bit Timer 2 base: 0x4003.2000
16/32-bit Timer 3 base: 0x4003.3000
16/32-bit Timer 4 base: 0x4003.4000
16/32-bit Timer 5 base: 0x4003.5000
32/64-bit Wide Timer 0 base: 0x4003.6000
32/64-bit Wide Timer 1 base: 0x4003.7000
32/64-bit Wide Timer 2 base: 0x4004.C000
32/64-bit Wide Timer 3 base: 0x4004.D000
32/64-bit Wide Timer 4 base: 0x4004.E000
32/64-bit Wide Timer 5 base: 0x4004.F000
Offset 0x058
Type RO, reset 0x0000.7FFF
31
30
29
28
27
26
25
24
23
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
reserved
Type
Reset
RTCPD
Type
Reset
Bit/Field
Name
Type
Reset
31:16
reserved
RO
0x0000
15:0
RTCPD
RO
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.7FFF RTC Predivide Counter Value
The current RTC predivider value when the timer is operating in RTC
mode. This field has no meaning in other timer modes.
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Register 23: GPTM Timer A Prescale Snapshot (GPTMTAPS), offset 0x05C
For the 32/64-bit Wide GPTM, this register shows the current value of the Timer A prescaler in the
32-bit modes. For 16-/32-bit wide GPTM, this register shows the current value of the Timer A
prescaler for periodic snapshot mode.
GPTM Timer A Prescale Snapshot (GPTMTAPS)
16/32-bit Timer 0 base: 0x4003.0000
16/32-bit Timer 1 base: 0x4003.1000
16/32-bit Timer 2 base: 0x4003.2000
16/32-bit Timer 3 base: 0x4003.3000
16/32-bit Timer 4 base: 0x4003.4000
16/32-bit Timer 5 base: 0x4003.5000
32/64-bit Wide Timer 0 base: 0x4003.6000
32/64-bit Wide Timer 1 base: 0x4003.7000
32/64-bit Wide Timer 2 base: 0x4004.C000
32/64-bit Wide Timer 3 base: 0x4004.D000
32/64-bit Wide Timer 4 base: 0x4004.E000
32/64-bit Wide Timer 5 base: 0x4004.F000
Offset 0x05C
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
PSS
Type
Reset
Bit/Field
Name
Type
Reset
Description
31:16
reserved
RO
0x0000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:0
PSS
RO
0x0000
GPTM Timer A Prescaler Snapshot
A read returns the current value of the GPTM Timer A Prescaler.
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Register 24: GPTM Timer B Prescale Snapshot (GPTMTBPS), offset 0x060
For the 32/64-bit Wide GPTM, this register shows the current value of the Timer B prescaler in the
32-bit modes. For 16-/32-bit wide GPTM, this register shows the current value of the Timer B
prescaler for periodic snapshot mode.
GPTM Timer B Prescale Snapshot (GPTMTBPS)
16/32-bit Timer 0 base: 0x4003.0000
16/32-bit Timer 1 base: 0x4003.1000
16/32-bit Timer 2 base: 0x4003.2000
16/32-bit Timer 3 base: 0x4003.3000
16/32-bit Timer 4 base: 0x4003.4000
16/32-bit Timer 5 base: 0x4003.5000
32/64-bit Wide Timer 0 base: 0x4003.6000
32/64-bit Wide Timer 1 base: 0x4003.7000
32/64-bit Wide Timer 2 base: 0x4004.C000
32/64-bit Wide Timer 3 base: 0x4004.D000
32/64-bit Wide Timer 4 base: 0x4004.E000
32/64-bit Wide Timer 5 base: 0x4004.F000
Offset 0x060
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
PSS
Type
Reset
Bit/Field
Name
Type
Reset
Description
31:16
reserved
RO
0x0000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:0
PSS
RO
0x0000
GPTM Timer A Prescaler Value
A read returns the current value of the GPTM Timer A Prescaler.
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Register 25: GPTM Timer A Prescale Value (GPTMTAPV), offset 0x064
For the 32/64-bit Wide GPTM, this register shows the current free-running value of the Timer A
prescaler in the 32-bit modes. Software can use this value in conjunction with the GPTMTAV register
to determine the time elapsed between an interrupt and the ISR entry. This register is ununsed in
16/32-bit GPTM mode.
GPTM Timer A Prescale Value (GPTMTAPV)
16/32-bit Timer 0 base: 0x4003.0000
16/32-bit Timer 1 base: 0x4003.1000
16/32-bit Timer 2 base: 0x4003.2000
16/32-bit Timer 3 base: 0x4003.3000
16/32-bit Timer 4 base: 0x4003.4000
16/32-bit Timer 5 base: 0x4003.5000
32/64-bit Wide Timer 0 base: 0x4003.6000
32/64-bit Wide Timer 1 base: 0x4003.7000
32/64-bit Wide Timer 2 base: 0x4004.C000
32/64-bit Wide Timer 3 base: 0x4004.D000
32/64-bit Wide Timer 4 base: 0x4004.E000
32/64-bit Wide Timer 5 base: 0x4004.F000
Offset 0x064
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
PSV
Type
Reset
Bit/Field
Name
Type
Reset
Description
31:16
reserved
RO
0x0000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:0
PSV
RO
0x0000
GPTM Timer A Prescaler Value
A read returns the current, free-running value of the Timer A prescaler.
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Register 26: GPTM Timer B Prescale Value (GPTMTBPV), offset 0x068
For the 32/64-bit Wide GPTM, this register shows the current free-running value of the Timer B
prescaler in the 32-bit modes. Software can use this value in conjunction with the GPTMTBV register
to determine the time elapsed between an interrupt and the ISR entry. This register is ununsed in
16/32-bit GPTM mode.
GPTM Timer B Prescale Value (GPTMTBPV)
16/32-bit Timer 0 base: 0x4003.0000
16/32-bit Timer 1 base: 0x4003.1000
16/32-bit Timer 2 base: 0x4003.2000
16/32-bit Timer 3 base: 0x4003.3000
16/32-bit Timer 4 base: 0x4003.4000
16/32-bit Timer 5 base: 0x4003.5000
32/64-bit Wide Timer 0 base: 0x4003.6000
32/64-bit Wide Timer 1 base: 0x4003.7000
32/64-bit Wide Timer 2 base: 0x4004.C000
32/64-bit Wide Timer 3 base: 0x4004.D000
32/64-bit Wide Timer 4 base: 0x4004.E000
32/64-bit Wide Timer 5 base: 0x4004.F000
Offset 0x068
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
PSV
Type
Reset
Bit/Field
Name
Type
Reset
Description
31:16
reserved
RO
0x0000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:0
PSV
RO
0x0000
GPTM Timer B Prescaler Value
A read returns the current, free-running value of the Timer A prescaler.
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Register 27: GPTM Peripheral Properties (GPTMPP), offset 0xFC0
The GPTMPP register provides information regarding the properties of the General-Purpose Timer
module.
GPTM Peripheral Properties (GPTMPP)
16/32-bit Timer 0 base: 0x4003.0000
16/32-bit Timer 1 base: 0x4003.1000
16/32-bit Timer 2 base: 0x4003.2000
16/32-bit Timer 3 base: 0x4003.3000
16/32-bit Timer 4 base: 0x4003.4000
16/32-bit Timer 5 base: 0x4003.5000
32/64-bit Wide Timer 0 base: 0x4003.6000
32/64-bit Wide Timer 1 base: 0x4003.7000
32/64-bit Wide Timer 2 base: 0x4004.C000
32/64-bit Wide Timer 3 base: 0x4004.D000
32/64-bit Wide Timer 4 base: 0x4004.E000
32/64-bit Wide Timer 5 base: 0x4004.F000
Offset 0xFC0
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
SIZE
Bit/Field
Name
Type
Reset
31:4
reserved
RO
0
3:0
SIZE
RO
0x0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Count Size
Value Description
0
Timer A and Timer B counters are 16 bits each with an 8-bit
prescale counter.
1
Timer A and Timer B counters are 32 bits each with a 16-bit
prescale counter.
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12
Watchdog Timers
A watchdog timer can generate a non-maskable interrupt (NMI), a regular interrupt or a reset when
a time-out value is reached. The watchdog timer is used to regain control when a system has failed
due to a software error or due to the failure of an external device to respond in the expected way.
The TM4C1237H6PZ microcontroller has two Watchdog Timer Modules, one module is clocked by
the system clock (Watchdog Timer 0) and the other (Watchdog Timer 1) is clocked by the PIOSC
The two modules are identical except that WDT1 is in a different clock domain, and therefore requires
synchronizers. As a result, WDT1 has a bit defined in the Watchdog Timer Control (WDTCTL)
register to indicate when a write to a WDT1 register is complete. Software can use this bit to ensure
that the previous access has completed before starting the next access.
The TM4C1237H6PZ controller has two Watchdog Timer modules with the following features:
■ 32-bit down counter with a programmable load register
■ Separate watchdog clock with an enable
■ Programmable interrupt generation logic with interrupt masking and optional NMI function
■ Lock register protection from runaway software
■ Reset generation logic with an enable/disable
■ User-enabled stalling when the microcontroller asserts the CPU Halt flag during debug
The Watchdog Timer can be configured to generate an interrupt to the controller on its first time-out,
and to generate a reset signal on its second time-out. Once the Watchdog Timer has been configured,
the lock register can be written to prevent the timer configuration from being inadvertently altered.
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12.1
Block Diagram
Figure 12-1. WDT Module Block Diagram
WDTLOAD
Control / Clock /
Interrupt
Generation
WDTCTL
WDTICR
Interrupt/NMI
WDTRIS
32-Bit Down
Counter
WDTMIS
0x0000.0000
WDTLOCK
System Clock/
PIOSC
WDTTEST
Comparator
WDTVALUE
Identification Registers
12.2
WDTPCellID0
WDTPeriphID0
WDTPeriphID4
WDTPCellID1
WDTPeriphID1
WDTPeriphID5
WDTPCellID2
WDTPeriphID2
WDTPeriphID6
WDTPCellID3
WDTPeriphID3
WDTPeriphID7
Functional Description
The Watchdog Timer module generates the first time-out signal when the 32-bit counter reaches
the zero state after being enabled; enabling the counter also enables the watchdog timer interrupt.
The watchdog interrupt can be programmed to be a non-maskable interrupt (NMI) using the INTTYPE
bit in the WDTCTL register. After the first time-out event, the 32-bit counter is re-loaded with the
value of the Watchdog Timer Load (WDTLOAD) register, and the timer resumes counting down
from that value. Once the Watchdog Timer has been configured, the Watchdog Timer Lock
(WDTLOCK) register is written, which prevents the timer configuration from being inadvertently
altered by software.
If the timer counts down to its zero state again before the first time-out interrupt is cleared, and the
reset signal has been enabled by setting the RESEN bit in the WDTCTL register, the Watchdog timer
asserts its reset signal to the system. If the interrupt is cleared before the 32-bit counter reaches its
second time-out, the 32-bit counter is loaded with the value in the WDTLOAD register, and counting
resumes from that value.
If WDTLOAD is written with a new value while the Watchdog Timer counter is counting, then the
counter is loaded with the new value and continues counting.
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Writing to WDTLOAD does not clear an active interrupt. An interrupt must be specifically cleared
by writing to the Watchdog Interrupt Clear (WDTICR) register.
The Watchdog module interrupt and reset generation can be enabled or disabled as required. When
the interrupt is re-enabled, the 32-bit counter is preloaded with the load register value and not its
last state.
The watchdog timer is disabled by default out of reset. To achieve maximum watchdog protection
of the device, the watchdog timer can be enabled at the start of the reset vector.
12.2.1
Register Access Timing
Because the Watchdog Timer 1 module has an independent clocking domain, its registers must be
written with a timing gap between accesses. Software must guarantee that this delay is inserted
between back-to-back writes to WDT1 registers or between a write followed by a read to the registers.
The timing for back-to-back reads from the WDT1 module has no restrictions. The WRC bit in the
Watchdog Control (WDTCTL) register for WDT1 indicates that the required timing gap has elapsed.
This bit is cleared on a write operation and set once the write completes, indicating to software that
another write or read may be started safely. Software should poll WDTCTL for WRC=1 prior to
accessing another register. Note that WDT0 does not have this restriction as it runs off the system
clock.
12.3
Initialization and Configuration
To use the WDT, its peripheral clock must be enabled by setting the Rn bit in the Watchdog Timer
Run Mode Clock Gating Control (RCGCWD) register, see page 328.
The Watchdog Timer is configured using the following sequence:
1. Load the WDTLOAD register with the desired timer load value.
2. If WDT1, wait for the WRC bit in the WDTCTL register to be set.
3. If the Watchdog is configured to trigger system resets, set the RESEN bit in the WDTCTL register.
4. If WDT1, wait for the WRC bit in the WDTCTL register to be set.
5. Set the INTEN bit in the WDTCTL register to enable the Watchdog, enable interrupts, and lock
the control register.
If software requires that all of the watchdog registers are locked, the Watchdog Timer module can
be fully locked by writing any value to the WDTLOCK register. To unlock the Watchdog Timer, write
a value of 0x1ACC.E551.
To service the watchdog, periodically reload the count value into the WDTLOAD register to restart
the count. The interrupt can be enabled using the INTEN bit in the WDTCTL register to allow the
processor to attempt corrective action if the watchdog is not serviced often enough. The RESEN bit
in WDTCTL can be set so that the system resets if the failure is not recoverable using the ISR.
12.4
Register Map
Table 12-1 on page 766 lists the Watchdog registers. The offset listed is a hexadecimal increment
to the register's address, relative to the Watchdog Timer base address:
■ WDT0: 0x4000.0000
■ WDT1: 0x4000.1000
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Note that the Watchdog Timer module clock must be enabled before the registers can be programmed
(see page 328).
Table 12-1. Watchdog Timers Register Map
Offset
Name
0x000
Reset
WDTLOAD
RW
0xFFFF.FFFF
Watchdog Load
767
0x004
WDTVALUE
RO
0xFFFF.FFFF
Watchdog Value
768
0x008
WDTCTL
RW
0x0000.0000
(WDT0)
0x8000.0000
(WDT1)
Watchdog Control
769
0x00C
WDTICR
WO
-
Watchdog Interrupt Clear
771
0x010
WDTRIS
RO
0x0000.0000
Watchdog Raw Interrupt Status
772
0x014
WDTMIS
RO
0x0000.0000
Watchdog Masked Interrupt Status
773
0x418
WDTTEST
RW
0x0000.0000
Watchdog Test
774
0xC00
WDTLOCK
RW
0x0000.0000
Watchdog Lock
775
0xFD0
WDTPeriphID4
RO
0x0000.0000
Watchdog Peripheral Identification 4
776
0xFD4
WDTPeriphID5
RO
0x0000.0000
Watchdog Peripheral Identification 5
777
0xFD8
WDTPeriphID6
RO
0x0000.0000
Watchdog Peripheral Identification 6
778
0xFDC
WDTPeriphID7
RO
0x0000.0000
Watchdog Peripheral Identification 7
779
0xFE0
WDTPeriphID0
RO
0x0000.0005
Watchdog Peripheral Identification 0
780
0xFE4
WDTPeriphID1
RO
0x0000.0018
Watchdog Peripheral Identification 1
781
0xFE8
WDTPeriphID2
RO
0x0000.0018
Watchdog Peripheral Identification 2
782
0xFEC
WDTPeriphID3
RO
0x0000.0001
Watchdog Peripheral Identification 3
783
0xFF0
WDTPCellID0
RO
0x0000.000D
Watchdog PrimeCell Identification 0
784
0xFF4
WDTPCellID1
RO
0x0000.00F0
Watchdog PrimeCell Identification 1
785
0xFF8
WDTPCellID2
RO
0x0000.0006
Watchdog PrimeCell Identification 2
786
0xFFC
WDTPCellID3
RO
0x0000.00B1
Watchdog PrimeCell Identification 3
787
12.5
Description
See
page
Type
Register Descriptions
The remainder of this section lists and describes the WDT registers, in numerical order by address
offset.
766
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Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Register 1: Watchdog Load (WDTLOAD), offset 0x000
This register is the 32-bit interval value used by the 32-bit counter. When this register is written, the
value is immediately loaded and the counter restarts counting down from the new value. If the
WDTLOAD register is loaded with 0x0000.0000, an interrupt is immediately generated.
Watchdog Load (WDTLOAD)
WDT0 base: 0x4000.0000
WDT1 base: 0x4000.1000
Offset 0x000
Type RW, reset 0xFFFF.FFFF
31
30
29
28
27
26
25
24
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
15
14
13
12
11
10
9
8
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
23
22
21
20
19
18
17
16
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
7
6
5
4
3
2
1
0
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
WDTLOAD
Type
Reset
WDTLOAD
Type
Reset
Bit/Field
Name
Type
31:0
WDTLOAD
RW
Reset
RW
1
Description
0xFFFF.FFFF Watchdog Load Value
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Texas Instruments-Production Data
Watchdog Timers
Register 2: Watchdog Value (WDTVALUE), offset 0x004
This register contains the current count value of the timer.
Watchdog Value (WDTVALUE)
WDT0 base: 0x4000.0000
WDT1 base: 0x4000.1000
Offset 0x004
Type RO, reset 0xFFFF.FFFF
31
30
29
28
27
26
25
24
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
15
14
13
12
11
10
9
8
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
23
22
21
20
19
18
17
16
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
7
6
5
4
3
2
1
0
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
WDTVALUE
Type
Reset
WDTVALUE
Type
Reset
Bit/Field
Name
Type
31:0
WDTVALUE
RO
Reset
RO
1
Description
0xFFFF.FFFF Watchdog Value
Current value of the 32-bit down counter.
768
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Register 3: Watchdog Control (WDTCTL), offset 0x008
This register is the watchdog control register. The watchdog timer can be configured to generate a
reset signal (on second time-out) or an interrupt on time-out.
When the watchdog interrupt has been enabled by setting the INTEN bit, all subsequent writes to
the INTEN bit are ignored. The only mechanisms that can re-enable writes to this bit are a hardware
reset or a software reset initiated by setting the appropriate bit in the Watchdog Timer Software
Reset (SRWD) register.
Important: Because the Watchdog Timer 1 module has an independent clocking domain, its
registers must be written with a timing gap between accesses. Software must guarantee
that this delay is inserted between back-to-back writes to WDT1 registers or between
a write followed by a read to the registers. The timing for back-to-back reads from the
WDT1 module has no restrictions. The WRC bit in the Watchdog Control (WDTCTL)
register for WDT1 indicates that the required timing gap has elapsed. This bit is cleared
on a write operation and set once the write completes, indicating to software that another
write or read may be started safely. Software should poll WDTCTL for WRC=1 prior to
accessing another register. Note that WDT0 does not have this restriction as it runs off
the system clock and therefore does not have a WRC bit.
Watchdog Control (WDTCTL)
WDT0 base: 0x4000.0000
WDT1 base: 0x4000.1000
Offset 0x008
Type RW, reset 0x0000.0000 (WDT0) and 0x8000.0000 (WDT1)
31
30
29
28
27
26
25
24
22
21
20
19
18
17
16
RO
1
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
INTTYPE
RESEN
INTEN
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
RW
0
RW
0
WRC
Type
Reset
23
reserved
reserved
Type
Reset
RO
0
Bit/Field
Name
Type
Reset
31
WRC
RO
1
Description
Write Complete
The WRC values are defined as follows:
Value Description
0
A write access to one of the WDT1 registers is in progress.
1
A write access is not in progress, and WDT1 registers can be
read or written.
Note:
30:3
reserved
RO
0x000.000
This bit is reserved for WDT0 and has a reset value of 0.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
June 12, 2014
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Watchdog Timers
Bit/Field
Name
Type
Reset
2
INTTYPE
RW
0
Description
Watchdog Interrupt Type
The INTTYPE values are defined as follows:
Value Description
1
RESEN
RW
0
0
Watchdog interrupt is a standard interrupt.
1
Watchdog interrupt is a non-maskable interrupt.
Watchdog Reset Enable
The RESEN values are defined as follows:
Value Description
0
INTEN
RW
0
0
Disabled.
1
Enable the Watchdog module reset output.
Watchdog Interrupt Enable
The INTEN values are defined as follows:
Value Description
0
Interrupt event disabled. Once this bit is set, it can only be
cleared by a hardware reset or a software reset initiated by
setting the appropriate bit in the Watchdog Timer Software
Reset (SRWD) register.
1
Interrupt event enabled. Once enabled, all writes are ignored.
Setting this bit enables the Watchdog Timer.
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Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C
This register is the interrupt clear register. A write of any value to this register clears the Watchdog
interrupt and reloads the 32-bit counter from the WDTLOAD register. Write to this register when a
watchdog time-out interrupt has occurred to properly service the Watchdog. Value for a read or
reset is indeterminate.
Note:
Locking the watchdog registers by using the WDTLOCK register does not affect the WDTICR
register and allows interrupts to always be serviced. Thus, a write at any time of the WDTICR
register clears the WDTMIS register and reloads the 32-bit counter from the WDTLOAD
register. The WDTICR register should only be written when interrupts have triggered and
need to be serviced.
Watchdog Interrupt Clear (WDTICR)
WDT0 base: 0x4000.0000
WDT1 base: 0x4000.1000
Offset 0x00C
Type WO, reset 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
WDTINTCLR
Type
Reset
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
15
14
13
12
11
10
9
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
8
7
6
5
4
3
2
1
0
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WDTINTCLR
Type
Reset
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
Bit/Field
Name
Type
Reset
31:0
WDTINTCLR
WO
-
WO
-
WO
-
Description
Watchdog Interrupt Clear
A write of any value to this register clears the Watchdog interrupt and
reloads the 32-bit counter from the WDTLOAD register. Write to this
register when a watchdog time-out interrupt has occurred to properly
service the Watchdog. Value for a read or reset is indeterminate.
June 12, 2014
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Texas Instruments-Production Data
Watchdog Timers
Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010
This register is the raw interrupt status register. Watchdog interrupt events can be monitored via
this register if the controller interrupt is masked.
Watchdog Raw Interrupt Status (WDTRIS)
WDT0 base: 0x4000.0000
WDT1 base: 0x4000.1000
Offset 0x010
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:1
reserved
RO
0x0000.000
0
WDTRIS
RO
0
RO
0
WDTRIS
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Watchdog Raw Interrupt Status
Value Description
0
The watchdog has not timed out.
1
A watchdog time-out event has occurred.
772
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014
This register is the masked interrupt status register. The value of this register is the logical AND of
the raw interrupt bit and the Watchdog interrupt enable bit.
Watchdog Masked Interrupt Status (WDTMIS)
WDT0 base: 0x4000.0000
WDT1 base: 0x4000.1000
Offset 0x014
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:1
reserved
RO
0x0000.000
0
WDTMIS
RO
0
RO
0
WDTMIS
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Watchdog Masked Interrupt Status
Value Description
0
The watchdog has not timed out or the watchdog timer interrupt
is masked.
1
A watchdog time-out event has been signalled to the interrupt
controller.
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Texas Instruments-Production Data
Watchdog Timers
Register 7: Watchdog Test (WDTTEST), offset 0x418
This register provides user-enabled stalling when the microcontroller asserts the CPU halt flag
during debug.
Watchdog Test (WDTTEST)
WDT0 base: 0x4000.0000
WDT1 base: 0x4000.1000
Offset 0x418
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
STALL
Bit/Field
Name
Type
Reset
31:9
reserved
RO
0x0000.00
8
STALL
RW
0
RW
0
reserved
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Watchdog Stall Enable
Value Description
7:0
reserved
RO
0x00
0
The watchdog timer continues counting if the microcontroller is
stopped with a debugger.
1
If the microcontroller is stopped with a debugger, the watchdog
timer stops counting. Once the microcontroller is restarted, the
watchdog timer resumes counting.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
774
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Register 8: Watchdog Lock (WDTLOCK), offset 0xC00
Writing 0x1ACC.E551 to the WDTLOCK register enables write access to all other registers. Writing
any other value to the WDTLOCK register re-enables the locked state for register writes to all the
other registers, except for the Watchdog Test (WDTTEST) register. The locked state will be enabled
after 2 clock cycles. Reading the WDTLOCK register returns the lock status rather than the 32-bit
value written. Therefore, when write accesses are disabled, reading the WDTLOCK register returns
0x0000.0001 (when locked; otherwise, the returned value is 0x0000.0000 (unlocked)).
Watchdog Lock (WDTLOCK)
WDT0 base: 0x4000.0000
WDT1 base: 0x4000.1000
Offset 0xC00
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
15
14
13
12
11
10
9
8
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
23
22
21
20
19
18
17
16
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
7
6
5
4
3
2
1
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
WDTLOCK
Type
Reset
WDTLOCK
Type
Reset
Bit/Field
Name
Type
31:0
WDTLOCK
RW
Reset
RW
0
Description
0x0000.0000 Watchdog Lock
A write of the value 0x1ACC.E551 unlocks the watchdog registers for
write access. A write of any other value reapplies the lock, preventing
any register updates, except for the WDTTEST register. Avoid writes
to the WDTTEST register when the watchdog registers are locked.
A read of this register returns the following values:
Value
Description
0x0000.0001 Locked
0x0000.0000 Unlocked
June 12, 2014
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Texas Instruments-Production Data
Watchdog Timers
Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 4 (WDTPeriphID4)
WDT0 base: 0x4000.0000
WDT1 base: 0x4000.1000
Offset 0xFD0
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
PID4
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
PID4
RO
0x00
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
WDT Peripheral ID Register [7:0]
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June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset
0xFD4
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 5 (WDTPeriphID5)
WDT0 base: 0x4000.0000
WDT1 base: 0x4000.1000
Offset 0xFD4
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
PID5
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
PID5
RO
0x00
RO
0
RO
0
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
WDT Peripheral ID Register [15:8]
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Texas Instruments-Production Data
Watchdog Timers
Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset
0xFD8
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 6 (WDTPeriphID6)
WDT0 base: 0x4000.0000
WDT1 base: 0x4000.1000
Offset 0xFD8
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
PID6
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
PID6
RO
0x00
RO
0
RO
0
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
WDT Peripheral ID Register [23:16]
778
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset
0xFDC
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 7 (WDTPeriphID7)
WDT0 base: 0x4000.0000
WDT1 base: 0x4000.1000
Offset 0xFDC
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
PID7
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
PID7
RO
0x00
RO
0
RO
0
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
WDT Peripheral ID Register [31:24]
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Watchdog Timers
Register 13: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset
0xFE0
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 0 (WDTPeriphID0)
WDT0 base: 0x4000.0000
WDT1 base: 0x4000.1000
Offset 0xFE0
Type RO, reset 0x0000.0005
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
1
RO
0
RO
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
PID0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
PID0
RO
0x05
RO
0
RO
0
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Watchdog Peripheral ID Register [7:0]
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Tiva™ TM4C1237H6PZ Microcontroller
Register 14: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset
0xFE4
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 1 (WDTPeriphID1)
WDT0 base: 0x4000.0000
WDT1 base: 0x4000.1000
Offset 0xFE4
Type RO, reset 0x0000.0018
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
1
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
PID1
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
PID1
RO
0x18
RO
0
RO
0
RO
0
RO
0
RO
1
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Watchdog Peripheral ID Register [15:8]
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Watchdog Timers
Register 15: Watchdog Peripheral Identification 2 (WDTPeriphID2), offset
0xFE8
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 2 (WDTPeriphID2)
WDT0 base: 0x4000.0000
WDT1 base: 0x4000.1000
Offset 0xFE8
Type RO, reset 0x0000.0018
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
1
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
PID2
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
PID2
RO
0x18
RO
0
RO
0
RO
0
RO
0
RO
1
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Watchdog Peripheral ID Register [23:16]
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Tiva™ TM4C1237H6PZ Microcontroller
Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset
0xFEC
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 3 (WDTPeriphID3)
WDT0 base: 0x4000.0000
WDT1 base: 0x4000.1000
Offset 0xFEC
Type RO, reset 0x0000.0001
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
0
RO
0
RO
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
PID3
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
PID3
RO
0x01
RO
0
RO
0
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Watchdog Peripheral ID Register [31:24]
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Watchdog Timers
Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0
The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog PrimeCell Identification 0 (WDTPCellID0)
WDT0 base: 0x4000.0000
WDT1 base: 0x4000.1000
Offset 0xFF0
Type RO, reset 0x0000.000D
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
1
RO
0
RO
1
reserved
Type
Reset
reserved
Type
Reset
CID0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
CID0
RO
0x0D
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Watchdog PrimeCell ID Register [7:0]
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Tiva™ TM4C1237H6PZ Microcontroller
Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4
The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog PrimeCell Identification 1 (WDTPCellID1)
WDT0 base: 0x4000.0000
WDT1 base: 0x4000.1000
Offset 0xFF4
Type RO, reset 0x0000.00F0
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
1
RO
1
RO
1
RO
1
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
CID1
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
CID1
RO
0xF0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Watchdog PrimeCell ID Register [15:8]
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Watchdog Timers
Register 19: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8
The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog PrimeCell Identification 2 (WDTPCellID2)
WDT0 base: 0x4000.0000
WDT1 base: 0x4000.1000
Offset 0xFF8
Type RO, reset 0x0000.0006
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
1
RO
0
reserved
Type
Reset
reserved
Type
Reset
CID2
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
CID2
RO
0x06
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Watchdog PrimeCell ID Register [23:16]
786
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Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC
The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog PrimeCell Identification 3 (WDTPCellID3)
WDT0 base: 0x4000.0000
WDT1 base: 0x4000.1000
Offset 0xFFC
Type RO, reset 0x0000.00B1
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
1
RO
0
RO
1
RO
1
RO
0
RO
0
RO
0
RO
1
reserved
Type
Reset
reserved
Type
Reset
CID3
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
CID3
RO
0xB1
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Watchdog PrimeCell ID Register [31:24]
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Analog-to-Digital Converter (ADC)
13
Analog-to-Digital Converter (ADC)
An analog-to-digital converter (ADC) is a peripheral that converts a continuous analog voltage to a
discrete digital number. Two identical converter modules are included, which share 22 input channels.
The TM4C1237H6PZ ADC module features 12-bit conversion resolution and supports 22 input
channels, plus an internal temperature sensor. Each ADC module contains four programmable
sequencers allowing the sampling of multiple analog input sources without controller intervention.
Each sample sequencer provides flexible programming with fully configurable input source, trigger
events, interrupt generation, and sequencer priority. In addition, the conversion value can optionally
be diverted to a digital comparator module. Each ADC module provides eight digital comparators.
Each digital comparator evaluates the ADC conversion value against its two user-defined values to
determine the operational range of the signal. The trigger source for ADC0 and ADC1 may be
independent or the two ADC modules may operate from the same trigger source and operate on
the same or different inputs. A phase shifter can delay the start of sampling by a specified phase
angle. When using both ADC modules, it is possible to configure the converters to start the
conversions coincidentally or within a relative phase from each other, see “Sample Phase
Control” on page 794.
The TM4C1237H6PZ microcontroller provides two ADC modules with each having the following
features:
■ 22 shared analog input channels
■ 12-bit precision ADC
■ Single-ended and differential-input configurations
■ On-chip internal temperature sensor
■ Maximum sample rate of one million samples/second
■ Optional phase shift in sample time programmable from 22.5º to 337.5º
■ Four programmable sample conversion sequencers from one to eight entries long, with
corresponding conversion result FIFOs
■ Flexible trigger control
– Controller (software)
– Timers
– Analog Comparators
– GPIO
■ Hardware averaging of up to 64 samples
■ Eight digital comparators
■ Converter uses two external reference signals (VREFA+ and VREFA-) or VDDA and GNDA as the
voltage reference
■ Power and ground for the analog circuitry is separate from the digital power and ground
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Tiva™ TM4C1237H6PZ Microcontroller
■ Efficient transfers using Micro Direct Memory Access Controller (µDMA)
– Dedicated channel for each sample sequencer
– ADC module uses burst requests for DMA
13.1
Block Diagram
The TM4C1237H6PZ microcontroller contains two identical Analog-to-Digital Converter modules.
These two modules, ADC0 and ADC1, share the same 22 analog input channels. Each ADC module
operates independently and can therefore execute different sample sequences, sample any of the
analog input channels at any time, and generate different interrupts and triggers. Figure
13-1 on page 789 shows how the two modules are connected to analog inputs and the system bus.
Figure 13-1. Implementation of Two ADC Blocks
Triggers
ADC 0
Input
Channels
Interrupts/
Triggers
ADC 1
Interrupts/
Triggers
Figure 13-2 on page 790 provides details on the internal configuration of the ADC controls and data
registers.
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Analog-to-Digital Converter (ADC)
Figure 13-2. ADC Module Block Diagram
External Voltage Ref
VDDA/GNDA
Trigger Events
Comparator
GPIO
Timer
PWM
SS3
Comparator
GPIO
Timer
PWM
Sample
Sequencer 0
Control/Status
SS2
ADCSSMUX0
ADCACTSS
ADCSSEMUX0
ADCOSTAT
ADCSSCTL0
ADCUSTAT
ADCSSFSTAT0
Analog Inputs
(AINx)
ADCSSPRI
Sample
Sequencer 1
ADCSPC
ADCPP
Comparator
GPIO
Timer
PWM
Analog-to-Digital
Converter
SS1
ADCPC
ADCSSMUX1
ADCTSSEL
ADCSSEMUX1
Hardware Averager
ADCSAC
ADCSSCTL1
ADCCC
ADCSSFSTAT1
Comparator
GPIO
Timer
PWM
Sample
Sequencer 2
SS0
ADCSSMUX2
ADCSSEMUX2
ADCEMUX
FIFO Block
ADCSSCTL2
ADCPSSI
ADCSSOPn
ADCSSFSTAT2
SS0 Interrupt
SS1 Interrupt
SS2 Interrupt
SS3 Interrupt
Sample
Sequencer 3
ADCSSMUX3
Interrupt Control
Digital
Comparator
ADCSSFIFO0
ADCSSDCn
ADCSSFIFO1
ADCDCCTLn
ADCSSFIFO2
ADCDCCMPn
ADCSSFIFO3
ADCDCRIC
ADCSSEMUX3
ADCIM
ADCSSCTL3
ADCRIS
ADCSSFSTAT3
ADCISC
DC Interrupts
ADCDCISC
PWM Trigger
13.2
Signal Description
The following table lists the external signals of the ADC module and describes the function of each.
The AINx signals are analog functions for some GPIO signals. The column in the table below titled
"Pin Mux/Pin Assignment" lists the GPIO pin placement for the ADC signals. These signals are
configured by clearing the corresponding DEN bit in the GPIO Digital Enable (GPIODEN) register
and setting the corresponding AMSEL bit in the GPIO Analog Mode Select (GPIOAMSEL) register.
For more information on configuring GPIOs, see “General-Purpose Input/Outputs
(GPIOs)” on page 634. The VREFA+ and VREFA- signals (with the word "fixed" in the Pin Mux/Pin
Assignment column) have a fixed pin assignment and function and are not 5-V tolerant.
Table 13-1. ADC Signals (100LQFP)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
AIN0
12
PE3
I
Analog
Analog-to-digital converter input 0.
AIN1
13
PE2
I
Analog
Analog-to-digital converter input 1.
AIN2
14
PE1
I
Analog
Analog-to-digital converter input 2.
AIN3
15
PE0
I
Analog
Analog-to-digital converter input 3.
AIN4
100
PD7
I
Analog
Analog-to-digital converter input 4.
AIN5
99
PD6
I
Analog
Analog-to-digital converter input 5.
AIN6
98
PD5
I
Analog
Analog-to-digital converter input 6.
AIN7
97
PD4
I
Analog
Analog-to-digital converter input 7.
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Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Table 13-1. ADC Signals (100LQFP) (continued)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
AIN8
96
PE5
I
Analog
Analog-to-digital converter input 8.
AIN9
95
PE4
I
Analog
Analog-to-digital converter input 9.
AIN10
92
PB4
I
Analog
Analog-to-digital converter input 10.
AIN11
91
PB5
I
Analog
Analog-to-digital converter input 11.
AIN12
4
PD3
I
Analog
Analog-to-digital converter input 12.
AIN13
3
PD2
I
Analog
Analog-to-digital converter input 13.
AIN14
2
PD1
I
Analog
Analog-to-digital converter input 14.
AIN15
1
PD0
I
Analog
Analog-to-digital converter input 15.
AIN16
16
PH0
I
Analog
Analog-to-digital converter input 16.
AIN17
17
PH1
I
Analog
Analog-to-digital converter input 17.
AIN18
18
PH2
I
Analog
Analog-to-digital converter input 18.
AIN19
19
PH3
I
Analog
Analog-to-digital converter input 19.
AIN20
90
PE7
I
Analog
Analog-to-digital converter input 20.
AIN21
89
PE6
I
Analog
Analog-to-digital converter input 21.
VREFA+
8
fixed
-
Analog
A reference voltage used to specify the voltage at
which the ADC converts to a maximum value. This
pin is used in conjunction with VREFA-, which
specifies the minimum value . The voltage that is
applied to VREFA+ is the voltage with which an
AINn signal is converted to 4095. The VREFA+
voltage is limited to the range specified in Table
22-33 on page 1287 .
VREFA-
9
fixed
-
Analog
A reference voltage used to specify the input
voltage at which the ADC converts to a minimum
value. This pin is used in conjunction with VREFA+,
which specifies the maximum value. In other words,
the voltage that is applied to VREFA- is the voltage
with which an AINn signal is converted to 0, while
the voltage that is applied to VREFA+ is the voltage
with which an AINn signal is converted to 4095.
The VREFA- voltage is limited to the range specified
in Table 22-33 on page 1287 .
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
13.3
Functional Description
The TM4C1237H6PZ ADC collects sample data by using a programmable sequence-based approach
instead of the traditional single or double-sampling approaches found on many ADC modules. Each
sample sequence is a fully programmed series of consecutive (back-to-back) samples, allowing the
ADC to collect data from multiple input sources without having to be re-configured or serviced by
the processor. The programming of each sample in the sample sequence includes parameters such
as the input source and mode (differential versus single-ended input), interrupt generation on sample
completion, and the indicator for the last sample in the sequence. In addition, the μDMA can be
used to more efficiently move data from the sample sequencers without CPU intervention.
13.3.1
Sample Sequencers
The sampling control and data capture is handled by the sample sequencers. All of the sequencers
are identical in implementation except for the number of samples that can be captured and the depth
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Analog-to-Digital Converter (ADC)
of the FIFO. Table 13-2 on page 792 shows the maximum number of samples that each sequencer
can capture and its corresponding FIFO depth. Each sample that is captured is stored in the FIFO.
In this implementation, each FIFO entry is a 32-bit word, with the lower 12 bits containing the
conversion result.
Table 13-2. Samples and FIFO Depth of Sequencers
Sequencer
Number of Samples
Depth of FIFO
SS3
1
1
SS2
4
4
SS1
4
4
SS0
8
8
For a given sample sequence, each sample is defined by bit fields in the ADC Sample Sequence
Input Multiplexer Select (ADCSSMUXn), ADC Sample Sequence Extended Input Multiplexer
Select (ADCSSEMUXn) and ADC Sample Sequence Control (ADCSSCTLn) registers, where
"n" corresponds to the sequence number. The ADCSSMUXn and ADCSSEMUXn fields select the
input pin, while the ADCSSCTLn fields contain the sample control bits corresponding to parameters
such as temperature sensor selection, interrupt enable, end of sequence, and differential input
mode. Sample sequencers are enabled by setting the respective ASENn bit in the ADC Active
Sample Sequencer (ADCACTSS) register and should be configured before being enabled. Sampling
is then initiated by setting the SSn bit in the ADC Processor Sample Sequence Initiate (ADCPSSI)
register. In addition, sample sequences may be initiated on multiple ADC modules simultaneously
using the GSYNC and SYNCWAIT bits in the ADCPSSI register during the configuration of each ADC
module. For more information on using these bits, refer to page 832.
When configuring a sample sequence, multiple uses of the same input pin within the same sequence
are allowed. In the ADCSSCTLn register, the IEn bits can be set for any combination of samples,
allowing interrupts to be generated after every sample in the sequence if necessary. Also, the END
bit can be set at any point within a sample sequence. For example, if Sequencer 0 is used, the END
bit can be set in the nibble associated with the fifth sample, allowing Sequencer 0 to complete
execution of the sample sequence after the fifth sample.
After a sample sequence completes execution, the result data can be retrieved from the ADC
Sample Sequence Result FIFO (ADCSSFIFOn) registers. The FIFOs are simple circular buffers
that read a single address to "pop" result data. For software debug purposes, the positions of the
FIFO head and tail pointers are visible in the ADC Sample Sequence FIFO Status (ADCSSFSTATn)
registers along with FULL and EMPTY status flags. If a write is attempted when the FIFO is full, the
write does not occur and an overflow condition is indicated. Overflow and underflow conditions are
monitored using the ADCOSTAT and ADCUSTAT registers.
13.3.2
Module Control
Outside of the sample sequencers, the remainder of the control logic is responsible for tasks such
as:
■ Interrupt generation
■ DMA operation
■ Sequence prioritization
■ Trigger configuration
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■ Comparator configuration
■ External voltage reference
■ Sample phase control
■ Module clocking
Most of the ADC control logic runs at the ADC clock rate of 16 MHz. The internal ADC divider is
configured for 16-MHz operation automatically by hardware when the system XTAL is selected with
the PLL.
13.3.2.1
Interrupts
The register configurations of the sample sequencers and digital comparators dictate which events
generate raw interrupts, but do not have control over whether the interrupt is actually sent to the
interrupt controller. The ADC module's interrupt signals are controlled by the state of the MASK bits
in the ADC Interrupt Mask (ADCIM) register. Interrupt status can be viewed at two locations: the
ADC Raw Interrupt Status (ADCRIS) register, which shows the raw status of the various interrupt
signals; and the ADC Interrupt Status and Clear (ADCISC) register, which shows active interrupts
that are enabled by the ADCIM register. Sequencer interrupts are cleared by writing a 1 to the
corresponding IN bit in ADCISC. Digital comparator interrupts are cleared by writing a 1 to the ADC
Digital Comparator Interrupt Status and Clear (ADCDCISC) register.
13.3.2.2
DMA Operation
DMA may be used to increase efficiency by allowing each sample sequencer to operate independently
and transfer data without processor intervention or reconfiguration. The ADC module provides a
request signal from each sample sequencer to the associated dedicated channel of the μDMA
controller. The ADC does not support single transfer requests. A burst transfer request is asserted
when the interrupt bit for the sample sequence is set (IE bit in the ADCSSCTLn register is set).
The arbitration size of the μDMA transfer must be a power of 2, and the associated IE bits in the
ADCSSCTLn register must be set. For example, if the μDMA channel of SS0 has an arbitration
size of four, the IE3 bit (4th sample) and the IE7 bit (8th sample) must be set. Thus the μDMA
request occurs every time 4 samples have been acquired. No other special steps are needed to
enable the ADC module for μDMA operation.
Refer to the “Micro Direct Memory Access (μDMA)” on page 570 for more details about programming
the μDMA controller.
13.3.2.3
Prioritization
When sampling events (triggers) happen concurrently, they are prioritized for processing by the
values in the ADC Sample Sequencer Priority (ADCSSPRI) register. Valid priority values are in
the range of 0-3, with 0 being the highest priority and 3 being the lowest. Multiple active sample
sequencer units with the same priority do not provide consistent results, so software must ensure
that all active sample sequencer units have a unique priority value.
13.3.2.4
Sampling Events
Sample triggering for each sample sequencer is defined in the ADC Event Multiplexer Select
(ADCEMUX) register. Trigger sources include processor (default), analog comparators, an external
signal on a GPIO specified by the GPIO ADC Control (GPIOADCCTL) register, a GP Timer, and
continuous sampling. The processor triggers sampling by setting the SSx bits in the ADC Processor
Sample Sequence Initiate (ADCPSSI) register.
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Care must be taken when using the continuous sampling trigger. If a sequencer's priority is too high,
it is possible to starve other lower priority sequencers. Generally, a sample sequencer using
continuous sampling should be set to the lowest priority. Continuous sampling can be used with a
digital comparator to cause an interrupt when a particular voltage is seen on an input.
13.3.2.5
Sample Phase Control
The trigger source for ADC0 and ADC1 may be independent or the two ADC modules may operate
from the same trigger source and operate on the same or different inputs. If the converters are
running at the same sample rate, they may be configured to start the conversions coincidentally or
with one of 15 different discrete phases relative to each other. The sample time can be delayed
from the standard sampling time in 22.5° increments up to 337.5º using the ADC Sample Phase
Control (ADCSPC) register. Figure 13-3 on page 794 shows an example of various phase
relationships at a 1 Msps rate.
Figure 13-3. ADC Sample Phases
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
ADC Sample Clock
PHASE 0x0 (0.0°)
PHASE 0x1 (22.5°)
.
.
.
.
.
.
.
.
.
.
.
.
PHASE 0xE (315.0°)
PHASE 0xF (337.5°)
This feature can be used to double the sampling rate of an input. Both ADC module 0 and ADC
module 1 can be programmed to sample the same input. ADC module 0 could sample at the standard
position (the PHASE field in the ADCSPC register is 0x0). ADC module 1 can be configured to sample
at 180 (PHASE = 0x8). The two modules can be be synchronized using the GSYNC and SYNCWAIT
bits in the ADC Processor Sample Sequence Initiate (ADCPSSI) register. Software could then
combine the results from the two modules to create a sample rate of one million samples/second
at 16 MHz as shown in Figure 13-4 on page 794.
Figure 13-4. Doubling the ADC Sample Rate
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
ADC Sample Clock
GSYNC
ADC 0 PHASE 0x0 (0.0°)
ADC 1 PHASE 0x8 (180.0°)
Using the ADCSPC register, ADC0 and ADC1 may provide a number of interesting applications:
■ Coincident continuous sampling of different signals. The sample sequence steps run coincidently
in both converters.
– ADC Module 0, ADCSPC = 0x0, sampling AIN0
– ADC Module 1, ADCSPC = 0x0, sampling AIN1
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Note:
If two ADCs are configured to sample the same signal, a skew (phase lag) must be
added to one of the ADC modules to prevent coincident sampling. Phase lag can be
added by programming the PHASE field in the ADCSPC register.
■ Skewed sampling of the same signal. The sample sequence steps are 0.5 µs out of phase with
each other for 1 Msps. This configuration doubles the conversion bandwidth of a single input
when software combines the results as shown in Figure 13-5 on page 795.
– ADC Module 0, ADCSPC = 0x0, sampling AIN0
– ADC Module 1, ADCSPC = 0x8, sampling AIN0
Figure 13-5. Skewed Sampling
ADC0
ADC1
13.3.2.6
S1
S2
S1
S3
S2
S4
S3
S5
S4
S6
S5
S7
S6
S8
S7
S8
Module Clocking
The module is clocked by a 16-MHz clock which can be sourced by a divided version of the PLL
output, the PIOSC or an external source connected to MOSC (with the PLL in bypass mode). When
the PLL is operating, the ADC clock is derived from the PLL ÷ 25 by default. However, the PIOSC
can be used for the module clock using the ADC Clock Configuration (ADCCC) register. To use
the PIOSC to clock the ADC, first power up the PLL and then enable the PIOSC in the CS bit field
in the ADCCC register, then disable the PLL. When the PLL is bypassed, the module clock source
clock attached to the MOSC must be 16 MHz unless the PIOSC is used for the clock source. To
use the MOSC to clock the ADC, first power up the PLL and then enable the clock to the ADC
module, then disable the PLL and switch to the MOSC for the system clock. The ADC module can
continue to operate in Deep-Sleep mode if the PIOSC is the ADC module clock source.
The system clock must be at the same frequency or higher than the ADC clock. All ADC modules
share the same clock source to facilitate the synchronization of data samples between conversion
units, the selection and programming of which is provided by ADC0's ADCCC register. The ADC
modules do not run at different conversion rates.
13.3.2.7
Busy Status
The BUSY bit of the ADCACTSS register is used to indicate when the ADC is busy with a current
conversion. When there are no triggers pending which may start a new conversion in the immediate
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cycle or next few cycles, the BUSY bit reads as 0. Software must read the status of the BUSY bit as
clear before disabling the ADC clock by writing to the Analog-to-Digital Converter Run Mode
Clock Gating Control (RCGCADC) register.
13.3.2.8
Dither Enable
The DITHER bit in the ADCCTL register is used to reduce random noise in ADC sampling and keep
the ADC operation within the specified performance limits defined in Table 22-33 on page 1287. When
taking multiple consecutive samples with the ADC Module, the DITHER bit should be enabled in
the ADCCTL register along with hardware averaging in the ADC Sample Averaging Control
(ADCSAC) register. The DITHER bit is disabled by default at reset.
13.3.3
Hardware Sample Averaging Circuit
Higher precision results can be generated using the hardware averaging circuit, however, the
improved results are at the cost of throughput. Up to 64 samples can be accumulated and averaged
to form a single data entry in the sequencer FIFO. Throughput is decreased proportionally to the
number of samples in the averaging calculation. For example, if the averaging circuit is configured
to average 16 samples, the throughput is decreased by a factor of 16.
By default the averaging circuit is off, and all data from the converter passes through to the sequencer
FIFO. The averaging hardware is controlled by the ADC Sample Averaging Control (ADCSAC)
register (see page 834). A single averaging circuit has been implemented, thus all input channels
receive the same amount of averaging whether they are single-ended or differential.
Figure 13-6 shows an example in which the ADCSAC register is set to 0x2 for 4x hardware
oversampling and the IE1 bit is set for the sample sequence, resulting in an interrupt after the
second averaged value is stored in the FIFO.
Figure 13-6. Sample Averaging Example
A+B+C+D
4
A+B+C+D
4
INT
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13.3.4
Analog-to-Digital Converter
The Analog-to-Digital Converter (ADC) module uses a Successive Approximation Register (SAR)
architecture to deliver a 12-bit, low-power, high-precision conversion value. The successive
approximation uses a switched capacitor array to perform the dual functions of sampling and holding
the signal as well as providing the 12-bit DAC operation.
Figure 13-7 shows the ADC input equivalency diagram; for parameter values, see “Analog-to-Digital
Converter (ADC)” on page 1287.
Figure 13-7. ADC Input Equivalency
Tiva™ Microcontroller
Zs
Rs
VS
ESD clamps
to GND only
Input PAD
Equivalent
Circuit
RADC
Pin
Cs
VADCIN
5V ESD
Clamp
ZADC
12‐bit
SAR ADC
Converter
12‐bit
Word
IL
Pin
Input PAD
Equivalent
Circuit
Pin
Input PAD
Equivalent
Circuit
RADC
RADC
CADC
The ADC operates from both the 3.3-V analog and 1.2-V digital power supplies. The ADC clock can
be configured to reduce power consumption when ADC conversions are not required (see “System
Control” on page 221). The analog inputs are connected to the ADC through specially balanced input
paths to minimize the distortion and cross-talk on the inputs. Detailed information on the ADC power
supplies and analog inputs can be found in “Analog-to-Digital Converter (ADC)” on page 1287.
13.3.4.1
Voltage Reference
The ADC uses internal signals VREFP and VREFN as references to produce a conversion value
from the selected analog input. VREFP can be connected to either VREFA+ or VDDA and VREFN
can be connected to either VREFA- or GNDA as configured by the VREF bit in the ADC Control
(ADCCTL) register, as shown in Figure 13-8.
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Figure 13-8. ADC Voltage Reference
VDDA
VREFP
VREFA+
Voltage reference
selected using the
VREF field in the
ADCCTL register
VREFAVREFN
GNDA
ADC
The range of this conversion value is from 0x000 to 0xFFF. In single-ended-input mode, the 0x000
value corresponds to the voltage level on VREFN; the 0xFFF value corresponds to the voltage level
on VREFP. This configuration results in a resolution that can be calculated using the following
equation:
mV per ADC code = (VREFP - VREFN) / 4096
While the analog input pads can handle voltages beyond this range, the analog input voltages must
remain within the limits prescribed by Table 22-33 on page 1287 to produce accurate results. The
VREFA+ and VREFA- specifications define the useful range for the external voltage references on
VREFA+ and VREFA-, see Table 22-33 on page 1287. Care must be taken to supply a reference
voltage of acceptable quality. Figure 13-9 on page 799 shows the ADC conversion function of the
analog inputs.
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Figure 13-9. ADC Conversion Result
0xFFF
0xC00
0x800
P
EF
EF
R
VIN
-V
VR
)
N
N
EF
P
¾
(V
R
EF
EF
½
¼
(V
(V
R
R
EF
P
P
-V
-V
R
R
VR
EF
EF
N
)
)
N
0x400
- Input Saturation
13.3.5
Differential Sampling
In addition to traditional single-ended sampling, the ADC module supports differential sampling of
two analog input channels. To enable differential sampling, software must set the Dn bit in the
ADCSSCTL0n register in a step's configuration nibble.
When a sequence step is configured for differential sampling, the input pair to sample must be
configured in the ADCSSMUXn register. Differential pair 0 samples analog inputs 0 and 1; differential
pair 1 samples analog inputs 2 and 3; and so on (see Table 13-3 on page 799). The ADC does not
support other differential pairings such as analog input 0 with analog input 3.
Table 13-3. Differential Sampling Pairs
Differential Pair
Analog Inputs
0
0 and 1
1
2 and 3
2
4 and 5
3
6 and 7
4
8 and 9
5
10 and 11
6
12 and 13
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Table 13-3. Differential Sampling Pairs (continued)
Differential Pair
Analog Inputs
7
14 and 15
8
16 and 17
9
18 and 19
10
20 and 21
The voltage sampled in differential mode is the difference between the odd and even channels:
■ Input Positive Voltage: VIN+ = VIN_EVEN (even channel)
■ Input Negative Voltage: VIN- = VIN_ODD (odd channel)
The input differential voltage is defined as: VIND = VIN+ - VIN-, therefore:
■ If VIND = 0, then the conversion result = 0x800
■ If VIND > 0, then the conversion result > 0x800 (range is 0x800–0xFFF)
■ If VIND < 0, then the conversion result < 0x800 (range is 0–0x800)
When using differential sampling, the following definitions are relevant:
■ Input Common Mode Voltage: VINCM = (VIN+ + VIN-) / 2
■ Reference Positive Voltage: VREFP
■ Reference Negative Voltage: VREFN
■ Reference Differential Voltage: VREFD = VREFP - VREFN
■ Reference Common Mode Voltage: VREFCM = (VREFP + VREFN) / 2
The following conditions provide optimal results in differential mode:
■ Both VIN_EVEN and VIN_ODD must be in the range of (VREFP to VREFN) for a valid conversion
result
■ The maximum possible differential input swing, or the maximum differential range, is: -VREFDto
+VREFD, so the maximum peak-to-peak input differential signal is (+VREFD - -VREFD) = 2 *
VREFD= 2 * (VREFP - VREFN)
■ In order to take advantage of the maximum possible differential input swing, VINCM should be
very close to VREFCM, see Table 22-33 on page 1287.
If VINCM is not equal to VREFCM, the differential input signal may clip at either maximum or minimum
voltage, because either single ended input can never be larger than VREFP or smaller than VREFN,
and it is not possible to achieve full swing. Thus any difference in common mode between the input
voltage and the reference voltage limits the differential dynamic range of the ADC.
Because the maximum peak-to-peak differential signal voltage is 2 * (VREFP - VREFN), the ADC
codes are interpreted as:
mV per ADC code = (2 *(VREFP - VREFN)) / 4096
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Figure 13-10 shows how the differential voltage, ∆V, is represented in ADC codes.
Figure 13-10. Differential Voltage Representation
0xFFF
0x800
-(VREFP - VREFN)
0
VREFP - VREFN
V
- Input Saturation
13.3.6
Internal Temperature Sensor
The temperature sensor serves two primary purposes: 1) to notify the system that internal temperature
is too high or low for reliable operation and 2) to provide temperature measurements for calibration
of the Hibernate module RTC trim value.
The temperature sensor does not have a separate enable, because it also contains the bandgap
reference and must always be enabled. The reference is supplied to other analog modules; not just
the ADC. In addition, the temperature sensor has a second power-down input in the 3.3 V domain
which provides control by the Hibernation module.
The internal temperature sensor converts a temperature measurement into a voltage. This voltage
value, VTSENS, is given by the following equation (where TEMP is the temperature in °C):
VTSENS = 2.7 - ((TEMP + 55) / 75)
This relation is shown in Figure 13-11 on page 802.
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Figure 13-11. Internal Temperature Sensor Characteristic
VTSENS
VTSENS = 2.7 V – (TEMP+55)
75
2.5 V
1.633 V
0.833 V
-40° C
25° C
85° C
Temp
The temperature sensor reading can be sampled in a sample sequence by setting the TSn bit in
the ADCSSCTLn register. The temperature reading from the temperature sensor can also be given
as a function of the ADC value. The following formula calculates temperature (TEMP in ℃) based
on the ADC reading (ADCCODE, given as an unsigned decimal number from 0 to 4095) and the
maximum ADC voltage range (VREFP - VREFN):
TEMP = 147.5 - ((75 * (VREFP - VREFN) × ADCCODE) / 4096)
13.3.7
Digital Comparator Unit
An ADC is commonly used to sample an external signal and to monitor its value to ensure that it
remains in a given range. To automate this monitoring procedure and reduce the amount of processor
overhead that is required, each module provides eight digital comparators.
Conversions from the ADC that are sent to the digital comparators are compared against the user
programmable limits in the ADC Digital Comparator Range (ADCDCCMPn) registers. The ADC
can be configured to generate an interrupt depending on whether the ADC is operating within the
low, mid or high-band region configured in the ADCDCCMPn bit fields. The digital comparators four
operational modes (Once, Always, Hysteresis Once, Hysteresis Always) can be additionally applied
to the interrupt configuration.
13.3.7.1
Output Functions
ADC conversions can either be stored in the ADC Sample Sequence FIFOs or compared using the
digital comparator resources as defined by the SnDCOP bits in the ADC Sample Sequence n
Operation (ADCSSOPn) register. These selected ADC conversions are used by their respective
digital comparator to monitor the external signal. Each comparator has two possible output functions:
processor interrupts and triggers.
Each function has its own state machine to track the monitored signal. Even though the interrupt
and trigger functions can be enabled individually or both at the same time, the same conversion
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data is used by each function to determine if the right conditions have been met to assert the
associated output.
Interrupts
The digital comparator interrupt function is enabled by setting the CIE bit in the ADC Digital
Comparator Control (ADCDCCTLn) register. This bit enables the interrupt function state machine
to start monitoring the incoming ADC conversions. When the appropriate set of conditions is met,
and the DCONSSx bit is set in the ADCIM register, an interrupt is sent to the interrupt controller.
Note:
13.3.7.2
Only a single DCONSSn bit should be set at any given time. Setting more than one of these
bits results in the INRDC bit from the ADCRIS register being masked, and no interrupt is
generated on any of the sample sequencer interrupt lines. It is recommended that when
interrupts are used, they are enabled on alternating samples or at the end of the sample
sequence.
Operational Modes
Four operational modes are provided to support a broad range of applications and multiple possible
signaling requirements: Always, Once, Hysteresis Always, and Hysteresis Once. The operational
mode is selected using the CIM field in the ADCDCCTLn register.
Always Mode
In the Always operational mode, the associated interrupt or trigger is asserted whenever the ADC
conversion value meets its comparison criteria. The result is a string of assertions on the interrupt
or trigger while the conversions are within the appropriate range.
Once Mode
In the Once operational mode, the associated interrupt or trigger is asserted whenever the ADC
conversion value meets its comparison criteria, and the previous ADC conversion value did not.
The result is a single assertion of the interrupt or trigger when the conversions are within the
appropriate range.
Hysteresis-Always Mode
The Hysteresis-Always operational mode can only be used in conjunction with the low-band or
high-band regions because the mid-band region must be crossed and the opposite region entered
to clear the hysteresis condition. In the Hysteresis-Always mode, the associated interrupt or trigger
is asserted in the following cases: 1) the ADC conversion value meets its comparison criteria or 2)
a previous ADC conversion value has met the comparison criteria, and the hysteresis condition has
not been cleared by entering the opposite region. The result is a string of assertions on the interrupt
or trigger that continue until the opposite region is entered.
Hysteresis-Once Mode
The Hysteresis-Once operational mode can only be used in conjunction with the low-band or
high-band regions because the mid-band region must be crossed and the opposite region entered
to clear the hysteresis condition. In the Hysteresis-Once mode, the associated interrupt or trigger
is asserted only when the ADC conversion value meets its comparison criteria, the hysteresis
condition is clear, and the previous ADC conversion did not meet the comparison criteria. The result
is a single assertion on the interrupt or trigger.
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13.3.7.3
Function Ranges
The two comparison values, COMP0 and COMP1, in the ADC Digital Comparator Range
(ADCDCCMPn) register effectively break the conversion area into three distinct regions. These
regions are referred to as the low-band (less than COMP0), mid-band (greater than COMP0 but less
than or equal to COMP1), and high-band (greater than or equal to COMP1) regions. COMP0 and COMP1
may be programmed to the same value, effectively creating two regions, but COMP1 must always
be greater than or equal to the value of COMP0. A COMP1 value that is less than COMP0 generates
unpredictable results.
Low-Band Operation
To operate in the low-band region, the CIC field field in the ADCDCCTLn register must be
programmed to 0x0. This setting causes interrupts or triggers to be generated in the low-band region
as defined by the programmed operational mode. An example of the state of the interrupt/trigger
signal in the low-band region for each of the operational modes is shown in Figure 13-12 on page 804.
Note that a "0" in a column following the operational mode name (Always, Once, Hysteresis Always,
and Hysteresis Once) indicates that the interrupt or trigger signal is deasserted and a "1" indicates
that the signal is asserted.
Figure 13-12. Low-Band Operation (CIC=0x0)
COMP1
COMP0
Always –
0
0
0
0
1
1
1
0
0
1
1
0
0
0
0
1
Once –
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
1
Hysteresis Always –
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
Hysteresis Once –
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
Mid-Band Operation
To operate in the mid-band region, the CIC field field in the ADCDCCTLn register must be
programmed to 0x1. This setting causes interrupts or triggers to be generated in the mid-band region
according the operation mode. Only the Always and Once operational modes are available in the
mid-band region. An example of the state of the interrupt/trigger signal in the mid-band region for
each of the allowed operational modes is shown in Figure 13-13 on page 805. Note that a "0" in a
column following the operational mode name (Always or Once) indicates that the interrupt or trigger
signal is deasserted and a "1" indicates that the signal is asserted.
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Figure 13-13. Mid-Band Operation (CIC=0x1)
COMP1
COMP0
Always –
0
0
1
1
0
0
0
1
1
1
0
0
1
1
0
0
Once –
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
Hysteresis Always –
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Hysteresis Once –
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
High-Band Operation
To operate in the high-band region, the CIC field field in the ADCDCCTLn register must be
programmed to 0x3. This setting causes interrupts or triggers to be generated in the high-band
region according the operation mode. An example of the state of the interrupt/trigger signal in the
high-band region for each of the allowed operational modes is shown in Figure 13-14 on page 806.
Note that a "0" in a column following the operational mode name (Always, Once, Hysteresis Always,
and Hysteresis Once) indicates that the interrupt or trigger signal is deasserted and a "1" indicates
that the signal is asserted.
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Figure 13-14. High-Band Operation (CIC=0x3)
COMP1
COMP0
13.4
Always –
0
0
0
0
1
1
1
0
0
1
1
0
0
0
1
1
Once –
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
Hysteresis Always –
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
Hysteresis Once –
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
Initialization and Configuration
In order for the ADC module to be used, the PLL must be enabled and programmed to a supported
crystal frequency in the RCC register (see page 248). Using unsupported frequencies can cause
faulty operation in the ADC module.
13.4.1
Module Initialization
Initialization of the ADC module is a simple process with very few steps: enabling the clock to the
ADC, disabling the analog isolation circuit associated with all inputs that are to be used, and
reconfiguring the sample sequencer priorities (if needed).
The initialization sequence for the ADC is as follows:
1. Enable the ADC clock using the RCGCADC register (see page 344).
2. Enable the clock to the appropriate GPIO modules via the RCGCGPIO register (see page 331).
To find out which GPIO ports to enable, refer to “Signal Description” on page 790.
3. Set the GPIO AFSEL bits for the ADC input pins (see page 659). To determine which GPIOs to
configure, see Table 21-4 on page 1242.
4. Configure the AINx signals to be analog inputs by clearing the corresponding DEN bit in the
GPIO Digital Enable (GPIODEN) register (see page 670).
5. Disable the analog isolation circuit for all ADC input pins that are to be used by writing a 1 to
the appropriate bits of the GPIOAMSEL register (see page 675) in the associated GPIO block.
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6. If required by the application, reconfigure the sample sequencer priorities in the ADCSSPRI
register. The default configuration has Sample Sequencer 0 with the highest priority and Sample
Sequencer 3 as the lowest priority.
13.4.2
Sample Sequencer Configuration
Configuration of the sample sequencers is slightly more complex than the module initialization
because each sample sequencer is completely programmable.
The configuration for each sample sequencer should be as follows:
1. Ensure that the sample sequencer is disabled by clearing the corresponding ASENn bit in the
ADCACTSS register. Programming of the sample sequencers is allowed without having them
enabled. Disabling the sequencer during programming prevents erroneous execution if a trigger
event were to occur during the configuration process.
2. Configure the trigger event for the sample sequencer in the ADCEMUX register.
3. For each sample in the sample sequence, configure the corresponding input source in the
ADCSSMUXn and ADCSSEMUXn registers.
4. For each sample in the sample sequence, configure the sample control bits in the corresponding
nibble in the ADCSSCTLn register. When programming the last nibble, ensure that the END bit
is set. Failure to set the END bit causes unpredictable behavior.
5. If interrupts are to be used, set the corresponding MASK bit in the ADCIM register.
6. Enable the sample sequencer logic by setting the corresponding ASENn bit in the ADCACTSS
register.
13.5
Register Map
Table 13-4 on page 807 lists the ADC registers. The offset listed is a hexadecimal increment to the
register's address, relative to that ADC module's base address of:
■ ADC0: 0x4003.8000
■ ADC1: 0x4003.9000
Note that the ADC module clock must be enabled before the registers can be programmed (see
page 344). There must be a delay of 3 system clocks after the ADC module clock is enabled before
any ADC module registers are accessed.
Table 13-4. ADC Register Map
Offset
Name
0x000
Description
See
page
Type
Reset
ADCACTSS
RW
0x0000.0000
ADC Active Sample Sequencer
810
0x004
ADCRIS
RO
0x0000.0000
ADC Raw Interrupt Status
812
0x008
ADCIM
RW
0x0000.0000
ADC Interrupt Mask
814
0x00C
ADCISC
RW1C
0x0000.0000
ADC Interrupt Status and Clear
817
0x010
ADCOSTAT
RW1C
0x0000.0000
ADC Overflow Status
820
0x014
ADCEMUX
RW
0x0000.0000
ADC Event Multiplexer Select
822
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Texas Instruments-Production Data
Analog-to-Digital Converter (ADC)
Table 13-4. ADC Register Map (continued)
Offset
Name
0x018
See
page
Type
Reset
Description
ADCUSTAT
RW1C
0x0000.0000
ADC Underflow Status
827
0x020
ADCSSPRI
RW
0x0000.3210
ADC Sample Sequencer Priority
828
0x024
ADCSPC
RW
0x0000.0000
ADC Sample Phase Control
830
0x028
ADCPSSI
RW
-
ADC Processor Sample Sequence Initiate
832
0x030
ADCSAC
RW
0x0000.0000
ADC Sample Averaging Control
834
0x034
ADCDCISC
RW1C
0x0000.0000
ADC Digital Comparator Interrupt Status and Clear
835
0x038
ADCCTL
RW
0x0000.0000
ADC Control
837
0x040
ADCSSMUX0
RW
0x0000.0000
ADC Sample Sequence Input Multiplexer Select 0
838
0x044
ADCSSCTL0
RW
0x0000.0000
ADC Sample Sequence Control 0
840
0x048
ADCSSFIFO0
RO
-
ADC Sample Sequence Result FIFO 0
847
0x04C
ADCSSFSTAT0
RO
0x0000.0100
ADC Sample Sequence FIFO 0 Status
848
0x050
ADCSSOP0
RW
0x0000.0000
ADC Sample Sequence 0 Operation
850
0x054
ADCSSDC0
RW
0x0000.0000
ADC Sample Sequence 0 Digital Comparator Select
852
0x058
ADCSSEMUX0
RW
0x0000.0000
ADC Sample Sequence Extended Input Multiplexer Select
0
854
0x060
ADCSSMUX1
RW
0x0000.0000
ADC Sample Sequence Input Multiplexer Select 1
856
0x064
ADCSSCTL1
RW
0x0000.0000
ADC Sample Sequence Control 1
857
0x068
ADCSSFIFO1
RO
-
ADC Sample Sequence Result FIFO 1
847
0x06C
ADCSSFSTAT1
RO
0x0000.0100
ADC Sample Sequence FIFO 1 Status
848
0x070
ADCSSOP1
RW
0x0000.0000
ADC Sample Sequence 1 Operation
861
0x074
ADCSSDC1
RW
0x0000.0000
ADC Sample Sequence 1 Digital Comparator Select
862
0x078
ADCSSEMUX1
RW
0x0000.0000
ADC Sample Sequence Extended Input Multiplexer Select
1
864
0x080
ADCSSMUX2
RW
0x0000.0000
ADC Sample Sequence Input Multiplexer Select 2
856
0x084
ADCSSCTL2
RW
0x0000.0000
ADC Sample Sequence Control 2
857
0x088
ADCSSFIFO2
RO
-
ADC Sample Sequence Result FIFO 2
847
0x08C
ADCSSFSTAT2
RO
0x0000.0100
ADC Sample Sequence FIFO 2 Status
848
0x090
ADCSSOP2
RW
0x0000.0000
ADC Sample Sequence 2 Operation
861
0x094
ADCSSDC2
RW
0x0000.0000
ADC Sample Sequence 2 Digital Comparator Select
862
0x098
ADCSSEMUX2
RW
0x0000.0000
ADC Sample Sequence Extended Input Multiplexer Select
2
864
0x0A0
ADCSSMUX3
RW
0x0000.0000
ADC Sample Sequence Input Multiplexer Select 3
866
0x0A4
ADCSSCTL3
RW
0x0000.0000
ADC Sample Sequence Control 3
867
808
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Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Table 13-4. ADC Register Map (continued)
Offset
Name
0x0A8
Reset
ADCSSFIFO3
RO
-
ADC Sample Sequence Result FIFO 3
847
0x0AC
ADCSSFSTAT3
RO
0x0000.0100
ADC Sample Sequence FIFO 3 Status
848
0x0B0
ADCSSOP3
RW
0x0000.0000
ADC Sample Sequence 3 Operation
869
0x0B4
ADCSSDC3
RW
0x0000.0000
ADC Sample Sequence 3 Digital Comparator Select
870
0x0B8
ADCSSEMUX3
RW
0x0000.0000
ADC Sample Sequence Extended Input Multiplexer Select
3
871
0xD00
ADCDCRIC
WO
0x0000.0000
ADC Digital Comparator Reset Initial Conditions
872
0xE00
ADCDCCTL0
RW
0x0000.0000
ADC Digital Comparator Control 0
877
0xE04
ADCDCCTL1
RW
0x0000.0000
ADC Digital Comparator Control 1
877
0xE08
ADCDCCTL2
RW
0x0000.0000
ADC Digital Comparator Control 2
877
0xE0C
ADCDCCTL3
RW
0x0000.0000
ADC Digital Comparator Control 3
877
0xE10
ADCDCCTL4
RW
0x0000.0000
ADC Digital Comparator Control 4
877
0xE14
ADCDCCTL5
RW
0x0000.0000
ADC Digital Comparator Control 5
877
0xE18
ADCDCCTL6
RW
0x0000.0000
ADC Digital Comparator Control 6
877
0xE1C
ADCDCCTL7
RW
0x0000.0000
ADC Digital Comparator Control 7
877
0xE40
ADCDCCMP0
RW
0x0000.0000
ADC Digital Comparator Range 0
879
0xE44
ADCDCCMP1
RW
0x0000.0000
ADC Digital Comparator Range 1
879
0xE48
ADCDCCMP2
RW
0x0000.0000
ADC Digital Comparator Range 2
879
0xE4C
ADCDCCMP3
RW
0x0000.0000
ADC Digital Comparator Range 3
879
0xE50
ADCDCCMP4
RW
0x0000.0000
ADC Digital Comparator Range 4
879
0xE54
ADCDCCMP5
RW
0x0000.0000
ADC Digital Comparator Range 5
879
0xE58
ADCDCCMP6
RW
0x0000.0000
ADC Digital Comparator Range 6
879
0xE5C
ADCDCCMP7
RW
0x0000.0000
ADC Digital Comparator Range 7
879
0xFC0
ADCPP
RO
0x00B0.2167
ADC Peripheral Properties
880
0xFC4
ADCPC
RW
0x0000.0007
ADC Peripheral Configuration
882
0xFC8
ADCCC
RW
0x0000.0000
ADC Clock Configuration
883
13.6
Description
See
page
Type
Register Descriptions
The remainder of this section lists and describes the ADC registers, in numerical order by address
offset.
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809
Texas Instruments-Production Data
Analog-to-Digital Converter (ADC)
Register 1: ADC Active Sample Sequencer (ADCACTSS), offset 0x000
This register controls the activation of the sample sequencers. Each sample sequencer can be
enabled or disabled independently.
ADC Active Sample Sequencer (ADCACTSS)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x000
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
24
23
22
21
20
19
18
17
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
9
8
7
6
5
4
3
2
1
0
ASEN3
ASEN2
ASEN1
ASEN0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
BUSY
reserved
Type
Reset
16
Bit/Field
Name
Type
Reset
Description
31:17
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
16
BUSY
RO
0
ADC Busy
Value Description
0
ADC is idle
1
ADC is busy
15:4
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
ASEN3
RW
0
ADC SS3 Enable
Value Description
2
ASEN2
RW
0
0
Sample Sequencer 3 is disabled.
1
Sample Sequencer 3 is enabled.
ADC SS2 Enable
Value Description
1
ASEN1
RW
0
0
Sample Sequencer 2 is disabled.
1
Sample Sequencer 2 is enabled.
ADC SS1 Enable
Value Description
0
Sample Sequencer 1 is disabled.
1
Sample Sequencer 1 is enabled.
810
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Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Bit/Field
Name
Type
Reset
0
ASEN0
RW
0
Description
ADC SS0 Enable
Value Description
0
Sample Sequencer 0 is disabled.
1
Sample Sequencer 0 is enabled.
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Analog-to-Digital Converter (ADC)
Register 2: ADC Raw Interrupt Status (ADCRIS), offset 0x004
This register shows the status of the raw interrupt signal of each sample sequencer. These bits may
be polled by software to look for interrupt conditions without sending the interrupts to the interrupt
controller.
ADC Raw Interrupt Status (ADCRIS)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x004
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
24
23
22
21
20
19
18
17
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
9
8
7
6
5
4
3
2
1
0
INR3
INR2
INR1
INR0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
INRDC
reserved
Type
Reset
16
Bit/Field
Name
Type
Reset
Description
31:17
reserved
RO
0x000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
16
INRDC
RO
0
Digital Comparator Raw Interrupt Status
Value Description
0
All bits in the ADCDCISC register are clear.
1
At least one bit in the ADCDCISC register is set, meaning that
a digital comparator interrupt has occurred.
15:4
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
INR3
RO
0
SS3 Raw Interrupt Status
Value Description
0
An interrupt has not occurred.
1
A sample has completed conversion and the respective
ADCSSCTL3 IEn bit is set, enabling a raw interrupt.
This bit is cleared by writing a 1 to the IN3 bit in the ADCISC register.
2
INR2
RO
0
SS2 Raw Interrupt Status
Value Description
0
An interrupt has not occurred.
1
A sample has completed conversion and the respective
ADCSSCTL2 IEn bit is set, enabling a raw interrupt.
This bit is cleared by writing a 1 to the IN2 bit in the ADCISC register.
812
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Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Bit/Field
Name
Type
Reset
1
INR1
RO
0
Description
SS1 Raw Interrupt Status
Value Description
0
An interrupt has not occurred.
1
A sample has completed conversion and the respective
ADCSSCTL1 IEn bit is set, enabling a raw interrupt.
This bit is cleared by writing a 1 to the IN1 bit in the ADCISC register.
0
INR0
RO
0
SS0 Raw Interrupt Status
Value Description
0
An interrupt has not occurred.
1
A sample has completed conversion and the respective
ADCSSCTL0 IEn bit is set, enabling a raw interrupt.
This bit is cleared by writing a 1 to the IN0 bit in the ADCISC register.
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Texas Instruments-Production Data
Analog-to-Digital Converter (ADC)
Register 3: ADC Interrupt Mask (ADCIM), offset 0x008
This register controls whether the sample sequencer and digital comparator raw interrupt signals
are sent to the interrupt controller. Each raw interrupt signal can be masked independently.
Note:
Only a single DCONSSn bit should be set at any given time. Setting more than one of these
bits results in the INRDC bit from the ADCRIS register being masked, and no interrupt is
generated on any of the sample sequencer interrupt lines. It is recommended that when
interrupts are used, they are enabled on alternating samples or at the end of the sample
sequence.
ADC Interrupt Mask (ADCIM)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x008
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
19
18
17
16
DCONSS3 DCONSS2 DCONSS1 DCONSS0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
RW
0
RW
0
RW
0
3
2
1
0
MASK3
MASK2
MASK1
MASK0
RW
0
RW
0
RW
0
RW
0
Bit/Field
Name
Type
Reset
Description
31:20
reserved
RO
0x000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
19
DCONSS3
RW
0
Digital Comparator Interrupt on SS3
Value Description
18
DCONSS2
RW
0
0
The status of the digital comparators does not affect the SS3
interrupt status.
1
The raw interrupt signal from the digital comparators (INRDC
bit in the ADCRIS register) is sent to the interrupt controller on
the SS3 interrupt line.
Digital Comparator Interrupt on SS2
Value Description
0
The status of the digital comparators does not affect the SS2
interrupt status.
1
The raw interrupt signal from the digital comparators (INRDC
bit in the ADCRIS register) is sent to the interrupt controller on
the SS2 interrupt line.
814
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Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Bit/Field
Name
Type
Reset
17
DCONSS1
RW
0
Description
Digital Comparator Interrupt on SS1
Value Description
16
DCONSS0
RW
0
0
The status of the digital comparators does not affect the SS1
interrupt status.
1
The raw interrupt signal from the digital comparators (INRDC
bit in the ADCRIS register) is sent to the interrupt controller on
the SS1 interrupt line.
Digital Comparator Interrupt on SS0
Value Description
0
The status of the digital comparators does not affect the SS0
interrupt status.
1
The raw interrupt signal from the digital comparators (INRDC
bit in the ADCRIS register) is sent to the interrupt controller on
the SS0 interrupt line.
15:4
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
MASK3
RW
0
SS3 Interrupt Mask
Value Description
2
MASK2
RW
0
0
The status of Sample Sequencer 3 does not affect the SS3
interrupt status.
1
The raw interrupt signal from Sample Sequencer 3 (ADCRIS
register INR3 bit) is sent to the interrupt controller.
SS2 Interrupt Mask
Value Description
1
MASK1
RW
0
0
The status of Sample Sequencer 2 does not affect the SS2
interrupt status.
1
The raw interrupt signal from Sample Sequencer 2 (ADCRIS
register INR2 bit) is sent to the interrupt controller.
SS1 Interrupt Mask
Value Description
0
The status of Sample Sequencer 1 does not affect the SS1
interrupt status.
1
The raw interrupt signal from Sample Sequencer 1 (ADCRIS
register INR1 bit) is sent to the interrupt controller.
June 12, 2014
815
Texas Instruments-Production Data
Analog-to-Digital Converter (ADC)
Bit/Field
Name
Type
Reset
0
MASK0
RW
0
Description
SS0 Interrupt Mask
Value Description
0
The status of Sample Sequencer 0 does not affect the SS0
interrupt status.
1
The raw interrupt signal from Sample Sequencer 0 (ADCRIS
register INR0 bit) is sent to the interrupt controller.
816
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Register 4: ADC Interrupt Status and Clear (ADCISC), offset 0x00C
This register provides the mechanism for clearing sample sequencer interrupt conditions and shows
the status of interrupts generated by the sample sequencers and the digital comparators which have
been sent to the interrupt controller. When read, each bit field is the logical AND of the respective
INR and MASK bits. Sample sequencer interrupts are cleared by writing a 1 to the corresponding
bit position. Digital comparator interrupts are cleared by writing a 1 to the appropriate bits in the
ADCDCISC register. If software is polling the ADCRIS instead of generating interrupts, the sample
sequence INRn bits are still cleared via the ADCISC register, even if the INn bit is not set.
ADC Interrupt Status and Clear (ADCISC)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x00C
Type RW1C, reset 0x0000.0000
31
30
29
28
27
26
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
25
24
23
22
21
20
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
9
8
7
6
5
4
3
2
1
0
IN3
IN2
IN1
IN0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW1C
0
RW1C
0
RW1C
0
RW1C
0
reserved
Type
Reset
18
17
16
DCINSS3 DCINSS2 DCINSS1 DCINSS0
reserved
Type
Reset
19
Bit/Field
Name
Type
Reset
Description
31:20
reserved
RO
0x000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
19
DCINSS3
RO
0
Digital Comparator Interrupt Status on SS3
Value Description
0
No interrupt has occurred or the interrupt is masked.
1
Both the INRDC bit in the ADCRIS register and the DCONSS3
bit in the ADCIM register are set, providing a level-based
interrupt to the interrupt controller.
This bit is cleared by writing a 1 to it. Clearing this bit also clears the
INRDC bit in the ADCRIS register.
18
DCINSS2
RO
0
Digital Comparator Interrupt Status on SS2
Value Description
0
No interrupt has occurred or the interrupt is masked.
1
Both the INRDC bit in the ADCRIS register and the DCONSS2
bit in the ADCIM register are set, providing a level-based
interrupt to the interrupt controller.
This bit is cleared by writing a 1 to it. Clearing this bit also clears the
INRDC bit in the ADCRIS register.
June 12, 2014
817
Texas Instruments-Production Data
Analog-to-Digital Converter (ADC)
Bit/Field
Name
Type
Reset
17
DCINSS1
RO
0
Description
Digital Comparator Interrupt Status on SS1
Value Description
0
No interrupt has occurred or the interrupt is masked.
1
Both the INRDC bit in the ADCRIS register and the DCONSS1
bit in the ADCIM register are set, providing a level-based
interrupt to the interrupt controller.
This bit is cleared by writing a 1 to it. Clearing this bit also clears the
INRDC bit in the ADCRIS register.
16
DCINSS0
RO
0
Digital Comparator Interrupt Status on SS0
Value Description
0
No interrupt has occurred or the interrupt is masked.
1
Both the INRDC bit in the ADCRIS register and the DCONSS0
bit in the ADCIM register are set, providing a level-based
interrupt to the interrupt controller.
This bit is cleared by writing a 1 to it. Clearing this bit also clears the
INRDC bit in the ADCRIS register.
15:4
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
IN3
RW1C
0
SS3 Interrupt Status and Clear
Value Description
0
No interrupt has occurred or the interrupt is masked.
1
Both the INR3 bit in the ADCRIS register and the MASK3 bit in
the ADCIM register are set, providing a level-based interrupt to
the interrupt controller.
This bit is cleared by writing a 1. Clearing this bit also clears the INR3
bit in the ADCRIS register.
2
IN2
RW1C
0
SS2 Interrupt Status and Clear
Value Description
0
No interrupt has occurred or the interrupt is masked.
1
Both the INR2 bit in the ADCRIS register and the MASK2 bit in
the ADCIM register are set, providing a level-based interrupt to
the interrupt controller.
This bit is cleared by writing a 1. Clearing this bit also clears the INR2
bit in the ADCRIS register.
818
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Bit/Field
Name
Type
Reset
1
IN1
RW1C
0
Description
SS1 Interrupt Status and Clear
Value Description
0
No interrupt has occurred or the interrupt is masked.
1
Both the INR1 bit in the ADCRIS register and the MASK1 bit in
the ADCIM register are set, providing a level-based interrupt to
the interrupt controller.
This bit is cleared by writing a 1. Clearing this bit also clears the INR1
bit in the ADCRIS register.
0
IN0
RW1C
0
SS0 Interrupt Status and Clear
Value Description
0
No interrupt has occurred or the interrupt is masked.
1
Both the INR0 bit in the ADCRIS register and the MASK0 bit in
the ADCIM register are set, providing a level-based interrupt to
the interrupt controller.
This bit is cleared by writing a 1. Clearing this bit also clears the INR0
bit in the ADCRIS register.
June 12, 2014
819
Texas Instruments-Production Data
Analog-to-Digital Converter (ADC)
Register 5: ADC Overflow Status (ADCOSTAT), offset 0x010
This register indicates overflow conditions in the sample sequencer FIFOs. Once the overflow
condition has been handled by software, the condition can be cleared by writing a 1 to the
corresponding bit position.
ADC Overflow Status (ADCOSTAT)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x010
Type RW1C, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
OV3
OV2
OV1
OV0
RO
0
RO
0
RO
0
RO
0
RO
0
RW1C
0
RW1C
0
RW1C
0
RW1C
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:4
reserved
RO
0x0000.000
3
OV3
RW1C
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SS3 FIFO Overflow
Value Description
0
The FIFO has not overflowed.
1
The FIFO for Sample Sequencer 3 has hit an overflow condition,
meaning that the FIFO is full and a write was requested. When
an overflow is detected, the most recent write is dropped.
This bit is cleared by writing a 1.
2
OV2
RW1C
0
SS2 FIFO Overflow
Value Description
0
The FIFO has not overflowed.
1
The FIFO for Sample Sequencer 2 has hit an overflow condition,
meaning that the FIFO is full and a write was requested. When
an overflow is detected, the most recent write is dropped.
This bit is cleared by writing a 1.
1
OV1
RW1C
0
SS1 FIFO Overflow
Value Description
0
The FIFO has not overflowed.
1
The FIFO for Sample Sequencer 1 has hit an overflow condition,
meaning that the FIFO is full and a write was requested. When
an overflow is detected, the most recent write is dropped.
This bit is cleared by writing a 1.
820
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Bit/Field
Name
Type
Reset
0
OV0
RW1C
0
Description
SS0 FIFO Overflow
Value Description
0
The FIFO has not overflowed.
1
The FIFO for Sample Sequencer 0 has hit an overflow condition,
meaning that the FIFO is full and a write was requested. When
an overflow is detected, the most recent write is dropped.
This bit is cleared by writing a 1.
June 12, 2014
821
Texas Instruments-Production Data
Analog-to-Digital Converter (ADC)
Register 6: ADC Event Multiplexer Select (ADCEMUX), offset 0x014
The ADCEMUX selects the event (trigger) that initiates sampling for each sample sequencer. Each
sample sequencer can be configured with a unique trigger source.
ADC Event Multiplexer Select (ADCEMUX)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x014
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
EM3
Type
Reset
EM2
EM1
Bit/Field
Name
Type
Reset
31:16
reserved
RO
0x0000
EM0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
822
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Bit/Field
Name
Type
Reset
15:12
EM3
RW
0x0
Description
SS3 Trigger Select
This field selects the trigger source for Sample Sequencer 3.
The valid configurations for this field are:
Value
Event
0x0
Processor (default)
The trigger is initiated by setting the SSn bit in the ADCPSSI
register.
0x1
Analog Comparator 0
This trigger is configured by the Analog Comparator Control
0 (ACCTL0) register (page 1219).
0x2
Analog Comparator 1
This trigger is configured by the Analog Comparator Control
1 (ACCTL1) register (page 1219).
0x3
Analog Comparator 2
This trigger is configured by the Analog Comparator Control
2 (ACCTL2) register (page 1219).
0x4
External (GPIO Pins)
This trigger is connected to the GPIO interrupt for the
corresponding GPIO (see “ADC Trigger Source” on page 641).
0x5
Timer
In addition, the trigger must be enabled with the TnOTE bit
in the GPTMCTL register (page 726).
0x6
reserved
0x7
reserved
0x8
reserved
0x9
reserved
0xA-0xE reserved
0xF
Always (continuously sample)
June 12, 2014
823
Texas Instruments-Production Data
Analog-to-Digital Converter (ADC)
Bit/Field
Name
Type
Reset
11:8
EM2
RW
0x0
Description
SS2 Trigger Select
This field selects the trigger source for Sample Sequencer 2.
The valid configurations for this field are:
Value
Event
0x0
Processor (default)
The trigger is initiated by setting the SSn bit in the ADCPSSI
register.
0x1
Analog Comparator 0
This trigger is configured by the Analog Comparator Control
0 (ACCTL0) register (page 1219).
0x2
Analog Comparator 1
This trigger is configured by the Analog Comparator Control
1 (ACCTL1) register (page 1219).
0x3
Analog Comparator 2
This trigger is configured by the Analog Comparator Control
2 (ACCTL2) register (page 1219).
0x4
External (GPIO Pins)
This trigger is connected to the GPIO interrupt for the
corresponding GPIO (see “ADC Trigger Source” on page 641).
0x5
Timer
In addition, the trigger must be enabled with the TnOTE bit
in the GPTMCTL register (page 726).
0x6
reserved
0x7
reserved
0x8
reserved
0x9
reserved
0xA-0xE reserved
0xF
Always (continuously sample)
824
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Bit/Field
Name
Type
Reset
7:4
EM1
RW
0x0
Description
SS1 Trigger Select
This field selects the trigger source for Sample Sequencer 1.
The valid configurations for this field are:
Value
Event
0x0
Processor (default)
The trigger is initiated by setting the SSn bit in the ADCPSSI
register.
0x1
Analog Comparator 0
This trigger is configured by the Analog Comparator Control
0 (ACCTL0) register (page 1219).
0x2
Analog Comparator 1
This trigger is configured by the Analog Comparator Control
1 (ACCTL1) register (page 1219).
0x3
Analog Comparator 2
This trigger is configured by the Analog Comparator Control
2 (ACCTL2) register (page 1219).
0x4
External (GPIO Pins)
This trigger is connected to the GPIO interrupt for the
corresponding GPIO (see “ADC Trigger Source” on page 641).
0x5
Timer
In addition, the trigger must be enabled with the TnOTE bit
in the GPTMCTL register (page 726).
0x6
reserved
0x7
reserved
0x8
reserved
0x9
reserved
0xA-0xE reserved
0xF
Always (continuously sample)
June 12, 2014
825
Texas Instruments-Production Data
Analog-to-Digital Converter (ADC)
Bit/Field
Name
Type
Reset
3:0
EM0
RW
0x0
Description
SS0 Trigger Select
This field selects the trigger source for Sample Sequencer 0
The valid configurations for this field are:
Value
Event
0x0
Processor (default)
The trigger is initiated by setting the SSn bit in the ADCPSSI
register.
0x1
Analog Comparator 0
This trigger is configured by the Analog Comparator Control
0 (ACCTL0) register (page 1219).
0x2
Analog Comparator 1
This trigger is configured by the Analog Comparator Control
1 (ACCTL1) register (page 1219).
0x3
Analog Comparator 2
This trigger is configured by the Analog Comparator Control
2 (ACCTL2) register (page 1219).
0x4
External (GPIO Pins)
This trigger is connected to the GPIO interrupt for the
corresponding GPIO (see “ADC Trigger Source” on page 641).
0x5
Timer
In addition, the trigger must be enabled with the TnOTE bit
in the GPTMCTL register (page 726).
0x6
reserved
0x7
reserved
0x8
reserved
0x9
reserved
0xA-0xE reserved
0xF
Always (continuously sample)
826
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Register 7: ADC Underflow Status (ADCUSTAT), offset 0x018
This register indicates underflow conditions in the sample sequencer FIFOs. The corresponding
underflow condition is cleared by writing a 1 to the relevant bit position.
ADC Underflow Status (ADCUSTAT)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x018
Type RW1C, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
UV3
UV2
UV1
UV0
RO
0
RO
0
RO
0
RO
0
RO
0
RW1C
0
RW1C
0
RW1C
0
RW1C
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:4
reserved
RO
0x0000.000
3
UV3
RW1C
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SS3 FIFO Underflow
The valid configurations for this field are shown below. This bit is cleared
by writing a 1.
Value Description
2
UV2
RW1C
0
0
The FIFO has not underflowed.
1
The FIFO for the Sample Sequencer has hit an underflow
condition, meaning that the FIFO is empty and a read was
requested. The problematic read does not move the FIFO
pointers, and 0s are returned.
SS2 FIFO Underflow
The valid configurations are the same as those for the UV3 field. This
bit is cleared by writing a 1.
1
UV1
RW1C
0
SS1 FIFO Underflow
The valid configurations are the same as those for the UV3 field. This
bit is cleared by writing a 1.
0
UV0
RW1C
0
SS0 FIFO Underflow
The valid configurations are the same as those for the UV3 field. This
bit is cleared by writing a 1.
June 12, 2014
827
Texas Instruments-Production Data
Analog-to-Digital Converter (ADC)
Register 8: ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020
This register sets the priority for each of the sample sequencers. Out of reset, Sequencer 0 has the
highest priority, and Sequencer 3 has the lowest priority. When reconfiguring sequence priorities,
each sequence must have a unique priority for the ADC to operate properly.
ADC Sample Sequencer Priority (ADCSSPRI)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x020
Type RW, reset 0x0000.3210
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RW
1
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RW
0
RO
0
RO
0
RW
0
RW
1
RO
0
RO
0
RW
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
RO
0
SS3
RW
1
reserved
RO
0
SS2
RW
1
Bit/Field
Name
Type
Reset
31:14
reserved
RO
0x0000.0
13:12
SS3
RW
0x3
reserved
SS1
reserved
SS0
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SS3 Priority
This field contains a binary-encoded value that specifies the priority
encoding of Sample Sequencer 3. A priority encoding of 0x0 is highest
and 0x3 is lowest. The priorities assigned to the sequencers must be
uniquely mapped. The ADC may not operate properly if two or more
fields are equal.
11:10
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
9:8
SS2
RW
0x2
SS2 Priority
This field contains a binary-encoded value that specifies the priority
encoding of Sample Sequencer 2. A priority encoding of 0x0 is highest
and 0x3 is lowest. The priorities assigned to the sequencers must be
uniquely mapped. The ADC may not operate properly if two or more
fields are equal.
7:6
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5:4
SS1
RW
0x1
SS1 Priority
This field contains a binary-encoded value that specifies the priority
encoding of Sample Sequencer 1. A priority encoding of 0x0 is highest
and 0x3 is lowest. The priorities assigned to the sequencers must be
uniquely mapped. The ADC may not operate properly if two or more
fields are equal.
3:2
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
828
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Bit/Field
Name
Type
Reset
Description
1:0
SS0
RW
0x0
SS0 Priority
This field contains a binary-encoded value that specifies the priority
encoding of Sample Sequencer 0. A priority encoding of 0x0 is highest
and 0x3 is lowest. The priorities assigned to the sequencers must be
uniquely mapped. The ADC may not operate properly if two or more
fields are equal.
June 12, 2014
829
Texas Instruments-Production Data
Analog-to-Digital Converter (ADC)
Register 9: ADC Sample Phase Control (ADCSPC), offset 0x024
This register allows the ADC module to sample at one of 16 different discrete phases from 0.0°
through 337.5°. For example, the sample rate could be effectively doubled by sampling a signal
using one ADC module configured with the standard sample time and the second ADC module
configured with a 180.0° phase lag.
Note:
Care should be taken when the PHASE field is non-zero, as the resulting delay in sampling
the AINx input may result in undesirable system consequences. The time from ADC trigger
to sample is increased and could make the response time longer than anticipated. The
added latency could have ramifications in the system design. Designers should carefully
consider the impact of this delay.
ADC Sample Phase Control (ADCSPC)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x024
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
1
0
RW
0
RW
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:4
reserved
RO
0x0000.000
PHASE
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
830
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Bit/Field
Name
Type
Reset
3:0
PHASE
RW
0x0
Description
Phase Difference
This field selects the sample phase difference from the standard sample
time.
Value Description
0x0
ADC sample lags by 0.0°
0x1
ADC sample lags by 22.5°
0x2
ADC sample lags by 45.0°
0x3
ADC sample lags by 67.5°
0x4
ADC sample lags by 90.0°
0x5
ADC sample lags by 112.5°
0x6
ADC sample lags by 135.0°
0x7
ADC sample lags by 157.5°
0x8
ADC sample lags by 180.0°
0x9
ADC sample lags by 202.5°
0xA
ADC sample lags by 225.0°
0xB
ADC sample lags by 247.5°
0xC
ADC sample lags by 270.0°
0xD
ADC sample lags by 292.5°
0xE
ADC sample lags by 315.0°
0xF
ADC sample lags by 337.5°
June 12, 2014
831
Texas Instruments-Production Data
Analog-to-Digital Converter (ADC)
Register 10: ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028
This register provides a mechanism for application software to initiate sampling in the sample
sequencers. Sample sequences can be initiated individually or in any combination. When multiple
sequences are triggered simultaneously, the priority encodings in ADCSSPRI dictate execution
order.
This register also provides a means to configure and then initiate concurrent sampling on all ADC
modules. To do this, the first ADC module should be configured. The ADCPSSI register for that
module should then be written. The appropriate SS bits should be set along with the SYNCWAIT bit.
Additional ADC modules should then be configured following the same procedure. Once the final
ADC module is configured, its ADCPSSI register should be written with the appropriate SS bits set
along with the GSYNC bit. All of the ADC modules then begin concurrent sampling according to their
configuration.
ADC Processor Sample Sequence Initiate (ADCPSSI)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x028
Type RW, reset 31
30
GSYNC
Type
Reset
29
28
reserved
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
reserved
SYNCWAIT
RW
0
RO
0
RO
0
RO
0
RW
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31
GSYNC
RW
0
RO
0
RO
0
RO
0
RO
0
RO
0
3
2
1
0
SS3
SS2
SS1
SS0
WO
-
WO
-
WO
-
WO
-
Description
Global Synchronize
Value Description
30:28
reserved
RO
0x0
27
SYNCWAIT
RW
0
0
This bit is cleared once sampling has been initiated.
1
This bit initiates sampling in multiple ADC modules at the same
time. Any ADC module that has been initialized by setting an
SSn bit and the SYNCWAIT bit starts sampling once this bit is
written.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Synchronize Wait
Value Description
26:4
reserved
RO
0x0000.0
0
Sampling begins when a sample sequence has been initiated.
1
This bit allows the sample sequences to be initiated, but delays
sampling until the GSYNC bit is set.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
832
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Bit/Field
Name
Type
Reset
Description
3
SS3
WO
-
SS3 Initiate
Value Description
0
No effect.
1
Begin sampling on Sample Sequencer 3, if the sequencer is
enabled in the ADCACTSS register.
Only a write by software is valid; a read of this register returns no
meaningful data.
2
SS2
WO
-
SS2 Initiate
Value Description
0
No effect.
1
Begin sampling on Sample Sequencer 2, if the sequencer is
enabled in the ADCACTSS register.
Only a write by software is valid; a read of this register returns no
meaningful data.
1
SS1
WO
-
SS1 Initiate
Value Description
0
No effect.
1
Begin sampling on Sample Sequencer 1, if the sequencer is
enabled in the ADCACTSS register.
Only a write by software is valid; a read of this register returns no
meaningful data.
0
SS0
WO
-
SS0 Initiate
Value Description
0
No effect.
1
Begin sampling on Sample Sequencer 0, if the sequencer is
enabled in the ADCACTSS register.
Only a write by software is valid; a read of this register returns no
meaningful data.
June 12, 2014
833
Texas Instruments-Production Data
Analog-to-Digital Converter (ADC)
Register 11: ADC Sample Averaging Control (ADCSAC), offset 0x030
This register controls the amount of hardware averaging applied to conversion results. The final
conversion result stored in the FIFO is averaged from 2 AVG consecutive ADC samples at the specified
ADC speed. If AVG is 0, the sample is passed directly through without any averaging. If AVG=6,
then 64 consecutive ADC samples are averaged to generate one result in the sequencer FIFO. An
AVG=7 provides unpredictable results.
ADC Sample Averaging Control (ADCSAC)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x030
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
Bit/Field
Name
Type
Reset
31:3
reserved
RO
0x0000.000
2:0
AVG
RW
0x0
AVG
RW
0
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Hardware Averaging Control
Specifies the amount of hardware averaging that will be applied to ADC
samples. The AVG field can be any value between 0 and 6. Entering a
value of 7 creates unpredictable results.
Value Description
0x0
No hardware oversampling
0x1
2x hardware oversampling
0x2
4x hardware oversampling
0x3
8x hardware oversampling
0x4
16x hardware oversampling
0x5
32x hardware oversampling
0x6
64x hardware oversampling
0x7
reserved
834
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Register 12: ADC Digital Comparator Interrupt Status and Clear (ADCDCISC),
offset 0x034
This register provides status and acknowledgement of digital comparator interrupts. One bit is
provided for each comparator.
ADC Digital Comparator Interrupt Status and Clear (ADCDCISC)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x034
Type RW1C, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7
DCINT7
RW1C
0
RO
0
RO
0
7
6
5
4
3
2
1
0
DCINT7
DCINT6
DCINT5
DCINT4
DCINT3
DCINT2
DCINT1
DCINT0
RW1C
0
RW1C
0
RW1C
0
RW1C
0
RW1C
0
RW1C
0
RW1C
0
RW1C
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Digital Comparator 7 Interrupt Status and Clear
Value Description
0
No interrupt.
1
Digital Comparator 7 has generated an interrupt.
This bit is cleared by writing a 1.
6
DCINT6
RW1C
0
Digital Comparator 6 Interrupt Status and Clear
Value Description
0
No interrupt.
1
Digital Comparator 6 has generated an interrupt.
This bit is cleared by writing a 1.
5
DCINT5
RW1C
0
Digital Comparator 5 Interrupt Status and Clear
Value Description
0
No interrupt.
1
Digital Comparator 5 has generated an interrupt.
This bit is cleared by writing a 1.
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Analog-to-Digital Converter (ADC)
Bit/Field
Name
Type
Reset
4
DCINT4
RW1C
0
Description
Digital Comparator 4 Interrupt Status and Clear
Value Description
0
No interrupt.
1
Digital Comparator 4 has generated an interrupt.
This bit is cleared by writing a 1.
3
DCINT3
RW1C
0
Digital Comparator 3 Interrupt Status and Clear
Value Description
0
No interrupt.
1
Digital Comparator 3 has generated an interrupt.
This bit is cleared by writing a 1.
2
DCINT2
RW1C
0
Digital Comparator 2 Interrupt Status and Clear
Value Description
0
No interrupt.
1
Digital Comparator 2 has generated an interrupt.
This bit is cleared by writing a 1.
1
DCINT1
RW1C
0
Digital Comparator 1 Interrupt Status and Clear
Value Description
0
No interrupt.
1
Digital Comparator 1 has generated an interrupt.
This bit is cleared by writing a 1.
0
DCINT0
RW1C
0
Digital Comparator 0 Interrupt Status and Clear
Value Description
0
No interrupt.
1
Digital Comparator 0 has generated an interrupt.
This bit is cleared by writing a 1.
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Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Register 13: ADC Control (ADCCTL), offset 0x038
This register configures the voltage reference. The voltage references for the conversion can be
VREFA+ and VREFA- or VDDA and GNDA. Note that values set in this register apply to all ADC
modules, it is not possible to set one module to use internal references and another to use external
references.
ADC Control (ADCCTL)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x038
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
DITHER
RO
0
Bit/Field
Name
Type
Reset
31:7
reserved
RO
0x0000.000
6
DITHER
RW
0
RW
0
reserved
RO
0
VREF
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Dither Mode Enable
Value Description
5:1
reserved
RO
0
0
VREF
RW
0x0
0
Dither mode disabled
1
Dither mode enabled
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Voltage Reference Select
Value Description
0x0
VDDA and GNDA are the voltage references for all ADC modules.
0x1
The external VREFA+ and VREFA- inputs are the voltage
references for all ADC modules.
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Texas Instruments-Production Data
Analog-to-Digital Converter (ADC)
Register 14: ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0),
offset 0x040
This register, along with the ADCSSEMUX0 register, defines the analog input configuration for each
sample in a sequence executed with Sample Sequencer 0. If the corresponding EMUXn bit in the
ADCSSEMUX0 register is set, the MUXn field in this register selects from AIN[21:16]. When the
corresponding EMUXn bit is clear, the MUXn field selects from AIN[15:0]. This register is 32 bits
wide and contains information for eight possible samples.
Note:
Channels AIN[31:22] do not exist on this microcontroller. Configuring MUXn to be 0xA-0xF
when the corresponding EMUXn bit is set results in undefined behavior.
ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x040
Type RW, reset 0x0000.0000
31
30
29
28
27
26
RW
0
25
24
23
22
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
15
14
13
12
11
10
9
8
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
MUX7
Type
Reset
20
19
18
RW
0
RW
0
RW
0
RW
0
7
6
5
4
RW
0
RW
0
RW
0
RW
0
MUX6
MUX3
Type
Reset
21
17
16
RW
0
RW
0
RW
0
3
2
1
0
RW
0
RW
0
RW
0
RW
0
MUX5
MUX2
MUX4
MUX1
Bit/Field
Name
Type
Reset
31:28
MUX7
RW
0x0
MUX0
Description
8th Sample Input Select
The MUX7 field is used during the eighth sample of a sequence executed
with the sample sequencer. It specifies which of the analog inputs is
sampled for the analog-to-digital conversion. The value set here indicates
the corresponding pin, for example, a value of 0x1 when EMUX7 is clear
indicates the input is AIN1. A value of 0x1 when EMUX7 is set indicates
the input is AIN17.
If differential sampling is enabled (the D7 bit in the ADCSSCTL0 register
is set), this field must be set to the pair number "i", where the paired
inputs are "2i and 2i+1".
27:24
MUX6
RW
0x0
7th Sample Input Select
The MUX6 field is used during the seventh sample of a sequence
executed with the sample sequencer. It specifies which of the analog
inputs is sampled for the analog-to-digital conversion.
23:20
MUX5
RW
0x0
6th Sample Input Select
The MUX5 field is used during the sixth sample of a sequence executed
with the sample sequencer. It specifies which of the analog inputs is
sampled for the analog-to-digital conversion.
19:16
MUX4
RW
0x0
5th Sample Input Select
The MUX4 field is used during the fifth sample of a sequence executed
with the sample sequencer. It specifies which of the analog inputs is
sampled for the analog-to-digital conversion.
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Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Bit/Field
Name
Type
Reset
15:12
MUX3
RW
0x0
Description
4th Sample Input Select
The MUX3 field is used during the fourth sample of a sequence executed
with the sample sequencer. It specifies which of the analog inputs is
sampled for the analog-to-digital conversion.
11:8
MUX2
RW
0x0
3rd Sample Input Select
The MUX2 field is used during the third sample of a sequence executed
with the sample sequencer. It specifies which of the analog inputs is
sampled for the analog-to-digital conversion.
7:4
MUX1
RW
0x0
2nd Sample Input Select
The MUX1 field is used during the second sample of a sequence
executed with the sample sequencer. It specifies which of the analog
inputs is sampled for the analog-to-digital conversion.
3:0
MUX0
RW
0x0
1st Sample Input Select
The MUX0 field is used during the first sample of a sequence executed
with the sample sequencer. It specifies which of the analog inputs is
sampled for the analog-to-digital conversion.
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839
Texas Instruments-Production Data
Analog-to-Digital Converter (ADC)
Register 15: ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044
This register contains the configuration information for each sample for a sequence executed with
a sample sequencer. When configuring a sample sequence, the END bit must be set for the final
sample, whether it be after the first sample, eighth sample, or any sample in between. This register
is 32 bits wide and contains information for eight possible samples.
ADC Sample Sequence Control 0 (ADCSSCTL0)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x044
Type RW, reset 0x0000.0000
31
Type
Reset
Type
Reset
30
29
28
27
26
25
TS7
IE7
RW
0
RW
0
15
24
23
END7
D7
RW
0
RW
0
14
13
TS3
IE3
RW
0
RW
0
22
21
TS6
IE6
RW
0
RW
0
12
11
END3
D3
RW
0
RW
0
END6
D6
RW
0
RW
0
TS5
IE5
RW
0
RW
0
10
9
8
7
TS2
IE2
RW
0
RW
0
END2
D2
RW
0
RW
0
Bit/Field
Name
Type
Reset
31
TS7
RW
0
20
19
18
17
END5
D5
RW
0
RW
0
6
5
TS1
IE1
RW
0
RW
0
16
TS4
IE4
END4
D4
RW
0
RW
0
RW
0
RW
0
4
3
2
1
0
END1
D1
TS0
IE0
END0
D0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Description
8th Sample Temp Sensor Select
Value Description
30
IE7
RW
0
0
The input pin specified by the ADCSSMUXn register is read
during the eighth sample of the sample sequence.
1
The temperature sensor is read during the eighth sample of the
sample sequence.
8th Sample Interrupt Enable
Value Description
0
The raw interrupt is not asserted to the interrupt controller.
1
The raw interrupt signal (INR0 bit) is asserted at the end of the
eighth sample's conversion. If the MASK0 bit in the ADCIM
register is set, the interrupt is promoted to the interrupt controller.
It is legal to have multiple samples within a sequence generate interrupts.
29
END7
RW
0
8th Sample is End of Sequence
Value Description
0
Another sample in the sequence is the final sample.
1
The eighth sample is the last sample of the sequence.
It is possible to end the sequence on any sample position. Software
must set an ENDn bit somewhere within the sequence. Samples defined
after the sample containing a set ENDn bit are not requested for
conversion even though the fields may be non-zero.
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Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Bit/Field
Name
Type
Reset
28
D7
RW
0
Description
8th Sample Differential Input Select
Value Description
0
The analog inputs are not differentially sampled.
1
The analog input is differentially sampled. The corresponding
ADCSSMUXn nibble must be set to the pair number "i", where
the paired inputs are "2i and 2i+1".
Because the temperature sensor does not have a differential option,
this bit must not be set when the TS7 bit is set.
27
TS6
RW
0
7th Sample Temp Sensor Select
Value Description
26
IE6
RW
0
0
The input pin specified by the ADCSSMUXn register is read
during the seventh sample of the sample sequence.
1
The temperature sensor is read during the seventh sample of
the sample sequence.
7th Sample Interrupt Enable
Value Description
0
The raw interrupt is not asserted to the interrupt controller.
1
The raw interrupt signal (INR0 bit) is asserted at the end of the
seventh sample's conversion. If the MASK0 bit in the ADCIM
register is set, the interrupt is promoted to the interrupt controller.
It is legal to have multiple samples within a sequence generate interrupts.
25
END6
RW
0
7th Sample is End of Sequence
Value Description
0
Another sample in the sequence is the final sample.
1
The seventh sample is the last sample of the sequence.
It is possible to end the sequence on any sample position. Software
must set an ENDn bit somewhere within the sequence. Samples defined
after the sample containing a set ENDn bit are not requested for
conversion even though the fields may be non-zero.
24
D6
RW
0
7th Sample Differential Input Select
Value Description
0
The analog inputs are not differentially sampled.
1
The analog input is differentially sampled. The corresponding
ADCSSMUXn nibble must be set to the pair number "i", where
the paired inputs are "2i and 2i+1".
Because the temperature sensor does not have a differential option,
this bit must not be set when the TS6 bit is set.
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Texas Instruments-Production Data
Analog-to-Digital Converter (ADC)
Bit/Field
Name
Type
Reset
23
TS5
RW
0
Description
6th Sample Temp Sensor Select
Value Description
22
IE5
RW
0
0
The input pin specified by the ADCSSMUXn register is read
during the sixth sample of the sample sequence.
1
The temperature sensor is read during the sixth sample of the
sample sequence.
6th Sample Interrupt Enable
Value Description
0
The raw interrupt is not asserted to the interrupt controller.
1
The raw interrupt signal (INR0 bit) is asserted at the end of the
sixth sample's conversion. If the MASK0 bit in the ADCIM register
is set, the interrupt is promoted to the interrupt controller.
It is legal to have multiple samples within a sequence generate interrupts.
21
END5
RW
0
6th Sample is End of Sequence
Value Description
0
Another sample in the sequence is the final sample.
1
The sixth sample is the last sample of the sequence.
It is possible to end the sequence on any sample position. Software
must set an ENDn bit somewhere within the sequence. Samples defined
after the sample containing a set ENDn bit are not requested for
conversion even though the fields may be non-zero.
20
D5
RW
0
6th Sample Differential Input Select
Value Description
0
The analog inputs are not differentially sampled.
1
The analog input is differentially sampled. The corresponding
ADCSSMUXn nibble must be set to the pair number "i", where
the paired inputs are "2i and 2i+1".
Because the temperature sensor does not have a differential option,
this bit must not be set when the TS5 bit is set.
19
TS4
RW
0
5th Sample Temp Sensor Select
Value Description
0
The input pin specified by the ADCSSMUXn register is read
during the fifth sample of the sample sequence.
1
The temperature sensor is read during the fifth sample of the
sample sequence.
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Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Bit/Field
Name
Type
Reset
18
IE4
RW
0
Description
5th Sample Interrupt Enable
Value Description
0
The raw interrupt is not asserted to the interrupt controller.
1
The raw interrupt signal (INR0 bit) is asserted at the end of the
fifth sample's conversion. If the MASK0 bit in the ADCIM register
is set, the interrupt is promoted to the interrupt controller.
It is legal to have multiple samples within a sequence generate interrupts.
17
END4
RW
0
5th Sample is End of Sequence
Value Description
0
Another sample in the sequence is the final sample.
1
The fifth sample is the last sample of the sequence.
It is possible to end the sequence on any sample position. Software
must set an ENDn bit somewhere within the sequence. Samples defined
after the sample containing a set ENDn bit are not requested for
conversion even though the fields may be non-zero.
16
D4
RW
0
5th Sample Differential Input Select
Value Description
0
The analog inputs are not differentially sampled.
1
The analog input is differentially sampled. The corresponding
ADCSSMUXn nibble must be set to the pair number "i", where
the paired inputs are "2i and 2i+1".
Because the temperature sensor does not have a differential option,
this bit must not be set when the TS4 bit is set.
15
TS3
RW
0
4th Sample Temp Sensor Select
Value Description
14
IE3
RW
0
0
The input pin specified by the ADCSSMUXn register is read
during the fourth sample of the sample sequence.
1
The temperature sensor is read during the fourth sample of the
sample sequence.
4th Sample Interrupt Enable
Value Description
0
The raw interrupt is not asserted to the interrupt controller.
1
The raw interrupt signal (INR0 bit) is asserted at the end of the
fourth sample's conversion. If the MASK0 bit in the ADCIM
register is set, the interrupt is promoted to the interrupt controller.
It is legal to have multiple samples within a sequence generate interrupts.
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843
Texas Instruments-Production Data
Analog-to-Digital Converter (ADC)
Bit/Field
Name
Type
Reset
13
END3
RW
0
Description
4th Sample is End of Sequence
Value Description
0
Another sample in the sequence is the final sample.
1
The fourth sample is the last sample of the sequence.
It is possible to end the sequence on any sample position. Software
must set an ENDn bit somewhere within the sequence. Samples defined
after the sample containing a set ENDn bit are not requested for
conversion even though the fields may be non-zero.
12
D3
RW
0
4th Sample Differential Input Select
Value Description
0
The analog inputs are not differentially sampled.
1
The analog input is differentially sampled. The corresponding
ADCSSMUXn nibble must be set to the pair number "i", where
the paired inputs are "2i and 2i+1".
Because the temperature sensor does not have a differential option,
this bit must not be set when the TS3 bit is set.
11
TS2
RW
0
3rd Sample Temp Sensor Select
Value Description
10
IE2
RW
0
0
The input pin specified by the ADCSSMUXn register is read
during the third sample of the sample sequence.
1
The temperature sensor is read during the third sample of the
sample sequence.
3rd Sample Interrupt Enable
Value Description
0
The raw interrupt is not asserted to the interrupt controller.
1
The raw interrupt signal (INR0 bit) is asserted at the end of the
third sample's conversion. If the MASK0 bit in the ADCIM register
is set, the interrupt is promoted to the interrupt controller.
It is legal to have multiple samples within a sequence generate interrupts.
9
END2
RW
0
3rd Sample is End of Sequence
Value Description
0
Another sample in the sequence is the final sample.
1
The third sample is the last sample of the sequence.
It is possible to end the sequence on any sample position. Software
must set an ENDn bit somewhere within the sequence. Samples defined
after the sample containing a set ENDn bit are not requested for
conversion even though the fields may be non-zero.
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Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Bit/Field
Name
Type
Reset
8
D2
RW
0
Description
3rd Sample Differential Input Select
Value Description
0
The analog inputs are not differentially sampled.
1
The analog input is differentially sampled. The corresponding
ADCSSMUXn nibble must be set to the pair number "i", where
the paired inputs are "2i and 2i+1".
Because the temperature sensor does not have a differential option,
this bit must not be set when the TS2 bit is set.
7
TS1
RW
0
2nd Sample Temp Sensor Select
Value Description
6
IE1
RW
0
0
The input pin specified by the ADCSSMUXn register is read
during the second sample of the sample sequence.
1
The temperature sensor is read during the second sample of
the sample sequence.
2nd Sample Interrupt Enable
Value Description
0
The raw interrupt is not asserted to the interrupt controller.
1
The raw interrupt signal (INR0 bit) is asserted at the end of the
second sample's conversion. If the MASK0 bit in the ADCIM
register is set, the interrupt is promoted to the interrupt controller.
It is legal to have multiple samples within a sequence generate interrupts.
5
END1
RW
0
2nd Sample is End of Sequence
Value Description
0
Another sample in the sequence is the final sample.
1
The second sample is the last sample of the sequence.
It is possible to end the sequence on any sample position. Software
must set an ENDn bit somewhere within the sequence. Samples defined
after the sample containing a set ENDn bit are not requested for
conversion even though the fields may be non-zero.
4
D1
RW
0
2nd Sample Differential Input Select
Value Description
0
The analog inputs are not differentially sampled.
1
The analog input is differentially sampled. The corresponding
ADCSSMUXn nibble must be set to the pair number "i", where
the paired inputs are "2i and 2i+1".
Because the temperature sensor does not have a differential option,
this bit must not be set when the TS1 bit is set.
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Texas Instruments-Production Data
Analog-to-Digital Converter (ADC)
Bit/Field
Name
Type
Reset
3
TS0
RW
0
Description
1st Sample Temp Sensor Select
Value Description
2
IE0
RW
0
0
The input pin specified by the ADCSSMUXn register is read
during the first sample of the sample sequence.
1
The temperature sensor is read during the first sample of the
sample sequence.
1st Sample Interrupt Enable
Value Description
0
The raw interrupt is not asserted to the interrupt controller.
1
The raw interrupt signal (INR0 bit) is asserted at the end of the
first sample's conversion. If the MASK0 bit in the ADCIM register
is set, the interrupt is promoted to the interrupt controller.
It is legal to have multiple samples within a sequence generate interrupts.
1
END0
RW
0
1st Sample is End of Sequence
Value Description
0
Another sample in the sequence is the final sample.
1
The first sample is the last sample of the sequence.
It is possible to end the sequence on any sample position. Software
must set an ENDn bit somewhere within the sequence. Samples defined
after the sample containing a set ENDn bit are not requested for
conversion even though the fields may be non-zero.
0
D0
RW
0
1st Sample Differential Input Select
Value Description
0
The analog inputs are not differentially sampled.
1
The analog input is differentially sampled. The corresponding
ADCSSMUXn nibble must be set to the pair number "i", where
the paired inputs are "2i and 2i+1".
Because the temperature sensor does not have a differential option,
this bit must not be set when the TS0 bit is set.
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Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Register 16: ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048
Register 17: ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068
Register 18: ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088
Register 19: ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset
0x0A8
Important: This register is read-sensitive. See the register description for details.
This register contains the conversion results for samples collected with the sample sequencer (the
ADCSSFIFO0 register is used for Sample Sequencer 0, ADCSSFIFO1 for Sequencer 1,
ADCSSFIFO2 for Sequencer 2, and ADCSSFIFO3 for Sequencer 3). Reads of this register return
conversion result data in the order sample 0, sample 1, and so on, until the FIFO is empty. If the
FIFO is not properly handled by software, overflow and underflow conditions are registered in the
ADCOSTAT and ADCUSTAT registers.
ADC Sample Sequence Result FIFO n (ADCSSFIFOn)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x048
Type RO, reset 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
5
4
3
2
1
0
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
reserved
Type
Reset
RO
0
RO
0
DATA
RO
0
RO
0
RO
-
RO
-
RO
-
Bit/Field
Name
Type
Reset
31:12
reserved
RO
0x0000.0
11:0
DATA
RO
-
RO
-
RO
-
RO
-
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Conversion Result Data
June 12, 2014
847
Texas Instruments-Production Data
Analog-to-Digital Converter (ADC)
Register 20: ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset
0x04C
Register 21: ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset
0x06C
Register 22: ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset
0x08C
Register 23: ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset
0x0AC
This register provides a window into the sample sequencer, providing full/empty status information
as well as the positions of the head and tail pointers. The reset value of 0x100 indicates an empty
FIFO with the head and tail pointers both pointing to index 0. The ADCSSFSTAT0 register provides
status on FIFO0, which has 8 entries; ADCSSFSTAT1 on FIFO1, which has 4 entries;
ADCSSFSTAT2 on FIFO2, which has 4 entries; and ADCSSFSTAT3 on FIFO3 which has a single
entry.
ADC Sample Sequence FIFO n Status (ADCSSFSTATn)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x04C
Type RO, reset 0x0000.0100
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
RO
0
FULL
RO
0
RO
0
reserved
RO
0
RO
0
EMPTY
RO
0
Bit/Field
Name
Type
Reset
31:13
reserved
RO
0x0000.0
12
FULL
RO
0
RO
1
HPTR
TPTR
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
FIFO Full
Value Description
11:9
reserved
RO
0x0
8
EMPTY
RO
1
0
The FIFO is not currently full.
1
The FIFO is currently full.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
FIFO Empty
Value Description
0
The FIFO is not currently empty.
1
The FIFO is currently empty.
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Tiva™ TM4C1237H6PZ Microcontroller
Bit/Field
Name
Type
Reset
7:4
HPTR
RO
0x0
Description
FIFO Head Pointer
This field contains the current "head" pointer index for the FIFO, that is,
the next entry to be written.
Valid values are 0x0-0x7 for FIFO0; 0x0-0x3 for FIFO1 and FIFO2; and
0x0 for FIFO3.
3:0
TPTR
RO
0x0
FIFO Tail Pointer
This field contains the current "tail" pointer index for the FIFO, that is,
the next entry to be read.
Valid values are 0x0-0x7 for FIFO0; 0x0-0x3 for FIFO1 and FIFO2; and
0x0 for FIFO3.
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Analog-to-Digital Converter (ADC)
Register 24: ADC Sample Sequence 0 Operation (ADCSSOP0), offset 0x050
This register determines whether the sample from the given conversion on Sample Sequence 0 is
saved in the Sample Sequence FIFO0 or sent to the digital comparator unit.
ADC Sample Sequence 0 Operation (ADCSSOP0)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x050
Type RW, reset 0x0000.0000
31
30
29
reserved
Type
Reset
27
S7DCOP
26
25
reserved
24
23
S6DCOP
22
21
reserved
20
19
S5DCOP
18
17
reserved
16
S4DCOP
RO
0
RO
0
RO
0
RW
0
RO
0
RO
0
RO
0
RW
0
RO
0
RO
0
RO
0
RW
0
RO
0
RO
0
RO
0
RW
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
Type
Reset
28
RO
0
RO
0
S3DCOP
RO
0
RW
0
reserved
RO
0
RO
0
S2DCOP
RO
0
Bit/Field
Name
Type
Reset
31:29
reserved
RO
0x0
28
S7DCOP
RW
0
RW
0
reserved
RO
0
RO
0
S1DCOP
RO
0
RW
0
reserved
RO
0
RO
0
S0DCOP
RO
0
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Sample 7 Digital Comparator Operation
Value Description
27:25
reserved
RO
0x0
24
S6DCOP
RW
0
0
The eighth sample is saved in Sample Sequence FIFO0.
1
The eighth sample is sent to the digital comparator unit specified
by the S7DCSEL bit in the ADCSSDC0 register, and the value
is not written to the FIFO.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Sample 6 Digital Comparator Operation
Same definition as S7DCOP but used during the seventh sample.
23:21
reserved
RO
0x0
20
S5DCOP
RW
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Sample 5 Digital Comparator Operation
Same definition as S7DCOP but used during the sixth sample.
19:17
reserved
RO
0x0
16
S4DCOP
RW
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Sample 4 Digital Comparator Operation
Same definition as S7DCOP but used during the fifth sample.
15:13
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Tiva™ TM4C1237H6PZ Microcontroller
Bit/Field
Name
Type
Reset
12
S3DCOP
RW
0
Description
Sample 3 Digital Comparator Operation
Same definition as S7DCOP but used during the fourth sample.
11:9
reserved
RO
0x0
8
S2DCOP
RW
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Sample 2 Digital Comparator Operation
Same definition as S7DCOP but used during the third sample.
7:5
reserved
RO
0x0
4
S1DCOP
RW
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Sample 1 Digital Comparator Operation
Same definition as S7DCOP but used during the second sample.
3:1
reserved
RO
0x0
0
S0DCOP
RW
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Sample 0 Digital Comparator Operation
Same definition as S7DCOP but used during the first sample.
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Analog-to-Digital Converter (ADC)
Register 25: ADC Sample Sequence 0 Digital Comparator Select (ADCSSDC0),
offset 0x054
This register determines which digital comparator receives the sample from the given conversion
on Sample Sequence 0, if the corresponding SnDCOP bit in the ADCSSOP0 register is set.
ADC Sample Sequence 0 Digital Comparator Select (ADCSSDC0)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x054
Type RW, reset 0x0000.0000
31
30
29
28
27
26
S7DCSEL
Type
Reset
24
23
22
21
20
19
S5DCSEL
18
17
16
S4DCSEL
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
S3DCSEL
Type
Reset
25
S6DCSEL
RW
0
RW
0
S2DCSEL
RW
0
RW
0
RW
0
RW
0
RW
0
Bit/Field
Name
Type
Reset
31:28
S7DCSEL
RW
0x0
S1DCSEL
RW
0
RW
0
RW
0
RW
0
S0DCSEL
RW
0
RW
0
RW
0
RW
0
RW
0
Description
Sample 7 Digital Comparator Select
When the S7DCOP bit in the ADCSSOP0 register is set, this field
indicates which digital comparator unit (and its associated set of control
registers) receives the eighth sample from Sample Sequencer 0.
Note:
Values not listed are reserved.
Value Description
27:24
S6DCSEL
RW
0x0
0x0
Digital Comparator Unit 0 (ADCDCCMP0 and ADCDCCTL0)
0x1
Digital Comparator Unit 1 (ADCDCCMP1 and ADCDCCTL1)
0x2
Digital Comparator Unit 2 (ADCDCCMP2 and ADCDCCTL2)
0x3
Digital Comparator Unit 3 (ADCDCCMP3 and ADCDCCTL3)
0x4
Digital Comparator Unit 4 (ADCDCCMP4 and ADCDCCTL4)
0x5
Digital Comparator Unit 5 (ADCDCCMP5 and ADCDCCTL5)
0x6
Digital Comparator Unit 6 (ADCDCCMP6 and ADCDCCTL6)
0x7
Digital Comparator Unit 7 (ADCDCCMP7 and ADCDCCTL7)
Sample 6 Digital Comparator Select
This field has the same encodings as S7DCSEL but is used during the
seventh sample.
23:20
S5DCSEL
RW
0x0
Sample 5 Digital Comparator Select
This field has the same encodings as S7DCSEL but is used during the
sixth sample.
19:16
S4DCSEL
RW
0x0
Sample 4 Digital Comparator Select
This field has the same encodings as S7DCSEL but is used during the
fifth sample.
15:12
S3DCSEL
RW
0x0
Sample 3 Digital Comparator Select
This field has the same encodings as S7DCSEL but is used during the
fourth sample.
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Bit/Field
Name
Type
Reset
11:8
S2DCSEL
RW
0x0
Description
Sample 2 Digital Comparator Select
This field has the same encodings as S7DCSEL but is used during the
third sample.
7:4
S1DCSEL
RW
0x0
Sample 1 Digital Comparator Select
This field has the same encodings as S7DCSEL but is used during the
second sample.
3:0
S0DCSEL
RW
0x0
Sample 0 Digital Comparator Select
This field has the same encodings as S7DCSEL but is used during the
first sample.
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Analog-to-Digital Converter (ADC)
Register 26: ADC Sample Sequence Extended Input Multiplexer Select 0
(ADCSSEMUX0), offset 0x058
This register, along with the ADCSSMUX0 register, defines the analog input configuration for each
sample in a sequence executed with Sample Sequencer 0. If a bit in this register is set, the
corresponding MUXn field in the ADCSSMUX0 register selects from AIN[21:16]. When a bit in
this register is clear, the corresponding MUXn field selects from AIN[15:0]. This register is 32 bits
wide and contains information for eight possible samples.
Note that this register is not used when the differential channel designation is used (the Dn bit is set
in the ADCSSCTL0 register) because the ADCSSMUX0 register can select all the available pairs.
ADC Sample Sequence Extended Input Multiplexer Select 0 (ADCSSEMUX0)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x058
Type RW, reset 0x0000.0000
31
30
29
reserved
Type
Reset
27
EMUX7
26
25
reserved
24
23
EMUX6
22
21
reserved
20
19
EMUX5
18
17
reserved
16
EMUX4
RO
0
RO
0
RO
0
RW
0
RO
0
RO
0
RO
0
RW
0
RO
0
RO
0
RO
0
RW
0
RO
0
RO
0
RO
0
RW
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
Type
Reset
28
RO
0
RO
0
EMUX3
RO
0
RW
0
reserved
RO
0
RO
0
EMUX2
RO
0
RW
0
reserved
RO
0
RO
0
EMUX1
RO
0
RW
0
reserved
RO
0
RO
0
EMUX0
RO
0
RW
0
Bit/Field
Name
Type
Reset
Description
31:29
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
28
EMUX7
RW
0x0
8th Sample Input Select (Upper Bit)
The EMUX7 field is used during the eighth sample of a sequence
executed with the sample sequencer.
Value Description
0
The eighth sample input is selected from AIN[15:0] using the
ADCSSMUX0 register. For example, if the MUX7 field is 0x0,
AIN0 is selected.
1
The eighth sample input is selected from AIN[21:16] using
the ADCSSMUX0 register. For example, if the MUX7 field is 0x0,
AIN16 is selected.
27:25
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
24
EMUX6
RW
0x0
7th Sample Input Select (Upper Bit)
The EMUX6 field is used during the seventh sample of a sequence
executed with the sample sequencer. This bit has the same description
as EMUX7.
23:21
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Tiva™ TM4C1237H6PZ Microcontroller
Bit/Field
Name
Type
Reset
20
EMUX5
RW
0x0
Description
6th Sample Input Select (Upper Bit)
The EMUX5 field is used during the sixth sample of a sequence executed
with the sample sequencer. This bit has the same description as EMUX7.
19:17
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
16
EMUX4
RW
0x0
5th Sample Input Select (Upper Bit)
The EMUX4 field is used during the fifth sample of a sequence executed
with the sample sequencer. This bit has the same description as EMUX7.
15:13
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
12
EMUX3
RW
0x0
4th Sample Input Select (Upper Bit)
The EMUX3 field is used during the fourth sample of a sequence executed
with the sample sequencer. This bit has the same description as EMUX7.
11:9
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
8
EMUX2
RW
0x0
3rd Sample Input Select (Upper Bit)
The EMUX2 field is used during the third sample of a sequence executed
with the sample sequencer. This bit has the same description as EMUX7.
7:5
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
4
EMUX1
RW
0x0
2th Sample Input Select (Upper Bit)
The EMUX1 field is used during the second sample of a sequence
executed with the sample sequencer. This bit has the same description
as EMUX7.
3:1
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
EMUX0
RW
0x0
1st Sample Input Select (Upper Bit)
The EMUX0 field is used during the first sample of a sequence executed
with the sample sequencer. This bit has the same description as EMUX7.
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Analog-to-Digital Converter (ADC)
Register 27: ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1),
offset 0x060
Register 28: ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2),
offset 0x080
This register, along with the ADCSSEMUX1 or ADCSSEMUX2 register, defines the analog input
configuration for each sample in a sequence executed with Sample Sequencer 1 or 2. If the
corresponding EMUXn bit in the ADCSSEMUX1 or ADCSSEMUX2 register is set, the MUXn field in
this register selects from AIN[21:16]. When the corresponding EMUXn bit is clear, the MUXn field
selects from AIN[15:0]. These registers are 16 bits wide and contain information for four possible
samples. See the ADCSSMUX0 register on page 838 for detailed bit descriptions. The ADCSSMUX1
register affects Sample Sequencer 1 and the ADCSSMUX2 register affects Sample Sequencer 2.
Note:
Channels AIN[31:22] do not exist on this microcontroller. Configuring MUXn to be 0xA-0xF
when the corresponding EMUXn bit is set results in undefined behavior.
ADC Sample Sequence Input Multiplexer Select n (ADCSSMUXn)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x060
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
5
4
3
2
1
0
RW
0
RW
0
reserved
Type
Reset
RO
0
RO
0
15
14
RO
0
RO
0
RO
0
RO
0
13
12
11
10
MUX3
Type
Reset
RW
0
RW
0
RO
0
RO
0
RO
0
RO
0
9
8
7
6
MUX2
RW
0
RW
0
RW
0
RW
0
MUX1
RW
0
RW
0
RW
0
RW
0
MUX0
RW
0
Bit/Field
Name
Type
Reset
31:16
reserved
RO
0x0000
15:12
MUX3
RW
0x0
4th Sample Input Select
11:8
MUX2
RW
0x0
3rd Sample Input Select
7:4
MUX1
RW
0x0
2nd Sample Input Select
3:0
MUX0
RW
0x0
1st Sample Input Select
RW
0
RW
0
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Tiva™ TM4C1237H6PZ Microcontroller
Register 29: ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064
Register 30: ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084
These registers contain the configuration information for each sample for a sequence executed with
Sample Sequencer 1 or 2. When configuring a sample sequence, the END bit must be set for the
final sample, whether it be after the first sample, fourth sample, or any sample in between. These
registers are 16-bits wide and contain information for four possible samples. See the ADCSSCTL0
register on page 840 for detailed bit descriptions. The ADCSSCTL1 register configures Sample
Sequencer 1 and the ADCSSCTL2 register configures Sample Sequencer 2.
ADC Sample Sequence Control n (ADCSSCTLn)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x064
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
TS3
IE3
END3
D3
TS2
IE2
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
END2
D2
TS1
IE1
END1
D1
TS0
IE0
END0
D0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
Type
Reset
Bit/Field
Name
Type
Reset
31:16
reserved
RO
0x0000
15
TS3
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
4th Sample Temp Sensor Select
Value Description
14
IE3
RW
0
0
The input pin specified by the ADCSSMUXn register is read
during the fourth sample of the sample sequence.
1
The temperature sensor is read during the fourth sample of the
sample sequence.
4th Sample Interrupt Enable
Value Description
0
The raw interrupt is not asserted to the interrupt controller.
1
The raw interrupt signal (INR0 bit) is asserted at the end of the
fourth sample's conversion. If the MASK0 bit in the ADCIM
register is set, the interrupt is promoted to the interrupt controller.
It is legal to have multiple samples within a sequence generate interrupts.
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Analog-to-Digital Converter (ADC)
Bit/Field
Name
Type
Reset
13
END3
RW
0
Description
4th Sample is End of Sequence
Value Description
0
Another sample in the sequence is the final sample.
1
The fourth sample is the last sample of the sequence.
It is possible to end the sequence on any sample position. Software
must set an ENDn bit somewhere within the sequence. Samples defined
after the sample containing a set ENDn bit are not requested for
conversion even though the fields may be non-zero.
12
D3
RW
0
4th Sample Differential Input Select
Value Description
0
The analog inputs are not differentially sampled.
1
The analog input is differentially sampled. The corresponding
ADCSSMUXn nibble must be set to the pair number "i", where
the paired inputs are "2i and 2i+1".
Because the temperature sensor does not have a differential option,
this bit must not be set when the TS3 bit is set.
11
TS2
RW
0
3rd Sample Temp Sensor Select
Value Description
10
IE2
RW
0
0
The input pin specified by the ADCSSMUXn register is read
during the third sample of the sample sequence.
1
The temperature sensor is read during the third sample of the
sample sequence.
3rd Sample Interrupt Enable
Value Description
0
The raw interrupt is not asserted to the interrupt controller.
1
The raw interrupt signal (INR0 bit) is asserted at the end of the
third sample's conversion. If the MASK0 bit in the ADCIM register
is set, the interrupt is promoted to the interrupt controller.
It is legal to have multiple samples within a sequence generate interrupts.
9
END2
RW
0
3rd Sample is End of Sequence
Value Description
0
Another sample in the sequence is the final sample.
1
The third sample is the last sample of the sequence.
It is possible to end the sequence on any sample position. Software
must set an ENDn bit somewhere within the sequence. Samples defined
after the sample containing a set ENDn bit are not requested for
conversion even though the fields may be non-zero.
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Bit/Field
Name
Type
Reset
8
D2
RW
0
Description
3rd Sample Differential Input Select
Value Description
0
The analog inputs are not differentially sampled.
1
The analog input is differentially sampled. The corresponding
ADCSSMUXn nibble must be set to the pair number "i", where
the paired inputs are "2i and 2i+1".
Because the temperature sensor does not have a differential option,
this bit must not be set when the TS2 bit is set.
7
TS1
RW
0
2nd Sample Temp Sensor Select
Value Description
6
IE1
RW
0
0
The input pin specified by the ADCSSMUXn register is read
during the second sample of the sample sequence.
1
The temperature sensor is read during the second sample of
the sample sequence.
2nd Sample Interrupt Enable
Value Description
0
The raw interrupt is not asserted to the interrupt controller.
1
The raw interrupt signal (INR0 bit) is asserted at the end of the
second sample's conversion. If the MASK0 bit in the ADCIM
register is set, the interrupt is promoted to the interrupt controller.
It is legal to have multiple samples within a sequence generate interrupts.
5
END1
RW
0
2nd Sample is End of Sequence
Value Description
0
Another sample in the sequence is the final sample.
1
The second sample is the last sample of the sequence.
It is possible to end the sequence on any sample position. Software
must set an ENDn bit somewhere within the sequence. Samples defined
after the sample containing a set ENDn bit are not requested for
conversion even though the fields may be non-zero.
4
D1
RW
0
2nd Sample Differential Input Select
Value Description
0
The analog inputs are not differentially sampled.
1
The analog input is differentially sampled. The corresponding
ADCSSMUXn nibble must be set to the pair number "i", where
the paired inputs are "2i and 2i+1".
Because the temperature sensor does not have a differential option,
this bit must not be set when the TS1 bit is set.
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Analog-to-Digital Converter (ADC)
Bit/Field
Name
Type
Reset
3
TS0
RW
0
Description
1st Sample Temp Sensor Select
Value Description
2
IE0
RW
0
0
The input pin specified by the ADCSSMUXn register is read
during the first sample of the sample sequence.
1
The temperature sensor is read during the first sample of the
sample sequence.
1st Sample Interrupt Enable
Value Description
0
The raw interrupt is not asserted to the interrupt controller.
1
The raw interrupt signal (INR0 bit) is asserted at the end of the
first sample's conversion. If the MASK0 bit in the ADCIM register
is set, the interrupt is promoted to the interrupt controller.
It is legal to have multiple samples within a sequence generate interrupts.
1
END0
RW
0
1st Sample is End of Sequence
Value Description
0
Another sample in the sequence is the final sample.
1
The first sample is the last sample of the sequence.
It is possible to end the sequence on any sample position. Software
must set an ENDn bit somewhere within the sequence. Samples defined
after the sample containing a set ENDn bit are not requested for
conversion even though the fields may be non-zero.
0
D0
RW
0
1st Sample Differential Input Select
Value Description
0
The analog inputs are not differentially sampled.
1
The analog input is differentially sampled. The corresponding
ADCSSMUXn nibble must be set to the pair number "i", where
the paired inputs are "2i and 2i+1".
Because the temperature sensor does not have a differential option,
this bit must not be set when the TS0 bit is set.
860
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Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Register 31: ADC Sample Sequence 1 Operation (ADCSSOP1), offset 0x070
Register 32: ADC Sample Sequence 2 Operation (ADCSSOP2), offset 0x090
This register determines whether the sample from the given conversion on Sample Sequence n is
saved in the Sample Sequence n FIFO or sent to the digital comparator unit. The ADCSSOP1
register controls Sample Sequencer 1 and the ADCSSOP2 register controls Sample Sequencer 2.
ADC Sample Sequence n Operation (ADCSSOPn)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x070
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
RO
0
S3DCOP
RO
0
RW
0
reserved
RO
0
RO
0
S2DCOP
RO
0
Bit/Field
Name
Type
Reset
31:13
reserved
RO
0x0000.0
12
S3DCOP
RW
0
RW
0
reserved
RO
0
RO
0
S1DCOP
RO
0
RW
0
reserved
RO
0
RO
0
S0DCOP
RO
0
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Sample 3 Digital Comparator Operation
Value Description
11:9
reserved
RO
0x0
8
S2DCOP
RW
0
0
The fourth sample is saved in Sample Sequence FIFOn.
1
The fourth sample is sent to the digital comparator unit specified
by the S3DCSEL bit in the ADCSSDC0n register, and the value
is not written to the FIFO.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Sample 2 Digital Comparator Operation
Same definition as S3DCOP but used during the third sample.
7:5
reserved
RO
0x0
4
S1DCOP
RW
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Sample 1 Digital Comparator Operation
Same definition as S3DCOP but used during the second sample.
3:1
reserved
RO
0x0
0
S0DCOP
RW
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Sample 0 Digital Comparator Operation
Same definition as S3DCOP but used during the first sample.
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Texas Instruments-Production Data
Analog-to-Digital Converter (ADC)
Register 33: ADC Sample Sequence 1 Digital Comparator Select (ADCSSDC1),
offset 0x074
Register 34: ADC Sample Sequence 2 Digital Comparator Select (ADCSSDC2),
offset 0x094
These registers determine which digital comparator receives the sample from the given conversion
on Sample Sequence n if the corresponding SnDCOP bit in the ADCSSOPn register is set. The
ADCSSDC1 register controls the selection for Sample Sequencer 1 and the ADCSSDC2 register
controls the selection for Sample Sequencer 2.
ADC Sample Sequence n Digital Comparator Select (ADCSSDCn)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x074
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RW
0
RW
0
RW
0
RW
0
RW
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
S3DCSEL
Type
Reset
S2DCSEL
RW
0
RW
0
Bit/Field
Name
Type
Reset
31:16
reserved
RO
0x0000
15:12
S3DCSEL
RW
0x0
S1DCSEL
RW
0
S0DCSEL
RW
0
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Sample 3 Digital Comparator Select
When the S3DCOP bit in the ADCSSOPn register is set, this field
indicates which digital comparator unit (and its associated set of control
registers) receives the eighth sample from Sample Sequencer n.
Note:
Values not listed are reserved.
Value Description
11:8
S2DCSEL
RW
0x0
0x0
Digital Comparator Unit 0 (ADCDCCMP0 and ADCCCTL0)
0x1
Digital Comparator Unit 1 (ADCDCCMP1 and ADCCCTL1)
0x2
Digital Comparator Unit 2 (ADCDCCMP2 and ADCCCTL2)
0x3
Digital Comparator Unit 3 (ADCDCCMP3 and ADCCCTL3)
0x4
Digital Comparator Unit 4 (ADCDCCMP4 and ADCCCTL4)
0x5
Digital Comparator Unit 5 (ADCDCCMP5 and ADCCCTL5)
0x6
Digital Comparator Unit 6 (ADCDCCMP6 and ADCCCTL6)
0x7
Digital Comparator Unit 7 (ADCDCCMP7 and ADCCCTL7)
Sample 2 Digital Comparator Select
This field has the same encodings as S3DCSEL but is used during the
third sample.
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Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Bit/Field
Name
Type
Reset
7:4
S1DCSEL
RW
0x0
Description
Sample 1 Digital Comparator Select
This field has the same encodings as S3DCSEL but is used during the
second sample.
3:0
S0DCSEL
RW
0x0
Sample 0 Digital Comparator Select
This field has the same encodings as S3DCSEL but is used during the
first sample.
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863
Texas Instruments-Production Data
Analog-to-Digital Converter (ADC)
Register 35: ADC Sample Sequence Extended Input Multiplexer Select 1
(ADCSSEMUX1), offset 0x078
Register 36: ADC Sample Sequence Extended Input Multiplexer Select 2
(ADCSSEMUX2), offset 0x098
This register, along with the ADCSSMUX1 or ADCSSMUX2 register, defines the analog input
configuration for each sample in a sequence executed with either Sample Sequencer 1 or 2. If a bit
in this register is set, the corresponding MUXn field in the ADCSSMUX1 or ADCSSMUX2 register
selects from AIN[21:16]. When a bit in this register is clear, the corresponding MUXn field selects
from AIN[15:0]. This register is 16 bits wide and contains information for four possible samples.
The ADCSSEMUX1 register controls Sample Sequencer 1 and the ADCSSEMUX2 register controls
Sample Sequencer 2.
Note that this register is not used when the differential channel designation is used (the Dn bit is set
in the ADCSSCTL1 or ADCSSCTL2 register) because the ADCSSMUX1 or ADCSSMUX2 register
can select all the available pairs.
ADC Sample Sequence Extended Input Multiplexer Select n (ADCSSEMUXn)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x078
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
6
5
4
3
2
1
reserved
Type
Reset
RO
0
15
RO
0
RO
0
14
13
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
12
11
EMUX3
RO
0
RW
0
RO
0
RO
0
10
9
reserved
RO
0
RO
0
RO
0
RO
0
8
7
EMUX2
RO
0
Bit/Field
Name
Type
Reset
31:13
reserved
RO
0x0000
12
EMUX3
RW
0x0
RW
0
reserved
RO
0
RO
0
EMUX1
RO
0
RW
0
reserved
RO
0
RO
0
0
EMUX0
RO
0
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
4th Sample Input Select (Upper Bit)
The EMUX3 field is used during the fourth sample of a sequence executed
with the sample sequencer.
Value Description
11:9
reserved
RO
0x0
0
The fourth sample input is selected from AIN[15:0] using the
ADCSSMUX1 or ADCSSMUX2 register. For example, if the
MUX3 field is 0x0, AIN0 is selected.
1
The fourth sample input is selected from AIN[21:16] using
the ADCSSMUX1 or ADCSSMUX2 register. For example, if the
MUX3 field is 0x0, AIN16 is selected.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Bit/Field
Name
Type
Reset
8
EMUX2
RW
0x0
Description
3rd Sample Input Select (Upper Bit)
The EMUX2 field is used during the third sample of a sequence executed
with the sample sequencer. This bit has the same description as EMUX3.
7:5
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
4
EMUX1
RW
0x0
2th Sample Input Select (Upper Bit)
The EMUX1 field is used during the second sample of a sequence
executed with the sample sequencer. This bit has the same description
as EMUX3.
3:1
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
EMUX0
RW
0x0
1st Sample Input Select (Upper Bit)
The EMUX0 field is used during the first sample of a sequence executed
with the sample sequencer. This bit has the same description as EMUX3.
June 12, 2014
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Texas Instruments-Production Data
Analog-to-Digital Converter (ADC)
Register 37: ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3),
offset 0x0A0
This register, along with the ADCSSEMUX3 register, defines the analog input configuration for the
sample in a sequence executed with Sample Sequencer 3. If the EMUX0 bit in the ADCSSEMUX3
register is set, the MUX0 field in this register selects from AIN[21:16]. When the EMUX0 bit is clear,
the MUX0 field selects from AIN[15:0]. This register is four bits wide and contains information for
one possible sample. See the ADCSSMUX0 register on page 838 for detailed bit descriptions.
ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x0A0
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
1
0
RW
0
RW
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
MUX0
RO
0
Bit/Field
Name
Type
Reset
31:4
reserved
RO
0x0000.000
3:0
MUX0
RW
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1st Sample Input Select
866
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Register 38: ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4
This register contains the configuration information for a sample executed with Sample Sequencer
3. This register is 4 bits wide and contains information for one possible sample. See the ADCSSCTL0
register on page 840 for detailed bit descriptions.
Note:
When configuring a sample sequence in this register, the END0 bit must be set.
ADC Sample Sequence Control 3 (ADCSSCTL3)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x0A4
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:4
reserved
RO
0x0000.000
3
TS0
RW
0
RO
0
RO
0
RO
0
RO
0
RO
0
3
2
1
0
TS0
IE0
END0
D0
RW
0
RW
0
RW
0
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1st Sample Temp Sensor Select
Value Description
2
IE0
RW
0
0
The input pin specified by the ADCSSMUXn register is read
during the first sample of the sample sequence.
1
The temperature sensor is read during the first sample of the
sample sequence.
Sample Interrupt Enable
Value Description
0
The raw interrupt is not asserted to the interrupt controller.
1
The raw interrupt signal (INR0 bit) is asserted at the end of this
sample's conversion. If the MASK0 bit in the ADCIM register is
set, the interrupt is promoted to the interrupt controller.
It is legal to have multiple samples within a sequence generate interrupts.
1
END0
RW
0
End of Sequence
This bit must be set before initiating a single sample sequence.
Value Description
0
Sampling and conversion continues.
1
This is the end of sequence.
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Texas Instruments-Production Data
Analog-to-Digital Converter (ADC)
Bit/Field
Name
Type
Reset
0
D0
RW
0
Description
Sample Differential Input Select
Value Description
0
The analog inputs are not differentially sampled.
1
The analog input is differentially sampled. The corresponding
ADCSSMUXn nibble must be set to the pair number "i", where
the paired inputs are "2i and 2i+1".
Because the temperature sensor does not have a differential option,
this bit must not be set when the TS0 bit is set.
868
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Register 39: ADC Sample Sequence 3 Operation (ADCSSOP3), offset 0x0B0
This register determines whether the sample from the given conversion on Sample Sequence 3 is
saved in the Sample Sequence 3 FIFO or sent to the digital comparator unit.
ADC Sample Sequence 3 Operation (ADCSSOP3)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x0B0
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:1
reserved
RO
0x0000.000
0
S0DCOP
RW
0
RO
0
S0DCOP
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Sample 0 Digital Comparator Operation
Value Description
0
The sample is saved in Sample Sequence FIFO3.
1
The sample is sent to the digital comparator unit specified by
the S0DCSEL bit in the ADCSSDC03 register, and the value is
not written to the FIFO.
June 12, 2014
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Texas Instruments-Production Data
Analog-to-Digital Converter (ADC)
Register 40: ADC Sample Sequence 3 Digital Comparator Select (ADCSSDC3),
offset 0x0B4
This register determines which digital comparator receives the sample from the given conversion
on Sample Sequence 3 if the corresponding SnDCOP bit in the ADCSSOP3 register is set.
ADC Sample Sequence 3 Digital Comparator Select (ADCSSDC3)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x0B4
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:4
reserved
RO
0x0000.000
3:0
S0DCSEL
RW
0x0
S0DCSEL
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
RW
0
RW
0
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Sample 0 Digital Comparator Select
When the S0DCOP bit in the ADCSSOP3 register is set, this field
indicates which digital comparator unit (and its associated set of control
registers) receives the sample from Sample Sequencer 3.
Note:
Values not listed are reserved.
Value Description
0x0
Digital Comparator Unit 0 (ADCDCCMP0 and ADCCCTL0)
0x1
Digital Comparator Unit 1 (ADCDCCMP1 and ADCCCTL1)
0x2
Digital Comparator Unit 2 (ADCDCCMP2 and ADCCCTL2)
0x3
Digital Comparator Unit 3 (ADCDCCMP3 and ADCCCTL3)
0x4
Digital Comparator Unit 4 (ADCDCCMP4 and ADCCCTL4)
0x5
Digital Comparator Unit 5 (ADCDCCMP5 and ADCCCTL5)
0x6
Digital Comparator Unit 6 (ADCDCCMP6 and ADCCCTL6)
0x7
Digital Comparator Unit 7 (ADCDCCMP7 and ADCCCTL7)
870
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Register 41: ADC Sample Sequence Extended Input Multiplexer Select 3
(ADCSSEMUX3), offset 0x0B8
This register, along with the ADCSSMUX3 register, defines the analog input configuration for the
sample in a sequence executed with Sample Sequencer 3. If EMUX0 is set, the MUX0 field in the
ADCSSMUX3 register selects from AIN[21:16]. When EMUX0 is clear, the MUX0 field selects from
AIN[15:0]. This register is 1 bit wide and contains information for one possible sample.
Note that this register is not used when the differential channel designation is used (the Dn bit is set
in the ADCSSCTL3 register) because the ADCSSMUX3 register can select all the available pairs.
ADC Sample Sequence Extended Input Multiplexer Select 3 (ADCSSEMUX3)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x0B8
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:1
reserved
RO
0x0000.000
0
EMUX0
RW
0x0
RO
0
EMUX0
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1st Sample Input Select (Upper Bit)
The EMUX0 field is used during the only sample of a sequence executed
with the sample sequencer.
Value Description
0
The sample input is selected from AIN[15:0] using the
ADCSSMUX3 register. For example, if the MUX0 field is 0x0,
AIN0 is selected.
1
The sample input is selected from AIN[21:16] using the
ADCSSMUX3 register. For example, if the MUX0 field is 0x0,
AIN16 is selected.
June 12, 2014
871
Texas Instruments-Production Data
Analog-to-Digital Converter (ADC)
Register 42: ADC Digital Comparator Reset Initial Conditions (ADCDCRIC),
offset 0xD00
This register provides the ability to reset any of the digital comparator interrupt or trigger functions
back to their initial conditions. Resetting these functions ensures that the data that is being used by
the interrupt and trigger functions in the digital comparator unit is not stale.
ADC Digital Comparator Reset Initial Conditions (ADCDCRIC)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0xD00
Type WO, reset 0x0000.0000
31
30
29
28
27
26
25
24
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
DCTRIG7 DCTRIG6 DCTRIG5 DCTRIG4 DCTRIG3 DCTRIG2 DCTRIG1 DCTRIG0
RO
0
RO
0
RO
0
RO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
7
6
5
4
3
2
1
0
DCINT7
DCINT6
DCINT5
DCINT4
DCINT3
DCINT2
DCINT1
DCINT0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
Bit/Field
Name
Type
Reset
Description
31:24
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
23
DCTRIG7
WO
0
Digital Comparator Trigger 7
Value Description
0
No effect.
1
Resets the Digital Comparator 7 trigger unit to its initial
conditions.
When the trigger has been cleared, this bit is automatically cleared.
Because the digital comparators use the current and previous ADC
conversion values to determine when to assert the trigger, it is important
to reset the digital comparator to initial conditions when starting a new
sequence so that stale data is not used. After setting this bit, software
should wait until the bit clears before continuing.
22
DCTRIG6
WO
0
Digital Comparator Trigger 6
Value Description
0
No effect.
1
Resets the Digital Comparator 6 trigger unit to its initial
conditions.
When the trigger has been cleared, this bit is automatically cleared.
Because the digital comparators use the current and previous ADC
conversion values to determine when to assert the trigger, it is important
to reset the digital comparator to initial conditions when starting a new
sequence so that stale data is not used.
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Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Bit/Field
Name
Type
Reset
21
DCTRIG5
WO
0
Description
Digital Comparator Trigger 5
Value Description
0
No effect.
1
Resets the Digital Comparator 5 trigger unit to its initial
conditions.
When the trigger has been cleared, this bit is automatically cleared.
Because the digital comparators use the current and previous ADC
conversion values to determine when to assert the trigger, it is important
to reset the digital comparator to initial conditions when starting a new
sequence so that stale data is not used.
20
DCTRIG4
WO
0
Digital Comparator Trigger 4
Value Description
0
No effect.
1
Resets the Digital Comparator 4 trigger unit to its initial
conditions.
When the trigger has been cleared, this bit is automatically cleared.
Because the digital comparators use the current and previous ADC
conversion values to determine when to assert the trigger, it is important
to reset the digital comparator to initial conditions when starting a new
sequence so that stale data is not used.
19
DCTRIG3
WO
0
Digital Comparator Trigger 3
Value Description
0
No effect.
1
Resets the Digital Comparator 3 trigger unit to its initial
conditions.
When the trigger has been cleared, this bit is automatically cleared.
Because the digital comparators use the current and previous ADC
conversion values to determine when to assert the trigger, it is important
to reset the digital comparator to initial conditions when starting a new
sequence so that stale data is not used.
18
DCTRIG2
WO
0
Digital Comparator Trigger 2
Value Description
0
No effect.
1
Resets the Digital Comparator 2 trigger unit to its initial
conditions.
When the trigger has been cleared, this bit is automatically cleared.
Because the digital comparators use the current and previous ADC
conversion values to determine when to assert the trigger, it is important
to reset the digital comparator to initial conditions when starting a new
sequence so that stale data is not used.
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Analog-to-Digital Converter (ADC)
Bit/Field
Name
Type
Reset
17
DCTRIG1
WO
0
Description
Digital Comparator Trigger 1
Value Description
0
No effect.
1
Resets the Digital Comparator 1 trigger unit to its initial
conditions.
When the trigger has been cleared, this bit is automatically cleared.
Because the digital comparators use the current and previous ADC
conversion values to determine when to assert the trigger, it is important
to reset the digital comparator to initial conditions when starting a new
sequence so that stale data is not used.
16
DCTRIG0
WO
0
Digital Comparator Trigger 0
Value Description
0
No effect.
1
Resets the Digital Comparator 0 trigger unit to its initial
conditions.
When the trigger has been cleared, this bit is automatically cleared.
Because the digital comparators use the current and previous ADC
conversion values to determine when to assert the trigger, it is important
to reset the digital comparator to initial conditions when starting a new
sequence so that stale data is not used.
15:8
reserved
RO
0x00
7
DCINT7
WO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Digital Comparator Interrupt 7
Value Description
0
No effect.
1
Resets the Digital Comparator 7 interrupt unit to its initial
conditions.
When the interrupt has been cleared, this bit is automatically cleared.
Because the digital comparators use the current and previous ADC
conversion values to determine when to assert the interrupt, it is
important to reset the digital comparator to initial conditions when starting
a new sequence so that stale data is not used.
6
DCINT6
WO
0
Digital Comparator Interrupt 6
Value Description
0
No effect.
1
Resets the Digital Comparator 6 interrupt unit to its initial
conditions.
When the interrupt has been cleared, this bit is automatically cleared.
Because the digital comparators use the current and previous ADC
conversion values to determine when to assert the interrupt, it is
important to reset the digital comparator to initial conditions when starting
a new sequence so that stale data is not used.
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Tiva™ TM4C1237H6PZ Microcontroller
Bit/Field
Name
Type
Reset
5
DCINT5
WO
0
Description
Digital Comparator Interrupt 5
Value Description
0
No effect.
1
Resets the Digital Comparator 5 interrupt unit to its initial
conditions.
When the interrupt has been cleared, this bit is automatically cleared.
Because the digital comparators use the current and previous ADC
conversion values to determine when to assert the interrupt, it is
important to reset the digital comparator to initial conditions when starting
a new sequence so that stale data is not used.
4
DCINT4
WO
0
Digital Comparator Interrupt 4
Value Description
0
No effect.
1
Resets the Digital Comparator 4 interrupt unit to its initial
conditions.
When the interrupt has been cleared, this bit is automatically cleared.
Because the digital comparators use the current and previous ADC
conversion values to determine when to assert the interrupt, it is
important to reset the digital comparator to initial conditions when starting
a new sequence so that stale data is not used.
3
DCINT3
WO
0
Digital Comparator Interrupt 3
Value Description
0
No effect.
1
Resets the Digital Comparator 3 interrupt unit to its initial
conditions.
When the interrupt has been cleared, this bit is automatically cleared.
Because the digital comparators use the current and previous ADC
conversion values to determine when to assert the interrupt, it is
important to reset the digital comparator to initial conditions when starting
a new sequence so that stale data is not used.
2
DCINT2
WO
0
Digital Comparator Interrupt 2
Value Description
0
No effect.
1
Resets the Digital Comparator 2 interrupt unit to its initial
conditions.
When the interrupt has been cleared, this bit is automatically cleared.
Because the digital comparators use the current and previous ADC
conversion values to determine when to assert the interrupt, it is
important to reset the digital comparator to initial conditions when starting
a new sequence so that stale data is not used.
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Analog-to-Digital Converter (ADC)
Bit/Field
Name
Type
Reset
1
DCINT1
WO
0
Description
Digital Comparator Interrupt 1
Value Description
0
No effect.
1
Resets the Digital Comparator 1 interrupt unit to its initial
conditions.
When the interrupt has been cleared, this bit is automatically cleared.
Because the digital comparators use the current and previous ADC
conversion values to determine when to assert the interrupt, it is
important to reset the digital comparator to initial conditions when starting
a new sequence so that stale data is not used.
0
DCINT0
WO
0
Digital Comparator Interrupt 0
Value Description
0
No effect.
1
Resets the Digital Comparator 0 interrupt unit to its initial
conditions.
When the interrupt has been cleared, this bit is automatically cleared.
Because the digital comparators use the current and previous ADC
conversion values to determine when to assert the interrupt, it is
important to reset the digital comparator to initial conditions when starting
a new sequence so that stale data is not used.
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Tiva™ TM4C1237H6PZ Microcontroller
Register 43: ADC Digital Comparator Control 0 (ADCDCCTL0), offset 0xE00
Register 44: ADC Digital Comparator Control 1 (ADCDCCTL1), offset 0xE04
Register 45: ADC Digital Comparator Control 2 (ADCDCCTL2), offset 0xE08
Register 46: ADC Digital Comparator Control 3 (ADCDCCTL3), offset 0xE0C
Register 47: ADC Digital Comparator Control 4 (ADCDCCTL4), offset 0xE10
Register 48: ADC Digital Comparator Control 5 (ADCDCCTL5), offset 0xE14
Register 49: ADC Digital Comparator Control 6 (ADCDCCTL6), offset 0xE18
Register 50: ADC Digital Comparator Control 7 (ADCDCCTL7), offset 0xE1C
This register provides the comparison encodings that generate an interrupt.
ADC Digital Comparator Control n (ADCDCCTLn)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0xE00
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RW
0
RW
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
CIE
Bit/Field
Name
Type
Reset
31:5
reserved
RO
0x0000.0
4
CIE
RW
0
RW
0
CIC
RW
0
CIM
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Comparison Interrupt Enable
Value Description
0
Disables the comparison interrupt. ADC conversion data has
no effect on interrupt generation.
1
Enables the comparison interrupt. The ADC conversion data is
used to determine if an interrupt should be generated according
to the programming of the CIC and CIM fields.
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Analog-to-Digital Converter (ADC)
Bit/Field
Name
Type
Reset
3:2
CIC
RW
0x0
Description
Comparison Interrupt Condition
This field specifies the operational region in which an interrupt is
generated when the ADC conversion data is compared against the
values of COMP0 and COMP1. The COMP0 and COMP1 fields are defined
in the ADCDCCMPx registers.
Value Description
0x0
Low Band
ADC Data < COMP0 ≤ COMP1
0x1
Mid Band
COMP0 ≤ ADC Data < COMP1
0x2
reserved
0x3
High Band
COMP0 < COMP1 ≤ ADC Data
1:0
CIM
RW
0x0
Comparison Interrupt Mode
This field specifies the mode by which the interrupt comparison is made.
Value Description
0x0
Always
This mode generates an interrupt every time the ADC conversion
data falls within the selected operational region.
0x1
Once
This mode generates an interrupt the first time that the ADC
conversion data enters the selected operational region.
0x2
Hysteresis Always
This mode generates an interrupt when the ADC conversion
data falls within the selected operational region and continues
to generate the interrupt until the hysteresis condition is cleared
by entering the opposite operational region.
0x3
Hysteresis Once
This mode generates an interrupt the first time that the ADC
conversion data falls within the selected operational region. No
additional interrupts are generated until the hysteresis condition
is cleared by entering the opposite operational region.
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Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Register 51: ADC Digital Comparator Range 0 (ADCDCCMP0), offset 0xE40
Register 52: ADC Digital Comparator Range 1 (ADCDCCMP1), offset 0xE44
Register 53: ADC Digital Comparator Range 2 (ADCDCCMP2), offset 0xE48
Register 54: ADC Digital Comparator Range 3 (ADCDCCMP3), offset 0xE4C
Register 55: ADC Digital Comparator Range 4 (ADCDCCMP4), offset 0xE50
Register 56: ADC Digital Comparator Range 5 (ADCDCCMP5), offset 0xE54
Register 57: ADC Digital Comparator Range 6 (ADCDCCMP6), offset 0xE58
Register 58: ADC Digital Comparator Range 7 (ADCDCCMP7), offset 0xE5C
This register defines the comparison values that are used to determine if the ADC conversion data
falls in the appropriate operating region.
Note:
The value in the COMP1 field must be greater than or equal to the value in the COMP0 field
or unexpected results can occur.
ADC Digital Comparator Range n (ADCDCCMPn)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0xE40
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
reserved
Type
Reset
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
21
COMP1
RO
0
RO
0
COMP0
RO
0
RO
0
RW
0
RW
0
RW
0
Bit/Field
Name
Type
Reset
31:28
reserved
RO
0x0
27:16
COMP1
RW
0x000
RW
0
RW
0
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Compare 1
The value in this field is compared against the ADC conversion data.
The result of the comparison is used to determine if the data lies within
the high-band region.
Note that the value of COMP1 must be greater than or equal to the value
of COMP0.
15:12
reserved
RO
0x0
11:0
COMP0
RW
0x000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Compare 0
The value in this field is compared against the ADC conversion data.
The result of the comparison is used to determine if the data lies within
the low-band region.
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Analog-to-Digital Converter (ADC)
Register 59: ADC Peripheral Properties (ADCPP), offset 0xFC0
The ADCPP register provides information regarding the properties of the ADC module.
ADC Peripheral Properties (ADCPP)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0xFC0
Type RO, reset 0x00B0.2167
31
30
29
28
RO
0
RO
0
RO
0
RO
0
15
14
13
RO
0
RO
0
RO
1
27
26
25
24
23
22
21
RO
0
RO
0
RO
0
RO
0
RO
1
RO
0
RO
1
12
11
10
9
8
7
6
RO
0
RO
0
RO
0
RO
0
RO
1
RO
0
RO
1
reserved
Type
Reset
DC
Type
Reset
19
18
17
RO
1
RO
0
RO
0
RO
0
RO
0
5
4
3
2
1
0
RO
1
RO
0
RO
0
RO
1
RO
1
RO
1
TS
20
RSL
TYPE
CH
Bit/Field
Name
Type
Reset
31:24
reserved
RO
0
23
TS
RO
0x1
16
MSR
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Temperature Sensor
Value Description
0
The ADC module does not have a temperature sensor.
1
The ADC module has a temperature sensor.
This field provides the similar information as the legacy DC1 register
TEMPSNS bit.
22:18
RSL
RO
0xC
Resolution
This field specifies the maximum number of binary bits used to represent
the converted sample. The field is encoded as a binary value, in the
range of 0 to 32 bits.
17:16
TYPE
RO
0x0
ADC Architecture
Value
Description
0x0
SAR
0x1 - 0x3 Reserved
15:10
DC
RO
0x8
Digital Comparator Count
This field specifies the number of ADC digital comparators available to
the converter. The field is encoded as a binary value, in the range of 0
to 63.
This field provides similar information to the legacy DC9 register
ADCnDCn bits.
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Tiva™ TM4C1237H6PZ Microcontroller
Bit/Field
Name
Type
Reset
Description
9:4
CH
RO
0x16
ADC Channel Count
This field specifies the number of ADC input channels available to the
converter. This field is encoded as a binary value, in the range of 0 to
63.
This field provides similar information to the legacy DC3 and DC8 register
ADCnAINn bits.
3:0
MSR
RO
0x7
Maximum ADC Sample Rate
This field specifies the maximum number of ADC conversions per
second. The MSR field is encoded as follows:
Value
Description
0x0
Reserved
0x1
125 ksps
0x2
Reserved
0x3
250 ksps
0x4
Reserved
0x5
500 ksps
0x6
Reserved
0x7
1 Msps
0x8 - 0xF Reserved
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Analog-to-Digital Converter (ADC)
Register 60: ADC Peripheral Configuration (ADCPC), offset 0xFC4
The ADCPC register provides information regarding the configuration of the peripheral.
ADC Peripheral Configuration (ADCPC)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0xFC4
Type RW, reset 0x0000.0007
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
RW
1
RW
1
RW
1
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
31:4
reserved
RO
3:0
SR
RW
Reset
SR
Description
0x0000.0000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x7
ADC Sample Rate
This field specifies the number of ADC conversions per second and is
used in Run, Sleep, and Deep-Sleep modes. The field encoding is based
on the legacy RCGC0 register encoding. The programmed sample rate
cannot exceed the maximum sample rate specified by the MSR field in
the ADCPP register. The SR field is encoded as follows:
Value
Description
0x0
Reserved
0x1
125 ksps
0x2
Reserved
0x3
250 ksps
0x4
Reserved
0x5
500 ksps
0x6
Reserved
0x7
1 Msps
0x8 - 0xF Reserved
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Tiva™ TM4C1237H6PZ Microcontroller
Register 61: ADC Clock Configuration (ADCCC), offset 0xFC8
The ADCCC register controls the clock source for the ADC module.
To use the PIOSC to clock the ADC, first power up the PLL and then enable the PIOSC in the CS
bit field, then disable the PLL.
To use the MOSC to clock the ADC, first power up the PLL and then enable the clock to the ADC
module, then disable the PLL and switch to the MOSC for the system clock.
ADC Clock Configuration (ADCCC)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0xFC8
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
reserved
Type
Reset
CS
Bit/Field
Name
Type
Reset
31:4
reserved
RO
0x0000.000
3:0
CS
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
ADC Clock Source
The following table specifies the clock source that generates the ADC
clock input, see Figure 5-5 on page 217.
Value
Description
0x0
Either the 16-MHz system clock (if the PLL bypass is in
effect) or the 16 MHz clock derived from PLL ÷ 25 (default).
Note that when the PLL is bypassed, the system clock must
be at least 16 MHz.
0x1
PIOSC
The PIOSC provides a 16-MHz clock source for the ADC.
If the PIOSC is used as the clock source, the ADC module
can continue to operate in Deep-Sleep mode.
0x2 - 0xF Reserved
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Universal Asynchronous Receivers/Transmitters (UARTs)
14
Universal Asynchronous Receivers/Transmitters
(UARTs)
The TM4C1237H6PZ controller includes eight Universal Asynchronous Receiver/Transmitter (UART)
with the following features:
■ Programmable baud-rate generator allowing speeds up to 5 Mbps for regular speed (divide by
16) and 10 Mbps for high speed (divide by 8)
■ Separate 16x8 transmit (TX) and receive (RX) FIFOs to reduce CPU interrupt service loading
■ Programmable FIFO length, including 1-byte deep operation providing conventional
double-buffered interface
■ FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8
■ Standard asynchronous communication bits for start, stop, and parity
■ Line-break generation and detection
■ Fully programmable serial interface characteristics
– 5, 6, 7, or 8 data bits
– Even, odd, stick, or no-parity bit generation/detection
– 1 or 2 stop bit generation
■ IrDA serial-IR (SIR) encoder/decoder providing
– Programmable use of IrDA Serial Infrared (SIR) or UART input/output
– Support of IrDA SIR encoder/decoder functions for data rates up to 115.2 Kbps half-duplex
– Support of normal 3/16 and low-power (1.41-2.23 μs) bit durations
– Programmable internal clock generator enabling division of reference clock by 1 to 256 for
low-power mode bit duration
■ Support for communication with ISO 7816 smart cards
■ Modem flow control and status (on UART1)
■ EIA-485 9-bit support
■ Standard FIFO-level and End-of-Transmission interrupts
■ Efficient transfers using Micro Direct Memory Access Controller (µDMA)
– Separate channels for transmit and receive
– Receive single request asserted when data is in the FIFO; burst request asserted at
programmed FIFO level
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Tiva™ TM4C1237H6PZ Microcontroller
– Transmit single request asserted when there is space in the FIFO; burst request asserted at
programmed FIFO level
14.1
Block Diagram
Figure 14-1. UART Module Block Diagram
PIOSC
Clock Control
UARTCC
UARTCTL
System Clock
DMA Request
Baud Clock
DMA Control
UARTDMACTL
Interrupt
Interrupt Control
TxFIFO
16 x 8
UARTIFLS
UARTIM
UARTMIS
UARTRIS
UARTICR
Identification Registers
.
.
.
UARTPCellID0
Transmitter
(with SIR
Transmit
Encoder)
UARTPCellID1
UnTx
Baud Rate
Generator
UARTPCellID2
UARTPCellID3
UARTDR
UARTPeriphID0
UARTIBRD
UARTFBRD
UARTPeriphID1
Receiver
(with SIR
Receive
Decoder)
Control/Status
UnRx
UARTRSR/ECR
UARTPeriphID2
UARTFR
UARTPeriphID3
RxFIFO
16 x 8
UARTLCRH
UARTPeriphID4
UARTCTL
UARTPeriphID5
UARTILPR
UART9BITADDR
UARTPeriphID6
.
.
.
UART9BITAMASK
UARTPeriphID7
14.2
UARTPP
Signal Description
The following table lists the external signals of the UART module and describes the function of each.
The UART signals are alternate functions for some GPIO signals and default to be GPIO signals at
reset, with the exception of the U0Rx and U0Tx pins which default to the UART function. The column
in the table below titled "Pin Mux/Pin Assignment" lists the possible GPIO pin placements for these
UART signals. The AFSEL bit in the GPIO Alternate Function Select (GPIOAFSEL) register
(page 659) should be set to choose the UART function. The number in parentheses is the encoding
that must be programmed into the PMCn field in the GPIO Port Control (GPIOPCTL) register
(page 677) to assign the UART signal to the specified GPIO port pin. For more information on
configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 634.
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Table 14-1. UART Signals (100LQFP)
Pin Name
Pin Number Pin Mux / Pin
Assignment
U0Rx
26
a
Pin Type
Buffer Type
Description
PA0 (1)
I
TTL
UART module 0 receive.
U0Tx
27
PA1 (1)
O
TTL
UART module 0 transmit.
U1CTS
24
41
PC5 (8)
PF1 (1)
I
TTL
UART module 1 Clear To Send modem flow control
input signal.
U1DCD
42
PF2 (1)
I
TTL
UART module 1 Data Carrier Detect modem status
input signal.
U1DSR
43
PF3 (1)
I
TTL
UART module 1 Data Set Ready modem output
control line.
U1DTR
39
PF4 (1)
O
TTL
UART module 1 Data Terminal Ready modem
status input signal.
U1RI
90
PE7 (1)
I
TTL
UART module 1 Ring Indicator modem status input
signal.
U1RTS
25
40
PC4 (8)
PF0 (1)
O
TTL
UART module 1 Request to Send modem flow
control output line.
U1Rx
25
70
PC4 (2)
PB0 (1)
I
TTL
UART module 1 receive.
U1Tx
24
71
PC5 (2)
PB1 (1)
O
TTL
UART module 1 transmit.
U2Rx
74
99
PG4 (1)
PD6 (1)
I
TTL
UART module 2 receive.
U2Tx
75
100
PG5 (1)
PD7 (1)
O
TTL
UART module 2 transmit.
U3Rx
23
PC6 (1)
I
TTL
UART module 3 receive.
U3Tx
22
PC7 (1)
O
TTL
UART module 3 transmit.
U4Rx
25
68
PC4 (1)
PJ0 (1)
I
TTL
UART module 4 receive.
U4Tx
24
69
PC5 (1)
PJ1 (1)
O
TTL
UART module 4 transmit.
U5Rx
11
95
PJ2 (1)
PE4 (1)
I
TTL
UART module 5 receive.
U5Tx
96
PE5 (1)
O
TTL
UART module 5 transmit.
U6Rx
97
PD4 (1)
I
TTL
UART module 6 receive.
U6Tx
98
PD5 (1)
O
TTL
UART module 6 transmit.
U7Rx
15
PE0 (1)
I
TTL
UART module 7 receive.
U7Tx
14
PE1 (1)
O
TTL
UART module 7 transmit.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
14.3
Functional Description
Each TM4C1237H6PZ UART performs the functions of parallel-to-serial and serial-to-parallel
conversions. It is similar in functionality to a 16C550 UART, but is not register compatible.
The UART is configured for transmit and/or receive via the TXE and RXE bits of the UART Control
(UARTCTL) register (see page 911). Transmit and receive are both enabled out of reset. Before any
control registers are programmed, the UART must be disabled by clearing the UARTEN bit in
UARTCTL. If the UART is disabled during a TX or RX operation, the current transaction is completed
prior to the UART stopping.
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The UART module also includes a serial IR (SIR) encoder/decoder block that can be connected to
an infrared transceiver to implement an IrDA SIR physical layer. The SIR function is programmed
using the UARTCTL register.
14.3.1
Transmit/Receive Logic
The transmit logic performs parallel-to-serial conversion on the data read from the transmit FIFO.
The control logic outputs the serial bit stream beginning with a start bit and followed by the data bits
(LSB first), parity bit, and the stop bits according to the programmed configuration in the control
registers. See Figure 14-2 on page 887 for details.
The receive logic performs serial-to-parallel conversion on the received bit stream after a valid start
pulse has been detected. Overrun, parity, frame error checking, and line-break detection are also
performed, and their status accompanies the data that is written to the receive FIFO.
Figure 14-2. UART Character Frame
UnTX
LSB
1
5-8 data bits
0
n
Parity bit
if enabled
Start
14.3.2
1-2
stop bits
MSB
Baud-Rate Generation
The baud-rate divisor is a 22-bit number consisting of a 16-bit integer and a 6-bit fractional part.
The number formed by these two values is used by the baud-rate generator to determine the bit
period. Having a fractional baud-rate divisor allows the UART to generate all the standard baud
rates.
The 16-bit integer is loaded through the UART Integer Baud-Rate Divisor (UARTIBRD) register
(see page 907) and the 6-bit fractional part is loaded with the UART Fractional Baud-Rate Divisor
(UARTFBRD) register (see page 908). The baud-rate divisor (BRD) has the following relationship
to the system clock (where BRDI is the integer part of the BRD and BRDF is the fractional part,
separated by a decimal place.)
BRD = BRDI + BRDF = UARTSysClk / (ClkDiv * Baud Rate)
where UARTSysClk is the system clock connected to the UART, and ClkDiv is either 16 (if HSE
in UARTCTL is clear) or 8 (if HSE is set). By default, this will be the main system clock described
in “Clock Control” on page 214. Alternatively, the UART may be clocked from the internal precision
oscillator (PIOSC), independent of the system clock selection. This will allow the UART clock to be
programmed independently of the system clock PLL settings. See the UARTCC register for more
details.
The 6-bit fractional number (that is to be loaded into the DIVFRAC bit field in the UARTFBRD register)
can be calculated by taking the fractional part of the baud-rate divisor, multiplying it by 64, and
adding 0.5 to account for rounding errors:
UARTFBRD[DIVFRAC] = integer(BRDF * 64 + 0.5)
The UART generates an internal baud-rate reference clock at 8x or 16x the baud-rate (referred to
as Baud8 and Baud16, depending on the setting of the HSE bit (bit 5) in UARTCTL). This reference
clock is divided by 8 or 16 to generate the transmit clock, and is used for error detection during
receive operations. Note that the state of the HSE bit has no effect on clock generation in ISO 7816
smart card mode (when the SMART bit in the UARTCTL register is set).
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Along with the UART Line Control, High Byte (UARTLCRH) register (see page 909), the UARTIBRD
and UARTFBRD registers form an internal 30-bit register. This internal register is only updated
when a write operation to UARTLCRH is performed, so any changes to the baud-rate divisor must
be followed by a write to the UARTLCRH register for the changes to take effect.
To update the baud-rate registers, there are four possible sequences:
■ UARTIBRD write, UARTFBRD write, and UARTLCRH write
■ UARTFBRD write, UARTIBRD write, and UARTLCRH write
■ UARTIBRD write and UARTLCRH write
■ UARTFBRD write and UARTLCRH write
14.3.3
Data Transmission
Data received or transmitted is stored in two 16-byte FIFOs, though the receive FIFO has an extra
four bits per character for status information. For transmission, data is written into the transmit FIFO.
If the UART is enabled, it causes a data frame to start transmitting with the parameters indicated
in the UARTLCRH register. Data continues to be transmitted until there is no data left in the transmit
FIFO. The BUSY bit in the UART Flag (UARTFR) register (see page 903) is asserted as soon as
data is written to the transmit FIFO (that is, if the FIFO is non-empty) and remains asserted while
data is being transmitted. The BUSY bit is negated only when the transmit FIFO is empty, and the
last character has been transmitted from the shift register, including the stop bits. The UART can
indicate that it is busy even though the UART may no longer be enabled.
When the receiver is idle (the UnRx signal is continuously 1), and the data input goes Low (a start
bit has been received), the receive counter begins running and data is sampled on the eighth cycle
of Baud16 or fourth cycle of Baud8 depending on the setting of the HSE bit (bit 5) in UARTCTL
(described in “Transmit/Receive Logic” on page 887).
The start bit is valid and recognized if the UnRx signal is still low on the eighth cycle of Baud16 (HSE
clear) or the fourth cycle of Baud 8 (HSE set), otherwise it is ignored. After a valid start bit is detected,
successive data bits are sampled on every 16th cycle of Baud16 or 8th cycle of Baud8 (that is, one
bit period later) according to the programmed length of the data characters and value of the HSE
bit in UARTCTL. The parity bit is then checked if parity mode is enabled. Data length and parity are
defined in the UARTLCRH register.
Lastly, a valid stop bit is confirmed if the UnRx signal is High, otherwise a framing error has occurred.
When a full word is received, the data is stored in the receive FIFO along with any error bits
associated with that word.
14.3.4
Serial IR (SIR)
The UART peripheral includes an IrDA serial-IR (SIR) encoder/decoder block. The IrDA SIR block
provides functionality that converts between an asynchronous UART data stream and a half-duplex
serial SIR interface. No analog processing is performed on-chip. The role of the SIR block is to
provide a digital encoded output and decoded input to the UART. When enabled, the SIR block
uses the UnTx and UnRx pins for the SIR protocol. These signals should be connected to an infrared
transceiver to implement an IrDA SIR physical layer link. The SIR block can receive and transmit,
but it is only half-duplex so it cannot do both at the same time. Transmission must be stopped before
data can be received. The IrDA SIR physical layer specifies a minimum 10-ms delay between
transmission and reception. The SIR block has two modes of operation:
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■ In normal IrDA mode, a zero logic level is transmitted as a high pulse of 3/16th duration of the
selected baud rate bit period on the output pin, while logic one levels are transmitted as a static
LOW signal. These levels control the driver of an infrared transmitter, sending a pulse of light
for each zero. On the reception side, the incoming light pulses energize the photo transistor base
of the receiver, pulling its output LOW and driving the UART input pin LOW.
■ In low-power IrDA mode, the width of the transmitted infrared pulse is set to three times the
period of the internally generated IrLPBaud16 signal (1.63 µs, assuming a nominal 1.8432 MHz
frequency) by changing the appropriate bit in the UARTCTL register (see page 911).
Whether the device is in normal or low-power IrDA mode, a start bit is deemed valid if the decoder
is still Low, one period of IrLPBaud16 after the Low was first detected. This enables a normal-mode
UART to receive data from a low-power mode UART that can transmit pulses as small as 1.41 µs.
Thus, for both low-power and normal mode operation, the ILPDVSR field in the UARTILPR register
must be programmed such that 1.42 MHz < FIrLPBaud16 < 2.12 MHz, resulting in a low-power pulse
duration of 1.41–2.11 μs (three times the period of IrLPBaud16). The minimum frequency of
IrLPBaud16 ensures that pulses less than one period of IrLPBaud16 are rejected, but pulses
greater than 1.4 μs are accepted as valid pulses.
Figure 14-3 on page 889 shows the UART transmit and receive signals, with and without IrDA
modulation.
Figure 14-3. IrDA Data Modulation
Data bits
Start
bit
UnTx
1
0
0
0
1
Stop
bit
0
0
1
1
1
UnTx with IrDA
3
16 Bit period
Bit period
UnRx with IrDA
UnRx
0
1
0
Start
1
0
0
1
1
Data bits
0
1
Stop
In both normal and low-power IrDA modes:
■ During transmission, the UART data bit is used as the base for encoding
■ During reception, the decoded bits are transferred to the UART receive logic
The IrDA SIR physical layer specifies a half-duplex communication link, with a minimum 10-ms
delay between transmission and reception. This delay must be generated by software because it
is not automatically supported by the UART. The delay is required because the infrared receiver
electronics might become biased or even saturated from the optical power coupled from the adjacent
transmitter LED. This delay is known as latency or receiver setup time.
14.3.5
ISO 7816 Support
The UART offers basic support to allow communication with an ISO 7816 smartcard. When bit 3
(SMART) of the UARTCTL register is set, the UnTx signal is used as a bit clock, and the UnRx signal
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is used as the half-duplex communication line connected to the smartcard. A GPIO signal can be
used to generate the reset signal to the smartcard. The remaining smartcard signals should be
provided by the system design. The maximum clock rate in this mode is system clock / 16.
When using ISO 7816 mode, the UARTLCRH register must be set to transmit 8-bit words (WLEN
bits 6:5 configured to 0x3) with EVEN parity (PEN set and EPS set). In this mode, the UART
automatically uses 2 stop bits, and the STP2 bit of the UARTLCRH register is ignored.
If a parity error is detected during transmission, UnRx is pulled Low during the second stop bit. In
this case, the UART aborts the transmission, flushes the transmit FIFO and discards any data it
contains, and raises a parity error interrupt, allowing software to detect the problem and initiate
retransmission of the affected data. Note that the UART does not support automatic retransmission
in this case.
14.3.6
Modem Handshake Support
This section describes how to configure and use the modem flow control and status signals for
UART1 when connected as a DTE (data terminal equipment) or as a DCE (data communications
equipment). In general, a modem is a DCE and a computing device that connects to a modem is
the DTE.
14.3.6.1
Signaling
The status signals provided by UART1 differ based on whether the UART is used as a DTE or DCE.
When used as a DTE, the modem flow control and status signals are defined as:
■ U1CTS is Clear To Send
■ U1DSR is Data Set Ready
■ U1DCD is Data Carrier Detect
■ U1RI is Ring Indicator
■ U1RTS is Request To Send
■ U1DTR is Data Terminal Ready
When used as a DCE, the modem flow control and status signals are defined as:
■ U1CTS is Request To Send
■ U1DSR is Data Terminal Ready
■ U1RTS is Clear To Send
■ U1DTR is Data Set Ready
Note that the support for DCE functions Data Carrier Detect and Ring Indicator are not provided. If
these signals are required, their function can be emulated by using a general-purpose I/O signal
and providing software support.
14.3.6.2
Flow Control
Flow control can be accomplished by either hardware or software. The following sections describe
the different methods.
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Hardware Flow Control (RTS/CTS)
Hardware flow control between two devices is accomplished by connecting the U1RTS output to the
Clear-To-Send input on the receiving device, and connecting the Request-To-Send output on the
receiving device to the U1CTS input.
The U1CTS input controls the transmitter. The transmitter may only transmit data when the U1CTS
input is asserted. The U1RTS output signal indicates the state of the receive FIFO. U1CTS remains
asserted until the preprogrammed watermark level is reached, indicating that the Receive FIFO has
no space to store additional characters.
The UARTCTL register bits 15 (CTSEN) and 14 (RTSEN) specify the flow control mode as shown in
Table 14-2 on page 891.
Table 14-2. Flow Control Mode
Description
CTSEN
RTSEN
1
1
RTS and CTS flow control enabled
1
0
Only CTS flow control enabled
0
1
Only RTS flow control enabled
0
0
Both RTS and CTS flow control disabled
Note that when RTSEN is 1, software cannot modify the U1RTS output value through the UARTCTL
register Request to Send (RTS) bit, and the status of the RTS bit should be ignored.
Software Flow Control (Modem Status Interrupts)
Software flow control between two devices is accomplished by using interrupts to indicate the status
of the UART. Interrupts may be generated for the U1DSR, U1DCD, U1CTS, and U1RI signals using
bits 3:0 of the UARTIM register, respectively. The raw and masked interrupt status may be checked
using the UARTRIS and UARTMIS register. These interrupts may be cleared using the UARTICR
register.
14.3.7
9-Bit UART Mode
The UART provides a 9-bit mode that is enabled with the 9BITEN bit in the UART9BITADDR
register. This feature is useful in a multi-drop configuration of the UART where a single master
connected to multiple slaves can communicate with a particular slave through its address or set of
addresses along with a qualifier for an address byte. All the slaves check for the address qualifier
in the place of the parity bit and, if set, then compare the byte received with the preprogrammed
address. If the address matches, then it receives or sends further data. If the address does not
match, it drops the address byte and any subsequent data bytes. If the UART is in 9-bit mode, then
the receiver operates with no parity mode. The address can be predefined to match with the received
byte and it can be configured with the UART9BITADDR register. The matching can be extended
to a set of addresses using the address mask in the UART9BITAMASK register. By default, the
UART9BITAMASK is 0xFF, meaning that only the specified address is matched.
When not finding a match, the rest of the data bytes with the 9th bit cleared are dropped. If a match
is found, then an interrupt is generated to the NVIC for further action. The subsequent data bytes
with the cleared 9th bit are stored in the FIFO. Software can mask this interrupt in case μDMA and/or
FIFO operations are enabled for this instance and processor intervention is not required. All the
send transactions with 9-bit mode are data bytes and the 9th bit is cleared. Software can override
the 9th bit to be set (to indicate address) by overriding the parity settings to sticky parity with odd
parity enabled for a particular byte. To match the transmission time with correct parity settings, the
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address byte can be transmitted as a single then a burst transfer. The Transmit FIFO does not hold
the address/data bit, hence software should take care of enabling the address bit appropriately.
14.3.8
FIFO Operation
The UART has two 16x8 FIFOs; one for transmit and one for receive. Both FIFOs are accessed via
the UART Data (UARTDR) register (see page 898). Read operations of the UARTDR register return
a 12-bit value consisting of 8 data bits and 4 error flags while write operations place 8-bit data in
the transmit FIFO.
Out of reset, both FIFOs are disabled and act as 1-byte-deep holding registers. The FIFOs are
enabled by setting the FEN bit in UARTLCRH (page 909).
FIFO status can be monitored via the UART Flag (UARTFR) register (see page 903) and the UART
Receive Status (UARTRSR) register. Hardware monitors empty, full and overrun conditions. The
UARTFR register contains empty and full flags (TXFE, TXFF, RXFE, and RXFF bits), and the
UARTRSR register shows overrun status via the OE bit. If the FIFOs are disabled, the empty and
full flags are set according to the status of the 1-byte-deep holding registers.
The trigger points at which the FIFOs generate interrupts is controlled via the UART Interrupt FIFO
Level Select (UARTIFLS) register (see page 915). Both FIFOs can be individually configured to
trigger interrupts at different levels. Available configurations include ⅛, ¼, ½, ¾, and ⅞. For example,
if the ¼ option is selected for the receive FIFO, the UART generates a receive interrupt after 4 data
bytes are received. Out of reset, both FIFOs are configured to trigger an interrupt at the ½ mark.
14.3.9
Interrupts
The UART can generate interrupts when the following conditions are observed:
■ Overrun Error
■ Break Error
■ Parity Error
■ Framing Error
■ Receive Timeout
■ Transmit (when condition defined in the TXIFLSEL bit in the UARTIFLS register is met, or if the
EOT bit in UARTCTL is set, when the last bit of all transmitted data leaves the serializer)
■ Receive (when condition defined in the RXIFLSEL bit in the UARTIFLS register is met)
All of the interrupt events are ORed together before being sent to the interrupt controller, so the
UART can only generate a single interrupt request to the controller at any given time. Software can
service multiple interrupt events in a single interrupt service routine by reading the UART Masked
Interrupt Status (UARTMIS) register (see page 923).
The interrupt events that can trigger a controller-level interrupt are defined in the UART Interrupt
Mask (UARTIM) register (see page 917) by setting the corresponding IM bits. If interrupts are not
used, the raw interrupt status is visible via the UART Raw Interrupt Status (UARTRIS) register
(see page 920).
Note:
For receive timeout, the RTIM bit in the UARTIM register must be set to see the RTMIS and
RTRIS status in the UARTMIS and UARTRIS registers.
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Interrupts are always cleared (for both the UARTMIS and UARTRIS registers) by writing a 1 to the
corresponding bit in the UART Interrupt Clear (UARTICR) register (see page 926).
The receive timeout interrupt is asserted when the receive FIFO is not empty, and no further data
is received over a 32-bit period when the HSE bit is clear or over a 64-bit period when the HSE bit
is set. The receive timeout interrupt is cleared either when the FIFO becomes empty through reading
all the data (or by reading the holding register), or when a 1 is written to the corresponding bit in the
UARTICR register.
The receive interrupt changes state when one of the following events occurs:
■ If the FIFOs are enabled and the receive FIFO reaches the programmed trigger level, the RXRIS
bit is set. The receive interrupt is cleared by reading data from the receive FIFO until it becomes
less than the trigger level, or by clearing the interrupt by writing a 1 to the RXIC bit.
■ If the FIFOs are disabled (have a depth of one location) and data is received thereby filling the
location, the RXRIS bit is set. The receive interrupt is cleared by performing a single read of the
receive FIFO, or by clearing the interrupt by writing a 1 to the RXIC bit.
The transmit interrupt changes state when one of the following events occurs:
■ If the FIFOs are enabled and the transmit FIFO progresses through the programmed trigger
level, the TXRIS bit is set. The transmit interrupt is based on a transition through level, therefore
the FIFO must be written past the programmed trigger level otherwise no further transmit interrupts
will be generated. The transmit interrupt is cleared by writing data to the transmit FIFO until it
becomes greater than the trigger level, or by clearing the interrupt by writing a 1 to the TXIC bit.
■ If the FIFOs are disabled (have a depth of one location) and there is no data present in the
transmitters single location, the TXRIS bit is set. It is cleared by performing a single write to the
transmit FIFO, or by clearing the interrupt by writing a 1 to the TXIC bit.
14.3.10
Loopback Operation
The UART can be placed into an internal loopback mode for diagnostic or debug work by setting
the LBE bit in the UARTCTL register (see page 911). In loopback mode, data transmitted on the
UnTx output is received on the UnRx input. Note that the LBE bit should be set before the UART is
enabled.
14.3.11
DMA Operation
The UART provides an interface to the μDMA controller with separate channels for transmit and
receive. The DMA operation of the UART is enabled through the UART DMA Control
(UARTDMACTL) register. When DMA operation is enabled, the UART asserts a DMA request on
the receive or transmit channel when the associated FIFO can transfer data. For the receive channel,
a single transfer request is asserted whenever any data is in the receive FIFO. A burst transfer
request is asserted whenever the amount of data in the receive FIFO is at or above the FIFO trigger
level configured in the UARTIFLS register. For the transmit channel, a single transfer request is
asserted whenever there is at least one empty location in the transmit FIFO. The burst request is
asserted whenever the transmit FIFO contains fewer characters than the FIFO trigger level. The
single and burst DMA transfer requests are handled automatically by the μDMA controller depending
on how the DMA channel is configured.
To enable DMA operation for the receive channel, set the RXDMAE bit of the DMA Control
(UARTDMACTL) register. To enable DMA operation for the transmit channel, set the TXDMAE bit
of the UARTDMACTL register. The UART can also be configured to stop using DMA for the receive
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channel if a receive error occurs. If the DMAERR bit of the UARTDMACR register is set and a receive
error occurs, the DMA receive requests are automatically disabled. This error condition can be
cleared by clearing the appropriate UART error interrupt.
If the µDMA is enabled, then the controller triggers an interrupt when the TX FIFO or RX FIFO has
reached a trigger point as programmed in the UARTIFLS register. The interrupt occurs on the UART
interrupt vector. Therefore, if interrupts are used for UART operation and DMA is enabled, the UART
interrupt handler must be designed to handle the μDMA completion interrupt.
Note:
To trigger an interrupt on transmit completion from the UART's serializer, the EOT bit must
be set in the UARTCTL register. In this configuration, the transmit interrupt is generated
once the FIFO is completely empty and all data including the stop bits have left the transmit
serializer. In this case, setting the TXIFLSEL bit in the UARTIFLS register is ignored.
When transfers are performed from a FIFO of the UART using the μDMA, and any interrupt is
generated from the UART, the UART module's status bit in the DMA Channel Interrupt Status
(DMACHIS) register must be checked at the end of the interrupt service routine. If the status bit is
set, clear the interrupt by writing a 1 to it.
See “Micro Direct Memory Access (μDMA)” on page 570 for more details about programming the
μDMA controller.
14.4
Initialization and Configuration
To enable and initialize the UART, the following steps are necessary:
1. Enable the UART module using the RCGCUART register (see page 336).
2. Enable the clock to the appropriate GPIO module via the RCGCGPIO register (see page 331).
To find out which GPIO port to enable, refer to Table 21-5 on page 1249.
3. Set the GPIO AFSEL bits for the appropriate pins (see page 659). To determine which GPIOs to
configure, see Table 21-4 on page 1242.
4. Configure the GPIO current level and/or slew rate as specified for the mode selected (see
page 661 and page 669).
5. Configure the PMCn fields in the GPIOPCTL register to assign the UART signals to the appropriate
pins (see page 677 and Table 21-5 on page 1249).
To use the UART, the peripheral clock must be enabled by setting the appropriate bit in the
RCGCUART register (page 336). In addition, the clock to the appropriate GPIO module must be
enabled via the RCGCGPIO register (page 331) in the System Control module. To find out which
GPIO port to enable, refer to Table 21-5 on page 1249.
This section discusses the steps that are required to use a UART module. For this example, the
UART clock is assumed to be 20 MHz, and the desired UART configuration is:
■ 115200 baud rate
■ Data length of 8 bits
■ One stop bit
■ No parity
■ FIFOs disabled
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■ No interrupts
The first thing to consider when programming the UART is the baud-rate divisor (BRD), because
the UARTIBRD and UARTFBRD registers must be written before the UARTLCRH register. Using
the equation described in “Baud-Rate Generation” on page 887, the BRD can be calculated:
BRD = 20,000,000 / (16 * 115,200) = 10.8507
which means that the DIVINT field of the UARTIBRD register (see page 907) should be set to 10
decimal or 0xA. The value to be loaded into the UARTFBRD register (see page 908) is calculated
by the equation:
UARTFBRD[DIVFRAC] = integer(0.8507 * 64 + 0.5) = 54
With the BRD values in hand, the UART configuration is written to the module in the following order:
1. Disable the UART by clearing the UARTEN bit in the UARTCTL register.
2. Write the integer portion of the BRD to the UARTIBRD register.
3. Write the fractional portion of the BRD to the UARTFBRD register.
4. Write the desired serial parameters to the UARTLCRH register (in this case, a value of
0x0000.0060).
5. Configure the UART clock source by writing to the UARTCC register.
6. Optionally, configure the µDMA channel (see “Micro Direct Memory Access (μDMA)” on page 570)
and enable the DMA option(s) in the UARTDMACTL register.
7. Enable the UART by setting the UARTEN bit in the UARTCTL register.
14.5
Register Map
Table 14-3 on page 896 lists the UART registers. The offset listed is a hexadecimal increment to the
register's address, relative to that UART's base address:
■
■
■
■
■
■
■
■
UART0: 0x4000.C000
UART1: 0x4000.D000
UART2: 0x4000.E000
UART3: 0x4000.F000
UART4: 0x4001.0000
UART5: 0x4001.1000
UART6: 0x4001.2000
UART7: 0x4001.3000
The UART module clock must be enabled before the registers can be programmed (see page 336).
There must be a delay of 3 system clocks after the UART module clock is enabled before any UART
module registers are accessed.
The UART must be disabled (see the UARTEN bit in the UARTCTL register on page 911) before any
of the control registers are reprogrammed. When the UART is disabled during a TX or RX operation,
the current transaction is completed prior to the UART stopping.
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Universal Asynchronous Receivers/Transmitters (UARTs)
Table 14-3. UART Register Map
Type
Reset
Description
See
page
UARTDR
RW
0x0000.0000
UART Data
898
0x004
UARTRSR/UARTECR
RW
0x0000.0000
UART Receive Status/Error Clear
900
0x018
UARTFR
RO
0x0000.0090
UART Flag
903
0x020
UARTILPR
RW
0x0000.0000
UART IrDA Low-Power Register
906
0x024
UARTIBRD
RW
0x0000.0000
UART Integer Baud-Rate Divisor
907
0x028
UARTFBRD
RW
0x0000.0000
UART Fractional Baud-Rate Divisor
908
0x02C
UARTLCRH
RW
0x0000.0000
UART Line Control
909
0x030
UARTCTL
RW
0x0000.0300
UART Control
911
0x034
UARTIFLS
RW
0x0000.0012
UART Interrupt FIFO Level Select
915
0x038
UARTIM
RW
0x0000.0000
UART Interrupt Mask
917
0x03C
UARTRIS
RO
0x0000.0000
UART Raw Interrupt Status
920
0x040
UARTMIS
RO
0x0000.0000
UART Masked Interrupt Status
923
0x044
UARTICR
W1C
0x0000.0000
UART Interrupt Clear
926
0x048
UARTDMACTL
RW
0x0000.0000
UART DMA Control
928
0x0A4
UART9BITADDR
RW
0x0000.0000
UART 9-Bit Self Address
929
0x0A8
UART9BITAMASK
RW
0x0000.00FF
UART 9-Bit Self Address Mask
930
0xFC0
UARTPP
RO
0x0000.0003
UART Peripheral Properties
931
0xFC8
UARTCC
RW
0x0000.0000
UART Clock Configuration
932
0xFD0
UARTPeriphID4
RO
0x0000.0000
UART Peripheral Identification 4
933
0xFD4
UARTPeriphID5
RO
0x0000.0000
UART Peripheral Identification 5
934
0xFD8
UARTPeriphID6
RO
0x0000.0000
UART Peripheral Identification 6
935
0xFDC
UARTPeriphID7
RO
0x0000.0000
UART Peripheral Identification 7
936
0xFE0
UARTPeriphID0
RO
0x0000.0060
UART Peripheral Identification 0
937
0xFE4
UARTPeriphID1
RO
0x0000.0000
UART Peripheral Identification 1
938
0xFE8
UARTPeriphID2
RO
0x0000.0018
UART Peripheral Identification 2
939
0xFEC
UARTPeriphID3
RO
0x0000.0001
UART Peripheral Identification 3
940
0xFF0
UARTPCellID0
RO
0x0000.000D
UART PrimeCell Identification 0
941
0xFF4
UARTPCellID1
RO
0x0000.00F0
UART PrimeCell Identification 1
942
0xFF8
UARTPCellID2
RO
0x0000.0005
UART PrimeCell Identification 2
943
0xFFC
UARTPCellID3
RO
0x0000.00B1
UART PrimeCell Identification 3
944
Offset
Name
0x000
896
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Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
14.6
Register Descriptions
The remainder of this section lists and describes the UART registers, in numerical order by address
offset.
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Universal Asynchronous Receivers/Transmitters (UARTs)
Register 1: UART Data (UARTDR), offset 0x000
Important: This register is read-sensitive. See the register description for details.
This register is the data register (the interface to the FIFOs).
For transmitted data, if the FIFO is enabled, data written to this location is pushed onto the transmit
FIFO. If the FIFO is disabled, data is stored in the transmitter holding register (the bottom word of
the transmit FIFO). A write to this register initiates a transmission from the UART.
For received data, if the FIFO is enabled, the data byte and the 4-bit status (break, frame, parity,
and overrun) is pushed onto the 12-bit wide receive FIFO. If the FIFO is disabled, the data byte and
status are stored in the receiving holding register (the bottom word of the receive FIFO). The received
data can be retrieved by reading this register.
UART Data (UARTDR)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
UART3 base: 0x4000.F000
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0x000
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
15
14
13
12
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
11
10
9
8
OE
BE
PE
FE
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:12
reserved
RO
0x0000.0
11
OE
RO
0
DATA
RW
0
RW
0
RW
0
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
UART Overrun Error
Value Description
0
No data has been lost due to a FIFO overrun.
1
New data was received when the FIFO was full, resulting in
data loss.
898
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Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Bit/Field
Name
Type
Reset
10
BE
RO
0
Description
UART Break Error
Value Description
0
No break condition has occurred
1
A break condition has been detected, indicating that the receive
data input was held Low for longer than a full-word transmission
time (defined as start, data, parity, and stop bits).
In FIFO mode, this error is associated with the character at the top of
the FIFO. When a break occurs, only one 0 character is loaded into the
FIFO. The next character is only enabled after the received data input
goes to a 1 (marking state), and the next valid start bit is received.
9
PE
RO
0
UART Parity Error
Value Description
0
No parity error has occurred
1
The parity of the received data character does not match the
parity defined by bits 2 and 7 of the UARTLCRH register.
In FIFO mode, this error is associated with the character at the top of
the FIFO.
8
FE
RO
0
UART Framing Error
Value Description
7:0
DATA
RW
0x00
0
No framing error has occurred
1
The received character does not have a valid stop bit (a valid
stop bit is 1).
Data Transmitted or Received
Data that is to be transmitted via the UART is written to this field.
When read, this field contains the data that was received by the UART.
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Universal Asynchronous Receivers/Transmitters (UARTs)
Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset
0x004
The UARTRSR/UARTECR register is the receive status register/error clear register.
In addition to the UARTDR register, receive status can also be read from the UARTRSR register.
If the status is read from this register, then the status information corresponds to the entry read from
UARTDR prior to reading UARTRSR. The status information for overrun is set immediately when
an overrun condition occurs.
The UARTRSR register cannot be written.
A write of any value to the UARTECR register clears the framing, parity, break, and overrun errors.
All the bits are cleared on reset.
Read-Only Status Register
UART Receive Status/Error Clear (UARTRSR/UARTECR)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
UART3 base: 0x4000.F000
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0x004
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
OE
BE
PE
FE
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:4
reserved
RO
0x0000.000
3
OE
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
UART Overrun Error
Value Description
0
No data has been lost due to a FIFO overrun.
1
New data was received when the FIFO was full, resulting in
data loss.
This bit is cleared by a write to UARTECR.
The FIFO contents remain valid because no further data is written when
the FIFO is full, only the contents of the shift register are overwritten.
The CPU must read the data in order to empty the FIFO.
900
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Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Bit/Field
Name
Type
Reset
2
BE
RO
0
Description
UART Break Error
Value Description
0
No break condition has occurred
1
A break condition has been detected, indicating that the receive
data input was held Low for longer than a full-word transmission
time (defined as start, data, parity, and stop bits).
This bit is cleared to 0 by a write to UARTECR.
In FIFO mode, this error is associated with the character at the top of
the FIFO. When a break occurs, only one 0 character is loaded into the
FIFO. The next character is only enabled after the receive data input
goes to a 1 (marking state) and the next valid start bit is received.
1
PE
RO
0
UART Parity Error
Value Description
0
No parity error has occurred
1
The parity of the received data character does not match the
parity defined by bits 2 and 7 of the UARTLCRH register.
This bit is cleared to 0 by a write to UARTECR.
0
FE
RO
0
UART Framing Error
Value Description
0
No framing error has occurred
1
The received character does not have a valid stop bit (a valid
stop bit is 1).
This bit is cleared to 0 by a write to UARTECR.
In FIFO mode, this error is associated with the character at the top of
the FIFO.
Write-Only Error Clear Register
UART Receive Status/Error Clear (UARTRSR/UARTECR)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
UART3 base: 0x4000.F000
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0x004
Type WO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
WO
0
WO
0
WO
0
WO
0
3
2
1
0
WO
0
WO
0
WO
0
WO
0
reserved
Type
Reset
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
WO
0
WO
0
WO
0
WO
0
WO
0
DATA
WO
0
WO
0
WO
0
WO
0
WO
0
June 12, 2014
WO
0
WO
0
901
Texas Instruments-Production Data
Universal Asynchronous Receivers/Transmitters (UARTs)
Bit/Field
Name
Type
Reset
31:8
reserved
WO
0x0000.00
7:0
DATA
WO
0x00
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Error Clear
A write to this register of any data clears the framing, parity, break, and
overrun flags.
902
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Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Register 3: UART Flag (UARTFR), offset 0x018
The UARTFR register is the flag register. After reset, the TXFF, RXFF, and BUSY bits are 0, and
TXFE and RXFE bits are 1. The RI, DCD, DSR and CTS bits indicate the modem flow control and
status. Note that the modem bits are only implemented on UART1 and are reserved on UART0 and
UART2.
UART Flag (UARTFR)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
UART3 base: 0x4000.F000
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0x018
Type RO, reset 0x0000.0090
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
15
14
13
RO
0
RO
0
RO
0
RO
0
12
11
10
9
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:9
reserved
RO
0x0000.00
8
RI
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RI
TXFE
RXFF
TXFF
RXFE
BUSY
DCD
DSR
CTS
RO
0
RO
1
RO
0
RO
0
RO
1
RO
0
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Ring Indicator
Value Description
0
The U1RI signal is not asserted.
1
The U1RI signal is asserted.
This bit is implemented only on UART1 and is reserved for UART0 and
UART2.
7
TXFE
RO
1
UART Transmit FIFO Empty
The meaning of this bit depends on the state of the FEN bit in the
UARTLCRH register.
Value Description
0
The transmitter has data to transmit.
1
If the FIFO is disabled (FEN is 0), the transmit holding register
is empty.
If the FIFO is enabled (FEN is 1), the transmit FIFO is empty.
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Universal Asynchronous Receivers/Transmitters (UARTs)
Bit/Field
Name
Type
Reset
6
RXFF
RO
0
Description
UART Receive FIFO Full
The meaning of this bit depends on the state of the FEN bit in the
UARTLCRH register.
Value Description
0
The receiver can receive data.
1
If the FIFO is disabled (FEN is 0), the receive holding register
is full.
If the FIFO is enabled (FEN is 1), the receive FIFO is full.
5
TXFF
RO
0
UART Transmit FIFO Full
The meaning of this bit depends on the state of the FEN bit in the
UARTLCRH register.
Value Description
0
The transmitter is not full.
1
If the FIFO is disabled (FEN is 0), the transmit holding register
is full.
If the FIFO is enabled (FEN is 1), the transmit FIFO is full.
4
RXFE
RO
1
UART Receive FIFO Empty
The meaning of this bit depends on the state of the FEN bit in the
UARTLCRH register.
Value Description
0
The receiver is not empty.
1
If the FIFO is disabled (FEN is 0), the receive holding register
is empty.
If the FIFO is enabled (FEN is 1), the receive FIFO is empty.
3
BUSY
RO
0
UART Busy
Value Description
0
The UART is not busy.
1
The UART is busy transmitting data. This bit remains set until
the complete byte, including all stop bits, has been sent from
the shift register.
This bit is set as soon as the transmit FIFO becomes non-empty
(regardless of whether UART is enabled).
2
DCD
RO
0
Data Carrier Detect
Value Description
0
The U1DCD signal is not asserted.
1
The U1DCD signal is asserted.
This bit is implemented only on UART1 and is reserved for UART0 and
UART2.
904
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Bit/Field
Name
Type
Reset
1
DSR
RO
0
Description
Data Set Ready
Value Description
0
The U1DSR signal is not asserted.
1
The U1DSR signal is asserted.
This bit is implemented only on UART1 and is reserved for UART0 and
UART2.
0
CTS
RO
0
Clear To Send
Value Description
0
The U1CTS signal is not asserted.
1
The U1CTS signal is asserted.
This bit is implemented only on UART1 and is reserved for UART0 and
UART2.
June 12, 2014
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Texas Instruments-Production Data
Universal Asynchronous Receivers/Transmitters (UARTs)
Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020
The UARTILPR register stores the 8-bit low-power counter divisor value used to derive the low-power
SIR pulse width clock by dividing down the system clock (SysClk). All the bits are cleared when
reset.
The internal IrLPBaud16 clock is generated by dividing down SysClk according to the low-power
divisor value written to UARTILPR. The duration of SIR pulses generated when low-power mode
is enabled is three times the period of the IrLPBaud16 clock. The low-power divisor value is
calculated as follows:
ILPDVSR = SysClk / FIrLPBaud16
where FIrLPBaud16 is nominally 1.8432 MHz.
Because the IrLPBaud16 clock is used to sample transmitted data irrespective of mode, the
ILPDVSR field must be programmed in both low power and normal mode,such that 1.42 MHz <
FIrLPBaud16 < 2.12 MHz, resulting in a low-power pulse duration of 1.41–2.11 μs (three times the
period of IrLPBaud16). The minimum frequency of IrLPBaud16 ensures that pulses less than
one period of IrLPBaud16 are rejected, but pulses greater than 1.4 μs are accepted as valid pulses.
Note:
Zero is an illegal value. Programming a zero value results in no IrLPBaud16 pulses being
generated.
UART IrDA Low-Power Register (UARTILPR)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
UART3 base: 0x4000.F000
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0x020
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
reserved
Type
Reset
ILPDVSR
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
ILPDVSR
RW
0x00
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
IrDA Low-Power Divisor
This field contains the 8-bit low-power divisor value.
906
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Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024
The UARTIBRD register is the integer part of the baud-rate divisor value. All the bits are cleared
on reset. The minimum possible divide ratio is 1 (when UARTIBRD=0), in which case the UARTFBRD
register is ignored. When changing the UARTIBRD register, the new value does not take effect until
transmission/reception of the current character is complete. Any changes to the baud-rate divisor
must be followed by a write to the UARTLCRH register. See “Baud-Rate Generation” on page 887
for configuration details.
UART Integer Baud-Rate Divisor (UARTIBRD)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
UART3 base: 0x4000.F000
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0x024
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
DIVINT
Type
Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bit/Field
Name
Type
Reset
Description
31:16
reserved
RO
0x0000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:0
DIVINT
RW
0x0000
Integer Baud-Rate Divisor
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Texas Instruments-Production Data
Universal Asynchronous Receivers/Transmitters (UARTs)
Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028
The UARTFBRD register is the fractional part of the baud-rate divisor value. All the bits are cleared
on reset. When changing the UARTFBRD register, the new value does not take effect until
transmission/reception of the current character is complete. Any changes to the baud-rate divisor
must be followed by a write to the UARTLCRH register. See “Baud-Rate Generation” on page 887
for configuration details.
UART Fractional Baud-Rate Divisor (UARTFBRD)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
UART3 base: 0x4000.F000
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0x028
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RW
0
RW
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
DIVFRAC
RO
0
Bit/Field
Name
Type
Reset
31:6
reserved
RO
0x0000.000
5:0
DIVFRAC
RW
0x0
RO
0
RO
0
RO
0
RW
0
RW
0
RW
0
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Fractional Baud-Rate Divisor
908
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Register 7: UART Line Control (UARTLCRH), offset 0x02C
The UARTLCRH register is the line control register. Serial parameters such as data length, parity,
and stop bit selection are implemented in this register.
When updating the baud-rate divisor (UARTIBRD and/or UARTIFRD), the UARTLCRH register
must also be written. The write strobe for the baud-rate divisor registers is tied to the UARTLCRH
register.
UART Line Control (UARTLCRH)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
UART3 base: 0x4000.F000
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0x02C
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
FEN
STP2
EPS
PEN
BRK
RW
0
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
reserved
Type
Reset
SPS
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7
SPS
RW
0
RW
0
WLEN
RW
0
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
UART Stick Parity Select
When bits 1, 2, and 7 of UARTLCRH are set, the parity bit is transmitted
and checked as a 0. When bits 1 and 7 are set and 2 is cleared, the
parity bit is transmitted and checked as a 1.
When this bit is cleared, stick parity is disabled.
6:5
WLEN
RW
0x0
UART Word Length
The bits indicate the number of data bits transmitted or received in a
frame as follows:
Value Description
0x0
5 bits (default)
0x1
6 bits
0x2
7 bits
0x3
8 bits
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Texas Instruments-Production Data
Universal Asynchronous Receivers/Transmitters (UARTs)
Bit/Field
Name
Type
Reset
4
FEN
RW
0
Description
UART Enable FIFOs
Value Description
3
STP2
RW
0
0
The FIFOs are disabled (Character mode). The FIFOs become
1-byte-deep holding registers.
1
The transmit and receive FIFO buffers are enabled (FIFO mode).
UART Two Stop Bits Select
Value Description
0
One stop bit is transmitted at the end of a frame.
1
Two stop bits are transmitted at the end of a frame. The receive
logic does not check for two stop bits being received.
When in 7816 smartcard mode (the SMART bit is set in the
UARTCTL register), the number of stop bits is forced to 2.
2
EPS
RW
0
UART Even Parity Select
Value Description
0
Odd parity is performed, which checks for an odd number of 1s.
1
Even parity generation and checking is performed during
transmission and reception, which checks for an even number
of 1s in data and parity bits.
This bit has no effect when parity is disabled by the PEN bit.
1
PEN
RW
0
UART Parity Enable
Value Description
0
BRK
RW
0
0
Parity is disabled and no parity bit is added to the data frame.
1
Parity checking and generation is enabled.
UART Send Break
Value Description
0
Normal use.
1
A Low level is continually output on the UnTx signal, after
completing transmission of the current character. For the proper
execution of the break command, software must set this bit for
at least two frames (character periods).
910
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Register 8: UART Control (UARTCTL), offset 0x030
The UARTCTL register is the control register. All the bits are cleared on reset except for the Transmit
Enable (TXE) and Receive Enable (RXE) bits, which are set.
To enable the UART module, the UARTEN bit must be set. If software requires a configuration change
in the module, the UARTEN bit must be cleared before the configuration changes are written. If the
UART is disabled during a transmit or receive operation, the current transaction is completed prior
to the UART stopping.
Note that bits [15:14,11:10] are only implemented on UART1. These bits are reserved on UART0
and UART2.
Note:
The UARTCTL register should not be changed while the UART is enabled or else the results
are unpredictable. The following sequence is recommended for making changes to the
UARTCTL register.
1. Disable the UART.
2. Wait for the end of transmission or reception of the current character.
3. Flush the transmit FIFO by clearing bit 4 (FEN) in the line control register (UARTLCRH).
4. Reprogram the control register.
5. Enable the UART.
UART Control (UARTCTL)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
UART3 base: 0x4000.F000
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0x030
Type RW, reset 0x0000.0300
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
CTSEN
RTSEN
RTS
DTR
RW
0
RW
0
RW
0
RW
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RXE
TXE
LBE
reserved
HSE
EOT
SMART
SIRLP
SIREN
UARTEN
RW
1
RW
1
RW
0
RO
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
Type
Reset
reserved
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:16
reserved
RO
0x0000
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
June 12, 2014
911
Texas Instruments-Production Data
Universal Asynchronous Receivers/Transmitters (UARTs)
Bit/Field
Name
Type
Reset
15
CTSEN
RW
0
Description
Enable Clear To Send
Value Description
0
CTS hardware flow control is disabled.
1
CTS hardware flow control is enabled. Data is only transmitted
when the U1CTS signal is asserted.
This bit is implemented only on UART1 and is reserved for UART0 and
UART2.
14
RTSEN
RW
0
Enable Request to Send
Value Description
0
RTS hardware flow control is disabled.
1
RTS hardware flow control is enabled. Data is only requested
(by asserting U1RTS) when the receive FIFO has available
entries.
This bit is implemented only on UART1 and is reserved for UART0 and
UART2.
13:12
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
11
RTS
RW
0
Request to Send
When RTSEN is clear, the status of this bit is reflected on the U1RTS
signal. If RTSEN is set, this bit is ignored on a write and should be ignored
on read.
This bit is implemented only on UART1 and is reserved for UART0 and
UART2.
10
DTR
RW
0
Data Terminal Ready
This bit sets the state of the U1DTR output.
This bit is implemented only on UART1 and is reserved for UART0 and
UART2.
9
RXE
RW
1
UART Receive Enable
Value Description
0
The receive section of the UART is disabled.
1
The receive section of the UART is enabled.
If the UART is disabled in the middle of a receive, it completes the current
character before stopping.
Note:
To enable reception, the UARTEN bit must also be set.
912
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Bit/Field
Name
Type
Reset
8
TXE
RW
1
Description
UART Transmit Enable
Value Description
0
The transmit section of the UART is disabled.
1
The transmit section of the UART is enabled.
If the UART is disabled in the middle of a transmission, it completes the
current character before stopping.
Note:
7
LBE
RW
0
To enable transmission, the UARTEN bit must also be set.
UART Loop Back Enable
Value Description
0
Normal operation.
1
The UnTx path is fed through the UnRx path.
6
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5
HSE
RW
0
High-Speed Enable
Value Description
0
The UART is clocked using the system clock divided by 16.
1
The UART is clocked using the system clock divided by 8.
Note:
System clock used is also dependent on the baud-rate divisor
configuration (see page 907) and page 908).
The state of this bit has no effect on clock generation in ISO
7816 smart card mode (the SMART bit is set).
4
EOT
RW
0
End of Transmission
This bit determines the behavior of the TXRIS bit in the UARTRIS
register.
Value Description
0
The TXRIS bit is set when the transmit FIFO condition specified
in UARTIFLS is met.
1
The TXRIS bit is set only after all transmitted data, including
stop bits, have cleared the serializer.
June 12, 2014
913
Texas Instruments-Production Data
Universal Asynchronous Receivers/Transmitters (UARTs)
Bit/Field
Name
Type
Reset
3
SMART
RW
0
Description
ISO 7816 Smart Card Support
Value Description
0
Normal operation.
1
The UART operates in Smart Card mode.
The application must ensure that it sets 8-bit word length (WLEN set to
0x3) and even parity (PEN set to 1, EPS set to 1, SPS set to 0) in
UARTLCRH when using ISO 7816 mode.
In this mode, the value of the STP2 bit in UARTLCRH is ignored and
the number of stop bits is forced to 2. Note that the UART does not
support automatic retransmission on parity errors. If a parity error is
detected on transmission, all further transmit operations are aborted
and software must handle retransmission of the affected byte or
message.
2
SIRLP
RW
0
UART SIR Low-Power Mode
This bit selects the IrDA encoding mode.
Value Description
0
Low-level bits are transmitted as an active High pulse with a
width of 3/16th of the bit period.
1
The UART operates in SIR Low-Power mode. Low-level bits
are transmitted with a pulse width which is 3 times the period
of the IrLPBaud16 input signal, regardless of the selected bit
rate.
Setting this bit uses less power, but might reduce transmission distances.
See page 906 for more information.
1
SIREN
RW
0
UART SIR Enable
Value Description
0
UARTEN
RW
0
0
Normal operation.
1
The IrDA SIR block is enabled, and the UART will transmit and
receive data using SIR protocol.
UART Enable
Value Description
0
The UART is disabled.
1
The UART is enabled.
If the UART is disabled in the middle of transmission or reception, it
completes the current character before stopping.
914
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Register 9: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034
The UARTIFLS register is the interrupt FIFO level select register. You can use this register to define
the FIFO level at which the TXRIS and RXRIS bits in the UARTRIS register are triggered.
The interrupts are generated based on a transition through a level rather than being based on the
level. That is, the interrupts are generated when the fill level progresses through the trigger level.
For example, if the receive trigger level is set to the half-way mark, the interrupt is triggered as the
module is receiving the 9th character.
Out of reset, the TXIFLSEL and RXIFLSEL bits are configured so that the FIFOs trigger an interrupt
at the half-way mark.
UART Interrupt FIFO Level Select (UARTIFLS)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
UART3 base: 0x4000.F000
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0x034
Type RW, reset 0x0000.0012
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
4
3
2
1
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RXIFLSEL
RO
0
Bit/Field
Name
Type
Reset
31:6
reserved
RO
0x0000.00
5:3
RXIFLSEL
RW
0x2
RO
0
RO
0
RO
0
RW
0
RW
1
TXIFLSEL
RW
0
RW
0
RW
1
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
UART Receive Interrupt FIFO Level Select
The trigger points for the receive interrupt are as follows:
Value
Description
0x0
RX FIFO ≥ ⅛ full
0x1
RX FIFO ≥ ¼ full
0x2
RX FIFO ≥ ½ full (default)
0x3
RX FIFO ≥ ¾ full
0x4
RX FIFO ≥ ⅞ full
0x5-0x7 Reserved
June 12, 2014
915
Texas Instruments-Production Data
Universal Asynchronous Receivers/Transmitters (UARTs)
Bit/Field
Name
Type
Reset
2:0
TXIFLSEL
RW
0x2
Description
UART Transmit Interrupt FIFO Level Select
The trigger points for the transmit interrupt are as follows:
Value
Description
0x0
TX FIFO ≤ ⅞ empty
0x1
TX FIFO ≤ ¾ empty
0x2
TX FIFO ≤ ½ empty (default)
0x3
TX FIFO ≤ ¼ empty
0x4
TX FIFO ≤ ⅛ empty
0x5-0x7 Reserved
Note:
If the EOT bit in UARTCTL is set (see page 911), the transmit
interrupt is generated once the FIFO is completely empty and
all data including stop bits have left the transmit serializer. In
this case, the setting of TXIFLSEL is ignored.
916
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Register 10: UART Interrupt Mask (UARTIM), offset 0x038
The UARTIM register is the interrupt mask set/clear register.
On a read, this register gives the current value of the mask on the relevant interrupt. Setting a bit
allows the corresponding raw interrupt signal to be routed to the interrupt controller. Clearing a bit
prevents the raw interrupt signal from being sent to the interrupt controller.
Note that bits [3:0] are only implemented on UART1. These bits are reserved on UART0 and UART2.
UART Interrupt Mask (UARTIM)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
UART3 base: 0x4000.F000
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0x038
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
15
RO
0
RO
0
14
13
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
12
11
10
9
8
7
6
5
4
3
2
1
0
9BITIM
reserved
OEIM
BEIM
PEIM
FEIM
RTIM
TXIM
RXIM
DSRIM
DCDIM
CTSIM
RIIM
RW
0
RO
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:13
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
12
9BITIM
RW
0
9-Bit Mode Interrupt Mask
Value Description
0
The 9BITRIS interrupt is suppressed and not sent to the
interrupt controller.
1
An interrupt is sent to the interrupt controller when the 9BITRIS
bit in the UARTRIS register is set.
11
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
10
OEIM
RW
0
UART Overrun Error Interrupt Mask
Value Description
0
The OERIS interrupt is suppressed and not sent to the interrupt
controller.
1
An interrupt is sent to the interrupt controller when the OERIS
bit in the UARTRIS register is set.
June 12, 2014
917
Texas Instruments-Production Data
Universal Asynchronous Receivers/Transmitters (UARTs)
Bit/Field
Name
Type
Reset
9
BEIM
RW
0
Description
UART Break Error Interrupt Mask
Value Description
8
PEIM
RW
0
0
The BERIS interrupt is suppressed and not sent to the interrupt
controller.
1
An interrupt is sent to the interrupt controller when the BERIS
bit in the UARTRIS register is set.
UART Parity Error Interrupt Mask
Value Description
7
FEIM
RW
0
0
The PERIS interrupt is suppressed and not sent to the interrupt
controller.
1
An interrupt is sent to the interrupt controller when the PERIS
bit in the UARTRIS register is set.
UART Framing Error Interrupt Mask
Value Description
6
RTIM
RW
0
0
The FERIS interrupt is suppressed and not sent to the interrupt
controller.
1
An interrupt is sent to the interrupt controller when the FERIS
bit in the UARTRIS register is set.
UART Receive Time-Out Interrupt Mask
Value Description
5
TXIM
RW
0
0
The RTRIS interrupt is suppressed and not sent to the interrupt
controller.
1
An interrupt is sent to the interrupt controller when the RTRIS
bit in the UARTRIS register is set.
UART Transmit Interrupt Mask
Value Description
4
RXIM
RW
0
0
The TXRIS interrupt is suppressed and not sent to the interrupt
controller.
1
An interrupt is sent to the interrupt controller when the TXRIS
bit in the UARTRIS register is set.
UART Receive Interrupt Mask
Value Description
0
The RXRIS interrupt is suppressed and not sent to the interrupt
controller.
1
An interrupt is sent to the interrupt controller when the RXRIS
bit in the UARTRIS register is set.
918
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Bit/Field
Name
Type
Reset
3
DSRIM
RW
0
Description
UART Data Set Ready Modem Interrupt Mask
Value Description
0
The DSRRIS interrupt is suppressed and not sent to the interrupt
controller.
1
An interrupt is sent to the interrupt controller when the DSRRIS
bit in the UARTRIS register is set.
This bit is implemented only on UART1 and is reserved for UART0 and
UART2.
2
DCDIM
RW
0
UART Data Carrier Detect Modem Interrupt Mask
Value Description
0
The DCDRIS interrupt is suppressed and not sent to the interrupt
controller.
1
An interrupt is sent to the interrupt controller when the DCDRIS
bit in the UARTRIS register is set.
This bit is implemented only on UART1 and is reserved for UART0 and
UART2.
1
CTSIM
RW
0
UART Clear to Send Modem Interrupt Mask
Value Description
0
The CTSRIS interrupt is suppressed and not sent to the interrupt
controller.
1
An interrupt is sent to the interrupt controller when the CTSRIS
bit in the UARTRIS register is set.
This bit is implemented only on UART1 and is reserved for UART0 and
UART2.
0
RIIM
RW
0
UART Ring Indicator Modem Interrupt Mask
Value Description
0
The RIRIS interrupt is suppressed and not sent to the interrupt
controller.
1
An interrupt is sent to the interrupt controller when the RIRIS
bit in the UARTRIS register is set.
This bit is implemented only on UART1 and is reserved for UART0 and
UART2.
June 12, 2014
919
Texas Instruments-Production Data
Universal Asynchronous Receivers/Transmitters (UARTs)
Register 11: UART Raw Interrupt Status (UARTRIS), offset 0x03C
The UARTRIS register is the raw interrupt status register. On a read, this register gives the current
raw status value of the corresponding interrupt. A write has no effect.
Note that bits [3:0] are only implemented on UART1. These bits are reserved on UART0 and UART2.
UART Raw Interrupt Status (UARTRIS)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
UART3 base: 0x4000.F000
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0x03C
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
9BITRIS
reserved
OERIS
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
BERIS
PERIS
FERIS
RTRIS
TXRIS
RXRIS
DSRRIS
DCDRIS
CTSRIS
RIRIS
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:13
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
12
9BITRIS
RO
0
9-Bit Mode Raw Interrupt Status
Value Description
0
No interrupt
1
A receive address match has occurred.
This bit is cleared by writing a 1 to the 9BITIC bit in the UARTICR
register.
11
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
10
OERIS
RO
0
UART Overrun Error Raw Interrupt Status
Value Description
0
No interrupt
1
An overrun error has occurred.
This bit is cleared by writing a 1 to the OEIC bit in the UARTICR register.
920
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Bit/Field
Name
Type
Reset
9
BERIS
RO
0
Description
UART Break Error Raw Interrupt Status
Value Description
0
No interrupt
1
A break error has occurred.
This bit is cleared by writing a 1 to the BEIC bit in the UARTICR register.
8
PERIS
RO
0
UART Parity Error Raw Interrupt Status
Value Description
0
No interrupt
1
A parity error has occurred.
This bit is cleared by writing a 1 to the PEIC bit in the UARTICR register.
7
FERIS
RO
0
UART Framing Error Raw Interrupt Status
Value Description
0
No interrupt
1
A framing error has occurred.
This bit is cleared by writing a 1 to the FEIC bit in the UARTICR register.
6
RTRIS
RO
0
UART Receive Time-Out Raw Interrupt Status
Value Description
0
No interrupt
1
A receive time out has occurred.
This bit is cleared by writing a 1 to the RTIC bit in the UARTICR register.
For receive timeout, the RTIM bit in the UARTIM register must be set
to see the RTRIS status.
5
TXRIS
RO
0
UART Transmit Raw Interrupt Status
Value Description
0
No interrupt
1
If the EOT bit in the UARTCTL register is clear, the transmit
FIFO level has passed through the condition defined in the
UARTIFLS register.
If the EOT bit is set, the last bit of all transmitted data and flags
has left the serializer.
This bit is cleared by writing a 1 to the TXIC bit in the UARTICR register
or by writing data to the transmit FIFO until it becomes greater than the
trigger level, if the FIFO is enabled, or by writing a single byte if the FIFO
is disabled.
June 12, 2014
921
Texas Instruments-Production Data
Universal Asynchronous Receivers/Transmitters (UARTs)
Bit/Field
Name
Type
Reset
4
RXRIS
RO
0
Description
UART Receive Raw Interrupt Status
Value Description
0
No interrupt
1
The receive FIFO level has passed through the condition defined
in the UARTIFLS register.
This bit is cleared by writing a 1 to the RXIC bit in the UARTICR register
or by reading data from the receive FIFO until it becomes less than the
trigger level, if the FIFO is enabled, or by reading a single byte if the
FIFO is disabled.
3
DSRRIS
RO
0
UART Data Set Ready Modem Raw Interrupt Status
Value Description
0
No interrupt
1
Data Set Ready used for software flow control.
This bit is cleared by writing a 1 to the DSRIC bit in the UARTICR
register.
This bit is implemented only on UART1 and is reserved for UART0 and
UART2.
2
DCDRIS
RO
0
UART Data Carrier Detect Modem Raw Interrupt Status
Value Description
0
No interrupt
1
Data Carrier Detect used for software flow control.
This bit is cleared by writing a 1 to the DCDIC bit in the UARTICR
register.
This bit is implemented only on UART1 and is reserved for UART0 and
UART2.
1
CTSRIS
RO
0
UART Clear to Send Modem Raw Interrupt Status
Value Description
0
No interrupt
1
Clear to Send used for software flow control.
This bit is cleared by writing a 1 to the CTSIC bit in the UARTICR
register.
This bit is implemented only on UART1 and is reserved for UART0 and
UART2.
0
RIRIS
RO
0
UART Ring Indicator Modem Raw Interrupt Status
Value Description
0
No interrupt
1
Ring Indicator used for software flow control.
This bit is cleared by writing a 1 to the RIIC bit in the UARTICR register.
This bit is implemented only on UART1 and is reserved for UART0 and
UART2.
922
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040
The UARTMIS register is the masked interrupt status register. On a read, this register gives the
current masked status value of the corresponding interrupt. A write has no effect.
Note that bits [3:0] are only implemented on UART1. These bits are reserved on UART0 and UART2.
UART Masked Interrupt Status (UARTMIS)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
UART3 base: 0x4000.F000
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0x040
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
9BITMIS
reserved
OEMIS
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
BEMIS
PEMIS
FEMIS
RTMIS
TXMIS
RXMIS
CTSMIS
RIMIS
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
RO
0
RO
0
DSRMIS DCDMIS
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:13
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
12
9BITMIS
RO
0
9-Bit Mode Masked Interrupt Status
Value Description
0
An interrupt has not occurred or is masked.
1
An unmasked interrupt was signaled due to a receive address
match.
This bit is cleared by writing a 1 to the 9BITIC bit in the UARTICR
register.
11
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
10
OEMIS
RO
0
UART Overrun Error Masked Interrupt Status
Value Description
0
An interrupt has not occurred or is masked.
1
An unmasked interrupt was signaled due to an overrun error.
This bit is cleared by writing a 1 to the OEIC bit in the UARTICR register.
June 12, 2014
923
Texas Instruments-Production Data
Universal Asynchronous Receivers/Transmitters (UARTs)
Bit/Field
Name
Type
Reset
9
BEMIS
RO
0
Description
UART Break Error Masked Interrupt Status
Value Description
0
An interrupt has not occurred or is masked.
1
An unmasked interrupt was signaled due to a break error.
This bit is cleared by writing a 1 to the BEIC bit in the UARTICR register.
8
PEMIS
RO
0
UART Parity Error Masked Interrupt Status
Value Description
0
An interrupt has not occurred or is masked.
1
An unmasked interrupt was signaled due to a parity error.
This bit is cleared by writing a 1 to the PEIC bit in the UARTICR register.
7
FEMIS
RO
0
UART Framing Error Masked Interrupt Status
Value Description
0
An interrupt has not occurred or is masked.
1
An unmasked interrupt was signaled due to a framing error.
This bit is cleared by writing a 1 to the FEIC bit in the UARTICR register.
6
RTMIS
RO
0
UART Receive Time-Out Masked Interrupt Status
Value Description
0
An interrupt has not occurred or is masked.
1
An unmasked interrupt was signaled due to a receive time out.
This bit is cleared by writing a 1 to the RTIC bit in the UARTICR register.
For receive timeout, the RTIM bit in the UARTIM register must be set
to see the RTMIS status.
5
TXMIS
RO
0
UART Transmit Masked Interrupt Status
Value Description
0
An interrupt has not occurred or is masked.
1
An unmasked interrupt was signaled due to passing through
the specified transmit FIFO level (if the EOT bit is clear) or due
to the transmission of the last data bit (if the EOT bit is set).
This bit is cleared by writing a 1 to the TXIC bit in the UARTICR register
or by writing data to the transmit FIFO until it becomes greater than the
trigger level, if the FIFO is enabled, or by writing a single byte if the FIFO
is disabled.
924
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Bit/Field
Name
Type
Reset
4
RXMIS
RO
0
Description
UART Receive Masked Interrupt Status
Value Description
0
An interrupt has not occurred or is masked.
1
An unmasked interrupt was signaled due to passing through
the specified receive FIFO level.
This bit is cleared by writing a 1 to the RXIC bit in the UARTICR register
or by reading data from the receive FIFO until it becomes less than the
trigger level, if the FIFO is enabled, or by reading a single byte if the
FIFO is disabled.
3
DSRMIS
RO
0
UART Data Set Ready Modem Masked Interrupt Status
Value Description
0
An interrupt has not occurred or is masked.
1
An unmasked interrupt was signaled due to Data Set Ready.
This bit is cleared by writing a 1 to the DSRIC bit in the UARTICR
register.
This bit is implemented only on UART1 and is reserved for UART0 and
UART2.
2
DCDMIS
RO
0
UART Data Carrier Detect Modem Masked Interrupt Status
Value Description
0
An interrupt has not occurred or is masked.
1
An unmasked interrupt was signaled due to Data Carrier Detect.
This bit is cleared by writing a 1 to the DCDIC bit in the UARTICR
register.
This bit is implemented only on UART1 and is reserved for UART0 and
UART2.
1
CTSMIS
RO
0
UART Clear to Send Modem Masked Interrupt Status
Value Description
0
An interrupt has not occurred or is masked.
1
An unmasked interrupt was signaled due to Clear to Send.
This bit is cleared by writing a 1 to the CTSIC bit in the UARTICR
register.
This bit is implemented only on UART1 and is reserved for UART0 and
UART2.
0
RIMIS
RO
0
UART Ring Indicator Modem Masked Interrupt Status
Value Description
0
An interrupt has not occurred or is masked.
1
An unmasked interrupt was signaled due to Ring Indicator.
This bit is cleared by writing a 1 to the RIIC bit in the UARTICR register.
This bit is implemented only on UART1 and is reserved for UART0 and
UART2.
June 12, 2014
925
Texas Instruments-Production Data
Universal Asynchronous Receivers/Transmitters (UARTs)
Register 13: UART Interrupt Clear (UARTICR), offset 0x044
The UARTICR register is the interrupt clear register. On a write of 1, the corresponding interrupt
(both raw interrupt and masked interrupt, if enabled) is cleared. A write of 0 has no effect.
Note that bits [3:0] are only implemented on UART1. These bits are reserved on UART0 and UART2.
UART Interrupt Clear (UARTICR)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
UART3 base: 0x4000.F000
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0x044
Type W1C, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
9BITIC
reserved
OEIC
RW
0
RO
0
W1C
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
BEIC
PEIC
FEIC
RTIC
TXIC
RXIC
W1C
0
W1C
0
W1C
0
W1C
0
W1C
0
W1C
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
RO
0
RO
0
DSRMIC DCDMIC CTSMIC
W1C
0
W1C
0
W1C
0
RIMIC
W1C
0
Bit/Field
Name
Type
Reset
Description
31:13
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
12
9BITIC
RW
0
9-Bit Mode Interrupt Clear
Writing a 1 to this bit clears the 9BITRIS bit in the UARTRIS register
and the 9BITMIS bit in the UARTMIS register.
11
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
10
OEIC
W1C
0
Overrun Error Interrupt Clear
Writing a 1 to this bit clears the OERIS bit in the UARTRIS register and
the OEMIS bit in the UARTMIS register.
9
BEIC
W1C
0
Break Error Interrupt Clear
Writing a 1 to this bit clears the BERIS bit in the UARTRIS register and
the BEMIS bit in the UARTMIS register.
8
PEIC
W1C
0
Parity Error Interrupt Clear
Writing a 1 to this bit clears the PERIS bit in the UARTRIS register and
the PEMIS bit in the UARTMIS register.
7
FEIC
W1C
0
Framing Error Interrupt Clear
Writing a 1 to this bit clears the FERIS bit in the UARTRIS register and
the FEMIS bit in the UARTMIS register.
926
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Bit/Field
Name
Type
Reset
6
RTIC
W1C
0
Description
Receive Time-Out Interrupt Clear
Writing a 1 to this bit clears the RTRIS bit in the UARTRIS register and
the RTMIS bit in the UARTMIS register.
5
TXIC
W1C
0
Transmit Interrupt Clear
Writing a 1 to this bit clears the TXRIS bit in the UARTRIS register and
the TXMIS bit in the UARTMIS register.
4
RXIC
W1C
0
Receive Interrupt Clear
Writing a 1 to this bit clears the RXRIS bit in the UARTRIS register and
the RXMIS bit in the UARTMIS register.
3
DSRMIC
W1C
0
UART Data Set Ready Modem Interrupt Clear
Writing a 1 to this bit clears the DSRRIS bit in the UARTRIS register
and the DSRMIS bit in the UARTMIS register.
This bit is implemented only on UART1 and is reserved for UART0 and
UART2.
2
DCDMIC
W1C
0
UART Data Carrier Detect Modem Interrupt Clear
Writing a 1 to this bit clears the DCDRIS bit in the UARTRIS register
and the DCDMIS bit in the UARTMIS register.
This bit is implemented only on UART1 and is reserved for UART0 and
UART2.
1
CTSMIC
W1C
0
UART Clear to Send Modem Interrupt Clear
Writing a 1 to this bit clears the CTSRIS bit in the UARTRIS register
and the CTSMIS bit in the UARTMIS register.
This bit is implemented only on UART1 and is reserved for UART0 and
UART2.
0
RIMIC
W1C
0
UART Ring Indicator Modem Interrupt Clear
Writing a 1 to this bit clears the RIRIS bit in the UARTRIS register and
the RIMIS bit in the UARTMIS register.
This bit is implemented only on UART1 and is reserved for UART0 and
UART2.
June 12, 2014
927
Texas Instruments-Production Data
Universal Asynchronous Receivers/Transmitters (UARTs)
Register 14: UART DMA Control (UARTDMACTL), offset 0x048
The UARTDMACTL register is the DMA control register.
UART DMA Control (UARTDMACTL)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
UART3 base: 0x4000.F000
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0x048
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
2
1
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
9
8
7
6
5
4
3
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
31:3
reserved
RO
2
DMAERR
RW
RO
0
Reset
DMAERR TXDMAE RXDMAE
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
RW
0
RW
0
Description
0x00000.000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
DMA on Error
Value Description
1
TXDMAE
RW
0
0
µDMA receive requests are unaffected when a receive error
occurs.
1
µDMA receive requests are automatically disabled when a
receive error occurs.
Transmit DMA Enable
Value Description
0
RXDMAE
RW
0
0
µDMA for the transmit FIFO is disabled.
1
µDMA for the transmit FIFO is enabled.
Receive DMA Enable
Value Description
0
µDMA for the receive FIFO is disabled.
1
µDMA for the receive FIFO is enabled.
928
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Register 15: UART 9-Bit Self Address (UART9BITADDR), offset 0x0A4
The UART9BITADDR register is used to write the specific address that should be matched with the
receiving byte when the 9-bit Address Mask (UART9BITAMASK) is set to 0xFF. This register is
used in conjunction with UART9BITAMASK to form a match for address-byte received.
UART 9-Bit Self Address (UART9BITADDR)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
UART3 base: 0x4000.F000
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0x0A4
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
15
14
13
12
9BITEN
Type
Reset
RW
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
11
10
9
8
7
6
5
4
reserved
RO
0
RO
0
RO
0
ADDR
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:16
reserved
RO
0x0000
15
9BITEN
RW
0
RO
0
RW
0
RW
0
RW
0
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Enable 9-Bit Mode
Value Description
0
9-bit mode is disabled.
1
9-bit mode is enabled.
14:8
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
ADDR
RW
0x00
Self Address for 9-Bit Mode
This field contains the address that should be matched when
UART9BITAMASK is 0xFF.
June 12, 2014
929
Texas Instruments-Production Data
Universal Asynchronous Receivers/Transmitters (UARTs)
Register 16: UART 9-Bit Self Address Mask (UART9BITAMASK), offset 0x0A8
The UART9BITAMASK register is used to enable the address mask for 9-bit mode. The address
bits are masked to create a set of addresses to be matched with the received address byte.
UART 9-Bit Self Address Mask (UART9BITAMASK)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
UART3 base: 0x4000.F000
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0x0A8
Type RW, reset 0x0000.00FF
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RW
1
RW
1
RW
1
RW
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
MASK
RO
0
RO
0
RO
0
RO
0
RW
1
RW
1
RW
1
RW
1
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
MASK
RW
0xFF
Self Address Mask for 9-Bit Mode
This field contains the address mask that creates a set of addresses
that should be matched.
930
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Register 17: UART Peripheral Properties (UARTPP), offset 0xFC0
The UARTPP register provides information regarding the properties of the UART module.
UART Peripheral Properties (UARTPP)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
UART3 base: 0x4000.F000
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0xFC0
Type RO, reset 0x0000.0003
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:2
reserved
RO
0x0000.000
1
NB
RO
0x1
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
1
0
NB
SC
RO
1
RO
1
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
9-Bit Support
Value Description
0
SC
RO
0x1
0
The UART module does not provide support for the transmission
of 9-bit data for RS-485 support.
1
The UART module provides support for the transmission of 9-bit
data for RS-485 support.
Smart Card Support
Value Description
0
The UART module does not provide smart card support.
1
The UART module provides smart card support.
June 12, 2014
931
Texas Instruments-Production Data
Universal Asynchronous Receivers/Transmitters (UARTs)
Register 18: UART Clock Configuration (UARTCC), offset 0xFC8
The UARTCC register controls the baud clock source for the UART module. For more information,
see the section called “Communication Clock Sources” on page 217.
Note:
If the PIOSC is used for the UART baud clock, the system clock frequency must be at least
9 MHz in Run mode.
UART Clock Configuration (UARTCC)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
UART3 base: 0x4000.F000
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0xFC8
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
reserved
Type
Reset
CS
Bit/Field
Name
Type
Reset
31:4
reserved
RO
0x0000.000
3:0
CS
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
UART Baud Clock Source
The following table specifies the source that generates for the UART
baud clock:
Value
Description
0x0
System clock (based on clock source and divisor factor)
0x1-0x4 reserved
0x5
PIOSC
0x5-0xF Reserved
932
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Register 19: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 4 (UARTPeriphID4)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
UART3 base: 0x4000.F000
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0xFD0
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
PID4
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
PID4
RO
0x00
RO
0
RO
0
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
UART Peripheral ID Register [7:0]
Can be used by software to identify the presence of this peripheral.
June 12, 2014
933
Texas Instruments-Production Data
Universal Asynchronous Receivers/Transmitters (UARTs)
Register 20: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 5 (UARTPeriphID5)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
UART3 base: 0x4000.F000
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0xFD4
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
PID5
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
PID5
RO
0x00
RO
0
RO
0
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
UART Peripheral ID Register [15:8]
Can be used by software to identify the presence of this peripheral.
934
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Register 21: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 6 (UARTPeriphID6)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
UART3 base: 0x4000.F000
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0xFD8
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
PID6
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
PID6
RO
0x00
RO
0
RO
0
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
UART Peripheral ID Register [23:16]
Can be used by software to identify the presence of this peripheral.
June 12, 2014
935
Texas Instruments-Production Data
Universal Asynchronous Receivers/Transmitters (UARTs)
Register 22: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 7 (UARTPeriphID7)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
UART3 base: 0x4000.F000
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0xFDC
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
PID7
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
PID7
RO
0x00
RO
0
RO
0
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
UART Peripheral ID Register [31:24]
Can be used by software to identify the presence of this peripheral.
936
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Register 23: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 0 (UARTPeriphID0)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
UART3 base: 0x4000.F000
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0xFE0
Type RO, reset 0x0000.0060
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
PID0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
PID0
RO
0x60
RO
0
RO
0
RO
1
RO
1
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
UART Peripheral ID Register [7:0]
Can be used by software to identify the presence of this peripheral.
June 12, 2014
937
Texas Instruments-Production Data
Universal Asynchronous Receivers/Transmitters (UARTs)
Register 24: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 1 (UARTPeriphID1)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
UART3 base: 0x4000.F000
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0xFE4
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
PID1
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
PID1
RO
0x00
RO
0
RO
0
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
UART Peripheral ID Register [15:8]
Can be used by software to identify the presence of this peripheral.
938
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Register 25: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 2 (UARTPeriphID2)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
UART3 base: 0x4000.F000
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0xFE8
Type RO, reset 0x0000.0018
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
1
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
PID2
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
PID2
RO
0x18
RO
0
RO
0
RO
0
RO
0
RO
1
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
UART Peripheral ID Register [23:16]
Can be used by software to identify the presence of this peripheral.
June 12, 2014
939
Texas Instruments-Production Data
Universal Asynchronous Receivers/Transmitters (UARTs)
Register 26: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 3 (UARTPeriphID3)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
UART3 base: 0x4000.F000
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0xFEC
Type RO, reset 0x0000.0001
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
0
RO
0
RO
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
PID3
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
PID3
RO
0x01
RO
0
RO
0
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
UART Peripheral ID Register [31:24]
Can be used by software to identify the presence of this peripheral.
940
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Register 27: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0
The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset
values.
UART PrimeCell Identification 0 (UARTPCellID0)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
UART3 base: 0x4000.F000
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0xFF0
Type RO, reset 0x0000.000D
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
1
RO
1
RO
0
RO
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
CID0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
CID0
RO
0x0D
RO
0
RO
0
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
UART PrimeCell ID Register [7:0]
Provides software a standard cross-peripheral identification system.
June 12, 2014
941
Texas Instruments-Production Data
Universal Asynchronous Receivers/Transmitters (UARTs)
Register 28: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4
The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset
values.
UART PrimeCell Identification 1 (UARTPCellID1)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
UART3 base: 0x4000.F000
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0xFF4
Type RO, reset 0x0000.00F0
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
CID1
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
CID1
RO
0xF0
RO
0
RO
1
RO
1
RO
1
RO
1
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
UART PrimeCell ID Register [15:8]
Provides software a standard cross-peripheral identification system.
942
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Register 29: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8
The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset
values.
UART PrimeCell Identification 2 (UARTPCellID2)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
UART3 base: 0x4000.F000
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0xFF8
Type RO, reset 0x0000.0005
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
1
RO
0
RO
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
CID2
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
CID2
RO
0x05
RO
0
RO
0
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
UART PrimeCell ID Register [23:16]
Provides software a standard cross-peripheral identification system.
June 12, 2014
943
Texas Instruments-Production Data
Universal Asynchronous Receivers/Transmitters (UARTs)
Register 30: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC
The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset
values.
UART PrimeCell Identification 3 (UARTPCellID3)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
UART3 base: 0x4000.F000
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0xFFC
Type RO, reset 0x0000.00B1
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
0
RO
0
RO
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
CID3
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
CID3
RO
0xB1
RO
0
RO
1
RO
0
RO
1
RO
1
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
UART PrimeCell ID Register [31:24]
Provides software a standard cross-peripheral identification system.
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15
Synchronous Serial Interface (SSI)
The TM4C1237H6PZ microcontroller includes four Synchronous Serial Interface (SSI) modules.
Each SSI module is a master or slave interface for synchronous serial communication with peripheral
devices that have either Freescale SPI, MICROWIRE, or Texas Instruments synchronous serial
interfaces.
The TM4C1237H6PZ SSI modules have the following features:
■ Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments
synchronous serial interfaces
■ Master or slave operation
■ Programmable clock bit rate and prescaler
■ Separate transmit and receive FIFOs, each 16 bits wide and 8 locations deep
■ Programmable data frame size from 4 to 16 bits
■ Internal loopback test mode for diagnostic/debug testing
■ Standard FIFO-based interrupts and End-of-Transmission interrupt
■ Efficient transfers using Micro Direct Memory Access Controller (µDMA)
– Separate channels for transmit and receive
– Receive single request asserted when data is in the FIFO; burst request asserted when FIFO
contains 4 entries
– Transmit single request asserted when there is space in the FIFO; burst request asserted
when four or more entries are available to be written in the FIFO
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15.1
Block Diagram
Figure 15-1. SSI Module Block Diagram
DMA Request
DMA Control
SSIDMACTL
Interrupt
Interrupt Control
TxFIFO
8 x 16
SSIIM
SSIMIS
SSIRIS
SSIICR
.
.
.
Control/Status
SSInTx
SSICR0
SSICR1
SSISR
SSInRx
Transmit/
Receive
Logic
SSIDR
RxFIFO
8 x 16
Clock Prescaler
System Clock
SSInClk
SSInFss
.
.
.
Clock Control
SSICPSR
SSICC
PIOSC
SSI Baud Clock
Identification Registers
SSIPCellID0
SSIPCellID1
SSIPCellID2
SSIPCellID3
15.2
SSIPeriphID0
SSIPeriphID1
SSIPeriphID2
SSIPeriphID3
SSIPeriphID4
SSIPeriphID5
SSIPeriphID6
SSIPeriphID7
Signal Description
The following table lists the external signals of the SSI module and describes the function of each.
Most SSI signals are alternate functions for some GPIO signals and default to be GPIO signals at
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reset. The exceptions to this rule are the SSI0Clk, SSI0Fss, SSI0Rx, and SSI0Tx pins, which
default to the SSI function. The "Pin Mux/Pin Assignment" column in the following table lists the
possible GPIO pin placements for the SSI signals. The AFSEL bit in the GPIO Alternate Function
Select (GPIOAFSEL) register (page 659) should be set to choose the SSI function. The number in
parentheses is the encoding that must be programmed into the PMCn field in the GPIO Port Control
(GPIOPCTL) register (page 677) to assign the SSI signal to the specified GPIO port pin. For more
information on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 634.
Table 15-1. SSI Signals (100LQFP)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
SSI0Clk
28
PA2 (2)
I/O
TTL
SSI module 0 clock
SSI0Fss
29
PA3 (2)
I/O
TTL
SSI module 0 frame signal
SSI0Rx
30
PA4 (2)
I
TTL
SSI module 0 receive
SSI0Tx
31
PA5 (2)
O
TTL
SSI module 0 transmit
SSI1Clk
1
42
PD0 (2)
PF2 (2)
I/O
TTL
SSI module 1 clock.
SSI1Fss
2
43
PD1 (2)
PF3 (2)
I/O
TTL
SSI module 1 frame signal.
SSI1Rx
3
40
PD2 (2)
PF0 (2)
I
TTL
SSI module 1 receive.
SSI1Tx
4
41
PD3 (2)
PF1 (2)
O
TTL
SSI module 1 transmit.
SSI2Clk
79
92
PH4 (2)
PB4 (2)
I/O
TTL
SSI module 2 clock.
SSI2Fss
78
91
PH5 (2)
PB5 (2)
I/O
TTL
SSI module 2 frame signal.
SSI2Rx
77
PH6 (2)
I
TTL
SSI module 2 receive.
SSI2Tx
76
PH7 (2)
O
TTL
SSI module 2 transmit.
SSI3Clk
1
16
49
PD0 (1)
PH0 (2)
PK0 (2)
I/O
TTL
SSI module 3 clock.
SSI3Fss
2
17
48
PD1 (1)
PH1 (2)
PK1 (2)
I/O
TTL
SSI module 3 frame signal.
SSI3Rx
3
18
47
PD2 (1)
PH2 (2)
PK2 (2)
I
TTL
SSI module 3 receive.
SSI3Tx
4
19
46
PD3 (1)
PH3 (2)
PK3 (2)
O
TTL
SSI module 3 transmit.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
15.3
Functional Description
The SSI performs serial-to-parallel conversion on data received from a peripheral device. The CPU
accesses data, control, and status information. The transmit and receive paths are buffered with
internal FIFO memories allowing up to eight 16-bit values to be stored independently in both transmit
and receive modes. The SSI also supports the µDMA interface. The transmit and receive FIFOs
can be programmed as destination/source addresses in the µDMA module. µDMA operation is
enabled by setting the appropriate bit(s) in the SSIDMACTL register (see page 976).
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15.3.1
Bit Rate Generation
The SSI includes a programmable bit rate clock divider and prescaler to generate the serial output
clock. Bit rates are supported to 2 MHz and higher, although maximum bit rate is determined by
peripheral devices.
The serial bit rate is derived by dividing down the input clock (SysClk). The clock is first divided by
an even prescale value CPSDVSR from 2 to 254, which is programmed in the SSI Clock Prescale
(SSICPSR) register (see page 969). The clock is further divided by a value from 1 to 256, which is
1 + SCR, where SCR is the value programmed in the SSI Control 0 (SSICR0) register (see page 962).
The frequency of the output clock SSInClk is defined by:
SSInClk = SysClk / (CPSDVSR * (1 + SCR))
Note:
The System Clock or the PIOSC can be used as the source for the SSInClk. When the
CS field in the SSI Clock Configuration (SSICC) register is configured to 0x5, PIOSC is
selected as the source. For master mode, the system clock or the PIOSC must be at least
two times faster than the SSInClk, with the restriction that SSInClk cannot be faster than
25 MHz. For slave mode, the system clock or the PIOSC must be at least 12 times faster
than the SSInClk, with the restriction that SSInClk cannot be faster than 6.67 MHz.
See “Synchronous Serial Interface (SSI)” on page 1291 to view SSI timing parameters.
15.3.2
FIFO Operation
15.3.2.1
Transmit FIFO
The common transmit FIFO is a 16-bit wide, 8-locations deep, first-in, first-out memory buffer. The
CPU writes data to the FIFO by writing the SSI Data (SSIDR) register (see page 966), and data is
stored in the FIFO until it is read out by the transmission logic.
When configured as a master or a slave, parallel data is written into the transmit FIFO prior to serial
conversion and transmission to the attached slave or master, respectively, through the SSInTx pin.
In slave mode, the SSI transmits data each time the master initiates a transaction. If the transmit
FIFO is empty and the master initiates, the slave transmits the 8th most recent value in the transmit
FIFO. If less than 8 values have been written to the transmit FIFO since the SSI module clock was
enabled using the Rn bit in the RCGCSSI register, then 0 is transmitted. Care should be taken to
ensure that valid data is in the FIFO as needed. The SSI can be configured to generate an interrupt
or a µDMA request when the FIFO is empty.
15.3.2.2
Receive FIFO
The common receive FIFO is a 16-bit wide, 8-locations deep, first-in, first-out memory buffer.
Received data from the serial interface is stored in the buffer until read out by the CPU, which
accesses the read FIFO by reading the SSIDR register.
When configured as a master or slave, serial data received through the SSInRx pin is registered
prior to parallel loading into the attached slave or master receive FIFO, respectively.
15.3.3
Interrupts
The SSI can generate interrupts when the following conditions are observed:
■ Transmit FIFO service (when the transmit FIFO is half full or less)
■ Receive FIFO service (when the receive FIFO is half full or more)
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■ Receive FIFO time-out
■ Receive FIFO overrun
■ End of transmission
■ Receive DMA transfer complete
■ Transmit DMA transfer complete
All of the interrupt events are ORed together before being sent to the interrupt controller, so the SSI
generates a single interrupt request to the controller regardless of the number of active interrupts.
Each of the four individual maskable interrupts can be masked by clearing the appropriate bit in the
SSI Interrupt Mask (SSIIM) register (see page 970). Setting the appropriate mask bit enables the
interrupt.
The individual outputs, along with a combined interrupt output, allow use of either a global interrupt
service routine or modular device drivers to handle interrupts. The transmit and receive dynamic
dataflow interrupts have been separated from the status interrupts so that data can be read or written
in response to the FIFO trigger levels. The status of the individual interrupt sources can be read
from the SSI Raw Interrupt Status (SSIRIS) and SSI Masked Interrupt Status (SSIMIS) registers
(see page 971 and page 973, respectively).
The receive FIFO has a time-out period that is 32 periods at the rate of SSInClk (whether or not
SSInClk is currently active) and is started when the RX FIFO goes from EMPTY to not-EMPTY. If
the RX FIFO is emptied before 32 clocks have passed, the time-out period is reset. As a result, the
ISR should clear the Receive FIFO Time-out Interrupt just after reading out the RX FIFO by writing
a 1 to the RTIC bit in the SSI Interrupt Clear (SSIICR) register. The interrupt should not be cleared
so late that the ISR returns before the interrupt is actually cleared, or the ISR may be re-activated
unnecessarily.
The End-of-Transmission (EOT) interrupt indicates that the data has been transmitted completely
and is only valid for Master mode devices/operations. This interrupt can be used to indicate when
it is safe to turn off the SSI module clock or enter sleep mode. In addition, because transmitted data
and received data complete at exactly the same time, the interrupt can also indicate that read data
is ready immediately, without waiting for the receive FIFO time-out period to complete.
Note:
15.3.4
In Freescale SPI mode only, a condition can be created where an EOT interrupt is generated
for every byte transferred even if the FIFO is full. If the EOT bit has been set to 0 in an
integrated slave SSI and the µDMA has been configured to transfer data from this SSI to
a Master SSI on the device using external loopback, an EOT interrupt is generated by the
SSI slave for every byte even if the FIFO is full.
Frame Formats
Each data frame is between 4 and 16 bits long depending on the size of data programmed and is
transmitted starting with the MSB. There are three basic frame types that can be selected by
programming the FRF bit in the SSICR0 register:
■ Texas Instruments synchronous serial
■ Freescale SPI
■ MICROWIRE
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For all three formats, the serial clock (SSInClk) is held inactive while the SSI is idle, and SSInClk
transitions at the programmed frequency only during active transmission or reception of data. The
idle state of SSInClk is utilized to provide a receive timeout indication that occurs when the receive
FIFO still contains data after a timeout period.
For Freescale SPI and MICROWIRE frame formats, the serial frame (SSInFss) pin is active Low,
and is asserted (pulled down) during the entire transmission of the frame.
For Texas Instruments synchronous serial frame format, the SSInFss pin is pulsed for one serial
clock period starting at its rising edge, prior to the transmission of each frame. For this frame format,
both the SSI and the off-chip slave device drive their output data on the rising edge of SSInClk
and latch data from the other device on the falling edge.
Unlike the full-duplex transmission of the other two frame formats, the MICROWIRE format uses a
special master-slave messaging technique which operates at half-duplex. In this mode, when a
frame begins, an 8-bit control message is transmitted to the off-chip slave. During this transmit, no
incoming data is received by the SSI. After the message has been sent, the off-chip slave decodes
it and, after waiting one serial clock after the last bit of the 8-bit control message has been sent,
responds with the requested data. The returned data can be 4 to 16 bits in length, making the total
frame length anywhere from 13 to 25 bits.
15.3.4.1
Texas Instruments Synchronous Serial Frame Format
Figure 15-2 on page 950 shows the Texas Instruments synchronous serial frame format for a single
transmitted frame.
Figure 15-2. TI Synchronous Serial Frame Format (Single Transfer)
SSInClk
SSInFss
SSInTx/SSInRx
MSB
LSB
4 to 16 bits
In this mode, SSInClk and SSInFss are forced Low, and the transmit data line SSInTx is tristated
whenever the SSI is idle. Once the bottom entry of the transmit FIFO contains data, SSInFss is
pulsed High for one SSInClk period. The value to be transmitted is also transferred from the transmit
FIFO to the serial shift register of the transmit logic. On the next rising edge of SSInClk, the MSB
of the 4 to 16-bit data frame is shifted out on the SSInTx pin. Likewise, the MSB of the received
data is shifted onto the SSInRx pin by the off-chip serial slave device.
Both the SSI and the off-chip serial slave device then clock each data bit into their serial shifter on
each falling edge of SSInClk. The received data is transferred from the serial shifter to the receive
FIFO on the first rising edge of SSInClk after the LSB has been latched.
Figure 15-3 on page 951 shows the Texas Instruments synchronous serial frame format when
back-to-back frames are transmitted.
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Figure 15-3. TI Synchronous Serial Frame Format (Continuous Transfer)
SSInClk
SSInFss
SSInTx/SSInRx
MSB
LSB
4 to 16 bits
15.3.4.2
Freescale SPI Frame Format
The Freescale SPI interface is a four-wire interface where the SSInFss signal behaves as a slave
select. The main feature of the Freescale SPI format is that the inactive state and phase of the
SSInClk signal are programmable through the SPO and SPH bits in the SSICR0 control register.
SPO Clock Polarity Bit
When the SPO clock polarity control bit is clear, it produces a steady state Low value on the SSInClk
pin. If the SPO bit is set, a steady state High value is placed on the SSInClk pin when data is not
being transferred.
SPH Phase Control Bit
The SPH phase control bit selects the clock edge that captures data and allows it to change state.
The state of this bit has the most impact on the first bit transmitted by either allowing or not allowing
a clock transition before the first data capture edge. When the SPH phase control bit is clear, data
is captured on the first clock edge transition. If the SPH bit is set, data is captured on the second
clock edge transition.
15.3.4.3
Freescale SPI Frame Format with SPO=0 and SPH=0
Single and continuous transmission signal sequences for Freescale SPI format with SPO=0 and
SPH=0 are shown in Figure 15-4 on page 952 and Figure 15-5 on page 952.
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Figure 15-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0
SSInClk
SSInFss
SSInRx
LSB
MSB
Q
4 to 16 bits
SSInTx
MSB
Note:
LSB
Q is undefined.
Figure 15-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0
SSInClk
SSInFss
SSInRx LSB
LSB
MSB
MSB
4 to16 bits
SSInTx LSB
MSB
LSB
MSB
In this configuration, during idle periods:
■ SSInClk is forced Low
■ SSInFss is forced High
■ The transmit data line SSInTx is tristated
■ When the SSI is configured as a master, it enables the SSInClk pad
■ When the SSI is configured as a slave, it disables the SSInClk pad
If the SSI is enabled and valid data is in the transmit FIFO, the start of transmission is signified by
the SSInFss master signal being driven Low, causing slave data to be enabled onto the SSInRx
input line of the master. The master SSInTx output pad is enabled.
One half SSInClk period later, valid master data is transferred to the SSInTx pin. Once both the
master and slave data have been set, the SSInClk master clock pin goes High after one additional
half SSInClk period.
The data is now captured on the rising and propagated on the falling edges of the SSInClk signal.
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In the case of a single word transmission, after all bits of the data word have been transferred, the
SSInFss line is returned to its idle High state one SSInClk period after the last bit has been
captured.
However, in the case of continuous back-to-back transmissions, the SSInFss signal must be pulsed
High between each data word transfer because the slave select pin freezes the data in its serial
peripheral register and does not allow it to be altered if the SPH bit is clear. Therefore, the master
device must raise the SSInFss pin of the slave device between each data transfer to enable the
serial peripheral data write. On completion of the continuous transfer, the SSInFss pin is returned
to its idle state one SSInClk period after the last bit has been captured.
15.3.4.4
Freescale SPI Frame Format with SPO=0 and SPH=1
The transfer signal sequence for Freescale SPI format with SPO=0 and SPH=1 is shown in Figure
15-6 on page 953, which covers both single and continuous transfers.
Figure 15-6. Freescale SPI Frame Format with SPO=0 and SPH=1
SSInClk
SSInFss
SSInRx
Q
Q
MSB
LSB
Q
4 to 16 bits
SSInTx
LSB
MSB
Note:
Q is undefined.
In this configuration, during idle periods:
■ SSInClk is forced Low
■ SSInFss is forced High
■ The transmit data line SSInTx is tristated
■ When the SSI is configured as a master, it enables the SSInClk pad
■ When the SSI is configured as a slave, it disables the SSInClk pad
If the SSI is enabled and valid data is in the transmit FIFO, the start of transmission is signified by
the SSInFss master signal being driven Low. The master SSInTx output is enabled. After an
additional one-half SSInClk period, both master and slave valid data are enabled onto their
respective transmission lines. At the same time, the SSInClk is enabled with a rising edge transition.
Data is then captured on the falling edges and propagated on the rising edges of the SSInClk
signal.
In the case of a single word transfer, after all bits have been transferred, the SSInFss line is returned
to its idle High state one SSInClk period after the last bit has been captured.
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For continuous back-to-back transfers, the SSInFss pin is held Low between successive data
words, and termination is the same as that of the single word transfer.
15.3.4.5
Freescale SPI Frame Format with SPO=1 and SPH=0
Single and continuous transmission signal sequences for Freescale SPI format with SPO=1 and
SPH=0 are shown in Figure 15-7 on page 954 and Figure 15-8 on page 954.
Figure 15-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0
SSInClk
SSInFss
SSInRx
MSB
LSB
Q
4 to 16 bits
SSInTx
LSB
MSB
Note:
Q is undefined.
Figure 15-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0
SSInClk
SSInFss
SSInTx/SSInRx LSB
MSB
LSB
MSB
4 to 16 bits
In this configuration, during idle periods:
■ SSInClk is forced High
■ SSInFss is forced High
■ The transmit data line SSInTx is tristated
■ When the SSI is configured as a master, it enables the SSInClk pad
■ When the SSI is configured as a slave, it disables the SSInClk pad
If the SSI is enabled and valid data is in the transmit FIFO, the start of transmission is signified by
the SSInFss master signal being driven Low, causing slave data to be immediately transferred
onto the SSInRx line of the master. The master SSInTx output pad is enabled.
One-half period later, valid master data is transferred to the SSInTx line. Once both the master and
slave data have been set, the SSInClk master clock pin becomes Low after one additional half
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SSInClk period, meaning that data is captured on the falling edges and propagated on the rising
edges of the SSInClk signal.
In the case of a single word transmission, after all bits of the data word are transferred, the SSInFss
line is returned to its idle High state one SSInClk period after the last bit has been captured.
However, in the case of continuous back-to-back transmissions, the SSInFss signal must be pulsed
High between each data word transfer because the slave select pin freezes the data in its serial
peripheral register and does not allow it to be altered if the SPH bit is clear. Therefore, the master
device must raise the SSInFss pin of the slave device between each data transfer to enable the
serial peripheral data write. On completion of the continuous transfer, the SSInFss pin is returned
to its idle state one SSInClk period after the last bit has been captured.
15.3.4.6
Freescale SPI Frame Format with SPO=1 and SPH=1
The transfer signal sequence for Freescale SPI format with SPO=1 and SPH=1 is shown in Figure
15-9 on page 955, which covers both single and continuous transfers.
Figure 15-9. Freescale SPI Frame Format with SPO=1 and SPH=1
SSInClk
SSInFss
SSInRx
Q
MSB
LSB
Q
4 to 16 bits
MSB
SSInTx
Note:
LSB
Q is undefined.
In this configuration, during idle periods:
■ SSInClk is forced High
■ SSInFss is forced High
■ The transmit data line SSInTx is tristated
■ When the SSI is configured as a master, it enables the SSInClk pad
■ When the SSI is configured as a slave, it disables the SSInClk pad
If the SSI is enabled and valid data is in the transmit FIFO, the start of transmission is signified by
the SSInFss master signal being driven Low. The master SSInTx output pad is enabled. After an
additional one-half SSInClk period, both master and slave data are enabled onto their respective
transmission lines. At the same time, SSInClk is enabled with a falling edge transition. Data is then
captured on the rising edges and propagated on the falling edges of the SSInClk signal.
After all bits have been transferred, in the case of a single word transmission, the SSInFss line is
returned to its idle high state one SSInClk period after the last bit has been captured.
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For continuous back-to-back transmissions, the SSInFss pin remains in its active Low state until
the final bit of the last word has been captured and then returns to its idle state as described above.
For continuous back-to-back transfers, the SSInFss pin is held Low between successive data words
and termination is the same as that of the single word transfer.
15.3.4.7
MICROWIRE Frame Format
Figure 15-10 on page 956 shows the MICROWIRE frame format for a single frame. Figure
15-11 on page 957 shows the same format when back-to-back frames are transmitted.
Figure 15-10. MICROWIRE Frame Format (Single Frame)
SSInClk
SSInFss
SSInTx
LSB
MSB
8-bit control
0
SSInRx
MSB
LSB
4 to 16 bits
output data
MICROWIRE format is very similar to SPI format, except that transmission is half-duplex instead of
full-duplex and uses a master-slave message passing technique. Each serial transmission begins
with an 8-bit control word that is transmitted from the SSI to the off-chip slave device. During this
transmission, no incoming data is received by the SSI. After the message has been sent, the off-chip
slave decodes it and, after waiting one serial clock after the last bit of the 8-bit control message has
been sent, responds with the required data. The returned data is 4 to 16 bits in length, making the
total frame length anywhere from 13 to 25 bits.
In this configuration, during idle periods:
■ SSInClk is forced Low
■ SSInFss is forced High
■ The transmit data line SSInTx is tristated
A transmission is triggered by writing a control byte to the transmit FIFO. The falling edge of SSInFss
causes the value contained in the bottom entry of the transmit FIFO to be transferred to the serial
shift register of the transmit logic and the MSB of the 8-bit control frame to be shifted out onto the
SSInTx pin. SSInFss remains Low for the duration of the frame transmission. The SSInRx pin
remains tristated during this transmission.
The off-chip serial slave device latches each control bit into its serial shifter on each rising edge of
SSInClk. After the last bit is latched by the slave device, the control byte is decoded during a one
clock wait-state, and the slave responds by transmitting data back to the SSI. Each bit is driven onto
the SSInRx line on the falling edge of SSInClk. The SSI in turn latches each bit on the rising edge
of SSInClk. At the end of the frame, for single transfers, the SSInFss signal is pulled High one
clock period after the last bit has been latched in the receive serial shifter, causing the data to be
transferred to the receive FIFO.
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Note:
The off-chip slave device can tristate the receive line either on the falling edge of SSInClk
after the LSB has been latched by the receive shifter or when the SSInFss pin goes High.
For continuous transfers, data transmission begins and ends in the same manner as a single transfer.
However, the SSInFss line is continuously asserted (held Low) and transmission of data occurs
back-to-back. The control byte of the next frame follows directly after the LSB of the received data
from the current frame. Each of the received values is transferred from the receive shifter on the
falling edge of SSInClk, after the LSB of the frame has been latched into the SSI.
Figure 15-11. MICROWIRE Frame Format (Continuous Transfer)
SSInClk
SSInFss
SSInTx
LSB
MSB
LSB
8-bit control
SSInRx
0
MSB
MSB
LSB
4 to 16 bits
output data
In the MICROWIRE mode, the SSI slave samples the first bit of receive data on the rising edge of
SSInClk after SSInFss has gone Low. Masters that drive a free-running SSInClk must ensure
that the SSInFss signal has sufficient setup and hold margins with respect to the rising edge of
SSInClk.
Figure 15-12 on page 957 illustrates these setup and hold time requirements. With respect to the
SSInClk rising edge on which the first bit of receive data is to be sampled by the SSI slave, SSInFss
must have a setup of at least two times the period of SSInClk on which the SSI operates. With
respect to the SSInClk rising edge previous to this edge, SSInFss must have a hold of at least
one SSInClk period.
Figure 15-12. MICROWIRE Frame Format, SSInFss Input Setup and Hold Requirements
tSetup=(2*tSSIClk)
tHold=tSSIClk
SSInClk
SSInFss
SSInRx
First RX data to be
sampled by SSI slave
15.3.5
DMA Operation
The SSI peripheral provides an interface to the μDMA controller with separate channels for transmit
and receive. The µDMA operation of the SSI is enabled through the SSI DMA Control (SSIDMACTL)
register. When µDMA operation is enabled, the SSI asserts a µDMA request on the receive or
transmit channel when the associated FIFO can transfer data.
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For the receive channel, a single transfer request is asserted whenever any data is in the receive
FIFO. A burst transfer request is asserted whenever the amount of data in the receive FIFO is 4 or
more items. For the transmit channel, a single transfer request is asserted whenever at least one
empty location is in the transmit FIFO. The burst request is asserted whenever the transmit FIFO
has 4 or more empty slots. The single and burst µDMA transfer requests are handled automatically
by the μDMA controller depending how the µDMA channel is configured.
To enable µDMA operation for the receive channel, the RXDMAE bit of the DMA Control
(SSIDMACTL) register should be set after configuring the µDMA. To enable µDMA operation for
the transmit channel, the TXDMAE bit of SSIDMACTL should be set after configuring the µDMA. If
µDMA is enabled, then the μDMA controller triggers an interrupt when a transfer is complete. The
interrupt occurs on the SSI interrupt vector. Therefore, if interrupts are used for SSI operation and
µDMA is enabled, the SSI interrupt handler must be designed to handle the μDMA completion
interrupt.
When transfers are performed from a FIFO of the SSI using the μDMA, and any interrupt is generated
from the SSI, the SSI module's status bit in the DMA Channel Interrupt Status (DMACHIS) register
must be checked at the end of the interrupt service routine. If the status bit is set, clear the interrupt
by writing a 1 to it.
See “Micro Direct Memory Access (μDMA)” on page 570 for more details about programming the
μDMA controller.
15.4
Initialization and Configuration
To enable and initialize the SSI, the following steps are necessary:
1. Enable the SSI module using the RCGCSSI register (see page 338).
2. Enable the clock to the appropriate GPIO module via the RCGCGPIO register (see page 331).
To find out which GPIO port to enable, refer to Table 21-5 on page 1249.
3. Set the GPIO AFSEL bits for the appropriate pins (see page 659). To determine which GPIOs to
configure, see Table 21-4 on page 1242.
4. Configure the PMCn fields in the GPIOPCTL register to assign the SSI signals to the appropriate
pins. See page 677 and Table 21-5 on page 1249.
5. Program the GPIODEN register to enable the pin's digital function. In addition, the drive strength,
drain select and pull-up/pull-down functions must be configured. Refer to “General-Purpose
Input/Outputs (GPIOs)” on page 634 for more information.
Note:
Pull-ups can be used to avoid unnecessary toggles on the SSI pins, which can take the
slave to a wrong state. In addition, if the SSIClk signal is programmed to steady state
High through the SPO bit in the SSICR0 register, then software must also configure the
GPIO port pin corresponding to the SSInClk signal as a pull-up in the GPIO Pull-Up
Select (GPIOPUR) register.
For each of the frame formats, the SSI is configured using the following steps:
1. Ensure that the SSE bit in the SSICR1 register is clear before making any configuration changes.
2. Select whether the SSI is a master or slave:
a. For master operations, set the SSICR1 register to 0x0000.0000.
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b. For slave mode (output enabled), set the SSICR1 register to 0x0000.0004.
c. For slave mode (output disabled), set the SSICR1 register to 0x0000.000C.
3. Configure the SSI clock source by writing to the SSICC register.
4. Configure the clock prescale divisor by writing the SSICPSR register.
5. Write the SSICR0 register with the following configuration:
■ Serial clock rate (SCR)
■ Desired clock phase/polarity, if using Freescale SPI mode (SPH and SPO)
■ The protocol mode: Freescale SPI, TI SSF, MICROWIRE (FRF)
■ The data size (DSS)
6. Optionally, configure the SSI module for μDMA use with the following steps:
a. Configure a μDMA for SSI use. See “Micro Direct Memory Access (μDMA)” on page 570 for
more information.
b. Enable the SSI Module's TX FIFO or RX FIFO by setting the TXDMAE or RXDMAE bit in the
SSIDMACTL register.
7. Enable the SSI by setting the SSE bit in the SSICR1 register.
As an example, assume the SSI must be configured to operate with the following parameters:
■ Master operation
■ Freescale SPI mode (SPO=1, SPH=1)
■ 1 Mbps bit rate
■ 8 data bits
Assuming the system clock is 20 MHz, the bit rate calculation would be:
SSInClk = SysClk / (CPSDVSR * (1 + SCR))
1x106 = 20x106 / (CPSDVSR * (1 + SCR))
In this case, if CPSDVSR=0x2, SCR must be 0x9.
The configuration sequence would be as follows:
1. Ensure that the SSE bit in the SSICR1 register is clear.
2. Write the SSICR1 register with a value of 0x0000.0000.
3. Write the SSICPSR register with a value of 0x0000.0002.
4. Write the SSICR0 register with a value of 0x0000.09C7.
5. The SSI is then enabled by setting the SSE bit in the SSICR1 register.
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15.5
Register Map
Table 15-2 on page 960 lists the SSI registers. The offset listed is a hexadecimal increment to the
register’s address, relative to that SSI module’s base address:
■
■
■
■
SSI0: 0x4000.8000
SSI1: 0x4000.9000
SSI2: 0x4000.A000
SSI3: 0x4000.B000
Note that the SSI module clock must be enabled before the registers can be programmed (see
page 338). The Rn bit of the PRSSI register must be read as 0x1 before any SSI module registers
are accessed.
Note:
The SSI must be disabled (see the SSE bit in the SSICR1 register) before any of the control
registers are reprogrammed.
Table 15-2. SSI Register Map
Type
Reset
Description
See
page
SSICR0
RW
0x0000.0000
SSI Control 0
962
0x004
SSICR1
RW
0x0000.0000
SSI Control 1
964
0x008
SSIDR
RW
0x0000.0000
SSI Data
966
0x00C
SSISR
RO
0x0000.0003
SSI Status
967
0x010
SSICPSR
RW
0x0000.0000
SSI Clock Prescale
969
0x014
SSIIM
RW
0x0000.0000
SSI Interrupt Mask
970
0x018
SSIRIS
RO
0x0000.0008
SSI Raw Interrupt Status
971
0x01C
SSIMIS
RO
0x0000.0000
SSI Masked Interrupt Status
973
0x020
SSIICR
W1C
0x0000.0000
SSI Interrupt Clear
975
0x024
SSIDMACTL
RW
0x0000.0000
SSI DMA Control
976
0xFC8
SSICC
RW
0x0000.0000
SSI Clock Configuration
977
0xFD0
SSIPeriphID4
RO
0x0000.0000
SSI Peripheral Identification 4
978
0xFD4
SSIPeriphID5
RO
0x0000.0000
SSI Peripheral Identification 5
979
0xFD8
SSIPeriphID6
RO
0x0000.0000
SSI Peripheral Identification 6
980
0xFDC
SSIPeriphID7
RO
0x0000.0000
SSI Peripheral Identification 7
981
0xFE0
SSIPeriphID0
RO
0x0000.0022
SSI Peripheral Identification 0
982
0xFE4
SSIPeriphID1
RO
0x0000.0000
SSI Peripheral Identification 1
983
0xFE8
SSIPeriphID2
RO
0x0000.0018
SSI Peripheral Identification 2
984
0xFEC
SSIPeriphID3
RO
0x0000.0001
SSI Peripheral Identification 3
985
0xFF0
SSIPCellID0
RO
0x0000.000D
SSI PrimeCell Identification 0
986
0xFF4
SSIPCellID1
RO
0x0000.00F0
SSI PrimeCell Identification 1
987
Offset
Name
0x000
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Table 15-2. SSI Register Map (continued)
Offset
Name
0xFF8
0xFFC
15.6
Description
See
page
Type
Reset
SSIPCellID2
RO
0x0000.0005
SSI PrimeCell Identification 2
988
SSIPCellID3
RO
0x0000.00B1
SSI PrimeCell Identification 3
989
Register Descriptions
The remainder of this section lists and describes the SSI registers, in numerical order by address
offset.
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Register 1: SSI Control 0 (SSICR0), offset 0x000
The SSICR0 register contains bit fields that control various functions within the SSI module.
Functionality such as protocol mode, clock rate, and data size are configured in this register.
SSI Control 0 (SSICR0)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
SSI2 base: 0x4000.A000
SSI3 base: 0x4000.B000
Offset 0x000
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
5
4
3
2
1
0
RW
0
RW
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
15
14
13
12
RO
0
RO
0
RO
0
RO
0
11
10
9
8
SCR
Type
Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bit/Field
Name
Type
Reset
31:16
reserved
RO
0x0000
15:8
SCR
RW
0x00
RW
0
RO
0
7
6
SPH
SPO
RW
0
RW
0
FRF
RW
0
DSS
RW
0
RW
0
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SSI Serial Clock Rate
This bit field is used to generate the transmit and receive bit rate of the
SSI. The bit rate is:
BR=SysClk/(CPSDVSR * (1 + SCR))
where CPSDVSR is an even value from 2-254 programmed in the
SSICPSR register, and SCR is a value from 0-255.
7
SPH
RW
0
SSI Serial Clock Phase
This bit is only applicable to the Freescale SPI Format.
The SPH control bit selects the clock edge that captures data and allows
it to change state. This bit has the most impact on the first bit transmitted
by either allowing or not allowing a clock transition before the first data
capture edge.
Value Description
6
SPO
RW
0
0
Data is captured on the first clock edge transition.
1
Data is captured on the second clock edge transition.
SSI Serial Clock Polarity
Value Description
0
A steady state Low value is placed on the SSInClk pin.
1
A steady state High value is placed on the SSInClk pin when
data is not being transferred.
Note:
If this bit is set, then software must also configure the
GPIO port pin corresponding to the SSInClk signal
as a pull-up in the GPIO Pull-Up Select (GPIOPUR)
register.
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Bit/Field
Name
Type
Reset
5:4
FRF
RW
0x0
Description
SSI Frame Format Select
Value Frame Format
3:0
DSS
RW
0x0
0x0
Freescale SPI Frame Format
0x1
Texas Instruments Synchronous Serial Frame Format
0x2
MICROWIRE Frame Format
0x3
Reserved
SSI Data Size Select
Value
Data Size
0x0-0x2 Reserved
0x3
4-bit data
0x4
5-bit data
0x5
6-bit data
0x6
7-bit data
0x7
8-bit data
0x8
9-bit data
0x9
10-bit data
0xA
11-bit data
0xB
12-bit data
0xC
13-bit data
0xD
14-bit data
0xE
15-bit data
0xF
16-bit data
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Register 2: SSI Control 1 (SSICR1), offset 0x004
The SSICR1 register contains bit fields that control various functions within the SSI module. Master
and slave mode functionality is controlled by this register.
SSI Control 1 (SSICR1)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
SSI2 base: 0x4000.A000
SSI3 base: 0x4000.B000
Offset 0x004
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
10
9
8
7
6
5
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:5
reserved
RO
0x0000.0
4
EOT
RW
0
RO
0
RO
0
RO
0
RO
0
4
3
2
1
0
EOT
reserved
MS
SSE
LBM
RW
0
RO
0
RW
0
RW
0
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
End of Transmission
This bit is only valid for Master mode devices and operations (MS = 0x0).
Value Description
0
The TXRIS interrupt indicates that the transmit FIFO is half full
or less.
1
The End of Transmit interrupt mode for the TXRIS interrupt is
enabled.
Note:
In Freescale SPI mode only, a condition can be created where
an EOT interrupt is generated for every byte transferred even
if the FIFO is full. If the EOT bit has been set to 0 in an
integrated slave SSI and the µDMA has been configured to
transfer data from this SSI to a Master SSI on the device using
external loopback, an EOT interrupt is generated by the SSI
slave for every byte even if the FIFO is full.
3
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2
MS
RW
0
SSI Master/Slave Select
This bit selects Master or Slave mode and can be modified only when
the SSI is disabled (SSE=0).
Value Description
0
The SSI is configured as a master.
1
The SSI is configured as a slave.
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Bit/Field
Name
Type
Reset
1
SSE
RW
0
Description
SSI Synchronous Serial Port Enable
Value Description
0
SSI operation is disabled.
1
SSI operation is enabled.
Note:
0
LBM
RW
0
This bit must be cleared before any control registers
are reprogrammed.
SSI Loopback Mode
Value Description
0
Normal serial port operation enabled.
1
Output of the transmit serial shift register is connected internally
to the input of the receive serial shift register.
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Register 3: SSI Data (SSIDR), offset 0x008
Important: This register is read-sensitive. See the register description for details.
The SSIDR register is 16-bits wide. When the SSIDR register is read, the entry in the receive FIFO
that is pointed to by the current FIFO read pointer is accessed. When a data value is removed by
the SSI receive logic from the incoming data frame, it is placed into the entry in the receive FIFO
pointed to by the current FIFO write pointer.
When the SSIDR register is written to, the entry in the transmit FIFO that is pointed to by the write
pointer is written to. Data values are removed from the transmit FIFO one value at a time by the
transmit logic. Each data value is loaded into the transmit serial shifter, then serially shifted out onto
the SSInTx pin at the programmed bit rate.
When a data size of less than 16 bits is selected, the user must right-justify data written to the
transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is
automatically right-justified in the receive buffer.
When the SSI is programmed for MICROWIRE frame format, the default size for transmit data is
eight bits (the most significant byte is ignored). The receive data size is controlled by the programmer.
The transmit FIFO and the receive FIFO are not cleared even when the SSE bit in the SSICR1
register is cleared, allowing the software to fill the transmit FIFO before enabling the SSI.
SSI Data (SSIDR)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
SSI2 base: 0x4000.A000
SSI3 base: 0x4000.B000
Offset 0x008
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
DATA
Type
Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bit/Field
Name
Type
Reset
Description
31:16
reserved
RO
0x0000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:0
DATA
RW
0x0000
SSI Receive/Transmit Data
A read operation reads the receive FIFO. A write operation writes the
transmit FIFO.
Software must right-justify data when the SSI is programmed for a data
size that is less than 16 bits. Unused bits at the top are ignored by the
transmit logic. The receive logic automatically right-justifies the data.
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Register 4: SSI Status (SSISR), offset 0x00C
The SSISR register contains bits that indicate the FIFO fill status and the SSI busy status.
SSI Status (SSISR)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
SSI2 base: 0x4000.A000
SSI3 base: 0x4000.B000
Offset 0x00C
Type RO, reset 0x0000.0003
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
10
9
8
7
6
5
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:5
reserved
RO
0x0000.00
4
BSY
RO
0
RO
0
RO
0
RO
0
RO
0
4
3
2
1
0
BSY
RFF
RNE
TNF
TFE
RO
0
RO
0
RO
0
RO
1
RO
1
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SSI Busy Bit
Value Description
3
RFF
RO
0
0
The SSI is idle.
1
The SSI is currently transmitting and/or receiving a frame, or
the transmit FIFO is not empty.
SSI Receive FIFO Full
Value Description
2
RNE
RO
0
0
The receive FIFO is not full.
1
The receive FIFO is full.
SSI Receive FIFO Not Empty
Value Description
1
TNF
RO
1
0
The receive FIFO is empty.
1
The receive FIFO is not empty.
SSI Transmit FIFO Not Full
Value Description
0
The transmit FIFO is full.
1
The transmit FIFO is not full.
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Bit/Field
Name
Type
Reset
0
TFE
RO
1
Description
SSI Transmit FIFO Empty
Value Description
0
The transmit FIFO is not empty.
1
The transmit FIFO is empty.
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Register 5: SSI Clock Prescale (SSICPSR), offset 0x010
The SSICPSR register specifies the division factor which is used to derive the SSInClk from the
system clock. The clock is further divided by a value from 1 to 256, which is 1 + SCR. SCR is
programmed in the SSICR0 register. The frequency of the SSInClk is defined by:
SSInClk = SysClk / (CPSDVSR * (1 + SCR))
The value programmed into this register must be an even number between 2 and 254. The
least-significant bit of the programmed number is hard-coded to zero. If an odd number is written
to this register, data read back from this register has the least-significant bit as zero.
SSI Clock Prescale (SSICPSR)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
SSI2 base: 0x4000.A000
SSI3 base: 0x4000.B000
Offset 0x010
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
reserved
Type
Reset
CPSDVSR
RO
0
RW
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
CPSDVSR
RW
0x00
SSI Clock Prescale Divisor
This value must be an even number from 2 to 254, depending on the
frequency of SSInClk. The LSB always returns 0 on reads.
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Register 6: SSI Interrupt Mask (SSIIM), offset 0x014
The SSIIM register is the interrupt mask set or clear register. It is a read/write register and all bits
are cleared on reset.
On a read, this register gives the current value of the mask on the corresponding interrupt. Setting
a bit clears the mask, enabling the interrupt to be sent to the interrupt controller. Clearing a bit sets
the corresponding mask, preventing the interrupt from being signaled to the controller.
SSI Interrupt Mask (SSIIM)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
SSI2 base: 0x4000.A000
SSI3 base: 0x4000.B000
Offset 0x014
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
TXIM
RXIM
RTIM
RORIM
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
Description
31:4
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
TXIM
RW
0
SSI Transmit FIFO Interrupt Mask
Value Description
2
RXIM
RW
0
0
The transmit FIFO interrupt is masked.
1
The transmit FIFO interrupt is not masked.
SSI Receive FIFO Interrupt Mask
Value Description
1
RTIM
RW
0
0
The receive FIFO interrupt is masked.
1
The receive FIFO interrupt is not masked.
SSI Receive Time-Out Interrupt Mask
Value Description
0
RORIM
RW
0
0
The receive FIFO time-out interrupt is masked.
1
The receive FIFO time-out interrupt is not masked.
SSI Receive Overrun Interrupt Mask
Value Description
0
The receive FIFO overrun interrupt is masked.
1
The receive FIFO overrun interrupt is not masked.
970
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018
The SSIRIS register is the raw interrupt status register. On a read, this register gives the current
raw status value of the corresponding interrupt prior to masking. A write has no effect.
SSI Raw Interrupt Status (SSIRIS)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
SSI2 base: 0x4000.A000
SSI3 base: 0x4000.B000
Offset 0x018
Type RO, reset 0x0000.0008
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
3
2
1
0
TXRIS
RXRIS
RTRIS
RORRIS
RO
1
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:4
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
TXRIS
RO
1
SSI Transmit FIFO Raw Interrupt Status
Value Description
0
No interrupt.
1
If the EOT bit in the SSICR1 register is clear, the transmit FIFO
is half empty or less.
If the EOT bit is set, the transmit FIFO is empty, and the last bit
has been transmitted out of the serializer.
This bit is cleared when the transmit FIFO is more than half full (if the
EOT bit is clear) or when it has any data in it (if the EOT bit is set).
2
RXRIS
RO
0
SSI Receive FIFO Raw Interrupt Status
Value Description
0
No interrupt.
1
The receive FIFO is half full or more.
This bit is cleared when the receive FIFO is less than half full.
1
RTRIS
RO
0
SSI Receive Time-Out Raw Interrupt Status
Value Description
0
No interrupt.
1
The receive time-out has occurred.
This bit is cleared when a 1 is written to the RTIC bit in the SSI Interrupt
Clear (SSIICR) register.
June 12, 2014
971
Texas Instruments-Production Data
Synchronous Serial Interface (SSI)
Bit/Field
Name
Type
Reset
0
RORRIS
RO
0
Description
SSI Receive Overrun Raw Interrupt Status
Value Description
0
No interrupt.
1
The receive FIFO has overflowed
This bit is cleared when a 1 is written to the RORIC bit in the SSI
Interrupt Clear (SSIICR) register.
972
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C
The SSIMIS register is the masked interrupt status register. On a read, this register gives the current
masked status value of the corresponding interrupt. A write has no effect.
SSI Masked Interrupt Status (SSIMIS)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
SSI2 base: 0x4000.A000
SSI3 base: 0x4000.B000
Offset 0x01C
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
3
2
1
0
TXMIS
RXMIS
RTMIS
RORMIS
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:4
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
TXMIS
RO
0
SSI Transmit FIFO Masked Interrupt Status
Value Description
0
An interrupt has not occurred or is masked.
1
An unmasked interrupt was signaled due to the transmit FIFO
being half empty or less (if the EOT bit is clear) or due to the
transmission of the last data bit (if the EOT bit is set).
This bit is cleared when the transmit FIFO is more than half empty (if
the EOT bit is clear) or when it has any data in it (if the EOT bit is set).
2
RXMIS
RO
0
SSI Receive FIFO Masked Interrupt Status
Value Description
0
An interrupt has not occurred or is masked.
1
An unmasked interrupt was signaled due to the receive FIFO
being half full or more.
This bit is cleared when the receive FIFO is less than half full.
1
RTMIS
RO
0
SSI Receive Time-Out Masked Interrupt Status
Value Description
0
An interrupt has not occurred or is masked.
1
An unmasked interrupt was signaled due to the receive time
out.
This bit is cleared when a 1 is written to the RTIC bit in the SSI Interrupt
Clear (SSIICR) register.
June 12, 2014
973
Texas Instruments-Production Data
Synchronous Serial Interface (SSI)
Bit/Field
Name
Type
Reset
0
RORMIS
RO
0
Description
SSI Receive Overrun Masked Interrupt Status
Value Description
0
An interrupt has not occurred or is masked.
1
An unmasked interrupt was signaled due to the receive FIFO
overflowing.
This bit is cleared when a 1 is written to the RORIC bit in the SSI
Interrupt Clear (SSIICR) register.
974
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Register 9: SSI Interrupt Clear (SSIICR), offset 0x020
The SSIICR register is the interrupt clear register. On a write of 1, the corresponding interrupt is
cleared. A write of 0 has no effect.
SSI Interrupt Clear (SSIICR)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
SSI2 base: 0x4000.A000
SSI3 base: 0x4000.B000
Offset 0x020
Type W1C, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
1
0
RTIC
RORIC
W1C
0
W1C
0
Bit/Field
Name
Type
Reset
Description
31:2
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1
RTIC
W1C
0
SSI Receive Time-Out Interrupt Clear
Writing a 1 to this bit clears the RTRIS bit in the SSIRIS register and
the RTMIS bit in the SSIMIS register.
0
RORIC
W1C
0
SSI Receive Overrun Interrupt Clear
Writing a 1 to this bit clears the RORRIS bit in the SSIRIS register and
the RORMIS bit in the SSIMIS register.
June 12, 2014
975
Texas Instruments-Production Data
Synchronous Serial Interface (SSI)
Register 10: SSI DMA Control (SSIDMACTL), offset 0x024
The SSIDMACTL register is the µDMA control register.
SSI DMA Control (SSIDMACTL)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
SSI2 base: 0x4000.A000
SSI3 base: 0x4000.B000
Offset 0x024
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
1
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:2
reserved
RO
0x0000.000
1
TXDMAE
RW
0
TXDMAE RXDMAE
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Transmit DMA Enable
Value Description
0
RXDMAE
RW
0
0
µDMA for the transmit FIFO is disabled.
1
µDMA for the transmit FIFO is enabled.
Receive DMA Enable
Value Description
0
µDMA for the receive FIFO is disabled.
1
µDMA for the receive FIFO is enabled.
976
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Register 11: SSI Clock Configuration (SSICC), offset 0xFC8
The SSICC register controls the baud clock source for the SSI module.
Note:
If the PIOSC is used for the SSI baud clock, the system clock frequency must be at least
16 MHz in Run mode.
SSI Clock Configuration (SSICC)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
SSI2 base: 0x4000.A000
SSI3 base: 0x4000.B000
Offset 0xFC8
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
reserved
Type
Reset
CS
Bit/Field
Name
Type
Reset
31:4
reserved
RO
0x0000.000
3:0
CS
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SSI Baud Clock Source
The following table specifies the source that generates for the SSI baud
clock:
Value
Description
0x0
System clock (based on clock source and divisor factor)
0x1-0x4
reserved
0x5
PIOSC
0x6 - 0xF Reserved
June 12, 2014
977
Texas Instruments-Production Data
Synchronous Serial Interface (SSI)
Register 12: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 4 (SSIPeriphID4)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
SSI2 base: 0x4000.A000
SSI3 base: 0x4000.B000
Offset 0xFD0
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
PID4
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
PID4
RO
0x00
RO
0
RO
0
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SSI Peripheral ID Register [7:0]
Can be used by software to identify the presence of this peripheral.
978
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Register 13: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 5 (SSIPeriphID5)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
SSI2 base: 0x4000.A000
SSI3 base: 0x4000.B000
Offset 0xFD4
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
PID5
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
PID5
RO
0x00
RO
0
RO
0
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SSI Peripheral ID Register [15:8]
Can be used by software to identify the presence of this peripheral.
June 12, 2014
979
Texas Instruments-Production Data
Synchronous Serial Interface (SSI)
Register 14: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 6 (SSIPeriphID6)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
SSI2 base: 0x4000.A000
SSI3 base: 0x4000.B000
Offset 0xFD8
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
PID6
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
PID6
RO
0x00
RO
0
RO
0
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SSI Peripheral ID Register [23:16]
Can be used by software to identify the presence of this peripheral.
980
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Register 15: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 7 (SSIPeriphID7)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
SSI2 base: 0x4000.A000
SSI3 base: 0x4000.B000
Offset 0xFDC
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
PID7
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
PID7
RO
0x00
RO
0
RO
0
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SSI Peripheral ID Register [31:24]
Can be used by software to identify the presence of this peripheral.
June 12, 2014
981
Texas Instruments-Production Data
Synchronous Serial Interface (SSI)
Register 16: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 0 (SSIPeriphID0)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
SSI2 base: 0x4000.A000
SSI3 base: 0x4000.B000
Offset 0xFE0
Type RO, reset 0x0000.0022
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
0
RO
1
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
PID0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
PID0
RO
0x22
RO
0
RO
0
RO
0
RO
1
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SSI Peripheral ID Register [7:0]
Can be used by software to identify the presence of this peripheral.
982
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Register 17: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 1 (SSIPeriphID1)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
SSI2 base: 0x4000.A000
SSI3 base: 0x4000.B000
Offset 0xFE4
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
PID1
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
PID1
RO
0x00
RO
0
RO
0
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SSI Peripheral ID Register [15:8]
Can be used by software to identify the presence of this peripheral.
June 12, 2014
983
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Synchronous Serial Interface (SSI)
Register 18: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 2 (SSIPeriphID2)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
SSI2 base: 0x4000.A000
SSI3 base: 0x4000.B000
Offset 0xFE8
Type RO, reset 0x0000.0018
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
1
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
PID2
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
PID2
RO
0x18
RO
0
RO
0
RO
0
RO
0
RO
1
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SSI Peripheral ID Register [23:16]
Can be used by software to identify the presence of this peripheral.
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Tiva™ TM4C1237H6PZ Microcontroller
Register 19: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 3 (SSIPeriphID3)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
SSI2 base: 0x4000.A000
SSI3 base: 0x4000.B000
Offset 0xFEC
Type RO, reset 0x0000.0001
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
0
RO
0
RO
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
PID3
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
PID3
RO
0x01
RO
0
RO
0
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SSI Peripheral ID Register [31:24]
Can be used by software to identify the presence of this peripheral.
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Synchronous Serial Interface (SSI)
Register 20: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0
The SSIPCellIDn registers are hard-coded, and the fields within the register determine the reset
value.
SSI PrimeCell Identification 0 (SSIPCellID0)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
SSI2 base: 0x4000.A000
SSI3 base: 0x4000.B000
Offset 0xFF0
Type RO, reset 0x0000.000D
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
1
RO
1
RO
0
RO
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
CID0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
CID0
RO
0x0D
RO
0
RO
0
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SSI PrimeCell ID Register [7:0]
Provides software a standard cross-peripheral identification system.
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Register 21: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4
The SSIPCellIDn registers are hard-coded, and the fields within the register determine the reset
value.
SSI PrimeCell Identification 1 (SSIPCellID1)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
SSI2 base: 0x4000.A000
SSI3 base: 0x4000.B000
Offset 0xFF4
Type RO, reset 0x0000.00F0
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
CID1
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
CID1
RO
0xF0
RO
0
RO
1
RO
1
RO
1
RO
1
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SSI PrimeCell ID Register [15:8]
Provides software a standard cross-peripheral identification system.
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Synchronous Serial Interface (SSI)
Register 22: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8
The SSIPCellIDn registers are hard-coded, and the fields within the register determine the reset
value.
SSI PrimeCell Identification 2 (SSIPCellID2)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
SSI2 base: 0x4000.A000
SSI3 base: 0x4000.B000
Offset 0xFF8
Type RO, reset 0x0000.0005
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
1
RO
0
RO
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
CID2
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
CID2
RO
0x05
RO
0
RO
0
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SSI PrimeCell ID Register [23:16]
Provides software a standard cross-peripheral identification system.
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Tiva™ TM4C1237H6PZ Microcontroller
Register 23: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC
The SSIPCellIDn registers are hard-coded, and the fields within the register determine the reset
value.
SSI PrimeCell Identification 3 (SSIPCellID3)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
SSI2 base: 0x4000.A000
SSI3 base: 0x4000.B000
Offset 0xFFC
Type RO, reset 0x0000.00B1
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
0
RO
0
RO
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
CID3
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
CID3
RO
0xB1
RO
0
RO
1
RO
0
RO
1
RO
1
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SSI PrimeCell ID Register [31:24]
Provides software a standard cross-peripheral identification system.
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Inter-Integrated Circuit (I2C) Interface
16
Inter-Integrated Circuit (I2C) Interface
The Inter-Integrated Circuit (I2C) bus provides bi-directional data transfer through a two-wire design
(a serial data line SDA and a serial clock line SCL), and interfaces to external I2C devices such as
serial memory (RAMs and ROMs), networking devices, LCDs, tone generators, and so on. The I2C
bus may also be used for system testing and diagnostic purposes in product development and
manufacturing. The TM4C1237H6PZ microcontroller includes providing the ability to communicate
(both transmit and receive) with other I2C devices on the bus.
The TM4C1237H6PZ controller includes I2C modules with the following features:
■ Devices on the I2C bus can be designated as either a master or a slave
– Supports both transmitting and receiving data as either a master or a slave
– Supports simultaneous master and slave operation
■ Four I2C modes
– Master transmit
– Master receive
– Slave transmit
– Slave receive
■ Four transmission speeds:
– Standard (100 Kbps)
– Fast-mode (400 Kbps)
– Fast-mode plus (1 Mbps)
– High-speed mode (3.33 Mbps)
■ Clock low timeout interrupt
■ Dual slave address capability
■ Glitch suppression
■ Master and slave interrupt generation
– Master generates interrupts when a transmit or receive operation completes (or aborts due
to an error)
– Slave generates interrupts when data has been transferred or requested by a master or when
a START or STOP condition is detected
■ Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing
mode
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16.1
Block Diagram
Figure 16-1. I2C Block Diagram
I2CSCL
I2C Control
Interrupt
I2CMSA
I2CSOAR
I2CMCS
I2CSCSR
I2CMDR
I2CSDR
I2CMTPR
I2CSIMR
I2CMIMR
I2CSRIS
I2CMRIS
I2CSMIS
I2CMMIS
I2CSICR
I2CMICR
I2CPP
I2C Master Core
I2CSDA
I2CSCL
2
I C I/O Select
I2CSDA
I2CSCL
I2C Slave Core
I2CSDA
I2CMCR
16.2
Signal Description
The following table lists the external signals of the I2C interface and describes the function of each.
The I2C interface signals are alternate functions for some GPIO signals and default to be GPIO
signals at reset, with the exception of the I2C0SCL and I2CSDA pins which default to the I2C
function. The column in the table below titled "Pin Mux/Pin Assignment" lists the possible GPIO pin
placements for the I2C signals. The AFSEL bit in the GPIO Alternate Function Select (GPIOAFSEL)
register (page 659) should be set to choose the I2C function. The number in parentheses is the
encoding that must be programmed into the PMCn field in the GPIO Port Control (GPIOPCTL)
register (page 677) to assign the I2C signal to the specified GPIO port pin. Note that the I2CSDA pin
should be set to open drain using the GPIO Open Drain Select (GPIOODR) register. For more
information on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 634.
Table 16-1. I2C Signals (100LQFP)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
I2C0SCL
72
PB2 (3)
I/O
OD
I2C module 0 clock. Note that this signal has an
active pull-up. The corresponding port pin should
not be configured as open drain.
I2C0SDA
73
PB3 (3)
I/O
OD
I2C module 0 data.
I2C1SCL
34
74
PA6 (3)
PG4 (3)
I/O
OD
I2C module 1 clock. Note that this signal has an
active pull-up. The corresponding port pin should
not be configured as open drain.
I2C1SDA
35
75
PA7 (3)
PG5 (3)
I/O
OD
I2C module 1 data.
I2C2SCL
36
95
PF6 (3)
PE4 (3)
I/O
OD
I2C module 2 clock. Note that this signal has an
active pull-up. The corresponding port pin should
not be configured as open drain.
I2C2SDA
58
96
PF7 (3)
PE5 (3)
I/O
OD
I2C module 2 data.
I2C3SCL
1
62
PD0 (3)
PG0 (3)
I/O
OD
I2C module 3 clock. Note that this signal has an
active pull-up. The corresponding port pin should
not be configured as open drain.
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Table 16-1. I2C Signals (100LQFP) (continued)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
I2C3SDA
2
61
PD1 (3)
PG1 (3)
I/O
OD
I2C module 3 data.
I2C4SCL
60
PG2 (3)
I/O
OD
I2C module 4 clock. Note that this signal has an
active pull-up. The corresponding port pin should
not be configured as open drain.
I2C4SDA
59
PG3 (3)
I/O
OD
I2C module 4 data.
I2C5SCL
87
PG6 (3)
I/O
OD
I2C module 5 clock. Note that this signal has an
active pull-up. The corresponding port pin should
not be configured as open drain.
I2C5SDA
88
PG7 (3)
I/O
OD
I2C module 5 data.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
16.3
Functional Description
Each I2C module is comprised of both master and slave functions and is identified by a unique
address. A master-initiated communication generates the clock signal, SCL. For proper operation,
the SDA pin must be configured as an open-drain signal. Due to the internal circuitry that supports
high-speed operation, the SCL pin must not be configured as an open-drain signal, although the
internal circuitry causes it to act as if it were an open drain signal. Both SDA and SCL signals must
be connected to a positive supply voltage using a pull-up resistor. A typical I2C bus configuration is
shown in Figure 16-2. Refer to the I2C-bus specification and user manual to determine the size of
the pull-ups needed for proper operation.
See “Inter-Integrated Circuit (I2C) Interface” on page 1294 for I2C timing diagrams.
Figure 16-2. I2C Bus Configuration
RPUP
SCL
SDA
I2C Bus
I2CSCL
I2CSDA
Tiva™
Microcontroller
16.3.1
RPUP
SCL
SDA
3rd Party Device
with I2C Interface
SCL
SDA
3rd Party Device
with I2C Interface
I2C Bus Functional Overview
The I2C bus uses only two signals: SDA and SCL, named I2CSDA and I2CSCL on TM4C1237H6PZ
microcontrollers. SDA is the bi-directional serial data line and SCL is the bi-directional serial clock
line. The bus is considered idle when both lines are High.
Every transaction on the I2C bus is nine bits long, consisting of eight data bits and a single
acknowledge bit. The number of bytes per transfer (defined as the time between a valid START
and STOP condition, described in “START and STOP Conditions” on page 993) is unrestricted, but
each data byte has to be followed by an acknowledge bit, and data must be transferred MSB first.
When a receiver cannot receive another complete byte, it can hold the clock line SCL Low and force
the transmitter into a wait state. The data transfer continues when the receiver releases the clock
SCL.
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16.3.1.1
START and STOP Conditions
The protocol of the I2C bus defines two states to begin and end a transaction: START and STOP.
A High-to-Low transition on the SDA line while the SCL is High is defined as a START condition,
and a Low-to-High transition on the SDA line while SCL is High is defined as a STOP condition.
The bus is considered busy after a START condition and free after a STOP condition. See Figure
16-3.
Figure 16-3. START and STOP Conditions
SDA
SDA
SCL
SCL
START
condition
STOP
condition
The STOP bit determines if the cycle stops at the end of the data cycle or continues on to a repeated
START condition. To generate a single transmit cycle, the I2C Master Slave Address (I2CMSA)
register is written with the desired address, the R/S bit is cleared, and the Control register is written
with ACK=X (0 or 1), STOP=1, START=1, and RUN=1 to perform the operation and stop. When the
operation is completed (or aborted due an error), the interrupt pin becomes active and the data may
be read from the I2C Master Data (I2CMDR) register. When the I2C module operates in Master
receiver mode, the ACK bit is normally set causing the I2C bus controller to transmit an acknowledge
automatically after each byte. This bit must be cleared when the I2C bus controller requires no further
data to be transmitted from the slave transmitter.
When operating in slave mode, the STARTRIS and STOPRIS bits in the I2C Slave Raw Interrupt
Status (I2CSRIS) register indicate detection of start and stop conditions on the bus and the I2C
Slave Masked Interrupt Status (I2CSMIS) register can be configured to allow STARTRIS and
STOPRIS to be promoted to controller interrupts (when interrupts are enabled).
16.3.1.2
Data Format with 7-Bit Address
Data transfers follow the format shown in Figure 16-4. After the START condition, a slave address
is transmitted. This address is 7-bits long followed by an eighth bit, which is a data direction bit (R/S
bit in the I2CMSA register). If the R/S bit is clear, it indicates a transmit operation (send), and if it
is set, it indicates a request for data (receive). A data transfer is always terminated by a STOP
condition generated by the master, however, a master can initiate communications with another
device on the bus by generating a repeated START condition and addressing another slave without
first generating a STOP condition. Various combinations of receive/transmit formats are then possible
within a single transfer.
Figure 16-4. Complete Data Transfer with a 7-Bit Address
SDA
MSB
SCL
1
Start
2
LSB
R/S
ACK
7
8
9
MSB
1
2
Slave address
7
Data
LSB
ACK
8
9
Stop
The first seven bits of the first byte make up the slave address (see Figure 16-5). The eighth bit
determines the direction of the message. A zero in the R/S position of the first byte means that the
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master transmits (sends) data to the selected slave, and a one in this position means that the master
receives data from the slave.
Figure 16-5. R/S Bit in First Byte
MSB
LSB
R/S
Slave address
16.3.1.3
Data Validity
The data on the SDA line must be stable during the high period of the clock, and the data line can
only change when SCL is Low (see Figure 16-6).
Figure 16-6. Data Validity During Bit Transfer on the I2C Bus
SDA
SCL
16.3.1.4
Data line Change
stable of data
allowed
Acknowledge
All bus transactions have a required acknowledge clock cycle that is generated by the master. During
the acknowledge cycle, the transmitter (which can be the master or slave) releases the SDA line.
To acknowledge the transaction, the receiver must pull down SDA during the acknowledge clock
cycle. The data transmitted out by the receiver during the acknowledge cycle must comply with the
data validity requirements described in “Data Validity” on page 994.
When a slave receiver does not acknowledge the slave address, SDA must be left High by the slave
so that the master can generate a STOP condition and abort the current transfer. If the master
device is acting as a receiver during a transfer, it is responsible for acknowledging each transfer
made by the slave. Because the master controls the number of bytes in the transfer, it signals the
end of data to the slave transmitter by not generating an acknowledge on the last data byte. The
slave transmitter must then release SDA to allow the master to generate the STOP or a repeated
START condition.
If the slave is required to provide a manual ACK or NACK, the I2C Slave ACK Control
(I2CSACKCTL) register allows the slave to NACK for invalid data or command or ACK for valid
data or command. When this operation is enabled, the MCU slave module I2C clock is pulled low
after the last data bit until this register is written with the indicated response.
16.3.1.5
Repeated Start
The I2C master module has the capability of executing a repeated START (transmit or receive) after
an initial transfer has occurred.
A repeated start sequence for a Master transmit is as follows:
1. When the device is in the idle state, the Master writes the slave address to the I2CMSA register
and configures the R/S bit for the desired transfer type.
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2. Data is written to the I2CMDR register.
3. When the BUSY bit in the I2CMCS register is 0 , the Master writes 0x3 to the I2CMCS register
to initiate a transfer.
4. The Master does not generate a STOP condition but instead writes another slave address to
the I2CMSA register and then writes 0x3 to initiate the repeated START.
A repeated start sequence for a Master receive is similar:
1. When the device is in idle, the Master writes the slave address to the I2CMSA register and
configures the R/S bit for the desired transfer type.
2. The master reads data from the I2CMDR register.
3. When the BUSY bit in the I2CMCS register is 0 , the Master writes 0x3 to the I2CMCS register
to initiate a transfer.
4. The Master does not generate a STOP condition but instead writes another slave address to
the I2CMSA register and then writes 0x3 to initiate the repeated START.
For more information on repeated START, refer to Figure 16-12 on page 1005 and Figure
16-13 on page 1006.
16.3.1.6
Clock Low Timeout (CLTO)
The I2C slave can extend the transaction by pulling the clock low periodically to create a slow bit
transfer rate. The I2C module has a 12-bit programmable counter that is used to track how long the
clock has been held low. The upper 8 bits of the count value are software programmable through
the I2C Master Clock Low Timeout Count (I2CMCLKOCNT) register. The lower four bits are not
user visible and are 0x0. The CNTL value programmed in the I2CMCLKOCNT register has to be
greater than 0x01. The application can program the eight most significant bits of the counter to
reflect the acceptable cumulative low period in transaction. The count is loaded at the START
condition and counts down on each falling edge of the internal bus clock of the Master. Note that
the internal bus clock generated for this counter keeps running at the programmed I2C speed even
if SCL is held low on the bus. Upon reaching terminal count, the master state machine forces ABORT
on the bus by issuing a STOP condition at the instance of SCL and SDA release.
As an example, if an I2C module was operating at 100 kHz speed, programming the I2CMCLKOCNT
register to 0xDA would translate to the value 0xDA0 since the lower four bits are set to 0x0. This
would translate to a decimal value of 3488 clocks or a cumulative clock low period of 34.88 ms at
100 kHz.
The CLKRIS bit in the I2C Master Raw Interrupt Status (I2CMRIS) register is set when the clock
timeout period is reached, allowing the master to start corrective action to resolve the remote slave
state. In addition, the CLKTO bit in the I2C Master Control/Status (I2CMCS) register is set; this bit
is cleared when a STOP condition is sent or during the I2C master reset. The status of the raw SDA
and SCL signals are readable by software through the SDA and SCL bits in the I2C Master Bus
Monitor (I2CMBMON) register to help determine the state of the remote slave.
In the event of a CLTO condition, application software must choose how it intends to attempt bus
recovery. Most applications may attempt to manually toggle the I2C pins to force the slave to let go
of the clock signal (a common solution is to attempt to force a STOP on the bus). If a CLTO is
detected before the end of a burst transfer, and the bus is successfully recovered by the master,
the master hardware attempts to finish the pending burst operation. Depending on the state of the
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slave after bus recovery, the actual behavior on the bus varies. If the slave resumes in a state where
it can acknowledge the master (essentially, where it was before the bus hang), it continues where
it left off. However, if the slave resumes in a reset state (or if a forced STOP by the master causes
the slave to enter the idle state), it may ignore the master's attempt to complete the burst operation
and NAK the first data byte that the master sends or requests.
Since the behavior of slaves cannot always be predicted, it is suggested that the application software
always write the STOP bit in the I2C Master Configuration (I2CMCR) register during the CLTO
interrupt service routine. This limits the amount of data the master attempts to send or receive upon
bus recovery to a single byte, and after the single byte is on the wire, the master issues a STOP.
An alternative solution is to have the application software reset the I2C peripheral before attempting
to manually recover the bus. This solution allows the I2C master hardware to be returned to a known
good (and idle) state before attempting to recover a stuck bus and prevents any unwanted data
from appearing on the wire.
Note:
16.3.1.7
The Master Clock Low Timeout counter counts for the entire time SCL is held Low
continuously. If SCL is deasserted at any point, the Master Clock Low Timeout Counter is
reloaded with the value in the I2CMCLKOCNT register and begins counting down from this
value.
Dual Address
The I2C interface supports dual address capability for the slave. The additional programmable
address is provided and can be matched if enabled. In legacy mode with dual address disabled,
the I2C slave provides an ACK on the bus if the address matches the OAR field in the I2CSOAR
register. In dual address mode, the I2C slave provides an ACK on the bus if either the OAR field in
the I2CSOAR register or the OAR2 field in the I2CSOAR2 register is matched. The enable for dual
address is programmable through the OAR2EN bit in the I2CSOAR2 register and there is no disable
on the legacy address.
The OAR2SEL bit in the I2CSCSR register indicates if the address that was ACKed is the alternate
address or not. When this bit is clear, it indicates either legacy operation or no address match.
16.3.1.8
Arbitration
A master may start a transfer only if the bus is idle. It's possible for two or more masters to generate
a START condition within minimum hold time of the START condition. In these situations, an
arbitration scheme takes place on the SDA line, while SCL is High. During arbitration, the first of
the competing master devices to place a 1 (High) on SDA, while another master transmits a 0 (Low),
switches off its data output stage and retires until the bus is idle again.
Arbitration can take place over several bits. Its first stage is a comparison of address bits, and if
both masters are trying to address the same device, arbitration continues on to the comparison of
data bits.
16.3.1.9
Glitch Suppression in Multi-Master Configuration
When a multi-master configuration is being used, the GFE bit in the I2C Master Configuration
(I2CMCR) register can be set to enable glitch suppression on the SCL and SDA lines and assure
proper signal values. The filter can be programmed to different filter widths using the GFPW bit in
the I2C Master Configuration 2 (I2CMCR2) register. The glitch suppression value is in terms of
buffered system clocks. Note that all signals will be delayed internally when glitch suppression is
nonzero. For example, if GFPW is set to 0x7, 31 clocks should be added onto the calculation for the
expected transaction time.
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16.3.2
Available Speed Modes
The I2C bus can run in Standard mode (100 kbps), Fast mode (400 kbps), Fast mode plus (1 Mbps)
or High-Speed mode (3.33 Mbps). The selected mode should match the speed of the other I2C
devices on the bus.
16.3.2.1
Standard, Fast, and Fast Plus Modes
Standard, Fast, and Fast Plus modes are selected using a value in the I2C Master Timer Period
(I2CMTPR) register that results in an SCL frequency of 100 kbps for Standard mode, 400 kbps for
Fast mode, or 1 Mbps for Fast mode plus.
The I2C clock rate is determined by the parameters CLK_PRD, TIMER_PRD, SCL_LP, and SCL_HP
where:
CLK_PRD is the system clock period
SCL_LP is the low phase of SCL (fixed at 6)
SCL_HP is the high phase of SCL (fixed at 4)
TIMER_PRD is the programmed value in the I2CMTPR register (see page 1019). This value is
determined by replacing the known variables in the equation below and solving for TIMER_PRD.
The I2C clock period is calculated as follows:
SCL_PERIOD = 2 × (1 + TIMER_PRD) × (SCL_LP + SCL_HP) × CLK_PRD
For example:
CLK_PRD = 50 ns
TIMER_PRD = 2
SCL_LP=6
SCL_HP=4
yields a SCL frequency of:
1/SCL_PERIOD = 333 Khz
Table 16-2 gives examples of the timer periods that should be used to generate Standard, Fast
mode, and Fast mode plus SCL frequencies based on various system clock frequencies.
Table 16-2. Examples of I2C Master Timer Period Versus Speed Mode
System Clock
Timer Period
Standard Mode
Timer Period
Fast Mode
Timer
Period
Fast Mode
Plus
4 MHz
0x01
100 Kbps
-
-
-
-
6 MHz
0x02
100 Kbps
-
-
-
-
12.5 MHz
0x06
89 Kbps
0x01
312 Kbps
-
-
16.7 MHz
0x08
93 Kbps
0x02
278 Kbps
-
-
20 MHz
0x09
100 Kbps
0x02
333 Kbps
-
-
25 MHz
0x0C
96.2 Kbps
0x03
312 Kbps
-
-
33 MHz
0x10
97.1 Kbps
0x04
330 Kbps
-
-
40 MHz
0x13
100 Kbps
0x04
400 Kbps
0x01
1000 Kbps
50 MHz
0x18
100 Kbps
0x06
357 Kbps
0x02
833 Kbps
80 MHz
0x27
100 Kbps
0x09
400 Kbps
0x03
1000 Kbps
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16.3.2.2
High-Speed Mode
The TM4C1237H6PZ I2C peripheral has support for High-speed operation as both a master and
slave. High-Speed mode is configured by setting the HS bit in the I2C Master Control/Status
(I2CMCS) register. High-Speed mode transmits data at a high bit rate with a 66.6%/33.3% duty
cycle, but communication and arbitration are done at Standard, Fast mode, or Fast-mode plus
speed, depending on which is selected by the user. When the HS bit in the I2CMCS register is set,
current mode pull-ups are enabled.
The clock period can be selected using the equation below, but in this case, SCL_LP=2 and
SCL_HP=1.
SCL_PERIOD = 2 × (1 + TIMER_PRD) × (SCL_LP + SCL_HP) × CLK_PRD
So for example:
CLK_PRD = 25 ns
TIMER_PRD = 1
SCL_LP=2
SCL_HP=1
yields a SCL frequency of:
1/T = 3.33 Mhz
Table 16-3 on page 998 gives examples of timer period and system clock in High-Speed mode. Note
that the HS bit in the I2CMTPR register needs to be set for the TPR value to be used in High-Speed
mode.
Table 16-3. Examples of I2C Master Timer Period in High-Speed Mode
System Clock
Timer Period
Transmission Mode
40 MHz
0x01
3.33 Mbps
50 MHz
0x02
2.77 Mbps
80 MHz
0x03
3.33 Mbps
When operating as a master, the protocol is shown in Figure 16-7. The master is responsible for
sending a master code byte in either Standard (100 Kbps) or Fast-mode (400 Kbps) before it begins
transferring in High-speed mode. The master code byte must contain data in the form of 0000.1XXX
and is used to tell the slave devices to prepare for a High-speed transfer. The master code byte
should never be acknowledged by a slave since it is only used to indicate that the upcoming data
is going to be transferred at a higher data rate. To send the master code byte, software should place
the value of the master code byte into the I2CMSA register and write the I2CMCS register with a
value of 0x13. This places the I2C master peripheral in High-speed mode, and all subsequent
transfers (until STOP) are carried out at High-speed data rate using the normal I2CMCS command
bits, without setting the HS bit in the I2CMCS register. Again, setting the HS bit in the I2CMCS register
is only necessary during the master code byte.
When operating as a High-speed slave, there is no additional software required.
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Figure 16-7. High-Speed Data Format
R/W
SDA
Device-Specific
NAK
Address
Data
SCL
Standard (100 KHz) or Fast Mode (400 KHz)
High Speed
(3.3 Mbps)
Note:
16.3.3
High-Speed mode is 3.4 Mbps, provided correct system clock frequency is set and there is
appropriate pull strength on SCL and SDA lines.
Interrupts
The I2C can generate interrupts when the following conditions are observed:
■ Master transaction completed
■ Master arbitration lost
■ Master transaction error
■ Master bus timeout
■ Slave transaction received
■ Slave transaction requested
■ Stop condition on bus detected
■ Start condition on bus detected
The I2C master and I2C slave modules have separate interrupt signals. While both modules can
generate interrupts for multiple conditions, only a single interrupt signal is sent to the interrupt
controller.
16.3.3.1
I2C Master Interrupts
The I2C master module generates an interrupt when a transaction completes (either transmit or
receive), when arbitration is lost, or when an error occurs during a transaction. To enable the I2C
master interrupt, software must set the IM bit in the I2C Master Interrupt Mask (I2CMIMR) register.
When an interrupt condition is met, software must check the ERROR and ARBLST bits in the I2C
Master Control/Status (I2CMCS) register to verify that an error didn't occur during the last transaction
and to ensure that arbitration has not been lost. An error condition is asserted if the last transaction
wasn't acknowledged by the slave. If an error is not detected and the master has not lost arbitration,
the application can proceed with the transfer. The interrupt is cleared by writing a 1 to the IC bit in
the I2C Master Interrupt Clear (I2CMICR) register.
If the application doesn't require the use of interrupts, the raw interrupt status is always visible via
the I2C Master Raw Interrupt Status (I2CMRIS) register.
16.3.3.2
I2C Slave Interrupts
The slave module can generate an interrupt when data has been received or requested. This interrupt
is enabled by setting the DATAIM bit in the I2C Slave Interrupt Mask (I2CSIMR) register. Software
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determines whether the module should write (transmit) or read (receive) data from the I2C Slave
Data (I2CSDR) register, by checking the RREQ and TREQ bits of the I2C Slave Control/Status
(I2CSCSR) register. If the slave module is in receive mode and the first byte of a transfer is received,
the FBR bit is set along with the RREQ bit. The interrupt is cleared by setting the DATAIC bit in the
I2C Slave Interrupt Clear (I2CSICR) register.
In addition, the slave module can generate an interrupt when a start and stop condition is detected.
These interrupts are enabled by setting the STARTIM and STOPIM bits of the I2C Slave Interrupt
Mask (I2CSIMR) register and cleared by writing a 1 to the STOPIC and STARTIC bits of the I2C
Slave Interrupt Clear (I2CSICR) register.
If the application doesn't require the use of interrupts, the raw interrupt status is always visible via
the I2C Slave Raw Interrupt Status (I2CSRIS) register.
16.3.4
Loopback Operation
The I2C modules can be placed into an internal loopback mode for diagnostic or debug work by
setting the LPBK bit in the I2C Master Configuration (I2CMCR) register. In loopback mode, the
SDA and SCL signals from the master and are tied to the SDA and SCL signals of the slave module
to allow internal testing of the device without having to go through I/O.
16.3.5
Command Sequence Flow Charts
This section details the steps required to perform the various I2C transfer types in both master and
slave mode.
16.3.5.1
I2C Master Command Sequences
The figures that follow show the command sequences available for the I2C master.
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Figure 16-8. Master Single TRANSMIT
Idle
Write Slave
Address to
I2CMSA
Sequence
may be
omitted in a
Single Master
system
Write data to
I2CMDR
Read I2CMCS
NO
BUSBSY bit=0?
YES
Write ---0-111
to I2CMCS
Read I2CMCS
NO
BUSY bit=0?
YES
Error Service
NO
ERROR bit=0?
YES
Idle
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Figure 16-9. Master Single RECEIVE
Idle
Write Slave
Address to
I2CMSA
Sequence may be
omitted in a Single
Master system
Read I2CMCS
NO
BUSBSY bit=0?
YES
Write ---00111
to I2CMCS
Read I2CMCS
NO
BUSY bit=0?
YES
Error Service
NO
ERROR bit=0?
YES
Read data from
I2CMDR
Idle
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Figure 16-10. Master TRANSMIT of Multiple Data Bytes
Idle
Write Slave
Address to
I2CMSA
Sequence
may be
omitted in a
Single Master
system
Read I2CMCS
Write data to
I2CMDR
BUSY bit=0?
YES
Read I2CMCS
ERROR bit=0?
NO
NO
NO
BUSBSY bit=0?
YES
Write data to
I2CMDR
YES
Write ---0-011
to I2CMCS
NO
ARBLST bit=1?
YES
Write ---0-001
to I2CMCS
NO
Index=n?
YES
Write ---0-101
to I2CMCS
Write ---0-100
to I2CMCS
Error Service
Idle
Read I2CMCS
NO
BUSY bit=0?
YES
Error Service
NO
ERROR bit=0?
YES
Idle
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Figure 16-11. Master RECEIVE of Multiple Data Bytes
Idle
Write Slave
Address to
I2CMSA
Sequence
may be
omitted in a
Single Master
system
Read I2CMCS
BUSY bit=0?
Read I2CMCS
NO
YES
NO
BUSBSY bit=0?
ERROR bit=0?
NO
YES
Write ---01011
to I2CMCS
NO
Read data from
I2CMDR
ARBLST bit=1?
YES
Write ---01001
to I2CMCS
NO
Write ---0-100
to I2CMCS
Index=m-1?
Error Service
YES
Write ---00101
to I2CMCS
Idle
Read I2CMCS
BUSY bit=0?
NO
YES
NO
ERROR bit=0?
YES
Error Service
Read data from
I2CMDR
Idle
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Figure 16-12. Master RECEIVE with Repeated START after Master TRANSMIT
Idle
Master operates in
Master Transmit mode
STOP condition is not
generated
Write Slave
Address to
I2CMSA
Write ---01011
to I2CMCS
Master operates in
Master Receive mode
Repeated START
condition is generated
with changing data
direction
Idle
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Figure 16-13. Master TRANSMIT with Repeated START after Master RECEIVE
Idle
Master operates in
Master Receive mode
STOP condition is not
generated
Write Slave
Address to
I2CMSA
Write ---0-011
to I2CMCS
Master operates in
Master Transmit mode
Repeated START
condition is generated
with changing data
direction
Idle
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Figure 16-14. Standard High Speed Mode Master Transmit
IDLE
write slave address
to I2CMSA register
Master code and
arbitration is always
done in FAST or
STANDARD mode
write „---10011”
to I2CMCS register
read I2CMCS register
no
Busy=’0'
yes
no
IDLE
Error=’0'
yes
Normal sequence starts here. The
sequence below covers SINGLE send
write Slave Address
to I2MSA register
write Data
to I2CMDR register
write „---0-111”
to I2CMCS register
read I2CMCS register
no
Busy=’0'
yes
yes
IDLE
Error=’0'
no
Error service
IDLE
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16.3.5.2
I2C Slave Command Sequences
Figure 16-15 on page 1008 presents the command sequence available for the I2C slave.
Figure 16-15. Slave Command Sequence
Idle
Write OWN Slave
Address to
I2CSOAR
Write -------1
to I2CSCSR
Read I2CSCSR
NO
TREQ bit=1?
YES
Write data to
I2CSDR
NO
RREQ bit=1?
FBR is
also valid
YES
Read data from
I2CSDR
16.4
Initialization and Configuration
16.4.1
Configure the I2C Module to Transmit a Single Byte as a Master
The following example shows how to configure the I2C module to transmit a single byte as a master.
This assumes the system clock is 20 MHz.
1. Enable the I2C clock using the RCGCI2C register in the System Control module (see page 340).
2. Enable the clock to the appropriate GPIO module via the RCGCGPIO register in the System
Control module (see page 331). To find out which GPIO port to enable, refer to Table
21-5 on page 1249.
3. In the GPIO module, enable the appropriate pins for their alternate function using the
GPIOAFSEL register (see page 659). To determine which GPIOs to configure, see Table
21-4 on page 1242.
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4. Enable the I2CSDA pin for open-drain operation. See page 664.
5. Configure the PMCn fields in the GPIOPCTL register to assign the I2C signals to the appropriate
pins. See page 677 and Table 21-5 on page 1249.
6. Initialize the I2C Master by writing the I2CMCR register with a value of 0x0000.0010.
7. Set the desired SCL clock speed of 100 Kbps by writing the I2CMTPR register with the correct
value. The value written to the I2CMTPR register represents the number of system clock periods
in one SCL clock period. The TPR value is determined by the following equation:
TPR = (System Clock/(2*(SCL_LP + SCL_HP)*SCL_CLK))-1;
TPR = (20MHz/(2*(6+4)*100000))-1;
TPR = 9
Write the I2CMTPR register with the value of 0x0000.0009.
8. Specify the slave address of the master and that the next operation is a Transmit by writing the
I2CMSA register with a value of 0x0000.0076. This sets the slave address to 0x3B.
9. Place data (byte) to be transmitted in the data register by writing the I2CMDR register with the
desired data.
10. Initiate a single byte transmit of the data from Master to Slave by writing the I2CMCS register
with a value of 0x0000.0007 (STOP, START, RUN).
11. Wait until the transmission completes by polling the I2CMCS register's BUSBSY bit until it has
been cleared.
12. Check the ERROR bit in the I2CMCS register to confirm the transmit was acknowledged.
16.4.2
Configure the I2C Master to High Speed Mode
To configure the I2C master to High Speed mode:
1. Enable the I2C clock using the RCGCI2C register in the System Control module (see page 340).
2. Enable the clock to the appropriate GPIO module via the RCGCGPIO register in the System
Control module (see page 331). To find out which GPIO port to enable, refer to Table
21-5 on page 1249.
3. In the GPIO module, enable the appropriate pins for their alternate function using the
GPIOAFSEL register (see page 659). To determine which GPIOs to configure, see Table
21-4 on page 1242.
4. Enable the I2CSDA pin for open-drain operation. See page 664.
5. Configure the PMCn fields in the GPIOPCTL register to assign the I2C signals to the appropriate
pins. See page 677 and Table 21-5 on page 1249.
6. Initialize the I2C Master by writing the I2CMCR register with a value of 0x0000.0010.
7. Set the desired SCL clock speed of 3.33 Mbps by writing the I2CMTPR register with the correct
value. The value written to the I2CMTPR register represents the number of system clock periods
in one SCL clock period. The TPR value is determined by the following equation:
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TPR = (System Clock/(2*(SCL_LP + SCL_HP)*SCL_CLK))-1;
TPR = (80 MHz/(2*(2+1)*3330000))-1;
TPR = 3
Write the I2CMTPR register with the value of 0x0000.0003.
8. To send the master code byte, software should place the value of the master code byte into the
I2CMSA register and write the I2CMCS register with a value of 0x13.
9. This places the I2C master peripheral in High-speed mode, and all subsequent transfers (until
STOP) are carried out at High-speed data rate using the normal I2CMCS command bits, without
setting the HS bit in the I2CMCS register.
10. The transaction is ended by setting the STOP bit in the I2CMCS register.
11. Wait until the transmission completes by polling the I2CMCS register's BUSBSY bit until it has
been cleared.
12. Check the ERROR bit in the I2CMCS register to confirm the transmit was acknowledged.
16.5
Register Map
Table 16-4 on page 1010 lists the I2C registers. All addresses given are relative to the I2C base address:
■
■
■
■
■
■
I2C 0: 0x4002.0000
I2C 1: 0x4002.1000
I2C 2: 0x4002.2000
I2C 3: 0x4002.3000
I2C 4: 0x400C.0000
I2C 5: 0x400C.1000
Note that the I2C module clock must be enabled before the registers can be programmed (see
page 340). There must be a delay of 3 system clocks after the I2C module clock is enabled before
any I2C module registers are accessed.
The hw_i2c.h file in the TivaWare™ Driver Library uses a base address of 0x800 for the I2C slave
registers. Be aware when using registers with offsets between 0x800 and 0x818 that TivaWare™
for C Series uses an offset between 0x000 and 0x018 with the slave base address.
Table 16-4. Inter-Integrated Circuit (I2C) Interface Register Map
Offset
Name
Type
Reset
Description
See
page
I2C Master
0x000
I2CMSA
RW
0x0000.0000
I2C Master Slave Address
1012
0x004
I2CMCS
RW
0x0000.0020
I2C Master Control/Status
1013
0x008
I2CMDR
RW
0x0000.0000
I2C Master Data
1018
0x00C
I2CMTPR
RW
0x0000.0001
I2C Master Timer Period
1019
0x010
I2CMIMR
RW
0x0000.0000
I2C Master Interrupt Mask
1020
0x014
I2CMRIS
RO
0x0000.0000
I2C Master Raw Interrupt Status
1021
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Table 16-4. Inter-Integrated Circuit (I2C) Interface Register Map (continued)
Description
See
page
0x0000.0000
I2C Master Masked Interrupt Status
1022
WO
0x0000.0000
I2C Master Interrupt Clear
1023
I2CMCR
RW
0x0000.0000
I2C Master Configuration
1024
0x024
I2CMCLKOCNT
RW
0x0000.0000
I2C Master Clock Low Timeout Count
1026
0x02C
I2CMBMON
RO
0x0000.0003
I2C Master Bus Monitor
1027
0x038
I2CMCR2
RW
0x0000.0000
I2C Master Configuration 2
1028
0x800
I2CSOAR
RW
0x0000.0000
I2C Slave Own Address
1029
0x804
I2CSCSR
RO
0x0000.0000
I2C Slave Control/Status
1030
0x808
I2CSDR
RW
0x0000.0000
I2C Slave Data
1032
0x80C
I2CSIMR
RW
0x0000.0000
I2C Slave Interrupt Mask
1033
0x810
I2CSRIS
RO
0x0000.0000
I2C Slave Raw Interrupt Status
1034
0x814
I2CSMIS
RO
0x0000.0000
I2C Slave Masked Interrupt Status
1035
0x818
I2CSICR
WO
0x0000.0000
I2C Slave Interrupt Clear
1036
0x81C
I2CSOAR2
RW
0x0000.0000
I2C Slave Own Address 2
1037
0x820
I2CSACKCTL
RW
0x0000.0000
I2C Slave ACK Control
1038
Offset
Name
Type
Reset
0x018
I2CMMIS
RO
0x01C
I2CMICR
0x020
I2C Slave
I2C Status and Control
0xFC0
I2CPP
RO
0x0000.0001
I2C Peripheral Properties
1039
0xFC4
I2CPC
RO
0x0000.0001
I2C Peripheral Configuration
1040
16.6
Register Descriptions (I2C Master)
The remainder of this section lists and describes the I2C master registers, in numerical order by
address offset.
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Register 1: I2C Master Slave Address (I2CMSA), offset 0x000
This register consists of eight bits: seven address bits (A6-A0), and a Receive/Send bit, which
determines if the next operation is a Receive (High), or Transmit (Low).
I2C Master Slave Address (I2CMSA)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
Offset 0x000
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
4
3
2
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
SA
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:1
SA
RW
0x00
RO
0
RW
0
RW
0
RW
0
RW
0
0
R/S
RW
0
RW
0
RW
0
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
I2C Slave Address
This field specifies bits A6 through A0 of the slave address.
0
R/S
RW
0
Receive/Send
The R/S bit specifies if the next master operation is a Receive (High)
or Transmit (Low).
Value Description
0
Transmit
1
Receive
1012
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Register 2: I2C Master Control/Status (I2CMCS), offset 0x004
This register accesses status bits when read and control bits when written. When read, the status
register indicates the state of the I2C bus controller. When written, the control register configures
the I2C controller operation.
The START bit generates the START or REPEATED START condition. The STOP bit determines if
the cycle stops at the end of the data cycle or continues to the next transfer cycle, which could be
a repeated START. To generate a single transmit cycle, the I2C Master Slave Address (I2CMSA)
register is written with the desired address, the R/S bit is cleared, and this register is written with
ACK=X (0 or 1), STOP=1, START=1, and RUN=1 to perform the operation and stop. When the operation
is completed (or aborted due an error), an interrupt becomes active and the data may be read from
the I2CMDR register. When the I2C module operates in Master receiver mode, the ACK bit is normally
set, causing the I2C bus controller to transmit an acknowledge automatically after each byte. This
bit must be cleared when the I2C bus controller requires no further data to be transmitted from the
slave transmitter.
Read-Only Status Register
I2C Master Control/Status (I2CMCS)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
Offset 0x004
Type RO, reset 0x0000.0020
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
CLKTO
BUSBSY
IDLE
ARBLST
ERROR
BUSY
RO
0
RO
0
RO
1
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7
CLKTO
RO
0
DATACK ADRACK
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Clock Timeout Error
Value Description
0
No clock timeout error.
1
The clock timeout error has occurred.
This bit is cleared when the master sends a STOP condition or if the
I2C master is reset.
June 12, 2014
1013
Texas Instruments-Production Data
Inter-Integrated Circuit (I2C) Interface
Bit/Field
Name
Type
Reset
6
BUSBSY
RO
0
Description
Bus Busy
Value Description
0
The I2C bus is idle.
1
The I2C bus is busy.
The bit changes based on the START and STOP conditions.
5
IDLE
RO
1
I2C Idle
Value Description
4
ARBLST
RO
0
0
The I2C controller is not idle.
1
The I2C controller is idle.
Arbitration Lost
Value Description
3
DATACK
RO
0
0
The I2C controller won arbitration.
1
The I2C controller lost arbitration.
Acknowledge Data
Value Description
2
ADRACK
RO
0
0
The transmitted data was acknowledged
1
The transmitted data was not acknowledged.
Acknowledge Address
Value Description
1
ERROR
RO
0
0
The transmitted address was acknowledged
1
The transmitted address was not acknowledged.
Error
Value Description
0
No error was detected on the last operation.
1
An error occurred on the last operation.
The error can be from the slave address not being acknowledged or the
transmit data not being acknowledged.
0
BUSY
RO
0
I2C Busy
Value Description
0
The controller is idle.
1
The controller is busy.
When the BUSY bit is set, the other status bits are not valid.
1014
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Write-Only Control Register
I2C Master Control/Status (I2CMCS)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
Offset 0x004
Type WO, reset 0x0000.0020
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
10
9
8
7
6
5
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
4
3
2
1
0
HS
ACK
STOP
START
RUN
WO
0
WO
0
WO
0
WO
0
WO
0
Bit/Field
Name
Type
Reset
Description
31:5
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
4
HS
WO
0
High-Speed Enable
Value Description
3
ACK
WO
0
0
The master operates in Standard, Fast mode, or Fast mode
plus as selected by using a value in the I2CMTPR register that
results in an SCL frequency of 100 kbps for Standard mode,
400 kbps for Fast mode, or 1 Mpbs for Fast mode plus.
1
The master operates in High-Speed mode with transmission
speeds up to 3.33 Mbps.
Data Acknowledge Enable
Value Description
2
STOP
WO
0
0
The received data byte is not acknowledged automatically by
the master.
1
The received data byte is acknowledged automatically by the
master. See field decoding in Table 16-5 on page 1016.
Generate STOP
Value Description
0
The controller does not generate the STOP condition.
1
The controller generates the STOP condition. See field decoding
in Table 16-5 on page 1016.
June 12, 2014
1015
Texas Instruments-Production Data
Inter-Integrated Circuit (I2C) Interface
Bit/Field
Name
Type
Reset
1
START
WO
0
Description
Generate START
Value Description
0
RUN
WO
0
The controller does not generate the START condition.
1
The controller generates the START or repeated START
condition. See field decoding in Table 16-5 on page 1016.
I2C Master Enable
0
Value Description
0
This encoding means the master is unable to transmit or receive
data.
1
The master is able to transmit or receive data.
See field decoding in Table 16-5 on page 1016.
Table 16-5. Write Field Decoding for I2CMCS[3:0] Field
Current I2CMSA[0]
State
R/S
Idle
I2CMCS[3:0]
ACK
STOP
START
RUN
Description
0
X
a
0
1
1
START condition followed by TRANSMIT (master goes
to the Master Transmit state).
0
X
1
1
1
START condition followed by a TRANSMIT and STOP
condition (master remains in Idle state).
1
0
0
1
1
START condition followed by RECEIVE operation with
negative ACK (master goes to the Master Receive state).
1
0
1
1
1
START condition followed by RECEIVE and STOP
condition (master remains in Idle state).
1
1
0
1
1
START condition followed by RECEIVE (master goes to
the Master Receive state).
1
1
1
1
1
Illegal
All other combinations not listed are non-operations.
NOP
1016
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Table 16-5. Write Field Decoding for I2CMCS[3:0] Field (continued)
Current I2CMSA[0]
State
R/S
Master
Transmit
I2CMCS[3:0]
Description
ACK
STOP
START
RUN
X
X
0
0
1
TRANSMIT operation (master remains in Master
Transmit state).
X
X
1
0
0
STOP condition (master goes to Idle state).
X
X
1
0
1
TRANSMIT followed by STOP condition (master goes
to Idle state).
0
X
0
1
1
Repeated START condition followed by a TRANSMIT
(master remains in Master Transmit state).
0
X
1
1
1
Repeated START condition followed by TRANSMIT and
STOP condition (master goes to Idle state).
1
0
0
1
1
Repeated START condition followed by a RECEIVE
operation with a negative ACK (master goes to Master
Receive state).
1
0
1
1
1
Repeated START condition followed by a TRANSMIT
and STOP condition (master goes to Idle state).
1
1
0
1
1
Repeated START condition followed by RECEIVE
(master goes to Master Receive state).
1
1
1
1
1
Illegal.
All other combinations not listed are non-operations.
NOP.
X
0
0
0
1
RECEIVE operation with negative ACK (master remains
in Master Receive state).
X
X
1
0
0
STOP condition (master goes to Idle state).
X
0
1
0
1
RECEIVE followed by STOP condition (master goes to
Idle state).
X
1
0
0
1
RECEIVE operation (master remains in Master Receive
state).
X
1
1
0
1
Illegal.
1
0
0
1
1
Repeated START condition followed by RECEIVE
operation with a negative ACK (master remains in Master
Receive state).
1
0
1
1
1
Repeated START condition followed by RECEIVE and
STOP condition (master goes to Idle state).
1
1
0
1
1
Repeated START condition followed by RECEIVE
(master remains in Master Receive state).
0
X
0
1
1
Repeated START condition followed by TRANSMIT
(master goes to Master Transmit state).
0
X
1
1
1
Repeated START condition followed by TRANSMIT and
STOP condition (master goes to Idle state).
Master
Receive
All other combinations not listed are non-operations.
b
NOP.
a. An X in a table cell indicates the bit can be 0 or 1.
b. In Master Receive mode, a STOP condition should be generated only after a Data Negative Acknowledge executed by
the master or an Address Negative Acknowledge executed by the slave.
June 12, 2014
1017
Texas Instruments-Production Data
Inter-Integrated Circuit (I2C) Interface
Register 3: I2C Master Data (I2CMDR), offset 0x008
Important: This register is read-sensitive. See the register description for details.
This register contains the data to be transmitted when in the Master Transmit state and the data
received when in the Master Receive state.
I2C Master Data (I2CMDR)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
Offset 0x008
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
reserved
Type
Reset
DATA
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
DATA
RW
0x00
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
This byte contains the data transferred during a transaction.
1018
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Register 4: I2C Master Timer Period (I2CMTPR), offset 0x00C
This register is programmed to set the timer period for the SCL clock and assign the SCL clock to
either standard or high-speed mode.
I2C Master Timer Period (I2CMTPR)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
Offset 0x00C
Type RW, reset 0x0000.0001
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RW
0
RW
0
RW
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
HS
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7
HS
WO
0x0
RO
0
WO
0
TPR
RW
0
RW
0
RW
0
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
High-Speed Enable
Value Description
6:0
TPR
RW
0x1
0
The SCL Clock Period set by TPR applies to Standard mode
(100 Kbps), Fast-mode (400 Kbps), or Fast-mode plus (1 Mbps).
1
The SCL Clock Period set by TPR applies to High-speed mode
(3.33 Mbps).
Timer Period
This field is used in the equation to configure SCL_PERIOD:
SCL_PERIOD = 2×(1 + TPR)×(SCL_LP + SCL_HP)×CLK_PRD
where:
SCL_PRD is the SCL line period (I2C clock).
TPR is the Timer Period register value (range of 1 to 127).
SCL_LP is the SCL Low period (fixed at 6).
SCL_HP is the SCL High period (fixed at 4).
CLK_PRD is the system clock period in ns.
June 12, 2014
1019
Texas Instruments-Production Data
Inter-Integrated Circuit (I2C) Interface
Register 5: I2C Master Interrupt Mask (I2CMIMR), offset 0x010
This register controls whether a raw interrupt is promoted to a controller interrupt.
I2C Master Interrupt Mask (I2CMIMR)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
Offset 0x010
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
1
0
CLKIM
IM
RW
0
RW
0
Bit/Field
Name
Type
Reset
Description
31:2
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1
CLKIM
RW
0
Clock Timeout Interrupt Mask
Value Description
0
IM
RW
0
0
The CLKRIS interrupt is suppressed and not sent to the interrupt
controller.
1
The clock timeout interrupt is sent to the interrupt controller
when the CLKRIS bit in the I2CMRIS register is set.
Master Interrupt Mask
Value Description
0
The RIS interrupt is suppressed and not sent to the interrupt
controller.
1
The master interrupt is sent to the interrupt controller when the
RIS bit in the I2CMRIS register is set.
1020
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Register 6: I2C Master Raw Interrupt Status (I2CMRIS), offset 0x014
This register specifies whether an interrupt is pending.
I2C Master Raw Interrupt Status (I2CMRIS)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
Offset 0x014
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
1
0
CLKRIS
RIS
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:2
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1
CLKRIS
RO
0
Clock Timeout Raw Interrupt Status
Value Description
0
No interrupt.
1
The clock timeout interrupt is pending.
This bit is cleared by writing a 1 to the CLKIC bit in the I2CMICR register.
0
RIS
RO
0
Master Raw Interrupt Status
Value Description
0
No interrupt.
1
A master interrupt is pending.
This bit is cleared by writing a 1 to the IC bit in the I2CMICR register.
June 12, 2014
1021
Texas Instruments-Production Data
Inter-Integrated Circuit (I2C) Interface
Register 7: I2C Master Masked Interrupt Status (I2CMMIS), offset 0x018
This register specifies whether an interrupt was signaled.
I2C Master Masked Interrupt Status (I2CMMIS)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
Offset 0x018
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
1
0
CLKMIS
MIS
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:2
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1
CLKMIS
RO
0
Clock Timeout Masked Interrupt Status
Value Description
0
No interrupt.
1
An unmasked clock timeout interrupt was signaled and is
pending.
This bit is cleared by writing a 1 to the CLKIC bit in the I2CMICR register.
0
MIS
RO
0
Masked Interrupt Status
Value Description
0
An interrupt has not occurred or is masked.
1
An unmasked master interrupt was signaled and is pending.
This bit is cleared by writing a 1 to the IC bit in the I2CMICR register.
1022
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Register 8: I2C Master Interrupt Clear (I2CMICR), offset 0x01C
This register clears the raw and masked interrupts.
I2C Master Interrupt Clear (I2CMICR)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
Offset 0x01C
Type WO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
1
0
CLKIC
IC
WO
0
WO
0
Bit/Field
Name
Type
Reset
Description
31:2
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1
CLKIC
WO
0
Clock Timeout Interrupt Clear
Writing a 1 to this bit clears the CLKRIS bit in the I2CMRIS register and
the CLKMIS bit in the I2CMMIS register.
A read of this register returns no meaningful data.
0
IC
WO
0
Master Interrupt Clear
Writing a 1 to this bit clears the RIS bit in the I2CMRIS register and the
MIS bit in the I2CMMIS register.
A read of this register returns no meaningful data.
June 12, 2014
1023
Texas Instruments-Production Data
Inter-Integrated Circuit (I2C) Interface
Register 9: I2C Master Configuration (I2CMCR), offset 0x020
This register configures the mode (Master or Slave), enables the glitch filter, and sets the interface
for test mode loopback.
I2C Master Configuration (I2CMCR)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
Offset 0x020
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
3
2
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
15
14
13
12
RO
0
RO
0
RO
0
RO
0
RO
0
11
10
9
8
7
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:7
reserved
RO
0x0000.00
6
GFE
RW
0
RO
0
RO
0
6
5
4
GFE
SFE
MFE
RW
0
RW
0
RW
0
reserved
RO
0
RO
0
0
LPBK
RO
0
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
I2C Glitch Filter Enable
Value Description
0
I2C glitch filter is disabled.
1
I2C glitch filter is enabled.
Use the GFPW bit in the I2C Master Configuration 2 (I2CMCR2) register
to program the pulse width.
5
SFE
RW
0
I2C Slave Function Enable
Value Description
4
MFE
RW
0
0
Slave mode is disabled.
1
Slave mode is enabled.
I2C Master Function Enable
Value Description
3:1
reserved
RO
0x0
0
Master mode is disabled.
1
Master mode is enabled.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1024
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Bit/Field
Name
Type
Reset
0
LPBK
RW
0
Description
I2C Loopback
Value Description
0
Normal operation.
1
The controller in a test mode loopback configuration.
June 12, 2014
1025
Texas Instruments-Production Data
Inter-Integrated Circuit (I2C) Interface
Register 10: I2C Master Clock Low Timeout Count (I2CMCLKOCNT), offset
0x024
This register contains the upper 8 bits of a 12-bit counter that can be used to keep the timeout limit
for clock stretching by a remote slave. The lower four bits of the counter are not user visible and
are always 0x0.
Note:
The Master Clock Low Timeout counter counts for the entire time SCL is held Low
continuously. If SCL is deasserted at any point, the Master Clock Low Timeout Counter is
reloaded with the value in the I2CMCLKOCNT register and begins counting down from this
value.
I2C Master Clock Low Timeout Count (I2CMCLKOCNT)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
Offset 0x024
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
reserved
Type
Reset
CNTL
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
CNTL
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
I2C Master Count
This field contains the upper 8 bits of a 12-bit counter for the clock low
timeout count.
Note:
The value of CNTL must be greater than 0x1.
1026
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Register 11: I2C Master Bus Monitor (I2CMBMON), offset 0x02C
This register is used to determine the SCL and SDA signal status.
I2C Master Bus Monitor (I2CMBMON)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
Offset 0x02C
Type RO, reset 0x0000.0003
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:2
reserved
RO
0x0000.000
1
SDA
RO
1
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
1
0
SDA
SCL
RO
1
RO
1
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
I2C SDA Status
Value Description
0
SCL
RO
1
0
The I2CSDA signal is low.
1
The I2CSDA signal is high.
I2C SCL Status
Value Description
0
The I2CSCL signal is low.
1
The I2CSCL signal is high.
June 12, 2014
1027
Texas Instruments-Production Data
Inter-Integrated Circuit (I2C) Interface
Register 12: I2C Master Configuration 2 (I2CMCR2), offset 0x038
This register can be programmed to select the pulse width for glitch suppression, measured in
system clocks.
I2C Master Configuration 2 (I2CMCR2)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
Offset 0x038
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
5
4
3
2
1
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
15
14
13
12
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
11
10
9
8
7
6
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
GFPW
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
RW
0
reserved
RW
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:7
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
6:4
GFPW
RW
0
I2C Glitch Filter Pulse Width
This field controls the pulse width select for glitch suppression on the
SCL and SDA lines. Glitch suppression values can be programmed
relative to system clocks.
Value Description
3:0
16.7
reserved
RO
0
0x0
Bypass
0x1
1 clock
0x2
2 clocks
0x3
3 clocks
0x4
4 clocks
0x5
8 clocks
0x6
16 clocks
0x7
31 clocks
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Register Descriptions (I2C Slave)
The remainder of this section lists and describes the I2C slave registers, in numerical order by
address offset.
1028
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Register 13: I2C Slave Own Address (I2CSOAR), offset 0x800
This register consists of seven address bits that identify the TM4C1237H6PZ I2C device on the I2C
bus.
I2C Slave Own Address (I2CSOAR)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
Offset 0x800
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
reserved
Type
Reset
OAR
RO
0
Bit/Field
Name
Type
Reset
31:7
reserved
RO
0x0000.00
6:0
OAR
RW
0x00
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
I2C Slave Own Address
This field specifies bits A6 through A0 of the slave address.
June 12, 2014
1029
Texas Instruments-Production Data
Inter-Integrated Circuit (I2C) Interface
Register 14: I2C Slave Control/Status (I2CSCSR), offset 0x804
This register functions as a control register when written, and a status register when read.
Read-Only Status Register
I2C Slave Control/Status (I2CSCSR)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
Offset 0x804
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
OAR2SEL
FBR
TREQ
RREQ
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:4
reserved
RO
0x0000.000
3
OAR2SEL
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
OAR2 Address Matched
Value Description
0
Either the address is not matched or the match is in legacy
mode.
1
OAR2 address matched and ACKed by the slave.
This bit gets reevaluated after every address comparison.
2
FBR
RO
0
First Byte Received
Value Description
0
The first byte has not been received.
1
The first byte following the slave's own address has been
received.
This bit is only valid when the RREQ bit is set and is automatically cleared
when data has been read from the I2CSDR register.
Note:
This bit is not used for slave transmit operations.
1030
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Bit/Field
Name
Type
Reset
1
TREQ
RO
0
Description
Transmit Request
Value Description
0
RREQ
RO
0
0
No outstanding transmit request.
1
The I2C controller has been addressed as a slave transmitter
and is using clock stretching to delay the master until data has
been written to the I2CSDR register.
Receive Request
Value Description
0
No outstanding receive data.
1
The I2C controller has outstanding receive data from the I2C
master and is using clock stretching to delay the master until
the data has been read from the I2CSDR register.
Write-Only Control Register
I2C Slave Control/Status (I2CSCSR)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
Offset 0x804
Type WO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:1
reserved
RO
0x0000.000
0
DA
WO
0
RO
0
0
DA
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
WO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Device Active
Value Description
0
Disables the I2C slave operation.
1
Enables the I2C slave operation.
Once this bit has been set, it should not be set again unless it has been
cleared by writing a 0 or by a reset, otherwise transfer failures may
occur.
June 12, 2014
1031
Texas Instruments-Production Data
Inter-Integrated Circuit (I2C) Interface
Register 15: I2C Slave Data (I2CSDR), offset 0x808
Important: This register is read-sensitive. See the register description for details.
This register contains the data to be transmitted when in the Slave Transmit state, and the data
received when in the Slave Receive state.
I2C Slave Data (I2CSDR)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
Offset 0x808
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
reserved
Type
Reset
DATA
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
DATA
RW
0x00
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Data for Transfer
This field contains the data for transfer during a slave receive or transmit
operation.
1032
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Register 16: I2C Slave Interrupt Mask (I2CSIMR), offset 0x80C
This register controls whether a raw interrupt is promoted to a controller interrupt.
I2C Slave Interrupt Mask (I2CSIMR)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
Offset 0x80C
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
2
1
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
9
8
7
6
5
4
3
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
STOPIM STARTIM DATAIM
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
RW
0
RW
0
Bit/Field
Name
Type
Reset
Description
31:3
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2
STOPIM
RW
0
Stop Condition Interrupt Mask
Value Description
1
STARTIM
RW
0
0
The STOPRIS interrupt is suppressed and not sent to the
interrupt controller.
1
The STOP condition interrupt is sent to the interrupt controller
when the STOPRIS bit in the I2CSRIS register is set.
Start Condition Interrupt Mask
Value Description
0
DATAIM
RW
0
0
The STARTRIS interrupt is suppressed and not sent to the
interrupt controller.
1
The START condition interrupt is sent to the interrupt controller
when the STARTRIS bit in the I2CSRIS register is set.
Data Interrupt Mask
Value Description
0
The DATARIS interrupt is suppressed and not sent to the
interrupt controller.
1
The data received or data requested interrupt is sent to the
interrupt controller when the DATARIS bit in the I2CSRIS register
is set.
June 12, 2014
1033
Texas Instruments-Production Data
Inter-Integrated Circuit (I2C) Interface
Register 17: I2C Slave Raw Interrupt Status (I2CSRIS), offset 0x810
This register specifies whether an interrupt is pending.
I2C Slave Raw Interrupt Status (I2CSRIS)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
Offset 0x810
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
2
1
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
9
8
7
6
5
4
3
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
STOPRIS STARTRIS DATARIS
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:3
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2
STOPRIS
RO
0
Stop Condition Raw Interrupt Status
Value Description
0
No interrupt.
1
A STOP condition interrupt is pending.
This bit is cleared by writing a 1 to the STOPIC bit in the I2CSICR
register.
1
STARTRIS
RO
0
Start Condition Raw Interrupt Status
Value Description
0
No interrupt.
1
A START condition interrupt is pending.
This bit is cleared by writing a 1 to the STARTIC bit in the I2CSICR
register.
0
DATARIS
RO
0
Data Raw Interrupt Status
Value Description
0
No interrupt.
1
A data received or data requested interrupt is pending.
This bit is cleared by writing a 1 to the DATAIC bit in the I2CSICR
register.
1034
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Register 18: I2C Slave Masked Interrupt Status (I2CSMIS), offset 0x814
This register specifies whether an interrupt was signaled.
I2C Slave Masked Interrupt Status (I2CSMIS)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
Offset 0x814
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
2
1
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
9
8
7
6
5
4
3
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
STOPMIS STARTMIS DATAMIS
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:3
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2
STOPMIS
RO
0
Stop Condition Masked Interrupt Status
Value Description
0
An interrupt has not occurred or is masked.
1
An unmasked STOP condition interrupt was signaled is pending.
This bit is cleared by writing a 1 to the STOPIC bit in the I2CSICR
register.
1
STARTMIS
RO
0
Start Condition Masked Interrupt Status
Value Description
0
An interrupt has not occurred or is masked.
1
An unmasked START condition interrupt was signaled is
pending.
This bit is cleared by writing a 1 to the STARTIC bit in the I2CSICR
register.
0
DATAMIS
RO
0
Data Masked Interrupt Status
Value Description
0
An interrupt has not occurred or is masked.
1
An unmasked data received or data requested interrupt was
signaled is pending.
This bit is cleared by writing a 1 to the DATAIC bit in the I2CSICR
register.
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Inter-Integrated Circuit (I2C) Interface
Register 19: I2C Slave Interrupt Clear (I2CSICR), offset 0x818
This register clears the raw interrupt. A read of this register returns no meaningful data.
I2C Slave Interrupt Clear (I2CSICR)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
Offset 0x818
Type WO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
2
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
9
8
7
6
5
4
3
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
STOPIC STARTIC
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
WO
0
WO
0
0
DATAIC
WO
0
Bit/Field
Name
Type
Reset
Description
31:3
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2
STOPIC
WO
0
Stop Condition Interrupt Clear
Writing a 1 to this bit clears the STOPRIS bit in the I2CSRIS register
and the STOPMIS bit in the I2CSMIS register.
A read of this register returns no meaningful data.
1
STARTIC
WO
0
Start Condition Interrupt Clear
Writing a 1 to this bit clears the STARTRIS bit in the I2CSRIS register
and the STARTMIS bit in the I2CSMIS register.
A read of this register returns no meaningful data.
0
DATAIC
WO
0
Data Interrupt Clear
Writing a 1 to this bit clears the STOPRIS bit in the I2CSRIS register
and the STOPMIS bit in the I2CSMIS register.
A read of this register returns no meaningful data.
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Register 20: I2C Slave Own Address 2 (I2CSOAR2), offset 0x81C
This register consists of seven address bits that identify the alternate address for the I2C device on
the I2C bus.
I2C Slave Own Address 2 (I2CSOAR2)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
Offset 0x81C
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
reserved
Type
Reset
OAR2EN
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7
OAR2EN
RW
0
RW
0
OAR2
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
I2C Slave Own Address 2 Enable
Value Description
6:0
OAR2
RW
0x00
0
The alternate address is disabled.
1
Enables the use of the alternate address in the OAR2 field.
I2C Slave Own Address 2
This field specifies the alternate OAR2 address.
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Register 21: I2C Slave ACK Control (I2CSACKCTL), offset 0x820
This register enables the I2C slave to NACK for invalid data or command or ACK for valid data or
command. The I2C clock is pulled low after the last data bit until this register is written.
I2C Slave ACK Control (I2CSACKCTL)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
Offset 0x820
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:2
reserved
RO
0x0000.000
1
ACKOVAL
RW
0
ACKOVAL ACKOEN
RW
0
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
I2C Slave ACK Override Value
Value Description
0
ACKOEN
RW
0
0
An ACK is sent indicating valid data or command.
1
A NACK is sent indicating invalid data or command.
I2C Slave ACK Override Enable
Value Description
16.8
0
A response in not provided.
1
An ACK or NACK is sent according to the value written to the
ACKOVAL bit.
Register Descriptions (I2C Status and Control)
The remainder of this section lists and describes the I2C status and control registers, in numerical
order by address offset.
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Register 22: I2C Peripheral Properties (I2CPP), offset 0xFC0
The I2CPP register provides information regarding the properties of the I2C module.
I2C Peripheral Properties (I2CPP)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
Offset 0xFC0
Type RO, reset 0x0000.0001
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
reserved
Type
Reset
reserved
Type
Reset
RO
0
HS
Bit/Field
Name
Type
Reset
Description
31:1
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
HS
RO
0x1
High-Speed Capable
Value Description
0
The interface is capable of Standard, Fast, or Fast mode plus
operation.
1
The interface is capable of High-Speed operation.
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Inter-Integrated Circuit (I2C) Interface
Register 23: I2C Peripheral Configuration (I2CPC), offset 0xFC4
The I2CPC register allows software to enable features present in the I2C module.
I2C Peripheral Configuration (I2CPC)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
Offset 0xFC4
Type RO, reset 0x0000.0001
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW
1
reserved
Type
Reset
reserved
Type
Reset
RO
0
HS
Bit/Field
Name
Type
Reset
Description
31:1
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
HS
RW
1
High-Speed Capable
Value Description
0
The interface is set to Standard, Fast or Fast mode plus
operation.
1
The interface is set to High-Speed operation. Note that this
encoding may only be used if the HS bit in the I2CPP register
is set. Otherwise, this encoding is not available.
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17
Controller Area Network (CAN) Module
Controller Area Network (CAN) is a multicast, shared serial bus standard for connecting electronic
control units (ECUs). CAN was specifically designed to be robust in electromagnetically-noisy
environments and can utilize a differential balanced line like RS-485 or a more robust twisted-pair
wire. Originally created for automotive purposes, it is also used in many embedded control
applications (such as industrial and medical). Bit rates up to 1 Mbps are possible at network lengths
less than 40 meters. Decreased bit rates allow longer network distances (for example, 125 Kbps at
500 meters).
The TM4C1237H6PZ microcontroller includes one CAN unit with the following features:
■ CAN protocol version 2.0 part A/B
■ Bit rates up to 1 Mbps
■ 32 message objects with individual identifier masks
■ Maskable interrupt
■ Disable Automatic Retransmission mode for Time-Triggered CAN (TTCAN) applications
■ Programmable loopback mode for self-test operation
■ Programmable FIFO mode enables storage of multiple message objects
■ Gluelessly attaches to an external CAN transceiver through the CANnTX and CANnRX signals
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17.1
Block Diagram
Figure 17-1. CAN Controller Block Diagram
CAN Control
CANCTL
CANSTS
CANERR
CANBIT
CANINT
CANTST
CANBRPE
CAN Tx
CAN Interface 1
APB Pins
APB
Interface
CANIF1CRQ
CANIF1CMSK
CANIF1MSK1
CANIF1MSK2
CANIF1ARB1
CANIF1ARB2
CANIF1MCTL
CANIF1DA1
CANIF1DA2
CANIF1DB1
CANIF1DB2
CAN Core
CAN Rx
CAN Interface 2
CANIF2CRQ
CANIF2CMSK
CANIF2MSK1
CANIF2MSK2
CANIF2ARB1
CANIF2ARB2
CANIF2MCTL
CANIF2DA1
CANIF2DA2
CANIF2DB1
CANIF2DB2
Message Object
Registers
CANTXRQ1
CANTXRQ2
CANNWDA1
CANNWDA2
CANMSG1INT
CANMSG2INT
CANMSG1VAL
CANMSG2VAL
Message RAM
32 Message Objects
17.2
Signal Description
The following table lists the external signals of the CAN controller and describes the function of
each. The CAN controller signals are alternate functions for some GPIO signals and default to be
GPIO signals at reset. The column in the table below titled "Pin Mux/Pin Assignment" lists the
possible GPIO pin placements for the CAN signals. The AFSEL bit in the GPIO Alternate Function
Select (GPIOAFSEL) register (page 659) should be set to choose the CAN controller function. The
number in parentheses is the encoding that must be programmed into the PMCn field in the GPIO
Port Control (GPIOPCTL) register (page 677) to assign the CAN signal to the specified GPIO port
pin. For more information on configuring GPIOs, see “General-Purpose Input/Outputs
(GPIOs)” on page 634.
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Table 17-1. Controller Area Network Signals (100LQFP)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
CAN0Rx
40
92
95
PF0 (3)
PB4 (8)
PE4 (8)
I
TTL
CAN module 0 receive.
CAN0Tx
43
91
96
PF3 (3)
PB5 (8)
PE5 (8)
O
TTL
CAN module 0 transmit.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
17.3
Functional Description
The TM4C1237H6PZ CAN controller conforms to the CAN protocol version 2.0 (parts A and B).
Message transfers that include data, remote, error, and overload frames with an 11-bit identifier
(standard) or a 29-bit identifier (extended) are supported. Transfer rates can be programmed up to
1 Mbps.
The CAN module consists of three major parts:
■ CAN protocol controller and message handler
■ Message memory
■ CAN register interface
A data frame contains data for transmission, whereas a remote frame contains no data and is used
to request the transmission of a specific message object. The CAN data/remote frame is constructed
as shown in Figure 17-2.
Figure 17-2. CAN Data/Remote Frame
Remote
Transmission
Request
Start
Of Frame
Bus
Idle
R
S
Control
O Message Delimiter T Field
R
F
Number 1
Of Bits
11 or 29
1
6
Delimiter
Bits
Data Field
CRC
Sequence
A
C
K
EOP
IFS
0 . . . 64
15
1 1 1
7
3
CRC Sequence
CRC
Field
Arbitration Field
Bit Stuffing
End of
Frame
Field
Bus
Idle
Interframe
Field
Acknowledgement
Field
CAN Data Frame
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The protocol controller transfers and receives the serial data from the CAN bus and passes the data
on to the message handler. The message handler then loads this information into the appropriate
message object based on the current filtering and identifiers in the message object memory. The
message handler is also responsible for generating interrupts based on events on the CAN bus.
The message object memory is a set of 32 identical memory blocks that hold the current configuration,
status, and actual data for each message object. These memory blocks are accessed via either of
the CAN message object register interfaces.
The message memory is not directly accessible in the TM4C1237H6PZ memory map, so the
TM4C1237H6PZ CAN controller provides an interface to communicate with the message memory
via two CAN interface register sets for communicating with the message objects. These two interfaces
must be used to read or write to each message object. The two message object interfaces allow
parallel access to the CAN controller message objects when multiple objects may have new
information that must be processed. In general, one interface is used for transmit data and one for
receive data.
17.3.1
Initialization
To use the CAN controller, the peripheral clock must be enabled using the RCGC0 register (see
page 442). In addition, the clock to the appropriate GPIO module must be enabled via the RCGC2
register (see page 448). To find out which GPIO port to enable, refer to Table 21-4 on page 1242. Set
the GPIO AFSEL bits for the appropriate pins (see page 659). Configure the PMCn fields in the
GPIOPCTL register to assign the CAN signals to the appropriate pins. See page 677 and Table
21-5 on page 1249.
Software initialization is started by setting the INIT bit in the CAN Control (CANCTL) register (with
software or by a hardware reset) or by going bus-off, which occurs when the transmitter's error
counter exceeds a count of 255. While INIT is set, all message transfers to and from the CAN bus
are stopped and the CANnTX signal is held High. Entering the initialization state does not change
the configuration of the CAN controller, the message objects, or the error counters. However, some
configuration registers are only accessible while in the initialization state.
To initialize the CAN controller, set the CAN Bit Timing (CANBIT) register and configure each
message object. If a message object is not needed, label it as not valid by clearing the MSGVAL bit
in the CAN IFn Arbitration 2 (CANIFnARB2) register. Otherwise, the whole message object must
be initialized, as the fields of the message object may not have valid information, causing unexpected
results. Both the INIT and CCE bits in the CANCTL register must be set in order to access the
CANBIT register and the CAN Baud Rate Prescaler Extension (CANBRPE) register to configure
the bit timing. To leave the initialization state, the INIT bit must be cleared. Afterwards, the internal
Bit Stream Processor (BSP) synchronizes itself to the data transfer on the CAN bus by waiting for
the occurrence of a sequence of 11 consecutive recessive bits (indicating a bus idle condition)
before it takes part in bus activities and starts message transfers. Message object initialization does
not require the CAN to be in the initialization state and can be done on the fly. However, message
objects should all be configured to particular identifiers or set to not valid before message transfer
starts. To change the configuration of a message object during normal operation, clear the MSGVAL
bit in the CANIFnARB2 register to indicate that the message object is not valid during the change.
When the configuration is completed, set the MSGVAL bit again to indicate that the message object
is once again valid.
17.3.2
Operation
Two sets of CAN Interface Registers (CANIF1x and CANIF2x) are used to access the message
objects in the Message RAM. The CAN controller coordinates transfers to and from the Message
RAM to and from the registers. The two sets are independent and identical and can be used to
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queue transactions. Generally, one interface is used to transmit data and one is used to receive
data.
Once the CAN module is initialized and the INIT bit in the CANCTL register is cleared, the CAN
module synchronizes itself to the CAN bus and starts the message transfer. As each message is
received, it goes through the message handler's filtering process, and if it passes through the filter,
is stored in the message object specified by the MNUM bit in the CAN IFn Command Request
(CANIFnCRQ) register. The whole message (including all arbitration bits, data-length code, and
eight data bytes) is stored in the message object. If the Identifier Mask (the MSK bits in the CAN IFn
Mask 1 and CAN IFn Mask 2 (CANIFnMSKn) registers) is used, the arbitration bits that are masked
to "don't care" may be overwritten in the message object.
The CPU may read or write each message at any time via the CAN Interface Registers. The message
handler guarantees data consistency in case of concurrent accesses.
The transmission of message objects is under the control of the software that is managing the CAN
hardware. Message objects can be used for one-time data transfers or can be permanent message
objects used to respond in a more periodic manner. Permanent message objects have all arbitration
and control set up, and only the data bytes are updated. At the start of transmission, the appropriate
TXRQST bit in the CAN Transmission Request n (CANTXRQn) register and the NEWDAT bit in the
CAN New Data n (CANNWDAn) register are set. If several transmit messages are assigned to the
same message object (when the number of message objects is not sufficient), the whole message
object has to be configured before the transmission of this message is requested.
The transmission of any number of message objects may be requested at the same time; they are
transmitted according to their internal priority, which is based on the message identifier (MNUM) for
the message object, with 1 being the highest priority and 32 being the lowest priority. Messages
may be updated or set to not valid any time, even when their requested transmission is still pending.
The old data is discarded when a message is updated before its pending transmission has started.
Depending on the configuration of the message object, the transmission of a message may be
requested autonomously by the reception of a remote frame with a matching identifier.
Transmission can be automatically started by the reception of a matching remote frame. To enable
this mode, set the RMTEN bit in the CAN IFn Message Control (CANIFnMCTL) register. A matching
received remote frame causes the TXRQST bit to be set, and the message object automatically
transfers its data or generates an interrupt indicating a remote frame was requested. A remote frame
can be strictly a single message identifier, or it can be a range of values specified in the message
object. The CAN mask registers, CANIFnMSKn, configure which groups of frames are identified
as remote frame requests. The UMASK bit in the CANIFnMCTL register enables the MSK bits in the
CANIFnMSKn register to filter which frames are identified as a remote frame request. The MXTD
bit in the CANIFnMSK2 register should be set if a remote frame request is expected to be triggered
by 29-bit extended identifiers.
17.3.3
Transmitting Message Objects
If the internal transmit shift register of the CAN module is ready for loading, and if a data transfer is
not occurring between the CAN Interface Registers and message RAM, the valid message object
with the highest priority that has a pending transmission request is loaded into the transmit shift
register by the message handler and the transmission is started. The message object's NEWDAT bit
in the CANNWDAn register is cleared. After a successful transmission, and if no new data was
written to the message object since the start of the transmission, the TXRQST bit in the CANTXRQn
register is cleared. If the CAN controller is configured to interrupt on a successful transmission of a
message object, (the TXIE bit in the CAN IFn Message Control (CANIFnMCTL) register is set),
the INTPND bit in the CANIFnMCTL register is set after a successful transmission. If the CAN
module has lost the arbitration or if an error occurred during the transmission, the message is
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re-transmitted as soon as the CAN bus is free again. If, meanwhile, the transmission of a message
with higher priority has been requested, the messages are transmitted in the order of their priority.
17.3.4
Configuring a Transmit Message Object
The following steps illustrate how to configure a transmit message object.
1. In the CAN IFn Command Mask (CANIFnCMASK) register:
■ Set the WRNRD bit to specify a write to the CANIFnCMASK register; specify whether to
transfer the IDMASK, DIR, and MXTD of the message object into the CAN IFn registers using
the MASK bit
■ Specify whether to transfer the ID, DIR, XTD, and MSGVAL of the message object into the
interface registers using the ARB bit
■ Specify whether to transfer the control bits into the interface registers using the CONTROL
bit
■ Specify whether to clear the INTPND bit in the CANIFnMCTL register using the CLRINTPND
bit
■ Specify whether to clear the NEWDAT bit in the CANNWDAn register using the NEWDAT bit
■ Specify which bits to transfer using the DATAA and DATAB bits
2. In the CANIFnMSK1 register, use the MSK[15:0] bits to specify which of the bits in the 29-bit
or 11-bit message identifier are used for acceptance filtering. Note that MSK[15:0] in this
register are used for bits [15:0] of the 29-bit message identifier and are not used for an 11-bit
identifier. A value of 0x00 enables all messages to pass through the acceptance filtering. Also
note that in order for these bits to be used for acceptance filtering, they must be enabled by
setting the UMASK bit in the CANIFnMCTL register.
3. In the CANIFnMSK2 register, use the MSK[12:0] bits to specify which of the bits in the 29-bit
or 11-bit message identifier are used for acceptance filtering. Note that MSK[12:0] are used
for bits [28:16] of the 29-bit message identifier; whereas MSK[12:2] are used for bits [10:0] of
the 11-bit message identifier. Use the MXTD and MDIR bits to specify whether to use XTD and
DIR for acceptance filtering. A value of 0x00 enables all messages to pass through the
acceptance filtering. Also note that in order for these bits to be used for acceptance filtering,
they must be enabled by setting the UMASK bit in the CANIFnMCTL register.
4. For a 29-bit identifier, configure ID[15:0] in the CANIFnARB1 register for bits [15:0] of the
message identifier and ID[12:0] in the CANIFnARB2 register for bits [28:16] of the message
identifier. Set the XTD bit to indicate an extended identifier; set the DIR bit to indicate transmit;
and set the MSGVAL bit to indicate that the message object is valid.
5. For an 11-bit identifier, disregard the CANIFnARB1 register and configure ID[12:2] in the
CANIFnARB2 register for bits [10:0] of the message identifier. Clear the XTD bit to indicate a
standard identifier; set the DIR bit to indicate transmit; and set the MSGVAL bit to indicate that
the message object is valid.
6. In the CANIFnMCTL register:
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■ Optionally set the UMASK bit to enable the mask (MSK, MXTD, and MDIR specified in the
CANIFnMSK1 and CANIFnMSK2 registers) for acceptance filtering
■ Optionally set the TXIE bit to enable the INTPND bit to be set after a successful transmission
■ Optionally set the RMTEN bit to enable the TXRQST bit to be set on the reception of a matching
remote frame allowing automatic transmission
■ Set the EOB bit for a single message object
■ Configure the DLC[3:0] field to specify the size of the data frame. Take care during this
configuration not to set the NEWDAT, MSGLST, INTPND or TXRQST bits.
7. Load the data to be transmitted into the CAN IFn Data (CANIFnDA1, CANIFnDA2, CANIFnDB1,
CANIFnDB2) registers. Byte 0 of the CAN data frame is stored in DATA[7:0] in the CANIFnDA1
register.
8. Program the number of the message object to be transmitted in the MNUM field in the CAN IFn
Command Request (CANIFnCRQ) register.
9. When everything is properly configured, set the TXRQST bit in the CANIFnMCTL register. Once
this bit is set, the message object is available to be transmitted, depending on priority and bus
availability. Note that setting the RMTEN bit in the CANIFnMCTL register can also start message
transmission if a matching remote frame has been received.
17.3.5
Updating a Transmit Message Object
The CPU may update the data bytes of a Transmit Message Object any time via the CAN Interface
Registers and neither the MSGVAL bit in the CANIFnARB2 register nor the TXRQST bits in the
CANIFnMCTL register have to be cleared before the update.
Even if only some of the data bytes are to be updated, all four bytes of the corresponding
CANIFnDAn/CANIFnDBn register have to be valid before the content of that register is transferred
to the message object. Either the CPU must write all four bytes into the CANIFnDAn/CANIFnDBn
register or the message object is transferred to the CANIFnDAn/CANIFnDBn register before the
CPU writes the new data bytes.
In order to only update the data in a message object, the WRNRD, DATAA and DATAB bits in the
CANIFnMSKn register are set, followed by writing the updated data into CANIFnDA1, CANIFnDA2,
CANIFnDB1, and CANIFnDB2 registers, and then the number of the message object is written to
the MNUM field in the CAN IFn Command Request (CANIFnCRQ) register. To begin transmission
of the new data as soon as possible, set the TXRQST bit in the CANIFnMSKn register.
To prevent the clearing of the TXRQST bit in the CANIFnMCTL register at the end of a transmission
that may already be in progress while the data is updated, the NEWDAT and TXRQST bits have to be
set at the same time in the CANIFnMCTL register. When these bits are set at the same time, NEWDAT
is cleared as soon as the new transmission has started.
17.3.6
Accepting Received Message Objects
When the arbitration and control field (the ID and XTD bits in the CANIFnARB2 and the RMTEN and
DLC[3:0] bits of the CANIFnMCTL register) of an incoming message is completely shifted into
the CAN controller, the message handling capability of the controller starts scanning the message
RAM for a matching valid message object. To scan the message RAM for a matching message
object, the controller uses the acceptance filtering programmed through the mask bits in the
CANIFnMSKn register and enabled using the UMASK bit in the CANIFnMCTL register. Each valid
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message object, starting with object 1, is compared with the incoming message to locate a matching
message object in the message RAM. If a match occurs, the scanning is stopped and the message
handler proceeds depending on whether it is a data frame or remote frame that was received.
17.3.7
Receiving a Data Frame
The message handler stores the message from the CAN controller receive shift register into the
matching message object in the message RAM. The data bytes, all arbitration bits, and the DLC bits
are all stored into the corresponding message object. In this manner, the data bytes are connected
with the identifier even if arbitration masks are used. The NEWDAT bit of the CANIFnMCTL register
is set to indicate that new data has been received. The CPU should clear this bit when it reads the
message object to indicate to the controller that the message has been received, and the buffer is
free to receive more messages. If the CAN controller receives a message and the NEWDAT bit is
already set, the MSGLST bit in the CANIFnMCTL register is set to indicate that the previous data
was lost. If the system requires an interrupt on successful reception of a frame, the RXIE bit of the
CANIFnMCTL register should be set. In this case, the INTPND bit of the same register is set, causing
the CANINT register to point to the message object that just received a message. The TXRQST bit
of this message object should be cleared to prevent the transmission of a remote frame.
17.3.8
Receiving a Remote Frame
A remote frame contains no data, but instead specifies which object should be transmitted. When
a remote frame is received, three different configurations of the matching message object have to
be considered:
Table 17-2. Message Object Configurations
Configuration in CANIFnMCTL
■
Description
■
DIR = 1 (direction = transmit); programmed in the At the reception of a matching remote frame, the TXRQST bit of this
CANIFnARB2 register
message object is set. The rest of the message object remains
unchanged, and the controller automatically transfers the data in
RMTEN = 1 (set the TXRQST bit of the
the message object as soon as possible.
CANIFnMCTL register at reception of the frame
to enable transmission)
■
UMASK = 1 or 0
■
DIR = 1 (direction = transmit); programmed in the At the reception of a matching remote frame, the TXRQST bit of this
CANIFnARB2 register
message object remains unchanged, and the remote frame is
ignored. This remote frame is disabled, the data is not transferred
RMTEN = 0 (do not change the TXRQST bit of the and nothing indicates that the remote frame ever happened.
CANIFnMCTL register at reception of the frame)
■
■
UMASK = 0 (ignore mask in the CANIFnMSKn
register)
■
DIR = 1 (direction = transmit); programmed in the At the reception of a matching remote frame, the TXRQST bit of this
CANIFnARB2 register
message object is cleared. The arbitration and control field (ID +
XTD + RMTEN + DLC) from the shift register is stored into the message
RMTEN = 0 (do not change the TXRQST bit of the object in the message RAM, and the NEWDAT bit of this message
CANIFnMCTL register at reception of the frame) object is set. The data field of the message object remains
unchanged; the remote frame is treated similar to a received data
UMASK = 1 (use mask (MSK, MXTD, and MDIR in
frame. This mode is useful for a remote data request from another
the CANIFnMSKn register) for acceptance filtering)
CAN device for which the TM4C1237H6PZ controller does not have
readily available data. The software must fill the data and answer
the frame manually.
■
■
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17.3.9
Receive/Transmit Priority
The receive/transmit priority for the message objects is controlled by the message number. Message
object 1 has the highest priority, while message object 32 has the lowest priority. If more than one
transmission request is pending, the message objects are transmitted in order based on the message
object with the lowest message number. This prioritization is separate from that of the message
identifier which is enforced by the CAN bus. As a result, if message object 1 and message object
2 both have valid messages to be transmitted, message object 1 is always transmitted first regardless
of the message identifier in the message object itself.
17.3.10
Configuring a Receive Message Object
The following steps illustrate how to configure a receive message object.
1. Program the CAN IFn Command Mask (CANIFnCMASK) register as described in the
“Configuring a Transmit Message Object” on page 1046 section, except that the WRNRD bit is set
to specify a write to the message RAM.
2. Program the CANIFnMSK1and CANIFnMSK2 registers as described in the “Configuring a
Transmit Message Object” on page 1046 section to configure which bits are used for acceptance
filtering. Note that in order for these bits to be used for acceptance filtering, they must be enabled
by setting the UMASK bit in the CANIFnMCTL register.
3. In the CANIFnMSK2 register, use the MSK[12:0] bits to specify which of the bits in the 29-bit
or 11-bit message identifier are used for acceptance filtering. Note that MSK[12:0] are used
for bits [28:16] of the 29-bit message identifier; whereas MSK[12:2] are used for bits [10:0] of
the 11-bit message identifier. Use the MXTD and MDIR bits to specify whether to use XTD and
DIR for acceptance filtering. A value of 0x00 enables all messages to pass through the
acceptance filtering. Also note that in order for these bits to be used for acceptance filtering,
they must be enabled by setting the UMASK bit in the CANIFnMCTL register.
4. Program the CANIFnARB1 and CANIFnARB2 registers as described in the “Configuring a
Transmit Message Object” on page 1046 section to program XTD and ID bits for the message
identifier to be received; set the MSGVAL bit to indicate a valid message; and clear the DIR bit
to specify receive.
5. In the CANIFnMCTL register:
■ Optionally set the UMASK bit to enable the mask (MSK, MXTD, and MDIR specified in the
CANIFnMSK1 and CANIFnMSK2 registers) for acceptance filtering
■ Optionally set the RXIE bit to enable the INTPND bit to be set after a successful reception
■ Clear the RMTEN bit to leave the TXRQST bit unchanged
■ Set the EOB bit for a single message object
■ Configure the DLC[3:0] field to specify the size of the data frame
Take care during this configuration not to set the NEWDAT, MSGLST, INTPND or TXRQST bits.
6. Program the number of the message object to be received in the MNUM field in the CAN IFn
Command Request (CANIFnCRQ) register. Reception of the message object begins as soon
as a matching frame is available on the CAN bus.
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When the message handler stores a data frame in the message object, it stores the received Data
Length Code and eight data bytes in the CANIFnDA1, CANIFnDA2, CANIFnDB1, and CANIFnDB2
register. Byte 0 of the CAN data frame is stored in DATA[7:0] in the CANIFnDA1 register. If the
Data Length Code is less than 8, the remaining bytes of the message object are overwritten by
unspecified values.
The CAN mask registers can be used to allow groups of data frames to be received by a message
object. The CAN mask registers, CANIFnMSKn, configure which groups of frames are received by
a message object. The UMASK bit in the CANIFnMCTL register enables the MSK bits in the
CANIFnMSKn register to filter which frames are received. The MXTD bit in the CANIFnMSK2 register
should be set if only 29-bit extended identifiers are expected by this message object.
17.3.11
Handling of Received Message Objects
The CPU may read a received message any time via the CAN Interface registers because the data
consistency is guaranteed by the message handler state machine.
Typically, the CPU first writes 0x007F to the CANIFnCMSK register and then writes the number of
the message object to the CANIFnCRQ register. That combination transfers the whole received
message from the message RAM into the Message Buffer registers (CANIFnMSKn, CANIFnARBn,
and CANIFnMCTL). Additionally, the NEWDAT and INTPND bits are cleared in the message RAM,
acknowledging that the message has been read and clearing the pending interrupt generated by
this message object.
If the message object uses masks for acceptance filtering, the CANIFnARBn registers show the
full, unmasked ID for the received message.
The NEWDAT bit in the CANIFnMCTL register shows whether a new message has been received
since the last time this message object was read. The MSGLST bit in the CANIFnMCTL register
shows whether more than one message has been received since the last time this message object
was read. MSGLST is not automatically cleared, and should be cleared by software after reading its
status.
Using a remote frame, the CPU may request new data from another CAN node on the CAN bus.
Setting the TXRQST bit of a receive object causes the transmission of a remote frame with the receive
object's identifier. This remote frame triggers the other CAN node to start the transmission of the
matching data frame. If the matching data frame is received before the remote frame could be
transmitted, the TXRQST bit is automatically reset. This prevents the possible loss of data when the
other device on the CAN bus has already transmitted the data slightly earlier than expected.
17.3.11.1 Configuration of a FIFO Buffer
With the exception of the EOB bit in the CANIFnMCTL register, the configuration of receive message
objects belonging to a FIFO buffer is the same as the configuration of a single receive message
object (see “Configuring a Receive Message Object” on page 1049). To concatenate two or more
message objects into a FIFO buffer, the identifiers and masks (if used) of these message objects
have to be programmed to matching values. Due to the implicit priority of the message objects, the
message object with the lowest message object number is the first message object in a FIFO buffer.
The EOB bit of all message objects of a FIFO buffer except the last one must be cleared. The EOB
bit of the last message object of a FIFO buffer is set, indicating it is the last entry in the buffer.
17.3.11.2 Reception of Messages with FIFO Buffers
Received messages with identifiers matching to a FIFO buffer are stored starting with the message
object with the lowest message number. When a message is stored into a message object of a
FIFO buffer, the NEWDAT of the CANIFnMCTL register bit of this message object is set. By setting
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NEWDAT while EOB is clear, the message object is locked and cannot be written to by the message
handler until the CPU has cleared the NEWDAT bit. Messages are stored into a FIFO buffer until the
last message object of this FIFO buffer is reached. Until all of the preceding message objects have
been released by clearing the NEWDAT bit, all further messages for this FIFO buffer are written into
the last message object of the FIFO buffer and therefore overwrite previous messages.
17.3.11.3 Reading from a FIFO Buffer
When the CPU transfers the contents of a message object from a FIFO buffer by writing its number
to the CANIFnCRQ register, the TXRQST and CLRINTPND bits in the CANIFnCMSK register should
be set such that the NEWDAT and INTPEND bits in the CANIFnMCTL register are cleared after the
read. The values of these bits in the CANIFnMCTL register always reflect the status of the message
object before the bits are cleared. To assure the correct function of a FIFO buffer, the CPU should
read out the message objects starting with the message object with the lowest message number.
When reading from the FIFO buffer, the user should be aware that a new received message is
placed in the message object with the lowest message number for which the NEWDAT bit of the
CANIFnMCTL register is clear. As a result, the order of the received messages in the FIFO is not
guaranteed. Figure 17-3 on page 1052 shows how a set of message objects which are concatenated
to a FIFO Buffer can be handled by the CPU.
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Figure 17-3. Message Objects in a FIFO Buffer
START
Message Interrupt
Read Interrupt Pointer
0x0000
Case Interrupt Pointer
else
0x8000
END
Status Change
Interrupt Handling
MNUM = Interrupt Pointer
Write MNUM to IFn Command Request
(Read Message to IFn Registers,
Reset NEWDAT = 0,
Reset INTPND = 0
Read IFn Message Control
Yes
No
NEWDAT = 1
Read Data from IFn Data A,B
EOB = 1
Yes
No
MNUM = MNUM + 1
17.3.12
Handling of Interrupts
If several interrupts are pending, the CAN Interrupt (CANINT) register points to the pending interrupt
with the highest priority, disregarding their chronological order. The status interrupt has the highest
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priority. Among the message interrupts, the message object's interrupt with the lowest message
number has the highest priority. A message interrupt is cleared by clearing the message object's
INTPND bit in the CANIFnMCTL register or by reading the CAN Status (CANSTS) register. The
status Interrupt is cleared by reading the CANSTS register.
The interrupt identifier INTID in the CANINT register indicates the cause of the interrupt. When no
interrupt is pending, the register reads as 0x0000. If the value of the INTID field is different from 0,
then an interrupt is pending. If the IE bit is set in the CANCTL register, the interrupt line to the
interrupt controller is active. The interrupt line remains active until the INTID field is 0, meaning
that all interrupt sources have been cleared (the cause of the interrupt is reset), or until IE is cleared,
which disables interrupts from the CAN controller.
The INTID field of the CANINT register points to the pending message interrupt with the highest
interrupt priority. The SIE bit in the CANCTL register controls whether a change of the RXOK, TXOK,
and LEC bits in the CANSTS register can cause an interrupt. The EIE bit in the CANCTLregister
controls whether a change of the BOFF and EWARN bits in the CANSTS register can cause an
interrupt. The IE bit in the CANCTL register controls whether any interrupt from the CAN controller
actually generates an interrupt to the interrupt controller. The CANINT register is updated even
when the IE bit in the CANCTL register is clear, but the interrupt is not indicated to the CPU.
A value of 0x8000 in the CANINT register indicates that an interrupt is pending because the CAN
module has updated, but not necessarily changed, the CANSTS register, indicating that either an
error or status interrupt has been generated. A write access to the CANSTS register can clear the
RXOK, TXOK, and LEC bits in that same register; however, the only way to clear the source of a
status interrupt is to read the CANSTS register.
The source of an interrupt can be determined in two ways during interrupt handling. The first is to
read the INTID bit in the CANINT register to determine the highest priority interrupt that is pending,
and the second is to read the CAN Message Interrupt Pending (CANMSGnINT) register to see
all of the message objects that have pending interrupts.
An interrupt service routine reading the message that is the source of the interrupt may read the
message and clear the message object's INTPND bit at the same time by setting the CLRINTPND
bit in the CANIFnCMSK register. Once the INTPND bit has been cleared, the CANINT register
contains the message number for the next message object with a pending interrupt.
17.3.13
Test Mode
A Test Mode is provided which allows various diagnostics to be performed. Test Mode is entered
by setting the TEST bit in the CANCTL register. Once in Test Mode, the TX[1:0], LBACK, SILENT
and BASIC bits in the CAN Test (CANTST) register can be used to put the CAN controller into the
various diagnostic modes. The RX bit in the CANTST register allows monitoring of the CANnRX
signal. All CANTST register functions are disabled when the TEST bit is cleared.
17.3.13.1 Silent Mode
Silent Mode can be used to analyze the traffic on a CAN bus without affecting it by the transmission
of dominant bits (Acknowledge Bits, Error Frames). The CAN Controller is put in Silent Mode setting
the SILENT bit in the CANTST register. In Silent Mode, the CAN controller is able to receive valid
data frames and valid remote frames, but it sends only recessive bits on the CAN bus and cannot
start a transmission. If the CAN Controller is required to send a dominant bit (ACK bit, overload flag,
or active error flag), the bit is rerouted internally so that the CAN Controller monitors this dominant
bit, although the CAN bus remains in recessive state.
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17.3.13.2 Loopback Mode
Loopback mode is useful for self-test functions. In Loopback Mode, the CAN Controller internally
routes the CANnTX signal on to the CANnRX signal and treats its own transmitted messages as
received messages and stores them (if they pass acceptance filtering) into the message buffer. The
CAN Controller is put in Loopback Mode by setting the LBACK bit in the CANTST register. To be
independent from external stimulation, the CAN Controller ignores acknowledge errors (a recessive
bit sampled in the acknowledge slot of a data/remote frame) in Loopback Mode. The actual value
of the CANnRX signal is disregarded by the CAN Controller. The transmitted messages can be
monitored on the CANnTX signal.
17.3.13.3 Loopback Combined with Silent Mode
Loopback Mode and Silent Mode can be combined to allow the CAN Controller to be tested without
affecting a running CAN system connected to the CANnTX and CANnRX signals. In this mode, the
CANnRX signal is disconnected from the CAN Controller and the CANnTX signal is held recessive.
This mode is enabled by setting both the LBACK and SILENT bits in the CANTST register.
17.3.13.4 Basic Mode
Basic Mode allows the CAN Controller to be operated without the Message RAM. In Basic Mode,
The CANIF1 registers are used as the transmit buffer. The transmission of the contents of the IF1
registers is requested by setting the BUSY bit of the CANIF1CRQ register. The CANIF1 registers
are locked while the BUSY bit is set. The BUSY bit indicates that a transmission is pending. As soon
the CAN bus is idle, the CANIF1 registers are loaded into the shift register of the CAN Controller
and transmission is started. When the transmission has completed, the BUSY bit is cleared and the
locked CANIF1 registers are released. A pending transmission can be aborted at any time by clearing
the BUSY bit in the CANIF1CRQ register while the CANIF1 registers are locked. If the CPU has
cleared the BUSY bit, a possible retransmission in case of lost arbitration or an error is disabled.
The CANIF2 Registers are used as a receive buffer. After the reception of a message, the contents
of the shift register are stored in the CANIF2 registers, without any acceptance filtering. Additionally,
the actual contents of the shift register can be monitored during the message transfer. Each time a
read message object is initiated by setting the BUSY bit of the CANIF2CRQ register, the contents
of the shift register are stored into the CANIF2 registers.
In Basic Mode, all message-object-related control and status bits and of the control bits of the
CANIFnCMSK registers are not evaluated. The message number of the CANIFnCRQ registers is
also not evaluated. In the CANIF2MCTL register, the NEWDAT and MSGLST bits retain their function,
the DLC[3:0] field shows the received DLC, the other control bits are cleared.
Basic Mode is enabled by setting the BASIC bit in the CANTST register.
17.3.13.5 Transmit Control
Software can directly override control of the CANnTX signal in four different ways.
■ CANnTX is controlled by the CAN Controller
■ The sample point is driven on the CANnTX signal to monitor the bit timing
■ CANnTX drives a low value
■ CANnTX drives a high value
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The last two functions, combined with the readable CAN receive pin CANnRX, can be used to check
the physical layer of the CAN bus.
The Transmit Control function is enabled by programming the TX[1:0] field in the CANTST register.
The three test functions for the CANnTX signal interfere with all CAN protocol functions. TX[1:0]
must be cleared when CAN message transfer or Loopback Mode, Silent Mode, or Basic Mode are
selected.
17.3.14
Bit Timing Configuration Error Considerations
Even if minor errors in the configuration of the CAN bit timing do not result in immediate failure, the
performance of a CAN network can be reduced significantly. In many cases, the CAN bit
synchronization amends a faulty configuration of the CAN bit timing to such a degree that only
occasionally an error frame is generated. In the case of arbitration, however, when two or more
CAN nodes simultaneously try to transmit a frame, a misplaced sample point may cause one of the
transmitters to become error passive. The analysis of such sporadic errors requires a detailed
knowledge of the CAN bit synchronization inside a CAN node and of the CAN nodes' interaction on
the CAN bus.
17.3.15
Bit Time and Bit Rate
The CAN system supports bit rates in the range of lower than 1 Kbps up to 1000 Kbps. Each member
of the CAN network has its own clock generator. The timing parameter of the bit time can be
configured individually for each CAN node, creating a common bit rate even though the CAN nodes'
oscillator periods may be different.
Because of small variations in frequency caused by changes in temperature or voltage and by
deteriorating components, these oscillators are not absolutely stable. As long as the variations
remain inside a specific oscillator's tolerance range, the CAN nodes are able to compensate for the
different bit rates by periodically resynchronizing to the bit stream.
According to the CAN specification, the bit time is divided into four segments (see Figure
17-4 on page 1056): the Synchronization Segment, the Propagation Time Segment, the Phase Buffer
Segment 1, and the Phase Buffer Segment 2. Each segment consists of a specific, programmable
number of time quanta (see Table 17-3 on page 1056). The length of the time quantum (tq), which is
the basic time unit of the bit time, is defined by the CAN controller's input clock (fsys) and the Baud
Rate Prescaler (BRP):
tq = BRP / fsys
The fsys input clock is the system clock frequency as configured by the RCC or RCC2 registers
(see page 248 or page 255).
The Synchronization Segment Sync is that part of the bit time where edges of the CAN bus level
are expected to occur; the distance between an edge that occurs outside of Sync and the Sync is
called the phase error of that edge.
The Propagation Time Segment Prop is intended to compensate for the physical delay times within
the CAN network.
The Phase Buffer Segments Phase1 and Phase2 surround the Sample Point.
The (Re-)Synchronization Jump Width (SJW) defines how far a resynchronization may move the
Sample Point inside the limits defined by the Phase Buffer Segments to compensate for edge phase
errors.
A given bit rate may be met by different bit-time configurations, but for the proper function of the
CAN network, the physical delay times and the oscillator's tolerance range have to be considered.
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Figure 17-4. CAN Bit Time
Nominal CAN Bit Time
a
b
TSEG1
Sync
Prop
TSEG2
Phase1
c
1 Time
Quantum
q)
(tq
Phase2
Sample
Point
a. TSEG1 = Prop + Phase1
b. TSEG2 = Phase2
c. Phase1 = Phase2 or Phase1 + 1 = Phase2
a
Table 17-3. CAN Protocol Ranges
Parameter
Range
Remark
BRP
[1 .. 64]
Defines the length of the time quantum tq. The CANBRPE register can
be used to extend the range to 1024.
Sync
1 tq
Fixed length, synchronization of bus input to system clock
Prop
[1 .. 8] tq
Compensates for the physical delay times
Phase1
[1 .. 8] tq
May be lengthened temporarily by synchronization
Phase2
[1 .. 8] tq
May be shortened temporarily by synchronization
SJW
[1 .. 4] tq
May not be longer than either Phase Buffer Segment
a. This table describes the minimum programmable ranges required by the CAN protocol.
The bit timing configuration is programmed in two register bytes in the CANBIT register. In the
CANBIT register, the four components TSEG2, TSEG1, SJW, and BRP have to be programmed to a
numerical value that is one less than its functional value; so instead of values in the range of [1..n],
values in the range of [0..n-1] are programmed. That way, for example, SJW (functional range of
[1..4]) is represented by only two bits in the SJW bit field. Table 17-4 shows the relationship between
the CANBIT register values and the parameters.
Table 17-4. CANBIT Register Values
CANBIT Register Field
Setting
TSEG2
Phase2 - 1
TSEG1
Prop + Phase1 - 1
SJW
SJW - 1
BRP
BRP
Therefore, the length of the bit time is (programmed values):
[TSEG1 + TSEG2 + 3] × tq
or (functional values):
[Sync + Prop + Phase1 + Phase2] × tq
The data in the CANBIT register is the configuration input of the CAN protocol controller. The baud
rate prescaler (configured by the BRP field) defines the length of the time quantum, the basic time
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unit of the bit time; the bit timing logic (configured by TSEG1, TSEG2, and SJW) defines the number
of time quanta in the bit time.
The processing of the bit time, the calculation of the position of the sample point, and occasional
synchronizations are controlled by the CAN controller and are evaluated once per time quantum.
The CAN controller translates messages to and from frames. In addition, the controller generates
and discards the enclosing fixed format bits, inserts and extracts stuff bits, calculates and checks
the CRC code, performs the error management, and decides which type of synchronization is to be
used. The bit value is received or transmitted at the sample point. The information processing time
(IPT) is the time after the sample point needed to calculate the next bit to be transmitted on the CAN
bus. The IPT includes any of the following: retrieving the next data bit, handling a CRC bit, determining
if bit stuffing is required, generating an error flag or simply going idle.
The IPT is application-specific but may not be longer than 2 tq; the CAN's IPT is 0 tq. Its length is
the lower limit of the programmed length of Phase2. In case of synchronization, Phase2 may be
shortened to a value less than IPT, which does not affect bus timing.
17.3.16
Calculating the Bit Timing Parameters
Usually, the calculation of the bit timing configuration starts with a required bit rate or bit time. The
resulting bit time (1/bit rate) must be an integer multiple of the system clock period.
The bit time may consist of 4 to 25 time quanta. Several combinations may lead to the required bit
time, allowing iterations of the following steps.
The first part of the bit time to be defined is Prop. Its length depends on the delay times measured
in the system. A maximum bus length as well as a maximum node delay has to be defined for
expandable CAN bus systems. The resulting time for Prop is converted into time quanta (rounded
up to the nearest integer multiple of tq).
Sync is 1 tq long (fixed), which leaves (bit time - Prop - 1) tq for the two Phase Buffer Segments. If
the number of remaining tq is even, the Phase Buffer Segments have the same length, that is,
Phase2 = Phase1, else Phase2 = Phase1 + 1.
The minimum nominal length of Phase2 has to be regarded as well. Phase2 may not be shorter
than the CAN controller's Information Processing Time, which is, depending on the actual
implementation, in the range of [0..2] tq.
The length of the synchronization jump width is set to the least of 4, Phase1 or Phase2.
The oscillator tolerance range necessary for the resulting configuration is calculated by the formula
given below:
(1 − df ) × fnom ≤ fosc ≤ (1 + df ) × fnom
where:
df
≤
(Phase _ seg1, Phase _ seg2) min
2 × (13 × tbit − Phase _ Seg 2)
■ df = Maximum tolerance of oscillator frequency
■ fosc
Actual=oscillator
df =max
2 × dffrequency
× fnom
■ fnom = Nominal oscillator frequency
Maximum frequency tolerance must take into account the following formulas:
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Controller Area Network (CAN) Module
− )df
× fnom
≤ fosc
+ )df
× fnom
(1 −(1df
× )fnom
≤ fosc
≤ (1≤ +(1df
× )fnom
(Phase
_ seg
1, Phase
_ seg
2) min
(Phase
_ seg
1, Phase
_ seg
2) min
df df
≤ ≤ 2 × (13 × tbit − Phase _ Seg 2)
2 × (13 × tbit − Phase _ Seg 2)
× df
× fnom
df df
maxmax
= 2=× 2df
× fnom
where:
■ Phase1 and Phase2 are from Table 17-3 on page 1056
■ tbit = Bit Time
■ dfmax = Maximum difference between two oscillators
If more than one configuration is possible, that configuration allowing the highest oscillator tolerance
range should be chosen.
CAN nodes with different system clocks require different configurations to come to the same bit
rate. The calculation of the propagation time in the CAN network, based on the nodes with the
longest delay times, is done once for the whole network.
The CAN system's oscillator tolerance range is limited by the node with the lowest tolerance range.
The calculation may show that bus length or bit rate have to be decreased or that the oscillator
frequencies' stability has to be increased in order to find a protocol-compliant configuration of the
CAN bit timing.
17.3.16.1 Example for Bit Timing at High Baud Rate
In this example, the frequency of CAN clock is 25 MHz, and the bit rate is 1 Mbps.
bit time = 1 µs = n * tq = 5 *
tq = 200 ns
tq = (Baud rate Prescaler)/CAN
Baud rate Prescaler = tq * CAN
Baud rate Prescaler = 200E-9 *
tq
Clock
Clock
25E6 = 5
tSync = 1 * tq = 200 ns
\\fixed at 1 time quanta
delay
delay
delay
tProp
\\400 is next integer multiple of tq
of bus driver 50 ns
of receiver circuit 30 ns
of bus line (40m) 220 ns
400 ns = 2 * tq
bit time = tSync +
bit time = tSync +
tPhase 1 + tPhase2
tPhase 1 + tPhase2
tPhase 1 + tPhase2
tPhase1 = 1 * tq
tPhase2 = 1 * tq
tTSeg1 + tTSeg2 = 5 * tq
tProp + tPhase 1 + tPhase2
= bit time - tSync - tProp
= (5 * tq) - (1 * tq) - (2 * tq)
= 2 * tq
\\tPhase2 = tPhase1
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tTSeg1 = tProp + tPhase1
tTSeg1 = (2 * tq) + (1 * tq)
tTSeg1 = 3 * tq
tTSeg2 = tPhase2
tTSeg2 = (Information Processing Time + 1) * tq
tTSeg2 = 1 * tq
\\Assumes IPT=0
tSJW = 1 * tq
\\Least of 4, Phase1 and Phase2
In the above example, the bit field values for the CANBIT register are:
= TSeg2 -1
TSEG2
= 1-1
=0
= TSeg1 -1
TSEG1
= 3-1
=2
= SJW -1
SJW
= 1-1
=0
= Baud rate prescaler - 1
BRP
= 5-1
=4
The final value programmed into the CANBIT register = 0x0204.
17.3.16.2 Example for Bit Timing at Low Baud Rate
In this example, the frequency of the CAN clock is 50 MHz, and the bit rate is 100 Kbps.
bit time = 10 µs = n * tq = 10 * tq
tq = 1 µs
tq = (Baud rate Prescaler)/CAN Clock
Baud rate Prescaler = tq * CAN Clock
Baud rate Prescaler = 1E-6 * 50E6 = 50
tSync = 1 * tq = 1 µs
\\fixed at 1 time quanta
delay
delay
delay
tProp
\\1 µs is next integer multiple of tq
of bus driver 200 ns
of receiver circuit 80 ns
of bus line (40m) 220 ns
1 µs = 1 * tq
bit time = tSync +
bit time = tSync +
tPhase 1 + tPhase2
tPhase 1 + tPhase2
tPhase 1 + tPhase2
tPhase1 = 4 * tq
tPhase2 = 4 * tq
tTSeg1 + tTSeg2 = 10 * tq
tProp + tPhase 1 + tPhase2
= bit time - tSync - tProp
= (10 * tq) - (1 * tq) - (1 * tq)
= 8 * tq
\\tPhase1 = tPhase2
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tTSeg1
tTSeg1
tTSeg1
tTSeg2
tTSeg2
tTSeg2
=
=
=
=
=
=
tProp + tPhase1
(1 * tq) + (4 * tq)
5 * tq
tPhase2
(Information Processing Time + 4) × tq
4 * tq
\\Assumes IPT=0
tSJW = 4 * tq
\\Least of 4, Phase1, and Phase2
= TSeg2 -1
TSEG2
= 4-1
=3
= TSeg1 -1
TSEG1
= 5-1
=4
= SJW -1
SJW
= 4-1
=3
= Baud rate prescaler - 1
BRP
= 50-1
=49
The final value programmed into the CANBIT register = 0x34F1.
17.4
Register Map
Table 17-5 on page 1060 lists the registers. All addresses given are relative to the CAN base address
of:
■ CAN0: 0x4004.0000
Note that the CAN controller clock must be enabled before the registers can be programmed (see
page 343). There must be a delay of 3 system clocks after the CAN module clock is enabled before
any CAN module registers are accessed.
Table 17-5. CAN Register Map
Type
Reset
Description
See
page
CANCTL
RW
0x0000.0001
CAN Control
1062
0x004
CANSTS
RW
0x0000.0000
CAN Status
1064
0x008
CANERR
RO
0x0000.0000
CAN Error Counter
1067
0x00C
CANBIT
RW
0x0000.2301
CAN Bit Timing
1068
0x010
CANINT
RO
0x0000.0000
CAN Interrupt
1069
0x014
CANTST
RW
0x0000.0000
CAN Test
1070
0x018
CANBRPE
RW
0x0000.0000
CAN Baud Rate Prescaler Extension
1072
0x020
CANIF1CRQ
RW
0x0000.0001
CAN IF1 Command Request
1073
0x024
CANIF1CMSK
RW
0x0000.0000
CAN IF1 Command Mask
1074
Offset
Name
0x000
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Table 17-5. CAN Register Map (continued)
Description
See
page
0x0000.FFFF
CAN IF1 Mask 1
1077
RW
0x0000.FFFF
CAN IF1 Mask 2
1078
CANIF1ARB1
RW
0x0000.0000
CAN IF1 Arbitration 1
1080
0x034
CANIF1ARB2
RW
0x0000.0000
CAN IF1 Arbitration 2
1081
0x038
CANIF1MCTL
RW
0x0000.0000
CAN IF1 Message Control
1083
0x03C
CANIF1DA1
RW
0x0000.0000
CAN IF1 Data A1
1086
0x040
CANIF1DA2
RW
0x0000.0000
CAN IF1 Data A2
1086
0x044
CANIF1DB1
RW
0x0000.0000
CAN IF1 Data B1
1086
0x048
CANIF1DB2
RW
0x0000.0000
CAN IF1 Data B2
1086
0x080
CANIF2CRQ
RW
0x0000.0001
CAN IF2 Command Request
1073
0x084
CANIF2CMSK
RW
0x0000.0000
CAN IF2 Command Mask
1074
0x088
CANIF2MSK1
RW
0x0000.FFFF
CAN IF2 Mask 1
1077
0x08C
CANIF2MSK2
RW
0x0000.FFFF
CAN IF2 Mask 2
1078
0x090
CANIF2ARB1
RW
0x0000.0000
CAN IF2 Arbitration 1
1080
0x094
CANIF2ARB2
RW
0x0000.0000
CAN IF2 Arbitration 2
1081
0x098
CANIF2MCTL
RW
0x0000.0000
CAN IF2 Message Control
1083
0x09C
CANIF2DA1
RW
0x0000.0000
CAN IF2 Data A1
1086
0x0A0
CANIF2DA2
RW
0x0000.0000
CAN IF2 Data A2
1086
0x0A4
CANIF2DB1
RW
0x0000.0000
CAN IF2 Data B1
1086
0x0A8
CANIF2DB2
RW
0x0000.0000
CAN IF2 Data B2
1086
0x100
CANTXRQ1
RO
0x0000.0000
CAN Transmission Request 1
1087
0x104
CANTXRQ2
RO
0x0000.0000
CAN Transmission Request 2
1087
0x120
CANNWDA1
RO
0x0000.0000
CAN New Data 1
1088
0x124
CANNWDA2
RO
0x0000.0000
CAN New Data 2
1088
0x140
CANMSG1INT
RO
0x0000.0000
CAN Message 1 Interrupt Pending
1089
0x144
CANMSG2INT
RO
0x0000.0000
CAN Message 2 Interrupt Pending
1089
0x160
CANMSG1VAL
RO
0x0000.0000
CAN Message 1 Valid
1090
0x164
CANMSG2VAL
RO
0x0000.0000
CAN Message 2 Valid
1090
Offset
Name
Type
Reset
0x028
CANIF1MSK1
RW
0x02C
CANIF1MSK2
0x030
17.5
CAN Register Descriptions
The remainder of this section lists and describes the CAN registers, in numerical order by address
offset. There are two sets of Interface Registers that are used to access the Message Objects in
the Message RAM: CANIF1x and CANIF2x. The function of the two sets are identical and are used
to queue transactions.
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Register 1: CAN Control (CANCTL), offset 0x000
This control register initializes the module and enables test mode and interrupts.
The bus-off recovery sequence (see CAN Specification Rev. 2.0) cannot be shortened by setting
or clearing INIT. If the device goes bus-off, it sets INIT, stopping all bus activities. Once INIT
has been cleared by the CPU, the device then waits for 129 occurrences of Bus Idle (129 * 11
consecutive High bits) before resuming normal operations. At the end of the bus-off recovery
sequence, the Error Management Counters are reset.
During the waiting time after INIT is cleared, each time a sequence of 11 High bits has been
monitored, a BITERROR0 code is written to the CANSTS register (the LEC field = 0x5), enabling
the CPU to readily check whether the CAN bus is stuck Low or continuously disturbed, and to monitor
the proceeding of the bus-off recovery sequence.
CAN Control (CANCTL)
CAN0 base: 0x4004.0000
Offset 0x000
Type RW, reset 0x0000.0001
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
TEST
CCE
DAR
reserved
EIE
SIE
IE
INIT
RW
0
RW
0
RW
0
RO
0
RW
0
RW
0
RW
0
RW
1
reserved
Type
Reset
reserved
Type
Reset
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7
TEST
RW
0
6
5
CCE
DAR
RW
RW
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Test Mode Enable
Value
Description
0
The CAN controller is operating normally.
1
The CAN controller is in test mode.
Configuration Change Enable
Value
Description
0
Write accesses to the CANBIT register are not allowed.
1
Write accesses to the CANBIT register are allowed if the
INIT bit is 1.
Disable Automatic-Retransmission
Value
Description
0
Auto-retransmission of disturbed messages is enabled.
1
Auto-retransmission is disabled.
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Bit/Field
Name
Type
Reset
4
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
EIE
RW
0
Error Interrupt Enable
2
1
0
SIE
IE
INIT
RW
RW
RW
0
0
1
Description
Value
Description
0
No error status interrupt is generated.
1
A change in the BOFF or EWARN bits in the CANSTS
register generates an interrupt.
Status Interrupt Enable
Value
Description
0
No status interrupt is generated.
1
An interrupt is generated when a message has successfully
been transmitted or received, or a CAN bus error has been
detected. A change in the TXOK, RXOK or LEC bits in the
CANSTS register generates an interrupt.
CAN Interrupt Enable
Value
Description
0
Interrupts disabled.
1
Interrupts enabled.
Initialization
Value
Description
0
Normal operation.
1
Initialization started.
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Register 2: CAN Status (CANSTS), offset 0x004
Important: This register is read-sensitive. See the register description for details.
The status register contains information for interrupt servicing such as Bus-Off, error count threshold,
and error types.
The LEC field holds the code that indicates the type of the last error to occur on the CAN bus. This
field is cleared when a message has been transferred (reception or transmission) without error. The
unused error code 0x7 may be written by the CPU to manually set this field to an invalid error so
that it can be checked for a change later.
An error interrupt is generated by the BOFF and EWARN bits, and a status interrupt is generated by
the RXOK, TXOK, and LEC bits, if the corresponding enable bits in the CAN Control (CANCTL)
register are set. A change of the EPASS bit or a write to the RXOK, TXOK, or LEC bits does not
generate an interrupt.
Reading the CAN Status (CANSTS) register clears the CAN Interrupt (CANINT) register, if it is
pending.
CAN Status (CANSTS)
CAN0 base: 0x4004.0000
Offset 0x004
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
BOFF
EWARN
EPASS
RXOK
TXOK
RO
0
RO
0
RO
0
RW
0
RW
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7
BOFF
RO
0
6
EWARN
RO
0
LEC
RW
0
RW
0
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Bus-Off Status
Value
Description
0
The CAN controller is not in bus-off state.
1
The CAN controller is in bus-off state.
Warning Status
Value
Description
0
Both error counters are below the error warning limit of
96.
1
At least one of the error counters has reached the error
warning limit of 96.
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Bit/Field
Name
Type
Reset
5
EPASS
RO
0
4
RXOK
RW
0
Description
Error Passive
Value
Description
0
The CAN module is in the Error Active state, that is, the
receive or transmit error count is less than or equal to 127.
1
The CAN module is in the Error Passive state, that is, the
receive or transmit error count is greater than 127.
Received a Message Successfully
Value
Description
0
Since this bit was last cleared, no message has been
successfully received.
1
Since this bit was last cleared, a message has been
successfully received, independent of the result of the
acceptance filtering.
This bit must be cleared by writing a 0 to it.
3
TXOK
RW
0
Transmitted a Message Successfully
Value
Description
0
Since this bit was last cleared, no message has been
successfully transmitted.
1
Since this bit was last cleared, a message has been
successfully transmitted error-free and acknowledged by
at least one other node.
This bit must be cleared by writing a 0 to it.
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Bit/Field
Name
Type
Reset
2:0
LEC
RW
0x0
Description
Last Error Code
This is the type of the last error to occur on the CAN bus.
Value
Description
0x0
No Error
0x1
Stuff Error
More than 5 equal bits in a sequence have occurred in a part
of a received message where this is not allowed.
0x2
Format Error
A fixed format part of the received frame has the wrong
format.
0x3
ACK Error
The message transmitted was not acknowledged by another
node.
0x4
Bit 1 Error
When a message is transmitted, the CAN controller monitors
the data lines to detect any conflicts. When the arbitration
field is transmitted, data conflicts are a part of the arbitration
protocol. When other frame fields are transmitted, data
conflicts are considered errors.
A Bit 1 Error indicates that the device wanted to send a High
level (logical 1) but the monitored bus value was Low (logical
0).
0x5
Bit 0 Error
A Bit 0 Error indicates that the device wanted to send a Low
level (logical 0), but the monitored bus value was High (logical
1).
During bus-off recovery, this status is set each time a
sequence of 11 High bits has been monitored. By checking
for this status, software can monitor the proceeding of the
bus-off recovery sequence without any disturbances to the
bus.
0x6
CRC Error
The CRC checksum was incorrect in the received message,
indicating that the calculated value received did not match
the calculated CRC of the data.
0x7
No Event
When the LEC bit shows this value, no CAN bus event was
detected since this value was written to the LEC field.
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Register 3: CAN Error Counter (CANERR), offset 0x008
This register contains the error counter values, which can be used to analyze the cause of an error.
CAN Error Counter (CANERR)
CAN0 base: 0x4004.0000
Offset 0x008
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RP
Type
Reset
RO
0
REC
TEC
RO
0
Bit/Field
Name
Type
Reset
31:16
reserved
RO
0x0000
15
RP
RO
0
14:8
REC
RO
0x00
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Received Error Passive
Value
Description
0
The Receive Error counter is below the Error Passive
level (127 or less).
1
The Receive Error counter has reached the Error Passive
level (128 or greater).
Receive Error Counter
This field contains the state of the receiver error counter (0 to 127).
7:0
TEC
RO
0x00
Transmit Error Counter
This field contains the state of the transmit error counter (0 to 255).
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Register 4: CAN Bit Timing (CANBIT), offset 0x00C
This register is used to program the bit width and bit quantum. Values are programmed to the system
clock frequency. This register is write-enabled by setting the CCE and INIT bits in the CANCTL
register. See “Bit Time and Bit Rate” on page 1055 for more information.
CAN Bit Timing (CANBIT)
CAN0 base: 0x4004.0000
Offset 0x00C
Type RW, reset 0x0000.2301
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RW
0
RW
0
RW
0
RW
1
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RW
1
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
1
reserved
Type
Reset
reserved
Type
Reset
RO
0
TSEG2
RW
0
RW
1
TSEG1
Bit/Field
Name
Type
Reset
31:15
reserved
RO
0x0000
14:12
TSEG2
RW
0x2
SJW
BRP
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Time Segment after Sample Point
0x00-0x07: The actual interpretation by the hardware of this value is
such that one more than the value programmed here is used.
So, for example, the reset value of 0x2 means that 3 (2+1) bit time
quanta are defined for Phase2 (see Figure 17-4 on page 1056). The bit
time quanta is defined by the BRP field.
11:8
TSEG1
RW
0x3
Time Segment Before Sample Point
0x00-0x0F: The actual interpretation by the hardware of this value is
such that one more than the value programmed here is used.
So, for example, the reset value of 0x3 means that 4 (3+1) bit time
quanta are defined for Phase1 (see Figure 17-4 on page 1056). The bit
time quanta is defined by the BRP field.
7:6
SJW
RW
0x0
(Re)Synchronization Jump Width
0x00-0x03: The actual interpretation by the hardware of this value is
such that one more than the value programmed here is used.
During the start of frame (SOF), if the CAN controller detects a phase
error (misalignment), it can adjust the length of TSEG2 or TSEG1 by the
value in SJW. So the reset value of 0 adjusts the length by 1 bit time
quanta.
5:0
BRP
RW
0x1
Baud Rate Prescaler
The value by which the oscillator frequency is divided for generating the
bit time quanta. The bit time is built up from a multiple of this quantum.
0x00-0x03F: The actual interpretation by the hardware of this value is
such that one more than the value programmed here is used.
BRP defines the number of CAN clock periods that make up 1 bit time
quanta, so the reset value is 2 bit time quanta (1+1).
The CANBRPE register can be used to further divide the bit time.
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Tiva™ TM4C1237H6PZ Microcontroller
Register 5: CAN Interrupt (CANINT), offset 0x010
This register indicates the source of the interrupt.
If several interrupts are pending, the CAN Interrupt (CANINT) register points to the pending interrupt
with the highest priority, disregarding the order in which the interrupts occurred. An interrupt remains
pending until the CPU has cleared it. If the INTID field is not 0x0000 (the default) and the IE bit in
the CANCTL register is set, the interrupt is active. The interrupt line remains active until the INTID
field is cleared by reading the CANSTS register, or until the IE bit in the CANCTL register is cleared.
Note:
Reading the CAN Status (CANSTS) register clears the CAN Interrupt (CANINT) register,
if it is pending.
CAN Interrupt (CANINT)
CAN0 base: 0x4004.0000
Offset 0x010
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
INTID
Type
Reset
Bit/Field
Name
Type
Reset
Description
31:16
reserved
RO
0x0000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:0
INTID
RO
0x0000
Interrupt Identifier
The number in this field indicates the source of the interrupt.
Value
Description
0x0000
No interrupt pending
0x0001-0x0020
Number of the message object that
caused the interrupt
0x0021-0x7FFF
Reserved
0x8000
Status Interrupt
0x8001-0xFFFF
Reserved
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Controller Area Network (CAN) Module
Register 6: CAN Test (CANTST), offset 0x014
This register is used for self-test and external pin access. It is write-enabled by setting the TEST bit
in the CANCTL register. Different test functions may be combined, however, CAN transfers are
affected if the TX bits in this register are not zero.
CAN Test (CANTST)
CAN0 base: 0x4004.0000
Offset 0x014
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
LBACK
SILENT
BASIC
RO
0
RO
0
RW
0
RW
0
RW
0
reserved
Type
Reset
reserved
Type
Reset
RX
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7
RX
RO
0
6:5
TX
RW
0x0
TX
RW
0
RW
0
reserved
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Receive Observation
Value
Description
0
The CANnRx pin is low.
1
The CANnRx pin is high.
Transmit Control
Overrides control of the CANnTx pin.
Value
Description
0x0
CAN Module Control
CANnTx is controlled by the CAN module; default
operation
0x1
Sample Point
The sample point is driven on the CANnTx signal. This
mode is useful to monitor bit timing.
0x2
Driven Low
CANnTx drives a low value. This mode is useful for
checking the physical layer of the CAN bus.
0x3
Driven High
CANnTx drives a high value. This mode is useful for
checking the physical layer of the CAN bus.
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Tiva™ TM4C1237H6PZ Microcontroller
Bit/Field
Name
Type
Reset
4
LBACK
RW
0
3
2
1:0
SILENT
BASIC
reserved
RW
RW
RO
0
0
0x0
Description
Loopback Mode
Value
Description
0
Loopback mode is disabled.
1
Loopback mode is enabled. In loopback mode, the data
from the transmitter is routed into the receiver. Any data
on the receive input is ignored.
Silent Mode
Value
Description
0
Silent mode is disabled.
1
Silent mode is enabled. In silent mode, the CAN controller
does not transmit data but instead monitors the bus. This
mode is also known as Bus Monitor mode.
Basic Mode
Value
Description
0
Basic mode is disabled.
1
Basic mode is enabled. In basic mode, software should
use the CANIF1 registers as the transmit buffer and use
the CANIF2 registers as the receive buffer.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Controller Area Network (CAN) Module
Register 7: CAN Baud Rate Prescaler Extension (CANBRPE), offset 0x018
This register is used to further divide the bit time set with the BRP bit in the CANBIT register. It is
write-enabled by setting the CCE bit in the CANCTL register.
CAN Baud Rate Prescaler Extension (CANBRPE)
CAN0 base: 0x4004.0000
Offset 0x018
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:4
reserved
RO
0x0000.000
3:0
BRPE
RW
0x0
BRPE
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Baud Rate Prescaler Extension
0x00-0x0F: Extend the BRP bit in the CANBIT register to values up to
1023. The actual interpretation by the hardware is one more than the
value programmed by BRPE (MSBs) and BRP (LSBs).
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Tiva™ TM4C1237H6PZ Microcontroller
Register 8: CAN IF1 Command Request (CANIF1CRQ), offset 0x020
Register 9: CAN IF2 Command Request (CANIF2CRQ), offset 0x080
A message transfer is started as soon as there is a write of the message object number to the MNUM
field when the TXRQST bit in the CANIF1MCTL register is set. With this write operation, the BUSY
bit is automatically set to indicate that a transfer between the CAN Interface Registers and the
internal message RAM is in progress. After a wait time of 3 to 6 CAN_CLK periods, the transfer
between the interface register and the message RAM completes, which then clears the BUSY bit.
CAN IFn Command Request (CANIFnCRQ)
CAN0 base: 0x4004.0000
Offset 0x020
Type RW, reset 0x0000.0001
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
1
reserved
Type
Reset
BUSY
Type
Reset
RO
0
reserved
RO
0
MNUM
Bit/Field
Name
Type
Reset
31:16
reserved
RO
0x0000
15
BUSY
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Busy Flag
Value
Description
0
This bit is cleared when read/write action has finished.
1
This bit is set when a write occurs to the message
number in this register.
14:6
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5:0
MNUM
RW
0x01
Message Number
Selects one of the 32 message objects in the message RAM for data
transfer. The message objects are numbered from 1 to 32.
Value
Description
0x00
Reserved
0 is not a valid message number; it is interpreted
as 0x20, or object 32.
0x01-0x20
Message Number
Indicates specified message object 1 to 32.
0x21-0x3F
Reserved
Not a valid message number; values are shifted and
it is interpreted as 0x01-0x1F.
June 12, 2014
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Controller Area Network (CAN) Module
Register 10: CAN IF1 Command Mask (CANIF1CMSK), offset 0x024
Register 11: CAN IF2 Command Mask (CANIF2CMSK), offset 0x084
Reading the Command Mask registers provides status for various functions. Writing to the Command
Mask registers specifies the transfer direction and selects which buffer registers are the source or
target of the data transfer.
Note that when a read from the message object buffer occurs when the WRNRD bit is clear and the
CLRINTPND and/or NEWDAT bits are set, the interrupt pending and/or new data flags in the message
object buffer are cleared.
CAN IFn Command Mask (CANIFnCMSK)
CAN0 base: 0x4004.0000
Offset 0x024
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
WRNRD
MASK
ARB
CONTROL
CLRINTPND
NEWDAT / TXRQST
reserved
DATAA
DATAB
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7
WRNRD
RW
0
6
MASK
RW
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Write, Not Read
Value
Description
0
Transfer the data in the CAN message object specified by
the MNUM field in the CANIFnCRQ register into the CANIFn
registers.
1
Transfer the data in the CANIFn registers to the CAN
message object specified by the MNUM field in the CAN
Command Request (CANIFnCRQ).
Note:
Interrupt pending and new data conditions in the message
buffer can be cleared by reading from the buffer (WRNRD = 0)
when the CLRINTPND and/or NEWDAT bits are set.
Access Mask Bits
Value
Description
0
Mask bits unchanged.
1
Transfer IDMASK + DIR + MXTD of the message object
into the Interface registers.
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Bit/Field
Name
Type
Reset
5
ARB
RW
0
4
3
CONTROL
CLRINTPND
RW
RW
0
0
Description
Access Arbitration Bits
Value
Description
0
Arbitration bits unchanged.
1
Transfer ID + DIR + XTD + MSGVAL of the message
object into the Interface registers.
Access Control Bits
Value
Description
0
Control bits unchanged.
1
Transfer control bits from the CANIFnMCTL register
into the Interface registers.
Clear Interrupt Pending Bit
The function of this bit depends on the configuration of the WRNRD bit.
Value
Description
0
If WRNRD is clear, the interrupt pending status is transferred
from the message buffer into the CANIFnMCTL register.
If WRNRD is set, the INTPND bit in the message object remains
unchanged.
1
If WRNRD is clear, the interrupt pending status is cleared in the
message buffer. Note the value of this bit that is transferred
to the CANIFnMCTL register always reflects the status of the
bits before clearing.
If WRNRD is set, the INTPND bit is cleared in the message
object.
2
NEWDAT / TXRQST
RW
0
NEWDAT / TXRQST Bit
The function of this bit depends on the configuration of the WRNRD bit.
Value
Description
0
If WRNRD is clear, the value of the new data status is transferred
from the message buffer into the CANIFnMCTL register.
If WRNRD is set, a transmission is not requested.
1
If WRNRD is clear, the new data status is cleared in the message
buffer. Note the value of this bit that is transferred to the
CANIFnMCTL register always reflects the status of the bits
before clearing.
If WRNRD is set, a transmission is requested. Note that when
this bit is set, the TXRQST bit in the CANIFnMCTL register is
ignored.
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Controller Area Network (CAN) Module
Bit/Field
Name
Type
Reset
1
DATAA
RW
0
Description
Access Data Byte 0 to 3
The function of this bit depends on the configuration of the WRNRD bit.
Value
Description
0
Data bytes 0-3 are unchanged.
1
If WRNRD is clear, transfer data bytes 0-3 in CANIFnDA1
and CANIFnDA2 to the message object.
If WRNRD is set, transfer data bytes 0-3 in message object
to CANIFnDA1 and CANIFnDA2.
0
DATAB
RW
0
Access Data Byte 4 to 7
The function of this bit depends on the configuration of the WRNRD bit
as follows:
Value
Description
0
Data bytes 4-7 are unchanged.
1
If WRNRD is clear, transfer data bytes 4-7 in CANIFnDA1
and CANIFnDA2 to the message object.
If WRNRD is set, transfer data bytes 4-7 in message object
to CANIFnDA1 and CANIFnDA2.
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Tiva™ TM4C1237H6PZ Microcontroller
Register 12: CAN IF1 Mask 1 (CANIF1MSK1), offset 0x028
Register 13: CAN IF2 Mask 1 (CANIF2MSK1), offset 0x088
The mask information provided in this register accompanies the data (CANIFnDAn), arbitration
information (CANIFnARBn), and control information (CANIFnMCTL) to the message object in the
message RAM. The mask is used with the ID bit in the CANIFnARBn register for acceptance
filtering. Additional mask information is contained in the CANIFnMSK2 register.
CAN IFn Mask 1 (CANIFnMSK1)
CAN0 base: 0x4004.0000
Offset 0x028
Type RW, reset 0x0000.FFFF
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
reserved
Type
Reset
MSK
Type
Reset
Bit/Field
Name
Type
Reset
Description
31:16
reserved
RO
0x0000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:0
MSK
RW
0xFFFF
Identifier Mask
When using a 29-bit identifier, these bits are used for bits [15:0] of the
ID. The MSK field in the CANIFnMSK2 register are used for bits [28:16]
of the ID. When using an 11-bit identifier, these bits are ignored.
Value
Description
0
The corresponding identifier field (ID) in the message
object cannot inhibit the match in acceptance filtering.
1
The corresponding identifier field (ID) is used for
acceptance filtering.
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Controller Area Network (CAN) Module
Register 14: CAN IF1 Mask 2 (CANIF1MSK2), offset 0x02C
Register 15: CAN IF2 Mask 2 (CANIF2MSK2), offset 0x08C
This register holds extended mask information that accompanies the CANIFnMSK1 register.
CAN IFn Mask 2 (CANIFnMSK2)
CAN0 base: 0x4004.0000
Offset 0x02C
Type RW, reset 0x0000.FFFF
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
MXTD
MDIR
reserved
RW
1
RW
1
RO
1
RW
0
RW
0
RW
0
RW
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RW
0
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
reserved
Type
Reset
Type
Reset
MSK
Bit/Field
Name
Type
Reset
31:16
reserved
RO
0x0000
15
MXTD
RW
1
14
13
MDIR
reserved
RW
RO
1
1
RW
1
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Mask Extended Identifier
Value
Description
0
The extended identifier bit (XTD in the CANIFnARB2
register) has no effect on the acceptance filtering.
1
The extended identifier bit XTD is used for acceptance
filtering.
Mask Message Direction
Value
Description
0
The message direction bit (DIR in the CANIFnARB2
register) has no effect for acceptance filtering.
1
The message direction bit DIR is used for acceptance
filtering.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Tiva™ TM4C1237H6PZ Microcontroller
Bit/Field
Name
Type
Reset
Description
12:0
MSK
RW
0xFF
Identifier Mask
When using a 29-bit identifier, these bits are used for bits [28:16] of the
ID. The MSK field in the CANIFnMSK1 register are used for bits [15:0]
of the ID. When using an 11-bit identifier, MSK[12:2] are used for bits
[10:0] of the ID.
Value
Description
0
The corresponding identifier field (ID) in the message
object cannot inhibit the match in acceptance filtering.
1
The corresponding identifier field (ID) is used for
acceptance filtering.
June 12, 2014
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Controller Area Network (CAN) Module
Register 16: CAN IF1 Arbitration 1 (CANIF1ARB1), offset 0x030
Register 17: CAN IF2 Arbitration 1 (CANIF2ARB1), offset 0x090
These registers hold the identifiers for acceptance filtering.
CAN IFn Arbitration 1 (CANIFnARB1)
CAN0 base: 0x4004.0000
Offset 0x030
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
ID
Type
Reset
Bit/Field
Name
Type
Reset
Description
31:16
reserved
RO
0x0000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:0
ID
RW
0x0000
Message Identifier
This bit field is used with the ID field in the CANIFnARB2 register to
create the message identifier.
When using a 29-bit identifier, bits 15:0 of the CANIFnARB1 register
are [15:0] of the ID, while bits 12:0 of the CANIFnARB2 register are
[28:16] of the ID.
When using an 11-bit identifier, these bits are not used.
1080
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Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Register 18: CAN IF1 Arbitration 2 (CANIF1ARB2), offset 0x034
Register 19: CAN IF2 Arbitration 2 (CANIF2ARB2), offset 0x094
These registers hold information for acceptance filtering.
CAN IFn Arbitration 2 (CANIFnARB2)
CAN0 base: 0x4004.0000
Offset 0x034
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
MSGVAL
XTD
DIR
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
Type
Reset
ID
Bit/Field
Name
Type
Reset
31:16
reserved
RO
0x0000
15
MSGVAL
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Message Valid
Value
Description
0
The message object is ignored by the message handler.
1
The message object is configured and ready to be
considered by the message handler within the CAN
controller.
All unused message objects should have this bit cleared during
initialization and before clearing the INIT bit in the CANCTL register.
The MSGVAL bit must also be cleared before any of the following bits
are modified or if the message object is no longer required: the ID fields
in the CANIFnARBn registers, the XTD and DIR bits in the CANIFnARB2
register, or the DLC field in the CANIFnMCTL register.
14
XTD
RW
0
Extended Identifier
Value
Description
0
An 11-bit Standard Identifier is used for this message
object.
1
A 29-bit Extended Identifier is used for this message
object.
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Bit/Field
Name
Type
Reset
13
DIR
RW
0
12:0
ID
RW
0x000
Description
Message Direction
Value
Description
0
Receive. When the TXRQST bit in the CANIFnMCTL register
is set, a remote frame with the identifier of this message object
is received. On reception of a data frame with matching
identifier, that message is stored in this message object.
1
Transmit. When the TXRQST bit in the CANIFnMCTL register
is set, the respective message object is transmitted as a data
frame. On reception of a remote frame with matching identifier,
the TXRQST bit of this message object is set (if RMTEN=1).
Message Identifier
This bit field is used with the ID field in the CANIFnARB2 register to
create the message identifier.
When using a 29-bit identifier, ID[15:0] of the CANIFnARB1 register
are [15:0] of the ID, while these bits, ID[12:0], are [28:16] of the ID.
When using an 11-bit identifier, ID[12:2] are used for bits [10:0] of
the ID. The ID field in the CANIFnARB1 register is ignored.
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Register 20: CAN IF1 Message Control (CANIF1MCTL), offset 0x038
Register 21: CAN IF2 Message Control (CANIF2MCTL), offset 0x098
This register holds the control information associated with the message object to be sent to the
Message RAM.
CAN IFn Message Control (CANIFnMCTL)
CAN0 base: 0x4004.0000
Offset 0x038
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
UMASK
TXIE
RXIE
RW
0
RW
0
RW
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RMTEN
TXRQST
EOB
RW
0
RW
0
RW
0
RO
0
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
NEWDAT MSGLST INTPND
Type
Reset
RW
0
RW
0
RW
0
Bit/Field
Name
Type
Reset
31:16
reserved
RO
0x0000
15
NEWDAT
RW
0
14
MSGLST
RW
0
reserved
RO
0
RO
0
DLC
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
New Data
Value
Description
0
No new data has been written into the data portion of this
message object by the message handler since the last time
this flag was cleared by the CPU.
1
The message handler or the CPU has written new data into
the data portion of this message object.
Message Lost
Value
Description
0
No message was lost since the last time this bit was
cleared by the CPU.
1
The message handler stored a new message into this
object when NEWDAT was set; the CPU has lost a message.
This bit is only valid for message objects when the DIR bit in the
CANIFnARB2 register is clear (receive).
13
INTPND
RW
0
Interrupt Pending
Value
Description
0
This message object is not the source of an interrupt.
1
This message object is the source of an interrupt. The
interrupt identifier in the CANINT register points to this
message object if there is not another interrupt source with
a higher priority.
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Bit/Field
Name
Type
Reset
12
UMASK
RW
0
11
10
9
8
TXIE
RXIE
RMTEN
TXRQST
RW
RW
RW
RW
0
0
0
0
Description
Use Acceptance Mask
Value
Description
0
Mask is ignored.
1
Use mask (MSK, MXTD, and MDIR bits in the
CANIFnMSKn registers) for acceptance filtering.
Transmit Interrupt Enable
Value
Description
0
The INTPND bit in the CANIFnMCTL register is unchanged
after a successful transmission of a frame.
1
The INTPND bit in the CANIFnMCTL register is set after
a successful transmission of a frame.
Receive Interrupt Enable
Value
Description
0
The INTPND bit in the CANIFnMCTL register is unchanged
after a successful reception of a frame.
1
The INTPND bit in the CANIFnMCTL register is set after
a successful reception of a frame.
Remote Enable
Value
Description
0
At the reception of a remote frame, the TXRQST bit in the
CANIFnMCTL register is left unchanged.
1
At the reception of a remote frame, the TXRQST bit in the
CANIFnMCTL register is set.
Transmit Request
Value
Description
0
This message object is not waiting for transmission.
1
The transmission of this message object is requested
and is not yet done.
Note:
If the WRNRD and TXRQST bits in the CANIFnCMSK register
are set, this bit is ignored.
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Bit/Field
Name
Type
Reset
7
EOB
RW
0
Description
End of Buffer
Value
Description
0
Message object belongs to a FIFO Buffer and is not the
last message object of that FIFO Buffer.
1
Single message object or last message object of a FIFO
Buffer.
This bit is used to concatenate two or more message objects (up to 32)
to build a FIFO buffer. For a single message object (thus not belonging
to a FIFO buffer), this bit must be set.
6:4
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3:0
DLC
RW
0x0
Data Length Code
Value
Description
0x0-0x8
Specifies the number of bytes in the data frame.
0x9-0xF
Defaults to a data frame with 8 bytes.
The DLC field in the CANIFnMCTL register of a message object must
be defined the same as in all the corresponding objects with the same
identifier at other nodes. When the message handler stores a data frame,
it writes DLC to the value given by the received message.
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Controller Area Network (CAN) Module
Register 22: CAN IF1 Data A1 (CANIF1DA1), offset 0x03C
Register 23: CAN IF1 Data A2 (CANIF1DA2), offset 0x040
Register 24: CAN IF1 Data B1 (CANIF1DB1), offset 0x044
Register 25: CAN IF1 Data B2 (CANIF1DB2), offset 0x048
Register 26: CAN IF2 Data A1 (CANIF2DA1), offset 0x09C
Register 27: CAN IF2 Data A2 (CANIF2DA2), offset 0x0A0
Register 28: CAN IF2 Data B1 (CANIF2DB1), offset 0x0A4
Register 29: CAN IF2 Data B2 (CANIF2DB2), offset 0x0A8
These registers contain the data to be sent or that has been received. In a CAN data frame, data
byte 0 is the first byte to be transmitted or received and data byte 7 is the last byte to be transmitted
or received. In CAN's serial bit stream, the MSB of each byte is transmitted first.
CAN IFn Data nn (CANIFnDnn)
CAN0 base: 0x4004.0000
Offset 0x03C
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
DATA
Type
Reset
Bit/Field
Name
Type
Reset
Description
31:16
reserved
RO
0x0000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:0
DATA
RW
0x0000
Data
The CANIFnDA1 registers contain data bytes 1 and 0; CANIFnDA2
data bytes 3 and 2; CANIFnDB1 data bytes 5 and 4; and CANIFnDB2
data bytes 7 and 6.
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Register 30: CAN Transmission Request 1 (CANTXRQ1), offset 0x100
Register 31: CAN Transmission Request 2 (CANTXRQ2), offset 0x104
The CANTXRQ1 and CANTXRQ2 registers hold the TXRQST bits of the 32 message objects. By
reading out these bits, the CPU can check which message object has a transmission request pending.
The TXRQST bit of a specific message object can be changed by three sources: (1) the CPU via the
CANIFnMCTL register, (2) the message handler state machine after the reception of a remote
frame, or (3) the message handler state machine after a successful transmission.
The CANTXRQ1 register contains the TXRQST bits of the first 16 message objects in the message
RAM; the CANTXRQ2 register contains the TXRQST bits of the second 16 message objects.
CAN Transmission Request n (CANTXRQn)
CAN0 base: 0x4004.0000
Offset 0x100
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
TXRQST
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:16
reserved
RO
0x0000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:0
TXRQST
RO
0x0000
Transmission Request Bits
Value
Description
0
The corresponding message object is not waiting for
transmission.
1
The transmission of the corresponding message object
is requested and is not yet done.
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Controller Area Network (CAN) Module
Register 32: CAN New Data 1 (CANNWDA1), offset 0x120
Register 33: CAN New Data 2 (CANNWDA2), offset 0x124
The CANNWDA1 and CANNWDA2 registers hold the NEWDAT bits of the 32 message objects. By
reading these bits, the CPU can check which message object has its data portion updated. The
NEWDAT bit of a specific message object can be changed by three sources: (1) the CPU via the
CANIFnMCTL register, (2) the message handler state machine after the reception of a data frame,
or (3) the message handler state machine after a successful transmission.
The CANNWDA1 register contains the NEWDAT bits of the first 16 message objects in the message
RAM; the CANNWDA2 register contains the NEWDAT bits of the second 16 message objects.
CAN New Data n (CANNWDAn)
CAN0 base: 0x4004.0000
Offset 0x120
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
NEWDAT
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:16
reserved
RO
0x0000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:0
NEWDAT
RO
0x0000
New Data Bits
Value
Description
0
No new data has been written into the data portion of the
corresponding message object by the message handler since
the last time this flag was cleared by the CPU.
1
The message handler or the CPU has written new data into
the data portion of the corresponding message object.
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Register 34: CAN Message 1 Interrupt Pending (CANMSG1INT), offset 0x140
Register 35: CAN Message 2 Interrupt Pending (CANMSG2INT), offset 0x144
The CANMSG1INT and CANMSG2INT registers hold the INTPND bits of the 32 message objects.
By reading these bits, the CPU can check which message object has an interrupt pending. The
INTPND bit of a specific message object can be changed through two sources: (1) the CPU via the
CANIFnMCTL register, or (2) the message handler state machine after the reception or transmission
of a frame.
This field is also encoded in the CANINT register.
The CANMSG1INT register contains the INTPND bits of the first 16 message objects in the message
RAM; the CANMSG2INT register contains the INTPND bits of the second 16 message objects.
CAN Message n Interrupt Pending (CANMSGnINT)
CAN0 base: 0x4004.0000
Offset 0x140
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
INTPND
Type
Reset
Bit/Field
Name
Type
Reset
Description
31:16
reserved
RO
0x0000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:0
INTPND
RO
0x0000
Interrupt Pending Bits
Value
Description
0
The corresponding message object is not the source of
an interrupt.
1
The corresponding message object is the source of an
interrupt.
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Controller Area Network (CAN) Module
Register 36: CAN Message 1 Valid (CANMSG1VAL), offset 0x160
Register 37: CAN Message 2 Valid (CANMSG2VAL), offset 0x164
The CANMSG1VAL and CANMSG2VAL registers hold the MSGVAL bits of the 32 message objects.
By reading these bits, the CPU can check which message object is valid. The message valid bit of
a specific message object can be changed with the CANIFnARB2 register.
The CANMSG1VAL register contains the MSGVAL bits of the first 16 message objects in the message
RAM; the CANMSG2VAL register contains the MSGVAL bits of the second 16 message objects in
the message RAM.
CAN Message n Valid (CANMSGnVAL)
CAN0 base: 0x4004.0000
Offset 0x160
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
MSGVAL
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:16
reserved
RO
0x0000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:0
MSGVAL
RO
0x0000
Message Valid Bits
Value
Description
0
The corresponding message object is not configured and
is ignored by the message handler.
1
The corresponding message object is configured and
should be considered by the message handler.
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18
Universal Serial Bus (USB) Controller
The TM4C1237H6PZ USB controller operates as a full-speed or low-speed function controller during
point-to-point communications with USB Host, Device, or OTG functions. The controller complies
with the USB 2.0 standard, which includes SUSPEND and RESUME signaling. 16 endpoints including
two hard-wired for control transfers (one endpoint for IN and one endpoint for OUT) plus 14 endpoints
defined by firmware along with a dynamic sizable FIFO support multiple packet queueing. µDMA
access to the FIFO allows minimal interference from system software. Software-controlled connect
and disconnect allows flexibility during USB device start-up. The controller complies with OTG
Standard's Session Request Protocol (SRP) and Host Negotiation Protocol (HNP).
The TM4C1237H6PZ USB module has the following features:
■ Complies with USB-IF (Implementer's Forum) certification standards
■ USB 2.0 full-speed (12 Mbps) and low-speed (1.5 Mbps) operation with integrated PHY
■ 4 transfer types: Control, Interrupt, Bulk, and Isochronous
■ 16 endpoints
– 1 dedicated control IN endpoint and 1 dedicated control OUT endpoint
– 7 configurable IN endpoints and 7 configurable OUT endpoints
■ 4 KB dedicated endpoint memory: one endpoint may be defined for double-buffered 1023-byte
isochronous packet size
■ VBUS droop and valid ID detection and interrupt
■ Efficient transfers using Micro Direct Memory Access Controller (µDMA)
– Separate channels for transmit and receive for up to three IN endpoints and three OUT
endpoints
– Channel requests asserted when FIFO contains required amount of data
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18.1
Block Diagram
Figure 18-1. USB Module Block Diagram
DMA
Requests
Endpoint Control
Transmit
EP0 – 31
Control
Receive
CPU Interface
Combine
Endpoints
Host
Transaction
Scheduler
Interrupt
Control
Interrupts
EP Reg.
Decoder
USB PHY
USB FS/LS
PHY
UTM
Synchronization
Packet
Encode/Decode
Data Sync
Packet Encode
HNP/SRP
Packet Decode
Timers
CRC Gen/Check
FIFO RAM
Controller
Rx
Rx
Buff
Buff
Tx
Buff
Common
Regs
AHB bus –
Slave mode
Cycle
Control
Tx
Buff
Cycle Control
FIFO
Decoder
USB Data Lines
D+ and D-
18.2
Signal Description
The following table lists the external signals of the USB controller and describes the function of
each. Some USB controller signals are alternate functions for some GPIO signals and default to be
GPIO signals at reset. The column in the table below titled "Pin Mux/Pin Assignment" lists the
possible GPIO pin placements for these USB signals. The AFSEL bit in the GPIO Alternate Function
Select (GPIOAFSEL) register (page 659) should be set to choose the USB function. The number in
parentheses is the encoding that must be programmed into the PMCn field in the GPIO Port Control
(GPIOPCTL) register (page 677) to assign the USB signal to the specified GPIO port pin. The
USB0VBUS and USB0ID signals are configured by clearing the appropriate DEN bit in the GPIO
Digital Enable (GPIODEN) register. For more information on configuring GPIOs, see
“General-Purpose Input/Outputs (GPIOs)” on page 634. The remaining signals (with the word "fixed"
in the Pin Mux/Pin Assignment column) have a fixed pin assignment and function.
Note:
When used in OTG mode, USB0VBUS and USB0ID do not require any configuration as they
are dedicated pins for the USB controller and directly connect to the USB connector's VBUS
and ID signals. If the USB controller is used as either a dedicated Host or Device, the
DEVMODOTG and DEVMOD bits in the USB General-Purpose Control and Status
(USBGPCS) register can be used to connect the USB0VBUS and USB0ID inputs to fixed
levels internally, freeing the PB0 and PB1 pins for GPIO use. For proper self-powered Device
operation, the VBUS value must still be monitored to assure that if the Host removes VBUS,
the self-powered Device disables the D+/D- pull-up resistors. This function can be
accomplished by connecting a standard GPIO to VBUS.
The termination resistors for the USB PHY have been added internally, and thus there is
no need for external resistors. For a device, there is a 1.5 KOhm pull-up on the D+ and for
a host there are 15 KOhm pull-downs on both D+ and D-.
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Table 18-1. USB Signals (100LQFP)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
USB0DM
68
PJ0
I/O
Analog
Bidirectional differential data pin (D- per USB
specification) for USB0.
USB0DP
69
PJ1
I/O
Analog
Bidirectional differential data pin (D+ per USB
specification) for USB0.
USB0EPEN
3
23
39
74
PD2 (8)
PC6 (8)
PF4 (8)
PG4 (8)
O
TTL
Optionally used in Host mode to control an external
power source to supply power to the USB bus.
USB0ID
70
PB0
I
Analog
This signal senses the state of the USB ID signal.
The USB PHY enables an integrated pull-up, and
an external element (USB connector) indicates the
initial state of the USB controller (pulled down is
the A side of the cable and pulled up is the B side).
USB0PFLT
4
22
37
75
PD3 (8)
PC7 (8)
PF5 (8)
PG5 (8)
I
TTL
Optionally used in Host mode by an external power
source to indicate an error state by that power
source.
USB0VBUS
71
PB1
I/O
Analog
This signal is used during the session request
protocol. This signal allows the USB PHY to both
sense the voltage level of VBUS, and pull up VBUS
momentarily during VBUS pulsing.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
18.3
Functional Description
The TM4C1237H6PZ USB controller provides full OTG negotiation by supporting both the Session
Request Protocol (SRP) and the Host Negotiation Protocol (HNP). The session request protocol
allows devices on the B side of a cable to request the A side device turn on VBUS. The host
negotiation protocol is used after the initial session request protocol has powered the bus and
provides a method to determine which end of the cable will act as the Host controller. When the
device is connected to non-OTG peripherals or devices, the controller can detect which cable end
was used and provides a register to indicate if the controller should act as the Host or the Device
controller. This indication and the mode of operation are handled automatically by the USB controller.
This auto-detection allows the system to use a single A/B connector instead of having both A and
B connectors in the system and supports full OTG negotiations with other OTG devices.
In addition, the USB controller provides support for connecting to non-OTG peripherals or Host
controllers. The USB controller can be configured to act as either a dedicated Host or Device, in
which case, the USB0VBUS and USB0ID signals can be used as GPIOs or any corresponding
alternate functions. However, when the USB controller is acting as a self-powered Device, a GPIO
input or analog comparator input must be connected to VBUS and configured to generate an interrupt
when the VBUS level drops. This interrupt is used to disable the pull-up resistor on the USB0DP
signal.
Note:
18.3.1
When the USB module is in operation, MOSC must be the clock source, either with or
without using the PLL, and the system clock must be at least 20 MHz.
Operation as a Device
This section describes the TM4C1237H6PZ USB controller's actions when it is being used as a
USB Device. Before the USB controller's operating mode is changed from Device to Host or Host
to Device, software must reset the USB controller by setting the USB0 bit in the Software Reset
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Control 2 (SRCR2) register (see page 440). IN endpoints, OUT endpoints, entry into and exit from
SUSPEND mode, and recognition of Start of Frame (SOF) are all described.
When in Device mode, IN transactions are controlled by an endpoint's transmit interface and use
the transmit endpoint registers for the given endpoint. OUT transactions are handled with an
endpoint's receive interface and use the receive endpoint registers for the given endpoint.
When configuring the size of the FIFOs for endpoints, take into account the maximum packet size
for an endpoint.
■ Bulk. Bulk endpoints should be the size of the maximum packet (up to 64 bytes) or twice the
maximum packet size if double buffering is used (described further in the following section).
■ Interrupt. Interrupt endpoints should be the size of the maximum packet (up to 64 bytes) or twice
the maximum packet size if double buffering is used.
■ Isochronous. Isochronous endpoints are more flexible and can be up to 1023 bytes.
■ Control. It is also possible to specify a separate control endpoint for a USB Device. However,
in most cases the USB Device should use the dedicated control endpoint on the USB controller's
endpoint 0.
18.3.1.1
Endpoints
When operating as a Device, the USB controller provides two dedicated control endpoints (IN and
OUT) and 14 configurable endpoints (7 IN and 7 OUT) that can be used for communications with
a Host controller. The endpoint number and direction associated with an endpoint is directly related
to its register designation. For example, when the Host is transmitting to endpoint 1, all configuration
and data is in the endpoint 1 transmit register interface.
Endpoint 0 is a dedicated control endpoint used for all control transactions to endpoint 0 during
enumeration or when any other control requests are made to endpoint 0. Endpoint 0 uses the first
64 bytes of the USB controller's FIFO RAM as a shared memory for both IN and OUT transactions.
The remaining 14 endpoints can be configured as control, bulk, interrupt, or isochronous endpoints.
They should be treated as 7 configurable IN and 7 configurable OUT endpoints. The endpoint pairs
are not required to have the same type for their IN and OUT endpoint configuration. For example,
the OUT portion of an endpoint pair could be a bulk endpoint, while the IN portion of that endpoint
pair could be an interrupt endpoint. The address and size of the FIFOs attached to each endpoint
can be modified to fit the application's needs.
18.3.1.2
IN Transactions as a Device
When operating as a USB Device, data for IN transactions is handled through the FIFOs attached
to the transmit endpoints. The sizes of the FIFOs for the 7 configurable IN endpoints are determined
by the USB Transmit FIFO Start Address (USBTXFIFOADD) register. The maximum size of a
data packet that may be placed in a transmit endpoint's FIFO for transmission is programmable and
is determined by the value written to the USB Maximum Transmit Data Endpoint n (USBTXMAXPn)
register for that endpoint. The endpoint's FIFO can also be configured to use double-packet or
single-packet buffering. When double-packet buffering is enabled, two data packets can be buffered
in the FIFO, which also requires that the FIFO is at least two packets in size. When double-packet
buffering is disabled, only one packet can be buffered, even if the packet size is less than half the
FIFO size.
Note:
The maximum packet size set for any endpoint must not exceed the FIFO size. The
USBTXMAXPn register should not be written to while data is in the FIFO as unexpected
results may occur.
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Single-Packet Buffering
If the size of the transmit endpoint's FIFO is less than twice the maximum packet size for this endpoint
(as set in the USB Transmit Dynamic FIFO Sizing (USBTXFIFOSZ) register), only one packet
can be buffered in the FIFO and single-packet buffering is required. When each packet is completely
loaded into the transmit FIFO, the TXRDY bit in the USB Transmit Control and Status Endpoint
n Low (USBTXCSRLn) register must be set. If the AUTOSET bit in the USB Transmit Control and
Status Endpoint n High (USBTXCSRHn) register is set, the TXRDY bit is automatically set when
a maximum-sized packet is loaded into the FIFO. For packet sizes less than the maximum, the
TXRDY bit must be set manually. When the TXRDY bit is set, either manually or automatically, the
packet is ready to be sent. When the packet has been successfully sent, both TXRDY and FIFONE
are cleared, and the appropriate transmit endpoint interrupt signaled. At this point, the next packet
can be loaded into the FIFO.
Double-Packet Buffering
If the size of the transmit endpoint's FIFO is at least twice the maximum packet size for this endpoint,
two packets can be buffered in the FIFO and double-packet buffering is allowed. As each packet is
loaded into the transmit FIFO, the TXRDY bit in the USBTXCSRLn register must be set. If the
AUTOSET bit in the USBTXCSRHn register is set, the TXRDY bit is automatically set when a
maximum-sized packet is loaded into the FIFO. For packet sizes less than the maximum, TXRDY
must be set manually. When the TXRDY bit is set, either manually or automatically, the packet is
ready to be sent. After the first packet is loaded, TXRDY is immediately cleared and an interrupt is
generated. A second packet can now be loaded into the transmit FIFO and TXRDY set again (either
manually or automatically if the packet is the maximum size). At this point, both packets are ready
to be sent. After each packet has been successfully sent, TXRDY is automatically cleared and the
appropriate transmit endpoint interrupt signaled to indicate that another packet can now be loaded
into the transmit FIFO. The state of the FIFONE bit in the USBTXCSRLn register at this point
indicates how many packets may be loaded. If the FIFONE bit is set, then another packet is in the
FIFO and only one more packet can be loaded. If the FIFONE bit is clear, then no packets are in
the FIFO and two more packets can be loaded.
Note:
18.3.1.3
Double-packet buffering is disabled if an endpoint's corresponding EPn bit is set in the USB
Transmit Double Packet Buffer Disable (USBTXDPKTBUFDIS) register. This bit is set
by default, so it must be cleared to enable double-packet buffering.
OUT Transactions as a Device
When in Device mode, OUT transactions are handled through the USB controller receive FIFOs.
The sizes of the receive FIFOs for the 7 configurable OUT endpoints are determined by the USB
Receive FIFO Start Address (USBRXFIFOADD) register. The maximum amount of data received
by an endpoint in any packet is determined by the value written to the USB Maximum Receive
Data Endpoint n (USBRXMAXPn) register for that endpoint. When double-packet buffering is
enabled, two data packets can be buffered in the FIFO. When double-packet buffering is disabled,
only one packet can be buffered even if the packet is less than half the FIFO size.
Note:
In all cases, the maximum packet size must not exceed the FIFO size.
Single-Packet Buffering
If the size of the receive endpoint FIFO is less than twice the maximum packet size for an endpoint,
only one data packet can be buffered in the FIFO and single-packet buffering is required. When a
packet is received and placed in the receive FIFO, the RXRDY and FULL bits in the USB Receive
Control and Status Endpoint n Low (USBRXCSRLn) register are set and the appropriate receive
endpoint is signaled, indicating that a packet can now be unloaded from the FIFO. After the packet
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has been unloaded, the RXRDY bit must be cleared in order to allow further packets to be received.
This action also generates the acknowledge signaling to the Host controller. If the AUTOCL bit in the
USB Receive Control and Status Endpoint n High (USBRXCSRHn) register is set and a
maximum-sized packet is unloaded from the FIFO, the RXRDY and FULL bits are cleared
automatically. For packet sizes less than the maximum, RXRDY must be cleared manually.
Double-Packet Buffering
If the size of the receive endpoint FIFO is at least twice the maximum packet size for the endpoint,
two data packets can be buffered and double-packet buffering can be used. When the first packet
is received and loaded into the receive FIFO, the RXRDY bit in the USBRXCSRLn register is set
and the appropriate receive endpoint interrupt is signaled to indicate that a packet can now be
unloaded from the FIFO.
Note:
The FULL bit in USBRXCSRLn is not set when the first packet is received. It is only set if
a second packet is received and loaded into the receive FIFO.
After each packet has been unloaded, the RXRDY bit must be cleared to allow further packets to be
received. If the AUTOCL bit in the USBRXCSRHn register is set and a maximum-sized packet is
unloaded from the FIFO, the RXRDY bit is cleared automatically. For packet sizes less than the
maximum, RXRDY must be cleared manually. If the FULL bit is set when RXRDY is cleared, the USB
controller first clears the FULL bit, then sets RXRDY again to indicate that there is another packet
waiting in the FIFO to be unloaded.
Note:
18.3.1.4
Double-packet buffering is disabled if an endpoint's corresponding EPn bit is set in the USB
Receive Double Packet Buffer Disable (USBRXDPKTBUFDIS) register. This bit is set
by default, so it must be cleared to enable double-packet buffering.
Scheduling
The Device has no control over the scheduling of transactions as scheduling is determined by the
Host controller. The TM4C1237H6PZ USB controller can set up a transaction at any time. The USB
controller waits for the request from the Host controller and generates an interrupt when the
transaction is complete or if it was terminated due to some error. If the Host controller makes a
request and the Device controller is not ready, the USB controller sends a busy response (NAK) to
all requests until it is ready.
18.3.1.5
Additional Actions
The USB controller responds automatically to certain conditions on the USB bus or actions by the
Host controller such as when the USB controller automatically stalls a control transfer or unexpected
zero length OUT data packets.
Stalled Control Transfer
The USB controller automatically issues a STALL handshake to a control transfer under the following
conditions:
1. The Host sends more data during an OUT data phase of a control transfer than was specified
in the Device request during the SETUP phase. This condition is detected by the USB controller
when the Host sends an OUT token (instead of an IN token) after the last OUT packet has been
unloaded and the DATAEND bit in the USB Control and Status Endpoint 0 Low (USBCSRL0)
register has been set.
2. The Host requests more data during an IN data phase of a control transfer than was specified
in the Device request during the SETUP phase. This condition is detected by the USB controller
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when the Host sends an IN token (instead of an OUT token) after the CPU has cleared TXRDY
and set DATAEND in response to the ACK issued by the Host to what should have been the last
packet.
3. The Host sends more than USBRXMAXPn bytes of data with an OUT data token.
4. The Host sends more than a zero length data packet for the OUT STATUS phase.
Zero Length OUT Data Packets
A zero-length OUT data packet is used to indicate the end of a control transfer. In normal operation,
such packets should only be received after the entire length of the Device request has been
transferred.
However, if the Host sends a zero-length OUT data packet before the entire length of Device request
has been transferred, it is signaling the premature end of the transfer. In this case, the USB controller
automatically flushes any IN token ready for the data phase from the FIFO and sets the DATAEND
bit in the USBCSRL0 register.
Setting the Device Address
When a Host is attempting to enumerate the USB Device, it requests that the Device change its
address from zero to some other value. The address is changed by writing the value that the Host
requested to the USB Device Functional Address (USBFADDR) register. However, care should
be taken when writing to USBFADDR to avoid changing the address before the transaction is
complete. This register should only be set after the SET_ADDRESS command is complete. Like all
control transactions, the transaction is only complete after the Device has left the STATUS phase.
In the case of a SET_ADDRESS command, the transaction is completed by responding to the IN
request from the Host with a zero-byte packet. Once the Device has responded to the IN request,
the USBFADDR register should be programmed to the new value as soon as possible to avoid
missing any new commands sent to the new address.
Note:
18.3.1.6
If the USBFADDR register is set to the new value as soon as the Device receives the OUT
transaction with the SET_ADDRESS command in the packet, it changes the address during
the control transfer. In this case, the Device does not receive the IN request that allows the
USB transaction to exit the STATUS phase of the control transfer because it is sent to the
old address. As a result, the Host does not get a response to the IN request, and the Host
fails to enumerate the Device.
Device Mode SUSPEND
When no activity has occurred on the USB bus for 3 ms, the USB controller automatically enters
SUSPEND mode. If the SUSPEND interrupt has been enabled in the USB Interrupt Enable (USBIE)
register, an interrupt is generated at this time. When in SUSPEND mode, the PHY also goes into
SUSPEND mode. When RESUME signaling is detected, the USB controller exits SUSPEND mode
and takes the PHY out of SUSPEND. If the RESUME interrupt is enabled, an interrupt is generated.
The USB controller can also be forced to exit SUSPEND mode by setting the RESUME bit in the USB
Power (USBPOWER) register. When this bit is set, the USB controller exits SUSPEND mode and
drives RESUME signaling onto the bus. The RESUME bit must be cleared after 10 ms (a maximum
of 15 ms) to end RESUME signaling.
To meet USB power requirements, the controller can be put into Deep Sleep mode which keeps
the controller in a static state. Hibernation mode should not be used for SUSPEND mode because
all internal state information is lost in hibernation.
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Important: When configured as a self-powered Device, the USB module meets the response timing
and power draw requirements for USB compliance of SUSPEND mode. When configured
as a bus-powered Device, the USB can operate in SUSPEND mode but produces a
higher power draw than required to be compliant.
18.3.1.7
Start-of-Frame
When the USB controller is operating in Device mode, it receives a Start-Of-Frame (SOF) packet
from the Host once every millisecond. When the SOF packet is received, the 11-bit frame number
contained in the packet is written into the USB Frame Value (USBFRAME) register, and an SOF
interrupt is also signaled and can be handled by the application. Once the USB controller has started
to receive SOF packets, it expects one every millisecond. If no SOF packet is received after 1.00358
ms, the packet is assumed to have been lost, and the USBFRAME register is not updated. The
USB controller continues and resynchronizes these pulses to the received SOF packets when these
packets are successfully received again.
18.3.1.8
USB RESET
When the USB controller is in Device mode and a RESET condition is detected on the USB bus,
the USB controller automatically performs the following actions:
■ Clears the USBFADDR register.
■ Clears the USB Endpoint Index (USBEPIDX) register.
■ Flushes all endpoint FIFOs.
■ Clears all control/status registers.
■ Enables all endpoint interrupts.
■ Generates a RESET interrupt.
When the application software driving the USB controller receives a RESET interrupt, any open
pipes are closed and the USB controller waits for bus enumeration to begin.
18.3.1.9
Connect/Disconnect
The USB controller connection to the USB bus is handled by software. The USB PHY can be
switched between normal mode and non-driving mode by setting or clearing the SOFTCONN bit of
the USBPOWER register. When the SOFTCONN bit is set, the PHY is placed in its normal mode,
and the USB0DP/USB0DM lines of the USB bus are enabled. At the same time, the USB controller
is placed into a state, in which it does not respond to any USB signaling except a USB RESET.
When the SOFTCONN bit is cleared, the PHY is put into non-driving mode, USB0DP and USB0DM are
tristated, and the USB controller appears to other devices on the USB bus as if it has been
disconnected. The non-driving mode is the default so the USB controller appears disconnected until
the SOFTCONN bit has been set. The application software can then choose when to set the PHY
into its normal mode. Systems with a lengthy initialization procedure may use this to ensure that
initialization is complete, and the system is ready to perform enumeration before connecting to the
USB bus. Once the SOFTCONN bit has been set, the USB controller can be disconnected by clearing
this bit.
Note:
The USB controller does not generate an interrupt when the Device is connected to the
Host. However, an interrupt is generated when the Host terminates a session.
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18.3.2
Operation as a Host
When the TM4C1237H6PZ USB controller is operating in Host mode, it can either be used for
point-to-point communications with another USB device or, when attached to a hub, for
communication with multiple devices. Before the USB controller's operating mode is changed from
Host to Device or Device to Host, software must reset the USB controller by setting the USB0 bit in
the Software Reset Control 2 (SRCR2) register (see page 440). Full-speed and low-speed USB
devices are supported, both for point-to-point communication and for operation through a hub. The
USB controller automatically carries out the necessary transaction translation needed to allow a
low-speed or full-speed device to be used with a USB 2.0 hub. Control, bulk, isochronous, and
interrupt transactions are supported. This section describes the USB controller's actions when it is
being used as a USB Host. Configuration of IN endpoints, OUT endpoints, entry into and exit from
SUSPEND mode, and RESET are all described.
When in Host mode, IN transactions are controlled by an endpoint's receive interface. All IN
transactions use the receive endpoint registers and all OUT endpoints use the transmit endpoint
registers for a given endpoint. As in Device mode, the FIFOs for endpoints should take into account
the maximum packet size for an endpoint.
■ Bulk. Bulk endpoints should be the size of the maximum packet (up to 64 bytes) or twice the
maximum packet size if double buffering is used (described further in the following section).
■ Interrupt. Interrupt endpoints should be the size of the maximum packet (up to 64 bytes) or twice
the maximum packet size if double buffering is used.
■ Isochronous. Isochronous endpoints are more flexible and can be up to 1023 bytes.
■ Control. It is also possible to specify a separate control endpoint to communicate with a Device.
However, in most cases the USB controller should use the dedicated control endpoint to
communicate with a Device's endpoint 0.
18.3.2.1
Endpoints
The endpoint registers are used to control the USB endpoint interfaces which communicate with
Device(s) that are connected. The endpoints consist of a dedicated control IN endpoint, a dedicated
control OUT endpoint, 7 configurable OUT endpoints, and 7 configurable IN endpoints.
The dedicated control interface can only be used for control transactions to endpoint 0 of Devices.
These control transactions are used during enumeration or other control functions that communicate
using endpoint 0 of Devices. This control endpoint shares the first 64 bytes of the USB controller's
FIFO RAM for IN and OUT transactions. The remaining IN and OUT interfaces can be configured
to communicate with control, bulk, interrupt, or isochronous Device endpoints.
These USB interfaces can be used to simultaneously schedule as many as 7 independent OUT
and 7 independent IN transactions to any endpoints on any Device. The IN and OUT controls are
paired in three sets of registers. However, they can be configured to communicate with different
types of endpoints and different endpoints on Devices. For example, the first pair of endpoint controls
can be split so that the OUT portion is communicating with a Device's bulk OUT endpoint 1, while
the IN portion is communicating with a Device's interrupt IN endpoint 2.
Before accessing any Device, whether for point-to-point communications or for communications via
a hub, the relevant USB Receive Functional Address Endpoint n (USBRXFUNCADDRn) or USB
Transmit Functional Address Endpoint n (USBTXFUNCADDRn) registers must be set for each
receive or transmit endpoint to record the address of the Device being accessed.
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The USB controller also supports connections to Devices through a USB hub by providing a register
that specifies the hub address and port of each USB transfer. The FIFO address and size are
customizable and can be specified for each USB IN and OUT transfer. Customization includes
allowing one FIFO per transaction, sharing a FIFO across transactions, and allowing for
double-buffered FIFOs.
18.3.2.2
IN Transactions as a Host
IN transactions are handled in a similar manner to the way in which OUT transactions are handled
when the USB controller is in Device mode except that the transaction first must be initiated by
setting the REQPKT bit in the USBCSRL0 register, indicating to the transaction scheduler that there
is an active transaction on this endpoint. The transaction scheduler then sends an IN token to the
target Device. When the packet is received and placed in the receive FIFO, the RXRDY bit in the
USBCSRL0 register is set, and the appropriate receive endpoint interrupt is signaled to indicate
that a packet can now be unloaded from the FIFO.
When the packet has been unloaded, RXRDY must be cleared. The AUTOCL bit in the USBRXCSRHn
register can be used to have RXRDY automatically cleared when a maximum-sized packet has been
unloaded from the FIFO. The AUTORQ bit in USBRXCSRHn causes the REQPKT bit to be automatically
set when the RXRDY bit is cleared. The AUTOCL and AUTORQ bits can be used with µDMA accesses
to perform complete bulk transfers without main processor intervention. When the RXRDY bit is
cleared, the controller sends an acknowledge to the Device. When there is a known number of
packets to be transferred, the USB Request Packet Count in Block Transfer Endpoint n
(USBRQPKTCOUNTn) register associated with the endpoint should be configured to the number
of packets to be transferred. The USB controller decrements the value in the USBRQPKTCOUNTn
register following each request. When the USBRQPKTCOUNTn value decrements to 0, the AUTORQ
bit is cleared to prevent any further transactions being attempted. For cases where the size of the
transfer is unknown, USBRQPKTCOUNTn should be cleared. AUTORQ then remains set until cleared
by the reception of a short packet (that is, less than the MAXLOAD value in the USBRXMAXPn
register) such as may occur at the end of a bulk transfer.
If the Device responds to a bulk or interrupt IN token with a NAK, the USB Host controller keeps
retrying the transaction until any NAK Limit that has been set has been reached. If the target Device
responds with a STALL, however, the USB Host controller does not retry the transaction but sets
the STALLED bit in the USBCSRL0 register. If the target Device does not respond to the IN token
within the required time, or the packet contained a CRC or bit-stuff error, the USB Host controller
retries the transaction. If after three attempts the target Device has still not responded, the USB
Host controller clears the REQPKT bit and sets the ERROR bit in the USBCSRL0 register.
18.3.2.3
OUT Transactions as a Host
OUT transactions are handled in a similar manner to the way in which IN transactions are handled
when the USB controller is in Device mode. The TXRDY bit in the USBTXCSRLn register must be
set as each packet is loaded into the transmit FIFO. Again, setting the AUTOSET bit in the
USBTXCSRHn register automatically sets TXRDY when a maximum-sized packet has been loaded
into the FIFO. Furthermore, AUTOSET can be used with the µDMA controller to perform complete
bulk transfers without software intervention.
If the target Device responds to the OUT token with a NAK, the USB Host controller keeps retrying
the transaction until the NAK Limit that has been set has been reached. However, if the target Device
responds with a STALL, the USB controller does not retry the transaction but interrupts the main
processor by setting the STALLED bit in the USBTXCSRLn register. If the target Device does not
respond to the OUT token within the required time, or the packet contained a CRC or bit-stuff error,
the USB Host controller retries the transaction. If after three attempts the target Device has still not
responded, the USB controller flushes the FIFO and sets the ERROR bit in the USBTXCSRLn register.
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18.3.2.4
Transaction Scheduling
Scheduling of transactions is handled automatically by the USB Host controller. The Host controller
allows configuration of the endpoint communication scheduling based on the type of endpoint
transaction. Interrupt transactions can be scheduled to occur in the range of every frame to every
255 frames in 1 frame increments. Bulk endpoints do not allow scheduling parameters, but do allow
for a NAK timeout in the event an endpoint on a Device is not responding. Isochronous endpoints
can be scheduled from every frame to every 216 frames, in powers of 2.
The USB controller maintains a frame counter. If the target Device is a full-speed device, the USB
controller automatically sends an SOF packet at the start of each frame and increments the frame
counter. If the target Device is a low-speed device, a K state is transmitted on the bus to act as a
keep-alive to stop the low-speed device from going into SUSPEND mode.
After the SOF packet has been transmitted, the USB Host controller cycles through all the configured
endpoints looking for active transactions. An active transaction is defined as a receive endpoint for
which the REQPKT bit is set or a transmit endpoint for which the TXRDY bit and/or the FIFONE bit is
set.
An isochronous or interrupt transaction is started if the transaction is found on the first scheduler
cycle of a frame and if the interval counter for that endpoint has counted down to zero. As a result,
only one interrupt or isochronous transaction occurs per endpoint every n frames, where n is the
interval set via the USB Host Transmit Interval Endpoint n (USBTXINTERVALn) or USB Host
Receive Interval Endpoint n (USBRXINTERVALn) register for that endpoint.
An active bulk transaction starts immediately, provided sufficient time is left in the frame to complete
the transaction before the next SOF packet is due. If the transaction must be retried (for example,
because a NAK was received or the target Device did not respond), then the transaction is not
retried until the transaction scheduler has first checked all the other endpoints for active transactions.
This process ensures that an endpoint that is sending a lot of NAKs does not block other transactions
on the bus. The controller also allows the user to specify a limit to the length of time for NAKs to be
received from a target Device before the endpoint times out.
18.3.2.5
USB Hubs
The following setup requirements apply to the USB Host controller only if it is used with a USB hub.
When a full- or low-speed Device is connected to the USB controller via a USB 2.0 hub, details of
the hub address and the hub port also must be recorded in the corresponding USB Receive Hub
Address Endpoint n (USBRXHUBADDRn) and USB Receive Hub Port Endpoint n
(USBRXHUBPORTn) or the USB Transmit Hub Address Endpoint n (USBTXHUBADDRn) and
USB Transmit Hub Port Endpoint n (USBTXHUBPORTn) registers. In addition, the speed at
which the Device operates (full or low) must be recorded in the USB Type Endpoint 0 (USBTYPE0)
(endpoint 0), USB Host Configure Transmit Type Endpoint n (USBTXTYPEn), or USB Host
Configure Receive Type Endpoint n (USBRXTYPEn) registers for each endpoint that is accessed
by the Device.
For hub communications, the settings in these registers record the current allocation of the endpoints
to the attached USB Devices. To maximize the number of Devices supported, the USB Host controller
allows this allocation to be changed dynamically by simply updating the address and speed
information recorded in these registers. Any changes in the allocation of endpoints to Device functions
must be made following the completion of any on-going transactions on the endpoints affected.
18.3.2.6
Babble
The USB Host controller does not start a transaction until the bus has been inactive for at least the
minimum inter-packet delay. The controller also does not start a transaction unless it can be finished
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before the end of the frame. If the bus is still active at the end of a frame, then the USB Host controller
assumes that the target Device to which it is connected has malfunctioned, and the USB controller
suspends all transactions and generates a babble interrupt.
18.3.2.7
Host SUSPEND
If the SUSPEND bit in the USBPOWER register is set, the USB Host controller completes the current
transaction then stops the transaction scheduler and frame counter. No further transactions are
started and no SOF packets are generated.
To exit SUSPEND mode, set the RESUME bit and clear the SUSPEND bit. While the RESUME bit is
set, the USB Host controller generates RESUME signaling on the bus. After 20 ms, the RESUME bit
must be cleared, at which point the frame counter and transaction scheduler start. The Host supports
the detection of a remote wake-up.
18.3.2.8
USB RESET
If the RESET bit in the USBPOWER register is set, the USB Host controller generates USB RESET
signaling on the bus. The RESET bit must be set for at least 20 ms to ensure correct resetting of the
target Device. After the CPU has cleared the bit, the USB Host controller starts its frame counter
and transaction scheduler.
18.3.2.9
Connect/Disconnect
A session is started by setting the SESSION bit in the USB Device Control (USBDEVCTL) register,
enabling the USB controller to wait for a Device to be connected. When a Device is detected, a
connect interrupt is generated. The speed of the Device that has been connected can be determined
by reading the USBDEVCTL register where the FSDEV bit is set for a full-speed Device, and the
LSDEV bit is set for a low-speed Device. The USB controller must generate a RESET to the Device,
and then the USB Host controller can begin Device enumeration. If the Device is disconnected while
a session is in progress, a disconnect interrupt is generated.
18.3.3
OTG Mode
To conserve power, the USB On-The-Go (OTG) supplement allows VBUS to only be powered up
when required and to be turned off when the bus is not in use. VBUS is always supplied by the A
device on the bus. The USB OTG controller determines whether it is the A device or the B device
by sampling the ID input from the PHY. This signal is pulled Low when an A-type plug is sensed
(signifying that the USB OTG controller should act as the A device) but taken High when a B-type
plug is sensed (signifying that the USB controller is a B device). Note that when switching between
OTG A and OTG B, the USB controller retains all register contents.
18.3.3.1
Starting a Session
When the USB OTG controller is ready to start a session, the SESSION bit must be set in the
USBDEVCTL register. The USB OTG controller then enables ID pin sensing. The ID input is either
taken Low if an A-type connection is detected or High if a B-type connection is detected. The DEV
bit in the USBDEVCTL register is also set to indicate whether the USB OTG controller has adopted
the role of the A device or the B device. The USB OTG controller also provides an interrupt to
indicate that ID pin sensing has completed and the mode value in the USBDEVCTL register is valid.
This interrupt is enabled in the USBIDVIM register, and the status is checked in the USBIDVISC
register. As soon as the USB controller has detected that it is on the A side of the cable, it must
enable VBUS power within 100ms or the USB controller reverts to Device mode.
If the USB OTG controller is the A device, then the USB OTG controller enters Host mode (the A
device is always the default Host), turns on VBUS, and waits for VBUS to go above the VBUS Valid
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threshold, as indicated by the VBUS bit in the USBDEVCTL register going to 0x3. The USB OTG
controller then waits for a peripheral to be connected. When a peripheral is detected, a Connect
interrupt is signaled and either the FSDEV or LSDEV bit in the USBDEVCTL register is set, depending
whether a full-speed or a low-speed peripheral is detected. The USB controller then issues a RESET
to the connected Device. The SESSION bit in the USBDEVCTL register can be cleared to end a
session. The USB OTG controller also automatically ends the session if babble is detected or if
VBUS drops below session valid.
Note:
The USB OTG controller may not remain in Host mode when connected to high-current
devices. Some devices draw enough current to momentarily drop VBUS below the
VBUS-valid level causing the controller to drop out of Host mode. The only way to get back
into Host mode is to allow VBUS to go below the Session End level. In this situation, the
device is causing VBUS to drop repeatedly and pull VBUS back low the next time VBUS is
enabled.
In addition, the USB OTG controller may not remain in Host mode when a device is told
that it can start using it's active configuration. At this point the device starts drawing more
current and can also drop VBUS below VBUS valid.
If the USB OTG controller is the B device, then the USB OTG controller requests a session using
the session request protocol defined in the USB On-The-Go supplement, that is, it first discharges
VBUS. Then when VBUS has gone below the Session End threshold (VBUS bit in the USBDEVCTL
register goes to 0x0) and the line state has been a single-ended zero for > 2 ms, the USB OTG
controller pulses the data line, then pulses VBUS. At the end of the session, the SESSION bit is
cleared either by the USB OTG controller or by the application software. The USB OTG controller
then causes the PHY to switch out the pull-up resistor on D+, signaling the A device to end the
session.
18.3.3.2
Detecting Activity
When the other device of the OTG setup wishes to start a session, it either raises VBUS above the
Session Valid threshold if it is the A device, or if it is the B device, it pulses the data line then pulses
VBUS. Depending on which of these actions happens, the USB controller can determine whether
it is the A device or the B device in the current setup and act accordingly. If VBUS is raised above
the Session Valid threshold, then the USB controller is the B device. The USB controller sets the
SESSION bit in the USBDEVCTL register. When RESET signaling is detected on the bus, a RESET
interrupt is signaled, which is interpreted as the start of a session.
The USB controller is in Device mode as the B device is the default mode. At the end of the session,
the A device turns off the power to VBUS. When VBUS drops below the Session Valid threshold,
the USB controller detects this drop and clears the SESSION bit to indicate that the session has
ended, causing a disconnect interrupt to be signaled. If data line and VBUS pulsing is detected,
then the USB controller is the A device. The controller generates a SESSION REQUEST interrupt
to indicate that the B device is requesting a session. The SESSION bit in the USBDEVCTL register
must be set to start a session.
18.3.3.3
Host Negotiation
When the USB controller is the A device, ID is Low, and the controller automatically enters Host
mode when a session starts. When the USB controller is the B device, ID is High, and the controller
automatically enters Device mode when a session starts. However, software can request that the
USB controller become the Host by setting the HOSTREQ bit in the USBDEVCTL register. This bit
can be set either at the same time as requesting a Session Start by setting the SESSION bit in the
USBDEVCTL register or at any time after a session has started. When the USB controller next
enters SUSPEND mode and if the HOSTREQ bit remains set, the controller enters Host mode and
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begins host negotiation (as specified in the USB On-The-Go supplement) by causing the PHY to
disconnect the pull-up resistor on the D+ line, causing the A device to switch to Device mode and
connect its own pull-up resistor. When the USB controller detects this, a Connect interrupt is
generated and the RESET bit in the USBPOWER register is set to begin resetting the A device. The
USB controller begins this reset sequence automatically to ensure that RESET is started as required
within 1 ms of the A device connecting its pull-up resistor. The main processor should wait at least
20 ms, then clear the RESET bit and enumerate the A device.
When the USB OTG controller B device has finished using the bus, the USB controller goes into
SUSPEND mode by setting the SUSPEND bit in the USBPOWER register. The A device detects this
and either terminates the session or reverts to Host mode. If the A device is USB OTG controller,
it generates a Disconnect interrupt.
18.3.4
DMA Operation
The USB peripheral provides an interface connected to the μDMA controller with separate channels
for 3 transmit endpoints and 3 receive endpoints. Software selects which endpoints to service with
the μDMA channels using the USB DMA Select (USBDMASEL) register. The μDMA operation of
the USB is enabled through the USBTXCSRHn and USBRXCSRHn registers, for the TX and RX
channels respectively. When μDMA operation is enabled, the USB asserts a μDMA request on the
enabled receive or transmit channel when the associated FIFO can transfer data. When either FIFO
can transfer data, the burst request for that channel is asserted. The μDMA channel must be
configured to operate in Basic mode, and the size of the μDMA transfer must be restricted to whole
multiples of the size of the USB FIFO. Both read and write transfers of the USB FIFOs using μDMA
must be configured in this manner. For example, if the USB endpoint is configured with a FIFO size
of 64 bytes, the μDMA channel can be used to transfer 64 bytes to or from the endpoint FIFO. If the
number of bytes to transfer is less than 64, then a programmed I/O method must be used to copy
the data to or from the FIFO.
If the DMAMOD bit in the USBTXCSRHn/USBRXCSRHn register is clear, an interrupt is generated
after every packet is transferred, but the μDMA continues transferring data. If the DMAMOD bit is set,
an interrupt is generated only when the entire μDMA transfer is complete. The interrupt occurs on
the USB interrupt vector. Therefore, if interrupts are used for USB operation and the μDMA is
enabled, the USB interrupt handler must be designed to handle the μDMA completion interrupt.
Care must be taken when using the μDMA to unload the receive FIFO as data is read from the
receive FIFO in 4 byte chunks regardless of value of the MAXLOAD field in the USBRXCSRHn
register. The RXRDY bit is cleared as follows.
Table 18-2. Remainder (MAXLOAD/4)
Value
Description
0
MAXLOAD = 64 bytes
1
MAXLOAD = 61 bytes
2
MAXLOAD = 62 bytes
3
MAXLOAD = 63 bytes
Table 18-3. Actual Bytes Read
Value
Description
0
MAXLOAD
1
MAXLOAD+3
2
MAXLOAD+2
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Table 18-3. Actual Bytes Read (continued)
Value
Description
3
MAXLOAD+1
Table 18-4. Packet Sizes That Clear RXRDY
Value
Description
0
MAXLOAD, MAXLOAD-1, MAXLOAD-2, MAXLOAD-3
1
MAXLOAD
2
MAXLOAD, MAXLOAD-1
3
MAXLOAD, MAXLOAD-1, MAXLOAD-2
To enable DMA operation for the endpoint receive channel, the DMAEN bit of the USBRXCSRHn
register should be set. To enable DMA operation for the endpoint transmit channel, the DMAEN bit
of the USBTXCSRHn register must be set.
See “Micro Direct Memory Access (μDMA)” on page 570 for more details about programming the
μDMA controller.
18.4
Initialization and Configuration
To use the USB Controller, the peripheral clock must be enabled via the RCGCUSB register (see
page 342). In addition, the clock to the appropriate GPIO module must be enabled via the RCGCGPIO
register in the System Control module (see page 331). To find out which GPIO port to enable, refer
to Table 21-4 on page 1242. Configure the PMCn fields in the GPIOPCTL register to assign the USB
signals to the appropriate pins (see page 677 and Table 21-5 on page 1249).
The initial configuration in all cases requires that the processor enable the USB controller and USB
controller's physical layer interface (PHY) before setting any registers. The next step is to enable
the USB PLL so that the correct clocking is provided to the PHY. To ensure that voltage is not
supplied to the bus incorrectly, the external power control signal, USB0EPEN, should be negated on
start up by configuring the USB0EPEN and USB0PFLT pins to be controlled by the USB controller
and not exhibit their default GPIO behavior.
Note:
When used in OTG mode, USB0VBUS and USB0ID do not require any configuration as they
are dedicated pins for the USB controller and directly connect to the USB connector's VBUS
and ID signals. If the USB controller is used as either a dedicated Host or Device, the
DEVMODOTG and DEVMOD bits in the USB General-Purpose Control and Status
(USBGPCS) register can be used to connect the USB0VBUS and USB0ID inputs to fixed
levels internally, freeing the PB0 and PB1 pins for GPIO use. For proper self-powered Device
operation, the VBUS value must still be monitored to assure that if the Host removes VBUS,
the self-powered Device disables the D+/D- pull-up resistors. This function can be
accomplished by connecting a standard GPIO to VBUS.
The termination resistors for the USB PHY have been added internally, and thus there is
no need for external resistors. For a device, there is a 1.5 KOhm pull-up on the D+ and for
a host there are 15 KOhm pull-downs on both D+ and D-.
18.4.1
Pin Configuration
When using the Device controller portion of the USB controller in a system that also provides Host
functionality, the power to VBUS must be disabled to allow the external Host controller to supply
power. Usually, the USB0EPEN signal is used to control the external regulator and should be negated
to avoid having two devices driving the USB0VBUS power pin on the USB connector.
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Universal Serial Bus (USB) Controller
When the USB controller is acting as a Host, it is in control of two signals that are attached to an
external voltage supply that provides power to VBUS. The Host controller uses the USB0EPEN signal
to enable or disable power to the USB0VBUS pin on the USB connector. An input pin, USB0PFLT,
provides feedback when there has been a power fault on VBUS. The USB0PFLT signal can be
configured to either automatically negate the USB0EPEN signal to disable power, and/or it can
generate an interrupt to the interrupt controller to allow software to handle the power fault condition.
The polarity and actions related to both USB0EPEN and USB0PFLT are fully configurable in the USB
controller. The controller also provides interrupts on Device insertion and removal to allow the Host
controller code to respond to these external events.
18.4.2
Endpoint Configuration
To start communication in Host or Device mode, the endpoint registers must first be configured. In
Host mode, this configuration establishes a connection between an endpoint register and an endpoint
on a Device. In Device mode, an endpoint must be configured before enumerating to the Host
controller.
In both cases, the endpoint 0 configuration is limited because it is a fixed-function, fixed-FIFO-size
endpoint. In Device and Host modes, the endpoint requires little setup but does require a
software-based state machine to progress through the setup, data, and status phases of a standard
control transaction. In Device mode, the configuration of the remaining endpoints is done once
before enumerating and then only changed if an alternate configuration is selected by the Host
controller. In Host mode, the endpoints must be configured to operate as control, bulk, interrupt or
isochronous mode. Once the type of endpoint is configured, a FIFO area must be assigned to each
endpoint. In the case of bulk, control and interrupt endpoints, each has a maximum of 64 bytes per
transaction. Isochronous endpoints can have packets with up to 1023 bytes per packet. In either
mode, the maximum packet size for the given endpoint must be set prior to sending or receiving
data.
Configuring each endpoint's FIFO involves reserving a portion of the overall USB FIFO RAM to
each endpoint. The total FIFO RAM available is 2 Kbytes with the first 64 bytes reserved for endpoint
0. The endpoint's FIFO must be at least as large as the maximum packet size. The FIFO can also
be configured as a double-buffered FIFO so that interrupts occur at the end of each packet and
allow filling the other half of the FIFO.
If operating as a Device, the USB Device controller's soft connect must be enabled when the Device
is ready to start communications, indicating to the Host controller that the Device is ready to start
the enumeration process. If operating as a Host controller, the Device soft connect must be disabled
and power must be provided to VBUS via the USB0EPEN signal.
18.5
Register Map
Table 18-5 on page 1106 lists the registers. All addresses given are relative to the USB base address
of 0x4005.0000. Note that the USB controller clock must be enabled before the registers can be
programmed (see page 342). There must be a delay of 3 system clocks after the USB module clock
is enabled before any USB module registers are accessed.
Table 18-5. Universal Serial Bus (USB) Controller Register Map
Type
Reset
Description
See
page
USBFADDR
RW
0x00
USB Device Functional Address
1114
USBPOWER
RW
0x20
USB Power
1115
Offset
Name
0x000
0x001
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Table 18-5. Universal Serial Bus (USB) Controller Register Map (continued)
Type
Reset
Description
See
page
USBTXIS
RO
0x0000
USB Transmit Interrupt Status
1118
0x004
USBRXIS
RO
0x0000
USB Receive Interrupt Status
1120
0x006
USBTXIE
RW
0xFFFF
USB Transmit Interrupt Enable
1121
0x008
USBRXIE
RW
0xFFFE
USB Receive Interrupt Enable
1123
0x00A
USBIS
RO
0x00
USB General Interrupt Status
1124
0x00B
USBIE
RW
0x06
USB Interrupt Enable
1127
0x00C
USBFRAME
RO
0x0000
USB Frame Value
1130
0x00E
USBEPIDX
RW
0x00
USB Endpoint Index
1131
0x00F
USBTEST
RW
0x00
USB Test Mode
1132
0x020
USBFIFO0
RW
0x0000.0000
USB FIFO Endpoint 0
1134
0x024
USBFIFO1
RW
0x0000.0000
USB FIFO Endpoint 1
1134
0x028
USBFIFO2
RW
0x0000.0000
USB FIFO Endpoint 2
1134
0x02C
USBFIFO3
RW
0x0000.0000
USB FIFO Endpoint 3
1134
0x030
USBFIFO4
RW
0x0000.0000
USB FIFO Endpoint 4
1134
0x034
USBFIFO5
RW
0x0000.0000
USB FIFO Endpoint 5
1134
0x038
USBFIFO6
RW
0x0000.0000
USB FIFO Endpoint 6
1134
0x03C
USBFIFO7
RW
0x0000.0000
USB FIFO Endpoint 7
1134
0x060
USBDEVCTL
RW
0x80
USB Device Control
1135
0x062
USBTXFIFOSZ
RW
0x00
USB Transmit Dynamic FIFO Sizing
1137
0x063
USBRXFIFOSZ
RW
0x00
USB Receive Dynamic FIFO Sizing
1137
0x064
USBTXFIFOADD
RW
0x0000
USB Transmit FIFO Start Address
1138
0x066
USBRXFIFOADD
RW
0x0000
USB Receive FIFO Start Address
1138
0x07A
USBCONTIM
RW
0x5C
USB Connect Timing
1139
0x07B
USBVPLEN
RW
0x3C
USB OTG VBUS Pulse Timing
1140
0x07D
USBFSEOF
RW
0x77
USB Full-Speed Last Transaction to End of Frame Timing
1141
0x07E
USBLSEOF
RW
0x72
USB Low-Speed Last Transaction to End of Frame
Timing
1142
0x080
USBTXFUNCADDR0
RW
0x00
USB Transmit Functional Address Endpoint 0
1143
0x082
USBTXHUBADDR0
RW
0x00
USB Transmit Hub Address Endpoint 0
1144
0x083
USBTXHUBPORT0
RW
0x00
USB Transmit Hub Port Endpoint 0
1145
0x088
USBTXFUNCADDR1
RW
0x00
USB Transmit Functional Address Endpoint 1
1143
0x08A
USBTXHUBADDR1
RW
0x00
USB Transmit Hub Address Endpoint 1
1144
Offset
Name
0x002
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Universal Serial Bus (USB) Controller
Table 18-5. Universal Serial Bus (USB) Controller Register Map (continued)
Type
Reset
Description
See
page
USBTXHUBPORT1
RW
0x00
USB Transmit Hub Port Endpoint 1
1145
0x08C
USBRXFUNCADDR1
RW
0x00
USB Receive Functional Address Endpoint 1
1146
0x08E
USBRXHUBADDR1
RW
0x00
USB Receive Hub Address Endpoint 1
1147
0x08F
USBRXHUBPORT1
RW
0x00
USB Receive Hub Port Endpoint 1
1148
0x090
USBTXFUNCADDR2
RW
0x00
USB Transmit Functional Address Endpoint 2
1143
0x092
USBTXHUBADDR2
RW
0x00
USB Transmit Hub Address Endpoint 2
1144
0x093
USBTXHUBPORT2
RW
0x00
USB Transmit Hub Port Endpoint 2
1145
0x094
USBRXFUNCADDR2
RW
0x00
USB Receive Functional Address Endpoint 2
1146
0x096
USBRXHUBADDR2
RW
0x00
USB Receive Hub Address Endpoint 2
1147
0x097
USBRXHUBPORT2
RW
0x00
USB Receive Hub Port Endpoint 2
1148
0x098
USBTXFUNCADDR3
RW
0x00
USB Transmit Functional Address Endpoint 3
1143
0x09A
USBTXHUBADDR3
RW
0x00
USB Transmit Hub Address Endpoint 3
1144
0x09B
USBTXHUBPORT3
RW
0x00
USB Transmit Hub Port Endpoint 3
1145
0x09C
USBRXFUNCADDR3
RW
0x00
USB Receive Functional Address Endpoint 3
1146
0x09E
USBRXHUBADDR3
RW
0x00
USB Receive Hub Address Endpoint 3
1147
0x09F
USBRXHUBPORT3
RW
0x00
USB Receive Hub Port Endpoint 3
1148
0x0A0
USBTXFUNCADDR4
RW
0x00
USB Transmit Functional Address Endpoint 4
1143
0x0A2
USBTXHUBADDR4
RW
0x00
USB Transmit Hub Address Endpoint 4
1144
0x0A3
USBTXHUBPORT4
RW
0x00
USB Transmit Hub Port Endpoint 4
1145
0x0A4
USBRXFUNCADDR4
RW
0x00
USB Receive Functional Address Endpoint 4
1146
0x0A6
USBRXHUBADDR4
RW
0x00
USB Receive Hub Address Endpoint 4
1147
0x0A7
USBRXHUBPORT4
RW
0x00
USB Receive Hub Port Endpoint 4
1148
0x0A8
USBTXFUNCADDR5
RW
0x00
USB Transmit Functional Address Endpoint 5
1143
0x0AA
USBTXHUBADDR5
RW
0x00
USB Transmit Hub Address Endpoint 5
1144
0x0AB
USBTXHUBPORT5
RW
0x00
USB Transmit Hub Port Endpoint 5
1145
0x0AC
USBRXFUNCADDR5
RW
0x00
USB Receive Functional Address Endpoint 5
1146
0x0AE
USBRXHUBADDR5
RW
0x00
USB Receive Hub Address Endpoint 5
1147
0x0AF
USBRXHUBPORT5
RW
0x00
USB Receive Hub Port Endpoint 5
1148
0x0B0
USBTXFUNCADDR6
RW
0x00
USB Transmit Functional Address Endpoint 6
1143
0x0B2
USBTXHUBADDR6
RW
0x00
USB Transmit Hub Address Endpoint 6
1144
0x0B3
USBTXHUBPORT6
RW
0x00
USB Transmit Hub Port Endpoint 6
1145
0x0B4
USBRXFUNCADDR6
RW
0x00
USB Receive Functional Address Endpoint 6
1146
Offset
Name
0x08B
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Table 18-5. Universal Serial Bus (USB) Controller Register Map (continued)
Type
Reset
Description
See
page
USBRXHUBADDR6
RW
0x00
USB Receive Hub Address Endpoint 6
1147
0x0B7
USBRXHUBPORT6
RW
0x00
USB Receive Hub Port Endpoint 6
1148
0x0B8
USBTXFUNCADDR7
RW
0x00
USB Transmit Functional Address Endpoint 7
1143
0x0BA
USBTXHUBADDR7
RW
0x00
USB Transmit Hub Address Endpoint 7
1144
0x0BB
USBTXHUBPORT7
RW
0x00
USB Transmit Hub Port Endpoint 7
1145
0x0BC
USBRXFUNCADDR7
RW
0x00
USB Receive Functional Address Endpoint 7
1146
0x0BE
USBRXHUBADDR7
RW
0x00
USB Receive Hub Address Endpoint 7
1147
0x0BF
USBRXHUBPORT7
RW
0x00
USB Receive Hub Port Endpoint 7
1148
0x102
USBCSRL0
W1C
0x00
USB Control and Status Endpoint 0 Low
1150
0x103
USBCSRH0
W1C
0x00
USB Control and Status Endpoint 0 High
1154
0x108
USBCOUNT0
RO
0x00
USB Receive Byte Count Endpoint 0
1156
0x10A
USBTYPE0
RW
0x00
USB Type Endpoint 0
1157
0x10B
USBNAKLMT
RW
0x00
USB NAK Limit
1158
0x110
USBTXMAXP1
RW
0x0000
USB Maximum Transmit Data Endpoint 1
1149
0x112
USBTXCSRL1
RW
0x00
USB Transmit Control and Status Endpoint 1 Low
1159
0x113
USBTXCSRH1
RW
0x00
USB Transmit Control and Status Endpoint 1 High
1163
0x114
USBRXMAXP1
RW
0x0000
USB Maximum Receive Data Endpoint 1
1167
0x116
USBRXCSRL1
RW
0x00
USB Receive Control and Status Endpoint 1 Low
1168
0x117
USBRXCSRH1
RW
0x00
USB Receive Control and Status Endpoint 1 High
1173
0x118
USBRXCOUNT1
RO
0x0000
USB Receive Byte Count Endpoint 1
1177
0x11A
USBTXTYPE1
RW
0x00
USB Host Transmit Configure Type Endpoint 1
1178
0x11B
USBTXINTERVAL1
RW
0x00
USB Host Transmit Interval Endpoint 1
1180
0x11C
USBRXTYPE1
RW
0x00
USB Host Configure Receive Type Endpoint 1
1181
0x11D
USBRXINTERVAL1
RW
0x00
USB Host Receive Polling Interval Endpoint 1
1183
0x120
USBTXMAXP2
RW
0x0000
USB Maximum Transmit Data Endpoint 2
1149
0x122
USBTXCSRL2
RW
0x00
USB Transmit Control and Status Endpoint 2 Low
1159
0x123
USBTXCSRH2
RW
0x00
USB Transmit Control and Status Endpoint 2 High
1163
0x124
USBRXMAXP2
RW
0x0000
USB Maximum Receive Data Endpoint 2
1167
0x126
USBRXCSRL2
RW
0x00
USB Receive Control and Status Endpoint 2 Low
1168
0x127
USBRXCSRH2
RW
0x00
USB Receive Control and Status Endpoint 2 High
1173
0x128
USBRXCOUNT2
RO
0x0000
USB Receive Byte Count Endpoint 2
1177
0x12A
USBTXTYPE2
RW
0x00
USB Host Transmit Configure Type Endpoint 2
1178
Offset
Name
0x0B6
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Table 18-5. Universal Serial Bus (USB) Controller Register Map (continued)
Type
Reset
Description
See
page
USBTXINTERVAL2
RW
0x00
USB Host Transmit Interval Endpoint 2
1180
0x12C
USBRXTYPE2
RW
0x00
USB Host Configure Receive Type Endpoint 2
1181
0x12D
USBRXINTERVAL2
RW
0x00
USB Host Receive Polling Interval Endpoint 2
1183
0x130
USBTXMAXP3
RW
0x0000
USB Maximum Transmit Data Endpoint 3
1149
0x132
USBTXCSRL3
RW
0x00
USB Transmit Control and Status Endpoint 3 Low
1159
0x133
USBTXCSRH3
RW
0x00
USB Transmit Control and Status Endpoint 3 High
1163
0x134
USBRXMAXP3
RW
0x0000
USB Maximum Receive Data Endpoint 3
1167
0x136
USBRXCSRL3
RW
0x00
USB Receive Control and Status Endpoint 3 Low
1168
0x137
USBRXCSRH3
RW
0x00
USB Receive Control and Status Endpoint 3 High
1173
0x138
USBRXCOUNT3
RO
0x0000
USB Receive Byte Count Endpoint 3
1177
0x13A
USBTXTYPE3
RW
0x00
USB Host Transmit Configure Type Endpoint 3
1178
0x13B
USBTXINTERVAL3
RW
0x00
USB Host Transmit Interval Endpoint 3
1180
0x13C
USBRXTYPE3
RW
0x00
USB Host Configure Receive Type Endpoint 3
1181
0x13D
USBRXINTERVAL3
RW
0x00
USB Host Receive Polling Interval Endpoint 3
1183
0x140
USBTXMAXP4
RW
0x0000
USB Maximum Transmit Data Endpoint 4
1149
0x142
USBTXCSRL4
RW
0x00
USB Transmit Control and Status Endpoint 4 Low
1159
0x143
USBTXCSRH4
RW
0x00
USB Transmit Control and Status Endpoint 4 High
1163
0x144
USBRXMAXP4
RW
0x0000
USB Maximum Receive Data Endpoint 4
1167
0x146
USBRXCSRL4
RW
0x00
USB Receive Control and Status Endpoint 4 Low
1168
0x147
USBRXCSRH4
RW
0x00
USB Receive Control and Status Endpoint 4 High
1173
0x148
USBRXCOUNT4
RO
0x0000
USB Receive Byte Count Endpoint 4
1177
0x14A
USBTXTYPE4
RW
0x00
USB Host Transmit Configure Type Endpoint 4
1178
0x14B
USBTXINTERVAL4
RW
0x00
USB Host Transmit Interval Endpoint 4
1180
0x14C
USBRXTYPE4
RW
0x00
USB Host Configure Receive Type Endpoint 4
1181
0x14D
USBRXINTERVAL4
RW
0x00
USB Host Receive Polling Interval Endpoint 4
1183
0x150
USBTXMAXP5
RW
0x0000
USB Maximum Transmit Data Endpoint 5
1149
0x152
USBTXCSRL5
RW
0x00
USB Transmit Control and Status Endpoint 5 Low
1159
0x153
USBTXCSRH5
RW
0x00
USB Transmit Control and Status Endpoint 5 High
1163
0x154
USBRXMAXP5
RW
0x0000
USB Maximum Receive Data Endpoint 5
1167
0x156
USBRXCSRL5
RW
0x00
USB Receive Control and Status Endpoint 5 Low
1168
0x157
USBRXCSRH5
RW
0x00
USB Receive Control and Status Endpoint 5 High
1173
0x158
USBRXCOUNT5
RO
0x0000
USB Receive Byte Count Endpoint 5
1177
Offset
Name
0x12B
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Tiva™ TM4C1237H6PZ Microcontroller
Table 18-5. Universal Serial Bus (USB) Controller Register Map (continued)
Type
Reset
Description
See
page
USBTXTYPE5
RW
0x00
USB Host Transmit Configure Type Endpoint 5
1178
0x15B
USBTXINTERVAL5
RW
0x00
USB Host Transmit Interval Endpoint 5
1180
0x15C
USBRXTYPE5
RW
0x00
USB Host Configure Receive Type Endpoint 5
1181
0x15D
USBRXINTERVAL5
RW
0x00
USB Host Receive Polling Interval Endpoint 5
1183
0x160
USBTXMAXP6
RW
0x0000
USB Maximum Transmit Data Endpoint 6
1149
0x162
USBTXCSRL6
RW
0x00
USB Transmit Control and Status Endpoint 6 Low
1159
0x163
USBTXCSRH6
RW
0x00
USB Transmit Control and Status Endpoint 6 High
1163
0x164
USBRXMAXP6
RW
0x0000
USB Maximum Receive Data Endpoint 6
1167
0x166
USBRXCSRL6
RW
0x00
USB Receive Control and Status Endpoint 6 Low
1168
0x167
USBRXCSRH6
RW
0x00
USB Receive Control and Status Endpoint 6 High
1173
0x168
USBRXCOUNT6
RO
0x0000
USB Receive Byte Count Endpoint 6
1177
0x16A
USBTXTYPE6
RW
0x00
USB Host Transmit Configure Type Endpoint 6
1178
0x16B
USBTXINTERVAL6
RW
0x00
USB Host Transmit Interval Endpoint 6
1180
0x16C
USBRXTYPE6
RW
0x00
USB Host Configure Receive Type Endpoint 6
1181
0x16D
USBRXINTERVAL6
RW
0x00
USB Host Receive Polling Interval Endpoint 6
1183
0x170
USBTXMAXP7
RW
0x0000
USB Maximum Transmit Data Endpoint 7
1149
0x172
USBTXCSRL7
RW
0x00
USB Transmit Control and Status Endpoint 7 Low
1159
0x173
USBTXCSRH7
RW
0x00
USB Transmit Control and Status Endpoint 7 High
1163
0x174
USBRXMAXP7
RW
0x0000
USB Maximum Receive Data Endpoint 7
1167
0x176
USBRXCSRL7
RW
0x00
USB Receive Control and Status Endpoint 7 Low
1168
0x177
USBRXCSRH7
RW
0x00
USB Receive Control and Status Endpoint 7 High
1173
0x178
USBRXCOUNT7
RO
0x0000
USB Receive Byte Count Endpoint 7
1177
0x17A
USBTXTYPE7
RW
0x00
USB Host Transmit Configure Type Endpoint 7
1178
0x17B
USBTXINTERVAL7
RW
0x00
USB Host Transmit Interval Endpoint 7
1180
0x17C
USBRXTYPE7
RW
0x00
USB Host Configure Receive Type Endpoint 7
1181
0x17D
USBRXINTERVAL7
RW
0x00
USB Host Receive Polling Interval Endpoint 7
1183
0x304
USBRQPKTCOUNT1
RW
0x0000
USB Request Packet Count in Block Transfer Endpoint
1
1184
0x308
USBRQPKTCOUNT2
RW
0x0000
USB Request Packet Count in Block Transfer Endpoint
2
1184
0x30C
USBRQPKTCOUNT3
RW
0x0000
USB Request Packet Count in Block Transfer Endpoint
3
1184
0x310
USBRQPKTCOUNT4
RW
0x0000
USB Request Packet Count in Block Transfer Endpoint
4
1184
Offset
Name
0x15A
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Texas Instruments-Production Data
Universal Serial Bus (USB) Controller
Table 18-5. Universal Serial Bus (USB) Controller Register Map (continued)
Type
Reset
Description
See
page
USBRQPKTCOUNT5
RW
0x0000
USB Request Packet Count in Block Transfer Endpoint
5
1184
0x318
USBRQPKTCOUNT6
RW
0x0000
USB Request Packet Count in Block Transfer Endpoint
6
1184
0x31C
USBRQPKTCOUNT7
RW
0x0000
USB Request Packet Count in Block Transfer Endpoint
7
1184
0x340
USBRXDPKTBUFDIS
RW
0x0000
USB Receive Double Packet Buffer Disable
1185
0x342
USBTXDPKTBUFDIS
RW
0x0000
USB Transmit Double Packet Buffer Disable
1186
0x400
USBEPC
RW
0x0000.0000
USB External Power Control
1187
0x404
USBEPCRIS
RO
0x0000.0000
USB External Power Control Raw Interrupt Status
1190
0x408
USBEPCIM
RW
0x0000.0000
USB External Power Control Interrupt Mask
1191
0x40C
USBEPCISC
RW
0x0000.0000
USB External Power Control Interrupt Status and Clear
1192
0x410
USBDRRIS
RO
0x0000.0000
USB Device RESUME Raw Interrupt Status
1193
0x414
USBDRIM
RW
0x0000.0000
USB Device RESUME Interrupt Mask
1194
0x418
USBDRISC
W1C
0x0000.0000
USB Device RESUME Interrupt Status and Clear
1195
0x41C
USBGPCS
RW
0x0000.0003
USB General-Purpose Control and Status
1196
0x430
USBVDC
RW
0x0000.0000
USB VBUS Droop Control
1197
0x434
USBVDCRIS
RO
0x0000.0000
USB VBUS Droop Control Raw Interrupt Status
1198
0x438
USBVDCIM
RW
0x0000.0000
USB VBUS Droop Control Interrupt Mask
1199
0x43C
USBVDCISC
RW
0x0000.0000
USB VBUS Droop Control Interrupt Status and Clear
1200
0x444
USBIDVRIS
RO
0x0000.0000
USB ID Valid Detect Raw Interrupt Status
1201
0x448
USBIDVIM
RW
0x0000.0000
USB ID Valid Detect Interrupt Mask
1202
0x44C
USBIDVISC
RW1C
0x0000.0000
USB ID Valid Detect Interrupt Status and Clear
1203
0x450
USBDMASEL
RW
0x0033.2211
USB DMA Select
1204
0xFC0
USBPP
RO
0x0000.10D0
USB Peripheral Properties
1206
Offset
Name
0x314
18.6
Register Descriptions
The TM4C1237H6PZ USB controller has On-The-Go (OTG) capabilities as specified in the USB0
bit field in the DC6 register (see page 428).
OTG B /
Device
OTG A /
This icon indicates that the register is used in OTG B or Device mode. Some registers are used for
both Host and Device mode and may have different bit definitions depending on the mode.
This icon indicates that the register is used in OTG A or Host mode. Some registers are used for
both Host and Device mode and may have different bit definitions depending on the mode. The
USB controller is in OTG B or Device mode upon reset, so the reset values shown for these registers
apply to the Device mode definition.
Host
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Tiva™ TM4C1237H6PZ Microcontroller
OTG
This icon indicates that the register is used for OTG-specific functions such as ID detection and
negotiation. Once OTG negotiation is complete, then the USB controller registers are used according
to their Host or Device mode meanings depending on whether the OTG negotiations made the USB
controller OTG A (Host) or OTG B (Device).
June 12, 2014
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Universal Serial Bus (USB) Controller
Register 1: USB Device Functional Address (USBFADDR), offset 0x000
OTG B /
Device
USBFADDR is an 8-bit register that contains the 7-bit address of the Device part of the transaction.
When the USB controller is being used in Device mode (the HOST bit in the USBDEVCTL register
is clear), this register must be written with the address received through a SET_ADDRESS command,
which is then used for decoding the function address in subsequent token packets.
Important: See the section called “Setting the Device Address” on page 1097 for special
considerations when writing this register.
USB Device Functional Address (USBFADDR)
Base 0x4005.0000
Offset 0x000
Type RW, reset 0x00
7
6
5
4
reserved
Type
Reset
RO
0
3
2
1
0
RW
0
RW
0
RW
0
FUNCADDR
RW
0
RW
0
RW
0
RW
0
Bit/Field
Name
Type
Reset
7
reserved
RO
0
6:0
FUNCADDR
RW
0x00
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Function Address
Function Address of Device as received through SET_ADDRESS.
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Tiva™ TM4C1237H6PZ Microcontroller
Register 2: USB Power (USBPOWER), offset 0x001
OTG A /
USBPOWER is an 8-bit register used for controlling SUSPEND and RESUME signaling and some
basic operational aspects of the USB controller.
Host
OTG B /
Device
OTG A / Host Mode
USB Power (USBPOWER)
Base 0x4005.0000
Offset 0x001
Type RW, reset 0x20
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
3
2
RESET
RO
1
RO
0
1
0
RESUME SUSPEND PWRDNPHY
RW
0
RW
0
RW1S
0
Bit/Field
Name
Type
Reset
7:4
reserved
RO
0x2
3
RESET
RW
0
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
RESET Signaling
Value Description
2
RESUME
RW
0
0
Ends RESET signaling on the bus.
1
Enables RESET signaling on the bus.
RESUME Signaling
Value Description
0
Ends RESUME signaling on the bus.
1
Enables RESUME signaling when the Device is in SUSPEND
mode.
This bit must be cleared by software 20 ms after being set.
1
SUSPEND
RW1S
0
SUSPEND Mode
Value Description
0
No effect.
1
Enables SUSPEND mode.
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Universal Serial Bus (USB) Controller
Bit/Field
Name
Type
Reset
0
PWRDNPHY
RW
0
Description
Power Down PHY
Value Description
0
No effect.
1
Powers down the internal USB PHY.
OTG B / Device Mode
USB Power (USBPOWER)
Base 0x4005.0000
Offset 0x001
Type RW, reset 0x20
Type
Reset
7
6
ISOUP
SOFTCONN
RW
0
RW
0
5
4
reserved
RO
1
RO
0
3
2
RESET
1
0
RESUME SUSPEND PWRDNPHY
RO
0
RW
0
RO
0
Bit/Field
Name
Type
Reset
7
ISOUP
RW
0
RW
0
Description
Isochronous Update
Value Description
0
No effect.
1
The USB controller waits for an SOF token from the time the
TXRDY bit is set in the USBTXCSRLn register before sending
the packet. If an IN token is received before an SOF token, then
a zero-length data packet is sent.
Note:
6
SOFTCONN
RW
0
This bit is only valid for isochronous transfers.
Soft Connect/Disconnect
Value Description
5:4
reserved
RO
0x2
3
RESET
RO
0
0
The USB D+/D- lines are tri-stated.
1
The USB D+/D- lines are enabled.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
RESET Signaling
Value Description
0
RESET signaling is not present on the bus.
1
RESET signaling is present on the bus.
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Tiva™ TM4C1237H6PZ Microcontroller
Bit/Field
Name
Type
Reset
2
RESUME
RW
0
Description
RESUME Signaling
Value Description
0
Ends RESUME signaling on the bus.
1
Enables RESUME signaling when the Device is in SUSPEND
mode.
This bit must be cleared by software 10 ms (a maximum of 15 ms) after
being set.
1
SUSPEND
RO
0
SUSPEND Mode
Value Description
0
PWRDNPHY
RW
0
0
This bit is cleared when software reads the interrupt register or
sets the RESUME bit above.
1
The USB controller is in SUSPEND mode.
Power Down PHY
Value Description
0
No effect.
1
Powers down the internal USB PHY.
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Universal Serial Bus (USB) Controller
Register 3: USB Transmit Interrupt Status (USBTXIS), offset 0x002
Important: This register is read-sensitive. See the register description for details.
OTG B /
USBTXIS is a 16-bit read-only register that indicates which interrupts are currently active for endpoint
0 and the transmit endpoints 1–7. The meaning of the EPn bits in this register is based on the mode
of the device. The EP1 through EP7 bits always indicate that the USB controller is sending data;
however, in Host mode, the bits refer to OUT endpoints; while in Device mode, the bits refer to IN
endpoints. The EP0 bit is special in Host and Device modes and indicates that either a control IN
or control OUT endpoint has generated an interrupt.
Device
Note:
OTG A /
Host
Bits relating to endpoints that have not been configured always return 0. Note also that all
active interrupts are cleared when this register is read.
USB Transmit Interrupt Status (USBTXIS)
Base 0x4005.0000
Offset 0x002
Type RO, reset 0x0000
15
14
13
12
11
10
9
8
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
EP7
EP6
EP5
EP4
EP3
EP2
EP1
EP0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
15:8
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7
EP7
RO
0
TX Endpoint 7 Interrupt
Value Description
6
EP6
RO
0
0
No interrupt.
1
The Endpoint 7 transmit interrupt is asserted.
TX Endpoint 6 Interrupt
Same description as EP7.
5
EP5
RO
0
TX Endpoint 5 Interrupt
Same description as EP7.
4
EP4
RO
0
TX Endpoint 4 Interrupt
Same description as EP7.
3
EP3
RO
0
TX Endpoint 3 Interrupt
Same description as EP7.
2
EP2
RO
0
TX Endpoint 2 Interrupt
Same description as EP7.
1
EP1
RO
0
TX Endpoint 1 Interrupt
Same description as EP7.
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Tiva™ TM4C1237H6PZ Microcontroller
Bit/Field
Name
Type
Reset
0
EP0
RO
0
Description
TX and RX Endpoint 0 Interrupt
Value Description
0
No interrupt.
1
The Endpoint 0 transmit and receive interrupt is asserted.
June 12, 2014
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Universal Serial Bus (USB) Controller
Register 4: USB Receive Interrupt Status (USBRXIS), offset 0x004
Important: This register is read-sensitive. See the register description for details.
OTG A /
USBRXIS is a 16-bit read-only register that indicates which of the interrupts for receive endpoints
1–7 are currently active.
Host
Note:
OTG B /
Device
15
Bits relating to endpoints that have not been configured always return 0. Note also that all
active interrupts are cleared when this register is read.
USB Receive Interrupt Status (USBRXIS)
Base 0x4005.0000
Offset 0x004
Type RO, reset 0x0000
14
13
12
11
10
9
8
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
EP7
EP6
EP5
EP4
EP3
EP2
EP1
reserved
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
15:8
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7
EP7
RO
0
RX Endpoint 7 Interrupt
Value Description
6
EP6
RO
0
0
No interrupt.
1
The Endpoint 7 transmit interrupt is asserted.
RX Endpoint 6 Interrupt
Same description as EP7.
5
EP5
RO
0
RX Endpoint 5 Interrupt
Same description as EP7.
4
EP4
RO
0
RX Endpoint 4 Interrupt
Same description as EP7.
3
EP3
RO
0
RX Endpoint 3 Interrupt
Same description as EP7.
2
EP2
RO
0
RX Endpoint 2 Interrupt
Same description as EP7
1
EP1
RO
0
RX Endpoint 1 Interrupt
Same description as EP7.
0
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Tiva™ TM4C1237H6PZ Microcontroller
Register 5: USB Transmit Interrupt Enable (USBTXIE), offset 0x006
OTG A /
Host
USBTXIE is a 16-bit register that provides interrupt enable bits for the interrupts in the USBTXIS
register. When a bit is set, the USB interrupt is asserted to the interrupt controller when the
corresponding interrupt bit in the USBTXIS register is set. When a bit is cleared, the interrupt in the
USBTXIS register is still set but the USB interrupt to the interrupt controller is not asserted. On reset,
all interrupts are enabled.
OTG B /
Device
USB Transmit Interrupt Enable (USBTXIE)
Base 0x4005.0000
Offset 0x006
Type RW, reset 0xFFFF
15
14
13
12
RO
0
RO
0
RO
0
RO
0
11
10
9
8
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
7
6
5
4
3
2
1
0
EP7
EP6
EP5
EP4
EP3
EP2
EP1
EP0
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
Bit/Field
Name
Type
Reset
Description
15:8
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7
EP7
RW
1
TX Endpoint 7 Interrupt Enable
Value Description
6
EP6
RW
1
0
The EP7 transmit interrupt is suppressed and not sent to the
interrupt controller.
1
An interrupt is sent to the interrupt controller when the EP7 bit
in the USBTXIS register is set.
TX Endpoint 6 Interrupt Enable
Same description as EP7.
5
EP5
RW
1
TX Endpoint 5 Interrupt Enable
Same description as EP7.
4
EP4
RW
1
TX Endpoint 4 Interrupt Enable
Same description as EP7.
3
EP3
RW
1
TX Endpoint 3 Interrupt Enable
Same description as EP7.
2
EP2
RW
1
TX Endpoint 2 Interrupt Enable
Same description as EP7.
1
EP1
RW
1
TX Endpoint 1 Interrupt Enable
Same description as EP7.
June 12, 2014
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Universal Serial Bus (USB) Controller
Bit/Field
Name
Type
Reset
0
EP0
RW
1
Description
TX and RX Endpoint 0 Interrupt Enable
Value Description
0
The EP0 transmit and receive interrupt is suppressed and not
sent to the interrupt controller.
1
An interrupt is sent to the interrupt controller when the EP0 bit
in the USBTXIS register is set.
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Tiva™ TM4C1237H6PZ Microcontroller
Register 6: USB Receive Interrupt Enable (USBRXIE), offset 0x008
OTG A /
Host
USBRXIE is a 16-bit register that provides interrupt enable bits for the interrupts in the USBRXIS
register. When a bit is set, the USB interrupt is asserted to the interrupt controller when the
corresponding interrupt bit in the USBRXIS register is set. When a bit is cleared, the interrupt in the
USBRXIS register is still set but the USB interrupt to the interrupt controller is not asserted. On
reset, all interrupts are enabled.
OTG B /
Device
USB Receive Interrupt Enable (USBRXIE)
Base 0x4005.0000
Offset 0x008
Type RW, reset 0xFFFE
15
14
13
12
RO
0
RO
0
RO
0
RO
0
11
10
9
8
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
7
6
5
4
3
2
1
0
EP7
EP6
EP5
EP4
EP3
EP2
EP1
reserved
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RO
0
Bit/Field
Name
Type
Reset
Description
15:8
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7
EP7
RW
1
RX Endpoint 7 Interrupt Enable
Value Description
6
EP6
RW
1
0
The EP7 receive interrupt is suppressed and not sent to the
interrupt controller.
1
An interrupt is sent to the interrupt controller when the EP7 bit
in the USBRXIS register is set.
RX Endpoint 6 Interrupt Enable
Same description as EP7.
5
EP5
RW
1
RX Endpoint 5 Interrupt Enable
Same description as EP7.
4
EP4
RW
1
RX Endpoint 4 Interrupt Enable
Same description as EP7.
3
EP3
RW
1
RX Endpoint 3 Interrupt Enable
Same description as EP7.
2
EP2
RW
1
RX Endpoint 2 Interrupt Enable
Same description as EP7.
1
EP1
RW
1
RX Endpoint 1 Interrupt Enable
Same description as EP7.
0
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
June 12, 2014
1123
Texas Instruments-Production Data
Universal Serial Bus (USB) Controller
Register 7: USB General Interrupt Status (USBIS), offset 0x00A
Important: This register is read-sensitive. See the register description for details.
OTG A /
USBIS is an 8-bit read-only register that indicates which USB interrupts are currently active. All
active interrupts are cleared when this register is read.
Host
OTG B /
Device
OTG A / Host Mode
USB General Interrupt Status (USBIS)
Base 0x4005.0000
Offset 0x00A
Type RO, reset 0x00
7
6
5
VBUSERR SESREQ DISCON
Type
Reset
RO
0
RO
0
4
3
CONN
SOF
RO
0
RO
0
RO
0
2
1
0
BABBLE RESUME reserved
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
7
VBUSERR
RO
0
VBUS Error
Value Description
6
SESREQ
RO
0
0
No interrupt.
1
VBUS has dropped below the VBUS Valid threshold during a
session.
SESSION REQUEST
Value Description
5
DISCON
RO
0
0
No interrupt.
1
SESSION REQUEST signaling has been detected.
Session Disconnect
Value Description
4
CONN
RO
0
0
No interrupt.
1
A Device disconnect has been detected.
Session Connect
Value Description
0
No interrupt.
1
A Device connection has been detected.
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Tiva™ TM4C1237H6PZ Microcontroller
Bit/Field
Name
Type
Reset
3
SOF
RO
0
Description
Start of Frame
Value Description
2
BABBLE
RO
0
0
No interrupt.
1
A new frame has started.
Babble Detected
Value Description
1
RESUME
RO
0
0
No interrupt.
1
Babble has been detected. This interrupt is active only after the
first SOF has been sent.
RESUME Signaling Detected
Value Description
0
No interrupt.
1
RESUME signaling has been detected on the bus while the
USB controller is in SUSPEND mode.
This interrupt can only be used if the USB controller's system clock is
enabled. If the user disables the clock programming, the USBDRRIS,
USBDRIM, and USBDRISC registers should be used.
0
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1
0
OTG B / Device Mode
USB General Interrupt Status (USBIS)
Base 0x4005.0000
Offset 0x00A
Type RO, reset 0x00
7
6
reserved
Type
Reset
RO
0
RO
0
5
4
3
2
DISCON
reserved
SOF
RESET
RO
0
RO
0
RO
0
RO
0
RESUME SUSPEND
RO
0
Bit/Field
Name
Type
Reset
7:6
reserved
RO
0x0
5
DISCON
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Session Disconnect
Value Description
0
No interrupt.
1
The device has been disconnected from the host.
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Universal Serial Bus (USB) Controller
Bit/Field
Name
Type
Reset
Description
4
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
SOF
RO
0
Start of Frame
Value Description
2
RESET
RO
0
0
No interrupt.
1
A new frame has started.
RESET Signaling Detected
Value Description
1
RESUME
RO
0
0
No interrupt.
1
RESET signaling has been detected on the bus.
RESUME Signaling Detected
Value Description
0
No interrupt.
1
RESUME signaling has been detected on the bus while the
USB controller is in SUSPEND mode.
This interrupt can only be used if the USB controller's system clock is
enabled. If the user disables the clock programming, the USBDRRIS,
USBDRIM, and USBDRISC registers should be used.
0
SUSPEND
RO
0
SUSPEND Signaling Detected
Value Description
0
No interrupt.
1
SUSPEND signaling has been detected on the bus.
1126
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Tiva™ TM4C1237H6PZ Microcontroller
Register 8: USB Interrupt Enable (USBIE), offset 0x00B
OTG A /
USBIE is an 8-bit register that provides interrupt enable bits for each of the interrupts in USBIS. At
reset interrupts 1 and 2 are enabled in Device mode.
Host
OTG B /
Device
OTG A / Host Mode
USB Interrupt Enable (USBIE)
Base 0x4005.0000
Offset 0x00B
Type RW, reset 0x06
7
6
5
VBUSERR SESREQ DISCON
Type
Reset
RW
0
RW
0
4
3
CONN
SOF
RW
0
RW
0
RW
0
2
1
0
BABBLE RESUME reserved
RW
1
RW
1
Bit/Field
Name
Type
Reset
7
VBUSERR
RW
0
RO
0
Description
Enable VBUS Error Interrupt
Value Description
6
SESREQ
RW
0
0
The VBUSERR interrupt is suppressed and not sent to the
interrupt controller.
1
An interrupt is sent to the interrupt controller when the VBUSERR
bit in the USBIS register is set.
Enable Session Request
Value Description
5
DISCON
RW
0
0
The SESREQ interrupt is suppressed and not sent to the interrupt
controller.
1
An interrupt is sent to the interrupt controller when the SESREEQ
bit in the USBIS register is set.
Enable Disconnect Interrupt
Value Description
0
The DISCON interrupt is suppressed and not sent to the interrupt
controller.
1
An interrupt is sent to the interrupt controller when the DISCON
bit in the USBIS register is set.
June 12, 2014
1127
Texas Instruments-Production Data
Universal Serial Bus (USB) Controller
Bit/Field
Name
Type
Reset
4
CONN
RW
0
Description
Enable Connect Interrupt
Value Description
3
SOF
RW
0
0
The CONN interrupt is suppressed and not sent to the interrupt
controller.
1
An interrupt is sent to the interrupt controller when the CONN bit
in the USBIS register is set.
Enable Start-of-Frame Interrupt
Value Description
2
BABBLE
RW
1
0
The SOF interrupt is suppressed and not sent to the interrupt
controller.
1
An interrupt is sent to the interrupt controller when the SOF bit
in the USBIS register is set.
Enable Babble Interrupt
Value Description
1
RESUME
RW
1
0
The BABBLE interrupt is suppressed and not sent to the interrupt
controller.
1
An interrupt is sent to the interrupt controller when the BABBLE
bit in the USBIS register is set.
Enable RESUME Interrupt
Value Description
0
reserved
RO
0
The RESUME interrupt is suppressed and not sent to the interrupt
controller.
1
An interrupt is sent to the interrupt controller when the RESUME
bit in the USBIS register is set.
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1
0
OTG B / Device Mode
USB Interrupt Enable (USBIE)
Base 0x4005.0000
Offset 0x00B
Type RW, reset 0x06
7
6
reserved
Type
Reset
RO
0
RO
0
5
4
3
2
DISCON
reserved
SOF
RESET
RW
0
RO
0
RW
0
RW
1
RESUME SUSPEND
RW
1
RW
0
1128
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Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Bit/Field
Name
Type
Reset
7:6
reserved
RO
0x0
5
DISCON
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Enable Disconnect Interrupt
Value Description
0
The DISCON interrupt is suppressed and not sent to the interrupt
controller.
1
An interrupt is sent to the interrupt controller when the DISCON
bit in the USBIS register is set.
4
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
SOF
RW
0
Enable Start-of-Frame Interrupt
Value Description
2
RESET
RW
1
0
The SOF interrupt is suppressed and not sent to the interrupt
controller.
1
An interrupt is sent to the interrupt controller when the SOF bit
in the USBIS register is set.
Enable RESET Interrupt
Value Description
1
RESUME
RW
1
0
The RESET interrupt is suppressed and not sent to the interrupt
controller.
1
An interrupt is sent to the interrupt controller when the RESET
bit in the USBIS register is set.
Enable RESUME Interrupt
Value Description
0
SUSPEND
RW
0
0
The RESUME interrupt is suppressed and not sent to the interrupt
controller.
1
An interrupt is sent to the interrupt controller when the RESUME
bit in the USBIS register is set.
Enable SUSPEND Interrupt
Value Description
0
The SUSPEND interrupt is suppressed and not sent to the
interrupt controller.
1
An interrupt is sent to the interrupt controller when the SUSPEND
bit in the USBIS register is set.
June 12, 2014
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Universal Serial Bus (USB) Controller
Register 9: USB Frame Value (USBFRAME), offset 0x00C
OTG A /
Host
USBFRAME is a 16-bit read-only register that holds the last received frame number.
USB Frame Value (USBFRAME)
Base 0x4005.0000
Offset 0x00C
Type RO, reset 0x0000
OTG B /
15
14
RO
0
RO
0
Device
13
12
11
10
9
8
7
6
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
FRAME
Bit/Field
Name
Type
Reset
15:11
reserved
RO
0x0
10:0
FRAME
RO
0x000
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Frame Number
1130
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Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Register 10: USB Endpoint Index (USBEPIDX), offset 0x00E
OTG A /
Host
Each endpoint's buffer can be accessed by configuring a FIFO size and starting address. The
USBEPIDX 8-bit register is used with the USBTXFIFOSZ, USBRXFIFOSZ, USBTXFIFOADD, and
USBRXFIFOADD registers.
USB Endpoint Index (USBEPIDX)
OTG B /
Device
Base 0x4005.0000
Offset 0x00E
Type RW, reset 0x00
7
6
RO
0
RO
0
5
4
3
2
RO
0
RW
0
RW
0
reserved
Type
Reset
RO
0
1
0
RW
0
RW
0
EPIDX
Bit/Field
Name
Type
Reset
Description
7:4
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3:0
EPIDX
RW
0x0
Endpoint Index
This bit field configures which endpoint is accessed when reading or
writing to one of the USB controller's indexed registers. A value of 0x0
corresponds to Endpoint 0 and a value of 0x7 corresponds to Endpoint
7.
June 12, 2014
1131
Texas Instruments-Production Data
Universal Serial Bus (USB) Controller
Register 11: USB Test Mode (USBTEST), offset 0x00F
OTG A /
Host
USBTEST is an 8-bit register that is primarily used to put the USB controller into one of the four test
modes for operation described in the USB 2.0 Specification, in response to a SET FEATURE:
USBTESTMODE command. This register is not used in normal operation.
Note:
Only one of these bits should be set at any time.
OTG B /
Device
OTG A / Host Mode
USB Test Mode (USBTEST)
Base 0x4005.0000
Offset 0x00F
Type RW, reset 0x00
7
6
5
4
3
2
FORCEH FIFOACC FORCEFS
Type
Reset
RW
0
RW1S
0
RW
0
1
0
RO
0
RO
0
reserved
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
7
FORCEH
RW
0
Description
Force Host Mode
Value Description
0
No effect.
1
Forces the USB controller to enter Host mode when the
SESSION bit is set, regardless of whether the USB controller is
connected to any peripheral. The state of the USB0DP and
USB0DM signals is ignored. The USB controller then remains in
Host mode until the SESSION bit is cleared, even if a Device is
disconnected. If the FORCEH bit remains set, the USB controller
re-enters Host mode the next time the SESSION bit is set.
While in this mode, status of the bus connection may be read using the
DEV bit of the USBDEVCTL register. The operating speed is determined
from the FORCEFS bit.
6
FIFOACC
RW1S
0
FIFO Access
Value Description
0
No effect.
1
Transfers the packet in the endpoint 0 transmit FIFO to the
endpoint 0 receive FIFO.
This bit is cleared automatically.
5
FORCEFS
RW
0
Force Full-Speed Mode
Value Description
0
The USB controller operates at Low Speed.
1
Forces the USB controller into Full-Speed mode upon receiving
a USB RESET.
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Tiva™ TM4C1237H6PZ Microcontroller
Bit/Field
Name
Type
Reset
4:0
reserved
RO
0x0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
OTG B / Device Mode
USB Test Mode (USBTEST)
Base 0x4005.0000
Offset 0x00F
Type RW, reset 0x00
7
6
5
4
3
2
reserved FIFOACC FORCEFS
Type
Reset
RO
0
RW1S
0
RW
0
1
0
RO
0
RO
0
reserved
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
7
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
6
FIFOACC
RW1S
0
FIFO Access
Value Description
0
No effect.
1
Transfers the packet in the endpoint 0 transmit FIFO to the
endpoint 0 receive FIFO.
This bit is cleared automatically.
5
FORCEFS
RW
0
Force Full-Speed Mode
Value Description
4:0
reserved
RO
0x0
0
The USB controller operates at Low Speed.
1
Forces the USB controller into Full-Speed mode upon receiving
a USB RESET.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Texas Instruments-Production Data
Universal Serial Bus (USB) Controller
Register 12: USB FIFO Endpoint 0 (USBFIFO0), offset 0x020
Register 13: USB FIFO Endpoint 1 (USBFIFO1), offset 0x024
Register 14: USB FIFO Endpoint 2 (USBFIFO2), offset 0x028
Register 15: USB FIFO Endpoint 3 (USBFIFO3), offset 0x02C
Register 16: USB FIFO Endpoint 4 (USBFIFO4), offset 0x030
Register 17: USB FIFO Endpoint 5 (USBFIFO5), offset 0x034
Register 18: USB FIFO Endpoint 6 (USBFIFO6), offset 0x038
Register 19: USB FIFO Endpoint 7 (USBFIFO7), offset 0x03C
Important: This register is read-sensitive. See the register description for details.
OTG A /
Host
OTG B /
Device
These 32-bit registers provide an address for CPU access to the FIFOs for each endpoint. Writing
to these addresses loads data into the Transmit FIFO for the corresponding endpoint. Reading from
these addresses unloads data from the Receive FIFO for the corresponding endpoint.
Transfers to and from FIFOs may be 8-bit, 16-bit or 32-bit as required, and any combination of
accesses is allowed provided the data accessed is contiguous. All transfers associated with one
packet must be of the same width so that the data is consistently byte-, halfword- or word-aligned.
However, the last transfer may contain fewer bytes than the previous transfers in order to complete
an odd-byte or odd-word transfer.
Depending on the size of the FIFO and the expected maximum packet size, the FIFOs support
either single-packet or double-packet buffering (see the section called “Single-Packet
Buffering” on page 1095). Burst writing of multiple packets is not supported as flags must be set after
each packet is written.
Following a STALL response or a transmit error on endpoint 1–7, the associated FIFO is completely
flushed.
USB FIFO Endpoint n (USBFIFOn)
Base 0x4005.0000
Offset 0x020
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
EPDATA
Type
Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
EPDATA
Type
Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bit/Field
Name
Type
31:0
EPDATA
RW
RW
0
Reset
RW
0
Description
0x0000.0000 Endpoint Data
Writing to this register loads the data into the Transmit FIFO and reading
unloads data from the Receive FIFO.
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Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Register 20: USB Device Control (USBDEVCTL), offset 0x060
OTG A /
Host
USBDEVCTL is an 8-bit register used for controlling and monitoring the USB VBUS line. If the PHY
is suspended, no PHY clock is received and the VBUS is not sampled. In addition, in Host mode,
USBDEVCTL provides the status information for the current operating mode (Host or Device) of
the USB controller. If the USB controller is in Host mode, this register also indicates if a full- or
low-speed Device has been connected.
USB Device Control (USBDEVCTL)
Base 0x4005.0000
Offset 0x060
Type RW, reset 0x80
Type
Reset
7
6
5
4
DEV
FSDEV
LSDEV
RO
1
RO
0
RO
0
3
2
VBUS
RO
0
HOST
RO
0
RO
0
1
0
HOSTREQ SESSION
RW
0
Bit/Field
Name
Type
Reset
7
DEV
RO
1
RW
0
Description
Device Mode
Value Description
0
The USB controller is operating on the OTG A side of the cable.
1
The USB controller is operating on the OTG B side of the cable.
Note:
6
FSDEV
RO
0
This value is only valid while a session is in progress.
Full-Speed Device Detected
Value Description
5
LSDEV
RO
0
0
A full-speed Device has not been detected on the port.
1
A full-speed Device has been detected on the port.
Low-Speed Device Detected
Value Description
4:3
VBUS
RO
0x0
0
A low-speed Device has not been detected on the port.
1
A low-speed Device has been detected on the port.
VBUS Level
Value Description
0x0
Below SessionEnd
VBUS is detected as under 0.5 V.
0x1
Above SessionEnd, below AValid
VBUS is detected as above 0.5 V and under 1.5 V.
0x2
Above AValid, below VBUSValid
VBUS is detected as above 1.5 V and below 4.75 V.
0x3
Above VBUSValid
VBUS is detected as above 4.75 V.
June 12, 2014
1135
Texas Instruments-Production Data
Universal Serial Bus (USB) Controller
Bit/Field
Name
Type
Reset
Description
2
HOST
RO
0
Host Mode
Value Description
0
The USB controller is acting as a Device.
1
The USB controller is acting as a Host.
Note:
1
HOSTREQ
RW
0
This value is only valid while a session is in progress.
Host Request
Value Description
0
No effect.
1
Initiates the Host Negotiation when SUSPEND mode is entered.
This bit is cleared when Host Negotiation is completed.
0
SESSION
RW
0
Session Start/End
When operating as an OTG A device:
Value Description
0
When cleared by software, this bit ends a session.
1
When set by software, this bit starts a session.
When operating as an OTG B device:
Value Description
0
The USB controller has ended a session. When the USB
controller is in SUSPEND mode, this bit may be cleared by
software to perform a software disconnect.
1
The USB controller has started a session. When set by software,
the Session Request Protocol is initiated.
Note:
Clearing this bit when the USB controller is not suspended
results in undefined behavior.
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Tiva™ TM4C1237H6PZ Microcontroller
Register 21: USB Transmit Dynamic FIFO Sizing (USBTXFIFOSZ), offset 0x062
Register 22: USB Receive Dynamic FIFO Sizing (USBRXFIFOSZ), offset 0x063
OTG A /
Host
These 8-bit registers allow the selected TX/RX endpoint FIFOs to be dynamically sized. USBEPIDX
is used to configure each transmit endpoint's FIFO size.
USB Dynamic FIFO Sizing (USBnXFIFOSZ)
OTG B /
Base 0x4005.0000
Offset 0x062
Type RW, reset 0x00
Device
7
6
5
reserved
Type
Reset
RO
0
RO
0
4
3
2
RW
0
RW
0
DPB
RO
0
RW
0
1
0
RW
0
RW
0
SIZE
Bit/Field
Name
Type
Reset
7:5
reserved
RO
0x0
4
DPB
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Double Packet Buffer Support
Value Description
3:0
SIZE
RW
0x0
0
Only single-packet buffering is supported.
1
Double-packet buffering is supported.
Max Packet Size
Maximum packet size to be allowed.
If DPB = 0, the FIFO also is this size; if DPB = 1, the FIFO is twice this
size.
Value
Packet Size (Bytes)
0x0
8
0x1
16
0x2
32
0x3
64
0x4
128
0x5
256
0x6
512
0x7
1024
0x8
2048
0x9-0xF Reserved
June 12, 2014
1137
Texas Instruments-Production Data
Universal Serial Bus (USB) Controller
Register 23: USB Transmit FIFO Start Address (USBTXFIFOADD), offset 0x064
Register 24: USB Receive FIFO Start Address (USBRXFIFOADD), offset 0x066
OTG A /
Host
OTG B /
USBTXFIFOADD and USBRXFIFOADD are 16-bit registers that control the start address of the
selected transmit and receive endpoint FIFOs.
USB Transmit FIFO Start Address (USBnXFIFOADD)
Base 0x4005.0000
Offset 0x064
Type RW, reset 0x0000
Device
15
14
13
RO
0
RO
0
RO
0
12
11
10
9
8
7
6
5
RO
0
RO
0
RO
0
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
RO
0
4
3
2
1
0
RW
0
RW
0
RW
0
RW
0
ADDR
RW
0
Bit/Field
Name
Type
Reset
Description
15:9
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
8:0
ADDR
RW
0x00
Transmit/Receive Start Address
Start address of the endpoint FIFO.
Value Start Address
0x0
0
0x1
8
0x2
16
0x3
24
0x4
32
0x5
40
0x6
48
0x7
56
0x8
64
...
...
0x1FF 4095
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Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Register 25: USB Connect Timing (USBCONTIM), offset 0x07A
OTG A /
Host
This 8-bit configuration register specifies connection and negotiation delays.
USB Connect Timing (USBCONTIM)
Base 0x4005.0000
Offset 0x07A
Type RW, reset 0x5C
OTG B /
7
6
RW
0
RW
1
Device
5
4
3
2
RW
1
RW
1
RW
1
WTCON
Type
Reset
RW
0
1
0
RW
0
RW
0
WTID
Bit/Field
Name
Type
Reset
7:4
WTCON
RW
0x5
Description
Connect Wait
This field configures the wait required to allow for the user's
connect/disconnect filter, in units of 533.3 ns. The default corresponds
to 2.667 µs.
3:0
WTID
RW
0xC
Wait ID
This field configures the delay required from the enable of the ID
detection to when the ID value is valid, in units of 4.369 ms. The default
corresponds to 52.43 ms.
June 12, 2014
1139
Texas Instruments-Production Data
Universal Serial Bus (USB) Controller
Register 26: USB OTG VBUS Pulse Timing (USBVPLEN), offset 0x07B
This 8-bit configuration register specifies the duration of the VBUS pulsing charge.
OTG
USB OTG VBUS Pulse Timing (USBVPLEN)
Base 0x4005.0000
Offset 0x07B
Type RW, reset 0x3C
7
6
5
4
RW
0
RW
0
RW
1
RW
1
3
2
1
0
RW
1
RW
1
RW
0
RW
0
VPLEN
Type
Reset
Bit/Field
Name
Type
Reset
Description
7:0
VPLEN
RW
0x3C
VBUS Pulse Length
This field configures the duration of the VBUS pulsing charge in units
of 546.1 µs. The default corresponds to 32.77 ms.
1140
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Register 27: USB Full-Speed Last Transaction to End of Frame Timing
(USBFSEOF), offset 0x07D
OTG A /
Host
OTG B /
This 8-bit configuration register specifies the minimum time gap allowed between the start of the
last transaction and the EOF for full-speed transactions.
USB Full-Speed Last Transaction to End of Frame Timing (USBFSEOF)
Base 0x4005.0000
Offset 0x07D
Type RW, reset 0x77
Device
7
6
5
4
3
2
1
0
RW
1
RW
1
RW
1
FSEOFG
Type
Reset
RW
0
RW
1
RW
1
RW
1
RW
0
Bit/Field
Name
Type
Reset
Description
7:0
FSEOFG
RW
0x77
Full-Speed End-of-Frame Gap
This field is used during full-speed transactions to configure the gap
between the last transaction and the End-of-Frame (EOF), in units of
533.3 ns. The default corresponds to 63.46 µs.
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Universal Serial Bus (USB) Controller
Register 28: USB Low-Speed Last Transaction to End of Frame Timing
(USBLSEOF), offset 0x07E
OTG A /
Host
OTG B /
This 8-bit configuration register specifies the minimum time gap that is to be allowed between the
start of the last transaction and the EOF for low-speed transactions.
USB Low-Speed Last Transaction to End of Frame Timing (USBLSEOF)
Base 0x4005.0000
Offset 0x07E
Type RW, reset 0x72
Device
7
6
5
4
3
2
1
0
RW
0
RW
1
RW
0
LSEOFG
Type
Reset
RW
0
RW
1
RW
1
RW
1
RW
0
Bit/Field
Name
Type
Reset
Description
7:0
LSEOFG
RW
0x72
Low-Speed End-of-Frame Gap
This field is used during low-speed transactions to set the gap between
the last transaction and the End-of-Frame (EOF), in units of 1.067 µs.
The default corresponds to 121.6 µs.
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Tiva™ TM4C1237H6PZ Microcontroller
Register 29: USB Transmit Functional Address Endpoint 0
(USBTXFUNCADDR0), offset 0x080
Register 30: USB Transmit Functional Address Endpoint 1
(USBTXFUNCADDR1), offset 0x088
Register 31: USB Transmit Functional Address Endpoint 2
(USBTXFUNCADDR2), offset 0x090
Register 32: USB Transmit Functional Address Endpoint 3
(USBTXFUNCADDR3), offset 0x098
Register 33: USB Transmit Functional Address Endpoint 4
(USBTXFUNCADDR4), offset 0x0A0
Register 34: USB Transmit Functional Address Endpoint 5
(USBTXFUNCADDR5), offset 0x0A8
Register 35: USB Transmit Functional Address Endpoint 6
(USBTXFUNCADDR6), offset 0x0B0
Register 36: USB Transmit Functional Address Endpoint 7
(USBTXFUNCADDR7), offset 0x0B8
OTG A /
Host
USBTXFUNCADDRn is an 8-bit read/write register that records the address of the target function
to be accessed through the associated endpoint (EPn). USBTXFUNCADDRn must be defined for
each transmit endpoint that is used.
Note:
USBTXFUNCADDR0 is used for both receive and transmit for endpoint 0.
USB Transmit Functional Address Endpoint n (USBTXFUNCADDRn)
Base 0x4005.0000
Offset 0x080
Type RW, reset 0x00
7
6
5
4
reserved
Type
Reset
RO
0
3
2
1
0
RW
0
RW
0
RW
0
ADDR
RW
0
RW
0
RW
0
RW
0
Bit/Field
Name
Type
Reset
7
reserved
RO
0
6:0
ADDR
RW
0x00
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Device Address
Specifies the USB bus address for the target Device.
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Universal Serial Bus (USB) Controller
Register 37: USB Transmit Hub Address Endpoint 0 (USBTXHUBADDR0),
offset 0x082
Register 38: USB Transmit Hub Address Endpoint 1 (USBTXHUBADDR1),
offset 0x08A
Register 39: USB Transmit Hub Address Endpoint 2 (USBTXHUBADDR2),
offset 0x092
Register 40: USB Transmit Hub Address Endpoint 3 (USBTXHUBADDR3),
offset 0x09A
Register 41: USB Transmit Hub Address Endpoint 4 (USBTXHUBADDR4),
offset 0x0A2
Register 42: USB Transmit Hub Address Endpoint 5 (USBTXHUBADDR5),
offset 0x0AA
Register 43: USB Transmit Hub Address Endpoint 6 (USBTXHUBADDR6),
offset 0x0B2
Register 44: USB Transmit Hub Address Endpoint 7 (USBTXHUBADDR7),
offset 0x0BA
OTG A /
Host
USBTXHUBADDRn is an 8-bit read/write register that, like USBTXHUBPORTn, only must be written
when a USB Device is connected to transmit endpoint EPn via a USB 2.0 hub. This register records
the address of the USB 2.0 hub through which the target associated with the endpoint is accessed.
Note:
USBTXHUBADDR0 is used for both receive and transmit for endpoint 0.
USB Transmit Hub Address Endpoint n (USBTXHUBADDRn)
Base 0x4005.0000
Offset 0x082
Type RW, reset 0x00
7
6
5
4
reserved
Type
Reset
RO
0
3
2
1
0
RW
0
RW
0
RW
0
ADDR
RW
0
RW
0
RW
0
RW
0
Bit/Field
Name
Type
Reset
7
reserved
RO
0
6:0
ADDR
RW
0x00
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Hub Address
This field specifies the USB bus address for the USB 2.0 hub.
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Tiva™ TM4C1237H6PZ Microcontroller
Register 45: USB Transmit Hub Port Endpoint 0 (USBTXHUBPORT0), offset
0x083
Register 46: USB Transmit Hub Port Endpoint 1 (USBTXHUBPORT1), offset
0x08B
Register 47: USB Transmit Hub Port Endpoint 2 (USBTXHUBPORT2), offset
0x093
Register 48: USB Transmit Hub Port Endpoint 3 (USBTXHUBPORT3), offset
0x09B
Register 49: USB Transmit Hub Port Endpoint 4 (USBTXHUBPORT4), offset
0x0A3
Register 50: USB Transmit Hub Port Endpoint 5 (USBTXHUBPORT5), offset
0x0AB
Register 51: USB Transmit Hub Port Endpoint 6 (USBTXHUBPORT6), offset
0x0B3
Register 52: USB Transmit Hub Port Endpoint 7 (USBTXHUBPORT7), offset
0x0BB
OTG A /
Host
USBTXHUBPORTn is an 8-bit read/write register that, like USBTXHUBADDRn, only must be written
when a full- or low-speed Device is connected to transmit endpoint EPn via a USB 2.0 hub. This
register records the port of the USB 2.0 hub through which the target associated with the endpoint
is accessed.
Note:
USBTXHUBPORT0 is used for both receive and transmit for endpoint 0.
USB Transmit Hub Port Endpoint n (USBTXHUBPORTn)
Base 0x4005.0000
Offset 0x083
Type RW, reset 0x00
7
6
5
4
reserved
Type
Reset
RO
0
3
2
1
0
RW
0
RW
0
RW
0
PORT
RW
0
RW
0
RW
0
RW
0
Bit/Field
Name
Type
Reset
7
reserved
RO
0
6:0
PORT
RW
0x00
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Hub Port
This field specifies the USB hub port number.
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Universal Serial Bus (USB) Controller
Register 53: USB Receive Functional Address Endpoint 1
(USBRXFUNCADDR1), offset 0x08C
Register 54: USB Receive Functional Address Endpoint 2
(USBRXFUNCADDR2), offset 0x094
Register 55: USB Receive Functional Address Endpoint 3
(USBRXFUNCADDR3), offset 0x09C
Register 56: USB Receive Functional Address Endpoint 4
(USBRXFUNCADDR4), offset 0x0A4
Register 57: USB Receive Functional Address Endpoint 5
(USBRXFUNCADDR5), offset 0x0AC
Register 58: USB Receive Functional Address Endpoint 6
(USBRXFUNCADDR6), offset 0x0B4
Register 59: USB Receive Functional Address Endpoint 7
(USBRXFUNCADDR7), offset 0x0BC
OTG A /
Host
USBRXFUNCADDRn is an 8-bit read/write register that records the address of the target function
accessed through the associated endpoint (EPn). USBRXFUNCADDRn must be defined for each
receive endpoint that is used.
Note:
USBTXFUNCADDR0 is used for both receive and transmit for endpoint 0.
USB Receive Functional Address Endpoint n (USBRXFUNCADDRn)
Base 0x4005.0000
Offset 0x08C
Type RW, reset 0x00
7
6
5
4
RW
0
RW
0
RW
0
reserved
Type
Reset
RO
0
3
2
1
0
RW
0
RW
0
RW
0
ADDR
RW
0
Bit/Field
Name
Type
Reset
7
reserved
RO
0
6:0
ADDR
RW
0x00
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Device Address
This field specifies the USB bus address for the target Device.
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Tiva™ TM4C1237H6PZ Microcontroller
Register 60: USB Receive Hub Address Endpoint 1 (USBRXHUBADDR1),
offset 0x08E
Register 61: USB Receive Hub Address Endpoint 2 (USBRXHUBADDR2),
offset 0x096
Register 62: USB Receive Hub Address Endpoint 3 (USBRXHUBADDR3),
offset 0x09E
Register 63: USB Receive Hub Address Endpoint 4 (USBRXHUBADDR4),
offset 0x0A6
Register 64: USB Receive Hub Address Endpoint 5 (USBRXHUBADDR5),
offset 0x0AE
Register 65: USB Receive Hub Address Endpoint 6 (USBRXHUBADDR6),
offset 0x0B6
Register 66: USB Receive Hub Address Endpoint 7 (USBRXHUBADDR7),
offset 0x0BE
OTG A /
Host
USBRXHUBADDRn is an 8-bit read/write register that, like USBRXHUBPORTn, only must be
written when a full- or low-speed Device is connected to receive endpoint EPn via a USB 2.0 hub.
This register records the address of the USB 2.0 hub through which the target associated with the
endpoint is accessed.
Note:
USBTXHUBADDR0 is used for both receive and transmit for endpoint 0.
USB Receive Hub Address Endpoint n (USBRXHUBADDRn)
Base 0x4005.0000
Offset 0x08E
Type RW, reset 0x00
7
6
5
4
RW
0
RW
0
RW
0
reserved
Type
Reset
RO
0
3
2
1
0
RW
0
RW
0
RW
0
ADDR
RW
0
Bit/Field
Name
Type
Reset
7
reserved
RO
0
6:0
ADDR
RW
0x00
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Hub Address
This field specifies the USB bus address for the USB 2.0 hub.
June 12, 2014
1147
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Universal Serial Bus (USB) Controller
Register 67: USB Receive Hub Port Endpoint 1 (USBRXHUBPORT1), offset
0x08F
Register 68: USB Receive Hub Port Endpoint 2 (USBRXHUBPORT2), offset
0x097
Register 69: USB Receive Hub Port Endpoint 3 (USBRXHUBPORT3), offset
0x09F
Register 70: USB Receive Hub Port Endpoint 4 (USBRXHUBPORT4), offset
0x0A7
Register 71: USB Receive Hub Port Endpoint 5 (USBRXHUBPORT5), offset
0x0AF
Register 72: USB Receive Hub Port Endpoint 6 (USBRXHUBPORT6), offset
0x0B7
Register 73: USB Receive Hub Port Endpoint 7 (USBRXHUBPORT7), offset
0x0BF
OTG A /
Host
USBRXHUBPORTn is an 8-bit read/write register that, like USBRXHUBADDRn, only must be
written when a full- or low-speed Device is connected to receive endpoint EPn via a USB 2.0 hub.
This register records the port of the USB 2.0 hub through which the target associated with the
endpoint is accessed.
Note:
USBTXHUBPORT0 is used for both receive and transmit for endpoint 0.
USB Receive Hub Port Endpoint n (USBRXHUBPORTn)
Base 0x4005.0000
Offset 0x08F
Type RW, reset 0x00
7
6
5
4
RW
0
RW
0
RW
0
reserved
Type
Reset
RO
0
3
2
1
0
RW
0
RW
0
RW
0
PORT
RW
0
Bit/Field
Name
Type
Reset
7
reserved
RO
0
6:0
PORT
RW
0x00
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Hub Port
This field specifies the USB hub port number.
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Tiva™ TM4C1237H6PZ Microcontroller
Register 74: USB Maximum Transmit Data Endpoint 1 (USBTXMAXP1), offset
0x110
Register 75: USB Maximum Transmit Data Endpoint 2 (USBTXMAXP2), offset
0x120
Register 76: USB Maximum Transmit Data Endpoint 3 (USBTXMAXP3), offset
0x130
Register 77: USB Maximum Transmit Data Endpoint 4 (USBTXMAXP4), offset
0x140
Register 78: USB Maximum Transmit Data Endpoint 5 (USBTXMAXP5), offset
0x150
Register 79: USB Maximum Transmit Data Endpoint 6 (USBTXMAXP6), offset
0x160
Register 80: USB Maximum Transmit Data Endpoint 7 (USBTXMAXP7), offset
0x170
OTG A /
Host
OTG B /
Device
The USBTXMAXPn 16-bit register defines the maximum amount of data that can be transferred
through the transmit endpoint in a single operation.
Bits 10:0 define (in bytes) the maximum payload transmitted in a single transaction. The value set
can be up to 1024 bytes but is subject to the constraints placed by the USB Specification on packet
sizes for bulk, interrupt and isochronous transfers in full-speed operation.
The total amount of data represented by the value written to this register must not exceed the FIFO
size for the transmit endpoint, and must not exceed half the FIFO size if double-buffering is required.
If this register is changed after packets have been sent from the endpoint, the transmit endpoint
FIFO must be completely flushed (using the FLUSH bit in USBTXCSRLn) after writing the new value
to this register.
Note:
USBTXMAXPn must be set to an even number of bytes for proper interrupt generation in
µDMA Basic Mode.
USB Maximum Transmit Data Endpoint n (USBTXMAXPn)
Base 0x4005.0000
Offset 0x110
Type RW, reset 0x0000
15
14
13
12
11
10
9
8
7
6
reserved
Type
Reset
RO
0
RO
0
RO
0
5
4
3
2
1
0
RW
0
RW
0
RW
0
RW
0
RW
0
MAXLOAD
RO
0
RO
0
RW
0
RW
0
Bit/Field
Name
Type
Reset
15:11
reserved
RO
0x0
10:0
MAXLOAD
RW
0x000
RW
0
RW
0
RW
0
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Maximum Payload
This field specifies the maximum payload in bytes per transaction.
June 12, 2014
1149
Texas Instruments-Production Data
Universal Serial Bus (USB) Controller
Register 81: USB Control and Status Endpoint 0 Low (USBCSRL0), offset
0x102
OTG A /
USBCSRL0 is an 8-bit register that provides control and status bits for endpoint 0.
Host
OTG B /
Device
OTG A / Host Mode
USB Control and Status Endpoint 0 Low (USBCSRL0)
Base 0x4005.0000
Offset 0x102
Type W1C, reset 0x00
7
NAKTO
Type
Reset
RW
0
6
5
STATUS REQPKT
RW
0
4
3
2
1
0
ERROR
SETUP
STALLED
TXRDY
RXRDY
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bit/Field
Name
Type
Reset
7
NAKTO
RW
0
Description
NAK Timeout
Value Description
0
No timeout.
1
Indicates that endpoint 0 is halted following the receipt of NAK
responses for longer than the time set by the USBNAKLMT
register.
Software must clear this bit to allow the endpoint to continue.
6
STATUS
RW
0
STATUS Packet
Value Description
0
No transaction.
1
Initiates a STATUS stage transaction. This bit must be set at
the same time as the TXRDY or REQPKT bit is set.
Setting this bit ensures that the DT bit is set in the USBCSRH0 register
so that a DATA1 packet is used for the STATUS stage transaction.
This bit is automatically cleared when the STATUS stage is over.
5
REQPKT
RW
0
Request Packet
Value Description
0
No request.
1
Requests an IN transaction.
This bit is cleared when the RXRDY bit is set.
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Tiva™ TM4C1237H6PZ Microcontroller
Bit/Field
Name
Type
Reset
4
ERROR
RW
0
Description
Error
Value Description
0
No error.
1
Three attempts have been made to perform a transaction with
no response from the peripheral. The EP0 bit in the USBTXIS
register is also set in this situation.
Software must clear this bit.
3
SETUP
RW
0
Setup Packet
Value Description
0
Sends an OUT token.
1
Sends a SETUP token instead of an OUT token for the
transaction. This bit should be set at the same time as the
TXRDY bit is set.
Setting this bit always clears the DT bit in the USBCSRH0 register to
send a DATA0 packet.
2
STALLED
RW
0
Endpoint Stalled
Value Description
0
No handshake has been received.
1
A STALL handshake has been received.
Software must clear this bit.
1
TXRDY
RW
0
Transmit Packet Ready
Value Description
0
No transmit packet is ready.
1
Software sets this bit after loading a data packet into the TX
FIFO. The EP0 bit in the USBTXIS register is also set in this
situation.
If both the TXRDY and SETUP bits are set, a setup packet is
sent. If just TXRDY is set, an OUT packet is sent.
This bit is cleared automatically when the data packet has been
transmitted.
0
RXRDY
RW
0
Receive Packet Ready
Value Description
0
No received packet has been received.
1
Indicates that a data packet has been received in the RX FIFO.
The EP0 bit in the USBTXIS register is also set in this situation.
Software must clear this bit after the packet has been read from the
FIFO to acknowledge that the data has been read from the FIFO.
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Texas Instruments-Production Data
Universal Serial Bus (USB) Controller
OTG B / Device Mode
USB Control and Status Endpoint 0 Low (USBCSRL0)
Base 0x4005.0000
Offset 0x102
Type W1C, reset 0x00
7
6
SETENDC RXRDYC
Type
Reset
W1C
0
W1C
0
5
STALL
4
3
2
SETEND DATAEND STALLED
RW
0
RO
0
RW
0
RW
0
1
0
TXRDY
RXRDY
RW
0
RO
0
Bit/Field
Name
Type
Reset
7
SETENDC
W1C
0
Description
Setup End Clear
Writing a 1 to this bit clears the SETEND bit.
6
RXRDYC
W1C
0
RXRDY Clear
Writing a 1 to this bit clears the RXRDY bit.
5
STALL
RW
0
Send Stall
Value Description
0
No effect.
1
Terminates the current transaction and transmits the STALL
handshake.
This bit is cleared automatically after the STALL handshake is
transmitted.
4
SETEND
RO
0
Setup End
Value Description
0
A control transaction has not ended or ended after the DATAEND
bit was set.
1
A control transaction has ended before the DATAEND bit has
been set. The EP0 bit in the USBTXIS register is also set in this
situation.
This bit is cleared by writing a 1 to the SETENDC bit.
3
DATAEND
RW
0
Data End
Value Description
0
No effect.
1
Set this bit in the following situations:
■
When setting TXRDY for the last data packet
■
When clearing RXRDY after unloading the last data
packet
■
When setting TXRDY for a zero-length data packet
This bit is cleared automatically.
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Tiva™ TM4C1237H6PZ Microcontroller
Bit/Field
Name
Type
Reset
2
STALLED
RW
0
Description
Endpoint Stalled
Value Description
0
A STALL handshake has not been transmitted.
1
A STALL handshake has been transmitted.
Software must clear this bit.
1
TXRDY
RW
0
Transmit Packet Ready
Value Description
0
No transmit packet is ready.
1
Software sets this bit after loading an IN data packet into the
TX FIFO. The EP0 bit in the USBTXIS register is also set in this
situation.
This bit is cleared automatically when the data packet has been
transmitted.
0
RXRDY
RO
0
Receive Packet Ready
Value Description
0
No data packet has been received.
1
A data packet has been received. The EP0 bit in the USBTXIS
register is also set in this situation.
This bit is cleared by writing a 1 to the RXRDYC bit.
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1153
Texas Instruments-Production Data
Universal Serial Bus (USB) Controller
Register 82: USB Control and Status Endpoint 0 High (USBCSRH0), offset
0x103
OTG A /
USBSR0H is an 8-bit register that provides control and status bits for endpoint 0.
Host
OTG B /
Device
OTG A / Host Mode
USB Control and Status Endpoint 0 High (USBCSRH0)
Base 0x4005.0000
Offset 0x103
Type W1C, reset 0x00
7
6
RO
0
RO
0
5
4
3
RO
0
RO
0
2
reserved
Type
Reset
RO
0
1
0
DTWE
DT
FLUSH
RW
0
RW
0
RW
0
Bit/Field
Name
Type
Reset
7:3
reserved
RO
0x0
2
DTWE
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Data Toggle Write Enable
Value Description
0
The DT bit cannot be written.
1
Enables the current state of the endpoint 0 data toggle to be
written (see DT bit).
This bit is automatically cleared once the new value is written.
1
DT
RW
0
Data Toggle
When read, this bit indicates the current state of the endpoint 0 data
toggle.
If DTWE is set, this bit may be written with the required setting of the data
toggle. If DTWE is Low, this bit cannot be written. Care should be taken
when writing to this bit as it should only be changed to RESET USB
endpoint 0.
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Tiva™ TM4C1237H6PZ Microcontroller
Bit/Field
Name
Type
Reset
Description
0
FLUSH
RW
0
Flush FIFO
Value Description
0
No effect.
1
Flushes the next packet to be transmitted/read from the endpoint
0 FIFO. The FIFO pointer is reset and the TXRDY/RXRDY bit is
cleared.
This bit is automatically cleared after the flush is performed.
Important:
This bit should only be set when TXRDY is clear and
RXRDY is set. At other times, it may cause data to be
corrupted.
OTG B / Device Mode
USB Control and Status Endpoint 0 High (USBCSRH0)
Base 0x4005.0000
Offset 0x103
Type W1C, reset 0x00
7
6
5
RO
0
RO
0
RO
0
4
3
2
1
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
0
FLUSH
RW
0
Bit/Field
Name
Type
Reset
Description
7:1
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
FLUSH
RW
0
Flush FIFO
Value Description
0
No effect.
1
Flushes the next packet to be transmitted/read from the endpoint
0 FIFO. The FIFO pointer is reset and the TXRDY/RXRDY bit is
cleared.
This bit is automatically cleared after the flush is performed.
Important:
This bit should only be set when TXRDY is clear and
RXRDY is set. At other times, it may cause data to be
corrupted.
June 12, 2014
1155
Texas Instruments-Production Data
Universal Serial Bus (USB) Controller
Register 83: USB Receive Byte Count Endpoint 0 (USBCOUNT0), offset 0x108
OTG A /
Host
USBCOUNT0 is an 8-bit read-only register that indicates the number of received data bytes in the
endpoint 0 FIFO. The value returned changes as the contents of the FIFO change and is only valid
while the RXRDY bit is set.
USB Receive Byte Count Endpoint 0 (USBCOUNT0)
OTG B /
Device
Base 0x4005.0000
Offset 0x108
Type RO, reset 0x00
7
6
5
4
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
3
2
1
0
RO
0
RO
0
RO
0
COUNT
RO
0
Bit/Field
Name
Type
Reset
7
reserved
RO
0
6:0
COUNT
RO
0x00
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
FIFO Count
COUNT is a read-only value that indicates the number of received data
bytes in the endpoint 0 FIFO.
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Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Register 84: USB Type Endpoint 0 (USBTYPE0), offset 0x10A
OTG A /
Host
This is an 8-bit register that must be written with the operating speed of the targeted Device being
communicated with using endpoint 0.
USB Type Endpoint 0 (USBTYPE0)
Base 0x4005.0000
Offset 0x10A
Type RW, reset 0x00
7
6
5
4
3
RW
0
RO
0
RO
0
RO
0
SPEED
Type
Reset
RW
0
2
1
0
RO
0
RO
0
RO
0
reserved
Bit/Field
Name
Type
Reset
7:6
SPEED
RW
0x0
Description
Operating Speed
This field specifies the operating speed of the target Device. If selected,
the target is assumed to have the same connection speed as the USB
controller.
Value
Description
0x0 - 0x1 Reserved
5:0
reserved
RO
0x0
0x2
Full
0x3
Low
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Universal Serial Bus (USB) Controller
Register 85: USB NAK Limit (USBNAKLMT), offset 0x10B
OTG A /
Host
USBNAKLMT is an 8-bit register that sets the number of frames after which endpoint 0 should time
out on receiving a stream of NAK responses. (Equivalent settings for other endpoints can be made
through their USBTXINTERVALn and USBRXINTERVALn registers.)
(m-1)
The number of frames selected is 2
(where m is the value set in the register, with valid values of
2–16). If the Host receives NAK responses from the target for more frames than the number
represented by the limit set in this register, the endpoint is halted.
Note:
A value of 0 or 1 disables the NAK timeout function.
USB NAK Limit (USBNAKLMT)
Base 0x4005.0000
Offset 0x10B
Type RW, reset 0x00
7
6
5
4
3
RO
0
RW
0
RW
0
reserved
Type
Reset
RO
0
RO
0
2
1
0
RW
0
RW
0
NAKLMT
RW
0
Bit/Field
Name
Type
Reset
Description
7:5
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
4:0
NAKLMT
RW
0x0
EP0 NAK Limit
This field specifies the number of frames after receiving a stream of
NAK responses.
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Tiva™ TM4C1237H6PZ Microcontroller
Register 86: USB Transmit Control and Status Endpoint 1 Low (USBTXCSRL1),
offset 0x112
Register 87: USB Transmit Control and Status Endpoint 2 Low (USBTXCSRL2),
offset 0x122
Register 88: USB Transmit Control and Status Endpoint 3 Low (USBTXCSRL3),
offset 0x132
Register 89: USB Transmit Control and Status Endpoint 4 Low (USBTXCSRL4),
offset 0x142
Register 90: USB Transmit Control and Status Endpoint 5 Low (USBTXCSRL5),
offset 0x152
Register 91: USB Transmit Control and Status Endpoint 6 Low (USBTXCSRL6),
offset 0x162
Register 92: USB Transmit Control and Status Endpoint 7 Low (USBTXCSRL7),
offset 0x172
OTG A /
USBTXCSRLn is an 8-bit register that provides control and status bits for transfers through the
currently selected transmit endpoint.
Host
OTG B /
Device
OTG A / Host Mode
USB Transmit Control and Status Endpoint n Low (USBTXCSRLn)
Base 0x4005.0000
Offset 0x112
Type RW, reset 0x00
Type
Reset
7
6
5
4
3
2
1
0
NAKTO
CLRDT
STALLED
SETUP
FLUSH
ERROR
FIFONE
TXRDY
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bit/Field
Name
Type
Reset
7
NAKTO
RW
0
Description
NAK Timeout
Value Description
0
No timeout.
1
Bulk endpoints only: Indicates that the transmit endpoint is halted
following the receipt of NAK responses for longer than the time
set by the NAKLMT field in the USBTXINTERVALn register.
Software must clear this bit to allow the endpoint to continue.
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Universal Serial Bus (USB) Controller
Bit/Field
Name
Type
Reset
6
CLRDT
RW
0
Description
Clear Data Toggle
Writing a 1 to this bit clears the DT bit in the USBTXCSRHn register.
5
STALLED
RW
0
Endpoint Stalled
Value Description
0
A STALL handshake has not been received.
1
Indicates that a STALL handshake has been received. When
this bit is set, any µDMA request that is in progress is stopped,
the FIFO is completely flushed, and the TXRDY bit is cleared.
Software must clear this bit.
4
SETUP
RW
0
Setup Packet
Value Description
0
No SETUP token is sent.
1
Sends a SETUP token instead of an OUT token for the
transaction. This bit should be set at the same time as the
TXRDY bit is set.
Note:
3
FLUSH
RW
0
Setting this bit also clears the DT bit in the USBTXCSRHn
register.
Flush FIFO
Value Description
0
No effect.
1
Flushes the latest packet from the endpoint transmit FIFO. The
FIFO pointer is reset and the TXRDY bit is cleared. The EPn bit
in the USBTXIS register is also set in this situation.
This bit may be set simultaneously with the TXRDY bit to abort the packet
that is currently being loaded into the FIFO. Note that if the FIFO is
double-buffered, FLUSH may have to be set twice to completely clear
the FIFO.
Important:
2
ERROR
RW
0
This bit should only be set when the TXRDY bit is clear.
At other times, it may cause data to be corrupted.
Error
Value Description
0
No error.
1
Three attempts have been made to send a packet and no
handshake packet has been received. The TXRDY bit is cleared,
the EPn bit in the USBTXIS register is set, and the FIFO is
completely flushed in this situation.
Software must clear this bit.
Note:
This is valid only when the endpoint is operating in Bulk or
Interrupt mode.
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Tiva™ TM4C1237H6PZ Microcontroller
Bit/Field
Name
Type
Reset
1
FIFONE
RW
0
Description
FIFO Not Empty
Value Description
0
TXRDY
RW
0
0
The FIFO is empty.
1
At least one packet is in the transmit FIFO.
Transmit Packet Ready
Value Description
0
No transmit packet is ready.
1
Software sets this bit after loading a data packet into the TX
FIFO.
This bit is cleared automatically when a data packet has been
transmitted. The EPn bit in the USBTXIS register is also set at this point.
TXRDY is also automatically cleared prior to loading a second packet
into a double-buffered FIFO.
OTG B / Device Mode
USB Transmit Control and Status Endpoint n Low (USBTXCSRLn)
Base 0x4005.0000
Offset 0x112
Type RW, reset 0x00
Type
Reset
7
6
5
4
3
2
1
0
reserved
CLRDT
STALLED
STALL
FLUSH
UNDRN
FIFONE
TXRDY
RO
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bit/Field
Name
Type
Reset
Description
7
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
6
CLRDT
RW
0
Clear Data Toggle
Writing a 1 to this bit clears the DT bit in the USBTXCSRHn register.
5
STALLED
RW
0
Endpoint Stalled
Value Description
0
A STALL handshake has not been transmitted.
1
A STALL handshake has been transmitted. The FIFO is flushed
and the TXRDY bit is cleared.
Software must clear this bit.
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Universal Serial Bus (USB) Controller
Bit/Field
Name
Type
Reset
Description
4
STALL
RW
0
Send STALL
Value Description
0
No effect.
1
Issues a STALL handshake to an IN token.
Software clears this bit to terminate the STALL condition.
Note:
3
FLUSH
RW
0
This bit has no effect in isochronous transfers.
Flush FIFO
Value Description
0
No effect.
1
Flushes the latest packet from the endpoint transmit FIFO. The
FIFO pointer is reset and the TXRDY bit is cleared. The EPn bit
in the USBTXIS register is also set in this situation.
This bit may be set simultaneously with the TXRDY bit to abort the packet
that is currently being loaded into the FIFO. Note that if the FIFO is
double-buffered, FLUSH may have to be set twice to completely clear
the FIFO.
Important:
2
UNDRN
RW
0
This bit should only be set when the TXRDY bit is clear.
At other times, it may cause data to be corrupted.
Underrun
Value Description
0
No underrun.
1
An IN token has been received when TXRDY is not set.
Software must clear this bit.
1
FIFONE
RW
0
FIFO Not Empty
Value Description
0
TXRDY
RW
0
0
The FIFO is empty.
1
At least one packet is in the transmit FIFO.
Transmit Packet Ready
Value Description
0
No transmit packet is ready.
1
Software sets this bit after loading a data packet into the TX
FIFO.
This bit is cleared automatically when a data packet has been
transmitted. The EPn bit in the USBTXIS register is also set at this point.
TXRDY is also automatically cleared prior to loading a second packet
into a double-buffered FIFO.
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Tiva™ TM4C1237H6PZ Microcontroller
Register 93: USB Transmit Control and Status Endpoint 1 High (USBTXCSRH1),
offset 0x113
Register 94: USB Transmit Control and Status Endpoint 2 High (USBTXCSRH2),
offset 0x123
Register 95: USB Transmit Control and Status Endpoint 3 High (USBTXCSRH3),
offset 0x133
Register 96: USB Transmit Control and Status Endpoint 4 High (USBTXCSRH4),
offset 0x143
Register 97: USB Transmit Control and Status Endpoint 5 High (USBTXCSRH5),
offset 0x153
Register 98: USB Transmit Control and Status Endpoint 6 High (USBTXCSRH6),
offset 0x163
Register 99: USB Transmit Control and Status Endpoint 7 High (USBTXCSRH7),
offset 0x173
OTG A /
USBTXCSRHn is an 8-bit register that provides additional control for transfers through the currently
selected transmit endpoint.
Host
OTG B /
Device
OTG A / Host Mode
USB Transmit Control and Status Endpoint n High (USBTXCSRHn)
Base 0x4005.0000
Offset 0x113
Type RW, reset 0x00
7
6
AUTOSET reserved
Type
Reset
RW
0
RO
0
5
4
3
2
1
MODE
DMAEN
FDT
DMAMOD
DTWE
DT
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bit/Field
Name
Type
Reset
7
AUTOSET
RW
0
0
Description
Auto Set
Value Description
0
The TXRDY bit must be set manually.
1
Enables the TXRDY bit to be automatically set when data of the
maximum packet size (value in USBTXMAXPn) is loaded into
the transmit FIFO. If a packet of less than the maximum packet
size is loaded, then the TXRDY bit must be set manually.
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Universal Serial Bus (USB) Controller
Bit/Field
Name
Type
Reset
Description
6
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5
MODE
RW
0
Mode
Value Description
0
Enables the endpoint direction as RX.
1
Enables the endpoint direction as TX.
Note:
4
DMAEN
RW
0
This bit only has an effect when the same endpoint FIFO is
used for both transmit and receive transactions.
DMA Request Enable
Value Description
0
Disables the DMA request for the transmit endpoint.
1
Enables the DMA request for the transmit endpoint.
Note:
3
FDT
RW
0
3 TX and 3 /RX endpoints can be connected to the µDMA
module. If this bit is set for a particular endpoint, the DMAATX,
DMABTX, or DMACTX field in the USB DMA Select
(USBDMASEL) register must be programmed
correspondingly.
Force Data Toggle
Value Description
2
DMAMOD
RW
0
0
No effect.
1
Forces the endpoint DT bit to switch and the data packet to be
cleared from the FIFO, regardless of whether an ACK was
received. This bit can be used by interrupt transmit endpoints
that are used to communicate rate feedback for isochronous
endpoints.
DMA Request Mode
Value Description
0
An interrupt is generated after every DMA packet transfer.
1
An interrupt is generated only after the entire DMA transfer is
complete.
Note:
1
DTWE
RW
0
This bit must not be cleared either before or in the same cycle
as the above DMAEN bit is cleared.
Data Toggle Write Enable
Value Description
0
The DT bit cannot be written.
1
Enables the current state of the transmit endpoint data to be
written (see DT bit).
This bit is automatically cleared once the new value is written.
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Tiva™ TM4C1237H6PZ Microcontroller
Bit/Field
Name
Type
Reset
Description
0
DT
RW
0
Data Toggle
When read, this bit indicates the current state of the transmit endpoint
data toggle.
If DTWE is High, this bit may be written with the required setting of the
data toggle. If DTWE is Low, any value written to this bit is ignored. Care
should be taken when writing to this bit as it should only be changed to
RESET the transmit endpoint.
OTG B / Device Mode
USB Transmit Control and Status Endpoint n High (USBTXCSRHn)
Base 0x4005.0000
Offset 0x113
Type RW, reset 0x00
Type
Reset
7
6
5
4
3
2
AUTOSET
ISO
MODE
DMAEN
FDT
DMAMOD
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
1
0
reserved
RO
0
Bit/Field
Name
Type
Reset
7
AUTOSET
RW
0
RO
0
Description
Auto Set
Value Description
6
ISO
RW
0
0
The TXRDY bit must be set manually.
1
Enables the TXRDY bit to be automatically set when data of the
maximum packet size (value in USBTXMAXPn) is loaded into
the transmit FIFO. If a packet of less than the maximum packet
size is loaded, then the TXRDY bit must be set manually.
Isochronous Transfers
Value Description
5
MODE
RW
0
0
Enables the transmit endpoint for bulk or interrupt transfers.
1
Enables the transmit endpoint for isochronous transfers.
Mode
Value Description
0
Enables the endpoint direction as RX.
1
Enables the endpoint direction as TX.
Note:
This bit only has an effect where the same endpoint FIFO is
used for both transmit and receive transactions.
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Universal Serial Bus (USB) Controller
Bit/Field
Name
Type
Reset
4
DMAEN
RW
0
Description
DMA Request Enable
Value Description
0
Disables the DMA request for the transmit endpoint.
1
Enables the DMA request for the transmit endpoint.
Note:
3
FDT
RW
0
3 TX and 3 RX endpoints can be connected to the µDMA
module. If this bit is set for a particular endpoint, the DMAATX,
DMABTX, or DMACTX field in the USB DMA Select
(USBDMASEL) register must be programmed
correspondingly.
Force Data Toggle
Value Description
2
DMAMOD
RW
0
0
No effect.
1
Forces the endpoint DT bit to switch and the data packet to be
cleared from the FIFO, regardless of whether an ACK was
received. This bit can be used by interrupt transmit endpoints
that are used to communicate rate feedback for isochronous
endpoints.
DMA Request Mode
Value Description
0
An interrupt is generated after every DMA packet transfer.
1
An interrupt is generated only after the entire DMA transfer is
complete.
Note:
1:0
reserved
RO
0
This bit must not be cleared either before or in the same cycle
as the above DMAEN bit is cleared.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Tiva™ TM4C1237H6PZ Microcontroller
Register 100: USB Maximum Receive Data Endpoint 1 (USBRXMAXP1), offset
0x114
Register 101: USB Maximum Receive Data Endpoint 2 (USBRXMAXP2), offset
0x124
Register 102: USB Maximum Receive Data Endpoint 3 (USBRXMAXP3), offset
0x134
Register 103: USB Maximum Receive Data Endpoint 4 (USBRXMAXP4), offset
0x144
Register 104: USB Maximum Receive Data Endpoint 5 (USBRXMAXP5), offset
0x154
Register 105: USB Maximum Receive Data Endpoint 6 (USBRXMAXP6), offset
0x164
Register 106: USB Maximum Receive Data Endpoint 7 (USBRXMAXP7), offset
0x174
OTG A /
Host
OTG B /
Device
The USBRXMAXPn is a 16-bit register which defines the maximum amount of data that can be
transferred through the selected receive endpoint in a single operation.
Bits 10:0 define (in bytes) the maximum payload transmitted in a single transaction. The value set
can be up to 1024 bytes but is subject to the constraints placed by the USB Specification on packet
sizes for bulk, interrupt and isochronous transfers in full-speed operations.
The total amount of data represented by the value written to this register must not exceed the FIFO
size for the receive endpoint, and must not exceed half the FIFO size if double-buffering is required.
Note:
USBRXMAXPn must be set to an even number of bytes for proper interrupt generation in
µDMA Basic mode.
USB Maximum Receive Data Endpoint n (USBRXMAXPn)
Base 0x4005.0000
Offset 0x114
Type RW, reset 0x0000
15
14
RO
0
RO
0
13
12
11
10
9
8
7
6
RO
0
RO
0
RW
0
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
RO
0
5
4
3
2
1
0
RW
0
RW
0
RW
0
RW
0
RW
0
MAXLOAD
Bit/Field
Name
Type
Reset
15:11
reserved
RO
0x0
10:0
MAXLOAD
RW
0x000
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Maximum Payload
The maximum payload in bytes per transaction.
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Universal Serial Bus (USB) Controller
Register 107: USB Receive Control and Status Endpoint 1 Low (USBRXCSRL1),
offset 0x116
Register 108: USB Receive Control and Status Endpoint 2 Low (USBRXCSRL2),
offset 0x126
Register 109: USB Receive Control and Status Endpoint 3 Low (USBRXCSRL3),
offset 0x136
Register 110: USB Receive Control and Status Endpoint 4 Low (USBRXCSRL4),
offset 0x146
Register 111: USB Receive Control and Status Endpoint 5 Low (USBRXCSRL5),
offset 0x156
Register 112: USB Receive Control and Status Endpoint 6 Low (USBRXCSRL6),
offset 0x166
Register 113: USB Receive Control and Status Endpoint 7 Low (USBRXCSRL7),
offset 0x176
OTG A /
USBRXCSRLn is an 8-bit register that provides control and status bits for transfers through the
currently selected receive endpoint.
Host
OTG B /
Device
OTG A / Host Mode
USB Receive Control and Status Endpoint n Low (USBRXCSRLn)
7
CLRDT
Type
Reset
W1C
0
6
5
STALLED REQPKT
RW
0
4
3
2
1
0
FLUSH
DATAERR / NAKTO
Base 0x4005.0000
Offset 0x116
Type RW, reset 0x00
ERROR
FULL
RXRDY
RW
0
RW
0
RW
0
RO
0
RW
0
RW
0
Bit/Field
Name
Type
Reset
7
CLRDT
W1C
0
Description
Clear Data Toggle
Writing a 1 to this bit clears the DT bit in the USBRXCSRHn register.
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Tiva™ TM4C1237H6PZ Microcontroller
Bit/Field
Name
Type
Reset
6
STALLED
RW
0
Description
Endpoint Stalled
Value Description
0
A STALL handshake has not been received.
1
A STALL handshake has been received. The EPn bit in the
USBRXIS register is also set.
Software must clear this bit.
5
REQPKT
RW
0
Request Packet
Value Description
0
No request.
1
Requests an IN transaction.
This bit is cleared when RXRDY is set.
4
FLUSH
RW
0
Flush FIFO
Value Description
0
No effect.
1
Flushes the next packet to be read from the endpoint receive
FIFO. The FIFO pointer is reset and the RXRDY bit is cleared.
Note that if the FIFO is double-buffered, FLUSH may have to be set
twice to completely clear the FIFO.
Important:
3
DATAERR / NAKTO
RW
0
This bit should only be set when the RXRDY bit is set. At
other times, it may cause data to be corrupted.
Data Error / NAK Timeout
Value Description
0
Normal operation.
1
Isochronous endpoints only: Indicates that RXRDY is set and
the data packet has a CRC or bit-stuff error. This bit is cleared
when RXRDY is cleared.
Bulk endpoints only: Indicates that the receive endpoint is halted
following the receipt of NAK responses for longer than the time
set by the NAKLMT field in the USBRXINTERVALn register.
Software must clear this bit to allow the endpoint to continue.
2
ERROR
RW
0
Error
Value Description
0
No error.
1
Three attempts have been made to receive a packet and no
data packet has been received. The EPn bit in the USBRXIS
register is set in this situation.
Software must clear this bit.
Note:
This bit is only valid when the receive endpoint is operating
in Bulk or Interrupt mode. In Isochronous mode, it always
returns zero.
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Universal Serial Bus (USB) Controller
Bit/Field
Name
Type
Reset
1
FULL
RO
0
Description
FIFO Full
Value Description
0
RXRDY
RW
0
0
The receive FIFO is not full.
1
No more packets can be loaded into the receive FIFO.
Receive Packet Ready
Value Description
0
No data packet has been received.
1
A data packet has been received. The EPn bit in the USBRXIS
register is also set in this situation.
If the AUTOCLR bit in the USBRXCSRHn register is set, then the this bit
is automatically cleared when a packet of USBRXMAXPn bytes has
been unloaded from the receive FIFO. If the AUTOCLR bit is clear, or if
packets of less than the maximum packet size are unloaded, then
software must clear this bit manually when the packet has been unloaded
from the receive FIFO.
OTG B / Device Mode
USB Receive Control and Status Endpoint n Low (USBRXCSRLn)
Base 0x4005.0000
Offset 0x116
Type RW, reset 0x00
Type
Reset
7
6
5
CLRDT
STALLED
STALL
W1C
0
RW
0
RW
0
4
3
FLUSH DATAERR
RW
0
2
1
0
OVER
FULL
RXRDY
RW
0
RO
0
RW
0
RO
0
Bit/Field
Name
Type
Reset
7
CLRDT
W1C
0
Description
Clear Data Toggle
Writing a 1 to this bit clears the DT bit in the USBRXCSRHn register.
6
STALLED
RW
0
Endpoint Stalled
Value Description
0
A STALL handshake has not been transmitted.
1
A STALL handshake has been transmitted.
Software must clear this bit.
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Tiva™ TM4C1237H6PZ Microcontroller
Bit/Field
Name
Type
Reset
Description
5
STALL
RW
0
Send STALL
Value Description
0
No effect.
1
Issues a STALL handshake.
Software must clear this bit to terminate the STALL condition.
Note:
4
FLUSH
RW
0
This bit has no effect where the endpoint is being used for
isochronous transfers.
Flush FIFO
Value Description
0
No effect.
1
Flushes the next packet from the endpoint receive FIFO. The
FIFO pointer is reset and the RXRDY bit is cleared.
The CPU writes a 1 to this bit to flush the next packet to be read from
the endpoint receive FIFO. The FIFO pointer is reset and the RXRDY bit
is cleared. Note that if the FIFO is double-buffered, FLUSH may have
to be set twice to completely clear the FIFO.
Important:
3
DATAERR
RO
0
This bit should only be set when the RXRDY bit is set. At
other times, it may cause data to be corrupted.
Data Error
Value Description
0
Normal operation.
1
Indicates that RXRDY is set and the data packet has a CRC or
bit-stuff error.
This bit is cleared when RXRDY is cleared.
Note:
2
OVER
RW
0
This bit is only valid when the endpoint is operating in
Isochronous mode. In Bulk mode, it always returns zero.
Overrun
Value Description
0
No overrun error.
1
Indicates that an OUT packet cannot be loaded into the receive
FIFO.
Software must clear this bit.
Note:
1
FULL
RO
0
This bit is only valid when the endpoint is operating in
Isochronous mode. In Bulk mode, it always returns zero.
FIFO Full
Value Description
0
The receive FIFO is not full.
1
No more packets can be loaded into the receive FIFO.
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Universal Serial Bus (USB) Controller
Bit/Field
Name
Type
Reset
0
RXRDY
RW
0
Description
Receive Packet Ready
Value Description
0
No data packet has been received.
1
A data packet has been received. The EPn bit in the USBRXIS
register is also set in this situation.
If the AUTOCLR bit in the USBRXCSRHn register is set, then the this bit
is automatically cleared when a packet of USBRXMAXPn bytes has
been unloaded from the receive FIFO. If the AUTOCLR bit is clear, or if
packets of less than the maximum packet size are unloaded, then
software must clear this bit manually when the packet has been unloaded
from the receive FIFO.
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Register 114: USB Receive Control and Status Endpoint 1 High
(USBRXCSRH1), offset 0x117
Register 115: USB Receive Control and Status Endpoint 2 High
(USBRXCSRH2), offset 0x127
Register 116: USB Receive Control and Status Endpoint 3 High
(USBRXCSRH3), offset 0x137
Register 117: USB Receive Control and Status Endpoint 4 High
(USBRXCSRH4), offset 0x147
Register 118: USB Receive Control and Status Endpoint 5 High
(USBRXCSRH5), offset 0x157
Register 119: USB Receive Control and Status Endpoint 6 High
(USBRXCSRH6), offset 0x167
Register 120: USB Receive Control and Status Endpoint 7 High
(USBRXCSRH7), offset 0x177
OTG A /
USBRXCSRHn is an 8-bit register that provides additional control and status bits for transfers
through the currently selected receive endpoint.
Host
OTG B /
Device
OTG A / Host Mode
USB Receive Control and Status Endpoint n High (USBRXCSRHn)
Base 0x4005.0000
Offset 0x117
Type RW, reset 0x00
7
6
5
AUTOCL AUTORQ DMAEN
Type
Reset
RW
0
RW
0
RW
0
4
3
PIDERR DMAMOD
RO
0
RW
0
2
1
0
DTWE
DT
reserved
RO
0
RO
0
RO
0
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Universal Serial Bus (USB) Controller
Bit/Field
Name
Type
Reset
Description
7
AUTOCL
RW
0
Auto Clear
Value Description
6
AUTORQ
RW
0
0
No effect.
1
Enables the RXRDY bit to be automatically cleared when a packet
of USBRXMAXPn bytes has been unloaded from the receive
FIFO. When packets of less than the maximum packet size are
unloaded, RXRDY must be cleared manually. Care must be taken
when using µDMA to unload the receive FIFO as data is read
from the receive FIFO in 4 byte chunks regardless of the value
of the MAXLOAD field in the USBRXMAXPn register, see “DMA
Operation” on page 1104.
Auto Request
Value Description
0
No effect.
1
Enables the REQPKT bit to be automatically set when the RXRDY
bit is cleared.
Note:
5
DMAEN
RW
0
This bit is automatically cleared when a short packet is
received.
DMA Request Enable
Value Description
0
Disables the µDMA request for the receive endpoint.
1
Enables the µDMA request for the receive endpoint.
Note:
4
PIDERR
RO
0
3 TX and 3 RX endpoints can be connected to the µDMA
module. If this bit is set for a particular endpoint, the DMAARX,
DMABRX, or DMACRX field in the USB DMA Select
(USBDMASEL) register must be programmed
correspondingly.
PID Error
Value Description
0
No error.
1
Indicates a PID error in the received packet of an isochronous
transaction.
This bit is ignored in bulk or interrupt transactions.
3
DMAMOD
RW
0
DMA Request Mode
Value Description
0
An interrupt is generated after every µDMA packet transfer.
1
An interrupt is generated only after the entire µDMA transfer is
complete.
Note:
This bit must not be cleared either before or in the same cycle
as the above DMAEN bit is cleared.
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Tiva™ TM4C1237H6PZ Microcontroller
Bit/Field
Name
Type
Reset
2
DTWE
RO
0
Description
Data Toggle Write Enable
Value Description
0
The DT bit cannot be written.
1
Enables the current state of the receive endpoint data to be
written (see DT bit).
This bit is automatically cleared once the new value is written.
1
DT
RO
0
Data Toggle
When read, this bit indicates the current state of the receive data toggle.
If DTWE is High, this bit may be written with the required setting of the
data toggle. If DTWE is Low, any value written to this bit is ignored. Care
should be taken when writing to this bit as it should only be changed to
RESET the receive endpoint.
0
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
OTG B / Device Mode
USB Receive Control and Status Endpoint n High (USBRXCSRHn)
Type
Reset
7
6
5
4
3
AUTOCL
ISO
DMAEN
DISNYET / PIDERR
Base 0x4005.0000
Offset 0x117
Type RW, reset 0x00
2
DMAMOD
RW
0
RW
0
RW
0
RW
0
RW
0
1
0
reserved
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
7
AUTOCL
RW
0
Auto Clear
Value Description
0
No effect.
1
Enables the RXRDY bit to be automatically cleared when a packet
of USBRXMAXPn bytes has been unloaded from the receive
FIFO. When packets of less than the maximum packet size are
unloaded, RXRDY must be cleared manually. Care must be taken
when using µDMA to unload the receive FIFO as data is read
from the receive FIFO in 4 byte chunks regardless of the value
of the MAXLOAD field in the USBRXMAXPn register, see “DMA
Operation” on page 1104.
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Universal Serial Bus (USB) Controller
Bit/Field
Name
Type
Reset
6
ISO
RW
0
Description
Isochronous Transfers
Value Description
5
DMAEN
RW
0
0
Enables the receive endpoint for isochronous transfers.
1
Enables the receive endpoint for bulk/interrupt transfers.
DMA Request Enable
Value Description
0
Disables the µDMA request for the receive endpoint.
1
Enables the µDMA request for the receive endpoint.
Note:
4
DISNYET / PIDERR
RW
0
3 TX and 3 RX endpoints can be connected to the µDMA
module. If this bit is set for a particular endpoint, the DMAARX,
DMABRX, or DMACRX field in the USB DMA Select
(USBDMASEL) register must be programmed
correspondingly.
Disable NYET / PID Error
Value Description
0
No effect.
1
For bulk or interrupt transactions: Disables the sending of NYET
handshakes. When this bit is set, all successfully received
packets are acknowledged, including at the point at which the
FIFO becomes full.
For isochronous transactions: Indicates a PID error in the
received packet.
3
DMAMOD
RW
0
DMA Request Mode
Value Description
0
An interrupt is generated after every µDMA packet transfer.
1
An interrupt is generated only after the entire µDMA transfer is
complete.
Note:
2:0
reserved
RO
0x0
This bit must not be cleared either before or in the same cycle
as the above DMAEN bit is cleared.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Tiva™ TM4C1237H6PZ Microcontroller
Register 121: USB Receive Byte Count Endpoint 1 (USBRXCOUNT1), offset
0x118
Register 122: USB Receive Byte Count Endpoint 2 (USBRXCOUNT2), offset
0x128
Register 123: USB Receive Byte Count Endpoint 3 (USBRXCOUNT3), offset
0x138
Register 124: USB Receive Byte Count Endpoint 4 (USBRXCOUNT4), offset
0x148
Register 125: USB Receive Byte Count Endpoint 5 (USBRXCOUNT5), offset
0x158
Register 126: USB Receive Byte Count Endpoint 6 (USBRXCOUNT6), offset
0x168
Register 127: USB Receive Byte Count Endpoint 7 (USBRXCOUNT7), offset
0x178
OTG A /
Host
Note:
The value returned changes as the FIFO is unloaded and is only valid while the RXRDY bit
in the USBRXCSRLn register is set.
OTG B /
USBRXCOUNTn is a 16-bit read-only register that holds the number of data bytes in the packet
currently in line to be read from the receive FIFO. If the packet is transmitted as multiple bulk packets,
the number given is for the combined packet.
Device
USB Receive Byte Count Endpoint n (USBRXCOUNTn)
Base 0x4005.0000
Offset 0x118
Type RO, reset 0x0000
15
14
13
12
11
10
9
8
7
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
COUNT
Bit/Field
Name
Type
Reset
15:13
reserved
RO
0x0
12:0
COUNT
RO
0x000
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Receive Packet Count
Indicates the number of bytes in the receive packet.
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Universal Serial Bus (USB) Controller
Register 128: USB Host Transmit Configure Type Endpoint 1 (USBTXTYPE1),
offset 0x11A
Register 129: USB Host Transmit Configure Type Endpoint 2 (USBTXTYPE2),
offset 0x12A
Register 130: USB Host Transmit Configure Type Endpoint 3 (USBTXTYPE3),
offset 0x13A
Register 131: USB Host Transmit Configure Type Endpoint 4 (USBTXTYPE4),
offset 0x14A
Register 132: USB Host Transmit Configure Type Endpoint 5 (USBTXTYPE5),
offset 0x15A
Register 133: USB Host Transmit Configure Type Endpoint 6 (USBTXTYPE6),
offset 0x16A
Register 134: USB Host Transmit Configure Type Endpoint 7 (USBTXTYPE7),
offset 0x17A
OTG A /
Host
USBTXTYPEn is an 8-bit register that must be written with the endpoint number to be targeted by
the endpoint, the transaction protocol to use for the currently selected transmit endpoint, and its
operating speed.
USB Host Transmit Configure Type Endpoint n (USBTXTYPEn)
Base 0x4005.0000
Offset 0x11A
Type RW, reset 0x00
7
6
SPEED
Type
Reset
RW
0
RW
0
5
4
3
2
PROTO
RW
0
RW
0
1
0
RW
0
RW
0
TEP
RW
0
RW
0
Bit/Field
Name
Type
Reset
7:6
SPEED
RW
0x0
Description
Operating Speed
This bit field specifies the operating speed of the target Device:
Value Description
0x0
Default
The target is assumed to be using the same connection speed
as the USB controller.
0x1
Reserved
0x2
Full
0x3
Low
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Bit/Field
Name
Type
Reset
5:4
PROTO
RW
0x0
Description
Protocol
Software must configure this bit field to select the required protocol for
the transmit endpoint:
Value Description
3:0
TEP
RW
0x0
0x0
Control
0x1
Isochronous
0x2
Bulk
0x3
Interrupt
Target Endpoint Number
Software must configure this value to the endpoint number contained
in the transmit endpoint descriptor returned to the USB controller during
Device enumeration.
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Universal Serial Bus (USB) Controller
Register 135: USB Host Transmit Interval Endpoint 1 (USBTXINTERVAL1),
offset 0x11B
Register 136: USB Host Transmit Interval Endpoint 2 (USBTXINTERVAL2),
offset 0x12B
Register 137: USB Host Transmit Interval Endpoint 3 (USBTXINTERVAL3),
offset 0x13B
Register 138: USB Host Transmit Interval Endpoint 4 (USBTXINTERVAL4),
offset 0x14B
Register 139: USB Host Transmit Interval Endpoint 5 (USBTXINTERVAL5),
offset 0x15B
Register 140: USB Host Transmit Interval Endpoint 6 (USBTXINTERVAL6),
offset 0x16B
Register 141: USB Host Transmit Interval Endpoint 7 (USBTXINTERVAL7),
offset 0x17B
OTG A /
Host
USBTXINTERVALn is an 8-bit register that, for interrupt and isochronous transfers, defines the
polling interval for the currently selected transmit endpoint. For bulk endpoints, this register defines
the number of frames after which the endpoint should time out on receiving a stream of NAK
responses.
The USBTXINTERVALn register value defines a number of frames, as follows:
Transfer Type
Interrupt
Speed
Valid values (m)
Interpretation
Low-Speed or Full-Speed
0x01 – 0xFF
The polling interval is m frames.
Isochronous
Full-Speed
0x01 – 0x10
The polling interval is 2(m-1) frames/micorframes..
Bulk
Full-Speed
0x02 – 0x10
The NAK Limit is 2(m-1) frames/microframes. A
value of 0 or 1 disables the NAK timeout
function.
USB Host Transmit Interval Endpoint n (USBTXINTERVALn)
Base 0x4005.0000
Offset 0x11B
Type RW, reset 0x00
7
6
5
RW
0
RW
0
RW
0
4
3
2
1
0
RW
0
RW
0
RW
0
TXPOLL / NAKLMT
Type
Reset
RW
0
RW
0
Bit/Field
Name
Type
Reset
Description
7:0
TXPOLL / NAKLMT
RW
0x00
TX Polling / NAK Limit
The polling interval for interrupt/isochronous transfers; the NAK limit for
bulk transfers. See table above for valid entries; other values are
reserved.
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Tiva™ TM4C1237H6PZ Microcontroller
Register 142: USB Host Configure Receive Type Endpoint 1 (USBRXTYPE1),
offset 0x11C
Register 143: USB Host Configure Receive Type Endpoint 2 (USBRXTYPE2),
offset 0x12C
Register 144: USB Host Configure Receive Type Endpoint 3 (USBRXTYPE3),
offset 0x13C
Register 145: USB Host Configure Receive Type Endpoint 4 (USBRXTYPE4),
offset 0x14C
Register 146: USB Host Configure Receive Type Endpoint 5 (USBRXTYPE5),
offset 0x15C
Register 147: USB Host Configure Receive Type Endpoint 6 (USBRXTYPE6),
offset 0x16C
Register 148: USB Host Configure Receive Type Endpoint 7 (USBRXTYPE7),
offset 0x17C
OTG A /
Host
USBRXTYPEn is an 8-bit register that must be written with the endpoint number to be targeted by
the endpoint, the transaction protocol to use for the currently selected receive endpoint, and its
operating speed.
USB Host Configure Receive Type Endpoint n (USBRXTYPEn)
Base 0x4005.0000
Offset 0x11C
Type RW, reset 0x00
7
6
SPEED
Type
Reset
RW
0
RW
0
5
4
3
2
PROTO
RW
0
RW
0
1
0
RW
0
RW
0
TEP
RW
0
RW
0
Bit/Field
Name
Type
Reset
7:6
SPEED
RW
0x0
Description
Operating Speed
This bit field specifies the operating speed of the target Device:
Value Description
0x0
Default
The target is assumed to be using the same connection speed
as the USB controller.
0x1
Reserved
0x2
Full
0x3
Low
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Universal Serial Bus (USB) Controller
Bit/Field
Name
Type
Reset
5:4
PROTO
RW
0x0
Description
Protocol
Software must configure this bit field to select the required protocol for
the receive endpoint:
Value Description
3:0
TEP
RW
0x0
0x0
Control
0x1
Isochronous
0x2
Bulk
0x3
Interrupt
Target Endpoint Number
Software must set this value to the endpoint number contained in the
receive endpoint descriptor returned to the USB controller during Device
enumeration.
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Tiva™ TM4C1237H6PZ Microcontroller
Register 149: USB Host Receive Polling Interval Endpoint 1
(USBRXINTERVAL1), offset 0x11D
Register 150: USB Host Receive Polling Interval Endpoint 2
(USBRXINTERVAL2), offset 0x12D
Register 151: USB Host Receive Polling Interval Endpoint 3
(USBRXINTERVAL3), offset 0x13D
Register 152: USB Host Receive Polling Interval Endpoint 4
(USBRXINTERVAL4), offset 0x14D
Register 153: USB Host Receive Polling Interval Endpoint 5
(USBRXINTERVAL5), offset 0x15D
Register 154: USB Host Receive Polling Interval Endpoint 6
(USBRXINTERVAL6), offset 0x16D
Register 155: USB Host Receive Polling Interval Endpoint 7
(USBRXINTERVAL7), offset 0x17D
OTG A /
Host
USBRXINTERVALn is an 8-bit register that, for interrupt and isochronous transfers, defines the
polling interval for the currently selected receive endpoint. For bulk endpoints, this register defines
the number of frames after which the endpoint should time out on receiving a stream of NAK
responses.
The USBRXINTERVALn register value defines a number of frames, as follows:
Transfer Type
Interrupt
Speed
Valid values (m)
Interpretation
Low-Speed or Full-Speed
0x01 – 0xFF
The polling interval is m frames.
Isochronous
Full-Speed
0x01 – 0x10
The polling interval is 2(m-1) frames/microframes.
Bulk
Full-Speed
0x02 – 0x10
The NAK Limit is 2(m-1) frames/microframes. A
value of 0 or 1 disables the NAK timeout
function.
USB Host Receive Polling Interval Endpoint n (USBRXINTERVALn)
Base 0x4005.0000
Offset 0x11D
Type RW, reset 0x00
7
6
5
RW
0
RW
0
RW
0
4
3
2
1
0
RW
0
RW
0
RW
0
TXPOLL / NAKLMT
Type
Reset
RW
0
RW
0
Bit/Field
Name
Type
Reset
Description
7:0
TXPOLL / NAKLMT
RW
0x00
RX Polling / NAK Limit
The polling interval for interrupt/isochronous transfers; the NAK limit for
bulk transfers. See table above for valid entries; other values are
reserved.
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Universal Serial Bus (USB) Controller
Register 156: USB Request Packet Count in Block Transfer Endpoint 1
(USBRQPKTCOUNT1), offset 0x304
Register 157: USB Request Packet Count in Block Transfer Endpoint 2
(USBRQPKTCOUNT2), offset 0x308
Register 158: USB Request Packet Count in Block Transfer Endpoint 3
(USBRQPKTCOUNT3), offset 0x30C
Register 159: USB Request Packet Count in Block Transfer Endpoint 4
(USBRQPKTCOUNT4), offset 0x310
Register 160: USB Request Packet Count in Block Transfer Endpoint 5
(USBRQPKTCOUNT5), offset 0x314
Register 161: USB Request Packet Count in Block Transfer Endpoint 6
(USBRQPKTCOUNT6), offset 0x318
Register 162: USB Request Packet Count in Block Transfer Endpoint 7
(USBRQPKTCOUNT7), offset 0x31C
OTG A /
Host
This 16-bit read/write register is used in Host mode to specify the number of packets that are to be
transferred in a block transfer of one or more bulk packets to receive endpoint n. The USB controller
uses the value recorded in this register to determine the number of requests to issue where the
AUTORQ bit in the USBRXCSRHn register has been set. See “IN Transactions as a Host” on page 1100.
Note:
Multiple packets combined into a single bulk packet within the FIFO count as one packet.
USB Request Packet Count in Block Transfer Endpoint n (USBRQPKTCOUNTn)
Base 0x4005.0000
Offset 0x304
Type RW, reset 0x0000
15
14
13
12
11
10
9
8
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
7
6
5
4
3
2
1
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
COUNT
Type
Reset
Bit/Field
Name
Type
Reset
15:0
COUNT
RW
0x0000
Description
Block Transfer Packet Count
Sets the number of packets of the size defined by the MAXLOAD bit field
that are to be transferred in a block transfer.
Note:
This is only used in Host mode when AUTORQ is set. The bit
has no effect in Device mode or when AUTORQ is not set.
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Register 163: USB Receive Double Packet Buffer Disable
(USBRXDPKTBUFDIS), offset 0x340
OTG A /
Host
USBRXDPKTBUFDIS is a 16-bit register that indicates which of the receive endpoints have disabled
the double-packet buffer functionality (see the section called “Double-Packet Buffering” on page 1096).
USB Receive Double Packet Buffer Disable (USBRXDPKTBUFDIS)
OTG B /
Base 0x4005.0000
Offset 0x340
Type RW, reset 0x0000
Device
15
14
13
12
11
10
9
8
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
EP7
EP6
EP5
EP4
EP3
EP2
EP1
reserved
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RO
0
Bit/Field
Name
Type
Reset
Description
15:8
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7
EP7
RW
0
EP7 RX Double-Packet Buffer Disable
Value Description
6
EP6
RW
0
0
Disables double-packet buffering.
1
Enables double-packet buffering.
EP6 RX Double-Packet Buffer Disable
Same description as EP7.
5
EP5
RW
0
EP5 RX Double-Packet Buffer Disable
Same description as EP7.
4
EP4
RW
0
EP4 RX Double-Packet Buffer Disable
Same description as EP7.
3
EP3
RW
0
EP3 RX Double-Packet Buffer Disable
Same description as EP7.
2
EP2
RW
0
EP2 RX Double-Packet Buffer Disable
Same description as EP7.
1
EP1
RW
0
EP1 RX Double-Packet Buffer Disable
Same description as EP7.
0
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Universal Serial Bus (USB) Controller
Register 164: USB Transmit Double Packet Buffer Disable
(USBTXDPKTBUFDIS), offset 0x342
OTG A /
Host
USBTXDPKTBUFDIS is a 16-bit register that indicates which of the transmit endpoints have disabled
the double-packet buffer functionality (see the section called “Double-Packet Buffering” on page 1095).
USB Transmit Double Packet Buffer Disable (USBTXDPKTBUFDIS)
OTG B /
Base 0x4005.0000
Offset 0x342
Type RW, reset 0x0000
Device
15
14
13
12
11
10
9
8
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
EP7
EP6
EP5
EP4
EP3
EP2
EP1
reserved
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RO
0
Bit/Field
Name
Type
Reset
Description
15:8
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7
EP7
RW
0
EP7 TX Double-Packet Buffer Disable
Value Description
6
EP6
RW
0
0
Disables double-packet buffering.
1
Enables double-packet buffering.
EP6 TX Double-Packet Buffer Disable
Same description as EP7.
5
EP5
RW
0
EP5 TX Double-Packet Buffer Disable
Same description as EP7.
4
EP4
RW
0
EP4 TX Double-Packet Buffer Disable
Same description as EP7.
3
EP3
RW
0
EP3 TX Double-Packet Buffer Disable
Same description as EP7.
2
EP2
RW
0
EP2 TX Double-Packet Buffer Disable
Same description as EP7.
1
EP1
RW
0
EP1 TX Double-Packet Buffer Disable
Same description as EP7.
0
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Tiva™ TM4C1237H6PZ Microcontroller
Register 165: USB External Power Control (USBEPC), offset 0x400
OTG A /
Host
This 32-bit register specifies the function of the two-pin external power interface (USB0EPEN and
USB0PFLT). The assertion of the power fault input may generate an automatic action, as controlled
by the hardware configuration registers. The automatic action is necessary because the fault condition
may require a response faster than one provided by firmware.
OTG B /
USB External Power Control (USBEPC)
Device
Base 0x4005.0000
Offset 0x400
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
PFLTACT
Bit/Field
Name
Type
Reset
31:10
reserved
RO
0x0000.0
9:8
PFLTACT
RW
0x0
reserved PFLTAEN PFLTSEN PFLTEN
RW
0
RO
0
RW
0
RW
0
reserved EPENDE
RW
0
RO
0
RW
0
EPEN
RW
0
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Power Fault Action
This bit field specifies how the USB0EPEN signal is changed when
detecting a USB power fault.
Value Description
0x0
Unchanged
USB0EPEN is controlled by the combination of the EPEN and
EPENDE bits.
0x1
Tristate
USB0EPEN is undriven (tristate).
0x2
Low
USB0EPEN is driven Low.
0x3
High
USB0EPEN is driven High.
7
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
June 12, 2014
1187
Texas Instruments-Production Data
Universal Serial Bus (USB) Controller
Bit/Field
Name
Type
Reset
6
PFLTAEN
RW
0
Description
Power Fault Action Enable
This bit specifies whether a USB power fault triggers any automatic
corrective action regarding the driven state of the USB0EPEN signal.
Value Description
0
Disabled
USB0EPEN is controlled by the combination of the EPEN and
EPENDE bits.
1
Enabled
The USB0EPEN output is automatically changed to the state
specified by the PFLTACT field.
5
PFLTSEN
RW
0
Power Fault Sense
This bit specifies the logical sense of the USB0PFLT input signal that
indicates an error condition.
The complementary state is the inactive state.
Value Description
0
Low Fault
If USB0PFLT is driven Low, the power fault is signaled internally
(if enabled by the PFLTEN bit).
1
High Fault
If USB0PFLT is driven High, the power fault is signaled internally
(if enabled by the PFLTEN bit).
4
PFLTEN
RW
0
Power Fault Input Enable
This bit specifies whether the USB0PFLT input signal is used in internal
logic.
Value Description
0
Not Used
The USB0PFLT signal is ignored.
1
Used
The USB0PFLT signal is used internally.
3
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1188
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Bit/Field
Name
Type
Reset
2
EPENDE
RW
0
Description
EPEN Drive Enable
This bit specifies whether the USB0EPEN signal is driven or undriven
(tristate). When driven, the signal value is specified by the EPEN field.
When not driven, the EPEN field is ignored and the USB0EPEN signal is
placed in a high-impedance state.
Value Description
0
Not Driven
The USB0EPEN signal is high impedance.
1
Driven
The USB0EPEN signal is driven to the logical value specified by
the value of the EPEN field.
The USB0EPEN signal is undriven at reset because the sense of the
external power supply enable is unknown. By adding the high-impedance
state, system designers may bias the power supply enable to the
disabled state using a large resistor (100 kΩ) and later configure and
drive the output signal to enable the power supply.
1:0
EPEN
RW
0x0
External Power Supply Enable Configuration
This bit field specifies and controls the logical value driven on the
USB0EPEN signal.
Value Description
0x0
Power Enable Active Low
The USB0EPEN signal is driven Low if the EPENDE bit is set.
0x1
Power Enable Active High
The USB0EPEN signal is driven High if the EPENDE bit is set.
0x2
Power Enable High if VBUS Low
The USB0EPEN signal is driven High when the A device is not
recognized.
0x3
Power Enable High if VBUS High
The USB0EPEN signal is driven High when the A device is
recognized.
June 12, 2014
1189
Texas Instruments-Production Data
Universal Serial Bus (USB) Controller
Register 166: USB External Power Control Raw Interrupt Status (USBEPCRIS),
offset 0x404
OTG A /
This 32-bit register specifies the unmasked interrupt status of the two-pin external power interface.
USB External Power Control Raw Interrupt Status (USBEPCRIS)
Host
Base 0x4005.0000
Offset 0x404
Type RO, reset 0x0000.0000
OTG B /
31
30
29
28
27
26
25
Device
24
23
22
21
20
19
18
17
16
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:1
reserved
RO
0x0000.000
0
PF
RO
0
RO
0
RO
0
0
PF
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
USB Power Fault Interrupt Status
Value Description
0
An interrupt has not occurred.
1
A Power Fault status has been detected.
This bit is cleared by writing a 1 to the PF bit in the USBEPCISC register.
1190
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Register 167: USB External Power Control Interrupt Mask (USBEPCIM), offset
0x408
OTG A /
This 32-bit register specifies the interrupt mask of the two-pin external power interface.
USB External Power Control Interrupt Mask (USBEPCIM)
Host
Base 0x4005.0000
Offset 0x408
Type RW, reset 0x0000.0000
OTG B /
31
30
29
28
27
26
25
Device
24
23
22
21
20
19
18
17
16
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:1
reserved
RO
0x0000.000
0
PF
RW
0
RO
0
RO
0
PF
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
USB Power Fault Interrupt Mask
Value Description
0
A detected power fault does not affect the interrupt status.
1
The raw interrupt signal from a detected power fault is sent to
the interrupt controller.
June 12, 2014
1191
Texas Instruments-Production Data
Universal Serial Bus (USB) Controller
Register 168: USB External Power Control Interrupt Status and Clear
(USBEPCISC), offset 0x40C
OTG A /
Host
This 32-bit register specifies the masked interrupt status of the two-pin external power interface. It
also provides a method to clear the interrupt state.
USB External Power Control Interrupt Status and Clear (USBEPCISC)
OTG B /
Base 0x4005.0000
Offset 0x40C
Type RW, reset 0x0000.0000
Device
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:1
reserved
RO
0x0000.000
0
PF
RW1C
0
RO
0
RO
0
0
PF
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW1C
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
USB Power Fault Interrupt Status and Clear
Value Description
0
No interrupt has occurred or the interrupt is masked.
1
The PF bits in the USBEPCRIS and USBEPCIM registers are
set, providing an interrupt to the interrupt controller.
This bit is cleared by writing a 1. Clearing this bit also clears the PF bit
in the USBEPCRIS register.
1192
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Register 169: USB Device RESUME Raw Interrupt Status (USBDRRIS), offset
0x410
OTG A /
Host
The USBDRRIS 32-bit register is the raw interrupt status register. On a read, this register gives the
current raw status value of the corresponding interrupt prior to masking. A write has no effect.
USB Device RESUME Raw Interrupt Status (USBDRRIS)
OTG B /
Base 0x4005.0000
Offset 0x410
Type RO, reset 0x0000.0000
Device
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:1
reserved
RO
0x0000.000
0
RESUME
RO
0
RO
0
RO
0
0
RESUME
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
RESUME Interrupt Status
Value Description
0
An interrupt has not occurred.
1
A RESUME status has been detected.
This bit is cleared by writing a 1 to the RESUME bit in the USBDRISC
register.
June 12, 2014
1193
Texas Instruments-Production Data
Universal Serial Bus (USB) Controller
Register 170: USB Device RESUME Interrupt Mask (USBDRIM), offset 0x414
OTG A /
Host
The USBDRIM 32-bit register is the masked interrupt status register. On a read, this register gives
the current value of the mask on the corresponding interrupt. Setting a bit sets the mask, preventing
the interrupt from being signaled to the interrupt controller. Clearing a bit clears the corresponding
mask, enabling the interrupt to be sent to the interrupt controller.
OTG B /
USB Device RESUME Interrupt Mask (USBDRIM)
Device
Base 0x4005.0000
Offset 0x414
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
RESUME
RW
0
Bit/Field
Name
Type
Reset
Description
31:1
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
RESUME
RW
0
RESUME Interrupt Mask
Value Description
0
A detected RESUME does not affect the interrupt status.
1
The raw interrupt signal from a detected RESUME is sent to
the interrupt controller. This bit should only be set when a
SUSPEND has been detected (the SUSPEND bit in the USBIS
register is set).
1194
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Register 171: USB Device RESUME Interrupt Status and Clear (USBDRISC),
offset 0x418
OTG A /
Host
The USBDRISC 32-bit register is the interrupt clear register. On a write of 1, the corresponding
interrupt is cleared. A write of 0 has no effect.
USB Device RESUME Interrupt Status and Clear (USBDRISC)
OTG B /
Base 0x4005.0000
Offset 0x418
Type W1C, reset 0x0000.0000
Device
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:1
reserved
RO
0x0000.000
0
RESUME
RW1C
0
RO
0
RO
0
0
RESUME
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW1C
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
RESUME Interrupt Status and Clear
Value Description
0
No interrupt has occurred or the interrupt is masked.
1
The RESUME bits in the USBDRRIS and USBDRCIM registers
are set, providing an interrupt to the interrupt controller.
This bit is cleared by writing a 1. Clearing this bit also clears the RESUME
bit in the USBDRCRIS register.
June 12, 2014
1195
Texas Instruments-Production Data
Universal Serial Bus (USB) Controller
Register 172: USB General-Purpose Control and Status (USBGPCS), offset
0x41C
OTG A /
USBGPCS provides the state of the internal ID signal.
Note:
Host
OTG B /
Device
When used in OTG mode, USB0VBUS and USB0ID do not require any configuration as they
are dedicated pins for the USB controller and directly connect to the USB connector's VBUS
and ID signals. If the USB controller is used as either a dedicated Host or Device, the
DEVMODOTG and DEVMOD bits in the USB General-Purpose Control and Status
(USBGPCS) register can be used to connect the USB0VBUS and USB0ID inputs to fixed
levels internally, freeing the PB0 and PB1 pins for GPIO use. For proper self-powered Device
operation, the VBUS value must still be monitored to assure that if the Host removes VBUS,
the self-powered Device disables the D+/D- pull-up resistors. This function can be
accomplished by connecting a standard GPIO to VBUS.
The termination resistors for the USB PHY have been added internally, and thus there is
no need for external resistors. For a device, there is a 1.5 KOhm pull-up on the D+ and for
a host there are 15 KOhm pull-downs on both D+ and D-.
USB General-Purpose Control and Status (USBGPCS)
Base 0x4005.0000
Offset 0x41C
Type RW, reset 0x0000.0003
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:2
reserved
RO
0x0000.000
1
DEVMODOTG
RW
1
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
1
0
DEVMODOTG
DEVMOD
RW
1
RW
1
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Enable Device Mode
This bit enables the DEVMOD bit to control the state of the internal ID
signal in OTG mode.
Value Description
0
DEVMOD
RW
1
0
The mode is specified by the state of the internal ID signal.
1
This bit enables the DEVMOD bit to control the internal ID signal.
Device Mode
This bit specifies the state of the internal ID signal in Host mode and in
OTG mode when the DEVMODOTG bit is set.
In Device mode this bit is ignored (assumed set).
Value Description
0
Host mode
1
Device mode
1196
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Register 173: USB VBUS Droop Control (USBVDC), offset 0x430
OTG A /
Host
This 32-bit register enables a controlled masking of VBUS to compensate for any in-rush current
by a Device that is connected to the Host controller. The in-rush current can cause VBUS to droop,
causing the USB controller's behavior to be unexpected. The USB Host controller allows VBUS to
fall lower than the VBUS Valid level (4.75 V) but not below AValid (2.0 V) for 65 microseconds
without signaling a VBUSERR interrupt in the controller. Without this, any glitch on VBUS would force
the USB Host controller to remove power from VBUS and then re-enumerate the Device.
USB VBUS Droop Control (USBVDC)
Base 0x4005.0000
Offset 0x430
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:1
reserved
RO
0x0000.000
0
VBDEN
RW
0
RO
0
VBDEN
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
VBUS Droop Enable
Value Description
0
No effect.
1
Any changes from VBUSVALID are masked when VBUS goes
below 4.75 V but not lower than 2.0 V for 65 microseconds.
During this time, the VBUS state indicates VBUSVALID.
June 12, 2014
1197
Texas Instruments-Production Data
Universal Serial Bus (USB) Controller
Register 174: USB VBUS Droop Control Raw Interrupt Status (USBVDCRIS),
offset 0x434
OTG A /
Host
This 32-bit register specifies the unmasked interrupt status of the VBUS droop limit of 65
microseconds.
USB VBUS Droop Control Raw Interrupt Status (USBVDCRIS)
Base 0x4005.0000
Offset 0x434
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:1
reserved
RO
0x0000.000
0
VD
RO
0
RO
0
0
VD
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
VBUS Droop Raw Interrupt Status
Value Description
0
An interrupt has not occurred.
1
A VBUS droop lasting for 65 microseconds has been detected.
This bit is cleared by writing a 1 to the VD bit in the USBVDCISC register.
1198
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Register 175: USB VBUS Droop Control Interrupt Mask (USBVDCIM), offset
0x438
OTG A /
This 32-bit register specifies the interrupt mask of the VBUS droop.
USB VBUS Droop Control Interrupt Mask (USBVDCIM)
Host
Base 0x4005.0000
Offset 0x438
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:1
reserved
RO
0x0000.000
0
VD
RW
0
RO
0
0
VD
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
VBUS Droop Interrupt Mask
Value Description
0
A detected VBUS droop does not affect the interrupt status.
1
The raw interrupt signal from a detected VBUS droop is sent to
the interrupt controller.
June 12, 2014
1199
Texas Instruments-Production Data
Universal Serial Bus (USB) Controller
Register 176: USB VBUS Droop Control Interrupt Status and Clear
(USBVDCISC), offset 0x43C
OTG A /
Host
This 32-bit register specifies the masked interrupt status of the VBUS droop and provides a method
to clear the interrupt state.
USB VBUS Droop Control Interrupt Status and Clear (USBVDCISC)
Base 0x4005.0000
Offset 0x43C
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:1
reserved
RO
0x0000.000
0
VD
RW1C
0
RO
0
0
VD
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW1C
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
VBUS Droop Interrupt Status and Clear
Value Description
0
No interrupt has occurred or the interrupt is masked.
1
The VD bits in the USBVDCRIS and USBVDCIM registers are
set, providing an interrupt to the interrupt controller.
This bit is cleared by writing a 1. Clearing this bit also clears the VD bit
in the USBVDCRIS register.
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Tiva™ TM4C1237H6PZ Microcontroller
Register 177: USB ID Valid Detect Raw Interrupt Status (USBIDVRIS), offset
0x444
This 32-bit register specifies whether the unmasked interrupt status of the ID value is valid.
OTG
USB ID Valid Detect Raw Interrupt Status (USBIDVRIS)
Base 0x4005.0000
Offset 0x444
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:1
reserved
RO
0x0000.000
0
ID
RO
0
RO
0
0
ID
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
ID Valid Detect Raw Interrupt Status
Value Description
0
An interrupt has not occurred.
1
A valid ID has been detected.
This bit is cleared by writing a 1 to the ID bit in the USBIDVISC register.
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Universal Serial Bus (USB) Controller
Register 178: USB ID Valid Detect Interrupt Mask (USBIDVIM), offset 0x448
This 32-bit register specifies the interrupt mask of the ID valid detection.
OTG
USB ID Valid Detect Interrupt Mask (USBIDVIM)
Base 0x4005.0000
Offset 0x448
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:1
reserved
RO
0x0000.000
0
ID
RW
0
RO
0
ID
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
ID Valid Detect Interrupt Mask
Value Description
0
A detected ID valid does not affect the interrupt status.
1
The raw interrupt signal from a detected ID valid is sent to the
interrupt controller.
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Tiva™ TM4C1237H6PZ Microcontroller
Register 179: USB ID Valid Detect Interrupt Status and Clear (USBIDVISC),
offset 0x44C
This 32-bit register specifies the masked interrupt status of the ID valid detect. It also provides a
method to clear the interrupt state.
OTG
USB ID Valid Detect Interrupt Status and Clear (USBIDVISC)
Base 0x4005.0000
Offset 0x44C
Type RW1C, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:1
reserved
RO
0x0000.000
0
ID
RW1C
0
RO
0
0
ID
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW1C
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
ID Valid Detect Interrupt Status and Clear
Value Description
0
No interrupt has occurred or the interrupt is masked.
1
The ID bits in the USBIDVRIS and USBIDVIM registers are
set, providing an interrupt to the interrupt controller.
This bit is cleared by writing a 1. Clearing this bit also clears the ID bit
in the USBIDVRIS register.
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Universal Serial Bus (USB) Controller
Register 180: USB DMA Select (USBDMASEL), offset 0x450
OTG A /
Host
OTG B /
This 32-bit register specifies which endpoints are mapped to the 6 allocated µDMA channels, see
Table 9-1 on page 572 for more information on channel assignments.
USB DMA Select (USBDMASEL)
Base 0x4005.0000
Offset 0x450
Type RW, reset 0x0033.2211
Device
31
30
29
28
RO
0
RO
0
RO
0
RO
0
15
14
13
RW
0
RW
0
27
26
25
24
23
22
RO
0
RO
0
RO
0
RO
0
RW
0
RW
0
12
11
10
9
8
7
6
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
RW
1
20
19
18
RW
1
RW
1
RW
0
RW
0
RW
1
RW
1
5
4
3
2
1
0
RW
1
RW
0
RW
0
DMACTX
DMABTX
Type
Reset
21
DMABRX
RW
1
16
DMACRX
DMAATX
RW
0
17
DMAARX
RW
0
RW
1
Bit/Field
Name
Type
Reset
Description
31:24
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
23:20
DMACTX
RW
0x3
DMA C TX Select
Specifies the TX mapping of the third USB endpoint on µDMA channel
5 (primary assignment).
Value
Description
0x0
reserved
0x1
Endpoint 1 TX
0x2
Endpoint 2 TX
0x3
Endpoint 3 TX
0x4
Endpoint 4 TX
0x5
Endpoint 5 TX
0x6
Endpoint 6 TX
0x7
Endpoint 7 TX
0x8 - 0xF reserved
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Tiva™ TM4C1237H6PZ Microcontroller
Bit/Field
Name
Type
Reset
19:16
DMACRX
RW
0x3
Description
DMA C RX Select
Specifies the RX and TX mapping of the third USB endpoint on µDMA
channel 4 (primary assignment).
Value
Description
0x0
reserved
0x1
Endpoint 1 RX
0x2
Endpoint 2 RX
0x3
Endpoint 3 RX
0x4
Endpoint 4 RX
0x5
Endpoint 5 RX
0x6
Endpoint 6 RX
0x7
Endpoint 7 RX
0x8 - 0xF reserved
15:12
DMABTX
RW
0x2
DMA B TX Select
Specifies the TX mapping of the second USB endpoint on µDMA channel
3 (primary assignment).
Same bit definitions as the DMACTX field.
11:8
DMABRX
RW
0x2
DMA B RX Select
Specifies the RX mapping of the second USB endpoint on µDMA channel
2 (primary assignment).
Same bit definitions as the DMACRX field.
7:4
DMAATX
RW
0x1
DMA A TX Select
Specifies the TX mapping of the first USB endpoint on µDMA channel
1 (primary assignment).
Same bit definitions as the DMACTX field.
3:0
DMAARX
RW
0x1
DMA A RX Select
Specifies the RX mapping of the first USB endpoint on µDMA channel
0 (primary assignment).
Same bit definitions as the DMACRX field.
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Universal Serial Bus (USB) Controller
Register 181: USB Peripheral Properties (USBPP), offset 0xFC0
The USBPP register provides information regarding the properties of the USB module.
USB Peripheral Properties (USBPP)
Base 0x4005.0000
Offset 0xFC0
Type RO, reset 0x0000.10D0
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
1
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
reserved
PHY
RO
0
RO
1
RO
0
RO
1
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
ECNT
Type
Reset
USB
RO
1
TYPE
Bit/Field
Name
Type
Reset
Description
31:16
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:8
ECNT
RO
0x10
Endpoint Count
This field indicates the hex value for the number of endpoints provided.
7:6
USB
RO
0x3
USB Capability
Value Description
0x0
NA
USB is not present.
0x1
DEVICE
Device Only
0x2
HOST
Device or Host
0x3
OTG
Device, Host, or OTG
5
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
4
PHY
RO
0x1
PHY Present
Value Description
3:0
TYPE
RO
0x0
0
A PHY is not integrated with the USB MAC.
1
A PHY is integrated with the USB MAC.
Controller Type
Value
Description
0x0
The first-generation USB controller.
0x1 - 0xF Reserved
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Tiva™ TM4C1237H6PZ Microcontroller
19
Analog Comparators
An analog comparator is a peripheral that compares two analog voltages and provides a logical
output that signals the comparison result.
Note:
Not all comparators have the option to drive an output pin. See “Signal
Description” on page 1208 for more information.
The comparator can provide its output to a device pin, acting as a replacement for an analog
comparator on the board. In addition, the comparator can signal the application via interrupts or
trigger the start of a sample sequence in the ADC. The interrupt generation and ADC triggering logic
is separate and independent. This flexibility means, for example, that an interrupt can be generated
on a rising edge and the ADC triggered on a falling edge.
The TM4C1237H6PZ microcontroller provides three independent integrated analog comparators
with the following functions:
■ Compare external pin input to external pin input or to internal programmable voltage reference
■ Compare a test voltage against any one of the following voltages:
– An individual external reference voltage
– A shared single external reference voltage
– A shared internal reference voltage
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Analog Comparators
19.1
Block Diagram
Figure 19-1. Analog Comparator Module Block Diagram
C2-
-ve input
C2+
+ve input
Comparator 2
output
+ve input (alternate)
ACCTL2
trigger
ACSTAT2
C2o
trigger
interrupt
reference input
C1-
-ve input
C1+
+ve input
Comparator 1
output
C1o
+ve input (alternate)
ACCTL1
trigger
trigger
ACSTAT1
interrupt
reference input
C0-
-ve input
C0+
+ve input
Comparator 0
output
C0o
+ve input (alternate)
ACCTL0
ACSTAT0
trigger
trigger
interrupt
reference input
Voltage
Ref
Interrupt Control
ACRIS
Internal
Bus
Interrupt
ACREFCTL
ACMIS
ACINTEN
Module
Status
ACMPPP
Note:
19.2
This block diagram depicts the maximum number of analog comparators and comparator outputs
for the family of microcontrollers; the number for this specific device may vary. See page 1221 for
what is included on this device.
Signal Description
The following table lists the external signals of the Analog Comparators and describes the function
of each. The Analog Comparator output signals are alternate functions for some GPIO signals and
default to be GPIO signals at reset. The column in the table below titled "Pin Mux/Pin Assignment"
lists the possible GPIO pin placements for the Analog Comparator signals. The AFSEL bit in the
GPIO Alternate Function Select (GPIOAFSEL) register (page 659) should be set to choose the
Analog Comparator function. The number in parentheses is the encoding that must be programmed
into the PMCn field in the GPIO Port Control (GPIOPCTL) register (page 677) to assign the Analog
Comparator signal to the specified GPIO port pin. The positive and negative input signals are
configured by clearing the DEN bit in the GPIO Digital Enable (GPIODEN) register. For more
information on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 634.
Table 19-1. Analog Comparators Signals (100LQFP)
Pin Name
C0+
Pin Number Pin Mux / Pin
Assignment
23
PC6
a
Pin Type
Buffer Type
I
Analog
Description
Analog comparator 0 positive input.
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Tiva™ TM4C1237H6PZ Microcontroller
Table 19-1. Analog Comparators Signals (100LQFP) (continued)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Analog
Description
C0-
22
PC7
I
Analog comparator 0 negative input.
C0o
40
PF0 (9)
O
TTL
C1+
24
PC5
I
Analog
Analog comparator 1 positive input.
C1-
25
PC4
I
Analog
Analog comparator 1 negative input.
C1o
41
PF1 (9)
O
TTL
C2+
87
PG6
I
Analog
Analog comparator 2 positive input.
C2-
88
PG7
I
Analog
Analog comparator 2 negative input.
C2o
42
PF2 (9)
O
TTL
Analog comparator 0 output.
Analog comparator 1 output.
Analog comparator 2 output.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
19.3
Functional Description
The comparator compares the VIN- and VIN+ inputs to produce an output, VOUT.
VIN- < VIN+, VOUT = 1
VIN- > VIN+, VOUT = 0
As shown in Figure 19-2 on page 1209, the input source for VIN- is an external input, Cn-, where n
is the analog comparator number. In addition to an external input, Cn+, input sources for VIN+ can
be the C0+ or an internal reference, VIREF.
Figure 19-2. Structure of Comparator Unit
-ve input
reference input
output
CINV
1
IntGen
2
TrigGen
ACCTL
ACSTAT
trigger
interrupt
+ve input (alternate)
0
internal
bus
+ve input
A comparator is configured through two status/control registers, Analog Comparator Control
(ACCTL) and Analog Comparator Status (ACSTAT). The internal reference is configured through
one control register, Analog Comparator Reference Voltage Control (ACREFCTL). Interrupt
status and control are configured through three registers, Analog Comparator Masked Interrupt
Status (ACMIS), Analog Comparator Raw Interrupt Status (ACRIS), and Analog Comparator
Interrupt Enable (ACINTEN).
Typically, the comparator output is used internally to generate an interrupt as controlled by the ISEN
bit in the ACCTL register. The output may also be used to drive one of the external pins (Cno), or
generate an analog-to-digital converter (ADC) trigger.
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Analog Comparators
Important: The ASRCP bits in the ACCTL register must be set before using the analog comparators.
19.3.1
Internal Reference Programming
The structure of the internal reference is shown in Figure 19-3 on page 1210. The internal reference
is controlled by a single configuration register (ACREFCTL).
Figure 19-3. Comparator Internal Reference Structure
N*R
N*R
0xF
0xE
0x1
0x0
Decoder
Note:
internal
reference
VIREF
In the figure above, N*R represents a multiple of the R value that produces the results specified
in Table 19-2 on page 1210.
The internal reference can be programmed in one of two modes (low range or high range) depending
on the RNG bit in the ACREFCTL register. When RNG is clear, the internal reference is in high-range
mode, and when RNG is set the internal reference is in low-range mode.
In each range, the internal reference, VIREF, has 16 preprogrammed thresholds or step values. The
threshold to be used to compare the external input voltage against is selected using the VREF field
in the ACREFCTL register.
In the high-range mode, the VIREF threshold voltages start at the ideal high-range starting voltage
of VDDA/4.2 and increase in ideal constant voltage steps of VDDA/29.4.
In the low-range mode, the VIREF threshold voltages start at 0 V and increase in ideal constant
voltage steps of VDDA/22.12. The ideal VIREF step voltages for each mode and their dependence
on the RNG and VREF fields are summarized in Table 19-2.
Table 19-2. Internal Reference Voltage and ACREFCTL Field Values
ACREFCTL Register
EN Bit Value
EN=0
RNG Bit Value
RNG=X
Output Reference Voltage Based on VREF Field Value
0 V (GND) for any value of VREF. It is recommended that RNG=1 and VREF=0 to
minimize noise on the reference ground.
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Tiva™ TM4C1237H6PZ Microcontroller
Table 19-2. Internal Reference Voltage and ACREFCTL Field Values (continued)
ACREFCTL Register
EN Bit Value
RNG Bit Value
RNG=0
Output Reference Voltage Based on VREF Field Value
VIREF High Range: 16 voltage threshold values indexed by VREF = 0x0 .. 0xF
Ideal starting voltage (VREF=0): VDDA / 4.2
Ideal step size: VDDA/ 29.4
Ideal VIREF threshold values: VIREF (VREF) = VDDA / 4.2 + VREF * (VDDA/ 29.4), for
VREF = 0x0 .. 0xF
For minimum and maximum VIREF threshold values, see Table 19-3 on page 1211.
EN=1
RNG=1
VIREF Low Range: 16 voltage threshold values indexed by VREF = 0x0 .. 0xF
Ideal starting voltage (VREF=0): 0 V
Ideal step size: VDDA/ 22.12
Ideal VIREF threshold values: VIREF (VREF) = VREF * (VDDA/ 22.12), for VREF = 0x0 ..
0xF
For minimum and maximum VIREF threshold values, see Table 19-4 on page 1212.
Note that the values shown in Table 19-2 are the ideal values of the VIREF thresholds. These values
actually vary between minimum and maximum values for each threshold step, depending on process
and temperature. The minimum and maximum values for each step are given by:
■ VIREF(VREF) [Min] = Ideal VIREF(VREF) – (Ideal Step size – 2 mV) / 2
■ VIREF(VREF) [Max] = Ideal VIREF(VREF) + (Ideal Step size – 2 mV) / 2
Examples of minimum and maximum VIREF values for VDDA = 3.3V for high and low ranges, are
shown inTable 19-3 and Table 19-4. Note that these examples are only valid for VDDA = 3.3V; values
scale up and down with VDDA.
Table 19-3. Analog Comparator Voltage Reference Characteristics, VDDA = 3.3V, EN= 1, and
RNG = 0
VREF Value
VIREF Min
Ideal VIREF
VIREF Max
Unit
0x0
0.731
0.786
0.841
V
0x1
0.843
0.898
0.953
V
0x2
0.955
1.010
1.065
V
0x3
1.067
1.122
1.178
V
0x4
1.180
1.235
1.290
V
0x5
1.292
1.347
1.402
V
0x6
1.404
1.459
1.514
V
0x7
1.516
1.571
1.627
V
0x8
1.629
1.684
1.739
V
0x9
1.741
1.796
1.851
V
0xA
1.853
1.908
1.963
V
0xB
1.965
2.020
2.076
V
0xC
2.078
2.133
2.188
V
0xD
2.190
2.245
2.300
V
0xE
2.302
2.357
2.412
V
0xF
2.414
2.469
2.525
V
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Analog Comparators
Table 19-4. Analog Comparator Voltage Reference Characteristics, VDDA = 3.3V, EN= 1, and
RNG = 1
19.4
VREF Value
VIREF Min
Ideal VIREF
VIREF Max
Unit
0x0
0.000
0.000
0.074
V
0x1
0.076
0.149
0.223
V
0x2
0.225
0.298
0.372
V
0x3
0.374
0.448
0.521
V
0x4
0.523
0.597
0.670
V
0x5
0.672
0.746
0.820
V
0x6
0.822
0.895
0.969
V
0x7
0.971
1.044
1.118
V
0x8
1.120
1.193
1.267
V
0x9
1.269
1.343
1.416
V
0xA
1.418
1.492
1.565
V
0xB
1.567
1.641
1.715
V
0xC
1.717
1.790
1.864
V
0xD
1.866
1.939
2.013
V
0xE
2.015
2.089
2.162
V
0xF
2.164
2.238
2.311
V
Initialization and Configuration
The following example shows how to configure an analog comparator to read back its output value
from an internal register.
1. Enable the analog comparator clock by writing a value of 0x0000.0001 to the RCGCACMP
register in the System Control module (see page 345).
2. Enable the clock to the appropriate GPIO modules via the RCGCGPIO register (see page 331).
To find out which GPIO ports to enable, refer to Table 21-5 on page 1249.
3. In the GPIO module, enable the GPIO port/pin associated with the input signals as GPIO inputs.
To determine which GPIO to configure, see Table 21-4 on page 1242.
4. Configure the PMCn fields in the GPIOPCTL register to assign the analog comparator output
signals to the appropriate pins (see page 677 and Table 21-5 on page 1249).
5. Configure the internal voltage reference to 1.65 V by writing the ACREFCTL register with the
value 0x0000.030C.
6. Configure the comparator to use the internal voltage reference and to not invert the output by
writing the ACCTLn register with the value of 0x0000.040C.
7. Delay for 10 µs.
8. Read the comparator output value by reading the ACSTATn register's OVAL value.
Change the level of the comparator negative input signal C- to see the OVAL value change.
1212
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19.5
Register Map
Table 19-5 on page 1213 lists the comparator registers. The offset listed is a hexadecimal increment
to the register's address, relative to the Analog Comparator base address of 0x4003.C000. Note
that the analog comparator clock must be enabled before the registers can be programmed (see
page 345). There must be a delay of 3 system clocks after the analog comparator module clock is
enabled before any analog comparator module registers are accessed.
Table 19-5. Analog Comparators Register Map
Description
See
page
0x0000.0000
Analog Comparator Masked Interrupt Status
1214
RO
0x0000.0000
Analog Comparator Raw Interrupt Status
1215
ACINTEN
RW
0x0000.0000
Analog Comparator Interrupt Enable
1216
0x010
ACREFCTL
RW
0x0000.0000
Analog Comparator Reference Voltage Control
1217
0x020
ACSTAT0
RO
0x0000.0000
Analog Comparator Status 0
1218
0x024
ACCTL0
RW
0x0000.0000
Analog Comparator Control 0
1219
0x040
ACSTAT1
RO
0x0000.0000
Analog Comparator Status 1
1218
0x044
ACCTL1
RW
0x0000.0000
Analog Comparator Control 1
1219
0x060
ACSTAT2
RO
0x0000.0000
Analog Comparator Status 2
1218
0x064
ACCTL2
RW
0x0000.0000
Analog Comparator Control 2
1219
0xFC0
ACMPPP
RO
0x0007.0007
Analog Comparator Peripheral Properties
1221
Offset
Name
Type
Reset
0x000
ACMIS
RW1C
0x004
ACRIS
0x008
19.6
Register Descriptions
The remainder of this section lists and describes the Analog Comparator registers, in numerical
order by address offset.
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Analog Comparators
Register 1: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x000
This register provides a summary of the interrupt status (masked) of the comparators.
Analog Comparator Masked Interrupt Status (ACMIS)
Base 0x4003.C000
Offset 0x000
Type RW1C, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
IN2
IN1
IN0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW1C
0
RW1C
0
RW1C
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
Bit/Field
Name
Type
Reset
31:3
reserved
RO
0x0000.000
2
IN2
RW1C
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Comparator 2 Masked Interrupt Status
Value Description
0
No interrupt has occurred or the interrupt is masked.
1
The IN2 bits in the ACRIS register and the ACINTEN registers
are set, providing an interrupt to the interrupt controller.
This bit is cleared by writing a 1. Clearing this bit also clears the IN2 bit
in the ACRIS register.
1
IN1
RW1C
0
Comparator 1 Masked Interrupt Status
Value Description
0
No interrupt has occurred or the interrupt is masked.
1
The IN1 bits in the ACRIS register and the ACINTEN registers
are set, providing an interrupt to the interrupt controller.
This bit is cleared by writing a 1. Clearing this bit also clears the IN1 bit
in the ACRIS register.
0
IN0
RW1C
0
Comparator 0 Masked Interrupt Status
Value Description
0
No interrupt has occurred or the interrupt is masked.
1
The IN0 bits in the ACRIS register and the ACINTEN registers
are set, providing an interrupt to the interrupt controller.
This bit is cleared by writing a 1. Clearing this bit also clears the IN0 bit
in the ACRIS register.
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Tiva™ TM4C1237H6PZ Microcontroller
Register 2: Analog Comparator Raw Interrupt Status (ACRIS), offset 0x004
This register provides a summary of the interrupt status (raw) of the comparators. The bits in this
register must be enabled to generate interrupts using the ACINTEN register.
Analog Comparator Raw Interrupt Status (ACRIS)
Base 0x4003.C000
Offset 0x004
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
IN2
IN1
IN0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
Bit/Field
Name
Type
Reset
31:3
reserved
RO
0x0000.000
2
IN2
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Comparator 2 Interrupt Status
Value Description
0
An interrupt has not occurred.
1
Comparator 2 has generated an interrupt for an event as
configured by the ISEN bit in the ACCTL2 register.
This bit is cleared by writing a 1 to the IN2 bit in the ACMIS register.
1
IN1
RO
0
Comparator 1 Interrupt Status
Value Description
0
An interrupt has not occurred.
1
Comparator 1 has generated an interruptfor an event as
configured by the ISEN bit in the ACCTL1 register.
This bit is cleared by writing a 1 to the IN1 bit in the ACMIS register.
0
IN0
RO
0
Comparator 0 Interrupt Status
Value Description
0
An interrupt has not occurred.
1
Comparator 0 has generated an interrupt for an event as
configured by the ISEN bit in the ACCTL0 register.
This bit is cleared by writing a 1 to the IN0 bit in the ACMIS register.
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Analog Comparators
Register 3: Analog Comparator Interrupt Enable (ACINTEN), offset 0x008
This register provides the interrupt enable for the comparators.
Analog Comparator Interrupt Enable (ACINTEN)
Base 0x4003.C000
Offset 0x008
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
IN2
IN1
IN0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
RW
0
RW
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
Bit/Field
Name
Type
Reset
Description
31:3
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2
IN2
RW
0
Comparator 2 Interrupt Enable
Value Description
1
IN1
RW
0
0
A comparator 2 interrupt does not affect the interrupt status.
1
The raw interrupt signal comparator 2 is sent to the interrupt
controller.
Comparator 1 Interrupt Enable
Value Description
0
IN0
RW
0
0
A comparator 1 interrupt does not affect the interrupt status.
1
The raw interrupt signal comparator 1 is sent to the interrupt
controller.
Comparator 0 Interrupt Enable
Value Description
0
A comparator 0 interrupt does not affect the interrupt status.
1
The raw interrupt signal comparator 0 is sent to the interrupt
controller.
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Tiva™ TM4C1237H6PZ Microcontroller
Register 4: Analog Comparator Reference Voltage Control (ACREFCTL), offset
0x010
This register specifies whether the resistor ladder is powered on as well as the range and tap.
Analog Comparator Reference Voltage Control (ACREFCTL)
Base 0x4003.C000
Offset 0x010
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
1
0
RW
0
RW
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
9
8
EN
RNG
RW
0
RW
0
Bit/Field
Name
Type
Reset
31:10
reserved
RO
0x0000.0
9
EN
RW
0
reserved
RO
0
RO
0
RO
0
VREF
RO
0
RW
0
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Resistor Ladder Enable
Value Description
0
The resistor ladder is unpowered.
1
Powers on the resistor ladder. The resistor ladder is connected
to VDDA.
This bit is cleared at reset so that the internal reference consumes the
least amount of power if it is not used.
8
RNG
RW
0
Resistor Ladder Range
Value Description
0
The ideal step size for the internal reference is VDDA / 29.4.
1
The ideal step size for the internal reference is VDDA / 22.12.
7:4
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3:0
VREF
RW
0x0
Resistor Ladder Voltage Ref
The VREF bit field specifies the resistor ladder tap that is passed through
an analog multiplexer. The voltage corresponding to the tap position is
the internal reference voltage available for comparison. See Table
19-2 on page 1210 for some output reference voltage examples.
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Analog Comparators
Register 5: Analog Comparator Status 0 (ACSTAT0), offset 0x020
Register 6: Analog Comparator Status 1 (ACSTAT1), offset 0x040
Register 7: Analog Comparator Status 2 (ACSTAT2), offset 0x060
These registers specify the current output value of the comparator.
Analog Comparator Status n (ACSTATn)
Base 0x4003.C000
Offset 0x020
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
OVAL
reserved
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:2
reserved
RO
0x0000.000
1
OVAL
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Comparator Output Value
Value Description
0
VIN- > VIN+
1
VIN- < VIN+
VIN - is the voltage on the Cn- pin. VIN+ is the voltage on the Cn+ pin,
the C0+ pin, or the internal voltage reference (VIREF) as defined by the
ASRCP bit in the ACCTL register.
0
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1218
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Tiva™ TM4C1237H6PZ Microcontroller
Register 8: Analog Comparator Control 0 (ACCTL0), offset 0x024
Register 9: Analog Comparator Control 1 (ACCTL1), offset 0x044
Register 10: Analog Comparator Control 2 (ACCTL2), offset 0x064
These registers configure the comparator's input and output.
Analog Comparator Control n (ACCTLn)
Base 0x4003.C000
Offset 0x024
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
reserved
TSLVAL
CINV
reserved
RO
0
RW
0
RW
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
TOEN
RO
0
RO
0
ASRCP
RW
0
RW
0
RW
0
Bit/Field
Name
Type
Reset
31:12
reserved
RO
0x0000.0
11
TOEN
RW
0
TSEN
RW
0
ISLVAL
RW
0
RW
0
ISEN
RW
0
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Trigger Output Enable
Value Description
10:9
ASRCP
RW
0x0
0
ADC events are suppressed and not sent to the ADC.
1
ADC events are sent to the ADC.
Analog Source Positive
The ASRCP field specifies the source of input voltage to the VIN+ terminal
of the comparator. The encodings for this field are as follows:
Value Description
0x0
Pin value of Cn+
0x1
Pin value of C0+
0x2
Internal voltage reference (VIREF)
0x3
Reserved
8
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7
TSLVAL
RW
0
Trigger Sense Level Value
Value Description
0
An ADC event is generated if the comparator output is Low.
1
An ADC event is generated if the comparator output is High.
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Analog Comparators
Bit/Field
Name
Type
Reset
6:5
TSEN
RW
0x0
Description
Trigger Sense
The TSEN field specifies the sense of the comparator output that
generates an ADC event. The sense conditioning is as follows:
Value Description
4
ISLVAL
RW
0
0x0
Level sense, see TSLVAL
0x1
Falling edge
0x2
Rising edge
0x3
Either edge
Interrupt Sense Level Value
Value Description
3:2
ISEN
RW
0x0
0
An interrupt is generated if the comparator output is Low.
1
An interrupt is generated if the comparator output is High.
Interrupt Sense
The ISEN field specifies the sense of the comparator output that
generates an interrupt. The sense conditioning is as follows:
Value Description
1
CINV
RW
0
0x0
Level sense, see ISLVAL
0x1
Falling edge
0x2
Rising edge
0x3
Either edge
Comparator Output Invert
Value Description
0
reserved
RO
0
0
The output of the comparator is unchanged.
1
The output of the comparator is inverted prior to being processed
by hardware.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Tiva™ TM4C1237H6PZ Microcontroller
Register 11: Analog Comparator Peripheral Properties (ACMPPP), offset 0xFC0
The ACMPPP register provides information regarding the properties of the analog comparator
module.
Analog Comparator Peripheral Properties (ACMPPP)
Base 0x4003.C000
Offset 0xFC0
Type RO, reset 0x0007.0007
31
30
29
28
27
26
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
25
24
23
22
21
20
19
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
9
8
7
6
5
4
3
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
18
17
16
C2O
C1O
C0O
RO
1
RO
1
RO
1
2
1
0
CMP2
CMP1
CMP0
RO
1
RO
1
RO
1
Bit/Field
Name
Type
Reset
Description
31:19
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
18
C2O
RO
0x1
Comparator Output 2 Present
Value Description
17
C1O
RO
0x1
0
Comparator output 2 is not present.
1
Comparator output 2 is present.
Comparator Output 1 Present
Value Description
16
C0O
RO
0x1
0
Comparator output 1 is not present.
1
Comparator output 1 is present.
Comparator Output 0 Present
Value Description
0
Comparator output 0 is not present.
1
Comparator output 0 is present.
15:3
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2
CMP2
RO
0x1
Comparator 2 Present
Value Description
0
Comparator 2 is not present.
1
Comparator 2 is present.
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Analog Comparators
Bit/Field
Name
Type
Reset
1
CMP1
RO
0x1
Description
Comparator 1 Present
Value Description
0
CMP0
RO
0x1
0
Comparator 1 is not present.
1
Comparator 1 is present.
Comparator 0 Present
Value Description
0
Comparator 0 is not present.
1
Comparator 0 is present.
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Tiva™ TM4C1237H6PZ Microcontroller
20
Pin Diagram
The TM4C1237H6PZ microcontroller pin diagram is shown below.
Each GPIO signal is identified by its GPIO port unless it defaults to an alternate function on reset.
In this case, the GPIO port name is followed by the default alternate function. To see a complete
list of possible functions for each pin, see Table 21-5 on page 1249.
Figure 20-1. 100-Pin LQFP Package Pin Diagram
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Signal Tables
21
Signal Tables
The following tables list the signals available for each pin. Signals are configured as GPIOs on reset,
except for those noted below. Use the GPIOAMSEL register (see page 675) to select analog mode.
For a GPIO pin to be used for an alternate digital function, the corresponding bit in the GPIOAFSEL
register (see page 659) must be set. Further pin muxing options are provided through the PMCx bit
field in the GPIOPCTL register (see page 677), which selects one of several available peripheral
functions for that GPIO.
Important: Table 10-1 on page 635 shows special consideration GPIO pins. Most GPIO pins are
configured as GPIOs and tri-stated by default (GPIOAFSEL=0, GPIODEN=0,
GPIOPDR=0, GPIOPUR=0, and GPIOPCTL=0). Special consideration pins may be
programed to a non-GPIO function or may have special commit controls out of reset.
In addition, a Power-On-Reset (POR) or asserting RST returns these GPIO to their
original special consideration state.
Table 21-1. GPIO Pins With Special Considerations
GPIO Pins
Default Reset
State
GPIOAFSEL GPIODEN GPIOPDR GPIOPUR GPIOPCTL GPIOCR
PA[1:0]
UART0
0
0
0
0
0x1
1
PA[5:2]
SSI0
0
0
0
0
0x2
1
PB[3:2]
I21C0
0
0
0
0
0x3
1
PC[3:0]
JTAG/SWD
PD[7]
GPIO
PF[0]
1
1
0
1
0x1
0
a
0
0
0
0
0x0
0
a
0
0
0
0
0x0
0
GPIO
a. This pin is configured as a GPIO by default but is locked and can only be reprogrammed by unlocking the
pin in the GPIOLOCK register and uncommitting it by setting the GPIOCR register.
Table 21-2 on page 1225 shows the pin-to-signal-name mapping, including functional characteristics
of the signals. Each possible alternate analog and digital function is listed for each pin.
Table 21-3 on page 1233 lists the signals in alphabetical order by signal name. If it is possible for a
signal to be on multiple pins, each possible pin assignment is listed. The "Pin Mux" column indicates
the GPIO and the encoding needed in the PMCx bit field in the GPIOPCTL register.
Table 21-4 on page 1242 groups the signals by functionality, except for GPIOs. If it is possible for a
signal to be on multiple pins, each possible pin assignment is listed.
Table 21-5 on page 1249 lists the GPIO pins and their analog and digital alternate functions. The AINx
analog signals are not 5-V tolerant and go through an isolation circuit before reaching their circuitry.
These signals are configured by clearing the corresponding DEN bit in the GPIO Digital Enable
(GPIODEN) register and setting the corresponding AMSEL bit in the GPIO Analog Mode Select
(GPIOAMSEL) register. Other analog signals are 5-V tolerant and are connected directly to their
circuitry (C0-, C0+, C1-, C1+, C2-, C2+, USB0VBUS, USB0ID). These signals are configured by
clearing the DEN bit in the GPIO Digital Enable (GPIODEN) register. The digital signals are enabled
by setting the appropriate bit in the GPIO Alternate Function Select (GPIOAFSEL) and GPIODEN
registers and configuring the PMCx bit field in the GPIO Port Control (GPIOPCTL) register to the
numeric enoding shown in the table below. Table entries that are shaded gray are the default values
for the corresponding GPIO pin.
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Tiva™ TM4C1237H6PZ Microcontroller
Table 21-6 on page 1252 lists the signals based on number of possible pin assignments. This table
can be used to plan how to configure the pins for a particular functionality. Application Note AN01274
Configuring Tiva™ C Series Microcontrollers with Pin Multiplexing provides an overview of the pin
muxing implementation, an explanation of how a system designer defines a pin configuration, and
examples of the pin configuration process.
Note:
21.1
All digital inputs are Schmitt triggered.
Signals by Pin Number
Table 21-2. Signals by Pin Number
Pin Number
a
Pin Name
Pin Type
Buffer Type
PD0
I/O
TTL
AIN15
I
Analog
I/O
OD
I2C module 3 clock. Note that this signal has an active pull-up. The
corresponding port pin should not be configured as open drain.
SSI1Clk
I/O
TTL
SSI module 1 clock.
SSI3Clk
I/O
TTL
SSI module 3 clock.
WT2CCP0
I/O
TTL
32/64-Bit Wide Timer 2 Capture/Compare/PWM 0.
PD1
I/O
TTL
GPIO port D bit 1.
5
6
7
Analog-to-digital converter input 15.
AIN14
I
Analog
I2C3SDA
I/O
OD
I2C module 3 data.
SSI1Fss
I/O
TTL
SSI module 1 frame signal.
SSI3Fss
I/O
TTL
SSI module 3 frame signal.
WT2CCP1
I/O
TTL
32/64-Bit Wide Timer 2 Capture/Compare/PWM 1.
PD2
I/O
TTL
GPIO port D bit 2.
AIN13
I
Analog
SSI1Rx
I
TTL
SSI module 1 receive.
2
4
GPIO port D bit 0.
I2C3SCL
1
3
Description
Analog-to-digital converter input 14.
Analog-to-digital converter input 13.
SSI3Rx
I
TTL
SSI module 3 receive.
USB0EPEN
O
TTL
Optionally used in Host mode to control an external power source
to supply power to the USB bus.
WT3CCP0
I/O
TTL
32/64-Bit Wide Timer 3 Capture/Compare/PWM 0.
PD3
I/O
TTL
GPIO port D bit 3.
AIN12
I
Analog
SSI1Tx
O
TTL
Analog-to-digital converter input 12.
SSI module 1 transmit.
SSI3Tx
O
TTL
SSI module 3 transmit.
USB0PFLT
I
TTL
Optionally used in Host mode by an external power source to
indicate an error state by that power source.
WT3CCP1
I/O
TTL
32/64-Bit Wide Timer 3 Capture/Compare/PWM 1.
VDD
-
Power
Positive supply for I/O and some logic.
GND
-
Power
Ground reference for logic and I/O pins.
VDDA
-
Power
The positive supply for the analog circuits (ADC, Analog
Comparators, etc.). These are separated from VDD to minimize
the electrical noise contained on VDD from affecting the analog
functions. VDDA pins must be supplied with a voltage that meets
the specification in Table 22-5 on page 1258, regardless of system
implementation.
June 12, 2014
1225
Texas Instruments-Production Data
Signal Tables
Table 21-2. Signals by Pin Number (continued)
Pin Number
a
Pin Name
Pin Type
Buffer Type
VREFA+
-
Analog
A reference voltage used to specify the voltage at which the ADC
converts to a maximum value. This pin is used in conjunction with
VREFA-, which specifies the minimum value . The voltage that is
applied to VREFA+ is the voltage with which an AINn signal is
converted to 4095. The VREFA+ voltage is limited to the range
specified in Table 22-33 on page 1287 .
VREFA-
-
Analog
A reference voltage used to specify the input voltage at which the
ADC converts to a minimum value. This pin is used in conjunction
with VREFA+, which specifies the maximum value. In other words,
the voltage that is applied to VREFA- is the voltage with which an
AINn signal is converted to 0, while the voltage that is applied to
VREFA+ is the voltage with which an AINn signal is converted to
4095. The VREFA- voltage is limited to the range specified in Table
22-33 on page 1287 .
GNDA
-
Power
The ground reference for the analog circuits (ADC, Analog
Comparators, etc.). These are separated from GND to minimize
the electrical noise contained on VDD from affecting the analog
functions.
PJ2
I/O
TTL
GPIO port J bit 2.
T2CCP0
I/O
TTL
16/32-Bit Timer 2 Capture/Compare/PWM 0.
U5Rx
I
TTL
UART module 5 receive.
PE3
I/O
TTL
GPIO port E bit 3.
AIN0
I
Analog
PE2
I/O
TTL
AIN1
I
Analog
PE1
I/O
TTL
AIN2
I
Analog
U7Tx
O
TTL
UART module 7 transmit.
PE0
I/O
TTL
GPIO port E bit 0.
AIN3
I
Analog
U7Rx
I
TTL
UART module 7 receive.
PH0
I/O
TTL
GPIO port H bit 0.
8
9
10
11
12
13
14
15
Description
Analog-to-digital converter input 0.
GPIO port E bit 2.
Analog-to-digital converter input 1.
GPIO port E bit 1.
Analog-to-digital converter input 2.
Analog-to-digital converter input 3.
AIN16
I
Analog
SSI3Clk
I/O
TTL
SSI module 3 clock.
WT2CCP0
I/O
TTL
32/64-Bit Wide Timer 2 Capture/Compare/PWM 0.
GPIO port H bit 1.
16
Analog-to-digital converter input 16.
PH1
I/O
TTL
AIN17
I
Analog
SSI3Fss
I/O
TTL
SSI module 3 frame signal.
WT2CCP1
I/O
TTL
32/64-Bit Wide Timer 2 Capture/Compare/PWM 1.
PH2
I/O
TTL
GPIO port H bit 2.
17
Analog-to-digital converter input 17.
AIN18
I
Analog
SSI3Rx
I
TTL
SSI module 3 receive.
WT5CCP0
I/O
TTL
32/64-Bit Wide Timer 5 Capture/Compare/PWM 0.
18
Analog-to-digital converter input 18.
1226
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Table 21-2. Signals by Pin Number (continued)
Pin Number
Pin Name
Pin Type
a
Buffer Type
Description
PH3
I/O
TTL
AIN19
I
Analog
SSI3Tx
O
TTL
SSI module 3 transmit.
32/64-Bit Wide Timer 5 Capture/Compare/PWM 1.
19
GPIO port H bit 3.
Analog-to-digital converter input 19.
WT5CCP1
I/O
TTL
20
VDD
-
Power
Positive supply for I/O and some logic.
21
GND
-
Power
Ground reference for logic and I/O pins.
PC7
I/O
TTL
C0-
I
Analog
22
23
GPIO port C bit 7.
Analog comparator 0 negative input.
U3Tx
O
TTL
UART module 3 transmit.
USB0PFLT
I
TTL
Optionally used in Host mode by an external power source to
indicate an error state by that power source.
WT1CCP1
I/O
TTL
32/64-Bit Wide Timer 1 Capture/Compare/PWM 1.
PC6
I/O
TTL
GPIO port C bit 6.
C0+
I
Analog
U3Rx
I
TTL
UART module 3 receive.
USB0EPEN
O
TTL
Optionally used in Host mode to control an external power source
to supply power to the USB bus.
WT1CCP0
I/O
TTL
32/64-Bit Wide Timer 1 Capture/Compare/PWM 0.
PC5
I/O
TTL
GPIO port C bit 5.
C1+
I
Analog
U1CTS
I
TTL
UART module 1 Clear To Send modem flow control input signal.
U1Tx
O
TTL
UART module 1 transmit.
24
Analog comparator 0 positive input.
Analog comparator 1 positive input.
U4Tx
O
TTL
UART module 4 transmit.
WT0CCP1
I/O
TTL
32/64-Bit Wide Timer 0 Capture/Compare/PWM 1.
PC4
I/O
TTL
GPIO port C bit 4.
C1-
I
Analog
U1RTS
O
TTL
UART module 1 Request to Send modem flow control output line.
U1Rx
I
TTL
UART module 1 receive.
U4Rx
I
TTL
UART module 4 receive.
WT0CCP0
I/O
TTL
32/64-Bit Wide Timer 0 Capture/Compare/PWM 0.
25
Analog comparator 1 negative input.
PA0
I/O
TTL
GPIO port A bit 0.
U0Rx
I
TTL
UART module 0 receive.
PA1
I/O
TTL
GPIO port A bit 1.
U0Tx
O
TTL
UART module 0 transmit.
PA2
I/O
TTL
GPIO port A bit 2.
SSI0Clk
I/O
TTL
SSI module 0 clock
PA3
I/O
TTL
GPIO port A bit 3.
SSI0Fss
I/O
TTL
SSI module 0 frame signal
26
27
28
29
PA4
I/O
TTL
GPIO port A bit 4.
SSI0Rx
I
TTL
SSI module 0 receive
PA5
I/O
TTL
GPIO port A bit 5.
SSI0Tx
O
TTL
SSI module 0 transmit
30
31
June 12, 2014
1227
Texas Instruments-Production Data
Signal Tables
Table 21-2. Signals by Pin Number (continued)
a
Pin Number
Pin Name
Pin Type
Buffer Type
32
VDD
-
Power
Positive supply for I/O and some logic.
33
GND
-
Power
Ground reference for logic and I/O pins.
PA6
I/O
TTL
GPIO port A bit 6.
I2C1SCL
I/O
OD
I2C module 1 clock. Note that this signal has an active pull-up. The
corresponding port pin should not be configured as open drain.
34
PA7
I/O
TTL
GPIO port A bit 7.
I2C1SDA
I/O
OD
I2C module 1 data.
PF6
I/O
TTL
GPIO port F bit 6.
I2C2SCL
I/O
OD
I2C module 2 clock. Note that this signal has an active pull-up. The
corresponding port pin should not be configured as open drain.
T3CCP0
I/O
TTL
16/32-Bit Timer 3 Capture/Compare/PWM 0.
PF5
I/O
TTL
GPIO port F bit 5.
T2CCP1
I/O
TTL
16/32-Bit Timer 2 Capture/Compare/PWM 1.
USB0PFLT
I
TTL
Optionally used in Host mode by an external power source to
indicate an error state by that power source.
VDDC
-
Power
PF4
I/O
TTL
GPIO port F bit 4.
T2CCP0
I/O
TTL
16/32-Bit Timer 2 Capture/Compare/PWM 0.
35
36
37
38
39
Description
Positive supply for most of the logic function, including the
processor core and most peripherals. The voltage on this pin is
1.2 V and is supplied by the on-chip LDO. The VDDC pins should
only be connected to each other and an external capacitor as
specified in Table 22-12 on page 1271 .
TRD3
O
TTL
Trace data 3.
U1DTR
O
TTL
UART module 1 Data Terminal Ready modem status input signal.
USB0EPEN
O
TTL
Optionally used in Host mode to control an external power source
to supply power to the USB bus.
PF0
I/O
TTL
GPIO port F bit 0.
C0o
O
TTL
Analog comparator 0 output.
CAN0Rx
I
TTL
CAN module 0 receive.
NMI
I
TTL
Non-maskable interrupt.
SSI1Rx
I
TTL
SSI module 1 receive.
T0CCP0
I/O
TTL
16/32-Bit Timer 0 Capture/Compare/PWM 0.
40
TRD2
O
TTL
Trace data 2.
U1RTS
O
TTL
UART module 1 Request to Send modem flow control output line.
PF1
I/O
TTL
GPIO port F bit 1.
C1o
O
TTL
Analog comparator 1 output.
SSI1Tx
O
TTL
SSI module 1 transmit.
T0CCP1
I/O
TTL
16/32-Bit Timer 0 Capture/Compare/PWM 1.
TRD1
O
TTL
Trace data 1.
U1CTS
I
TTL
UART module 1 Clear To Send modem flow control input signal.
41
1228
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Table 21-2. Signals by Pin Number (continued)
Pin Number
a
Pin Name
Pin Type
Buffer Type
PF2
I/O
TTL
GPIO port F bit 2.
C2o
O
TTL
Analog comparator 2 output.
SSI1Clk
I/O
TTL
SSI module 1 clock.
T1CCP0
I/O
TTL
16/32-Bit Timer 1 Capture/Compare/PWM 0.
TRD0
O
TTL
Trace data 0.
U1DCD
I
TTL
UART module 1 Data Carrier Detect modem status input signal.
PF3
I/O
TTL
GPIO port F bit 3.
CAN0Tx
O
TTL
CAN module 0 transmit.
SSI1Fss
I/O
TTL
SSI module 1 frame signal.
T1CCP1
I/O
TTL
16/32-Bit Timer 1 Capture/Compare/PWM 1.
TRCLK
O
TTL
Trace clock.
U1DSR
I
TTL
UART module 1 Data Set Ready modem output control line.
44
VDD
-
Power
Positive supply for I/O and some logic.
45
GND
-
Power
Ground reference for logic and I/O pins.
PK3
I/O
TTL
GPIO port K bit 3.
SSI3Tx
O
TTL
SSI module 3 transmit.
PK2
I/O
TTL
GPIO port K bit 2.
SSI3Rx
I
TTL
SSI module 3 receive.
42
43
46
47
Description
PK1
I/O
TTL
GPIO port K bit 1.
SSI3Fss
I/O
TTL
SSI module 3 frame signal.
PK0
I/O
TTL
GPIO port K bit 0.
SSI3Clk
I/O
TTL
SSI module 3 clock.
WAKE
I
TTL
An external input that brings the processor out of Hibernate mode
when asserted.
HIB
O
TTL
An output that indicates the processor is in Hibernate mode.
XOSC0
I
Analog
Hibernation module oscillator crystal input or an external clock
reference input. Note that this is either a 32.768-kHz crystal or a
32.768-kHz oscillator for the Hibernation module RTC.
GNDX
-
Power
GND for the Hibernation oscillator. When using a crystal clock
source, this pin should be connected to digital ground along with
the crystal load capacitors. When using an external oscillator, this
pin should be connected to digital ground.
XOSC1
O
Analog
Hibernation module oscillator crystal output. Leave unconnected
when using a single-ended clock source.
VBAT
-
Power
Power source for the Hibernation module. It is normally connected
to the positive terminal of a battery and serves as the battery
backup/Hibernation module power-source supply.
56
VDD
-
Power
Positive supply for I/O and some logic.
57
GND
-
Power
Ground reference for logic and I/O pins.
PF7
I/O
TTL
GPIO port F bit 7.
I2C2SDA
I/O
OD
I2C module 2 data.
T3CCP1
I/O
TTL
16/32-Bit Timer 3 Capture/Compare/PWM 1.
48
49
50
51
52
53
54
55
58
June 12, 2014
1229
Texas Instruments-Production Data
Signal Tables
Table 21-2. Signals by Pin Number (continued)
a
Pin Number
Pin Name
Pin Type
Buffer Type
PG3
I/O
TTL
GPIO port G bit 3.
59
I2C4SDA
I/O
OD
I2C module 4 data.
T5CCP1
I/O
TTL
16/32-Bit Timer 5 Capture/Compare/PWM 1.
60
61
62
Description
PG2
I/O
TTL
GPIO port G bit 2.
I2C4SCL
I/O
OD
I2C module 4 clock. Note that this signal has an active pull-up. The
corresponding port pin should not be configured as open drain.
T5CCP0
I/O
TTL
16/32-Bit Timer 5 Capture/Compare/PWM 0.
PG1
I/O
TTL
GPIO port G bit 1.
I2C3SDA
I/O
OD
I2C module 3 data.
T4CCP1
I/O
TTL
16/32-Bit Timer 4 Capture/Compare/PWM 1.
PG0
I/O
TTL
GPIO port G bit 0.
I2C3SCL
I/O
OD
I2C module 3 clock. Note that this signal has an active pull-up. The
corresponding port pin should not be configured as open drain.
T4CCP0
I/O
TTL
16/32-Bit Timer 4 Capture/Compare/PWM 0.
63
RST
I
TTL
System reset input.
64
GND
-
Power
Ground reference for logic and I/O pins.
65
OSC0
I
Analog
Main oscillator crystal input or an external clock reference input.
OSC1
O
Analog
Main oscillator crystal output. Leave unconnected when using a
single-ended clock source.
VDD
-
Power
Positive supply for I/O and some logic.
PJ0
I/O
TTL
GPIO port J bit 0. This pin is not 5-V tolerant.
T1CCP0
I/O
TTL
16/32-Bit Timer 1 Capture/Compare/PWM 0.
U4Rx
I
TTL
UART module 4 receive.
USB0DM
I/O
Analog
66
67
68
69
70
71
Bidirectional differential data pin (D- per USB specification) for
USB0.
PJ1
I/O
TTL
GPIO port J bit 1. This pin is not 5-V tolerant.
T1CCP1
I/O
TTL
16/32-Bit Timer 1 Capture/Compare/PWM 1.
U4Tx
O
TTL
UART module 4 transmit.
USB0DP
I/O
Analog
Bidirectional differential data pin (D+ per USB specification) for
USB0.
PB0
I/O
TTL
GPIO port B bit 0. This pin is not 5-V tolerant.
T2CCP0
I/O
TTL
16/32-Bit Timer 2 Capture/Compare/PWM 0.
UART module 1 receive.
U1Rx
I
TTL
USB0ID
I
Analog
PB1
I/O
TTL
GPIO port B bit 1. This pin is not 5-V tolerant.
T2CCP1
I/O
TTL
16/32-Bit Timer 2 Capture/Compare/PWM 1.
UART module 1 transmit.
U1Tx
O
TTL
USB0VBUS
I/O
Analog
This signal senses the state of the USB ID signal. The USB PHY
enables an integrated pull-up, and an external element (USB
connector) indicates the initial state of the USB controller (pulled
down is the A side of the cable and pulled up is the B side).
This signal is used during the session request protocol. This signal
allows the USB PHY to both sense the voltage level of VBUS, and
pull up VBUS momentarily during VBUS pulsing.
1230
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Table 21-2. Signals by Pin Number (continued)
Pin Number
72
73
74
75
76
a
Pin Name
Pin Type
Buffer Type
Description
PB2
I/O
TTL
GPIO port B bit 2.
I2C0SCL
I/O
OD
I2C module 0 clock. Note that this signal has an active pull-up. The
corresponding port pin should not be configured as open drain.
T3CCP0
I/O
TTL
16/32-Bit Timer 3 Capture/Compare/PWM 0.
PB3
I/O
TTL
GPIO port B bit 3.
I2C0SDA
I/O
OD
I2C module 0 data.
T3CCP1
I/O
TTL
16/32-Bit Timer 3 Capture/Compare/PWM 1.
PG4
I/O
TTL
GPIO port G bit 4.
I2C1SCL
I/O
OD
I2C module 1 clock. Note that this signal has an active pull-up. The
corresponding port pin should not be configured as open drain.
U2Rx
I
TTL
UART module 2 receive.
USB0EPEN
O
TTL
Optionally used in Host mode to control an external power source
to supply power to the USB bus.
WT0CCP0
I/O
TTL
32/64-Bit Wide Timer 0 Capture/Compare/PWM 0.
PG5
I/O
TTL
GPIO port G bit 5.
I2C1SDA
I/O
OD
I2C module 1 data.
U2Tx
O
TTL
UART module 2 transmit.
USB0PFLT
I
TTL
Optionally used in Host mode by an external power source to
indicate an error state by that power source.
WT0CCP1
I/O
TTL
32/64-Bit Wide Timer 0 Capture/Compare/PWM 1.
PH7
I/O
TTL
GPIO port H bit 7.
SSI2Tx
O
TTL
SSI module 2 transmit.
WT4CCP1
I/O
TTL
32/64-Bit Wide Timer 4 Capture/Compare/PWM 1.
PH6
I/O
TTL
GPIO port H bit 6.
SSI2Rx
I
TTL
SSI module 2 receive.
WT4CCP0
I/O
TTL
32/64-Bit Wide Timer 4 Capture/Compare/PWM 0.
PH5
I/O
TTL
GPIO port H bit 5.
SSI2Fss
I/O
TTL
SSI module 2 frame signal.
WT3CCP1
I/O
TTL
32/64-Bit Wide Timer 3 Capture/Compare/PWM 1.
PH4
I/O
TTL
GPIO port H bit 4.
SSI2Clk
I/O
TTL
SSI module 2 clock.
WT3CCP0
I/O
TTL
32/64-Bit Wide Timer 3 Capture/Compare/PWM 0.
80
VDD
-
Power
Positive supply for I/O and some logic.
81
GND
-
Power
Ground reference for logic and I/O pins.
PC3
I/O
TTL
GPIO port C bit 3.
77
78
79
SWO
O
TTL
JTAG TDO and SWO.
T5CCP1
I/O
TTL
16/32-Bit Timer 5 Capture/Compare/PWM 1.
TDO
O
TTL
JTAG TDO and SWO.
82
83
PC2
I/O
TTL
GPIO port C bit 2.
T5CCP0
I/O
TTL
16/32-Bit Timer 5 Capture/Compare/PWM 0.
TDI
I
TTL
JTAG TDI.
June 12, 2014
1231
Texas Instruments-Production Data
Signal Tables
Table 21-2. Signals by Pin Number (continued)
Pin Number
a
Pin Name
Pin Type
Buffer Type
PC1
I/O
TTL
GPIO port C bit 1.
SWDIO
I/O
TTL
JTAG TMS and SWDIO.
T4CCP1
I/O
TTL
16/32-Bit Timer 4 Capture/Compare/PWM 1.
TMS
I
TTL
JTAG TMS and SWDIO.
PC0
I/O
TTL
GPIO port C bit 0.
84
SWCLK
I
TTL
JTAG/SWD CLK.
T4CCP0
I/O
TTL
16/32-Bit Timer 4 Capture/Compare/PWM 0.
TCK
I
TTL
JTAG/SWD CLK.
VDDC
-
Power
PG6
I/O
TTL
85
86
87
GPIO port G bit 6.
C2+
I
Analog
I/O
OD
I2C module 5 clock. Note that this signal has an active pull-up. The
corresponding port pin should not be configured as open drain.
WT1CCP0
I/O
TTL
32/64-Bit Wide Timer 1 Capture/Compare/PWM 0.
PG7
I/O
TTL
GPIO port G bit 7.
Analog comparator 2 positive input.
C2-
I
Analog
I2C5SDA
I/O
OD
I2C module 5 data.
WT1CCP1
I/O
TTL
32/64-Bit Wide Timer 1 Capture/Compare/PWM 1.
Analog comparator 2 negative input.
GPIO port E bit 6.
PE6
I/O
TTL
AIN21
I
Analog
PE7
I/O
TTL
AIN20
I
Analog
U1RI
I
TTL
UART module 1 Ring Indicator modem status input signal.
GPIO port B bit 5.
89
91
Positive supply for most of the logic function, including the
processor core and most peripherals. The voltage on this pin is
1.2 V and is supplied by the on-chip LDO. The VDDC pins should
only be connected to each other and an external capacitor as
specified in Table 22-12 on page 1271 .
I2C5SCL
88
90
Description
Analog-to-digital converter input 21.
GPIO port E bit 7.
Analog-to-digital converter input 20.
PB5
I/O
TTL
AIN11
I
Analog
CAN0Tx
O
TTL
CAN module 0 transmit.
SSI2Fss
I/O
TTL
SSI module 2 frame signal.
T1CCP1
I/O
TTL
16/32-Bit Timer 1 Capture/Compare/PWM 1.
GPIO port B bit 4.
Analog-to-digital converter input 11.
PB4
I/O
TTL
AIN10
I
Analog
CAN0Rx
I
TTL
CAN module 0 receive.
SSI2Clk
I/O
TTL
SSI module 2 clock.
T1CCP0
I/O
TTL
16/32-Bit Timer 1 Capture/Compare/PWM 0.
93
VDD
-
Power
Positive supply for I/O and some logic.
94
GND
-
Power
Ground reference for logic and I/O pins.
92
Analog-to-digital converter input 10.
1232
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Table 21-2. Signals by Pin Number (continued)
Pin Number
95
96
Pin Name
Pin Type
Description
PE4
I/O
TTL
AIN9
I
Analog
CAN0Rx
I
TTL
CAN module 0 receive.
I2C2SCL
I/O
OD
I2C module 2 clock. Note that this signal has an active pull-up. The
corresponding port pin should not be configured as open drain.
U5Rx
I
TTL
UART module 5 receive.
PE5
I/O
TTL
GPIO port E bit 5.
AIN8
I
Analog
GPIO port E bit 4.
Analog-to-digital converter input 9.
Analog-to-digital converter input 8.
CAN0Tx
O
TTL
CAN module 0 transmit.
I2C2SDA
I/O
OD
I2C module 2 data.
U5Tx
O
TTL
UART module 5 transmit.
PD4
I/O
TTL
GPIO port D bit 4.
AIN7
I
Analog
97
Analog-to-digital converter input 7.
U6Rx
I
TTL
UART module 6 receive.
WT4CCP0
I/O
TTL
32/64-Bit Wide Timer 4 Capture/Compare/PWM 0.
PD5
I/O
TTL
GPIO port D bit 5.
AIN6
I
Analog
U6Tx
O
TTL
UART module 6 transmit.
WT4CCP1
I/O
TTL
32/64-Bit Wide Timer 4 Capture/Compare/PWM 1.
PD6
I/O
TTL
GPIO port D bit 6.
AIN5
I
Analog
98
99
100
a
Buffer Type
Analog-to-digital converter input 6.
Analog-to-digital converter input 5.
U2Rx
I
TTL
UART module 2 receive.
WT5CCP0
I/O
TTL
32/64-Bit Wide Timer 5 Capture/Compare/PWM 0.
GPIO port D bit 7.
PD7
I/O
TTL
AIN4
I
Analog
NMI
I
TTL
Non-maskable interrupt.
U2Tx
O
TTL
UART module 2 transmit.
WT5CCP1
I/O
TTL
32/64-Bit Wide Timer 5 Capture/Compare/PWM 1.
Analog-to-digital converter input 4.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
21.2
Signals by Signal Name
Table 21-3. Signals by Signal Name
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
AIN0
12
PE3
I
Analog
Analog-to-digital converter input 0.
AIN1
13
PE2
I
Analog
Analog-to-digital converter input 1.
AIN2
14
PE1
I
Analog
Analog-to-digital converter input 2.
AIN3
15
PE0
I
Analog
Analog-to-digital converter input 3.
AIN4
100
PD7
I
Analog
Analog-to-digital converter input 4.
AIN5
99
PD6
I
Analog
Analog-to-digital converter input 5.
AIN6
98
PD5
I
Analog
Analog-to-digital converter input 6.
June 12, 2014
1233
Texas Instruments-Production Data
Signal Tables
Table 21-3. Signals by Signal Name (continued)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
AIN7
97
PD4
I
Analog
Analog-to-digital converter input 7.
AIN8
96
PE5
I
Analog
Analog-to-digital converter input 8.
AIN9
95
PE4
I
Analog
Analog-to-digital converter input 9.
AIN10
92
PB4
I
Analog
Analog-to-digital converter input 10.
AIN11
91
PB5
I
Analog
Analog-to-digital converter input 11.
AIN12
4
PD3
I
Analog
Analog-to-digital converter input 12.
AIN13
3
PD2
I
Analog
Analog-to-digital converter input 13.
AIN14
2
PD1
I
Analog
Analog-to-digital converter input 14.
AIN15
1
PD0
I
Analog
Analog-to-digital converter input 15.
AIN16
16
PH0
I
Analog
Analog-to-digital converter input 16.
AIN17
17
PH1
I
Analog
Analog-to-digital converter input 17.
AIN18
18
PH2
I
Analog
Analog-to-digital converter input 18.
AIN19
19
PH3
I
Analog
Analog-to-digital converter input 19.
AIN20
90
PE7
I
Analog
Analog-to-digital converter input 20.
AIN21
89
PE6
I
Analog
Analog-to-digital converter input 21.
C0+
23
PC6
I
Analog
Analog comparator 0 positive input.
C0-
22
PC7
I
Analog
Analog comparator 0 negative input.
C0o
40
PF0 (9)
O
TTL
C1+
24
PC5
I
Analog
Analog comparator 1 positive input.
C1-
25
PC4
I
Analog
Analog comparator 1 negative input.
C1o
41
PF1 (9)
O
TTL
C2+
87
PG6
I
Analog
Analog comparator 2 positive input.
C2-
88
PG7
I
Analog
Analog comparator 2 negative input.
C2o
42
PF2 (9)
O
TTL
Analog comparator 2 output.
CAN0Rx
40
92
95
PF0 (3)
PB4 (8)
PE4 (8)
I
TTL
CAN module 0 receive.
CAN0Tx
43
91
96
PF3 (3)
PB5 (8)
PE5 (8)
O
TTL
CAN module 0 transmit.
GND
6
21
33
45
57
64
81
94
fixed
-
Power
Ground reference for logic and I/O pins.
GNDA
10
fixed
-
Power
The ground reference for the analog circuits (ADC,
Analog Comparators, etc.). These are separated
from GND to minimize the electrical noise contained
on VDD from affecting the analog functions.
Analog comparator 0 output.
Analog comparator 1 output.
1234
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Table 21-3. Signals by Signal Name (continued)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
GNDX
53
fixed
-
Power
GND for the Hibernation oscillator. When using a
crystal clock source, this pin should be connected
to digital ground along with the crystal load
capacitors. When using an external oscillator, this
pin should be connected to digital ground.
HIB
51
fixed
O
TTL
An output that indicates the processor is in
Hibernate mode.
I2C0SCL
72
PB2 (3)
I/O
OD
I2C module 0 clock. Note that this signal has an
active pull-up. The corresponding port pin should
not be configured as open drain.
I2C0SDA
73
PB3 (3)
I/O
OD
I2C module 0 data.
I2C1SCL
34
74
PA6 (3)
PG4 (3)
I/O
OD
I2C module 1 clock. Note that this signal has an
active pull-up. The corresponding port pin should
not be configured as open drain.
I2C1SDA
35
75
PA7 (3)
PG5 (3)
I/O
OD
I2C module 1 data.
I2C2SCL
36
95
PF6 (3)
PE4 (3)
I/O
OD
I2C module 2 clock. Note that this signal has an
active pull-up. The corresponding port pin should
not be configured as open drain.
I2C2SDA
58
96
PF7 (3)
PE5 (3)
I/O
OD
I2C module 2 data.
I2C3SCL
1
62
PD0 (3)
PG0 (3)
I/O
OD
I2C module 3 clock. Note that this signal has an
active pull-up. The corresponding port pin should
not be configured as open drain.
I2C3SDA
2
61
PD1 (3)
PG1 (3)
I/O
OD
I2C module 3 data.
I2C4SCL
60
PG2 (3)
I/O
OD
I2C module 4 clock. Note that this signal has an
active pull-up. The corresponding port pin should
not be configured as open drain.
I2C4SDA
59
PG3 (3)
I/O
OD
I2C module 4 data.
I2C5SCL
87
PG6 (3)
I/O
OD
I2C module 5 clock. Note that this signal has an
active pull-up. The corresponding port pin should
not be configured as open drain.
I2C5SDA
88
PG7 (3)
I/O
OD
I2C module 5 data.
NMI
40
100
PF0 (8)
PD7 (8)
I
TTL
Non-maskable interrupt.
OSC0
65
fixed
I
Analog
Main oscillator crystal input or an external clock
reference input.
OSC1
66
fixed
O
Analog
Main oscillator crystal output. Leave unconnected
when using a single-ended clock source.
PA0
26
-
I/O
TTL
GPIO port A bit 0.
PA1
27
-
I/O
TTL
GPIO port A bit 1.
PA2
28
-
I/O
TTL
GPIO port A bit 2.
PA3
29
-
I/O
TTL
GPIO port A bit 3.
PA4
30
-
I/O
TTL
GPIO port A bit 4.
PA5
31
-
I/O
TTL
GPIO port A bit 5.
PA6
34
-
I/O
TTL
GPIO port A bit 6.
June 12, 2014
1235
Texas Instruments-Production Data
Signal Tables
Table 21-3. Signals by Signal Name (continued)
Pin Name
PA7
Pin Number Pin Mux / Pin
Assignment
35
-
a
Pin Type
Buffer Type
I/O
TTL
Description
GPIO port A bit 7.
PB0
70
-
I/O
TTL
GPIO port B bit 0. This pin is not 5-V tolerant.
PB1
71
-
I/O
TTL
GPIO port B bit 1. This pin is not 5-V tolerant.
PB2
72
-
I/O
TTL
GPIO port B bit 2.
PB3
73
-
I/O
TTL
GPIO port B bit 3.
PB4
92
-
I/O
TTL
GPIO port B bit 4.
PB5
91
-
I/O
TTL
GPIO port B bit 5.
PC0
85
-
I/O
TTL
GPIO port C bit 0.
PC1
84
-
I/O
TTL
GPIO port C bit 1.
PC2
83
-
I/O
TTL
GPIO port C bit 2.
PC3
82
-
I/O
TTL
GPIO port C bit 3.
PC4
25
-
I/O
TTL
GPIO port C bit 4.
PC5
24
-
I/O
TTL
GPIO port C bit 5.
PC6
23
-
I/O
TTL
GPIO port C bit 6.
PC7
22
-
I/O
TTL
GPIO port C bit 7.
PD0
1
-
I/O
TTL
GPIO port D bit 0.
PD1
2
-
I/O
TTL
GPIO port D bit 1.
PD2
3
-
I/O
TTL
GPIO port D bit 2.
PD3
4
-
I/O
TTL
GPIO port D bit 3.
PD4
97
-
I/O
TTL
GPIO port D bit 4.
PD5
98
-
I/O
TTL
GPIO port D bit 5.
PD6
99
-
I/O
TTL
GPIO port D bit 6.
PD7
100
-
I/O
TTL
GPIO port D bit 7.
PE0
15
-
I/O
TTL
GPIO port E bit 0.
PE1
14
-
I/O
TTL
GPIO port E bit 1.
PE2
13
-
I/O
TTL
GPIO port E bit 2.
PE3
12
-
I/O
TTL
GPIO port E bit 3.
PE4
95
-
I/O
TTL
GPIO port E bit 4.
PE5
96
-
I/O
TTL
GPIO port E bit 5.
PE6
89
-
I/O
TTL
GPIO port E bit 6.
PE7
90
-
I/O
TTL
GPIO port E bit 7.
PF0
40
-
I/O
TTL
GPIO port F bit 0.
PF1
41
-
I/O
TTL
GPIO port F bit 1.
PF2
42
-
I/O
TTL
GPIO port F bit 2.
PF3
43
-
I/O
TTL
GPIO port F bit 3.
PF4
39
-
I/O
TTL
GPIO port F bit 4.
PF5
37
-
I/O
TTL
GPIO port F bit 5.
PF6
36
-
I/O
TTL
GPIO port F bit 6.
PF7
58
-
I/O
TTL
GPIO port F bit 7.
PG0
62
-
I/O
TTL
GPIO port G bit 0.
PG1
61
-
I/O
TTL
GPIO port G bit 1.
1236
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Table 21-3. Signals by Signal Name (continued)
Pin Name
PG2
Pin Number Pin Mux / Pin
Assignment
60
-
a
Pin Type
Buffer Type
I/O
TTL
Description
GPIO port G bit 2.
PG3
59
-
I/O
TTL
GPIO port G bit 3.
PG4
74
-
I/O
TTL
GPIO port G bit 4.
PG5
75
-
I/O
TTL
GPIO port G bit 5.
PG6
87
-
I/O
TTL
GPIO port G bit 6.
PG7
88
-
I/O
TTL
GPIO port G bit 7.
PH0
16
-
I/O
TTL
GPIO port H bit 0.
PH1
17
-
I/O
TTL
GPIO port H bit 1.
PH2
18
-
I/O
TTL
GPIO port H bit 2.
PH3
19
-
I/O
TTL
GPIO port H bit 3.
PH4
79
-
I/O
TTL
GPIO port H bit 4.
PH5
78
-
I/O
TTL
GPIO port H bit 5.
PH6
77
-
I/O
TTL
GPIO port H bit 6.
PH7
76
-
I/O
TTL
GPIO port H bit 7.
PJ0
68
-
I/O
TTL
GPIO port J bit 0. This pin is not 5-V tolerant.
PJ1
69
-
I/O
TTL
GPIO port J bit 1. This pin is not 5-V tolerant.
PJ2
11
-
I/O
TTL
GPIO port J bit 2.
PK0
49
-
I/O
TTL
GPIO port K bit 0.
PK1
48
-
I/O
TTL
GPIO port K bit 1.
PK2
47
-
I/O
TTL
GPIO port K bit 2.
PK3
46
-
I/O
TTL
GPIO port K bit 3.
RST
63
fixed
I
TTL
System reset input.
SSI0Clk
28
PA2 (2)
I/O
TTL
SSI module 0 clock
SSI0Fss
29
PA3 (2)
I/O
TTL
SSI module 0 frame signal
SSI0Rx
30
PA4 (2)
I
TTL
SSI module 0 receive
SSI0Tx
31
PA5 (2)
O
TTL
SSI module 0 transmit
SSI1Clk
1
42
PD0 (2)
PF2 (2)
I/O
TTL
SSI module 1 clock.
SSI1Fss
2
43
PD1 (2)
PF3 (2)
I/O
TTL
SSI module 1 frame signal.
SSI1Rx
3
40
PD2 (2)
PF0 (2)
I
TTL
SSI module 1 receive.
SSI1Tx
4
41
PD3 (2)
PF1 (2)
O
TTL
SSI module 1 transmit.
SSI2Clk
79
92
PH4 (2)
PB4 (2)
I/O
TTL
SSI module 2 clock.
SSI2Fss
78
91
PH5 (2)
PB5 (2)
I/O
TTL
SSI module 2 frame signal.
SSI2Rx
77
PH6 (2)
I
TTL
SSI module 2 receive.
SSI2Tx
76
PH7 (2)
O
TTL
SSI module 2 transmit.
SSI3Clk
1
16
49
PD0 (1)
PH0 (2)
PK0 (2)
I/O
TTL
SSI module 3 clock.
June 12, 2014
1237
Texas Instruments-Production Data
Signal Tables
Table 21-3. Signals by Signal Name (continued)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
SSI3Fss
2
17
48
PD1 (1)
PH1 (2)
PK1 (2)
I/O
TTL
SSI module 3 frame signal.
SSI3Rx
3
18
47
PD2 (1)
PH2 (2)
PK2 (2)
I
TTL
SSI module 3 receive.
SSI3Tx
4
19
46
PD3 (1)
PH3 (2)
PK3 (2)
O
TTL
SSI module 3 transmit.
SWCLK
85
PC0 (1)
I
TTL
JTAG/SWD CLK.
SWDIO
84
PC1 (1)
I/O
TTL
JTAG TMS and SWDIO.
SWO
82
PC3 (1)
O
TTL
JTAG TDO and SWO.
T0CCP0
40
PF0 (7)
I/O
TTL
16/32-Bit Timer 0 Capture/Compare/PWM 0.
T0CCP1
41
PF1 (7)
I/O
TTL
16/32-Bit Timer 0 Capture/Compare/PWM 1.
T1CCP0
42
68
92
PF2 (7)
PJ0 (7)
PB4 (7)
I/O
TTL
16/32-Bit Timer 1 Capture/Compare/PWM 0.
T1CCP1
43
69
91
PF3 (7)
PJ1 (7)
PB5 (7)
I/O
TTL
16/32-Bit Timer 1 Capture/Compare/PWM 1.
T2CCP0
11
39
70
PJ2 (7)
PF4 (7)
PB0 (7)
I/O
TTL
16/32-Bit Timer 2 Capture/Compare/PWM 0.
T2CCP1
37
71
PF5 (7)
PB1 (7)
I/O
TTL
16/32-Bit Timer 2 Capture/Compare/PWM 1.
T3CCP0
36
72
PF6 (7)
PB2 (7)
I/O
TTL
16/32-Bit Timer 3 Capture/Compare/PWM 0.
T3CCP1
58
73
PF7 (7)
PB3 (7)
I/O
TTL
16/32-Bit Timer 3 Capture/Compare/PWM 1.
T4CCP0
62
85
PG0 (7)
PC0 (7)
I/O
TTL
16/32-Bit Timer 4 Capture/Compare/PWM 0.
T4CCP1
61
84
PG1 (7)
PC1 (7)
I/O
TTL
16/32-Bit Timer 4 Capture/Compare/PWM 1.
T5CCP0
60
83
PG2 (7)
PC2 (7)
I/O
TTL
16/32-Bit Timer 5 Capture/Compare/PWM 0.
T5CCP1
59
82
PG3 (7)
PC3 (7)
I/O
TTL
16/32-Bit Timer 5 Capture/Compare/PWM 1.
TCK
85
PC0 (1)
I
TTL
JTAG/SWD CLK.
TDI
83
PC2 (1)
I
TTL
JTAG TDI.
TDO
82
PC3 (1)
O
TTL
JTAG TDO and SWO.
TMS
84
PC1 (1)
I
TTL
JTAG TMS and SWDIO.
TRCLK
43
PF3 (14)
O
TTL
Trace clock.
TRD0
42
PF2 (14)
O
TTL
Trace data 0.
TRD1
41
PF1 (14)
O
TTL
Trace data 1.
TRD2
40
PF0 (14)
O
TTL
Trace data 2.
TRD3
39
PF4 (14)
O
TTL
Trace data 3.
U0Rx
26
PA0 (1)
I
TTL
UART module 0 receive.
1238
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Table 21-3. Signals by Signal Name (continued)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
U0Tx
27
PA1 (1)
O
TTL
UART module 0 transmit.
U1CTS
24
41
PC5 (8)
PF1 (1)
I
TTL
UART module 1 Clear To Send modem flow control
input signal.
U1DCD
42
PF2 (1)
I
TTL
UART module 1 Data Carrier Detect modem status
input signal.
U1DSR
43
PF3 (1)
I
TTL
UART module 1 Data Set Ready modem output
control line.
U1DTR
39
PF4 (1)
O
TTL
UART module 1 Data Terminal Ready modem
status input signal.
U1RI
90
PE7 (1)
I
TTL
UART module 1 Ring Indicator modem status input
signal.
U1RTS
25
40
PC4 (8)
PF0 (1)
O
TTL
UART module 1 Request to Send modem flow
control output line.
U1Rx
25
70
PC4 (2)
PB0 (1)
I
TTL
UART module 1 receive.
U1Tx
24
71
PC5 (2)
PB1 (1)
O
TTL
UART module 1 transmit.
U2Rx
74
99
PG4 (1)
PD6 (1)
I
TTL
UART module 2 receive.
U2Tx
75
100
PG5 (1)
PD7 (1)
O
TTL
UART module 2 transmit.
U3Rx
23
PC6 (1)
I
TTL
UART module 3 receive.
U3Tx
22
PC7 (1)
O
TTL
UART module 3 transmit.
U4Rx
25
68
PC4 (1)
PJ0 (1)
I
TTL
UART module 4 receive.
U4Tx
24
69
PC5 (1)
PJ1 (1)
O
TTL
UART module 4 transmit.
U5Rx
11
95
PJ2 (1)
PE4 (1)
I
TTL
UART module 5 receive.
U5Tx
96
PE5 (1)
O
TTL
UART module 5 transmit.
U6Rx
97
PD4 (1)
I
TTL
UART module 6 receive.
U6Tx
98
PD5 (1)
O
TTL
UART module 6 transmit.
U7Rx
15
PE0 (1)
I
TTL
UART module 7 receive.
U7Tx
14
PE1 (1)
O
TTL
UART module 7 transmit.
USB0DM
68
PJ0
I/O
Analog
Bidirectional differential data pin (D- per USB
specification) for USB0.
USB0DP
69
PJ1
I/O
Analog
Bidirectional differential data pin (D+ per USB
specification) for USB0.
USB0EPEN
3
23
39
74
PD2 (8)
PC6 (8)
PF4 (8)
PG4 (8)
O
TTL
Optionally used in Host mode to control an external
power source to supply power to the USB bus.
USB0ID
70
PB0
I
Analog
This signal senses the state of the USB ID signal.
The USB PHY enables an integrated pull-up, and
an external element (USB connector) indicates the
initial state of the USB controller (pulled down is
the A side of the cable and pulled up is the B side).
June 12, 2014
1239
Texas Instruments-Production Data
Signal Tables
Table 21-3. Signals by Signal Name (continued)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
USB0PFLT
4
22
37
75
PD3 (8)
PC7 (8)
PF5 (8)
PG5 (8)
I
TTL
Optionally used in Host mode by an external power
source to indicate an error state by that power
source.
USB0VBUS
71
PB1
I/O
Analog
This signal is used during the session request
protocol. This signal allows the USB PHY to both
sense the voltage level of VBUS, and pull up VBUS
momentarily during VBUS pulsing.
VBAT
55
fixed
-
Power
Power source for the Hibernation module. It is
normally connected to the positive terminal of a
battery and serves as the battery
backup/Hibernation module power-source supply.
VDD
5
20
32
44
56
67
80
93
fixed
-
Power
Positive supply for I/O and some logic.
VDDA
7
fixed
-
Power
The positive supply for the analog circuits (ADC,
Analog Comparators, etc.). These are separated
from VDD to minimize the electrical noise contained
on VDD from affecting the analog functions. VDDA
pins must be supplied with a voltage that meets the
specification in Table 22-5 on page 1258, regardless
of system implementation.
VDDC
38
86
fixed
-
Power
Positive supply for most of the logic function,
including the processor core and most peripherals.
The voltage on this pin is 1.2 V and is supplied by
the on-chip LDO. The VDDC pins should only be
connected to each other and an external capacitor
as specified in Table 22-12 on page 1271 .
VREFA+
8
fixed
-
Analog
A reference voltage used to specify the voltage at
which the ADC converts to a maximum value. This
pin is used in conjunction with VREFA-, which
specifies the minimum value . The voltage that is
applied to VREFA+ is the voltage with which an
AINn signal is converted to 4095. The VREFA+
voltage is limited to the range specified in Table
22-33 on page 1287 .
VREFA-
9
fixed
-
Analog
A reference voltage used to specify the input
voltage at which the ADC converts to a minimum
value. This pin is used in conjunction with VREFA+,
which specifies the maximum value. In other words,
the voltage that is applied to VREFA- is the voltage
with which an AINn signal is converted to 0, while
the voltage that is applied to VREFA+ is the voltage
with which an AINn signal is converted to 4095.
The VREFA- voltage is limited to the range specified
in Table 22-33 on page 1287 .
WAKE
50
fixed
I
TTL
An external input that brings the processor out of
Hibernate mode when asserted.
1240
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Table 21-3. Signals by Signal Name (continued)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
WT0CCP0
25
74
PC4 (7)
PG4 (7)
I/O
TTL
32/64-Bit Wide Timer 0 Capture/Compare/PWM 0.
WT0CCP1
24
75
PC5 (7)
PG5 (7)
I/O
TTL
32/64-Bit Wide Timer 0 Capture/Compare/PWM 1.
WT1CCP0
23
87
PC6 (7)
PG6 (7)
I/O
TTL
32/64-Bit Wide Timer 1 Capture/Compare/PWM 0.
WT1CCP1
22
88
PC7 (7)
PG7 (7)
I/O
TTL
32/64-Bit Wide Timer 1 Capture/Compare/PWM 1.
WT2CCP0
1
16
PD0 (7)
PH0 (7)
I/O
TTL
32/64-Bit Wide Timer 2 Capture/Compare/PWM 0.
WT2CCP1
2
17
PD1 (7)
PH1 (7)
I/O
TTL
32/64-Bit Wide Timer 2 Capture/Compare/PWM 1.
WT3CCP0
3
79
PD2 (7)
PH4 (7)
I/O
TTL
32/64-Bit Wide Timer 3 Capture/Compare/PWM 0.
WT3CCP1
4
78
PD3 (7)
PH5 (7)
I/O
TTL
32/64-Bit Wide Timer 3 Capture/Compare/PWM 1.
WT4CCP0
77
97
PH6 (7)
PD4 (7)
I/O
TTL
32/64-Bit Wide Timer 4 Capture/Compare/PWM 0.
WT4CCP1
76
98
PH7 (7)
PD5 (7)
I/O
TTL
32/64-Bit Wide Timer 4 Capture/Compare/PWM 1.
WT5CCP0
18
99
PH2 (7)
PD6 (7)
I/O
TTL
32/64-Bit Wide Timer 5 Capture/Compare/PWM 0.
WT5CCP1
19
100
PH3 (7)
PD7 (7)
I/O
TTL
32/64-Bit Wide Timer 5 Capture/Compare/PWM 1.
XOSC0
52
fixed
I
Analog
Hibernation module oscillator crystal input or an
external clock reference input. Note that this is
either a 32.768-kHz crystal or a 32.768-kHz
oscillator for the Hibernation module RTC.
XOSC1
54
fixed
O
Analog
Hibernation module oscillator crystal output. Leave
unconnected when using a single-ended clock
source.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
June 12, 2014
1241
Texas Instruments-Production Data
Signal Tables
21.3
Signals by Function, Except for GPIO
Table 21-4. Signals by Function, Except for GPIO
Function
ADC
Pin Name
a
Pin Number
Pin Type
Buffer Type
Description
AIN0
12
I
Analog
Analog-to-digital converter input 0.
AIN1
13
I
Analog
Analog-to-digital converter input 1.
AIN2
14
I
Analog
Analog-to-digital converter input 2.
AIN3
15
I
Analog
Analog-to-digital converter input 3.
AIN4
100
I
Analog
Analog-to-digital converter input 4.
AIN5
99
I
Analog
Analog-to-digital converter input 5.
AIN6
98
I
Analog
Analog-to-digital converter input 6.
AIN7
97
I
Analog
Analog-to-digital converter input 7.
AIN8
96
I
Analog
Analog-to-digital converter input 8.
AIN9
95
I
Analog
Analog-to-digital converter input 9.
AIN10
92
I
Analog
Analog-to-digital converter input 10.
AIN11
91
I
Analog
Analog-to-digital converter input 11.
AIN12
4
I
Analog
Analog-to-digital converter input 12.
AIN13
3
I
Analog
Analog-to-digital converter input 13.
AIN14
2
I
Analog
Analog-to-digital converter input 14.
AIN15
1
I
Analog
Analog-to-digital converter input 15.
AIN16
16
I
Analog
Analog-to-digital converter input 16.
AIN17
17
I
Analog
Analog-to-digital converter input 17.
AIN18
18
I
Analog
Analog-to-digital converter input 18.
AIN19
19
I
Analog
Analog-to-digital converter input 19.
AIN20
90
I
Analog
Analog-to-digital converter input 20.
AIN21
89
I
Analog
Analog-to-digital converter input 21.
VREFA+
8
-
Analog
A reference voltage used to specify the voltage at
which the ADC converts to a maximum value. This
pin is used in conjunction with VREFA-, which
specifies the minimum value . The voltage that is
applied to VREFA+ is the voltage with which an
AINn signal is converted to 4095. The VREFA+
voltage is limited to the range specified in Table
22-33 on page 1287 .
VREFA-
9
-
Analog
A reference voltage used to specify the input
voltage at which the ADC converts to a minimum
value. This pin is used in conjunction with VREFA+,
which specifies the maximum value. In other words,
the voltage that is applied to VREFA- is the voltage
with which an AINn signal is converted to 0, while
the voltage that is applied to VREFA+ is the voltage
with which an AINn signal is converted to 4095.
The VREFA- voltage is limited to the range specified
in Table 22-33 on page 1287 .
1242
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Table 21-4. Signals by Function, Except for GPIO (continued)
Function
Analog Comparators
Controller Area
Network
Core
Pin Name
a
Pin Number
Pin Type
Buffer Type
Description
C0+
23
I
Analog
Analog comparator 0 positive input.
C0-
22
I
Analog
Analog comparator 0 negative input.
C0o
40
O
TTL
C1+
24
I
Analog
Analog comparator 1 positive input.
C1-
25
I
Analog
Analog comparator 1 negative input.
C1o
41
O
TTL
C2+
87
I
Analog
Analog comparator 2 positive input.
C2-
88
I
Analog
Analog comparator 2 negative input.
C2o
42
O
TTL
Analog comparator 2 output.
CAN0Rx
40
92
95
I
TTL
CAN module 0 receive.
CAN0Tx
43
91
96
O
TTL
CAN module 0 transmit.
TRCLK
43
O
TTL
Trace clock.
TRD0
42
O
TTL
Trace data 0.
TRD1
41
O
TTL
Trace data 1.
TRD2
40
O
TTL
Trace data 2.
TRD3
39
O
TTL
Trace data 3.
Analog comparator 0 output.
Analog comparator 1 output.
June 12, 2014
1243
Texas Instruments-Production Data
Signal Tables
Table 21-4. Signals by Function, Except for GPIO (continued)
Function
General-Purpose
Timers
Pin Name
a
Pin Number
Pin Type
Buffer Type
Description
T0CCP0
40
I/O
TTL
16/32-Bit Timer 0 Capture/Compare/PWM 0.
T0CCP1
41
I/O
TTL
16/32-Bit Timer 0 Capture/Compare/PWM 1.
T1CCP0
42
68
92
I/O
TTL
16/32-Bit Timer 1 Capture/Compare/PWM 0.
T1CCP1
43
69
91
I/O
TTL
16/32-Bit Timer 1 Capture/Compare/PWM 1.
T2CCP0
11
39
70
I/O
TTL
16/32-Bit Timer 2 Capture/Compare/PWM 0.
T2CCP1
37
71
I/O
TTL
16/32-Bit Timer 2 Capture/Compare/PWM 1.
T3CCP0
36
72
I/O
TTL
16/32-Bit Timer 3 Capture/Compare/PWM 0.
T3CCP1
58
73
I/O
TTL
16/32-Bit Timer 3 Capture/Compare/PWM 1.
T4CCP0
62
85
I/O
TTL
16/32-Bit Timer 4 Capture/Compare/PWM 0.
T4CCP1
61
84
I/O
TTL
16/32-Bit Timer 4 Capture/Compare/PWM 1.
T5CCP0
60
83
I/O
TTL
16/32-Bit Timer 5 Capture/Compare/PWM 0.
T5CCP1
59
82
I/O
TTL
16/32-Bit Timer 5 Capture/Compare/PWM 1.
WT0CCP0
25
74
I/O
TTL
32/64-Bit Wide Timer 0 Capture/Compare/PWM 0.
WT0CCP1
24
75
I/O
TTL
32/64-Bit Wide Timer 0 Capture/Compare/PWM 1.
WT1CCP0
23
87
I/O
TTL
32/64-Bit Wide Timer 1 Capture/Compare/PWM 0.
WT1CCP1
22
88
I/O
TTL
32/64-Bit Wide Timer 1 Capture/Compare/PWM 1.
WT2CCP0
1
16
I/O
TTL
32/64-Bit Wide Timer 2 Capture/Compare/PWM 0.
WT2CCP1
2
17
I/O
TTL
32/64-Bit Wide Timer 2 Capture/Compare/PWM 1.
WT3CCP0
3
79
I/O
TTL
32/64-Bit Wide Timer 3 Capture/Compare/PWM 0.
WT3CCP1
4
78
I/O
TTL
32/64-Bit Wide Timer 3 Capture/Compare/PWM 1.
WT4CCP0
77
97
I/O
TTL
32/64-Bit Wide Timer 4 Capture/Compare/PWM 0.
WT4CCP1
76
98
I/O
TTL
32/64-Bit Wide Timer 4 Capture/Compare/PWM 1.
WT5CCP0
18
99
I/O
TTL
32/64-Bit Wide Timer 5 Capture/Compare/PWM 0.
WT5CCP1
19
100
I/O
TTL
32/64-Bit Wide Timer 5 Capture/Compare/PWM 1.
1244
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Table 21-4. Signals by Function, Except for GPIO (continued)
Function
Pin Name
a
Pin Number
Pin Type
Buffer Type
Description
GNDX
53
-
Power
GND for the Hibernation oscillator. When using a
crystal clock source, this pin should be connected
to digital ground along with the crystal load
capacitors. When using an external oscillator, this
pin should be connected to digital ground.
HIB
51
O
TTL
VBAT
55
-
Power
Power source for the Hibernation module. It is
normally connected to the positive terminal of a
battery and serves as the battery
backup/Hibernation module power-source supply.
WAKE
50
I
TTL
An external input that brings the processor out of
Hibernate mode when asserted.
XOSC0
52
I
Analog
Hibernation module oscillator crystal input or an
external clock reference input. Note that this is
either a 32.768-kHz crystal or a 32.768-kHz
oscillator for the Hibernation module RTC.
XOSC1
54
O
Analog
Hibernation module oscillator crystal output. Leave
unconnected when using a single-ended clock
source.
I2C0SCL
72
I/O
OD
I2C module 0 clock. Note that this signal has an
active pull-up. The corresponding port pin should
not be configured as open drain.
I2C0SDA
73
I/O
OD
I2C module 0 data.
I2C1SCL
34
74
I/O
OD
I2C module 1 clock. Note that this signal has an
active pull-up. The corresponding port pin should
not be configured as open drain.
I2C1SDA
35
75
I/O
OD
I2C module 1 data.
I2C2SCL
36
95
I/O
OD
I2C module 2 clock. Note that this signal has an
active pull-up. The corresponding port pin should
not be configured as open drain.
I2C2SDA
58
96
I/O
OD
I2C module 2 data.
I2C3SCL
1
62
I/O
OD
I2C module 3 clock. Note that this signal has an
active pull-up. The corresponding port pin should
not be configured as open drain.
I2C3SDA
2
61
I/O
OD
I2C module 3 data.
I2C4SCL
60
I/O
OD
I2C module 4 clock. Note that this signal has an
active pull-up. The corresponding port pin should
not be configured as open drain.
I2C4SDA
59
I/O
OD
I2C module 4 data.
I2C5SCL
87
I/O
OD
I2C module 5 clock. Note that this signal has an
active pull-up. The corresponding port pin should
not be configured as open drain.
I2C5SDA
88
I/O
OD
I2C module 5 data.
Hibernate
I2C
An output that indicates the processor is in
Hibernate mode.
June 12, 2014
1245
Texas Instruments-Production Data
Signal Tables
Table 21-4. Signals by Function, Except for GPIO (continued)
Function
JTAG/SWD/SWO
Pin Name
Pin Number
a
Pin Type
Buffer Type
Description
SWCLK
85
I
TTL
JTAG/SWD CLK.
SWDIO
84
I/O
TTL
JTAG TMS and SWDIO.
SWO
82
O
TTL
JTAG TDO and SWO.
TCK
85
I
TTL
JTAG/SWD CLK.
TDI
83
I
TTL
JTAG TDI.
TDO
82
O
TTL
JTAG TDO and SWO.
TMS
84
I
TTL
JTAG TMS and SWDIO.
GND
6
21
33
45
57
64
81
94
-
Power
Ground reference for logic and I/O pins.
GNDA
10
-
Power
The ground reference for the analog circuits (ADC,
Analog Comparators, etc.). These are separated
from GND to minimize the electrical noise contained
on VDD from affecting the analog functions.
VDD
5
20
32
44
56
67
80
93
-
Power
Positive supply for I/O and some logic.
VDDA
7
-
Power
The positive supply for the analog circuits (ADC,
Analog Comparators, etc.). These are separated
from VDD to minimize the electrical noise contained
on VDD from affecting the analog functions. VDDA
pins must be supplied with a voltage that meets the
specification in Table 22-5 on page 1258, regardless
of system implementation.
VDDC
38
86
-
Power
Positive supply for most of the logic function,
including the processor core and most peripherals.
The voltage on this pin is 1.2 V and is supplied by
the on-chip LDO. The VDDC pins should only be
connected to each other and an external capacitor
as specified in Table 22-12 on page 1271 .
Power
1246
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Table 21-4. Signals by Function, Except for GPIO (continued)
Function
SSI
Pin Name
a
Pin Number
Pin Type
Buffer Type
SSI0Clk
28
I/O
TTL
SSI module 0 clock
SSI0Fss
29
I/O
TTL
SSI module 0 frame signal
SSI0Rx
30
I
TTL
SSI module 0 receive
SSI0Tx
31
O
TTL
SSI module 0 transmit
SSI1Clk
1
42
I/O
TTL
SSI module 1 clock.
SSI1Fss
2
43
I/O
TTL
SSI module 1 frame signal.
SSI1Rx
3
40
I
TTL
SSI module 1 receive.
SSI1Tx
4
41
O
TTL
SSI module 1 transmit.
SSI2Clk
79
92
I/O
TTL
SSI module 2 clock.
SSI2Fss
78
91
I/O
TTL
SSI module 2 frame signal.
SSI2Rx
77
I
TTL
SSI module 2 receive.
SSI2Tx
76
O
TTL
SSI module 2 transmit.
SSI3Clk
1
16
49
I/O
TTL
SSI module 3 clock.
SSI3Fss
2
17
48
I/O
TTL
SSI module 3 frame signal.
SSI3Rx
3
18
47
I
TTL
SSI module 3 receive.
SSI3Tx
4
19
46
O
TTL
SSI module 3 transmit.
NMI
40
100
I
TTL
Non-maskable interrupt.
OSC0
65
I
Analog
Main oscillator crystal input or an external clock
reference input.
OSC1
66
O
Analog
Main oscillator crystal output. Leave unconnected
when using a single-ended clock source.
RST
63
I
TTL
System Control &
Clocks
Description
System reset input.
June 12, 2014
1247
Texas Instruments-Production Data
Signal Tables
Table 21-4. Signals by Function, Except for GPIO (continued)
Function
Pin Name
Pin Number
a
Pin Type
Buffer Type
Description
U0Rx
26
I
TTL
UART module 0 receive.
U0Tx
27
O
TTL
UART module 0 transmit.
U1CTS
24
41
I
TTL
UART module 1 Clear To Send modem flow control
input signal.
U1DCD
42
I
TTL
UART module 1 Data Carrier Detect modem status
input signal.
U1DSR
43
I
TTL
UART module 1 Data Set Ready modem output
control line.
U1DTR
39
O
TTL
UART module 1 Data Terminal Ready modem
status input signal.
U1RI
90
I
TTL
UART module 1 Ring Indicator modem status input
signal.
U1RTS
25
40
O
TTL
UART module 1 Request to Send modem flow
control output line.
U1Rx
25
70
I
TTL
UART module 1 receive.
U1Tx
24
71
O
TTL
UART module 1 transmit.
U2Rx
74
99
I
TTL
UART module 2 receive.
U2Tx
75
100
O
TTL
UART module 2 transmit.
U3Rx
23
I
TTL
UART module 3 receive.
U3Tx
22
O
TTL
UART module 3 transmit.
U4Rx
25
68
I
TTL
UART module 4 receive.
U4Tx
24
69
O
TTL
UART module 4 transmit.
U5Rx
11
95
I
TTL
UART module 5 receive.
U5Tx
96
O
TTL
UART module 5 transmit.
U6Rx
97
I
TTL
UART module 6 receive.
U6Tx
98
O
TTL
UART module 6 transmit.
U7Rx
15
I
TTL
UART module 7 receive.
U7Tx
14
O
TTL
UART module 7 transmit.
UART
1248
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Table 21-4. Signals by Function, Except for GPIO (continued)
Function
Pin Name
a
Pin Number
Pin Type
Buffer Type
USB0DM
68
I/O
Analog
Bidirectional differential data pin (D- per USB
specification) for USB0.
USB0DP
69
I/O
Analog
Bidirectional differential data pin (D+ per USB
specification) for USB0.
USB0EPEN
3
23
39
74
O
TTL
Optionally used in Host mode to control an external
power source to supply power to the USB bus.
USB0ID
70
I
Analog
This signal senses the state of the USB ID signal.
The USB PHY enables an integrated pull-up, and
an external element (USB connector) indicates the
initial state of the USB controller (pulled down is
the A side of the cable and pulled up is the B side).
USB0PFLT
4
22
37
75
I
TTL
Optionally used in Host mode by an external power
source to indicate an error state by that power
source.
USB0VBUS
71
I/O
Analog
This signal is used during the session request
protocol. This signal allows the USB PHY to both
sense the voltage level of VBUS, and pull up VBUS
momentarily during VBUS pulsing.
USB
Description
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
21.4
GPIO Pins and Alternate Functions
Table 21-5. GPIO Pins and Alternate Functions
a
Digital Function (GPIOPCTL PMCx Bit Field Encoding)
IO
Pin
Analog
Function
1
2
3
4
5
6
7
8
9
14
15
PA0
26
-
U0Rx
-
-
-
-
-
-
-
-
-
-
PA1
27
-
U0Tx
-
-
-
-
-
-
-
-
-
-
PA2
28
-
-
SSI0Clk
-
-
-
-
-
-
-
-
-
PA3
29
-
-
SSI0Fss
-
-
-
-
-
-
-
-
-
PA4
30
-
-
SSI0Rx
-
-
-
-
-
-
-
-
-
PA5
31
-
-
SSI0Tx
-
-
-
-
-
-
-
-
-
PA6
34
-
-
-
I2C1SCL
-
-
-
-
-
-
-
-
PA7
35
-
-
-
I2C1SDA
-
-
-
-
-
-
-
-
PB0
70
USB0ID
U1Rx
-
-
-
-
-
T2CCP0
-
-
-
-
PB1
71
USB0VBUS
U1Tx
-
-
-
-
-
T2CCP1
-
-
-
-
PB2
72
-
-
-
I2C0SCL
-
-
-
T3CCP0
-
-
-
-
-
PB3
73
-
-
-
I2C0SDA
-
-
-
T3CCP1
-
-
-
PB4
92
AIN10
-
SSI2Clk
-
-
-
-
T1CCP0 CAN0Rx
-
-
-
PB5
91
AIN11
-
SSI2Fss
-
-
-
-
T1CCP1 CAN0Tx
-
-
-
PC0
85
-
TCK
SWCLK
-
-
-
-
-
T4CCP0
-
-
-
-
PC1
84
-
TMS
SWDIO
-
-
-
-
-
T4CCP1
-
-
-
-
PC2
83
-
TDI
-
-
-
-
-
T5CCP0
-
-
-
-
June 12, 2014
1249
Texas Instruments-Production Data
Signal Tables
Table 21-5. GPIO Pins and Alternate Functions (continued)
a
Digital Function (GPIOPCTL PMCx Bit Field Encoding)
IO
Pin
Analog
Function
1
2
3
4
5
6
7
8
9
14
15
PC3
82
-
TDO
SWO
-
-
-
-
-
T5CCP1
-
-
-
-
PC4
25
C1-
U4Rx
U1Rx
-
-
-
-
WT0CCP0 U1RTS
-
-
-
PC5
24
C1+
U4Tx
U1Tx
-
-
-
-
WT0CCP1 U1CTS
-
-
-
PC6
23
C0+
U3Rx
-
-
-
-
-
WT1CCP0 USB0EPEN
-
-
-
PC7
22
C0-
U3Tx
-
-
-
-
-
WT1CCP1 USB0PFLT
-
-
-
PD0
1
AIN15
SSI3Clk SSI1Clk I2C3SCL
-
-
-
WT2CCP0
-
-
-
-
-
PD1
2
AIN14
SSI3Fss SSI1Fss I2C3SDA
-
-
-
WT2CCP1
-
-
-
PD2
3
AIN13
SSI3Rx SSI1Rx
-
-
-
-
WT3CCP0 USB0EPEN
-
-
-
PD3
4
AIN12
SSI3Tx SSI1Tx
-
-
-
-
WT3CCP1 USB0PFLT
-
-
-
PD4
97
AIN7
U6Rx
-
-
-
-
-
WT4CCP0
-
-
-
-
PD5
98
AIN6
U6Tx
-
-
-
-
-
WT4CCP1
-
-
-
-
PD6
99
AIN5
U2Rx
-
-
-
-
-
WT5CCP0
-
-
-
-
PD7
100
AIN4
U2Tx
-
-
-
-
-
WT5CCP1
NMI
-
-
-
PE0
15
AIN3
U7Rx
-
-
-
-
-
-
-
-
-
-
PE1
14
AIN2
U7Tx
-
-
-
-
-
-
-
-
-
-
PE2
13
AIN1
-
-
-
-
-
-
-
-
-
-
-
PE3
12
AIN0
-
-
-
-
-
-
-
-
-
-
-
PE4
95
AIN9
U5Rx
-
I2C2SCL
-
-
-
-
CAN0Rx
-
-
-
PE5
96
AIN8
U5Tx
-
I2C2SDA
-
-
-
-
CAN0Tx
-
-
-
PE6
89
AIN21
-
-
-
-
-
-
-
-
-
-
-
PE7
90
AIN20
U1RI
-
-
-
-
-
-
-
-
-
-
PF0
40
-
U1RTS
SSI1Rx CAN0Rx
-
-
-
T0CCP0
NMI
C0o
TRD2
-
PF1
41
-
U1CTS
SSI1Tx
-
-
-
-
T0CCP1
-
C1o
TRD1
-
PF2
42
-
U1DCD
SSI1Clk
-
-
-
-
T1CCP0
-
C2o
TRD0
-
PF3
43
-
U1DSR
SSI1Fss CAN0Tx
-
-
-
T1CCP1
-
-
TRCLK
-
PF4
39
-
U1DTR
-
-
-
-
T2CCP0 USB0EPEN
-
TRD3
-
PF5
37
-
-
-
-
-
-
-
T2CCP1 USB0PFLT
-
-
-
PF6
36
-
-
-
I2C2SCL
-
-
-
T3CCP0
-
-
-
-
PF7
58
-
-
-
I2C2SDA
-
-
-
T3CCP1
-
-
-
-
PG0
62
-
-
-
I2C3SCL
-
-
-
T4CCP0
-
-
-
-
PG1
61
-
-
-
I2C3SDA
-
-
-
T4CCP1
-
-
-
-
PG2
60
-
-
-
I2C4SCL
-
-
-
T5CCP0
-
-
-
-
PG3
59
-
-
-
I2C4SDA
-
-
-
T5CCP1
-
-
-
-
PG4
74
-
U2Rx
-
I2C1SCL
-
-
-
WT0CCP0 USB0EPEN
-
-
-
-
PG5
75
-
U2Tx
-
I2C1SDA
-
-
-
WT0CCP1 USB0PFLT
-
-
-
PG6
87
C2+
-
-
I2C5SCL
-
-
-
WT1CCP0
-
-
-
-
PG7
88
C2-
-
-
I2C5SDA
-
-
-
WT1CCP1
-
-
-
-
PH0
16
AIN16
-
SSI3Clk
-
-
-
-
WT2CCP0
-
-
-
-
PH1
17
AIN17
-
SSI3Fss
-
-
-
-
WT2CCP1
-
-
-
-
1250
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Table 21-5. GPIO Pins and Alternate Functions (continued)
a
Digital Function (GPIOPCTL PMCx Bit Field Encoding)
IO
Pin
Analog
Function
1
2
3
4
5
6
7
8
9
14
15
PH2
18
AIN18
-
SSI3Rx
-
-
-
-
WT5CCP0
-
-
-
-
PH3
19
AIN19
-
SSI3Tx
-
-
-
-
WT5CCP1
-
-
-
-
PH4
79
-
-
SSI2Clk
-
-
-
-
WT3CCP0
-
-
-
-
PH5
78
-
-
SSI2Fss
-
-
-
-
WT3CCP1
-
-
-
-
PH6
77
-
-
SSI2Rx
-
-
-
-
WT4CCP0
-
-
-
-
PH7
76
-
-
SSI2Tx
-
-
-
-
WT4CCP1
-
-
-
-
PJ0
68
USB0DM
U4Rx
-
-
-
-
-
T1CCP0
-
-
-
-
PJ1
69
USB0DP
U4Tx
-
-
-
-
-
T1CCP1
-
-
-
-
PJ2
11
-
U5Rx
-
-
-
-
-
T2CCP0
-
-
-
-
PK0
49
-
-
SSI3Clk
-
-
-
-
-
-
-
-
-
PK1
48
-
-
SSI3Fss
-
-
-
-
-
-
-
-
-
PK2
47
-
-
SSI3Rx
-
-
-
-
-
-
-
-
-
PK3
46
-
-
SSI3Tx
-
-
-
-
-
-
-
-
-
a. The digital signals that are shaded gray are the power-on default values for the corresponding GPIO pin. Encodings 10-13 are not used
on this device.
June 12, 2014
1251
Texas Instruments-Production Data
Signal Tables
21.5
Possible Pin Assignments for Alternate Functions
Table 21-6. Possible Pin Assignments for Alternate Functions
# of Possible Assignments
one
Alternate Function
GPIO Function
AIN0
PE3
AIN1
PE2
AIN10
PB4
AIN11
PB5
AIN12
PD3
AIN13
PD2
AIN14
PD1
AIN15
PD0
AIN16
PH0
AIN17
PH1
AIN18
PH2
AIN19
PH3
AIN2
PE1
AIN20
PE7
AIN21
PE6
AIN3
PE0
AIN4
PD7
AIN5
PD6
AIN6
PD5
AIN7
PD4
AIN8
PE5
AIN9
PE4
C0+
PC6
C0-
PC7
C0o
PF0
C1+
PC5
C1-
PC4
C1o
PF1
C2+
PG6
C2-
PG7
C2o
PF2
I2C0SCL
PB2
I2C0SDA
PB3
I2C4SCL
PG2
I2C4SDA
PG3
I2C5SCL
PG6
I2C5SDA
PG7
SSI0Clk
PA2
SSI0Fss
PA3
1252
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Table 21-6. Possible Pin Assignments for Alternate Functions (continued)
# of Possible Assignments
Alternate Function
GPIO Function
SSI0Rx
PA4
SSI0Tx
PA5
SSI2Rx
PH6
SSI2Tx
PH7
SWCLK
PC0
SWDIO
PC1
SWO
PC3
T0CCP0
PF0
T0CCP1
PF1
TCK
PC0
TDI
PC2
TDO
PC3
TMS
PC1
TRCLK
PF3
TRD0
PF2
TRD1
PF1
TRD2
PF0
TRD3
PF4
U0Rx
PA0
U0Tx
PA1
U1DCD
PF2
U1DSR
PF3
U1DTR
PF4
U1RI
PE7
U3Rx
PC6
U3Tx
PC7
U5Tx
PE5
U6Rx
PD4
U6Tx
PD5
U7Rx
PE0
U7Tx
PE1
USB0DM
PJ0
USB0DP
PJ1
USB0ID
PB0
USB0VBUS
PB1
June 12, 2014
1253
Texas Instruments-Production Data
Signal Tables
Table 21-6. Possible Pin Assignments for Alternate Functions (continued)
# of Possible Assignments
two
Alternate Function
GPIO Function
I2C1SCL
PA6 PG4
I2C1SDA
PA7 PG5
I2C2SCL
PE4 PF6
I2C2SDA
PE5 PF7
I2C3SCL
PD0 PG0
I2C3SDA
PD1 PG1
NMI
PD7 PF0
SSI1Clk
PD0 PF2
SSI1Fss
PD1 PF3
SSI1Rx
PD2 PF0
SSI1Tx
PD3 PF1
SSI2Clk
PB4 PH4
SSI2Fss
PB5 PH5
T2CCP1
PB1 PF5
T3CCP0
PB2 PF6
T3CCP1
PB3 PF7
T4CCP0
PC0 PG0
T4CCP1
PC1 PG1
T5CCP0
PC2 PG2
T5CCP1
PC3 PG3
U1CTS
PC5 PF1
U1RTS
PC4 PF0
U1Rx
PB0 PC4
U1Tx
PB1 PC5
U2Rx
PD6 PG4
U2Tx
PD7 PG5
U4Rx
PC4 PJ0
U4Tx
PC5 PJ1
U5Rx
PE4 PJ2
WT0CCP0
PC4 PG4
WT0CCP1
PC5 PG5
WT1CCP0
PC6 PG6
WT1CCP1
PC7 PG7
WT2CCP0
PD0 PH0
WT2CCP1
PD1 PH1
WT3CCP0
PD2 PH4
WT3CCP1
PD3 PH5
WT4CCP0
PD4 PH6
WT4CCP1
PD5 PH7
WT5CCP0
PD6 PH2
WT5CCP1
PD7 PH3
1254
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Table 21-6. Possible Pin Assignments for Alternate Functions (continued)
# of Possible Assignments
Alternate Function
GPIO Function
CAN0Rx
PB4 PE4 PF0
CAN0Tx
PB5 PE5 PF3
SSI3Clk
PD0 PH0 PK0
SSI3Fss
PD1 PH1 PK1
SSI3Rx
PD2 PH2 PK2
SSI3Tx
PD3 PH3 PK3
T1CCP0
PB4 PF2 PJ0
T1CCP1
PB5 PF3 PJ1
three
T2CCP0
PB0 PF4 PJ2
USB0EPEN
PC6 PD2 PF4 PG4
USB0PFLT
PC7 PD3 PF5 PG5
four
21.6
Connections for Unused Signals
Table 21-7 on page 1255 shows how to handle signals for functions that are not used in a particular
system implementation for devices that are in a 100-pin LQFP package. Two options are shown in
the table: an acceptable practice and a preferred practice for reduced power consumption and
improved EMC characteristics. If a module is not used in a system, and its inputs are grounded, it
is important that the clock to the module is never enabled by setting the corresponding bit in the
RCGCx register.
Table 21-7. Connections for Unused Signals (100-Pin LQFP)
Function
GPIO
Signal Name
Pin Number
Acceptable Practice
Preferred Practice
All unused GPIOs
-
NC
GND
HIB
51
NC
NC
VBAT
55
NC
VDD
WAKE
50
NC
GND
Hibernate
No Connects
System Control
XOSC0
52
NC
GND
XOSC1
54
NC
NC
GNDX
53
GND
GND
NC
See NC pin numbers in
Table 21-3 on page 1233
NC
NC
OSC0
65
NC
GND
OSC1
66
NC
NC
RST
63
VDD
Pull up as shown in Figure
5-1 on page 210
USB0DM
68
NC
GND
USB0DP
69
NC
GND
USB
June 12, 2014
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Texas Instruments-Production Data
Electrical Characteristics
22
Electrical Characteristics
22.1
Maximum Ratings
The maximum ratings are the limits to which the device can be subjected without permanently
damaging the device. Device reliability may be adversely affected by exposure to absolute-maximum
ratings for extended periods.
Note:
The device is not guaranteed to operate properly at the maximum ratings.
Table 22-1. Absolute Maximum Ratings
Value
a
Parameter
Parameter Name
VDD
VDD supply voltage
b
Unit
Min
Max
0
4
V
VDDA
VDDA supply voltage
0
4
V
VBAT
VBAT battery supply voltage
0
4
V
VBAT battery supply voltage ramp time
0
0.7
V/µs
Input voltage on GPIOs, regardless of whether the
cde
microcontroller is powered
-0.3
5.5
V
Input voltage for PJ0, PJ1, PB0 and PB1 when
configured as GPIO
-0.3
VDD + 0.3
V
-
25
mA
-65
150
°C
-
150
°C
VBATRMP
VIN_GPIO
IGPIOMAX
TS
TJMAX
Maximum current per output pin
Unpowered storage temperature range
Maximum junction temperature
a. Voltages are measured with respect to GND.
b. To ensure proper operation, VDDA must be powered before VDD if sourced from different supplies, or connected to the
same supply as VDD. Note that the minimum operating voltage for VDD differs from the minimum operating voltage for
VDDA. This change should be accounted for in the system design if both are sourced from the same supply. There is
not a restriction on order for powering off.
c. Applies to static and dynamic signals including overshoot.
d. Refer to Figure 22-16 on page 1284 for a representation of the ESD protection on GPIOs.
e. For additional details, see the note on GPIO pad tolerance in “GPIO Module Characteristics” on page 1283.
Important: This device contains circuitry to protect the I/Os against damage due to high-static
voltages; however, it is advised that normal precautions be taken to avoid application
of any voltage higher than maximum-rated voltages to this high-impedance circuit.
Reliability of operation is enhanced if unused inputs are connected to an appropriate
logic voltage level (see “Connections for Unused Signals” on page 1255).
Table 22-2. ESD Absolute Maximum Ratings
Parameter
Component-Level ESD
a
Stress Voltage
Min
Nom
VESDHBM
b
Max
Unit
-
VESDCDM
c
-
-
2.0
kV
-
500
V
a. Electrostatic discharge (ESD) to measure device sensitivity/immunity to damage caused by electrostatic discharges in
device.
b. Level listed is passing level per ANSI/ESDA/JEDEC JS-001. JEDEC document JEP155 states that 500V HBM allows
safe manufacturing with a standard ESD control process.
c. Level listed is the passing level per EIA-JEDEC JESD22-C101E. JEDEC document JEP157 states that 250V CDM allows
safe manufacturing with a standard ESD control process.
1256
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
22.2
Operating Characteristics
Table 22-3. Temperature Characteristics
Characteristic
Symbol Value
Ambient operating temperature range
TA
Unit
-40 to +85
°C
Case operating temperature range
TC
-40 to +93
°C
Junction operating temperature range
TJ
-40 to +95
°C
a
Table 22-4. Thermal Characteristics
Characteristic
Symbol Value
b
Thermal resistance (junction to ambient) ΘJA
b
Unit
48.8
°C/W
Thermal resistance (junction to board)
ΘJB
26.5
°C/W
Thermal resistance (junction to case)
b
ΘJC
8.9
°C/W
Thermal metric (junction to top of
package)
ΨJT
0.2
°C/W
Thermal metric (junction to board)
ΨJB
26.1
°C/W
Junction temperature formula
TJ
TC + (P • ΨJT)
°C
c
TPCB + (P • ΨJB)
d
TA + (P • ΘJA)
ef
TB + (P • ΘJB)
a. For more details about thermal metrics and definitions, see the Semiconductor and IC Package Thermal Metrics Application
Report (literature number SPRA953).
b. Junction to ambient thermal resistance (ΘJA), junction to board thermal resistance (ΘJB), and junction to case thermal
resistance (ΘJC) numbers are determined by a package simulator.
c. TPCB is the temperature of the board acquired by following the steps listed in the EAI/JESD 51-8 standard summarized in
the Semiconductor and IC Package Thermal Metrics Application Report (literature number SPRA953).
d. Because ΘJA is highly variable and based on factors such as board design, chip/pad size, altitude, and external ambient
temperature, it is recommended that equations containing ΨJT and ΨJB be used for best results.
e. TB is temperature of the board.
f. ΘJB is not a pure reflection of the internal resistance of the package because it includes the resistance of the testing board
and environment. It is recommended that equations containing ΨJT and ΨJB be used for best results.
June 12, 2014
1257
Texas Instruments-Production Data
Electrical Characteristics
22.3
Recommended Operating Conditions
For special high-current applications, the GPIO output buffers may be used with the following
restrictions. With the GPIO pins configured as 8-mA output drivers, a total of four GPIO outputs may
be used to sink current loads up to 18 mA each. At 18-mA sink current loading, the VOL value is
specified as 1.2 V. The high-current GPIO package pins must be selected such that there are only
a maximum of two per side of the physical package with the total number of high-current GPIO
outputs not exceeding four for the entire package.
Table 22-5. Recommended DC Operating Conditions
Parameter
Parameter Name
Min
Nom
Max
Unit
VDD
VDD supply voltage
3.15
3.3
3.63
V
VDDA
VDDA supply voltage
2.97
3.3
3.63
V
VDDC
VDDC supply voltage
1.08
1.2
1.32
V
VDDC supply voltage, Deep-sleep mode
1.08
-
1.32
V
ab
VDDCDS
a. These values are valid when LDO is in operation.
b. There are peripheral timing restrictions for SSI and LPC in Deep-sleep mode. Please refer to those peripheral characteristic
sections for more information.
Table 22-6. Recommended GPIO Pad Operating Conditions
Parameter
Parameter Name
Min
Nom
Max
Unit
VIH
GPIO high-level input voltage
0.65 * VDD
-
5.5
V
VIL
GPIO low-level input voltage
0
-
0.35 * VDD
V
-
V
VHYS
GPIO input hysteresis
0.2
-
VOH
GPIO high-level output voltage
2.4
-
-
V
VOL
GPIO low-level output voltage
-
-
0.4
V
2-mA Drive
2.0
-
-
mA
4-mA Drive
4.0
-
-
mA
8-mA Drive
8.0
-
-
mA
2-mA Drive
2.0
-
-
mA
4-mA Drive
4.0
-
-
mA
8-mA Drive
8.0
-
-
mA
8-mA Drive, VOL=1.2 V
18.0
-
-
mA
a
High-level source current, VOH=2.4 V
IOH
a
Low-level sink current, VOL=0.4 V
IOL
a. IO specifications reflect the maximum current where the corresponding output voltage meets the VOH/VOL thresholds. IO
current can exceed these limits (subject to absolute maximum ratings).
a
Table 22-7. GPIO Current Restrictions
Parameter
IMAXL
IMAXB
Parameter Name
Min
Nom
Max
Unit
-
-
70
mA
b
-
-
70
mA
b
b
Cumulative maximum GPIO current per side, left
Cumulative maximum GPIO current per side, bottom
IMAXR
Cumulative maximum GPIO current per side, right
-
-
75
mA
IMAXT
Cumulative maximum GPIO current per side, top
b
-
-
70
mA
a. Based on design simulations, not tested in production.
b. Sum of sink and source current for GPIOs as shown in Table 22-8 on page 1259.
1258
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Table 22-8. GPIO Package Side Assignments
Side
GPIOs
Left
PC[4-7], PD[0-3], PE[0-3], PH[0-3], PJ2
Bottom
Right
Top
PA[0-7], PF[0-6], PK[0-3]
PB[0-3], PF7, PG[0-5], PJ[0-1]
PB[4-5], PC[0-3], PD[4-7], PE[4-7], PG[6-7], PH[4-7]
June 12, 2014
1259
Texas Instruments-Production Data
Electrical Characteristics
22.4
Load Conditions
Unless otherwise specified, the following conditions are true for all timing measurements.
Figure 22-1. Load Conditions
CL = 50 pF
pin
GND
1260
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
22.5
JTAG and Boundary Scan
Table 22-9. JTAG Characteristics
Parameter
No.
Parameter
Parameter Name
J1
FTCK
TCK operational clock frequency
J2
TTCK
TCK operational clock period
a
Min
Nom
Max
Unit
0
-
10
MHz
100
-
-
ns
J3
TTCK_LOW
TCK clock Low time
-
tTCK/2
-
ns
J4
TTCK_HIGH
TCK clock High time
-
tTCK/2
-
ns
J5
TTCK_R
TCK rise time
0
-
10
ns
J6
TTCK_F
TCK fall time
0
-
10
ns
J7
TTMS_SU
TMS setup time to TCK rise
8
-
-
ns
J8
TTMS_HLD
TMS hold time from TCK rise
4
-
-
ns
J9
TTDI_SU
TDI setup time to TCK rise
18
-
-
ns
J10
TTDI_HLD
TDI hold time from TCK rise
4
TCK fall to Data Valid from High-Z, 2-mA drive
TCK fall to Data Valid from High-Z, 4-mA drive
J11
TTDO_ZDV
TCK fall to Data Valid from High-Z, 8-mA drive
-
TTDO_DV
TTDO_DVZ
ns
ns
9
26
ns
8
26
ns
10
29
ns
TCK fall to Data Valid from Data Valid, 2-mA drive
14
20
ns
10
26
ns
8
21
ns
TCK fall to Data Valid from Data Valid, 8-mA drive
with slew rate control
10
26
ns
TCK fall to High-Z from Data Valid, 2-mA drive
7
16
ns
7
16
ns
7
16
ns
8
19
ns
TCK fall to Data Valid from Data Valid, 8-mA drive
-
TCK fall to High-Z from Data Valid, 4-mA drive
J13
35
TCK fall to Data Valid from High-Z, 8-mA drive with
slew rate control
TCK fall to Data Valid from Data Valid, 4-mA drive
J12
13
TCK fall to High-Z from Data Valid, 8-mA drive
-
TCK fall to High-Z from Data Valid, 8-mA drive with
slew rate control
a. A ratio of at least 8:1 must be kept between the system clock and TCK.
Figure 22-2. JTAG Test Clock Input Timing
J2
J3
J4
TCK
J6
J5
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1261
Texas Instruments-Production Data
Electrical Characteristics
Figure 22-3. JTAG Test Access Port (TAP) Timing
TCK
J7
TMS
TDI
J8
J8
TMS Input Valid
TMS Input Valid
J9
J9
J10
TDI Input Valid
J11
TDO
J7
J10
TDI Input Valid
J12
TDO Output Valid
1262
J13
TDO Output Valid
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
22.6
Power and Brown-Out
Table 22-10. Power-On and Brown-Out Levels
Parameter
No.
Parameter
Parameter Name
P1
TVDDA_RISE
P2
TVDD_RISE
P3
a
TVDDC_RISE
P4
VPOR
P5
VVDDA_POK
b
Min
Nom
Max
Unit
Analog Supply Voltage (VDDA) Rise Time
-
-
∞
µs
I/O Supply Voltage (VDD) Rise Time
-
-
∞
µs
Core Supply Voltage (VDDC) Rise Time
10.00
-
150.00
µs
Power-On Reset Threshold
2.00
2.30
2.60
V
VDDA Power-OK Threshold (Rising Edge)
2.70
2.85
3.00
V
VDDA Power-OK Threshold (Falling Edge)
2.71
2.80
2.89
V
VDD Power-OK Threshold (Rising Edge)
2.85
3.00
3.15
V
P6
VVDD_POK
VDD Power-OK Threshold (Falling Edge)
2.70
2.78
2.87
V
P7
VVDD_BOR0
Brown-Out 0 Reset Threshold
2.93
3.02
3.11
V
P8
VVDD_BOR1
Brown-Out 1 Reset Threshold
2.83
2.92
3.01
V
P9
VVDDC_POK
VDDC Power-OK Threshold (Rising Edge)
0.80
0.95
1.10
V
VDDC Power-OK Threshold (Falling Edge)
0.71
0.80
0.89
V
a. The MIN and MAX values are guaranteed by design assuming the external filter capacitor load is within the range of
CLDO. Please refer to “On-Chip Low Drop-Out (LDO) Regulator” on page 1271 for the CLDO value.
b. Digital logic, Flash memory, and SRAM are all designed to operate at VDD voltages below 2.70 V. The internal POK reset
protects the device from unpredictable operation on power down.
22.6.1
VDDA Levels
The VDDA supply has two monitors:
■ Power-On Reset (POR)
■ Power-OK (POK)
The POR monitor is used to keep the analog circuitry in reset until the VDDA supply has reached
the correct range for the analog circuitry to begin operating. The POK monitor is used to keep the
digital circuitry in reset until the VDDA power supply is at an acceptable operational level. The digital
Power-On Reset (Digital POR) is only released when the Power-On Reset has deasserted and
all of the Power-OK monitors for each of the supplies indicate that power levels are in operational
ranges.
Once the VDDA POK monitor has released the digital Power-On Reset on the initial power-up, voltage
drops on the VDDA supply will only be reflected in the following bits. The digital Power-On Reset will
not be re-asserted.
■ VDDARIS bit in the Raw Interrupt Status (RIS) register (see page 238).
■ VDDAMIS bit in the Masked Interrupt Status and Clear (MISC) register (see page 243). This bit
is set only if the VDDAIM bit in the Interrupt Mask Control (IMC) register has been set.
Figure 22-4 on page 1264 shows the relationship between VDDA, POR, POK, and an interrupt event.
June 12, 2014
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Electrical Characteristics
Figure 22-4. Power Assertions versus VDDA Levels
P1
VDDAMIN
22.6.2
POR
1
POK
1
INT
VDDA
P5RISE
P4
1
P5FALL
P4
0
0
0
VDD Levels
The VDD supply has three monitors:
■ Power-OK (POK)
■ Brown-Out Reset0 (BOR0)
■ Brown-Out Reset1 (BOR1)
The POK monitor is used to keep the digital circuitry in reset until the VDD power supply is at an
acceptable operational level. The digital Power-On Reset (Digital POR) is only released when
the Power-On Reset has deasserted and all of the Power-OK monitors for each of the supplies
indicate that power levels are in operational ranges. The BOR0 and the BOR1 monitors are used
to generate a reset to the device or assert an interrupt if the VDD supply drops below its operational
range. The BOR1 monitor's threshold is in between the BOR0 and POK thresholds.
If either a BOR0 event or a BOR1 event occurs, the following bits are affected:
■ BOR0RIS or BOR1RIS bits in the Raw Interrupt Status (RIS) register (see page 238).
■ BOR0MIS or BOR1MIS bits in the Masked Interrupt Status and Clear (MISC) register (see
page 243). These bits are set only if the respective BOR0IM or BOR1IM bits in the Interrupt Mask
Control (IMC) register have been set.
■ BOR bit in the Reset Cause (RESC) register (see page 246). This bit is set only if either of the
BOR0 or BOR1 events have been configured to initiate a reset.
In addition, the following bits control both the BOR0 and BOR1 events:
■ BOR0IM or BOR1IM bits in the Interrupt Mask Control (IMC) register (see page 241).
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June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
■ BOR0 or BOR1 bits in the Power-On and Brown-Out Reset Control (PBORCTL) register (see
page 237).
Figure 22-5 on page 1265 shows the relationship between:
■ VDD, POK, and a BOR0 event
■ VDD, POK, and a BOR1 event
Figure 22-5. Power and Brown-Out Assertions versus VDD Levels
P2
P6RISE
P7
BOR1
BOR0
POK
VDD
VDDMIN
22.6.3
P8
P6FALL
1
0
1
0
1
0
VDDC Levels
The VDDC supply has one monitor: the Power-OK (POK). The POK monitor is used to keep the
digital circuitry in reset until the VDDC power supply is at an acceptable operational level. The digital
Power-On Reset (Digital POR) is only released when the Power-On Reset has deasserted and
all of the Power-OK monitors for each of the supplies indicate that power levels are in operational
ranges. Figure 22-6 on page 1266 shows the relationship between POK and VDDC.
June 12, 2014
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Texas Instruments-Production Data
Electrical Characteristics
Figure 22-6. POK assertion vs VDDC
POK
VDDC
P3
22.6.4
VDDCMIN
P9RISE
P9FALL
1
0
VDD Glitches
Figure 22-7 on page 1266 shows the response of the BOR0, BOR1, and the POR circuit to glitches
on the VDD supply.
Figure 22-7. POR-BOR0-BOR1 VDD Glitch Response
22.6.5
VDD Droop Response
Figure 22-8 on page 1267 shows the response of the BOR0, BOR1, and the POR monitors to a drop
on the VDD supply.
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June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Figure 22-8. POR-BOR0-BOR1 VDD Droop Response
June 12, 2014
1267
Texas Instruments-Production Data
Electrical Characteristics
22.7
Reset
Table 22-11. Reset Characteristics
Parameter
No.
Parameter
R1
TDPORDLY
R2
TIRTOUT
R3
TBOR0DLY
Parameter Name
a
Digital POR to Internal Reset assertion delay
Standard Internal Reset time
Internal Reset time with recovery code repair
b
(program or erase)
Min
Nom
Max
Unit
0.80
-
5.35
µs
-
9
11.5
ms
c
-
-
6400
ms
a
0.25
-
1.95
µs
a
BOR0 to Internal Reset assertion delay
R3
TBOR1DLY
BOR1 to Internal Reset assertion delay
0.75
-
5.95
µs
R4
TRSTMIN
Minimum RST pulse width
-
250
-
ns
R5
TIRHWDLY
RST to Internal Reset assertion delay
-
250
-
ns
R6
TIRSWR
Internal reset timeout after software-initiated
system reset
-
2.07
-
µs
R7
TIRWDR
Internal reset timeout after Watchdog reset
-
2.10
-
µs
R8
TIRMFR
Internal reset timeout after MOSC failure reset
-
1.92
-
µs
a. Timing values are dependent on the VDD power-down ramp rate.
b. This parameter applies only in situations where a power-loss or brown-out event occurs during an EEPROM program or
erase operation, and EEPROM needs to be repaired (which is a rare case). For all other sequences, there is no impact
to normal Power-On Reset (POR) timing. This delay is in addition to other POR delays.
c. This value represents the maximum internal reset time when the EEPROM reaches its endurance limit.
Figure 22-9. Digital Power-On Reset Timing
Digital POR
R1
R2
Reset
(Internal)
Note:
The digital Power-On Reset is only released when the analog Power-On Reset has deasserted
and all of the Power-OK monitors for each of the supplies indicate that power levels are in operational
ranges.
1268
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Figure 22-10. Brown-Out Reset Timing
BOR
R3
R2
Reset
(Internal)
Figure 22-11. External Reset Timing (RST)
R4
RST
(Package Pin)
R5
R2
Reset
(Internal)
Figure 22-12. Software Reset Timing
Software
Reset
R6
Reset
(Internal)
Figure 22-13. Watchdog Reset Timing
Watchdog
Reset
R7
Reset
(Internal)
June 12, 2014
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Texas Instruments-Production Data
Electrical Characteristics
Figure 22-14. MOSC Failure Reset Timing
MOSC Fail
Reset
R8
Reset
(Internal)
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June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
22.8
On-Chip Low Drop-Out (LDO) Regulator
Table 22-12. LDO Regulator Characteristics
Parameter
Parameter Name
Min
Nom
Max
Unit
CLDO
External filter capacitor size for internal power
a
supply
2.5
-
4.0
µF
ESR
Filter capacitor equivalent series resistance
10
-
100
mΩ
ESL
Filter capacitor equivalent series inductance
VLDO
LDO output voltage
IINRUSH
Inrush current
-
-
0.5
nH
1.08
1.2
1.32
V
50
-
250
mA
a. The capacitor should be connected as close as possible to pin 86.
June 12, 2014
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Texas Instruments-Production Data
Electrical Characteristics
22.9
Clocks
The following sections provide specifications on the various clock sources and mode.
22.9.1
PLL Specifications
The following tables provide specifications for using the PLL.
Table 22-13. Phase Locked Loop (PLL) Characteristics
Parameter
FREF_XTAL
Parameter Name
External clock
PLL frequency
Max
Unit
-
25
MHz
5
-
25
MHz
-
400
-
5
a
referencea
FPLL
Nom
a
Crystal reference
FREF_EXT
TREADY
Min
b
MHz
c
reference clocks
c
reference clocks
PLL lock time, enabling the PLL
-
-
512 * (N+1)
PLL lock time, changing the XTAL field in the
RCC/RCC2 register or changing the OSCSRC
between MOSC and PIOSC
-
-
128 * (N+1)
d
d
a. If the PLL is not used, the minimum input frequency can be 4 MHz.
b. PLL frequency is automatically calculated by the hardware based on the XTAL field of the RCC register. The PLL frequency
that is set by the hardware can be calculated using the values in the PLLFREQ0 and PLLFREQ1 registers.
c. N is the value in the N field in the PLLFREQ1 register.
d. A reference clock is the clock period of the crystal being used, which can be MOSC or PIOSC. For example, a 16-MHz
crystal connected to MOSC yields a reference clock of 62.5 ns.
Table 22-14 on page 1272 shows the actual frequency of the PLL based on the crystal frequency used
(defined by the XTAL field in the RCC register).
Table 22-14. Actual PLL Frequency
XTAL
Crystal
Frequency
(MHz)
MINT
MFRAC
Q
N
PLL Multiplier
PLL
Frequency
(MHz)
Error
0x09
5.0
0x50
0x0
0x0
0x0
80
400
-
0x0A
5.12
0x9C
0x100
0x0
0x1
156.25
400
-
0x0B
6.0
0xC8
0x0
0x0
0x2
200
400
-
0x0C
6.144
0xC3
0x140
0x0
0x2
195.3125
400
-
0x0D
7.3728
0xA2
0x30A
0x0
0x2
162.7598
399.9984
0.0004%
0x0E
8.0
0x32
0x0
0x0
0x0
50
400
-
0x0F
8.192
0xC3
0x140
0x0
0x3
195.3125
400
-
0x10
10.0
0x50
0x0
0x0
0x1
80
400
-
0x11
12.0
0xC8
0x0
0x0
0x5
200
400
-
0x12
12.288
0xC3
0x140
0x0
0x5
195.3125
400
-
0x13
13.56
0xB0
0x3F6
0x0
0x5
176.9902
399.9979
0.0005%
0x14
14.318
0xC3
0x238
0x0
0x6
195.5547
399.9982
0.0005%
0x15
16.0
0x32
0x0
0x0
0x1
50
400
-
0x16
16.384
0xC3
0x140
0x0
0x7
195.3125
400
-
0x17
18
0xC8
0x0
0x0
0x8
200
400
-
0x18
20
0x50
0x0
0x0
0x3
80
400
-
0x19
24
0x32
0x0
0x0
0x2
50
400
-
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June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Table 22-14. Actual PLL Frequency (continued)
22.9.2
XTAL
Crystal
Frequency
(MHz)
MINT
MFRAC
Q
N
PLL Multiplier
PLL
Frequency
(MHz)
Error
0x1A
25
0x50
0x0
0x0
0x4
80
400
-
PIOSC Specifications
Table 22-15. PIOSC Clock Characteristics
Parameter
FPIOSC
Parameter Name
Min
Nom
Max
Unit
Factory calibration:
-
-
±3%
-
-
-
±1%
a
-
-
-
1
µs
Internal 16-MHz precision oscillator frequency variance across
the specified voltage and temperature range when factory
calibration is used
Recalibration:
Internal 16-MHz precision oscillator frequency variance when
7-bit recalibration is used
TSTART
b
PIOSC startup time
a. ±1% is only guaranteed at the specific voltage/temperature condition where the recalibration occurs.
b. PIOSC startup time is part of reset and is included in the internal reset timeout value (TIRTOUT) given in Table
22-11 on page 1268. Note that the TSTART value is based on simulation.
22.9.3
Low-Frequency Internal Oscillator (LFIOSC) Specifications
Table 22-16. Low-Frequency internal Oscillator Characteristics
Parameter
FLFIOSC
22.9.4
Parameter Name
Low-frequency internal oscillator (LFIOSC)
frequency
Min
Nom
Max
Unit
10
33
90
KHz
Hibernation Clock Source Specifications
Table 22-17. Hibernation Oscillator Input Characteristics
Parameter
Parameter Name
FHIBLFIOSC
Hibernation low frequency internal oscillator (HIB
LFIOSC) frequency
C1, C2
CINSE
CPKG
CPCB
CSHUNT
Min
Nom
Max
Unit
10
33
90
KHz
External load capacitance on XOSC0, XOSC1 pins
12
-
24
pF
Input capacitance of XOSC0 in single-ended mode
-
-
2
pF
-
0.5
-
pF
a
a
Device package stray shunt capacitance
a
PCB stray shunt capacitance
-
0.5
-
pF
-
-
4
pF
b
-
-
50
kΩ
b
Crystal effective series resistance, OSCDRV = 1
-
-
75
kΩ
Oscillator output drive level
-
-
0.25
µW
-
600
1500
ms
CMOS input high level, when using an external oscillator
with Supply > 3.3 V
2.64
-
-
V
CMOS input high level, when using an external oscillator
with 1.8 V ≤ Supply ≤ 3.3 V
0.8 *
Supply
-
-
V
a
Total shunt capacitance
Crystal effective series resistance, OSCDRV = 0
ESR
DL
TSTART
e
VIH
c
Oscillator startup time, when using a crystal
June 12, 2014
d
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Texas Instruments-Production Data
Electrical Characteristics
Table 22-17. Hibernation Oscillator Input Characteristics (continued)
Parameter
e
VIL
e
VHYS
Parameter Name
Min
Nom
Max
Unit
CMOS input low level, when using an external oscillator
with 1.8 V ≤ Supply ≤ 3.63 V
-
-
0.2 * Supply
V
CMOS input buffer hysteresis, when using an external
oscillator with 1.8 V ≤ Supply ≤ 3.63 V
360
960
1390
mV
30
-
70
%
DCHIBOSC_EXT External clock reference duty cycle
a. See information below table.
b. Crystal ESR specified by crystal manufacturer.
c. Oscillator startup time is specified from the time the oscillator is enabled to when it reaches a stable point of oscillation
such that the internal clock is valid.
d. Only valid for recommended supply conditions. Measured with OSCDRV bit set (high drive strength enabled, 24 pF).
e. Specification is relative to the larger of VDD or VBAT.
The load capacitors added on the board, C1 and C2, should be chosen such that the following
equation is satisfied (see Table 22-17 on page 1273 for typical values).
■ CL = load capacitance specified by crystal manufacturer
■ CL = (C1*C2)/(C1+C2) + CPKG + CPCB
■ CSHUNT = CPKG + CPCB + C0 (total shunt capacitance seen across XOSC0, XOSC1)
■ CPKG, CPCB as measured across the XOSC0, XOSC1 pins excluding the crystal
■ Clear the OSCDRV bit in the Hibernation Control (HIBCTL) register for C1,2 ≤ 18 pF; set the
OSCDRV bit for C1,2 > 18 pF.
■ C0 = Shunt capacitance of crystal specified by the crystal manufacturer
22.9.5
Main Oscillator Specifications
Table 22-18. Main Oscillator Input Characteristics
Parameter
Parameter Name
Min
FMOSC
Parallel resonance frequency
C1, C2
External load capacitance on OSC0, OSC1 pins
CPKG
CPCB
CSHUNT
b
b
Device package stray shunt capacitance
b
PCB stray shunt capacitance
b
Total shunt capacitance
MHz
pF
0.5
-
pF
-
0.5
-
pF
-
-
4
pF
-
300
Ω
cd
-
-
200
Ω
cd
-
-
130
Ω
cd
-
-
120
Ω
cd
-
-
100
Ω
cd
-
-
50
Ω
-
OSCPWR
-
mW
-
-
18
ms
0.65 * VDD
-
VDD
V
Crystal effective series resistance, 12 MHz
Crystal effective series resistance, 16 MHz
Crystal effective series resistance, 25 MHz
VIH
25
24
-
Crystal effective series resistance, 8 MHz
TSTART
-
4
-
Crystal effective series resistance, 6 MHz
DL
Unit
10
Nom
cd
Crystal effective series resistance, 4 MHz
ESR
Max
a
e
Oscillator output drive level
f
Oscillator startup time, when using a crystal
CMOS input high level, when using an external
oscillator
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June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Table 22-18. Main Oscillator Input Characteristics (continued)
Parameter
Parameter Name
Min
Nom
Max
VIL
CMOS input low level, when using an external oscillator
GND
-
0.35 * VDD
V
VHYS
CMOS input buffer hysteresis, when using an external
oscillator
150
-
-
mV
External clock reference duty cycle
45
-
55
%
DCOSC_EXT
Unit
a. 5 MHz is the minimum when using the PLL.
b. See information below table.
c. Crystal ESR specified by crystal manufacturer.
d. Crystal vendors can be contacted to confirm these specifications are met for a specific crystal part number if the vendors
generic crystal datasheet show limits outside of these specifications.
e. OSCPWR = (2 * pi * FP * CL * 2.5)2 * ESR / 2. An estimation of the typical power delivered to the crystal is based on the
CL, FP and ESR parameters of the crystal in the circuit as calculated by the OSCPWR equation. Ensure that the value
calculated for OSCPWR does not exceed the crystal's drive-level maximum.
f. Oscillator startup time is specified from the time the oscillator is enabled to when it reaches a stable point of oscillation
such that the internal clock is valid.
The load capacitors added on the board, C1 and C2, should be chosen such that the following
equation is satisfied (see Table 22-18 on page 1274 for typical values and Table 22-19 on page 1276
for detailed crystal parameter information).
■ CL = load capacitance specified by crystal manufacturer
■ CL = (C1*C2)/(C1+C2) + CSHUNT
■ CSHUNT = C0 + CPKG + CPCB (total shunt capacitance seen across OSC0, OSC1 crystal inputs)
■ CPKG, CPCB = the mutual caps as measured across the OSC0,OSC1 pins excluding the crystal.
■ C0 = Shunt capacitance of crystal specified by the crystal manufacturer
Table 22-19 on page 1276 lists part numbers of crystals that have been simulated and confirmed to
operate within the specifications in Table 22-18 on page 1274. Other crystals that have nearly identical
crystal parameters can be expected to work as well.
In the table below, the crystal parameters labeled C0, C1 and L1 are values that are obtained from
the crystal manufacturer. These numbers are usually a result of testing a relevant batch of crystals
on a network analyzer. The parameters labeled ESR, DL and CL are maximum numbers usually
available in the data sheet for a crystal.
The table also includes three columns of Recommended Component Values. These values apply
to system board components. C1 and C2 are the values in pico Farads of the load capacitors that
should be put on each leg of the crystal pins to ensure oscillation at the correct frequency. Rs is the
value in kΩ of a resistor that is placed in series with the crystal between the OSC1 pin and the crystal
pin. Rs dissipates some of the power so the Max Dl crystal parameter is not exceeded. Only use
the recommended C1, C2, and Rs values with the associated crystal part. The values in the table
were used in the simulation to ensure crystal startup and to determine the worst case drive level
(WC Dl). The value in the WC Dl column should not be greater than the Max Dl Crystal parameter.
The WC Dl value can be used to determine if a crystal with similar parameter values but a lower
Max Dl value is acceptable.
June 12, 2014
1275
Texas Instruments-Production Data
Electrical Characteristics
Crystal Spec
(Tolerance /
Stability)
Max Values
12
0
132
ESR (Ω)
Rs (kΩ)
12
C2 (pF)
8
C1 (pF)
500
CL (pf)
1.00 2.70 598.10 300
Max Dl (µW)
30/50 ppm
L1 (mH)
4
C1 (fF)
8 x 4.5
C0 (pF)
NX8045GB
PKG Size
Freq (MHz)
NX8045GB-
Typical Values
Recommended
Component
Values
(mm x mm)
NDK
Holder
MFG
MFG Part#
Crystal Parameters
WC Dl (μW)
Table 22-19. Crystal Parameters
4.000M-STDCJL-5
FOX
FQ1045A-4
2-SMD
10 x 4.5
4
30/30 ppm
1.18 4.05 396.00 150
500
10
14
14
0
103
NDK
NX8045GB-
NX8045GB
8 x 4.5
5
30/50 ppm
1.00 2.80 356.50 250
500
8
12
12
0
164
NX8045GB
8 x 4.5
6
30/50 ppm
1.30 4.10 173.20 250
500
8
12
12
0
214
5.000M-STDCSF-4
NDK
NX8045GB6.000M-STDCSF-4
FOX
FQ1045A-6
2-SMD
10 x 4.5
6
30/30 ppm
1.37 6.26 112.30 150
500
10
14
14
0
209
NDK
NX8045GB-
NX8045GB
8 x 4.5
8
30/50 ppm
1.00 2.80 139.30 200
500
8
12
12
0
277
4-SMD
7x5
8
30/30 ppm
1.95 6.69 59.10
80
500
10
14
14
0
217
8
50/30 ppm
1.82 4.90 85.70
80
500
16
24
24
0
298
7.2 x 5.2
12
10/20 ppm
2.37 8.85
50
500
10
12
12
2.0
a
124
NX3225GA 3.2 x 2.5
12
20/30 ppm
0.70 2.20 81.00 100
200
8
12
12
2.5
147
NX5032GA
5 x 3.2
12
30/50 ppm
0.93 3.12 56.40 120
500
8
12
12
0
362
4-SMD
5 x 3.2
12
30/30 ppm
1.16 4.16 42.30
500
10
14
14
0
8.000M-STDCSF-6
FOX
FQ7050B-8
ECS
ECS-80-16-
HC49/US 12.5 x 4.85
28A-TR
Abracon AABMM-
ABMM
20.5
12.0000MHz10-D-1-X-T
NDK
NX3225GA12.000MHZSTD-CRG-2
NDK
NX5032GA12.000MHZLN-CD-1
FOX
FQ5032B-12
Abracon AABMM-
ABMM
7.2 x 5.2
80
370
a
143
a
16
10/20 ppm
3.00 11.00 9.30
50
500
10
12
12
2.0
HC-49/UP 13.3 x 4.85
16
15/30 ppm
3.00 12.7
50
1000
10
12
12
2.0
139
NX3225GA 3.2 x 2.5
16
20/30 ppm
1.00 2.90 33.90
80
200
8
12
12
2
188
NX5032GA
16
30/50ppm
1.02 3.82 25.90 120
500
8
10
10
0
437
16.0000MHz10-D-1-X-T
Ecliptek ECX-6595-
8.1
16.000M
NDK
NX3225GA16.000MHZSTD-CRG-2
NDK
NX5032GA-
5 x 3.2
b
16.000MHZLN-CD-1
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Table 22-19. Crystal Parameters (continued)
WC Dl (μW)
Max Values
289
ABMM
7.2 x 5.2
25
10/20 ppm
3.00 11.00 3.70
50
500
10
12
12
2.0
a
158
HC-49/UP 13.3 x 4.85
25
15/30 ppm
3.00 12.8
3.2
40
1000
10
12
12
1.5
a
159
NX3225GA 3.2 x 2.5
25
20/30 ppm
1.10 4.70
8.70
50
200
8
12
12
2
181
10
10
1.0
CL (pf)
C1 (fF)
Rs (kΩ)
0.5
C2 (pF)
12
C1 (pF)
12
Max Dl (µW)
9
ESR (Ω)
300
ECX-42
L1 (mH)
60
ECS-160-9-42-
C0 (pF)
1.47 3.90 25.84
ECS
PKG Size
10/10 ppm
Holder
16
MFG Part#
4 x 2.5
MFG
Freq (MHz)
Typical Values
Recommended
Component
Values
(mm x mm)
Crystal Spec
(Tolerance /
Stability)
Crystal Parameters
CKM-TR
Abracon AABMM25.0000MHz10-D-1-X-T
Ecliptek ECX-659325.000M
NDK
NX3225GA25.000MHZSTD-CRG-2
NX5032GA-
NDK
25.000MHZ-
a
c
216
NX5032GA
5 x 3.2
25
30/50 ppm
1.3
5.1
7.1
70
500
8
12
12
0.75
269
HC3225/4
3.2 x 2.5
25
30/30 ppm
1.58 5.01
8.34
50
500
12
16
16
1
331
4-SMD
5 x 3.2
25
30/30 ppm
1.69 7.92
5.13
50
500
10
14
14
0.5
433
12
c
124
LD-CD-1
AURIS Q-25.000MHC3225/4F-30-30-E-12-TR
FOX
TXC
FQ5032B-25
7A2570018
NX5032GA
5 x 3.2
25
20/25 ppm
2.0
6.7
6.1
30
350
10
12
2.0
a. RS values as low as 0 Ohms can be used. Using a lower RS value will result in the WC DL to increase towards the Max DL of the crystal.
b. Although this ESR value is outside of the recommended crystal ESR maximum for this frequency, this crystal has been simulated to
confirm proper operation and is valid for use with this device.
c. RS values as low as 500 Ohms can be used. Using a lower RS value will result in the WC DL to increase towards the Max DL of the
crystal.
a
Table 22-20. Supported MOSC Crystal Frequencies
Value
Crystal Frequency (MHz) Not Using the PLL
0x00-0x5
0x06
Crystal Frequency (MHz) Using the PLL
reserved
4 MHz
reserved
0x07
4.096 MHz
reserved
0x08
4.9152 MHz
reserved
0x09
5 MHz (USB)
0x0A
5.12 MHz
0x0B
6 MHz (USB)
0x0C
6.144 MHz
0x0D
7.3728 MHz
0x0E
8 MHz (USB)
0x0F
8.192 MHz
0x10
10.0 MHz (USB)
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Table 22-20. Supported MOSC Crystal Frequencies (continued)
Value
Crystal Frequency (MHz) Not Using the PLL
Crystal Frequency (MHz) Using the PLL
0x11
12.0 MHz (USB)
0x12
12.288 MHz
0x13
13.56 MHz
0x14
14.31818 MHz
0x15
16.0 MHz (reset value)(USB)
0x16
16.384 MHz
0x17
18.0 MHz (USB)
0x18
20.0 MHz (USB)
0x19
24.0 MHz (USB)
0x1A
25.0 MHz (USB)
a. Frequencies that may be used with the USB interface are indicated in the table.
22.9.6
System Clock Specification with ADC Operation
Table 22-21. System Clock Characteristics with ADC Operation
Parameter
Fsysadc
Parameter Name
System clock frequency when the ADC
a
module is operating (when PLL is bypassed).
Min
Nom
Max
Unit
15.9952
16
16.0048
MHz
a. Clock frequency (plus jitter) must be stable inside specified range. ADC can be clocked from the PLL, directly from an
external clock source, or from the PIOSC, as long as frequency absolute precision is inside specified range.
22.9.7
System Clock Specification with USB Operation
Table 22-22. System Clock Characteristics with USB Operation
Parameter
Fsysusb
Parameter Name
System clock frequency when the USB module is
operating (note that MOSC must be the clock source,
either with or without using the PLL)
1278
Min
Nom
Max
Unit
20
-
-
MHz
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Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
22.10
Sleep Modes
a
Table 22-23. Sleep Modes AC Characteristics
Parameter
No
Parameter
Min
Nom
Max
Unit
Time to wake from interrupt in sleep mode
-
-
2
system
clocks
Time to wake from interrupt in deep-sleep mode,
using PIOSC for both Run mode and Deep-sleep
bc
mode
-
1.25
-
µs
Time to wake from interrupt in deep-sleep mode,
using PIOSC for Run mode and LFIOSC for
bc
Deep-sleep mode
-
350
-
µs
TWAKE_PLL_DS Time to wake from interrupt in deep-sleep mode
b
when using the PLL
-
-
TREADY
ms
TWAKE_S
D1
TWAKE_DS
D2
Parameter Name
b
a. Values in this table assume the LFIOSC is the clock source during sleep or deep-sleep mode.
b. Specified from registering the interrupt to first instruction.
c. If the main oscillator is used for run mode, add the main oscillator startup time, TSTART.
ab
Table 22-24. Time to Wake with Respect to Low-Power Modes
Mode
Sleep/Deep-Sleep
Run Mode
Mode
FLASHPM SRAMPM
Clock/Frequency
Clock/Frequency
0x0
Sleep
MOSC, PLL on 80MHz
MOSC, PLL on 80MHz
0x2
Time to Wake
Unit
Min
Max
0x0
0.28
0.30
µs
0x1
33.57
35.00
µs
0x3
33.75
35.05
µs
0x0
105.02
109.23
µs
0x1
137.85
143.93
µs
0x3
138.06
143.86
µs
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Table 22-24. Time to Wake with Respect to Low-Power Modes (continued)
Mode
Sleep/Deep-Sleep
Run Mode
Mode
FLASHPM SRAMPM
Clock/Frequency
Clock/Frequency
0x0
MOSC, PLL on 80MHz
PIOSC - 16MHz
0x2
0x0
PIOSC - 16MHz
PIOSC - 16MHz
0x2
Deep-Sleep
0x0
PIOSC - 16MHz
LFIOSC, PIOSC
c
off - 30kHz
0x2
0x0
MOSC, PLL on 80MHz
LFIOSC, PIOSC
c
off - 30kHz
0x2
Time to Wake
Unit
Min
Max
0x0
2.47
2.60
µs
0x1
35.31
36.35
µs
0x3
35.40
36.76
µs
0x0
107.05
111.54
µs
0x1
139.34
145.64
µs
0x3
140.41
145.53
µs
0x0
2.47
2.61
µs
0x1
35.25
36.65
µs
0x3
35.38
36.79
µs
0x0
107.43
111.52
µs
0x1
139.83
145.85
µs
0x3
139.35
145.54
µs
0x0
415.06
728.38
µs
0x1
436.60
740.88
µs
0x3
433.80
755.32
µs
0x0
503.73
812.82
µs
0x1
537.72
846.23
µs
0x3
536.10
839.25
µs
0x0
18.95
19.55
ms
0x1
18.94
19.54
ms
0x3
18.95
19.53
ms
0x0
18.95
19.54
ms
0x1
18.94
19.53
ms
0x3
18.95
19.54
ms
a. Time from wake event to first instruction of code execution.
b. If the LDO voltage is adjusted, it will take an extra 4 us to wake up from Sleep or Deep-sleep mode.
c. PIOSC is turned off by setting the PIOSCPD bit in the DSLPCLKCFG register.
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Tiva™ TM4C1237H6PZ Microcontroller
22.11
Hibernation Module
The Hibernation module requires special system implementation considerations because it is intended
to power down all other sections of its host device, refer to “Hibernation Module” on page 478.
Table 22-25. Hibernation Module Battery Characteristics
Parameter
VBAT
b
VBATRMP
VLOWBAT
Parameter Name
Min
Nominal
Max
Battery supply voltage
1.8
3.0
3.6
V
0
-
0.7
V/µs
Low battery detect voltage, VBATSEL=0x0
1.8
1.9
2.0
V
Low battery detect voltage, VBATSEL=0x1
2.0
2.1
2.2
V
Low battery detect voltage, VBATSEL=0x2
2.2
2.3
2.4
V
Low battery detect voltage, VBATSEL=0x3
2.4
2.5
2.6
V
VBAT battery supply voltage ramp time
a
Unit
a. To ensure proper functionality, any voltage input within the range of 3.6 V < VBAT ≤ 4 V must be connected through a
diode.
b. For recommended VBAT RC circuit values, refer to the diagrams located in“Hibernation Clock Source” on page 481.
Table 22-26. Hibernation Module AC Characteristics
Parameter
No
Parameter
H1
TWAKE
H2
TWAKE_TO_HIB
H3
H4
Parameter Name
Min
Nom
Max
Unit
100
-
-
ns
WAKE assert to HIB desassert
(wake up time)
-
-
1
hibernation
clock period
TVDD_RAMP
VDD ramp to 3.0 V
-
Depends on
characteristics of
power supply
-
μs
TVDD_CODE
VDD at 3.0 V to internal POR
deassert; first instruction executes
-
-
500
μs
WAKE assertion time
Figure 22-15. Hibernation Module Timing
H1
WAKE
H2
HIB
H3
VDD
H4
POR
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22.12
Flash Memory and EEPROM
Table 22-27. Flash Memory Characteristics
Parameter
PECYC
TRET
TPROG64
TERASE
TME
Parameter Name
a
Number of program/erase cycles before failure
Min
Nom
Max
Unit
100,000
-
-
cycles
Data retention, -40˚C to +85˚C
20
-
-
years
Program time for double-word-aligned 64 bits of
b
data
30
50
300
µs
Page erase time, 1.
b. If programming fewer than 64 bits of data, the programming time is the same. For example, if only 32 bits of data need
to be programmed, the other 32 bits are masked off.
a
Table 22-28. EEPROM Characteristics
Parameter Parameter Name
b
EPECYC
ETRET
ETPROG
ETREAD
ETME
Min
Number of mass program/erase cycles of a single word before 500,000
c
failure
Data retention, -40˚C to +85˚C
Nom
Max
Unit
-
-
cycles
20
-
-
years
Program time for 32 bits of data - space available
-
110
600
μs
Program time for 32 bits of data - requires a copy to the copy
buffer, copy buffer has space and less than 10% of EEPROM
endurance used
-
30
-
ms
Program time for 32 bits of data - requires a copy to the copy
buffer, copy buffer has space and greater than 90% of
EEPROM endurance used
-
-
900
ms
Program time for 32 bits of data - requires a copy to the copy
buffer, copy buffer requires an erase and less than 10% of
EEPROM endurance used
-
60
-
ms
Program time for 32 bits of data - requires a copy to the copy
buffer, copy buffer requires an erase and greater than 90% of
EEPROM endurance used
-
-
1800
ms
Read access time
-
4
-
system clocks
Mass erase time, 0 -> 1.
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22.13
Input/Output Pin Characteristics
22.13.1
GPIO Module Characteristics
Note:
All GPIO signals are 5-V tolerant when configured as inputs except for PJ0, PJ1, PB0 and
PB1, which are limited to 3.6 V. See “Signal Description” on page 634 for more information
on GPIO configuration.
Note:
GPIO pads are tolerant to 5-V digital inputs without creating reliability issues, as long as
the supply voltage, VDD, is present. There are limitations to how long a 5-V input can be
present on any given I/O pad if VDD is not present. Not meeting these conditions will affect
reliability of the device and affect the GPIO characteristics specifications.
■ If the voltage applied to a GPIO pad is in the high voltage range (5V +/- 10%) while VDD
is not present, such condition should be allowed for a maximum of 10,000 hours at 27°C
or 5,000 hours at 85°C, over the lifetime of the device.
■ If the voltage applied to a GPIO pad is in the normal voltage range (3.3V +/- 10%) while
VDD is not present or if the voltage applied is in the high voltage range (5V +/- 10%)
while VDD is present, there are no constraints on the lifetime of the device.
a
Table 22-29. GPIO Module Characteristics
Parameter Parameter Name
CGPIO
Min
Max
Unit
-
8
-
pF
RGPIOPU
GPIO internal pull-up resistor
13
20
30
kΩ
RGPIOPD
GPIO internal pull-down resistor
13
20
35
kΩ
GPIO input leakage current, 0 V ≤ VIN ≤ VDD GPIO
b
pins
-
-
1.0
µA
GPIO input leakage current, 0 V < VIN ≤ VDD, GPIO
pins configured as ADC or analog comparator inputs
-
-
2.0
µA
14.2
16.1
ns
11.9
15.5
ns
8.1
11.2
ns
9.5
11.8
ns
25.2
29.4
ns
13.3
16.8
ns
8.6
11.2
ns
11.3
12.9
ns
ILKG+
GPIO Digital Input Capacitance
Nom
c
GPIO rise time, 2-mA drive
c
TGPIOR
GPIO rise time, 4-mA drive
-
c
GPIO rise time, 8-mA drive
c
GPIO rise time, 8-mA drive with slew rate control
d
GPIO fall time, 2-mA drive
d
TGPIOF
GPIO fall time, 4-mA drive
-
d
GPIO fall time, 8-mA drive
d
GPIO fall time, 8-mA drive with slew rate control
a. VDD must be within the range specified in Table 22-5 on page 1258.
b. The leakage current is measured with VIN applied to the corresponding pin(s). The leakage of digital port pins is measured
individually. The port pin is configured as an input and the pull-up/pull-down resistor is disabled.
c. Time measured from 20% to 80% of VDD.
d. Time measured from 80% to 20% of VDD.
22.13.2
Types of I/O Pins and ESD Protection
With respect to ESD and leakage current, three types of I/O pins exist on the device: Power I/O
pins, I/O pins with fail-safe ESD protection (GPIOs other than PJ0 and PJ1, and XOSCn pins) and
I/O pins with non-fail-safe ESD protection (any non-power, non-GPIO (other than PJ0 and PJ1) and
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Electrical Characteristics
non-XOSCn pins). This section covers I/O pins with fail-safe ESD protection and I/O pins with
non-fail-safe ESD protection. Power I/O pin voltage and current limitations are specified in
“Recommended Operating Conditions” on page 1258.
22.13.2.1 Fail-Safe Pins
GPIOs other than PJ0 and PJ1, pins for the Hibernate 32-kHz oscillator (XOSCn), Hibernate input
pins, and I/O pins for the USB PHY use ESD protection as shown in Figure 22-16 on page 1284.
An unpowered device cannot be parasitically powered through any of these pins. This ESD protection
prevents a direct path between these I/O pads and any power supply rails in the device. GPIO/XOSCn
pad input voltages should be kept inside the maximum ratings specified in Table 22-1 on page 1256
to ensure current leakage and current injections are within acceptable range. Current leakages and
current injection for these pins are specified in Table 22-29 on page 1283.
Figure 22-16 on page 1284 shows a diagram of the ESD protection on fail-safe pins.
Some GPIOs when configured as inputs require a strong pull-up resistor to maintain a threshold
above the minimum value of VIH during power-on. See Table 22-31 on page 1285.
Figure 22-16. ESD Protection on Fail-Safe Pins
VDD
I/O Pad
ESD
Clamp
GND
a
Table 22-30. Pad Voltage/Current Characteristics for Fail-Safe Pins
Parameter
Parameter Name
bb
ILKG+
GPIO input leakage current, VDD< VIN ≤ 4.5 V
bc
GPIO input leakage current, 4.5 V < VIN ≤ 5.5 V
bd
ILKGIINJ+
IINJ-
GPIO input leakage current, VIN < -0.3 V
b
GPIO input leakage current, -0.3 V ≤ VIN < 0 V
fg
DC injection current, VDD < VIN ≤ 5.5 V
g
DC injection current, VIN ≤ 0 V
Min
Nom
Max
Unit
-
-
700
µA
-
-
100
µA
-
-
e
-
µA
-
-
10
µA
-
-
ILKG+
µA
-
-
0.5
mA
a. VIN must be within the range specified in Table 22-1 on page 1256.
b. To protect internal circuitry from over-voltage, the GPIOs have an internal voltage clamp that limits internal swings to VDD
without affecting swing at the I/O pad. This internal clamp starts turning on while VDD < VIN < 4.5 V and causes a somewhat
larger (but bounded) current draw. To save power, static input voltages between VDD and 4.5 V should be avoided.
c. Leakage current above maximum voltage (VIN = 5.5V) is not guaranteed, this condition is not allowed and can result in
permanent damage to the device.
d. Leakage outside the minimum range (-0.3V) is unbounded and must be limited to IINJ- using an external resistor.
e. In this case, ILKG- is unbounded and must be limited to IINJ- using an external resistor.
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f. Current injection is internally bounded for GPIOs, and maximum current into the pin is given by ILKG+ for VDD < VIN < 5.5
V.
g. If the I/O pad is not voltage limited, it should be current limited (to IINJ+ and IINJ-) if there is any possibility of the pad
voltage exceeding the VIO limits (including transient behavior during supply ramp up, or at any time when the part is
unpowered).
Table 22-31. Fail-Safe GPIOs that Require an External Pull-up
GPIO
Pin
Pull-Up Resistor Value
Unit
PB0
70
1k ≤ R ≤ 10k
Ω
PB1
71
1k ≤ R ≤ 10k
Ω
PE3
12
1k ≤ R ≤ 10k
Ω
22.13.2.2 Non-Fail-Safe Pins
The ADC external voltage reference input pins, the Main Oscillator (MOSC) crystal connection pins
and GPIO pins PJ0 and PJ1 have ESD protection as shown in Figure 22-17 on page 1285. These
pins have a potential path between the I/O pad and an internal power rail if either one of the ESD
diodes is accidentally forward biased. The voltage and current of these pins should follow the
specifications in Table 22-32 on page 1285 to prevent potential damage to the device. In addition to
the specifications outlined in Table 22-32 on page 1285, it is recommended that the ADC external
reference specifications in Table 22-33 on page 1287 be adhered to in order to prevent any gain error.
Figure 22-17 on page 1285 shows a diagram of the ESD protection on non-fail-safe pins.
Figure 22-17. ESD Protection on Non-Fail-Safe Pins
VDD
I/O Pad
GND
abcd
Table 22-32. Non-Fail-Safe I/O Pad Voltage/Current Characteristics
Parameter
VIO
ILKG+
Parameter Name
Min
Nom
Max
Unit
-0.3
VDD
VDD+0.3
V
ef
-
-
10
µA
ef
-
-
10
µA
-
-
2
mA
-
-
-0.5
mA
IO pad voltage limits
Positive IO leakage for VIO Max
ILKG-
Negative IO leakage for VIO Min
IINJ+
Max positive injection
IINJ-
Max negative injection if not voltage protected
g
g
a. VIN must be within the range specified in Table 22-1 on page 1256. Leakage current outside of this maximum voltage is not
guaranteed and can result in permanent damage of the device.
b. VDD must be within the range specified in Table 22-5 on page 1258.
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c. To avoid potential damage to the part, either the voltage or current on the ESD-protected, non-Power, non-Hibernate/XOSC
input/outputs should be limited externally as shown in this table.
d. I/O pads should be protected if at any point the IO voltage has a possibility of going outside the limits shown in the table.
If the part is unpowered, the IO pad Voltage or Current must be limited (as shown in this table) to avoid powering the
part through the IO pad, causing potential irreversible damage.
e. This value applies to an I/O pin that is voltage-protected within the Min and Max VIO ratings. Leakage outside the specified
voltage range is unbounded and must be limited to IINJ- using an external resistor.
f. MIN and MAX leakage current for the case when the I/O is voltage-protected to VIO Min or VIO Max.
g. If an I/O pin is not voltage-limited, it should be current-limited (to IINJ+ and IINJ-) if there is any possibility of the pad voltage
exceeding the VIO limits (including transient behavior during supply ramp up, or at any time when the part is unpowered).
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22.14
Analog-to-Digital Converter (ADC)
ab
Table 22-33. ADC Electrical Characteristics
Parameter
Parameter Name
Min
Nom
Max
Unit
POWER SUPPLY REQUIREMENTS
VDDA
ADC supply voltage
2.97
3.3
3.63
V
GNDA
ADC ground voltage
-
0
-
V
-
1.0 // 0.01
-
μF
VDDA / GNDA VOLTAGE REFERENCE
CREF
Voltage reference decoupling capacitance
c
EXTERNAL VOLTAGE REFERENCE INPUT
VREFA+
Positive external voltage reference for ADC,
when VREF field in the ADCCTL register is not
d
0x0 -
2.4
VDDA
VDDA
V
VREFA-
Negative external voltage reference for ADC,
when VREF field in the ADCCTL register is not
d
0x0
GNDA
GNDA
0.3
V
IVREF
Current on VREF+ input, using external VREF+
= 3.3 V
-
330.5
440
µA
ILVREF
DC leakage current on VREF+ input when
external VREF disabled
-
-
2.0
µA
CREF
External reference decoupling capacitance
-
1.0 // 0.01
-
μF
0
-
VDDA
V
Differential, full-scale analog input voltage,
fh
internal reference
-VDDA
-
VVDDA
V
Single-ended, full-scale analog input voltage,
dg
external reference
VREFA-
-
VREFA+
V
- (VREFA+ VREFA-)
-
VREFA+ VREFA-
V
-
-
(VREFP +
VREFN) / 2
mV
d
e
ANALOG INPUT
Single-ended, full- scale analog input voltage,
fg
internal reference
VADCIN
Differential, full-scale analog input voltage,
di
external reference
VINCM
j
Input common mode voltage, differential mode
± 25
IL
k
ADC input leakage current
k
RADC
ADC equivalent input resistance
CADC
ADC equivalent input capacitance
RS
k
k
Analog source resistance
-
-
2.0
µA
-
-
2.5
kΩ
-
-
10
pF
-
-
500
Ω
-
16
-
MHz
SAMPLING DYNAMICS
l
FADC
ADC conversion clock frequency
FCONV
ADC conversion rate
1
TS
ADC sample time
TC
ADC conversion time
-
TLT
Latency from trigger to start of conversion
250
m
Msps
-
1
-
2
ns
µs
-
ADC clocks
no
SYSTEM PERFORMANCE when using external reference
N
INL
Resolution
12
Integral nonlinearity error, over full input range
-
June 12, 2014
±1.5
bits
±3.0
LSB
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Texas Instruments-Production Data
Electrical Characteristics
Table 22-33. ADC Electrical Characteristics (continued)
Parameter
DNL
Parameter Name
Min
Nom
Max
Unit
p
Differential nonlinearity error, over full input
range
-
±0.8
+2.0/-1.0
LSB
EO
Offset error
-
±1.0
±3.0
LSB
EG
Gain error
q
-
±2.0
±3.0
LSB
-
±2.5
±4.0
LSB
ET
r
Total unadjusted error, over full input range
SYSTEM PERFORMANCE when using internal reference
N
Resolution
12
bits
INL
Integral nonlinearity error, over full input range
-
±1.5
±3.0
DNL
Differential nonlinearity error, over full input
range
-
±0.8
+2.0/-1.0
LSB
LSB
p
EO
Offset error
-
±5.0
±15.0
LSB
EG
Gain error
q
-
±10.0
±30.0
LSB
-
±10.0
±30.0
LSB
ET
r
Total unadjusted error, over full input range
st
DYNAMIC CHARACTERISTICS
SNRD
Signal-to-noise-ratio, Differential input, VADCIN:
u
-20dB FS, 1KHz
70
72
-
dB
SDRD
Signal-to-distortion ratio, Differential input,
uvw
VADCIN: -3dB FS, 1KHz
72
75
-
dB
SNDRD
Signal-to-Noise+Distortion ratio, Differential
uxy
input, VADCIN: -3dB FS, 1KHz
68
70
-
dB
Signal-to-noise-ratio, Single-ended input,
VADCIN: -20dB FS, 1KHz
60
65
-
dB
SDRS
Signal-to-distortion ratio, Single-ended input,
vw
VADCIN: -3dB FS, 1KHz
70
72
-
dB
SNDRS
Signal-to-Noise+Distortion ratio, Single-ended
xyz
input, VADCIN: -3dB FS, 1KHz
60
63
-
dB
SNRS
z
TEMPERATURE SENSOR
VTSENS
Temperature sensor voltage, junction
temperature 25 °C
-
1.633
-
V
STSENS
Temperature sensor slope
-
-13.3
-
mV/°C
-
-
±5
°C
ETSENS
aa
Temperature sensor accuracy
a. VREF+= 3.3V, FADC=16 MHz unless otherwise noted.
b. Best design practices suggest that static or quiet digital I/O signals be configured adjacent to sensitive analog inputs to
reduce capacitive coupling and cross talk. Analog signals configured adjacent to ADC input channels should meet the
same source resistance and bandwidth limitations that apply to the ADC input signals.
c. Two capacitors in parallel.
d. Assumes external filtering network between VREFA+ and VREFA- as shown in Figure 22-18 on page 1289. External reference
noise level must be under 12bit (-74 dB) of Full Scale input, over input bandwidth, measured at VREFA+ - VREFA-.
e. Two capacitors in parallel.
f. Internal reference is connected directly between VDDA and GNDA (VREFi = VDDA - GNDA). In this mode, EO, EG, ET, and
dynamic specifications are adversely affected due to internal voltage drop and noise on VDDA and GNDA. Internal
reference voltage is selected when VREF field in the ADCCTL register is 0x0.
g. VADCIN = VINP - VINN
h. With signal common mode as VDDA/2.
i. With signal common mode as (VREF+ + VREF-)/2.
j. This parameter is defined as the average of the differential inputs.
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Tiva™ TM4C1237H6PZ Microcontroller
k. As shown in Figure 22-19 on page 1290, RADC is the total equivalent resistance in the input line all the way up to the sampling
node at the input of the ADC.
l. See “System Clock Specification with ADC Operation” on page 1278 for full ADC clock frequency specification.
m. ADC conversion time (Tc) includes the ADC sample time (Ts).
n. Low noise environment is assumed in order to obtain values close to spec. Board must have good ground isolation between
analog and digital grounds, a clean reference voltage is assumed, and input signal must be bandlimited to Nyquist
bandwidth. No anti-aliasing filter is provided internally.
o. ADC static measurements taken by averaging over several samples. At least 20-sample averaging is assumed to obtain
expected typical or maximum spec values.
p. 12-bit DNL
q. Gain error is measured at max code after compensating for offset. Gain error is equivalent to "Full Scale Error." It can be
given in % of slope error, or in LSB, as done here.
r. Total Unadjusted Error is the maximum error at any one code versus the ideal ADC curve. It includes all other errors (offset
error, gain error and INL) at any given ADC code.
s. A low-noise environment is assumed in order to obtain values close to spec. The board must have good ground isolation
between analog and digital grounds and a clean reference voltage. The input signal must be band-limited to Nyquist
bandwidth. No anti-aliasing filter is provided internally.
t. ADC dynamic characteristics are measured using low-noise board design, with low-noise reference voltage ( < -74dB noise
level in signal BW) and low-noise analog supply voltage. Board noise and ground bouncing couple into the ADC and
affect dynamic characteristics. Clean external reference must be used to achieve shown specs.
u. Differential signal with correct common mode, applied between two ADC inputs.
v. SDR = -THD in dB.
w. For higher frequency inputs, degradation in SDR should be expected.
x. SNDR = S/(N+D) = SINAD (in dB)
y. Effective number of bits (ENOB) can be calculated from SNDR: ENOB = (SNDR - 1.76) / 6.02.
z. Single-ended inputs are more sensitive to board and trace noise than differential inputs; SNR and SNDR measurements
on single-ended inputs are highly dependent on how clean the test set-up is. If the input signal is not well-isolated on
the board, higher noise than specified could potentially be seen at the ADC output.
aa. Note that this parameter does not include ADC error.
Figure 22-18. ADC External Reference Filtering
Tiva™ Microcontroller
VREFP
VREFA+
IVREF
VREFA+
CREF
ADC
VREFN
VREFA
VREF
VREFA
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Electrical Characteristics
Figure 22-19. ADC Input Equivalency Diagram
Tiva™ Microcontroller
Zs
Rs
VS
ESD clamps
to GND only
Input PAD
Equivalent
Circuit
ZADC
RADC
Pin
Cs
VADCIN
5V ESD
Clamp
12‐bit
SAR ADC
Converter
12‐bit
Word
IL
Pin
Input PAD
Equivalent
Circuit
Pin
Input PAD
Equivalent
Circuit
RADC
RADC
CADC
1290
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
22.15
Synchronous Serial Interface (SSI)
Table 22-34. SSI Characteristics
Parameter
No.
Parameter
Parameter Name
Min
Nom
Max
Unit
S1
TCLK_PER
40
-
-
ns
SSIClk cycle time, as slave
150
-
-
ns
S2
TCLK_HIGH
SSIClk high time, as master
20
-
-
ns
SSIClk high time, as slave
75
-
-
ns
S3
TCLK_LOW
SSIClk low time, as master
20
-
-
ns
S4
TCLKR
SSIClk rise time
75
-
-
ns
1.25
-
-
S5
TCLKF
c
ns
1.25
-
-
ns
S6
TTXDMOV
Master Mode: Master Tx Data Output (to slave)
Valid Time from edge of SSIClk
-
-
15.7
ns
S7
TTXDMOH
Master Mode: Master Tx Data Output (to slave)
Hold Time from next SSIClk
0.31
-
-
ns
S8
TRXDMS
Master Mode: Master Rx Data In (from slave)
setup time
17.15
-
-
ns
S9
TRXDMH
Master Mode: Master Rx Data In (from slave) hold
time
0
-
-
ns
S10
TTXDSOV
Slave Mode: Master Tx Data Output (to Master)
Valid Time from edge of SSIClk
-
-
77.74
ns
S11
TTXDSOH
Slave Mode: Slave Tx Data Output (to Master)
Hold Time from next SSIClk
55.5
-
-
ns
S12
TRXDSSU
Slave Mode: Rx Data In (from master) setup time
-
-
ns
-
-
ns
a
S13
TRXDSH
SSIClk cycle time, as master
b
SSIClk low time, as slave
c
SSIClk fall time
Slave Mode: Rx Data In (from master) hold time
e
0
f
51.55
d
a. In master mode, the system clock must be at least twice as fast as the SSIClk.
b. In slave mode, the system clock must be at least 12 times faster than the SSIClk.
c. Note that the delays shown are using 8-mA drive strength.
d. This MAX value is for the minimum TSYSCLK (12.5 ns). To find the MAX TTXDSOV value for a larger TSYSCLK, use the
equation: 4*TSYSCLK+27.74.
e. This MIN value is for the minimum slave mode TSYSCLK (12.5 ns). To find the MIN TTXDSOH value for a larger TSYSCLK,
use the equation: 4*TSYSCLK+5.50.
f. This MIN value is for the minimum slave mode TSYSCLK (12.5 ns). To find the MIN TRXDSH value for a larger TSYSCLK, use
the equation: 4*TSYSCLK+1.55.
June 12, 2014
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Electrical Characteristics
Figure 22-20. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement
S1
S2
S4
S5
SSIClk
S3
SSIFss
SSITx
SSIRx
MSB
LSB
4 to 16 bits
Figure 22-21. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer
S2
S1
S5
S4
SSIClk
S3
SSIFss
SSITx
MSB
LSB
8-bit control
SSIRx
0
MSB
LSB
4 to 16 bits output data
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June 12, 2014
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Tiva™ TM4C1237H6PZ Microcontroller
Figure 22-22. Master Mode SSI Timing for SPI Frame Format (FRF=00), with SPH=1
S1
S5
S2
S4
SSIClk
(SPO=1)
S3
SSIClk
(SPO=0)
S7
S6
SSITx
MSB
(to slave)
S8
SSIRx
LSB
S9
MSB
( from slave)
LSB
SSIFss
Figure 22-23. Slave Mode SSI Timing for SPI Frame Format (FRF=00), with SPH=1
S1
S5
S4
S2
SSIClk
(SPO=1)
S3
S3
SSIClk
(SPO=0)
S10
SSITx
S11
MSB
(to master)
LSB
S12
S13
SSIRx
( from master)
MSB
LSB
SSIFss
June 12, 2014
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Electrical Characteristics
22.16
Inter-Integrated Circuit (I2C) Interface
Table 22-35. I2C Characteristics
Parameter
No.
Parameter Parameter Name
Min
Nom
Max
Unit
a
TSCH
Start condition hold time
36
-
-
system clocks
a
TLP
Clock Low period
36
-
-
system clocks
b
I3
TSRT
I2CSCL/I2CSDA rise time (VIL =0.5 V
to V IH =2.4 V)
-
-
(see note
b)
ns
I4
TDH
Data hold time (slave)
-
2
-
system clocks
Data hold time (master)
-
7
-
system clocks
c
TSFT
I2CSCL/I2CSDA fall time (VIH =2.4 V
to V IL =0.5 V)
-
9
10
ns
a
THT
Clock High time
24
-
-
system clocks
I1
I2
I5
I6
I7
Data setup time
18
-
-
system clocks
a
TSCSR
Start condition setup time (for
repeated start condition only)
36
-
-
system clocks
I9
a
TSCS
Stop condition setup time
24
-
-
system clocks
Data Valid (slave)
-
2
-
system clocks
I10
TDV
Data Valid (master)
-
(6 * (1 +
TPR)) + 1
-
system clocks
I8
TDS
a. Values depend on the value programmed into the TPR bit in the I2C Master Timer Period (I2CMTPR) register; a TPR
programmed for the maximum I2CSCL frequency (TPR=0x2) results in a minimum output timing as shown in the table
above. The I 2C interface is designed to scale the actual data transition time to move it to the middle of the I2CSCL Low
period. The actual position is affected by the value programmed into the TPR; however, the numbers given in the above
values are minimum values.
b. Because I2CSCL and I2CSDA operate as open-drain-type signals, which the controller can only actively drive Low, the
time I2CSCL or I2CSDA takes to reach a high level depends on external signal capacitance and pull-up resistor values.
c. Specified at a nominal 50 pF load.
Figure 22-24. I2C Timing
I2
I10
I6
I5
I2CSCL
I1
I4
I7
I8
I3
I9
I2CSDA
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Tiva™ TM4C1237H6PZ Microcontroller
22.17
Universal Serial Bus (USB) Controller
The TM4C1237H6PZ USB controller electrical specifications are compliant with the Universal Serial
Bus Specification Rev. 2.0 (full-speed and low-speed support) and the On-The-Go Supplement to
the USB 2.0 Specification Rev. 1.0. Some components of the USB system are integrated within the
TM4C1237H6PZ microcontroller and specific to the TM4C1237H6PZ microcontroller design.
June 12, 2014
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Texas Instruments-Production Data
Electrical Characteristics
22.18
Analog Comparator
ab
Table 22-36. Analog Comparator Characteristics
Parameter
Parameter Name
c
VINP,VINN
VCM
VOS
IINP,IINN
CMRR
Min
Nom
Max
Unit
Input voltage range
GNDA
-
VDDA
V
Input common mode voltage range
GNDA
-
VDDA
V
d
Input offset voltage
-
±10
±50
mV
Input leakage current over full voltage range
-
-
2.0
µA
Common mode rejection ratio
-
50
-
dB
e
TRT
Response time
-
-
1.0
µs
TMC
Comparator mode change to Output Valid
-
-
10
µs
a. Best design practices suggest that static or quiet digital I/O signals be configured adjacent to sensitive analog inputs to
reduce capacitive coupling and cross talk.
b. To achieve best analog results, the source resistance driving the analog inputs, VINP and VINN, should be kept low.
c. The external voltage inputs to the Analog Comparator are designed to be highly sensitive and can be affected by external
noise on the board. For this reason, VINP and VINN must be set to different voltage levels during idle states to ensure the
analog comparator triggers are not enabled. If an internal voltage reference is used, it should be set to a mid-supply
level. When operating in Sleep/Deep-Sleep modes, the Analog Comparator module external voltage inputs set to different
levels (greater than the input offset voltage) to achieve minimum current draw.
d. Measured at VREF=100 mV.
e. Measured at external VREF=100 mV, input signal switching from 75 mV to 125 mV.
Table 22-37. Analog Comparator Voltage Reference Characteristics
Parameter
Parameter Name
Min
Nom
Max
Unit
RHR
Resolution in high range
-
VDDA/29.4
-
V
RLR
Resolution in low range
-
VDDA/22.12
-
V
AHR
Absolute accuracy high range
-
-
±RHR/2
V
ALR
Absolute accuracy low range
-
-
±RLR/2
V
Table 22-38. Analog Comparator Voltage Reference Characteristics, VDDA = 3.3V, EN= 1, and
RNG = 0
VREF Value
VIREF Min
Ideal VIREF
VIREF Max
Unit
0x0
0.731
0.786
0.841
V
0x1
0.843
0.898
0.953
V
0x2
0.955
1.010
1.065
V
0x3
1.067
1.122
1.178
V
0x4
1.180
1.235
1.290
V
0x5
1.292
1.347
1.402
V
0x6
1.404
1.459
1.514
V
0x7
1.516
1.571
1.627
V
0x8
1.629
1.684
1.739
V
0x9
1.741
1.796
1.851
V
0xA
1.853
1.908
1.963
V
0xB
1.965
2.020
2.076
V
0xC
2.078
2.133
2.188
V
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June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
Table 22-38. Analog Comparator Voltage Reference Characteristics, VDDA = 3.3V, EN= 1, and
RNG = 0 (continued)
VREF Value
VIREF Min
Ideal VIREF
VIREF Max
Unit
0xD
2.190
2.245
2.300
V
0xE
2.302
2.357
2.412
V
0xF
2.414
2.469
2.525
V
Table 22-39. Analog Comparator Voltage Reference Characteristics, VDDA = 3.3V, EN= 1, and
RNG = 1
VREF Value
VIREF Min
Ideal VIREF
VIREF Max
Unit
0x0
0.000
0.000
0.074
V
0x1
0.076
0.149
0.223
V
0x2
0.225
0.298
0.372
V
0x3
0.374
0.448
0.521
V
0x4
0.523
0.597
0.670
V
0x5
0.672
0.746
0.820
V
0x6
0.822
0.895
0.969
V
0x7
0.971
1.044
1.118
V
0x8
1.120
1.193
1.267
V
0x9
1.269
1.343
1.416
V
0xA
1.418
1.492
1.565
V
0xB
1.567
1.641
1.715
V
0xC
1.717
1.790
1.864
V
0xD
1.866
1.939
2.013
V
0xE
2.015
2.089
2.162
V
0xF
2.164
2.238
2.311
V
June 12, 2014
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Electrical Characteristics
22.19
Current Consumption
Table 22-40. Current Consumption
System Clock
Parameter
Parameter Name
Conditions
VDD = 3.3 V
VDDA = 3.3 V
VDD = 3.3 V
VDDA = 3.3 V
VDD = 3.3 V
VDDA = 3.3 V
VDD = 3.3 V
VDDA = 3.3 V
a
IDDA
VDD = 3.3 V
Deep-Sleep mode
Peripherals = All ON
Run, Sleep and
Deep-sleep mode
VDD = 3.3 V
Peripherals = All OFF
mA
32.0
32.7
40.6
mA
19.6
19.7
20.3
27.6
mA
PIOSC
17.5
17.6
18.0
25.3
mA
45.0
45.1
40 MHz
MOSC with
PLL
31.9
16 MHz
MOSC with
PLL
16 MHz
-40°C 25°C
85°C
1 MHz
PIOSC
10.0
10.1
10.5
17.5
mA
80 MHz
MOSC with
PLL
24.5
24.7
25.2
31.3
mA
40 MHz
MOSC with
PLL
19.6
19.7
20.4
25.9
mA
16 MHz
MOSC with
PLL
12.1
12.2
12.7
18.7
mA
16 MHz
PIOSC
10.1
10.1
10.5
16.4
mA
1 MHz
PIOSC
5.45
5.50
5.98
11.6
mA
80 MHz
MOSC with
PLL
34.7
34.9
35.5
44.2
mA
40 MHz
MOSC with
PLL
22.2
22.4
22.9
30.2
mA
16 MHz
MOSC with
PLL
14.7
14.8
15.3
21.8
mA
16 MHz
PIOSC
12.8
12.9
13.4
19.7
mA
1 MHz
PIOSC
8.07
8.16
8.61
14.6
mA
80 MHz
MOSC with
PLL
15.2
15.3
15.8
21.7
mA
40 MHz
MOSC with
PLL
10.3
10.5
10.9
16.2
mA
16 MHz
MOSC with
PLL
7.32
7.45
7.92
13.0
mA
16 MHz
PIOSC
5.87
5.96
6.35
13.7
mA
1 MHz
PIOSC
3.54
3.63
4.07
8.84
mA
-
MOSC with
PLL,
PIOSC
2.71
2.71
2.71
3.97
mA
30 kHz
LFIOSC
2.54
2.54
2.54
3.68
mA
-
MOSC with
PLL,
PIOSC,
LFIOSC
0.28
0.28
0.29
0.56
mA
VDDA = 3.3 V
VDDA = 3.3 V
54.9
MOSC with
PLL
Peripherals = All OFF
Run, Sleep and
Deep-sleep mode
45.7
80 MHz
Peripherals = All ON
Run mode (SRAM loop)
Unit
Clock
Source
Peripherals = All OFF
IDD_RUN
Max
85°C
Frequency
Peripherals = All ON
Run mode (Flash loop)
Nom
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Tiva™ TM4C1237H6PZ Microcontroller
Table 22-40. Current Consumption (continued)
System Clock
Parameter
Parameter Name
Conditions
VDD = 3.3 V
Sleep mode (FLASHPM
= 0x0)
VDD = 3.3 V
VDD = 3.3 V
VDD = 3.3 V
20.2
27.1
mA
13.6
13.8
14.2
20.6
mA
b
11.7
11.8
12.2
18.5
mA
b
40 MHz
MOSC with
PLL
19.5
16 MHz
MOSC with
PLL
16 MHz
PIOSC
-40°C 25°C
85°C
1 MHz
PIOSC
7.01
7.06
7.93
12.0
mA
80 MHz
MOSC with
PLL
9.60
9.73
10.2
15.4
mA
40 MHz
MOSC with
PLL
7.49
7.60
8.06
13.2
mA
16 MHz
MOSC with
PLL
6.22
6.33
6.78
11.7
mA
16 MHz
PIOSC
b
4.28
4.35
4.77
9.52
mA
b
1 MHz
PIOSC
3.52
3.59
4.01
8.70
mA
80 MHz
MOSC with
PLL
28.4
28.6
29.2
37.2
mA
40 MHz
MOSC with
PLL
18.6
18.8
19.3
26.2
mA
16 MHz
MOSC with
PLL
12.7
12.9
13.3
19.7
mA
16 MHz
PIOSC
b
10.8
10.9
11.3
17.5
mA
b
1 MHz
PIOSC
7.09
7.20
7.67
13.6
mA
80 MHz
MOSC with
PLL
8.66
8.82
9.31
14.5
mA
40 MHz
MOSC with
PLL
6.55
6.69
7.17
12.1
mA
16 MHz
MOSC with
PLL
5.27
5.41
5.89
10.7
mA
16 MHz
PIOSC
b
3.34
3.44
3.88
8.65
mA
1 MHz
PIOSC
b
2.58
2.67
3.13
7.85
mA
VDDA = 3.3 V
Peripherals = All OFF
19.7
29.5
LDO = 1.2 V
Sleep mode (FLASHPM
= 0x2)
mA
29.3
VDDA = 3.3 V
Peripherals = All ON
38.1
MOSC with
PLL
LDO = 1.2 V
IDD_SLEEP
30.0
80 MHz
VDDA = 3.3 V
Peripherals = All OFF
Unit
Clock
Source
LDO = 1.2 V
Max
85°C
Frequency
VDDA = 3.3 V
Peripherals = All ON
Nom
LDO = 1.2 V
June 12, 2014
1299
Texas Instruments-Production Data
Electrical Characteristics
Table 22-40. Current Consumption (continued)
System Clock
Parameter
Parameter Name
Nom
Conditions
Frequency
VDD = 3.3 V
16 MHz
PIOSC
9.29
9.29
VDDA = 3.3 V
30 kHz
LFIOSC
5.10
5.10
VDD = 3.3 V
16 MHz
PIOSC
3.51
VDDA = 3.3 V
30 kHz
LFIOSC
Clock
Source
Max
85°C
Unit
9.66
15.9
mA
5.48
11.2
mA
3.51
3.91
8.67
mA
2.00
2.00
2.39
7.24
mA
-40°C 25°C
85°C
Peripherals = All ON
Deep-sleep mode
(FLASHPM = 0x0)
LDO = 1.2 V
Peripherals = All OFF
LDO = 1.2 V
IDD_DEEPSLEEP
VDD = 3.3 V
16 MHz
PIOSC
8.34
8.36
8.77
14.9
mA
VDDA = 3.3 V
30 kHz
LFIOSC
4.14
4.18
4.59
10.4
mA
VDD = 3.3 V
16 MHz
PIOSC
2.56
2.60
3.02
7.79
mA
VDDA = 3.3 V
30 kHz
LFIOSC
1.04
1.07
1.49
6.48
mA
-
-
1.23
1.38
1.54
5.20
µA
-
-
1.27
1.40
1.69
5.24
µA
-
-
3.17
4.49
10.6
28.1
µA
-
-
3.16
4.33
10.4
27.7
µA
Peripherals = All ON
Deep-sleep mode
(FLASHPM = 0x2)
LDO = 1.2 V
Peripherals = All OFF
LDO = 1.2 V
IHIB_NORTC
Hibernate mode
(external wake, RTC
disabled)
VBAT = 3.0 V
VDD = 0 V
VDDA = 0 V
System Clock = OFF
Hibernate Module = 32.768
kHz
IHIB_RTC
Hibernate mode (RTC
enabled)
VBAT = 3.0 V
VDD = 0 V
VDDA = 0 V
System Clock = OFF
Hibernate Module = 32.768
kHz
Hibernate mode
(VDD3ON mode, RTC
on)
VBAT = 3.0 V
VDD = 3.3 V
VDDA = 3.3 V
System Clock = OFF
IHIB_VDD3ON
Hibernate Module = 32.768
kHz
Hibernate mode
(VDD3ON mode, RTC
off)
VBAT = 3.0 V
VDD = 3.3 V
VDDA = 3.3 V
System Clock = OFF
Hibernate Module = 32.768
kHz
a. The value for IDDA is included in the above values for IDD_RUN, IDD_SLEEP, and IDD_DEEPSLEEP.
b. Note that if the MOSC is the source of the Run-mode system clock and is powered down in Sleep mode, wake time is increased by
TMOSC_SETTLE.
1300
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
A
Package Information
A.1
Orderable Devices
The figure below defines the full set of orderable part numbers for the TM4C123x Series. See the
Package Option Addendum for the complete list of valid orderable part numbers for the
TM4C1237H6PZ microcontroller.
Figure A-1. Key to Part Numbers
T M4 C 1 SSS M Y PPP T XX Z R
Shipping Medium
R = Tape-and-reel
Omitted = Default shipping (tray or tube)
Prefix
T = Qualified Device
X = Experimental Device
Revision
Core
M4 = ARM® Cortex™-M4
Special Codes
Optional
Tiva Series
C = Connected MCUs
Temperature
I = –40°C to +85°C
T = –40°C to +105°C
Package
PM = 64-pin LQFP
PZ = 100-pin LQFP
PGE = 144-pin LQFP
ZRB = 157-ball BGA
Data Memory
3 = 12 KB
5 = 24 KB
6 = 32 KB
Family
Part Number
SSS = Series identifier
Program Memory
C = 32 KB
D = 64 KB
E = 128 KB
H = 256 KB
A.2
Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers
of all microcontroller (MCU) devices. Each Tiva™ C Series family member has one of two prefixes:
XM4C or TM4C. These prefixes represent evolutionary stages of product development from
engineering prototypes (XM4C) through fully qualified production devices (TM4C).
Device development evolutionary flow:
■ XM4C — Experimental device that is not necessarily representative of the final device's electrical
specifications and may not use production assembly flow.
■ TM4C — Production version of the silicon die that is fully qualified.
XM4C devices are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
TM4C devices have been characterized fully, and the quality and reliability of the device have been
demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (XM4C) have a greater failure rate than the standard
production devices. Texas Instruments recommends that these devices not be used in any production
system because their expected end-use failure rate still is undefined. Only qualified production
devices are to be used.
June 12, 2014
1301
Texas Instruments-Production Data
Package Information
A.3
Device Markings
The figure below shows an example of the Tiva™ microcontroller package symbolization.
$$
TM4C123G
H6PGEI7
YMLLLLS
G1
This identifying number contains the following information:
■ Lines 1 and 5: Internal tracking numbers
■ Lines 2 and 3: Part number
For example, TM4C123G on the second line followed by H6PGEI7 on the third line indicates
orderable part number TM4C123GH6PGEI7. The silicon revision number is the last number in
the part number, in this example, 7. The DID0 register also identifies the version of the
microcontroller, as shown in the table below. Combined, the MAJOR and MINOR bit fields indicate
the die revision and part revision numbers.
MAJOR Bitfield Value
MINOR Bitfield Value
Die Revision
Part Revision
0x0
0x0
A0
1
0x0
0x1
A1
2
0x0
0x2
A2
3
0x0
0x3
A3
4
0x1
0x0
B0
5
0x1
0x1
B1
6
0x1
0x2
B2
7
■ Line 4: Date code
The first two characters on the fourth line indicate the date code, followed by internal tracking
numbers. The two-digit date code YM indicates the last digit of the year, then the month. For
example, a 34 for the first two digits of the fourth line indicates a date code of April 2013.
1302
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1237H6PZ Microcontroller
A.4
Packaging Diagram
Figure A-2. TM4C1237H6PZ 100-Pin LQFP Package Diagram
MECHANICAL DATA
MTQF013A – OCTOBER 1994 – REVISED DECEMBER 1996
PZ (S-PQFP-G100)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
75
0,08 M
51
76
50
100
26
1
0,13 NOM
25
12,00 TYP
Gage Plane
14,20
SQ
13,80
16,20
SQ
15,80
0,05 MIN
1,45
1,35
0,25
0°– 7°
0,75
0,45
Seating Plane
0,08
1,60 MAX
4040149 /B 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
June 12, 2014
1303
Texas Instruments-Production Data
PACKAGE OPTION ADDENDUM
www.ti.com
2-Mar-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TM4C1237H6PZI
ACTIVE
LQFP
PZ
100
90
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
TM4C1237
H6PZI
TM4C1237H6PZI7
ACTIVE
LQFP
PZ
100
90
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
TM4C1237
H6PZI7
TM4C1237H6PZI7R
ACTIVE
LQFP
PZ
100
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
TM4C1237
H6PZI7
TM4C1237H6PZIR
ACTIVE
LQFP
PZ
100
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
TM4C1237
H6PZI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of