TE X AS I NS TRUM E NTS - P RO DUCTION D ATA
Tiva™ TM4C123BH6PGE Microcontroller
D ATA SH E E T
D S -T M 4C 123BH6 P G E - 1 5 8 4 2 . 2 7 4 1
S P M S 367E
C o p yri g h t © 2 0 07-2014
Te xa s In stru me n ts In co rporated
Copyright
Copyright © 2007-2014 Texas Instruments Incorporated. Tiva and TivaWare are trademarks of Texas Instruments Incorporated. ARM and Thumb are
registered trademarks and Cortex is a trademark of ARM Limited. All other trademarks are the property of others.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard
warranty. Production processing does not necessarily include testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor
products and disclaimers thereto appears at the end of this data sheet.
Texas Instruments Incorporated
108 Wild Basin, Suite 350
Austin, TX 78746
http://www.ti.com/tm4c
http://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm
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Table of Contents
Revision History ............................................................................................................................. 34
About This Document .................................................................................................................... 38
Audience ..............................................................................................................................................
About This Manual ................................................................................................................................
Related Documents ...............................................................................................................................
Documentation Conventions ..................................................................................................................
38
38
38
39
1
Architectural Overview .......................................................................................... 41
1.1
1.2
1.3
1.3.1
1.3.2
1.3.3
1.3.4
1.3.5
1.3.6
1.3.7
1.3.8
1.4
1.5
1.6
Tiva™ C Series Overview .............................................................................................. 41
TM4C123BH6PGE Microcontroller Overview .................................................................. 42
TM4C123BH6PGE Microcontroller Features ................................................................... 45
ARM Cortex-M4F Processor Core .................................................................................. 45
On-Chip Memory ........................................................................................................... 47
Serial Communications Peripherals ................................................................................ 49
System Integration ........................................................................................................ 52
Advanced Motion Control ............................................................................................... 58
Analog .......................................................................................................................... 61
JTAG and ARM Serial Wire Debug ................................................................................ 62
Packaging and Temperature .......................................................................................... 63
TM4C123BH6PGE Microcontroller Hardware Details ....................................................... 63
Kits .............................................................................................................................. 63
Support Information ....................................................................................................... 63
2
The Cortex-M4F Processor ................................................................................... 64
2.1
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.3
2.3.1
2.3.2
2.3.3
2.3.4
2.3.5
2.3.6
2.4
2.4.1
2.4.2
2.4.3
2.4.4
2.4.5
2.4.6
2.4.7
2.5
2.5.1
Block Diagram .............................................................................................................. 65
Overview ...................................................................................................................... 66
System-Level Interface .................................................................................................. 66
Integrated Configurable Debug ...................................................................................... 66
Trace Port Interface Unit (TPIU) ..................................................................................... 67
Cortex-M4F System Component Details ......................................................................... 67
Programming Model ...................................................................................................... 68
Processor Mode and Privilege Levels for Software Execution ........................................... 68
Stacks .......................................................................................................................... 69
Register Map ................................................................................................................ 69
Register Descriptions .................................................................................................... 71
Exceptions and Interrupts .............................................................................................. 87
Data Types ................................................................................................................... 87
Memory Model .............................................................................................................. 87
Memory Regions, Types and Attributes ........................................................................... 90
Memory System Ordering of Memory Accesses .............................................................. 90
Behavior of Memory Accesses ....................................................................................... 90
Software Ordering of Memory Accesses ......................................................................... 91
Bit-Banding ................................................................................................................... 92
Data Storage ................................................................................................................ 95
Synchronization Primitives ............................................................................................. 95
Exception Model ........................................................................................................... 96
Exception States ........................................................................................................... 97
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2.5.2
2.5.3
2.5.4
2.5.5
2.5.6
2.5.7
2.6
2.6.1
2.6.2
2.6.3
2.6.4
2.7
2.7.1
2.7.2
2.8
Exception Types ............................................................................................................ 97
Exception Handlers ..................................................................................................... 102
Vector Table ................................................................................................................ 102
Exception Priorities ...................................................................................................... 103
Interrupt Priority Grouping ............................................................................................ 104
Exception Entry and Return ......................................................................................... 104
Fault Handling ............................................................................................................. 107
Fault Types ................................................................................................................. 108
Fault Escalation and Hard Faults .................................................................................. 108
Fault Status Registers and Fault Address Registers ...................................................... 109
Lockup ....................................................................................................................... 109
Power Management .................................................................................................... 110
Entering Sleep Modes ................................................................................................. 110
Wake Up from Sleep Mode .......................................................................................... 110
Instruction Set Summary .............................................................................................. 111
3
Cortex-M4 Peripherals ......................................................................................... 118
3.1
3.1.1
3.1.2
3.1.3
3.1.4
3.1.5
3.2
3.3
3.4
3.5
3.6
3.7
Functional Description ................................................................................................. 118
System Timer (SysTick) ............................................................................................... 119
Nested Vectored Interrupt Controller (NVIC) .................................................................. 120
System Control Block (SCB) ........................................................................................ 121
Memory Protection Unit (MPU) ..................................................................................... 121
Floating-Point Unit (FPU) ............................................................................................. 126
Register Map .............................................................................................................. 130
System Timer (SysTick) Register Descriptions .............................................................. 133
NVIC Register Descriptions .......................................................................................... 137
System Control Block (SCB) Register Descriptions ........................................................ 152
Memory Protection Unit (MPU) Register Descriptions .................................................... 181
Floating-Point Unit (FPU) Register Descriptions ............................................................ 190
4
JTAG Interface ...................................................................................................... 196
4.1
4.2
4.3
4.3.1
4.3.2
4.3.3
4.3.4
4.4
4.5
4.5.1
4.5.2
Block Diagram ............................................................................................................
Signal Description .......................................................................................................
Functional Description .................................................................................................
JTAG Interface Pins .....................................................................................................
JTAG TAP Controller ...................................................................................................
Shift Registers ............................................................................................................
Operational Considerations ..........................................................................................
Initialization and Configuration .....................................................................................
Register Descriptions ..................................................................................................
Instruction Register (IR) ...............................................................................................
Data Registers ............................................................................................................
197
197
198
198
200
200
201
203
204
204
206
5
System Control ..................................................................................................... 208
5.1
5.2
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
Signal Description .......................................................................................................
Functional Description .................................................................................................
Device Identification ....................................................................................................
Reset Control ..............................................................................................................
Non-Maskable Interrupt ...............................................................................................
Power Control .............................................................................................................
Clock Control ..............................................................................................................
4
208
208
208
209
214
214
215
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5.2.6
5.3
5.4
5.5
5.6
System Control ...........................................................................................................
Initialization and Configuration .....................................................................................
Register Map ..............................................................................................................
System Control Register Descriptions ...........................................................................
System Control Legacy Register Descriptions ...............................................................
222
226
227
232
419
6
System Exception Module ................................................................................... 483
6.1
6.2
6.3
Functional Description ................................................................................................. 483
Register Map .............................................................................................................. 483
Register Descriptions .................................................................................................. 483
7
Hibernation Module .............................................................................................. 491
7.1
7.2
7.3
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.3.6
7.3.7
7.3.8
7.3.9
7.3.10
7.3.11
7.3.12
7.4
7.4.1
7.4.2
7.4.3
7.4.4
7.4.5
7.5
7.6
Block Diagram ............................................................................................................
Signal Description .......................................................................................................
Functional Description .................................................................................................
Register Access Timing ...............................................................................................
Hibernation Clock Source ............................................................................................
System Implementation ...............................................................................................
Battery Management ...................................................................................................
Real-Time Clock ..........................................................................................................
Battery-Backed Memory ..............................................................................................
Power Control Using HIB .............................................................................................
Power Control Using VDD3ON Mode ...........................................................................
Initiating Hibernate ......................................................................................................
Waking from Hibernate ................................................................................................
Arbitrary Power Removal .............................................................................................
Interrupts and Status ...................................................................................................
Initialization and Configuration .....................................................................................
Initialization .................................................................................................................
RTC Match Functionality (No Hibernation) ....................................................................
RTC Match/Wake-Up from Hibernation .........................................................................
External Wake-Up from Hibernation ..............................................................................
RTC or External Wake-Up from Hibernation ..................................................................
Register Map ..............................................................................................................
Register Descriptions ..................................................................................................
492
492
493
493
494
495
496
497
499
499
500
500
500
500
501
501
501
502
503
503
503
503
504
8
Internal Memory ................................................................................................... 522
8.1
8.2
8.2.1
8.2.2
8.2.3
8.2.4
8.3
8.4
8.5
8.6
Block Diagram ............................................................................................................ 522
Functional Description ................................................................................................. 523
SRAM ........................................................................................................................ 523
ROM .......................................................................................................................... 524
Flash Memory ............................................................................................................. 526
EEPROM .................................................................................................................... 532
Register Map .............................................................................................................. 538
Flash Memory Register Descriptions (Flash Control Offset) ............................................ 539
EEPROM Register Descriptions (EEPROM Offset) ........................................................ 557
Memory Register Descriptions (System Control Offset) .................................................. 574
9
Micro Direct Memory Access (μDMA) ................................................................ 583
9.1
9.2
Block Diagram ............................................................................................................ 584
Functional Description ................................................................................................. 584
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9.2.1
9.2.2
9.2.3
9.2.4
9.2.5
9.2.6
9.2.7
9.2.8
9.2.9
9.2.10
9.3
9.3.1
9.3.2
9.3.3
9.3.4
9.3.5
9.4
9.5
9.6
Channel Assignments .................................................................................................. 585
Priority ........................................................................................................................ 586
Arbitration Size ............................................................................................................ 586
Request Types ............................................................................................................ 586
Channel Configuration ................................................................................................. 587
Transfer Modes ........................................................................................................... 589
Transfer Size and Increment ........................................................................................ 597
Peripheral Interface ..................................................................................................... 597
Software Request ........................................................................................................ 597
Interrupts and Errors .................................................................................................... 598
Initialization and Configuration ..................................................................................... 598
Module Initialization ..................................................................................................... 598
Configuring a Memory-to-Memory Transfer ................................................................... 599
Configuring a Peripheral for Simple Transmit ................................................................ 600
Configuring a Peripheral for Ping-Pong Receive ............................................................ 602
Configuring Channel Assignments ................................................................................ 604
Register Map .............................................................................................................. 604
μDMA Channel Control Structure ................................................................................. 606
μDMA Register Descriptions ........................................................................................ 613
10
General-Purpose Input/Outputs (GPIOs) ........................................................... 647
10.1
10.2
10.2.1
10.2.2
10.2.3
10.2.4
10.2.5
10.2.6
10.3
10.4
10.5
Signal Description ....................................................................................................... 647
Functional Description ................................................................................................. 651
Data Control ............................................................................................................... 653
Interrupt Control .......................................................................................................... 654
Mode Control .............................................................................................................. 656
Commit Control ........................................................................................................... 656
Pad Control ................................................................................................................. 656
Identification ............................................................................................................... 656
Initialization and Configuration ..................................................................................... 656
Register Map .............................................................................................................. 658
Register Descriptions .................................................................................................. 661
11
General-Purpose Timers ...................................................................................... 712
11.1
11.2
11.3
11.3.1
11.3.2
11.3.3
11.3.4
11.3.5
11.3.6
11.3.7
11.4
11.4.1
11.4.2
11.4.3
11.4.4
11.4.5
Block Diagram ............................................................................................................ 713
Signal Description ....................................................................................................... 714
Functional Description ................................................................................................. 716
GPTM Reset Conditions .............................................................................................. 717
Timer Modes ............................................................................................................... 718
Wait-for-Trigger Mode .................................................................................................. 727
Synchronizing GP Timer Blocks ................................................................................... 728
DMA Operation ........................................................................................................... 729
Accessing Concatenated 16/32-Bit GPTM Register Values ............................................ 729
Accessing Concatenated 32/64-Bit Wide GPTM Register Values .................................... 729
Initialization and Configuration ..................................................................................... 731
One-Shot/Periodic Timer Mode .................................................................................... 731
Real-Time Clock (RTC) Mode ...................................................................................... 732
Input Edge-Count Mode ............................................................................................... 732
Input Edge Time Mode ................................................................................................. 733
PWM Mode ................................................................................................................. 733
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11.5
11.6
Register Map .............................................................................................................. 734
Register Descriptions .................................................................................................. 735
12
Watchdog Timers ................................................................................................. 783
12.1
12.2
12.2.1
12.3
12.4
12.5
Block Diagram ............................................................................................................
Functional Description .................................................................................................
Register Access Timing ...............................................................................................
Initialization and Configuration .....................................................................................
Register Map ..............................................................................................................
Register Descriptions ..................................................................................................
784
784
785
785
785
786
13
Analog-to-Digital Converter (ADC) ..................................................................... 808
13.1
13.2
13.3
13.3.1
13.3.2
13.3.3
13.3.4
13.3.5
13.3.6
13.3.7
13.4
13.4.1
13.4.2
13.5
13.6
Block Diagram ............................................................................................................ 809
Signal Description ....................................................................................................... 810
Functional Description ................................................................................................. 811
Sample Sequencers .................................................................................................... 812
Module Control ............................................................................................................ 812
Hardware Sample Averaging Circuit ............................................................................. 816
Analog-to-Digital Converter .......................................................................................... 817
Differential Sampling ................................................................................................... 820
Internal Temperature Sensor ........................................................................................ 822
Digital Comparator Unit ............................................................................................... 823
Initialization and Configuration ..................................................................................... 827
Module Initialization ..................................................................................................... 827
Sample Sequencer Configuration ................................................................................. 828
Register Map .............................................................................................................. 828
Register Descriptions .................................................................................................. 830
14
Universal Asynchronous Receivers/Transmitters (UARTs) ............................. 908
14.1
Block Diagram ............................................................................................................
14.2
Signal Description .......................................................................................................
14.3
Functional Description .................................................................................................
14.3.1 Transmit/Receive Logic ...............................................................................................
14.3.2 Baud-Rate Generation .................................................................................................
14.3.3 Data Transmission ......................................................................................................
14.3.4 Serial IR (SIR) .............................................................................................................
14.3.5 ISO 7816 Support .......................................................................................................
14.3.6 Modem Handshake Support .........................................................................................
14.3.7 9-Bit UART Mode ........................................................................................................
14.3.8 FIFO Operation ...........................................................................................................
14.3.9 Interrupts ....................................................................................................................
14.3.10 Loopback Operation ....................................................................................................
14.3.11 DMA Operation ...........................................................................................................
14.4
Initialization and Configuration .....................................................................................
14.5
Register Map ..............................................................................................................
14.6
Register Descriptions ..................................................................................................
909
909
910
911
911
912
912
914
914
915
916
916
917
917
918
919
921
15
Synchronous Serial Interface (SSI) .................................................................... 969
15.1
15.2
15.3
Block Diagram ............................................................................................................ 970
Signal Description ....................................................................................................... 970
Functional Description ................................................................................................. 971
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15.3.1
15.3.2
15.3.3
15.3.4
15.3.5
15.4
15.5
15.6
Bit Rate Generation .....................................................................................................
FIFO Operation ...........................................................................................................
Interrupts ....................................................................................................................
Frame Formats ...........................................................................................................
DMA Operation ...........................................................................................................
Initialization and Configuration .....................................................................................
Register Map ..............................................................................................................
Register Descriptions ..................................................................................................
972
972
972
973
981
982
984
985
16
Inter-Integrated Circuit (I2C) Interface .............................................................. 1014
16.1
16.2
16.3
16.3.1
16.3.2
16.3.3
16.3.4
16.3.5
16.4
16.4.1
16.4.2
16.5
16.6
16.7
16.8
Block Diagram ........................................................................................................... 1015
Signal Description ..................................................................................................... 1015
Functional Description ............................................................................................... 1016
I2C Bus Functional Overview ...................................................................................... 1016
Available Speed Modes ............................................................................................. 1021
Interrupts .................................................................................................................. 1023
Loopback Operation .................................................................................................. 1024
Command Sequence Flow Charts .............................................................................. 1024
Initialization and Configuration .................................................................................... 1032
Configure the I2C Module to Transmit a Single Byte as a Master .................................. 1032
Configure the I2C Master to High Speed Mode ............................................................ 1033
Register Map ............................................................................................................ 1034
Register Descriptions (I2C Master) .............................................................................. 1035
Register Descriptions (I2C Slave) ............................................................................... 1052
Register Descriptions (I2C Status and Control) ............................................................ 1062
17
Controller Area Network (CAN) Module ........................................................... 1065
17.1
Block Diagram ........................................................................................................... 1066
17.2
Signal Description ..................................................................................................... 1066
17.3
Functional Description ............................................................................................... 1067
17.3.1 Initialization ............................................................................................................... 1068
17.3.2 Operation .................................................................................................................. 1069
17.3.3 Transmitting Message Objects ................................................................................... 1070
17.3.4 Configuring a Transmit Message Object ...................................................................... 1070
17.3.5 Updating a Transmit Message Object ......................................................................... 1071
17.3.6 Accepting Received Message Objects ........................................................................ 1072
17.3.7 Receiving a Data Frame ............................................................................................ 1072
17.3.8 Receiving a Remote Frame ........................................................................................ 1072
17.3.9 Receive/Transmit Priority ........................................................................................... 1073
17.3.10 Configuring a Receive Message Object ...................................................................... 1073
17.3.11 Handling of Received Message Objects ...................................................................... 1074
17.3.12 Handling of Interrupts ................................................................................................ 1076
17.3.13 Test Mode ................................................................................................................. 1077
17.3.14 Bit Timing Configuration Error Considerations ............................................................. 1079
17.3.15 Bit Time and Bit Rate ................................................................................................. 1079
17.3.16 Calculating the Bit Timing Parameters ........................................................................ 1081
17.4
Register Map ............................................................................................................ 1084
17.5
CAN Register Descriptions ......................................................................................... 1085
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18
Analog Comparators .......................................................................................... 1116
18.1
18.2
18.3
18.3.1
18.4
18.5
18.6
Block Diagram ...........................................................................................................
Signal Description .....................................................................................................
Functional Description ...............................................................................................
Internal Reference Programming ................................................................................
Initialization and Configuration ....................................................................................
Register Map ............................................................................................................
Register Descriptions .................................................................................................
1117
1117
1118
1119
1121
1122
1122
19
Pulse Width Modulator (PWM) .......................................................................... 1132
19.1
19.2
19.3
19.3.1
19.3.2
19.3.3
19.3.4
19.3.5
19.3.6
19.3.7
19.3.8
19.3.9
19.4
19.5
19.6
Block Diagram ........................................................................................................... 1133
Signal Description ..................................................................................................... 1135
Functional Description ............................................................................................... 1136
Clock Configuration ................................................................................................... 1136
PWM Timer ............................................................................................................... 1136
PWM Comparators .................................................................................................... 1137
PWM Signal Generator .............................................................................................. 1138
Dead-Band Generator ............................................................................................... 1139
Interrupt/ADC-Trigger Selector ................................................................................... 1139
Synchronization Methods .......................................................................................... 1140
Fault Conditions ........................................................................................................ 1141
Output Control Block .................................................................................................. 1142
Initialization and Configuration .................................................................................... 1142
Register Map ............................................................................................................ 1143
Register Descriptions ................................................................................................. 1146
20
Quadrature Encoder Interface (QEI) ................................................................. 1211
20.1
20.2
20.3
20.4
20.5
20.6
Block Diagram ...........................................................................................................
Signal Description .....................................................................................................
Functional Description ...............................................................................................
Initialization and Configuration ....................................................................................
Register Map ............................................................................................................
Register Descriptions .................................................................................................
21
Pin Diagram ........................................................................................................ 1234
1211
1213
1214
1216
1217
1217
22
Signal Tables ...................................................................................................... 1235
22.1
22.2
22.3
22.4
22.5
22.6
Signals by Pin Number ..............................................................................................
Signals by Signal Name .............................................................................................
Signals by Function, Except for GPIO .........................................................................
GPIO Pins and Alternate Functions ............................................................................
Possible Pin Assignments for Alternate Functions .......................................................
Connections for Unused Signals .................................................................................
1236
1249
1262
1273
1276
1280
23
Electrical Characteristics .................................................................................. 1282
23.1
23.2
23.3
23.4
23.5
23.6
23.6.1
Maximum Ratings ......................................................................................................
Operating Characteristics ...........................................................................................
Recommended Operating Conditions .........................................................................
Load Conditions ........................................................................................................
JTAG and Boundary Scan ..........................................................................................
Power and Brown-Out ...............................................................................................
VDDA Levels ............................................................................................................
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1283
1284
1286
1287
1289
1289
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23.6.2 VDD Levels ............................................................................................................... 1290
23.6.3 VDDC Levels ............................................................................................................ 1291
23.6.4 VDD Glitches ............................................................................................................ 1292
23.6.5 VDD Droop Response ............................................................................................... 1292
23.7
Reset ........................................................................................................................ 1294
23.8
On-Chip Low Drop-Out (LDO) Regulator ..................................................................... 1297
23.9
Clocks ...................................................................................................................... 1298
23.9.1 PLL Specifications ..................................................................................................... 1298
23.9.2 PIOSC Specifications ................................................................................................ 1299
23.9.3 Low-Frequency Internal Oscillator (LFIOSC) Specifications .......................................... 1299
23.9.4 Hibernation Clock Source Specifications ..................................................................... 1299
23.9.5 Main Oscillator Specifications ..................................................................................... 1300
23.9.6 System Clock Specification with ADC Operation .......................................................... 1304
23.10 Sleep Modes ............................................................................................................. 1305
23.11 Hibernation Module ................................................................................................... 1307
23.12 Flash Memory and EEPROM ..................................................................................... 1309
23.13 Input/Output Pin Characteristics ................................................................................. 1310
23.13.1 GPIO Module Characteristics ..................................................................................... 1310
23.13.2 Types of I/O Pins and ESD Protection ......................................................................... 1310
23.14 Analog-to-Digital Converter (ADC) .............................................................................. 1314
23.15 Synchronous Serial Interface (SSI) ............................................................................. 1318
23.16 Inter-Integrated Circuit (I2C) Interface ......................................................................... 1321
23.17 Analog Comparator ................................................................................................... 1322
23.18 Pulse-Width Modulator (PWM) ................................................................................... 1323
23.19 Current Consumption ................................................................................................. 1324
A
Package Information .......................................................................................... 1327
A.1
A.2
A.3
A.4
Orderable Devices .....................................................................................................
Device Nomenclature ................................................................................................
Device Markings ........................................................................................................
Packaging Diagram ...................................................................................................
10
1327
1327
1328
1329
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Tiva™ TM4C123BH6PGE Microcontroller
List of Figures
Figure 1-1.
Figure 2-1.
Figure 2-2.
Figure 2-3.
Figure 2-4.
Figure 2-5.
Figure 2-6.
Figure 2-7.
Figure 3-1.
Figure 3-2.
Figure 4-1.
Figure 4-2.
Figure 4-3.
Figure 4-4.
Figure 4-5.
Figure 5-1.
Figure 5-2.
Figure 5-3.
Figure 5-4.
Figure 5-5.
Figure 5-6.
Figure 7-1.
Figure 7-2.
Figure 7-3.
Figure 7-4.
Figure 7-5.
Figure 7-6.
Figure 8-1.
Figure 8-2.
Figure 9-1.
Figure 9-2.
Figure 9-3.
Figure 9-4.
Figure 9-5.
Figure 9-6.
Figure 10-1.
Figure 10-2.
Figure 10-3.
Figure 10-4.
Figure 11-1.
Figure 11-2.
Figure 11-3.
Figure 11-4.
Figure 11-5.
Figure 11-6.
Tiva™ TM4C123BH6PGE Microcontroller High-Level Block Diagram ....................... 44
CPU Block Diagram ............................................................................................. 66
TPIU Block Diagram ............................................................................................ 67
Cortex-M4F Register Set ...................................................................................... 70
Bit-Band Mapping ................................................................................................ 94
Data Storage ....................................................................................................... 95
Vector Table ...................................................................................................... 103
Exception Stack Frame ...................................................................................... 106
SRD Use Example ............................................................................................. 124
FPU Register Bank ............................................................................................ 127
JTAG Module Block Diagram .............................................................................. 197
Test Access Port State Machine ......................................................................... 200
IDCODE Register Format ................................................................................... 206
BYPASS Register Format ................................................................................... 206
Boundary Scan Register Format ......................................................................... 207
Basic RST Configuration .................................................................................... 211
External Circuitry to Extend Power-On Reset ....................................................... 211
Reset Circuit Controlled by Switch ...................................................................... 212
Power Architecture ............................................................................................ 215
Main Clock Tree ................................................................................................ 218
Module Clock Selection ...................................................................................... 224
Hibernation Module Block Diagram ..................................................................... 492
Using a Crystal as the Hibernation Clock Source with a Single Battery Source ...... 495
Using a Dedicated Oscillator as the Hibernation Clock Source with VDD3ON
Mode ................................................................................................................ 495
Using a Regulator for Both VDD and VBAT ............................................................ 496
Counter Behavior with a TRIM Value of 0x8002 ................................................... 499
Counter Behavior with a TRIM Value of 0x7FFC .................................................. 499
Internal Memory Block Diagram .......................................................................... 522
EEPROM Block Diagram ................................................................................... 523
μDMA Block Diagram ......................................................................................... 584
Example of Ping-Pong μDMA Transaction ........................................................... 590
Memory Scatter-Gather, Setup and Configuration ................................................ 592
Memory Scatter-Gather, μDMA Copy Sequence .................................................. 593
Peripheral Scatter-Gather, Setup and Configuration ............................................. 595
Peripheral Scatter-Gather, μDMA Copy Sequence ............................................... 596
Digital I/O Pads ................................................................................................. 652
Analog/Digital I/O Pads ...................................................................................... 653
GPIODATA Write Example ................................................................................. 654
GPIODATA Read Example ................................................................................. 654
GPTM Module Block Diagram ............................................................................ 713
Reading the RTC Value ...................................................................................... 721
Input Edge-Count Mode Example, Counting Down ............................................... 723
16-Bit Input Edge-Time Mode Example ............................................................... 724
16-Bit PWM Mode Example ................................................................................ 726
CCP Output, GPTMTnMATCHR > GPTMTnILR ................................................... 726
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Table of Contents
Figure 11-7.
Figure 11-8.
Figure 11-9.
Figure 12-1.
Figure 13-1.
Figure 13-2.
Figure 13-3.
Figure 13-4.
Figure 13-5.
Figure 13-6.
Figure 13-7.
Figure 13-8.
Figure 13-9.
Figure 13-10.
Figure 13-11.
Figure 13-12.
Figure 13-13.
Figure 13-14.
Figure 14-1.
Figure 14-2.
Figure 14-3.
Figure 15-1.
Figure 15-2.
Figure 15-3.
Figure 15-4.
Figure 15-5.
Figure 15-6.
Figure 15-7.
Figure 15-8.
Figure 15-9.
Figure 15-10.
Figure 15-11.
Figure 15-12.
Figure 16-1.
Figure 16-2.
Figure 16-3.
Figure 16-4.
Figure 16-5.
Figure 16-6.
Figure 16-7.
Figure 16-8.
Figure 16-9.
Figure 16-10.
Figure 16-11.
Figure 16-12.
Figure 16-13.
Figure 16-14.
Figure 16-15.
CCP Output, GPTMTnMATCHR = GPTMTnILR ................................................... 727
CCP Output, GPTMTnILR > GPTMTnMATCHR ................................................... 727
Timer Daisy Chain ............................................................................................. 728
WDT Module Block Diagram .............................................................................. 784
Implementation of Two ADC Blocks .................................................................... 809
ADC Module Block Diagram ............................................................................... 810
ADC Sample Phases ......................................................................................... 814
Doubling the ADC Sample Rate .......................................................................... 814
Skewed Sampling .............................................................................................. 815
Sample Averaging Example ............................................................................... 817
ADC Input Equivalency ...................................................................................... 818
ADC Voltage Reference ..................................................................................... 819
ADC Conversion Result ..................................................................................... 820
Differential Voltage Representation ..................................................................... 822
Internal Temperature Sensor Characteristic ......................................................... 823
Low-Band Operation (CIC=0x0 and/or CTC=0x0) ................................................ 825
Mid-Band Operation (CIC=0x1 and/or CTC=0x1) ................................................. 826
High-Band Operation (CIC=0x3 and/or CTC=0x3) ................................................ 827
UART Module Block Diagram ............................................................................. 909
UART Character Frame ..................................................................................... 911
IrDA Data Modulation ......................................................................................... 913
SSI Module Block Diagram ................................................................................. 970
TI Synchronous Serial Frame Format (Single Transfer) ........................................ 974
TI Synchronous Serial Frame Format (Continuous Transfer) ................................ 975
Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 .......................... 976
Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .................. 976
Freescale SPI Frame Format with SPO=0 and SPH=1 ......................................... 977
Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ............... 978
Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ........ 978
Freescale SPI Frame Format with SPO=1 and SPH=1 ......................................... 979
MICROWIRE Frame Format (Single Frame) ........................................................ 980
MICROWIRE Frame Format (Continuous Transfer) ............................................. 981
MICROWIRE Frame Format, SSInFss Input Setup and Hold Requirements .......... 981
I2C Block Diagram ........................................................................................... 1015
I2C Bus Configuration ....................................................................................... 1016
START and STOP Conditions ........................................................................... 1017
Complete Data Transfer with a 7-Bit Address ..................................................... 1017
R/S Bit in First Byte .......................................................................................... 1018
Data Validity During Bit Transfer on the I2C Bus ................................................. 1018
High-Speed Data Format .................................................................................. 1023
Master Single TRANSMIT ................................................................................ 1025
Master Single RECEIVE ................................................................................... 1026
Master TRANSMIT of Multiple Data Bytes ......................................................... 1027
Master RECEIVE of Multiple Data Bytes ............................................................ 1028
Master RECEIVE with Repeated START after Master TRANSMIT ....................... 1029
Master TRANSMIT with Repeated START after Master RECEIVE ....................... 1030
Standard High Speed Mode Master Transmit ..................................................... 1031
Slave Command Sequence .............................................................................. 1032
12
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Figure 17-1.
Figure 17-2.
Figure 17-3.
Figure 17-4.
Figure 18-1.
Figure 18-2.
Figure 18-3.
Figure 19-1.
Figure 19-2.
Figure 19-3.
Figure 19-4.
Figure 19-5.
Figure 19-6.
Figure 20-1.
Figure 20-2.
Figure 20-3.
Figure 21-1.
Figure 23-1.
Figure 23-2.
Figure 23-3.
Figure 23-4.
Figure 23-5.
Figure 23-6.
Figure 23-7.
Figure 23-8.
Figure 23-9.
Figure 23-10.
Figure 23-11.
Figure 23-12.
Figure 23-13.
Figure 23-14.
Figure 23-15.
Figure 23-16.
Figure 23-17.
Figure 23-18.
Figure 23-19.
Figure 23-20.
Figure 23-21.
Figure 23-22.
Figure 23-23.
Figure 23-24.
Figure A-1.
Figure A-2.
CAN Controller Block Diagram .......................................................................... 1066
CAN Data/Remote Frame ................................................................................. 1068
Message Objects in a FIFO Buffer .................................................................... 1076
CAN Bit Time ................................................................................................... 1080
Analog Comparator Module Block Diagram ....................................................... 1117
Structure of Comparator Unit ............................................................................ 1118
Comparator Internal Reference Structure .......................................................... 1119
PWM Module Diagram ..................................................................................... 1134
PWM Generator Block Diagram ........................................................................ 1134
PWM Count-Down Mode .................................................................................. 1138
PWM Count-Up/Down Mode ............................................................................. 1138
PWM Generation Example In Count-Up/Down Mode .......................................... 1139
PWM Dead-Band Generator ............................................................................. 1139
QEI Block Diagram .......................................................................................... 1212
QEI Input Signal Logic ...................................................................................... 1213
Quadrature Encoder and Velocity Predivider Operation ...................................... 1215
144-Pin LQFP Package Pin Diagram ................................................................ 1234
Load Conditions ............................................................................................... 1286
JTAG Test Clock Input Timing ........................................................................... 1287
JTAG Test Access Port (TAP) Timing ................................................................ 1288
Power Assertions versus VDDA Levels ............................................................. 1290
Power and Brown-Out Assertions versus VDD Levels ........................................ 1291
POK assertion vs VDDC ................................................................................... 1292
POR-BOR0-BOR1 VDD Glitch Response .......................................................... 1292
POR-BOR0-BOR1 VDD Droop Response ......................................................... 1293
Digital Power-On Reset Timing ......................................................................... 1294
Brown-Out Reset Timing .................................................................................. 1295
External Reset Timing (RST) ............................................................................ 1295
Software Reset Timing ..................................................................................... 1295
Watchdog Reset Timing ................................................................................... 1295
MOSC Failure Reset Timing ............................................................................. 1296
Hibernation Module Timing ............................................................................... 1308
ESD Protection on Fail-Safe Pins ...................................................................... 1311
ESD Protection on Non-Fail-Safe Pins .............................................................. 1312
ADC External Reference Filtering ..................................................................... 1316
ADC Input Equivalency Diagram ....................................................................... 1317
SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing
Measurement .................................................................................................. 1319
SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............... 1319
Master Mode SSI Timing for SPI Frame Format (FRF=00), with SPH=1 .............. 1320
Slave Mode SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................ 1320
I2C Timing ....................................................................................................... 1321
Key to Part Numbers ........................................................................................ 1327
TM4C123BH6PGE 144-Pin LQFP Package Diagram ......................................... 1329
June 12, 2014
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Texas Instruments-Production Data
Table of Contents
List of Tables
Table 1.
Table 2.
Table 1-1.
Table 2-1.
Table 2-2.
Table 2-3.
Table 2-4.
Table 2-5.
Table 2-6.
Table 2-7.
Table 2-8.
Table 2-9.
Table 2-10.
Table 2-11.
Table 2-12.
Table 2-13.
Table 3-1.
Table 3-2.
Table 3-3.
Table 3-4.
Table 3-5.
Table 3-6.
Table 3-7.
Table 3-8.
Table 3-9.
Table 3-10.
Table 4-1.
Table 4-2.
Table 4-3.
Table 5-1.
Table 5-2.
Table 5-3.
Table 5-4.
Table 5-5.
Table 5-6.
Table 5-7.
Table 5-8.
Table 6-1.
Table 7-1.
Table 7-2.
Table 7-3.
Table 8-1.
Table 8-2.
Table 8-3.
Table 9-1.
Table 9-2.
Revision History .................................................................................................. 34
Documentation Conventions ................................................................................ 39
TM4C123BH6PGE Microcontroller Features ......................................................... 42
Summary of Processor Mode, Privilege Level, and Stack Use ................................ 69
Processor Register Map ....................................................................................... 70
PSR Register Combinations ................................................................................. 76
Memory Map ....................................................................................................... 87
Memory Access Behavior ..................................................................................... 91
SRAM Memory Bit-Banding Regions .................................................................... 93
Peripheral Memory Bit-Banding Regions ............................................................... 93
Exception Types .................................................................................................. 99
Interrupts ............................................................................................................ 99
Exception Return Behavior ................................................................................. 107
Faults ............................................................................................................... 108
Fault Status and Fault Address Registers ............................................................ 109
Cortex-M4F Instruction Summary ....................................................................... 111
Core Peripheral Register Regions ....................................................................... 118
Memory Attributes Summary .............................................................................. 122
TEX, S, C, and B Bit Field Encoding ................................................................... 124
Cache Policy for Memory Attribute Encoding ....................................................... 125
AP Bit Field Encoding ........................................................................................ 125
Memory Region Attributes for Tiva™ C Series Microcontrollers ............................. 126
QNaN and SNaN Handling ................................................................................. 129
Peripherals Register Map ................................................................................... 130
Interrupt Priority Levels ...................................................................................... 160
Example SIZE Field Values ................................................................................ 188
JTAG_SWD_SWO Signals (144LQFP) ................................................................ 197
JTAG Port Pins State after Power-On Reset or RST assertion .............................. 198
JTAG Instruction Register Commands ................................................................. 204
System Control & Clocks Signals (144LQFP) ...................................................... 208
Reset Sources ................................................................................................... 209
Clock Source Options ........................................................................................ 216
Possible System Clock Frequencies Using the SYSDIV Field ............................... 219
Examples of Possible System Clock Frequencies Using the SYSDIV2 Field .......... 219
Examples of Possible System Clock Frequencies with DIV400=1 ......................... 220
System Control Register Map ............................................................................. 227
RCC2 Fields that Override RCC Fields ............................................................... 255
System Exception Register Map ......................................................................... 483
Hibernate Signals (144LQFP) ............................................................................. 492
Hibernation Module Clock Operation ................................................................... 502
Hibernation Module Register Map ....................................................................... 504
Flash Memory Protection Policy Combinations .................................................... 527
User-Programmable Flash Memory Resident Registers ....................................... 531
Flash Register Map ............................................................................................ 538
μDMA Channel Assignments .............................................................................. 585
Request Type Support ....................................................................................... 587
14
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Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Table 9-3.
Table 9-4.
Table 9-5.
Table 9-6.
Table 9-7.
Table 9-8.
Table 9-9.
Table 9-10.
Table 9-11.
Table 9-12.
Control Structure Memory Map ........................................................................... 588
Channel Control Structure .................................................................................. 588
μDMA Read Example: 8-Bit Peripheral ................................................................ 597
μDMA Interrupt Assignments .............................................................................. 598
Channel Control Structure Offsets for Channel 30 ................................................ 599
Channel Control Word Configuration for Memory Transfer Example ...................... 600
Channel Control Structure Offsets for Channel 7 .................................................. 601
Channel Control Word Configuration for Peripheral Transmit Example .................. 601
Primary and Alternate Channel Control Structure Offsets for Channel 8 ................. 602
Channel Control Word Configuration for Peripheral Ping-Pong Receive
Example ............................................................................................................ 603
Table 9-13.
μDMA Register Map .......................................................................................... 605
Table 10-1.
GPIO Pins With Special Considerations .............................................................. 648
Table 10-2.
GPIO Pins and Alternate Functions (144LQFP) ................................................... 648
Table 10-3.
GPIO Pad Configuration Examples ..................................................................... 657
Table 10-4.
GPIO Interrupt Configuration Example ................................................................ 658
Table 10-5.
GPIO Pins With Special Considerations .............................................................. 659
Table 10-6.
GPIO Register Map ........................................................................................... 660
Table 10-7.
GPIO Pins With Special Considerations .............................................................. 676
Table 10-8.
GPIO Pins With Special Considerations .............................................................. 683
Table 10-9.
GPIO Pins With Special Considerations .............................................................. 685
Table 10-10. GPIO Pins With Special Considerations .............................................................. 688
Table 10-11. GPIO Pins With Special Considerations .............................................................. 695
Table 11-1.
Available CCP Pins ............................................................................................ 714
Table 11-2.
General-Purpose Timers Signals (144LQFP) ....................................................... 714
Table 11-3.
General-Purpose Timer Capabilities .................................................................... 717
Table 11-4.
Counter Values When the Timer is Enabled in Periodic or One-Shot Modes .......... 718
Table 11-5.
16-Bit Timer With Prescaler Configurations ......................................................... 719
Table 11-6.
32-Bit Timer (configured in 32/64-bit mode) With Prescaler Configurations ............ 720
Table 11-7.
Counter Values When the Timer is Enabled in RTC Mode .................................... 720
Table 11-8.
Counter Values When the Timer is Enabled in Input Edge-Count Mode ................. 722
Table 11-9.
Counter Values When the Timer is Enabled in Input Event-Count Mode ................ 723
Table 11-10. Counter Values When the Timer is Enabled in PWM Mode ................................... 725
Table 11-11. Timeout Actions for GPTM Modes ...................................................................... 728
Table 11-12. Timers Register Map .......................................................................................... 735
Table 12-1.
Watchdog Timers Register Map .......................................................................... 786
Table 13-1.
ADC Signals (144LQFP) .................................................................................... 810
Table 13-2.
Samples and FIFO Depth of Sequencers ............................................................ 812
Table 13-3.
Differential Sampling Pairs ................................................................................. 820
Table 13-4.
ADC Register Map ............................................................................................. 828
Table 14-1.
UART Signals (144LQFP) .................................................................................. 910
Table 14-2.
Flow Control Mode ............................................................................................. 915
Table 14-3.
UART Register Map ........................................................................................... 920
Table 15-1.
SSI Signals (144LQFP) ...................................................................................... 971
Table 15-2.
SSI Register Map .............................................................................................. 984
Table 16-1.
I2C Signals (144LQFP) .................................................................................... 1015
Table 16-2.
Examples of I2C Master Timer Period Versus Speed Mode ................................. 1021
Table 16-3.
Examples of I2C Master Timer Period in High-Speed Mode ................................ 1022
June 12, 2014
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Texas Instruments-Production Data
Table of Contents
Table 16-4.
Table 16-5.
Table 17-1.
Table 17-2.
Table 17-3.
Table 17-4.
Table 17-5.
Table 18-1.
Table 18-2.
Table 18-3.
Table 18-4.
Table 18-5.
Table 19-1.
Table 19-2.
Table 20-1.
Table 20-2.
Table 22-1.
Table 22-2.
Table 22-3.
Table 22-4.
Table 22-5.
Table 22-6.
Table 22-7.
Table 23-1.
Table 23-2.
Table 23-3.
Table 23-4.
Table 23-5.
Table 23-6.
Table 23-7.
Table 23-8.
Table 23-9.
Table 23-10.
Table 23-11.
Table 23-12.
Table 23-13.
Table 23-14.
Table 23-15.
Table 23-16.
Table 23-17.
Table 23-18.
Table 23-19.
Table 23-20.
Table 23-21.
Table 23-22.
Table 23-23.
Inter-Integrated Circuit (I2C) Interface Register Map ........................................... 1034
Write Field Decoding for I2CMCS[3:0] Field ....................................................... 1040
Controller Area Network Signals (144LQFP) ...................................................... 1067
Message Object Configurations ........................................................................ 1073
CAN Protocol Ranges ...................................................................................... 1080
CANBIT Register Values .................................................................................. 1080
CAN Register Map ........................................................................................... 1084
Analog Comparators Signals (144LQFP) ........................................................... 1117
Internal Reference Voltage and ACREFCTL Field Values ................................... 1119
Analog Comparator Voltage Reference Characteristics, VDDA = 3.3V, EN= 1, and
RNG = 0 .......................................................................................................... 1120
Analog Comparator Voltage Reference Characteristics, VDDA = 3.3V, EN= 1, and
RNG = 1 .......................................................................................................... 1121
Analog Comparators Register Map ................................................................... 1122
PWM Signals (144LQFP) ................................................................................. 1135
PWM Register Map .......................................................................................... 1143
QEI Signals (144LQFP) .................................................................................... 1213
QEI Register Map ............................................................................................ 1217
GPIO Pins With Special Considerations ............................................................ 1235
Signals by Pin Number ..................................................................................... 1236
Signals by Signal Name ................................................................................... 1249
Signals by Function, Except for GPIO ............................................................... 1262
GPIO Pins and Alternate Functions ................................................................... 1273
Possible Pin Assignments for Alternate Functions .............................................. 1276
Connections for Unused Signals (144-Pin LQFP) ............................................... 1280
Absolute Maximum Ratings .............................................................................. 1282
ESD Absolute Maximum Ratings ...................................................................... 1282
Temperature Characteristics ............................................................................. 1283
Thermal Characteristics ................................................................................... 1283
Recommended DC Operating Conditions .......................................................... 1284
Recommended GPIO Pad Operating Conditions ................................................ 1284
GPIO Current Restrictions ................................................................................ 1284
GPIO Package Side Assignments ..................................................................... 1285
JTAG Characteristics ....................................................................................... 1287
Power-On and Brown-Out Levels ...................................................................... 1289
Reset Characteristics ....................................................................................... 1294
LDO Regulator Characteristics ......................................................................... 1297
Phase Locked Loop (PLL) Characteristics ......................................................... 1298
Actual PLL Frequency ...................................................................................... 1298
PIOSC Clock Characteristics ............................................................................ 1299
Low-Frequency internal Oscillator Characteristics .............................................. 1299
Hibernation Oscillator Input Characteristics ........................................................ 1299
Main Oscillator Input Characteristics ................................................................. 1300
Crystal Parameters .......................................................................................... 1302
Supported MOSC Crystal Frequencies .............................................................. 1303
System Clock Characteristics with ADC Operation ............................................. 1304
Sleep Modes AC Characteristics ....................................................................... 1305
Time to Wake with Respect to Low-Power Modes .............................................. 1305
16
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Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Table 23-24.
Table 23-25.
Table 23-26.
Table 23-27.
Table 23-28.
Table 23-29.
Table 23-30.
Table 23-31.
Table 23-32.
Table 23-33.
Table 23-34.
Table 23-35.
Table 23-36.
Table 23-37.
Hibernation Module Battery Characteristics ....................................................... 1307
Hibernation Module AC Characteristics ............................................................. 1307
Flash Memory Characteristics ........................................................................... 1309
EEPROM Characteristics ................................................................................. 1309
GPIO Module Characteristics ............................................................................ 1310
Pad Voltage/Current Characteristics for Fail-Safe Pins ....................................... 1311
Fail-Safe GPIOs that Require an External Pull-up .............................................. 1312
Non-Fail-Safe I/O Pad Voltage/Current Characteristics ....................................... 1312
ADC Electrical Characteristics .......................................................................... 1314
SSI Characteristics .......................................................................................... 1318
I2C Characteristics ........................................................................................... 1321
Analog Comparator Characteristics ................................................................... 1322
Analog Comparator Voltage Reference Characteristics ...................................... 1322
Analog Comparator Voltage Reference Characteristics, VDDA = 3.3V, EN= 1, and
RNG = 0 .......................................................................................................... 1322
Table 23-38. Analog Comparator Voltage Reference Characteristics, VDDA = 3.3V, EN= 1, and
RNG = 1 .......................................................................................................... 1323
Table 23-39. PWM Timing Characteristics ............................................................................. 1323
Table 23-40. Current Consumption ....................................................................................... 1324
June 12, 2014
17
Texas Instruments-Production Data
Table of Contents
List of Registers
The Cortex-M4F Processor ........................................................................................................... 64
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Cortex General-Purpose Register 0 (R0) ........................................................................... 72
Cortex General-Purpose Register 1 (R1) ........................................................................... 72
Cortex General-Purpose Register 2 (R2) ........................................................................... 72
Cortex General-Purpose Register 3 (R3) ........................................................................... 72
Cortex General-Purpose Register 4 (R4) ........................................................................... 72
Cortex General-Purpose Register 5 (R5) ........................................................................... 72
Cortex General-Purpose Register 6 (R6) ........................................................................... 72
Cortex General-Purpose Register 7 (R7) ........................................................................... 72
Cortex General-Purpose Register 8 (R8) ........................................................................... 72
Cortex General-Purpose Register 9 (R9) ........................................................................... 72
Cortex General-Purpose Register 10 (R10) ....................................................................... 72
Cortex General-Purpose Register 11 (R11) ........................................................................ 72
Cortex General-Purpose Register 12 (R12) ....................................................................... 72
Stack Pointer (SP) ........................................................................................................... 73
Link Register (LR) ............................................................................................................ 74
Program Counter (PC) ..................................................................................................... 75
Program Status Register (PSR) ........................................................................................ 76
Priority Mask Register (PRIMASK) .................................................................................... 80
Fault Mask Register (FAULTMASK) .................................................................................. 81
Base Priority Mask Register (BASEPRI) ............................................................................ 82
Control Register (CONTROL) ........................................................................................... 83
Floating-Point Status Control (FPSC) ................................................................................ 85
Cortex-M4 Peripherals ................................................................................................................. 118
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
SysTick Control and Status Register (STCTRL), offset 0x010 ........................................... 134
SysTick Reload Value Register (STRELOAD), offset 0x014 .............................................. 136
SysTick Current Value Register (STCURRENT), offset 0x018 ........................................... 137
Interrupt 0-31 Set Enable (EN0), offset 0x100 .................................................................. 138
Interrupt 32-63 Set Enable (EN1), offset 0x104 ................................................................ 138
Interrupt 64-95 Set Enable (EN2), offset 0x108 ................................................................ 138
Interrupt 96-127 Set Enable (EN3), offset 0x10C ............................................................. 138
Interrupt 128-138 Set Enable (EN4), offset 0x110 ............................................................ 139
Interrupt 0-31 Clear Enable (DIS0), offset 0x180 .............................................................. 140
Interrupt 32-63 Clear Enable (DIS1), offset 0x184 ............................................................ 140
Interrupt 64-95 Clear Enable (DIS2), offset 0x188 ............................................................ 140
Interrupt 96-127 Clear Enable (DIS3), offset 0x18C .......................................................... 140
Interrupt 128-138 Clear Enable (DIS4), offset 0x190 ........................................................ 141
Interrupt 0-31 Set Pending (PEND0), offset 0x200 ........................................................... 142
Interrupt 32-63 Set Pending (PEND1), offset 0x204 ......................................................... 142
Interrupt 64-95 Set Pending (PEND2), offset 0x208 ......................................................... 142
Interrupt 96-127 Set Pending (PEND3), offset 0x20C ....................................................... 142
Interrupt 128-138 Set Pending (PEND4), offset 0x210 ...................................................... 143
Interrupt 0-31 Clear Pending (UNPEND0), offset 0x280 ................................................... 144
Interrupt 32-63 Clear Pending (UNPEND1), offset 0x284 .................................................. 144
Interrupt 64-95 Clear Pending (UNPEND2), offset 0x288 .................................................. 144
18
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Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
Register 29:
Register 30:
Register 31:
Register 32:
Register 33:
Register 34:
Register 35:
Register 36:
Register 37:
Register 38:
Register 39:
Register 40:
Register 41:
Register 42:
Register 43:
Register 44:
Register 45:
Register 46:
Register 47:
Register 48:
Register 49:
Register 50:
Register 51:
Register 52:
Register 53:
Register 54:
Register 55:
Register 56:
Register 57:
Register 58:
Register 59:
Register 60:
Register 61:
Register 62:
Register 63:
Register 64:
Register 65:
Register 66:
Register 67:
Register 68:
Register 69:
Interrupt 96-127 Clear Pending (UNPEND3), offset 0x28C ............................................... 144
Interrupt 128-138 Clear Pending (UNPEND4), offset 0x290 .............................................. 145
Interrupt 0-31 Active Bit (ACTIVE0), offset 0x300 ............................................................. 146
Interrupt 32-63 Active Bit (ACTIVE1), offset 0x304 ........................................................... 146
Interrupt 64-95 Active Bit (ACTIVE2), offset 0x308 ........................................................... 146
Interrupt 96-127 Active Bit (ACTIVE3), offset 0x30C ........................................................ 146
Interrupt 128-138 Active Bit (ACTIVE4), offset 0x310 ....................................................... 147
Interrupt 0-3 Priority (PRI0), offset 0x400 ......................................................................... 148
Interrupt 4-7 Priority (PRI1), offset 0x404 ......................................................................... 148
Interrupt 8-11 Priority (PRI2), offset 0x408 ....................................................................... 148
Interrupt 12-15 Priority (PRI3), offset 0x40C .................................................................... 148
Interrupt 16-19 Priority (PRI4), offset 0x410 ..................................................................... 148
Interrupt 20-23 Priority (PRI5), offset 0x414 ..................................................................... 148
Interrupt 24-27 Priority (PRI6), offset 0x418 ..................................................................... 148
Interrupt 28-31 Priority (PRI7), offset 0x41C .................................................................... 148
Interrupt 32-35 Priority (PRI8), offset 0x420 ..................................................................... 148
Interrupt 36-39 Priority (PRI9), offset 0x424 ..................................................................... 148
Interrupt 40-43 Priority (PRI10), offset 0x428 ................................................................... 148
Interrupt 44-47 Priority (PRI11), offset 0x42C ................................................................... 148
Interrupt 48-51 Priority (PRI12), offset 0x430 ................................................................... 148
Interrupt 52-55 Priority (PRI13), offset 0x434 ................................................................... 148
Interrupt 56-59 Priority (PRI14), offset 0x438 ................................................................... 148
Interrupt 60-63 Priority (PRI15), offset 0x43C .................................................................. 148
Interrupt 64-67 Priority (PRI16), offset 0x440 ................................................................... 150
Interrupt 68-71 Priority (PRI17), offset 0x444 ................................................................... 150
Interrupt 72-75 Priority (PRI18), offset 0x448 ................................................................... 150
Interrupt 76-79 Priority (PRI19), offset 0x44C .................................................................. 150
Interrupt 80-83 Priority (PRI20), offset 0x450 ................................................................... 150
Interrupt 84-87 Priority (PRI21), offset 0x454 ................................................................... 150
Interrupt 88-91 Priority (PRI22), offset 0x458 ................................................................... 150
Interrupt 92-95 Priority (PRI23), offset 0x45C .................................................................. 150
Interrupt 96-99 Priority (PRI24), offset 0x460 ................................................................... 150
Interrupt 100-103 Priority (PRI25), offset 0x464 ............................................................... 150
Interrupt 104-107 Priority (PRI26), offset 0x468 ............................................................... 150
Interrupt 108-111 Priority (PRI27), offset 0x46C ............................................................... 150
Interrupt 112-115 Priority (PRI28), offset 0x470 ................................................................ 150
Interrupt 116-119 Priority (PRI29), offset 0x474 ................................................................ 150
Interrupt 120-123 Priority (PRI30), offset 0x478 ............................................................... 150
Interrupt 124-127 Priority (PRI31), offset 0x47C ............................................................... 150
Interrupt 128-131 Priority (PRI32), offset 0x480 ............................................................... 150
Interrupt 132-135 Priority (PRI33), offset 0x484 ............................................................... 150
Interrupt 136-138 Priority (PRI34), offset 0x488 ............................................................... 150
Software Trigger Interrupt (SWTRIG), offset 0xF00 .......................................................... 152
Auxiliary Control (ACTLR), offset 0x008 .......................................................................... 153
CPU ID Base (CPUID), offset 0xD00 ............................................................................... 155
Interrupt Control and State (INTCTRL), offset 0xD04 ........................................................ 156
Vector Table Offset (VTABLE), offset 0xD08 .................................................................... 159
Application Interrupt and Reset Control (APINT), offset 0xD0C ......................................... 160
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Table of Contents
Register 70:
Register 71:
Register 72:
Register 73:
Register 74:
Register 75:
Register 76:
Register 77:
Register 78:
Register 79:
Register 80:
Register 81:
Register 82:
Register 83:
Register 84:
Register 85:
Register 86:
Register 87:
Register 88:
Register 89:
Register 90:
Register 91:
Register 92:
Register 93:
Register 94:
System Control (SYSCTRL), offset 0xD10 ....................................................................... 162
Configuration and Control (CFGCTRL), offset 0xD14 ....................................................... 164
System Handler Priority 1 (SYSPRI1), offset 0xD18 ......................................................... 166
System Handler Priority 2 (SYSPRI2), offset 0xD1C ........................................................ 167
System Handler Priority 3 (SYSPRI3), offset 0xD20 ......................................................... 168
System Handler Control and State (SYSHNDCTRL), offset 0xD24 .................................... 169
Configurable Fault Status (FAULTSTAT), offset 0xD28 ..................................................... 173
Hard Fault Status (HFAULTSTAT), offset 0xD2C .............................................................. 179
Memory Management Fault Address (MMADDR), offset 0xD34 ........................................ 180
Bus Fault Address (FAULTADDR), offset 0xD38 .............................................................. 181
MPU Type (MPUTYPE), offset 0xD90 ............................................................................. 182
MPU Control (MPUCTRL), offset 0xD94 .......................................................................... 183
MPU Region Number (MPUNUMBER), offset 0xD98 ....................................................... 185
MPU Region Base Address (MPUBASE), offset 0xD9C ................................................... 186
MPU Region Base Address Alias 1 (MPUBASE1), offset 0xDA4 ....................................... 186
MPU Region Base Address Alias 2 (MPUBASE2), offset 0xDAC ...................................... 186
MPU Region Base Address Alias 3 (MPUBASE3), offset 0xDB4 ....................................... 186
MPU Region Attribute and Size (MPUATTR), offset 0xDA0 ............................................... 188
MPU Region Attribute and Size Alias 1 (MPUATTR1), offset 0xDA8 .................................. 188
MPU Region Attribute and Size Alias 2 (MPUATTR2), offset 0xDB0 .................................. 188
MPU Region Attribute and Size Alias 3 (MPUATTR3), offset 0xDB8 .................................. 188
Coprocessor Access Control (CPAC), offset 0xD88 .......................................................... 191
Floating-Point Context Control (FPCC), offset 0xF34 ........................................................ 192
Floating-Point Context Address (FPCA), offset 0xF38 ...................................................... 194
Floating-Point Default Status Control (FPDSC), offset 0xF3C ........................................... 195
System Control ............................................................................................................................ 208
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Device Identification 0 (DID0), offset 0x000 ..................................................................... 233
Device Identification 1 (DID1), offset 0x004 ..................................................................... 235
Brown-Out Reset Control (PBORCTL), offset 0x030 ........................................................ 238
Raw Interrupt Status (RIS), offset 0x050 .......................................................................... 239
Interrupt Mask Control (IMC), offset 0x054 ...................................................................... 241
Masked Interrupt Status and Clear (MISC), offset 0x058 .................................................. 243
Reset Cause (RESC), offset 0x05C ................................................................................ 246
Run-Mode Clock Configuration (RCC), offset 0x060 ......................................................... 248
GPIO High-Performance Bus Control (GPIOHBCTL), offset 0x06C ................................... 252
Run-Mode Clock Configuration 2 (RCC2), offset 0x070 .................................................... 255
Main Oscillator Control (MOSCCTL), offset 0x07C ........................................................... 258
Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 ........................................ 259
System Properties (SYSPROP), offset 0x14C .................................................................. 261
Precision Internal Oscillator Calibration (PIOSCCAL), offset 0x150 ................................... 263
Precision Internal Oscillator Statistics (PIOSCSTAT), offset 0x154 .................................... 265
PLL Frequency 0 (PLLFREQ0), offset 0x160 ................................................................... 266
PLL Frequency 1 (PLLFREQ1), offset 0x164 ................................................................... 267
PLL Status (PLLSTAT), offset 0x168 ............................................................................... 268
Sleep Power Configuration (SLPPWRCFG), offset 0x188 ................................................. 269
Deep-Sleep Power Configuration (DSLPPWRCFG), offset 0x18C ..................................... 271
LDO Sleep Power Control (LDOSPCTL), offset 0x1B4 ..................................................... 273
LDO Sleep Power Calibration (LDOSPCAL), offset 0x1B8 ................................................ 275
20
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Tiva™ TM4C123BH6PGE Microcontroller
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
Register 29:
Register 30:
Register 31:
Register 32:
Register 33:
Register 34:
Register 35:
Register 36:
Register 37:
Register 38:
Register 39:
Register 40:
Register 41:
Register 42:
Register 43:
Register 44:
Register 45:
Register 46:
Register 47:
Register 48:
Register 49:
Register 50:
Register 51:
Register 52:
Register 53:
Register 54:
Register 55:
Register 56:
Register 57:
Register 58:
Register 59:
Register 60:
Register 61:
Register 62:
Register 63:
Register 64:
Register 65:
LDO Deep-Sleep Power Control (LDODPCTL), offset 0x1BC ........................................... 276
LDO Deep-Sleep Power Calibration (LDODPCAL), offset 0x1C0 ...................................... 278
Sleep / Deep-Sleep Power Mode Status (SDPMST), offset 0x1CC .................................... 279
Watchdog Timer Peripheral Present (PPWD), offset 0x300 ............................................... 282
16/32-Bit General-Purpose Timer Peripheral Present (PPTIMER), offset 0x304 ................. 283
General-Purpose Input/Output Peripheral Present (PPGPIO), offset 0x308 ........................ 285
Micro Direct Memory Access Peripheral Present (PPDMA), offset 0x30C .......................... 288
Hibernation Peripheral Present (PPHIB), offset 0x314 ...................................................... 289
Universal Asynchronous Receiver/Transmitter Peripheral Present (PPUART), offset
0x318 ........................................................................................................................... 290
Synchronous Serial Interface Peripheral Present (PPSSI), offset 0x31C ............................ 292
Inter-Integrated Circuit Peripheral Present (PPI2C), offset 0x320 ...................................... 294
Universal Serial Bus Peripheral Present (PPUSB), offset 0x328 ........................................ 296
Controller Area Network Peripheral Present (PPCAN), offset 0x334 .................................. 297
Analog-to-Digital Converter Peripheral Present (PPADC), offset 0x338 ............................. 298
Analog Comparator Peripheral Present (PPACMP), offset 0x33C ...................................... 299
Pulse Width Modulator Peripheral Present (PPPWM), offset 0x340 ................................... 300
Quadrature Encoder Interface Peripheral Present (PPQEI), offset 0x344 ........................... 301
EEPROM Peripheral Present (PPEEPROM), offset 0x358 ................................................ 302
32/64-Bit Wide General-Purpose Timer Peripheral Present (PPWTIMER), offset 0x35C ..... 303
Watchdog Timer Software Reset (SRWD), offset 0x500 ................................................... 305
16/32-Bit General-Purpose Timer Software Reset (SRTIMER), offset 0x504 ...................... 307
General-Purpose Input/Output Software Reset (SRGPIO), offset 0x508 ............................ 309
Micro Direct Memory Access Software Reset (SRDMA), offset 0x50C ............................... 312
Hibernation Software Reset (SRHIB), offset 0x514 ........................................................... 313
Universal Asynchronous Receiver/Transmitter Software Reset (SRUART), offset 0x518 .... 314
Synchronous Serial Interface Software Reset (SRSSI), offset 0x51C ................................ 316
Inter-Integrated Circuit Software Reset (SRI2C), offset 0x520 ........................................... 318
Controller Area Network Software Reset (SRCAN), offset 0x534 ....................................... 320
Analog-to-Digital Converter Software Reset (SRADC), offset 0x538 .................................. 322
Analog Comparator Software Reset (SRACMP), offset 0x53C .......................................... 324
Pulse Width Modulator Software Reset (SRPWM), offset 0x540 ....................................... 325
Quadrature Encoder Interface Software Reset (SRQEI), offset 0x544 ............................... 327
EEPROM Software Reset (SREEPROM), offset 0x558 .................................................... 329
32/64-Bit Wide General-Purpose Timer Software Reset (SRWTIMER), offset 0x55C .......... 330
Watchdog Timer Run Mode Clock Gating Control (RCGCWD), offset 0x600 ...................... 332
16/32-Bit General-Purpose Timer Run Mode Clock Gating Control (RCGCTIMER), offset
0x604 ........................................................................................................................... 333
General-Purpose Input/Output Run Mode Clock Gating Control (RCGCGPIO), offset
0x608 ........................................................................................................................... 335
Micro Direct Memory Access Run Mode Clock Gating Control (RCGCDMA), offset
0x60C ........................................................................................................................... 338
Hibernation Run Mode Clock Gating Control (RCGCHIB), offset 0x614 ............................. 339
Universal Asynchronous Receiver/Transmitter Run Mode Clock Gating Control (RCGCUART),
offset 0x618 .................................................................................................................. 340
Synchronous Serial Interface Run Mode Clock Gating Control (RCGCSSI), offset
0x61C ........................................................................................................................... 342
Inter-Integrated Circuit Run Mode Clock Gating Control (RCGCI2C), offset 0x620 ............. 344
Controller Area Network Run Mode Clock Gating Control (RCGCCAN), offset 0x634 ......... 346
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Register 66:
Register 67:
Register 68:
Register 69:
Register 70:
Register 71:
Register 72:
Register 73:
Register 74:
Register 75:
Register 76:
Register 77:
Register 78:
Register 79:
Register 80:
Register 81:
Register 82:
Register 83:
Register 84:
Register 85:
Register 86:
Register 87:
Register 88:
Register 89:
Register 90:
Register 91:
Register 92:
Register 93:
Register 94:
Register 95:
Register 96:
Analog-to-Digital Converter Run Mode Clock Gating Control (RCGCADC), offset 0x638 .... 347
Analog Comparator Run Mode Clock Gating Control (RCGCACMP), offset 0x63C ............. 348
Pulse Width Modulator Run Mode Clock Gating Control (RCGCPWM), offset 0x640 .......... 349
Quadrature Encoder Interface Run Mode Clock Gating Control (RCGCQEI), offset
0x644 ........................................................................................................................... 350
EEPROM Run Mode Clock Gating Control (RCGCEEPROM), offset 0x658 ....................... 351
32/64-Bit Wide General-Purpose Timer Run Mode Clock Gating Control (RCGCWTIMER),
offset 0x65C .................................................................................................................. 352
Watchdog Timer Sleep Mode Clock Gating Control (SCGCWD), offset 0x700 .................... 354
16/32-Bit General-Purpose Timer Sleep Mode Clock Gating Control (SCGCTIMER), offset
0x704 ........................................................................................................................... 355
General-Purpose Input/Output Sleep Mode Clock Gating Control (SCGCGPIO), offset
0x708 ........................................................................................................................... 357
Micro Direct Memory Access Sleep Mode Clock Gating Control (SCGCDMA), offset
0x70C ........................................................................................................................... 360
Hibernation Sleep Mode Clock Gating Control (SCGCHIB), offset 0x714 ........................... 361
Universal Asynchronous Receiver/Transmitter Sleep Mode Clock Gating Control
(SCGCUART), offset 0x718 ............................................................................................ 362
Synchronous Serial Interface Sleep Mode Clock Gating Control (SCGCSSI), offset
0x71C ........................................................................................................................... 364
Inter-Integrated Circuit Sleep Mode Clock Gating Control (SCGCI2C), offset 0x720 ........... 366
Controller Area Network Sleep Mode Clock Gating Control (SCGCCAN), offset 0x734 ....... 368
Analog-to-Digital Converter Sleep Mode Clock Gating Control (SCGCADC), offset
0x738 ........................................................................................................................... 369
Analog Comparator Sleep Mode Clock Gating Control (SCGCACMP), offset 0x73C .......... 370
Pulse Width Modulator Sleep Mode Clock Gating Control (SCGCPWM), offset 0x740 ........ 371
Quadrature Encoder Interface Sleep Mode Clock Gating Control (SCGCQEI), offset
0x744 ........................................................................................................................... 372
EEPROM Sleep Mode Clock Gating Control (SCGCEEPROM), offset 0x758 ..................... 373
32/64-Bit Wide General-Purpose Timer Sleep Mode Clock Gating Control (SCGCWTIMER),
offset 0x75C .................................................................................................................. 374
Watchdog Timer Deep-Sleep Mode Clock Gating Control (DCGCWD), offset 0x800 .......... 376
16/32-Bit General-Purpose Timer Deep-Sleep Mode Clock Gating Control (DCGCTIMER),
offset 0x804 .................................................................................................................. 377
General-Purpose Input/Output Deep-Sleep Mode Clock Gating Control (DCGCGPIO), offset
0x808 ........................................................................................................................... 379
Micro Direct Memory Access Deep-Sleep Mode Clock Gating Control (DCGCDMA), offset
0x80C ........................................................................................................................... 382
Hibernation Deep-Sleep Mode Clock Gating Control (DCGCHIB), offset 0x814 .................. 383
Universal Asynchronous Receiver/Transmitter Deep-Sleep Mode Clock Gating Control
(DCGCUART), offset 0x818 ............................................................................................ 384
Synchronous Serial Interface Deep-Sleep Mode Clock Gating Control (DCGCSSI), offset
0x81C ........................................................................................................................... 386
Inter-Integrated Circuit Deep-Sleep Mode Clock Gating Control (DCGCI2C), offset
0x820 ........................................................................................................................... 388
Controller Area Network Deep-Sleep Mode Clock Gating Control (DCGCCAN), offset
0x834 ........................................................................................................................... 390
Analog-to-Digital Converter Deep-Sleep Mode Clock Gating Control (DCGCADC), offset
0x838 ........................................................................................................................... 391
22
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Tiva™ TM4C123BH6PGE Microcontroller
Register 97:
Register 98:
Register 99:
Register 100:
Register 101:
Register 102:
Register 103:
Register 104:
Register 105:
Register 106:
Register 107:
Register 108:
Register 109:
Register 110:
Register 111:
Register 112:
Register 113:
Register 114:
Register 115:
Register 116:
Register 117:
Register 118:
Register 119:
Register 120:
Register 121:
Register 122:
Register 123:
Register 124:
Register 125:
Register 126:
Register 127:
Register 128:
Register 129:
Register 130:
Register 131:
Register 132:
Register 133:
Register 134:
Register 135:
Register 136:
Register 137:
Register 138:
Register 139:
Analog Comparator Deep-Sleep Mode Clock Gating Control (DCGCACMP), offset
0x83C ........................................................................................................................... 392
Pulse Width Modulator Deep-Sleep Mode Clock Gating Control (DCGCPWM), offset
0x840 ........................................................................................................................... 393
Quadrature Encoder Interface Deep-Sleep Mode Clock Gating Control (DCGCQEI), offset
0x844 ........................................................................................................................... 394
EEPROM Deep-Sleep Mode Clock Gating Control (DCGCEEPROM), offset 0x858 ........... 395
32/64-Bit Wide General-Purpose Timer Deep-Sleep Mode Clock Gating Control
(DCGCWTIMER), offset 0x85C ...................................................................................... 396
Watchdog Timer Peripheral Ready (PRWD), offset 0xA00 ................................................ 398
16/32-Bit General-Purpose Timer Peripheral Ready (PRTIMER), offset 0xA04 ................... 399
General-Purpose Input/Output Peripheral Ready (PRGPIO), offset 0xA08 ......................... 401
Micro Direct Memory Access Peripheral Ready (PRDMA), offset 0xA0C ........................... 404
Hibernation Peripheral Ready (PRHIB), offset 0xA14 ....................................................... 405
Universal Asynchronous Receiver/Transmitter Peripheral Ready (PRUART), offset
0xA18 ........................................................................................................................... 406
Synchronous Serial Interface Peripheral Ready (PRSSI), offset 0xA1C ............................. 408
Inter-Integrated Circuit Peripheral Ready (PRI2C), offset 0xA20 ....................................... 410
Controller Area Network Peripheral Ready (PRCAN), offset 0xA34 ................................... 412
Analog-to-Digital Converter Peripheral Ready (PRADC), offset 0xA38 ............................... 413
Analog Comparator Peripheral Ready (PRACMP), offset 0xA3C ....................................... 414
Pulse Width Modulator Peripheral Ready (PRPWM), offset 0xA40 .................................... 415
Quadrature Encoder Interface Peripheral Ready (PRQEI), offset 0xA44 ............................ 416
EEPROM Peripheral Ready (PREEPROM), offset 0xA58 ................................................. 417
32/64-Bit Wide General-Purpose Timer Peripheral Ready (PRWTIMER), offset 0xA5C ...... 418
Device Capabilities 0 (DC0), offset 0x008 ........................................................................ 420
Device Capabilities 1 (DC1), offset 0x010 ........................................................................ 422
Device Capabilities 2 (DC2), offset 0x014 ........................................................................ 425
Device Capabilities 3 (DC3), offset 0x018 ........................................................................ 428
Device Capabilities 4 (DC4), offset 0x01C ....................................................................... 432
Device Capabilities 5 (DC5), offset 0x020 ........................................................................ 435
Device Capabilities 6 (DC6), offset 0x024 ........................................................................ 437
Device Capabilities 7 (DC7), offset 0x028 ........................................................................ 438
Device Capabilities 8 (DC8), offset 0x02C ....................................................................... 441
Software Reset Control 0 (SRCR0), offset 0x040 ............................................................. 444
Software Reset Control 1 (SRCR1), offset 0x044 ............................................................. 446
Software Reset Control 2 (SRCR2), offset 0x048 ............................................................. 449
Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 ................................... 451
Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 ................................... 455
Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 ................................... 459
Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 ................................. 462
Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 ................................. 465
Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 ................................. 469
Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 ....................... 471
Deep-Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 ....................... 474
Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 ....................... 478
Device Capabilities 9 (DC9), offset 0x190 ........................................................................ 480
Non-Volatile Memory Information (NVMSTAT), offset 0x1A0 ............................................. 482
June 12, 2014
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System Exception Module .......................................................................................................... 483
Register 1:
Register 2:
Register 3:
Register 4:
System Exception Raw Interrupt Status (SYSEXCRIS), offset 0x000 ................................
System Exception Interrupt Mask (SYSEXCIM), offset 0x004 ...........................................
System Exception Masked Interrupt Status (SYSEXCMIS), offset 0x008 ...........................
System Exception Interrupt Clear (SYSEXCIC), offset 0x00C ...........................................
484
486
488
490
Hibernation Module ..................................................................................................................... 491
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Hibernation RTC Counter (HIBRTCC), offset 0x000 .........................................................
Hibernation RTC Match 0 (HIBRTCM0), offset 0x004 .......................................................
Hibernation RTC Load (HIBRTCLD), offset 0x00C ...........................................................
Hibernation Control (HIBCTL), offset 0x010 .....................................................................
Hibernation Interrupt Mask (HIBIM), offset 0x014 .............................................................
Hibernation Raw Interrupt Status (HIBRIS), offset 0x018 ..................................................
Hibernation Masked Interrupt Status (HIBMIS), offset 0x01C ............................................
Hibernation Interrupt Clear (HIBIC), offset 0x020 .............................................................
Hibernation RTC Trim (HIBRTCT), offset 0x024 ...............................................................
Hibernation RTC Sub Seconds (HIBRTCSS), offset 0x028 ...............................................
Hibernation Data (HIBDATA), offset 0x030-0x06F ............................................................
505
506
507
508
512
514
516
518
519
520
521
Internal Memory ........................................................................................................................... 522
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
Register 29:
Register 30:
Flash Memory Address (FMA), offset 0x000 .................................................................... 540
Flash Memory Data (FMD), offset 0x004 ......................................................................... 541
Flash Memory Control (FMC), offset 0x008 ..................................................................... 542
Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ............................................ 544
Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................ 547
Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 ..................... 549
Flash Memory Control 2 (FMC2), offset 0x020 ................................................................. 552
Flash Write Buffer Valid (FWBVAL), offset 0x030 ............................................................. 553
Flash Write Buffer n (FWBn), offset 0x100 - 0x17C .......................................................... 554
Flash Size (FSIZE), offset 0xFC0 .................................................................................... 555
SRAM Size (SSIZE), offset 0xFC4 .................................................................................. 556
ROM Software Map (ROMSWMAP), offset 0xFCC ........................................................... 557
EEPROM Size Information (EESIZE), offset 0x000 .......................................................... 558
EEPROM Current Block (EEBLOCK), offset 0x004 .......................................................... 559
EEPROM Current Offset (EEOFFSET), offset 0x008 ........................................................ 560
EEPROM Read-Write (EERDWR), offset 0x010 .............................................................. 561
EEPROM Read-Write with Increment (EERDWRINC), offset 0x014 .................................. 562
EEPROM Done Status (EEDONE), offset 0x018 .............................................................. 563
EEPROM Support Control and Status (EESUPP), offset 0x01C ........................................ 565
EEPROM Unlock (EEUNLOCK), offset 0x020 .................................................................. 567
EEPROM Protection (EEPROT), offset 0x030 ................................................................. 568
EEPROM Password (EEPASS0), offset 0x034 ................................................................. 570
EEPROM Password (EEPASS1), offset 0x038 ................................................................. 570
EEPROM Password (EEPASS2), offset 0x03C ................................................................ 570
EEPROM Interrupt (EEINT), offset 0x040 ........................................................................ 571
EEPROM Block Hide (EEHIDE), offset 0x050 .................................................................. 572
EEPROM Debug Mass Erase (EEDBGME), offset 0x080 ................................................. 573
EEPROM Peripheral Properties (EEPROMPP), offset 0xFC0 ........................................... 574
ROM Control (RMCTL), offset 0x0F0 .............................................................................. 575
Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 ................... 576
24
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Register 31:
Register 32:
Register 33:
Register 34:
Register 35:
Register 36:
Register 37:
Register 38:
Register 39:
Register 40:
Register 41:
Register 42:
Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 .................................... 576
Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208 .................................... 576
Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C ................................... 576
Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400 ............... 577
Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404 ............................... 577
Flash Memory Protection Program Enable 2 (FMPPE2), offset 0x408 ............................... 577
Flash Memory Protection Program Enable 3 (FMPPE3), offset 0x40C ............................... 577
Boot Configuration (BOOTCFG), offset 0x1D0 ................................................................. 579
User Register 0 (USER_REG0), offset 0x1E0 .................................................................. 582
User Register 1 (USER_REG1), offset 0x1E4 .................................................................. 582
User Register 2 (USER_REG2), offset 0x1E8 .................................................................. 582
User Register 3 (USER_REG3), offset 0x1EC ................................................................. 582
Micro Direct Memory Access (μDMA) ........................................................................................ 583
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
Register 29:
Register 30:
Register 31:
Register 32:
Register 33:
Register 34:
Register 35:
DMA Channel Source Address End Pointer (DMASRCENDP), offset 0x000 ...................... 607
DMA Channel Destination Address End Pointer (DMADSTENDP), offset 0x004 ................ 608
DMA Channel Control Word (DMACHCTL), offset 0x008 .................................................. 609
DMA Status (DMASTAT), offset 0x000 ............................................................................ 614
DMA Configuration (DMACFG), offset 0x004 ................................................................... 616
DMA Channel Control Base Pointer (DMACTLBASE), offset 0x008 .................................. 617
DMA Alternate Channel Control Base Pointer (DMAALTBASE), offset 0x00C .................... 618
DMA Channel Wait-on-Request Status (DMAWAITSTAT), offset 0x010 ............................. 619
DMA Channel Software Request (DMASWREQ), offset 0x014 ......................................... 620
DMA Channel Useburst Set (DMAUSEBURSTSET), offset 0x018 .................................... 621
DMA Channel Useburst Clear (DMAUSEBURSTCLR), offset 0x01C ................................. 622
DMA Channel Request Mask Set (DMAREQMASKSET), offset 0x020 .............................. 623
DMA Channel Request Mask Clear (DMAREQMASKCLR), offset 0x024 ........................... 624
DMA Channel Enable Set (DMAENASET), offset 0x028 ................................................... 625
DMA Channel Enable Clear (DMAENACLR), offset 0x02C ............................................... 626
DMA Channel Primary Alternate Set (DMAALTSET), offset 0x030 .................................... 627
DMA Channel Primary Alternate Clear (DMAALTCLR), offset 0x034 ................................. 628
DMA Channel Priority Set (DMAPRIOSET), offset 0x038 ................................................. 629
DMA Channel Priority Clear (DMAPRIOCLR), offset 0x03C .............................................. 630
DMA Bus Error Clear (DMAERRCLR), offset 0x04C ........................................................ 631
DMA Channel Assignment (DMACHASGN), offset 0x500 ................................................. 632
DMA Channel Interrupt Status (DMACHIS), offset 0x504 .................................................. 633
DMA Channel Map Select 0 (DMACHMAP0), offset 0x510 ............................................... 634
DMA Channel Map Select 1 (DMACHMAP1), offset 0x514 ............................................... 635
DMA Channel Map Select 2 (DMACHMAP2), offset 0x518 ............................................... 636
DMA Channel Map Select 3 (DMACHMAP3), offset 0x51C .............................................. 637
DMA Peripheral Identification 0 (DMAPeriphID0), offset 0xFE0 ......................................... 638
DMA Peripheral Identification 1 (DMAPeriphID1), offset 0xFE4 ......................................... 639
DMA Peripheral Identification 2 (DMAPeriphID2), offset 0xFE8 ......................................... 640
DMA Peripheral Identification 3 (DMAPeriphID3), offset 0xFEC ........................................ 641
DMA Peripheral Identification 4 (DMAPeriphID4), offset 0xFD0 ......................................... 642
DMA PrimeCell Identification 0 (DMAPCellID0), offset 0xFF0 ........................................... 643
DMA PrimeCell Identification 1 (DMAPCellID1), offset 0xFF4 ........................................... 644
DMA PrimeCell Identification 2 (DMAPCellID2), offset 0xFF8 ........................................... 645
DMA PrimeCell Identification 3 (DMAPCellID3), offset 0xFFC ........................................... 646
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General-Purpose Input/Outputs (GPIOs) ................................................................................... 647
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
Register 29:
Register 30:
Register 31:
Register 32:
Register 33:
Register 34:
Register 35:
Register 36:
Register 37:
GPIO Data (GPIODATA), offset 0x000 ............................................................................ 662
GPIO Direction (GPIODIR), offset 0x400 ......................................................................... 664
GPIO Interrupt Sense (GPIOIS), offset 0x404 .................................................................. 665
GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 ........................................................ 667
GPIO Interrupt Event (GPIOIEV), offset 0x40C ................................................................ 669
GPIO Interrupt Mask (GPIOIM), offset 0x410 ................................................................... 670
GPIO Raw Interrupt Status (GPIORIS), offset 0x414 ........................................................ 671
GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 ................................................... 673
GPIO Interrupt Clear (GPIOICR), offset 0x41C ................................................................ 675
GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 ............................................ 676
GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 ........................................................ 678
GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 ........................................................ 679
GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 ........................................................ 680
GPIO Open Drain Select (GPIOODR), offset 0x50C ......................................................... 682
GPIO Pull-Up Select (GPIOPUR), offset 0x510 ................................................................ 683
GPIO Pull-Down Select (GPIOPDR), offset 0x514 ........................................................... 685
GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 ................................................ 687
GPIO Digital Enable (GPIODEN), offset 0x51C ................................................................ 688
GPIO Lock (GPIOLOCK), offset 0x520 ............................................................................ 690
GPIO Commit (GPIOCR), offset 0x524 ............................................................................ 691
GPIO Analog Mode Select (GPIOAMSEL), offset 0x528 ................................................... 693
GPIO Port Control (GPIOPCTL), offset 0x52C ................................................................. 695
GPIO ADC Control (GPIOADCCTL), offset 0x530 ............................................................ 697
GPIO DMA Control (GPIODMACTL), offset 0x534 ........................................................... 698
GPIO Select Interrupt (GPIOSI), offset 0x538 .................................................................. 699
GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 ....................................... 700
GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 ....................................... 701
GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 ....................................... 702
GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC ...................................... 703
GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 ....................................... 704
GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4 ....................................... 705
GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 ....................................... 706
GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC ...................................... 707
GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 .......................................... 708
GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 .......................................... 709
GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 .......................................... 710
GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC ......................................... 711
General-Purpose Timers ............................................................................................................. 712
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
GPTM Configuration (GPTMCFG), offset 0x000 ..............................................................
GPTM Timer A Mode (GPTMTAMR), offset 0x004 ...........................................................
GPTM Timer B Mode (GPTMTBMR), offset 0x008 ...........................................................
GPTM Control (GPTMCTL), offset 0x00C ........................................................................
GPTM Synchronize (GPTMSYNC), offset 0x010 ..............................................................
GPTM Interrupt Mask (GPTMIMR), offset 0x018 ..............................................................
GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C .....................................................
GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 ................................................
GPTM Interrupt Clear (GPTMICR), offset 0x024 ..............................................................
26
736
738
742
746
750
754
757
760
763
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Tiva™ TM4C123BH6PGE Microcontroller
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
GPTM Timer A Interval Load (GPTMTAILR), offset 0x028 ................................................ 765
GPTM Timer B Interval Load (GPTMTBILR), offset 0x02C ................................................ 766
GPTM Timer A Match (GPTMTAMATCHR), offset 0x030 .................................................. 767
GPTM Timer B Match (GPTMTBMATCHR), offset 0x034 ................................................. 768
GPTM Timer A Prescale (GPTMTAPR), offset 0x038 ....................................................... 769
GPTM Timer B Prescale (GPTMTBPR), offset 0x03C ...................................................... 770
GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 ........................................... 771
GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ........................................... 772
GPTM Timer A (GPTMTAR), offset 0x048 ....................................................................... 773
GPTM Timer B (GPTMTBR), offset 0x04C ....................................................................... 774
GPTM Timer A Value (GPTMTAV), offset 0x050 ............................................................... 775
GPTM Timer B Value (GPTMTBV), offset 0x054 .............................................................. 776
GPTM RTC Predivide (GPTMRTCPD), offset 0x058 ........................................................ 777
GPTM Timer A Prescale Snapshot (GPTMTAPS), offset 0x05C ........................................ 778
GPTM Timer B Prescale Snapshot (GPTMTBPS), offset 0x060 ........................................ 779
GPTM Timer A Prescale Value (GPTMTAPV), offset 0x064 .............................................. 780
GPTM Timer B Prescale Value (GPTMTBPV), offset 0x068 .............................................. 781
GPTM Peripheral Properties (GPTMPP), offset 0xFC0 ..................................................... 782
Watchdog Timers ......................................................................................................................... 783
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Watchdog Load (WDTLOAD), offset 0x000 ...................................................................... 787
Watchdog Value (WDTVALUE), offset 0x004 ................................................................... 788
Watchdog Control (WDTCTL), offset 0x008 ..................................................................... 789
Watchdog Interrupt Clear (WDTICR), offset 0x00C .......................................................... 791
Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 .................................................. 792
Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 ............................................. 793
Watchdog Test (WDTTEST), offset 0x418 ....................................................................... 794
Watchdog Lock (WDTLOCK), offset 0xC00 ..................................................................... 795
Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 ................................. 796
Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 ................................. 797
Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 ................................. 798
Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC ................................ 799
Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ................................. 800
Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ................................. 801
Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ................................. 802
Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC ................................. 803
Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 .................................... 804
Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 .................................... 805
Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 .................................... 806
Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC .................................. 807
Analog-to-Digital Converter (ADC) ............................................................................................. 808
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
ADC Active Sample Sequencer (ADCACTSS), offset 0x000 ............................................. 831
ADC Raw Interrupt Status (ADCRIS), offset 0x004 ........................................................... 833
ADC Interrupt Mask (ADCIM), offset 0x008 ..................................................................... 835
ADC Interrupt Status and Clear (ADCISC), offset 0x00C .................................................. 838
ADC Overflow Status (ADCOSTAT), offset 0x010 ............................................................ 841
ADC Event Multiplexer Select (ADCEMUX), offset 0x014 ................................................. 843
ADC Underflow Status (ADCUSTAT), offset 0x018 ........................................................... 848
ADC Trigger Source Select (ADCTSSEL), offset 0x01C ................................................... 849
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Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
Register 29:
Register 30:
Register 31:
Register 32:
Register 33:
Register 34:
Register 35:
Register 36:
Register 37:
Register 38:
Register 39:
Register 40:
Register 41:
Register 42:
Register 43:
Register 44:
Register 45:
Register 46:
Register 47:
Register 48:
Register 49:
Register 50:
Register 51:
Register 52:
Register 53:
ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020 ............................................. 851
ADC Sample Phase Control (ADCSPC), offset 0x024 ...................................................... 853
ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028 ................................. 855
ADC Sample Averaging Control (ADCSAC), offset 0x030 ................................................. 857
ADC Digital Comparator Interrupt Status and Clear (ADCDCISC), offset 0x034 ................. 858
ADC Control (ADCCTL), offset 0x038 ............................................................................. 860
ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0), offset 0x040 ............... 861
ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044 ........................................ 863
ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048 ................................ 870
ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068 ................................ 870
ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088 ................................ 870
ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset 0x0A8 ............................... 870
ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset 0x04C ............................. 871
ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset 0x06C ............................. 871
ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset 0x08C ............................ 871
ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset 0x0AC ............................ 871
ADC Sample Sequence 0 Operation (ADCSSOP0), offset 0x050 ...................................... 873
ADC Sample Sequence 0 Digital Comparator Select (ADCSSDC0), offset 0x054 .............. 875
ADC Sample Sequence Extended Input Multiplexer Select 0 (ADCSSEMUX0), offset
0x058 ........................................................................................................................... 877
ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1), offset 0x060 ............... 879
ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2), offset 0x080 ............... 879
ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064 ........................................ 880
ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084 ........................................ 880
ADC Sample Sequence 1 Operation (ADCSSOP1), offset 0x070 ...................................... 884
ADC Sample Sequence 2 Operation (ADCSSOP2), offset 0x090 ..................................... 884
ADC Sample Sequence 1 Digital Comparator Select (ADCSSDC1), offset 0x074 .............. 885
ADC Sample Sequence 2 Digital Comparator Select (ADCSSDC2), offset 0x094 .............. 885
ADC Sample Sequence Extended Input Multiplexer Select 1 (ADCSSEMUX1), offset
0x078 ........................................................................................................................... 887
ADC Sample Sequence Extended Input Multiplexer Select 2 (ADCSSEMUX2), offset 0x098
..................................................................................................................................... 887
ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3), offset 0x0A0 ............... 889
ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4 ........................................ 890
ADC Sample Sequence 3 Operation (ADCSSOP3), offset 0x0B0 ..................................... 892
ADC Sample Sequence 3 Digital Comparator Select (ADCSSDC3), offset 0x0B4 .............. 893
ADC Sample Sequence Extended Input Multiplexer Select 3 (ADCSSEMUX3), offset
0x0B8 ........................................................................................................................... 894
ADC Digital Comparator Reset Initial Conditions (ADCDCRIC), offset 0xD00 ..................... 895
ADC Digital Comparator Control 0 (ADCDCCTL0), offset 0xE00 ....................................... 900
ADC Digital Comparator Control 1 (ADCDCCTL1), offset 0xE04 ....................................... 900
ADC Digital Comparator Control 2 (ADCDCCTL2), offset 0xE08 ....................................... 900
ADC Digital Comparator Control 3 (ADCDCCTL3), offset 0xE0C ...................................... 900
ADC Digital Comparator Control 4 (ADCDCCTL4), offset 0xE10 ....................................... 900
ADC Digital Comparator Control 5 (ADCDCCTL5), offset 0xE14 ....................................... 900
ADC Digital Comparator Control 6 (ADCDCCTL6), offset 0xE18 ....................................... 900
ADC Digital Comparator Control 7 (ADCDCCTL7), offset 0xE1C ...................................... 900
ADC Digital Comparator Range 0 (ADCDCCMP0), offset 0xE40 ....................................... 903
ADC Digital Comparator Range 1 (ADCDCCMP1), offset 0xE44 ....................................... 903
28
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Tiva™ TM4C123BH6PGE Microcontroller
Register 54:
Register 55:
Register 56:
Register 57:
Register 58:
Register 59:
Register 60:
Register 61:
Register 62:
ADC Digital Comparator Range 2 (ADCDCCMP2), offset 0xE48 ....................................... 903
ADC Digital Comparator Range 3 (ADCDCCMP3), offset 0xE4C ...................................... 903
ADC Digital Comparator Range 4 (ADCDCCMP4), offset 0xE50 ....................................... 903
ADC Digital Comparator Range 5 (ADCDCCMP5), offset 0xE54 ....................................... 903
ADC Digital Comparator Range 6 (ADCDCCMP6), offset 0xE58 ....................................... 903
ADC Digital Comparator Range 7 (ADCDCCMP7), offset 0xE5C ...................................... 903
ADC Peripheral Properties (ADCPP), offset 0xFC0 .......................................................... 904
ADC Peripheral Configuration (ADCPC), offset 0xFC4 ..................................................... 906
ADC Clock Configuration (ADCCC), offset 0xFC8 ............................................................ 907
Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 908
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
Register 29:
Register 30:
UART Data (UARTDR), offset 0x000 ............................................................................... 922
UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... 924
UART Flag (UARTFR), offset 0x018 ................................................................................ 927
UART IrDA Low-Power Register (UARTILPR), offset 0x020 ............................................. 930
UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ 931
UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... 932
UART Line Control (UARTLCRH), offset 0x02C ............................................................... 933
UART Control (UARTCTL), offset 0x030 ......................................................................... 935
UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 939
UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 941
UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 944
UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 947
UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 950
UART DMA Control (UARTDMACTL), offset 0x048 .......................................................... 952
UART 9-Bit Self Address (UART9BITADDR), offset 0x0A4 ............................................... 953
UART 9-Bit Self Address Mask (UART9BITAMASK), offset 0x0A8 .................................... 954
UART Peripheral Properties (UARTPP), offset 0xFC0 ...................................................... 955
UART Clock Configuration (UARTCC), offset 0xFC8 ........................................................ 956
UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 957
UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 958
UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 959
UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 960
UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 961
UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 962
UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... 963
UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 964
UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 965
UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 966
UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 967
UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 968
Synchronous Serial Interface (SSI) ............................................................................................ 969
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
SSI Control 0 (SSICR0), offset 0x000 ..............................................................................
SSI Control 1 (SSICR1), offset 0x004 ..............................................................................
SSI Data (SSIDR), offset 0x008 ......................................................................................
SSI Status (SSISR), offset 0x00C ...................................................................................
SSI Clock Prescale (SSICPSR), offset 0x010 ..................................................................
SSI Interrupt Mask (SSIIM), offset 0x014 .........................................................................
SSI Raw Interrupt Status (SSIRIS), offset 0x018 ..............................................................
June 12, 2014
986
988
990
991
993
994
995
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Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 997
SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 999
SSI DMA Control (SSIDMACTL), offset 0x024 ............................................................... 1000
SSI Clock Configuration (SSICC), offset 0xFC8 ............................................................. 1001
SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ........................................... 1002
SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ........................................... 1003
SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ........................................... 1004
SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC .......................................... 1005
SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ........................................... 1006
SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ........................................... 1007
SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ........................................... 1008
SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC .......................................... 1009
SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 .............................................. 1010
SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 .............................................. 1011
SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 .............................................. 1012
SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................. 1013
Inter-Integrated Circuit (I2C) Interface ...................................................................................... 1014
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
I2C Master Slave Address (I2CMSA), offset 0x000 ......................................................... 1036
I2C Master Control/Status (I2CMCS), offset 0x004 ......................................................... 1037
I2C Master Data (I2CMDR), offset 0x008 ....................................................................... 1042
I2C Master Timer Period (I2CMTPR), offset 0x00C ......................................................... 1043
I2C Master Interrupt Mask (I2CMIMR), offset 0x010 ....................................................... 1044
I2C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ............................................... 1045
I2C Master Masked Interrupt Status (I2CMMIS), offset 0x018 .......................................... 1046
I2C Master Interrupt Clear (I2CMICR), offset 0x01C ....................................................... 1047
I2C Master Configuration (I2CMCR), offset 0x020 .......................................................... 1048
I2C Master Clock Low Timeout Count (I2CMCLKOCNT), offset 0x024 ............................. 1050
I2C Master Bus Monitor (I2CMBMON), offset 0x02C ....................................................... 1051
I2C Master Configuration 2 (I2CMCR2), offset 0x038 ...................................................... 1052
I2C Slave Own Address (I2CSOAR), offset 0x800 .......................................................... 1053
I2C Slave Control/Status (I2CSCSR), offset 0x804 ......................................................... 1054
I2C Slave Data (I2CSDR), offset 0x808 ......................................................................... 1056
I2C Slave Interrupt Mask (I2CSIMR), offset 0x80C ......................................................... 1057
I2C Slave Raw Interrupt Status (I2CSRIS), offset 0x810 ................................................. 1058
I2C Slave Masked Interrupt Status (I2CSMIS), offset 0x814 ............................................ 1059
I2C Slave Interrupt Clear (I2CSICR), offset 0x818 .......................................................... 1060
I2C Slave Own Address 2 (I2CSOAR2), offset 0x81C ..................................................... 1061
I2C Slave ACK Control (I2CSACKCTL), offset 0x820 ...................................................... 1062
I2C Peripheral Properties (I2CPP), offset 0xFC0 ............................................................ 1063
I2C Peripheral Configuration (I2CPC), offset 0xFC4 ....................................................... 1064
Controller Area Network (CAN) Module ................................................................................... 1065
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
CAN Control (CANCTL), offset 0x000 ............................................................................ 1087
CAN Status (CANSTS), offset 0x004 ............................................................................. 1089
CAN Error Counter (CANERR), offset 0x008 ................................................................. 1092
CAN Bit Timing (CANBIT), offset 0x00C ........................................................................ 1093
CAN Interrupt (CANINT), offset 0x010 ........................................................................... 1094
CAN Test (CANTST), offset 0x014 ................................................................................ 1095
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Tiva™ TM4C123BH6PGE Microcontroller
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
Register 29:
Register 30:
Register 31:
Register 32:
Register 33:
Register 34:
Register 35:
Register 36:
Register 37:
CAN Baud Rate Prescaler Extension (CANBRPE), offset 0x018 ..................................... 1097
CAN IF1 Command Request (CANIF1CRQ), offset 0x020 .............................................. 1098
CAN IF2 Command Request (CANIF2CRQ), offset 0x080 .............................................. 1098
CAN IF1 Command Mask (CANIF1CMSK), offset 0x024 ................................................ 1099
CAN IF2 Command Mask (CANIF2CMSK), offset 0x084 ................................................ 1099
CAN IF1 Mask 1 (CANIF1MSK1), offset 0x028 .............................................................. 1102
CAN IF2 Mask 1 (CANIF2MSK1), offset 0x088 .............................................................. 1102
CAN IF1 Mask 2 (CANIF1MSK2), offset 0x02C .............................................................. 1103
CAN IF2 Mask 2 (CANIF2MSK2), offset 0x08C .............................................................. 1103
CAN IF1 Arbitration 1 (CANIF1ARB1), offset 0x030 ....................................................... 1105
CAN IF2 Arbitration 1 (CANIF2ARB1), offset 0x090 ....................................................... 1105
CAN IF1 Arbitration 2 (CANIF1ARB2), offset 0x034 ....................................................... 1106
CAN IF2 Arbitration 2 (CANIF2ARB2), offset 0x094 ....................................................... 1106
CAN IF1 Message Control (CANIF1MCTL), offset 0x038 ................................................ 1108
CAN IF2 Message Control (CANIF2MCTL), offset 0x098 ................................................ 1108
CAN IF1 Data A1 (CANIF1DA1), offset 0x03C ............................................................... 1111
CAN IF1 Data A2 (CANIF1DA2), offset 0x040 ................................................................ 1111
CAN IF1 Data B1 (CANIF1DB1), offset 0x044 ................................................................ 1111
CAN IF1 Data B2 (CANIF1DB2), offset 0x048 ................................................................ 1111
CAN IF2 Data A1 (CANIF2DA1), offset 0x09C ............................................................... 1111
CAN IF2 Data A2 (CANIF2DA2), offset 0x0A0 ............................................................... 1111
CAN IF2 Data B1 (CANIF2DB1), offset 0x0A4 ............................................................... 1111
CAN IF2 Data B2 (CANIF2DB2), offset 0x0A8 ............................................................... 1111
CAN Transmission Request 1 (CANTXRQ1), offset 0x100 .............................................. 1112
CAN Transmission Request 2 (CANTXRQ2), offset 0x104 .............................................. 1112
CAN New Data 1 (CANNWDA1), offset 0x120 ............................................................... 1113
CAN New Data 2 (CANNWDA2), offset 0x124 ............................................................... 1113
CAN Message 1 Interrupt Pending (CANMSG1INT), offset 0x140 ................................... 1114
CAN Message 2 Interrupt Pending (CANMSG2INT), offset 0x144 ................................... 1114
CAN Message 1 Valid (CANMSG1VAL), offset 0x160 ..................................................... 1115
CAN Message 2 Valid (CANMSG2VAL), offset 0x164 ..................................................... 1115
Analog Comparators ................................................................................................................. 1116
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Analog Comparator Masked Interrupt Status (ACMIS), offset 0x000 ................................ 1123
Analog Comparator Raw Interrupt Status (ACRIS), offset 0x004 ..................................... 1124
Analog Comparator Interrupt Enable (ACINTEN), offset 0x008 ....................................... 1125
Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x010 ..................... 1126
Analog Comparator Status 0 (ACSTAT0), offset 0x020 ................................................... 1127
Analog Comparator Status 1 (ACSTAT1), offset 0x040 ................................................... 1127
Analog Comparator Status 2 (ACSTAT2), offset 0x060 ................................................... 1127
Analog Comparator Control 0 (ACCTL0), offset 0x024 ................................................... 1128
Analog Comparator Control 1 (ACCTL1), offset 0x044 ................................................... 1128
Analog Comparator Control 2 (ACCTL2), offset 0x064 ................................................... 1128
Analog Comparator Peripheral Properties (ACMPPP), offset 0xFC0 ................................ 1130
Pulse Width Modulator (PWM) .................................................................................................. 1132
Register 1:
Register 2:
Register 3:
Register 4:
PWM Master Control (PWMCTL), offset 0x000 ..............................................................
PWM Time Base Sync (PWMSYNC), offset 0x004 .........................................................
PWM Output Enable (PWMENABLE), offset 0x008 ........................................................
PWM Output Inversion (PWMINVERT), offset 0x00C .....................................................
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Table of Contents
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
Register 29:
Register 30:
Register 31:
Register 32:
Register 33:
Register 34:
Register 35:
Register 36:
Register 37:
Register 38:
Register 39:
Register 40:
Register 41:
Register 42:
Register 43:
Register 44:
Register 45:
Register 46:
Register 47:
Register 48:
Register 49:
Register 50:
Register 51:
Register 52:
PWM Output Fault (PWMFAULT), offset 0x010 .............................................................. 1154
PWM Interrupt Enable (PWMINTEN), offset 0x014 ......................................................... 1156
PWM Raw Interrupt Status (PWMRIS), offset 0x018 ...................................................... 1158
PWM Interrupt Status and Clear (PWMISC), offset 0x01C .............................................. 1161
PWM Status (PWMSTATUS), offset 0x020 .................................................................... 1164
PWM Fault Condition Value (PWMFAULTVAL), offset 0x024 ........................................... 1166
PWM Enable Update (PWMENUPD), offset 0x028 ......................................................... 1168
PWM0 Control (PWM0CTL), offset 0x040 ...................................................................... 1172
PWM1 Control (PWM1CTL), offset 0x080 ...................................................................... 1172
PWM2 Control (PWM2CTL), offset 0x0C0 ..................................................................... 1172
PWM3 Control (PWM3CTL), offset 0x100 ...................................................................... 1172
PWM0 Interrupt and Trigger Enable (PWM0INTEN), offset 0x044 ................................... 1177
PWM1 Interrupt and Trigger Enable (PWM1INTEN), offset 0x084 ................................... 1177
PWM2 Interrupt and Trigger Enable (PWM2INTEN), offset 0x0C4 ................................... 1177
PWM3 Interrupt and Trigger Enable (PWM3INTEN), offset 0x104 ................................... 1177
PWM0 Raw Interrupt Status (PWM0RIS), offset 0x048 ................................................... 1180
PWM1 Raw Interrupt Status (PWM1RIS), offset 0x088 ................................................... 1180
PWM2 Raw Interrupt Status (PWM2RIS), offset 0x0C8 .................................................. 1180
PWM3 Raw Interrupt Status (PWM3RIS), offset 0x108 ................................................... 1180
PWM0 Interrupt Status and Clear (PWM0ISC), offset 0x04C .......................................... 1182
PWM1 Interrupt Status and Clear (PWM1ISC), offset 0x08C .......................................... 1182
PWM2 Interrupt Status and Clear (PWM2ISC), offset 0x0CC .......................................... 1182
PWM3 Interrupt Status and Clear (PWM3ISC), offset 0x10C .......................................... 1182
PWM0 Load (PWM0LOAD), offset 0x050 ...................................................................... 1184
PWM1 Load (PWM1LOAD), offset 0x090 ...................................................................... 1184
PWM2 Load (PWM2LOAD), offset 0x0D0 ...................................................................... 1184
PWM3 Load (PWM3LOAD), offset 0x110 ...................................................................... 1184
PWM0 Counter (PWM0COUNT), offset 0x054 ............................................................... 1185
PWM1 Counter (PWM1COUNT), offset 0x094 ............................................................... 1185
PWM2 Counter (PWM2COUNT), offset 0x0D4 .............................................................. 1185
PWM3 Counter (PWM3COUNT), offset 0x114 ............................................................... 1185
PWM0 Compare A (PWM0CMPA), offset 0x058 ............................................................ 1186
PWM1 Compare A (PWM1CMPA), offset 0x098 ............................................................ 1186
PWM2 Compare A (PWM2CMPA), offset 0x0D8 ............................................................ 1186
PWM3 Compare A (PWM3CMPA), offset 0x118 ............................................................. 1186
PWM0 Compare B (PWM0CMPB), offset 0x05C ............................................................ 1187
PWM1 Compare B (PWM1CMPB), offset 0x09C ............................................................ 1187
PWM2 Compare B (PWM2CMPB), offset 0x0DC ........................................................... 1187
PWM3 Compare B (PWM3CMPB), offset 0x11C ............................................................ 1187
PWM0 Generator A Control (PWM0GENA), offset 0x060 ............................................... 1188
PWM1 Generator A Control (PWM1GENA), offset 0x0A0 ............................................... 1188
PWM2 Generator A Control (PWM2GENA), offset 0x0E0 ............................................... 1188
PWM3 Generator A Control (PWM3GENA), offset 0x120 ............................................... 1188
PWM0 Generator B Control (PWM0GENB), offset 0x064 ............................................... 1191
PWM1 Generator B Control (PWM1GENB), offset 0x0A4 ............................................... 1191
PWM2 Generator B Control (PWM2GENB), offset 0x0E4 ............................................... 1191
PWM3 Generator B Control (PWM3GENB), offset 0x124 ............................................... 1191
PWM0 Dead-Band Control (PWM0DBCTL), offset 0x068 ............................................... 1194
32
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Register 53:
Register 54:
Register 55:
Register 56:
Register 57:
Register 58:
Register 59:
Register 60:
Register 61:
Register 62:
Register 63:
Register 64:
Register 65:
Register 66:
Register 67:
Register 68:
Register 69:
Register 70:
Register 71:
Register 72:
Register 73:
Register 74:
Register 75:
Register 76:
Register 77:
Register 78:
Register 79:
Register 80:
Register 81:
Register 82:
Register 83:
Register 84:
Register 85:
Register 86:
Register 87:
Register 88:
PWM1 Dead-Band Control (PWM1DBCTL), offset 0x0A8 ............................................... 1194
PWM2 Dead-Band Control (PWM2DBCTL), offset 0x0E8 ............................................... 1194
PWM3 Dead-Band Control (PWM3DBCTL), offset 0x128 ............................................... 1194
PWM0 Dead-Band Rising-Edge Delay (PWM0DBRISE), offset 0x06C ............................ 1195
PWM1 Dead-Band Rising-Edge Delay (PWM1DBRISE), offset 0x0AC ............................ 1195
PWM2 Dead-Band Rising-Edge Delay (PWM2DBRISE), offset 0x0EC ............................ 1195
PWM3 Dead-Band Rising-Edge Delay (PWM3DBRISE), offset 0x12C ............................ 1195
PWM0 Dead-Band Falling-Edge-Delay (PWM0DBFALL), offset 0x070 ............................ 1196
PWM1 Dead-Band Falling-Edge-Delay (PWM1DBFALL), offset 0x0B0 ............................ 1196
PWM2 Dead-Band Falling-Edge-Delay (PWM2DBFALL), offset 0x0F0 ............................ 1196
PWM3 Dead-Band Falling-Edge-Delay (PWM3DBFALL), offset 0x130 ............................ 1196
PWM0 Fault Source 0 (PWM0FLTSRC0), offset 0x074 .................................................. 1197
PWM1 Fault Source 0 (PWM1FLTSRC0), offset 0x0B4 .................................................. 1197
PWM2 Fault Source 0 (PWM2FLTSRC0), offset 0x0F4 .................................................. 1197
PWM3 Fault Source 0 (PWM3FLTSRC0), offset 0x134 .................................................. 1197
PWM0 Fault Source 1 (PWM0FLTSRC1), offset 0x078 .................................................. 1199
PWM1 Fault Source 1 (PWM1FLTSRC1), offset 0x0B8 .................................................. 1199
PWM2 Fault Source 1 (PWM2FLTSRC1), offset 0x0F8 .................................................. 1199
PWM3 Fault Source 1 (PWM3FLTSRC1), offset 0x138 .................................................. 1199
PWM0 Minimum Fault Period (PWM0MINFLTPER), offset 0x07C ................................... 1202
PWM1 Minimum Fault Period (PWM1MINFLTPER), offset 0x0BC ................................... 1202
PWM2 Minimum Fault Period (PWM2MINFLTPER), offset 0x0FC ................................... 1202
PWM3 Minimum Fault Period (PWM3MINFLTPER), offset 0x13C ................................... 1202
PWM0 Fault Pin Logic Sense (PWM0FLTSEN), offset 0x800 .......................................... 1203
PWM1 Fault Pin Logic Sense (PWM1FLTSEN), offset 0x880 .......................................... 1203
PWM2 Fault Pin Logic Sense (PWM2FLTSEN), offset 0x900 .......................................... 1203
PWM3 Fault Pin Logic Sense (PWM3FLTSEN), offset 0x980 .......................................... 1203
PWM0 Fault Status 0 (PWM0FLTSTAT0), offset 0x804 ................................................... 1204
PWM1 Fault Status 0 (PWM1FLTSTAT0), offset 0x884 ................................................... 1204
PWM2 Fault Status 0 (PWM2FLTSTAT0), offset 0x904 ................................................... 1204
PWM3 Fault Status 0 (PWM3FLTSTAT0), offset 0x984 ................................................... 1204
PWM0 Fault Status 1 (PWM0FLTSTAT1), offset 0x808 ................................................... 1206
PWM1 Fault Status 1 (PWM1FLTSTAT1), offset 0x888 ................................................... 1206
PWM2 Fault Status 1 (PWM2FLTSTAT1), offset 0x908 ................................................... 1206
PWM3 Fault Status 1 (PWM3FLTSTAT1), offset 0x988 ................................................... 1206
PWM Peripheral Properties (PWMPP), offset 0xFC0 ...................................................... 1209
Quadrature Encoder Interface (QEI) ........................................................................................ 1211
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
QEI Control (QEICTL), offset 0x000 ..............................................................................
QEI Status (QEISTAT), offset 0x004 ..............................................................................
QEI Position (QEIPOS), offset 0x008 ............................................................................
QEI Maximum Position (QEIMAXPOS), offset 0x00C .....................................................
QEI Timer Load (QEILOAD), offset 0x010 .....................................................................
QEI Timer (QEITIME), offset 0x014 ...............................................................................
QEI Velocity Counter (QEICOUNT), offset 0x018 ...........................................................
QEI Velocity (QEISPEED), offset 0x01C ........................................................................
QEI Interrupt Enable (QEIINTEN), offset 0x020 .............................................................
QEI Raw Interrupt Status (QEIRIS), offset 0x024 ...........................................................
QEI Interrupt Status and Clear (QEIISC), offset 0x028 ...................................................
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1222
1223
1224
1225
1226
1227
1228
1230
1232
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Revision History
Revision History
The revision history table notes changes made between the indicated revisions of the
TM4C123BH6PGE data sheet.
Table 1. Revision History
Date
June 2014
March 2014
November 2013
Revision
Description
15842.2741 ■
In System Control Chapter, corrected description for MINSYSDIV bitfield in Device Capabilities 1
(DC1) legacy register.
■
In Timers chapter, removed erroneous references to TCACT bit field.
■
In SSI chapter, corrected that during idle periods the transmit data line SSInTx is tristated.
■
In Package Information appendix:
– Corrected Key to Part Numbers diagram.
– Moved Orderable Part Numbers table to addendum.
– Deleted Packaging Materials section and put into separate packaging document.
■
Additional minor data sheet clarifications and corrections.
15741.2722 ■
In the Internal Memory chapter, in the EEPROM section:
– Added section on soft reset handling.
– Added important information on EEPROM initialization and configuration.
■
In the DMA chapter, added information regarding interrupts and transfers from the UART or SSI
modules.
■
In the Hibernation chapter, noted that the EXTW bit is set in the HIBRIS register regardless of the
PINWEN setting in the HIBCTL register.
■
In the GPIO chapter:
– Corrected table GPIO Pins with Special Considerations.
– Added information on preventing false interrupts.
■
In the Timer chapter:
– Clarified initialization and configuration for Input-Edge Count mode.
– Clarified behavior of TnMIE and TnCINTD bits in the GPTM Timer n Mode (GPTMTnMR)
register.
■
In the Electrical Characteristics chapter:
– In table Reset Characteristics, clarified internal reset time parameter values.
– In table Hibernation Oscillator Input Characteristics, added parameter CINSE Input capacitance.
– In tables Hibernation Oscillator Input Characteristics and Main Oscillator Input Characteristics,
removed parameter C0 Crystal shunt capacitance.
– Updated table Crystal Parameters.
– In table GPIO Module Characteristics, added parameter CGPIO GPIO Digital Input Capacitance.
– Added table PWM Timing Characteristics.
■
In the Package Information appendix:
– Updated Orderable Devices section to reflect silicon revision 7 part numbers.
– Added Tape and Reel pin 1 location.
■
Additional minor data sheet clarifications and corrections.
15553.2700 ■
■
In System Control chapter, clarified PIOSC features and accuracy.
In Hibernation Module chapter:
–
Corrected figures "Using a Crystal as the Hibernation Clock Source with a Single Battery Source"
and "Using a Regulator for Both VDD and VBAT".
34
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Table 1. Revision History (continued)
Date
Revision
Description
Replaced RTC Trim tables with two new figures "Counter Behavior with a TRIM Value of 0x8002"
and "Counter Behavior with a TRIM Value of 0x7FFC".
–
Clarified Hibernation Data (HIBDATA) register description.
■
In Watchdog Timers chapter, clarified Watchdog Control (WDTCTL) register description.
■
In ADC chapter:
–
Clarified functionality when using an ADC digital comparator as a fault source.
–
Clarified signals used for ADC voltage reference.
–
Clarified ADC Trigger Source Select (ADCTSSEL) register description.
–
Corrected VREF bit in ADC Control (ADCCTL) register from 2-bit field [1:0] to 1-bit field [0].
■
In UART chapter, clarified DMA operation.
■
In SSI chapter:
–
Corrected timing guidelines in figures "Freescale SPI Frame Format (Continuous Transfer) with
SPO=1 and SPH=0" and "Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0".
–
Clarified SSI Initialization and Configuration.
–
Corrected bit 3 in SSI Control 1 (SSICR1) register from SOD (SSI Slave Mode Output Disable)
to reserved.
■
In PWM chapter, added clarifications to PWM0 Control (PWM0CTL), PWM0 Interrupt Status and
Clear (PWM0ISC), PWM0 Counter (PWM0COUNT), PWM0 Fault Status 0 (PWM0FLTSTAT0),
and PWM0 Fault Status 1 (PWM0FLTSTAT1) registers.
■
In Signal Tables chapter:
■
■
July 16, 2013
–
15033.2672 ■
–
In Unused Signals table, corrected preferred and acceptable practices for RST pin.
–
Clarified GNDX pin description.
In Electrical Characteristics chapter:
–
In Power-On and Brown-Out Levels table, corrected TVDDC_RISE parameter min and max values.
–
In PIOSC Clock Characteristics table, clarified FPIOSC parameter values by defining values for
both factory calibration and recalibration. Also added PIOSC startup time parameter to table.
–
In Main Oscillator Specifications section, corrected minimum value for External load capacitance
on OSC0, OSC1 pins. Also added two 25-MHz crystals to Crystal Parameters table.
–
Corrected figure "Master Mode SSI Timing for SPI Frame Format (FRF=00), with SPH=1".
–
In I2C Characteristics table, clarified TDH data hold time parameter values by defining values
for both slave and master. In addition, added parameter I10 TDV data valid.
–
Modified figure "I2C Timing" to add new parameter I10.
In Packaging Information appendix, added Packaging Materials figures.
In the Electrical Characteristics chapter:
–
Added maximum junction temperature to Maximum Ratings table. Also moved Unpowered
storage temperature range parameter to this table.
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Revision History
Table 1. Revision History (continued)
Date
Revision
Description
■
July 2013
14995.2667 ■
–
In SSI Characteristics table, corrected values for TRXDMS, TRXDMH, and TRXDSSU. Also clarified
footnotes to table.
–
Corrected parameter numbers in figures "Master Mode SSI Timing for SPI Frame Format
(FRF=00), with SPH=1" and "Slave Mode SSI Timing for SPI Frame Format (FRF=00), with
SPH=1".
Additional minor data sheet clarifications and corrections.
Deleted erroneous references to the PWM Peripheral Configuration (PWMPC) register.
■
In the System Control chapter, corrected resets for bits [7:4] in System Properties (SYSPROP)
register.
■
In the Hibernation Module chapter:
–
Corrected figures "Using a Crystal as the Hibernation Clock Source with a Single Battery Source"
and "Using a Dedicated Oscillator as the Hibernation Clock Source with VDD3ON Mode".
–
Clarified when the Hibernation module can generate interrupts.
■
In the Internal Memory chapter, removed the INVPL bit from the EEPROM Done Status (EEDONE)
register.
■
In the uDMA chapter, in the µDMA Channel Assignments table, corrected names of timers 6-11 to
wide timers 0-5.
■
In the Timers chapter:
–
Clarified that the timer must be configured for one-shot or periodic time-out mode to produce
an ADC trigger assertion and that the GPTM does not generate triggers for match, compare
events or compare match events.
–
Added a step in the RTC Mode initialization and configuration: If the timer has been operating
in a different mode prior to this, clear any residual set bits in the GPTM Timer n Mode
(GPTMTnMR) register before reconfiguring.
■
In the Watchdog Timer chapter, added a note that locking the watchdog registers using the
WDTLOCK register does not affect the WDTICR register and allows interrupts to always be serviced.
■
In the SSI chapter, clarified note in Bit Rate Generation section to indicate that the System Clock
or the PIOSC can be used as the source for SSIClk. Also corrected to indicate maximum SSIClk
limit in SSI slave mode as well as the fact that SYSCLK has to be at least 12 times that of SSICLk.
■
In the PWM chapter, clarified that the PWM has two clock sources, selected by the USPWMDIV bit
in the Run-Mode Clock Configuration (RCC) register.
■
In the QEI chapter, noted that the INTERROR bit is only applicable when the QEI is operating in
quadrature phase mode (SIGMODE=0) and should be masked when SIGMODE=1. Similarly, the
INTDIR bit is only applicable when the QEI is operating in clock/direction mode (SIGMODE=1) and
should be masked when SIGMODE=0.
■
In the Electrical Characteristics chapter:
–
Moved Maximum Ratings and ESD Absolute Maximum Ratings to the front of the chapter.
–
Added VBATRMP parameter to Maximum Ratings and Hibernation Module Battery Characteristics
tables.
–
Added ambient and junction temperatures to Temperature Characteristics table and clarified
values in Thermal Characteristics table.
–
Added clarifying footnote to VVDD_POK parameter in Power-On and Brown-Out Levels table.
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Tiva™ TM4C123BH6PGE Microcontroller
Table 1. Revision History (continued)
Date
Revision
Description
–
In the Flash Memory and EEPROM Characteristics tables, added a parameter for page/mass
erase times for 10k cycles and corrected existing values for all page and mass erase parameters.
–
Corrected DNL max value in ADC Electrical Characteristics table.
–
In the SSI Characteristics table, changed parameter names for S7-S14, provided a max number
instead of a min for S7, and corrected values for S9-S14.
–
Replaced figure "SSI Timing for SPI Frame Format (FRF=00), with SPH=1" with two figures,
one for Master Mode and one for Slave Mode.
–
Updated and added values to the table Table 23-40 on page 1324.
■
In the Package Information appendix, moved orderable devices table from addendum to appendix,
clarified part markings and moved packaging diagram from addendum to appendix.
■
Additional minor data sheet clarifications and corrections.
June 12, 2014
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About This Document
About This Document
This data sheet provides reference information for the TM4C123BH6PGE microcontroller, describing
the functional blocks of the system-on-chip (SoC) device designed around the ARM® Cortex™-M4F
core.
Audience
This manual is intended for system software developers, hardware designers, and application
developers.
About This Manual
This document is organized into sections that correspond to each major feature.
Related Documents
The following related documents are available on the Tiva™ C Series web site at
http://www.ti.com/tiva-c:
■ Tiva™ C Series TM4C123x Silicon Errata (literature number SPMZ849)
■ TivaWare™ Boot Loader for C Series User's Guide (literature number SPMU301)
■ TivaWare™ Graphics Library for C Series User's Guide (literature number SPMU300)
■ TivaWare™ for C Series Release Notes (literature number SPMU299)
■ TivaWare™ Peripheral Driver Library for C Series User's Guide (literature number SPMU298)
■ TivaWare™ USB Library for C Series User's Guide (literature number SPMU297)
■ Tiva™ C Series TM4C123x ROM User’s Guide (literature number SPMU367)
The following related documents may also be useful:
■ ARM® Cortex™-M4 Errata (literature number SPMZ637)
■ ARM® Cortex™-M4 Technical Reference Manual
■ ARM® Debug Interface V5 Architecture Specification
■ ARM® Embedded Trace Macrocell Architecture Specification
■ Cortex™-M4 instruction set chapter in the ARM® Cortex™-M4 Devices Generic User Guide
(literature number ARM DUI 0553A)
■ IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture
This documentation list was current as of publication date. Please check the web site for additional
documentation, including application notes and white papers.
38
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Tiva™ TM4C123BH6PGE Microcontroller
Documentation Conventions
This document uses the conventions shown in Table 2 on page 39.
Table 2. Documentation Conventions
Notation
Meaning
General Register Notation
REGISTER
APB registers are indicated in uppercase bold. For example, PBORCTL is the Power-On and
Brown-Out Reset Control register. If a register name contains a lowercase n, it represents more
than one register. For example, SRCRn represents any (or all) of the three Software Reset Control
registers: SRCR0, SRCR1 , and SRCR2.
bit
A single bit in a register.
bit field
Two or more consecutive and related bits.
offset 0xnnn
A hexadecimal increment to a register's address, relative to that module's base address as specified
in Table 2-4 on page 87.
Register N
Registers are numbered consecutively throughout the document to aid in referencing them. The
register number has no meaning to software.
reserved
Register bits marked reserved are reserved for future use. In most cases, reserved bits are set to
0; however, user software should not rely on the value of a reserved bit. To provide software
compatibility with future products, the value of a reserved bit should be preserved across a
read-modify-write operation.
yy:xx
The range of register bits inclusive from xx to yy. For example, 31:15 means bits 15 through 31 in
that register.
Register Bit/Field
Types
This value in the register bit diagram indicates whether software running on the controller can
change the value of the bit field.
RC
Software can read this field. The bit or field is cleared by hardware after reading the bit/field.
RO
Software can read this field. Always write the chip reset value.
RW
Software can read or write this field.
RWC
Software can read or write this field. Writing to it with any value clears the register.
RW1C
Software can read or write this field. A write of a 0 to a W1C bit does not affect the bit value in the
register. A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged.
This register type is primarily used for clearing interrupt status bits where the read operation provides
the interrupt status and the write of the read value clears only the interrupts being reported at the
time the register was read.
RW1S
Software can read or write a 1 to this field. A write of a 0 to a RW1S bit does not affect the bit value
in the register.
W1C
Software can write this field. A write of a 0 to a W1C bit does not affect the bit value in the register.
A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. A
read of the register returns no meaningful data.
This register is typically used to clear the corresponding bit in an interrupt register.
WO
Only a write by software is valid; a read of the register returns no meaningful data.
Register Bit/Field
Reset Value
This value in the register bit diagram shows the bit/field value after any reset, unless noted.
0
Bit cleared to 0 on chip reset.
1
Bit set to 1 on chip reset.
-
Nondeterministic.
Pin/Signal Notation
[]
Pin alternate function; a pin defaults to the signal without the brackets.
pin
Refers to the physical connection on the package.
signal
Refers to the electrical signal encoding of a pin.
June 12, 2014
39
Texas Instruments-Production Data
About This Document
Table 2. Documentation Conventions (continued)
Notation
Meaning
assert a signal
Change the value of the signal from the logically False state to the logically True state. For active
High signals, the asserted signal value is 1 (High); for active Low signals, the asserted signal value
is 0 (Low). The active polarity (High or Low) is defined by the signal name (see SIGNAL and SIGNAL
below).
deassert a signal
Change the value of the signal from the logically True state to the logically False state.
SIGNAL
Signal names are in uppercase and in the Courier font. An overbar on a signal name indicates that
it is active Low. To assert SIGNAL is to drive it Low; to deassert SIGNAL is to drive it High.
SIGNAL
Signal names are in uppercase and in the Courier font. An active High signal has no overbar. To
assert SIGNAL is to drive it High; to deassert SIGNAL is to drive it Low.
Numbers
X
An uppercase X indicates any of several values is allowed, where X can be any legal pattern. For
example, a binary value of 0X00 can be either 0100 or 0000, a hex value of 0xX is 0x0 or 0x1, and
so on.
0x
Hexadecimal numbers have a prefix of 0x. For example, 0x00FF is the hexadecimal number FF.
All other numbers within register tables are assumed to be binary. Within conceptual information,
binary numbers are indicated with a b suffix, for example, 1011b, and decimal numbers are written
without a prefix or suffix.
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1
Architectural Overview
®
Texas Instrument's Tiva™ C Series microcontrollers provide designers a high-performance ARM
Cortex™-M-based architecture with a broad set of integration capabilities and a strong ecosystem
of software and development tools. Targeting performance and flexibility, the Tiva™ C Series
architecture offers a 80 MHz Cortex-M with FPU, a variety of integrated memories and multiple
programmable GPIO. Tiva™ C Series devices offer consumers compelling cost-effective solutions
by integrating application-specific peripherals and providing a comprehensive library of software
tools which minimize board costs and design-cycle time. Offering quicker time-to-market and cost
savings, the Tiva™ C Series microcontrollers are the leading choice in high-performance 32-bit
applications.
This chapter contains an overview of the Tiva™ C Series microcontrollers as well as details on the
TM4C123BH6PGE microcontroller:
■
■
■
■
■
■
1.1
“Tiva™ C Series Overview” on page 41
“TM4C123BH6PGE Microcontroller Overview” on page 42
“TM4C123BH6PGE Microcontroller Features” on page 45
“TM4C123BH6PGE Microcontroller Hardware Details” on page 63
“Kits” on page 63
“Support Information” on page 63
Tiva™ C Series Overview
The Tiva™ C Series ARM Cortex-M4 microcontrollers provide top performance and advanced
integration. The product family is positioned for cost-conscious applications requiring significant
control processing and connectivity capabilities such as:
■
■
■
■
■
■
■
■
■
■
■
Low power, hand-held smart devices
Gaming equipment
Home and commercial site monitoring and control
Motion control
Medical instrumentation
Test and measurement equipment
Factory automation
Fire and security
Smart Energy/Smart Grid solutions
Intelligent lighting control
Transportation
For applications requiring extreme conservation of power, the TM4C123BH6PGE microcontroller
features a battery-backed Hibernation module to efficiently power down the TM4C123BH6PGE to
a low-power state during extended periods of inactivity. With a power-up/power-down sequencer,
a real-time counter (RTC), multiple wake-from-hibernate options, and dedicated battery-backed
memory, the Hibernation module positions the TM4C123BH6PGE microcontroller perfectly for
battery applications.
In addition, the TM4C123BH6PGE microcontroller offers the advantages of ARM's widely available
development tools, System-on-Chip (SoC) infrastructure IP applications, and a large user community.
Additionally, the microcontroller uses ARM's Thumb®-compatible Thumb-2 instruction set to reduce
memory requirements and, thereby, cost. Finally, much of the TM4C123BH6PGE microcontroller
code is compatible to the Tiva™ C Series product line, providing flexibility across designs.
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Texas Instruments offers a complete solution to get to market quickly, with evaluation and
development boards, white papers and application notes, an easy-to-use peripheral driver library,
and a strong support, sales, and distributor network.
1.2
TM4C123BH6PGE Microcontroller Overview
The TM4C123BH6PGE microcontroller combines complex integration and high performance with
the features shown in Table 1-1.
Table 1-1. TM4C123BH6PGE Microcontroller Features
Feature
Description
Performance
Core
ARM Cortex-M4F processor core
Performance
80-MHz operation; 100 DMIPS performance
Flash
256 KB single-cycle Flash memory
System SRAM
32 KB single-cycle SRAM
EEPROM
2KB of EEPROM
Internal ROM
Internal ROM loaded with TivaWare™ for C Series software
Security
Communication Interfaces
Universal Asynchronous Receivers/Transmitter (UART) Eight UARTs
Synchronous Serial Interface (SSI)
Four SSI modules
Inter-Integrated Circuit (I2C)
Six I2C modules with four transmission speeds including high-speed
mode
Controller Area Network (CAN)
Two CAN 2.0 A/B controllers
System Integration
Micro Direct Memory Access (µDMA)
ARM® PrimeCell® 32-channel configurable μDMA controller
General-Purpose Timer (GPTM)
Six 16/32-bit GPTM blocks and six 32/64-bit Wide GPTM blocks
Watchdog Timer (WDT)
Two watchdog timers
Hibernation Module (HIB)
Low-power battery-backed Hibernation module
General-Purpose Input/Output (GPIO)
14 physical GPIO blocks
Advanced Motion Control
Pulse Width Modulator (PWM)
Two PWM modules, each with four PWM generator blocks and a
control block, for a total of 16 PWM outputs.
Quadrature Encoder Interface (QEI)
Two QEI modules
Analog Support
Analog-to-Digital Converter (ADC)
Two 12-bit ADC modules, each with a maximum sample rate of one
million samples/second
Analog Comparator Controller
Three independent integrated analog comparators
Digital Comparator
16 digital comparators
JTAG and Serial Wire Debug (SWD)
One JTAG module with integrated ARM SWD
Package Information
Package
144-pin LQFP
Operating Range (Ambient)
Industrial (-40°C to 85°C) temperature range
Figure 1-1 on page 44 shows the features on the TM4C123BH6PGE microcontroller. Note that
there are two on-chip buses that connect the core to the peripherals. The Advanced Peripheral Bus
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(APB) bus is the legacy bus. The Advanced High-Performance Bus (AHB) bus provides better
back-to-back access performance than the APB bus.
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Figure 1-1. Tiva™ TM4C123BH6PGE Microcontroller High-Level Block Diagram
JTAG/SWD
ARM®
Cortex™-M4F
ROM
(80MHz)
System
Control and
Clocks
(w/ Precis. Osc.)
ETM
FPU
NVIC
MPU
DCode bus
Boot Loader
DriverLib
AES & CRC
Flash
(256KB)
ICode bus
System Bus
TM4C123BH6PGE
Bus Matrix
SRAM
(32KB)
SYSTEM PERIPHERALS
EEPROM
(2K)
Hibernation
Module
GPIOs
(105)
GeneralPurpose
Timer (12)
I2C
(6)
CAN
Controller
(2)
Analog
Comparator
(3)
Advanced Peripheral Bus (APB)
Watchdog
Timer
(2)
Advanced High-Performance Bus (AHB)
DMA
SERIAL PERIPHERALS
UART
(8)
SSI
(4)
ANALOG PERIPHERALS
12- Bit ADC
Channels
(24)
MOTION CONTROL PERIPHERALS
PWM
(16)
QEI
(2)
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1.3
TM4C123BH6PGE Microcontroller Features
The TM4C123BH6PGE microcontroller component features and general function are discussed in
more detail in the following section.
1.3.1
ARM Cortex-M4F Processor Core
All members of the Tiva™ C Series, including the TM4C123BH6PGE microcontroller, are designed
around an ARM Cortex-M processor core. The ARM Cortex-M processor provides the core for a
high-performance, low-cost platform that meets the needs of minimal memory implementation,
reduced pin count, and low power consumption, while delivering outstanding computational
performance and exceptional system response to interrupts.
1.3.1.1
Processor Core (see page 64)
■ 32-bit ARM Cortex-M4F architecture optimized for small-footprint embedded applications
■ 80-MHz operation; 100 DMIPS performance
■ Outstanding processing performance combined with fast interrupt handling
■ Thumb-2 mixed 16-/32-bit instruction set delivers the high performance expected of a 32-bit
ARM core in a compact memory size usually associated with 8- and 16-bit devices, typically in
the range of a few kilobytes of memory for microcontroller-class applications
– Single-cycle multiply instruction and hardware divide
– Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined
peripheral control
– Unaligned data access, enabling data to be efficiently packed into memory
■ IEEE754-compliant single-precision Floating-Point Unit (FPU)
■ 16-bit SIMD vector processing unit
■ Fast code execution permits slower processor clock or increases sleep mode time
■ Harvard architecture characterized by separate buses for instruction and data
■ Efficient processor core, system and memories
■ Hardware division and fast digital-signal-processing orientated multiply accumulate
■ Saturating arithmetic for signal processing
■ Deterministic, high-performance interrupt handling for time-critical applications
■ Memory protection unit (MPU) to provide a privileged mode for protected operating system
functionality
■ Enhanced system debug with extensive breakpoint and trace capabilities
■ Serial Wire Debug and Serial Wire Trace reduce the number of pins required for debugging and
tracing
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■ Migration from the ARM7™ processor family for better performance and power efficiency
■ Optimized for single-cycle Flash memory usage up to specific frequencies; see “Internal
Memory” on page 522 for more information.
■ Ultra-low power consumption with integrated sleep modes
1.3.1.2
System Timer (SysTick) (see page 119)
ARM Cortex-M4F includes an integrated system timer, SysTick. SysTick provides a simple, 24-bit,
clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter
can be used in several different ways, for example:
■ An RTOS tick timer that fires at a programmable rate (for example, 100 Hz) and invokes a SysTick
routine
■ A high-speed alarm timer using the system clock
■ A variable rate alarm or signal timer—the duration is range-dependent on the reference clock
used and the dynamic range of the counter
■ A simple counter used to measure time to completion and time used
■ An internal clock-source control based on missing/meeting durations
1.3.1.3
Nested Vectored Interrupt Controller (NVIC) (see page 120)
The TM4C123BH6PGE controller includes the ARM Nested Vectored Interrupt Controller (NVIC).
The NVIC and Cortex-M4F prioritize and handle all exceptions in Handler Mode. The processor
state is automatically stored to the stack on an exception and automatically restored from the stack
at the end of the Interrupt Service Routine (ISR). The interrupt vector is fetched in parallel to the
state saving, enabling efficient interrupt entry. The processor supports tail-chaining, meaning that
back-to-back interrupts can be performed without the overhead of state saving and restoration.
Software can set eight priority levels on 7 exceptions (system handlers) and 95 interrupts.
■ Deterministic, fast interrupt processing: always 12 cycles, or just 6 cycles with tail-chaining (these
values reflect no FPU stacking)
■ External non-maskable interrupt signal (NMI) available for immediate execution of NMI handler
for safety critical applications
■ Dynamically reprioritizable interrupts
■ Exceptional interrupt handling via hardware implementation of required register manipulations
1.3.1.4
System Control Block (SCB) (see page 121)
The SCB provides system implementation information and system control, including configuration,
control, and reporting of system exceptions.
1.3.1.5
Memory Protection Unit (MPU) (see page 121)
The MPU supports the standard ARM7 Protected Memory System Architecture (PMSA) model. The
MPU provides full support for protection regions, overlapping protection regions, access permissions,
and exporting memory attributes to the system.
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1.3.1.6
Floating-Point Unit (FPU) (see page 126)
The FPU fully supports single-precision add, subtract, multiply, divide, multiply and accumulate,
and square root operations. It also provides conversions between fixed-point and floating-point data
formats, and floating-point constant instructions.
■ 32-bit instructions for single-precision (C float) data-processing operations
■ Combined multiply and accumulate instructions for increased precision (Fused MAC)
■ Hardware support for conversion, addition, subtraction, multiplication with optional accumulate,
division, and square-root
■ Hardware support for denormals and all IEEE rounding modes
■ 32 dedicated 32-bit single-precision registers, also addressable as 16 double-word registers
■ Decoupled three stage pipeline
1.3.2
On-Chip Memory
The TM4C123BH6PGE microcontroller is integrated with the following set of on-chip memory and
features:
■ 32 KB single-cycle SRAM
■ 256 KB Flash memory
■ 2KB EEPROM
■ Internal ROM loaded with TivaWare™ for C Series software:
– TivaWare™ Peripheral Driver Library
– TivaWare Boot Loader
– Advanced Encryption Standard (AES) cryptography tables
– Cyclic Redundancy Check (CRC) error detection functionality
1.3.2.1
SRAM (see page 523)
The TM4C123BH6PGE microcontroller provides 32 KB of single-cycle on-chip SRAM. The internal
SRAM of the device is located at offset 0x2000.0000 of the device memory map.
Because read-modify-write (RMW) operations are very time consuming, ARM has introduced
bit-banding technology in the Cortex-M4F processor. With a bit-band-enabled processor, certain
regions in the memory map (SRAM and peripheral space) can use address aliases to access
individual bits in a single, atomic operation.
Data can be transferred to and from SRAM by the following masters:
■ µDMA
1.3.2.2
Flash Memory (see page 526)
The TM4C123BH6PGE microcontroller provides 256 KB of single-cycle on-chip Flash memory. The
Flash memory is organized as a set of 1-KB blocks that can be individually erased. Erasing a block
causes the entire contents of the block to be reset to all 1s. These blocks are paired into a set of
2-KB blocks that can be individually protected. The blocks can be marked as read-only or
execute-only, providing different levels of code protection. Read-only blocks cannot be erased or
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programmed, protecting the contents of those blocks from being modified. Execute-only blocks
cannot be erased or programmed, and can only be read by the controller instruction fetch mechanism,
protecting the contents of those blocks from being read by either the controller or by a debugger.
1.3.2.3
ROM (see page 524)
The TM4C123BH6PGE ROM is preprogrammed with the following software and programs:
■ TivaWare Peripheral Driver Library
■ TivaWare Boot Loader
■ Advanced Encryption Standard (AES) cryptography tables
■ Cyclic Redundancy Check (CRC) error-detection functionality
The TivaWare Peripheral Driver Library is a royalty-free software library for controlling on-chip
peripherals with a boot-loader capability. The library performs both peripheral initialization and
control functions, with a choice of polled or interrupt-driven peripheral support. In addition, the library
is designed to take full advantage of the stellar interrupt performance of the ARM Cortex-M4F core.
No special pragmas or custom assembly code prologue/epilogue functions are required. For
applications that require in-field programmability, the royalty-free TivaWare Boot Loader can act as
an application loader and support in-field firmware updates.
The Advanced Encryption Standard (AES) is a publicly defined encryption standard used by the
U.S. Government. AES is a strong encryption method with reasonable performance and size. In
addition, it is fast in both hardware and software, is fairly easy to implement, and requires little
memory. The Texas Instruments encryption package is available with full source code, and is based
on Lesser General Public License (LGPL) source. An LGPL means that the code can be used within
an application without any copyleft implications for the application (the code does not automatically
become open source). Modifications to the package source, however, must be open source.
CRC (Cyclic Redundancy Check) is a technique to validate a span of data has the same contents
as when previously checked. This technique can be used to validate correct receipt of messages
(nothing lost or modified in transit), to validate data after decompression, to validate that Flash
memory contents have not been changed, and for other cases where the data needs to be validated.
A CRC is preferred over a simple checksum (for example, XOR all bits) because it catches changes
more readily.
1.3.2.4
EEPROM (see page 532)
The TM4C123BH6PGE microcontroller includes an EEPROM with the following features:
■ 2Kbytes of memory accessible as 512 32-bit words
■ 32 blocks of 16 words (64 bytes) each
■ Built-in wear leveling
■ Access protection per block
■ Lock protection option for the whole peripheral as well as per block using 32-bit to 96-bit unlock
codes (application selectable)
■ Interrupt support for write completion to avoid polling
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■ Endurance of 500K writes (when writing at fixed offset in every alternate page in circular fashion)
to 15M operations (when cycling through two pages ) per each 2-page block.
1.3.3
Serial Communications Peripherals
The TM4C123BH6PGE controller supports both asynchronous and synchronous serial
communications with:
■ Two CAN 2.0 A/B controllers
■ Eight UARTs with IrDA, 9-bit and ISO 7816 support.
■ Six I2C modules with four transmission speeds including high-speed mode
■ Four Synchronous Serial Interface modules (SSI)
The following sections provide more detail on each of these communications functions.
1.3.3.1
Controller Area Network (CAN) (see page 1065)
Controller Area Network (CAN) is a multicast shared serial-bus standard for connecting electronic
control units (ECUs). CAN was specifically designed to be robust in electromagnetically noisy
environments and can utilize a differential balanced line like RS-485 or twisted-pair wire. Originally
created for automotive purposes, it is now used in many embedded control applications (for example,
industrial or medical). Bit rates up to 1 Mbps are possible at network lengths below 40 meters.
Decreased bit rates allow longer network distances (for example, 125 Kbps at 500m).
A transmitter sends a message to all CAN nodes (broadcasting). Each node decides on the basis
of the identifier received whether it should process the message. The identifier also determines the
priority that the message enjoys in competition for bus access. Each CAN message can transmit
from 0 to 8 bytes of user information.
The TM4C123BH6PGE microcontroller includes two CAN units with the following features:
■ CAN protocol version 2.0 part A/B
■ Bit rates up to 1 Mbps
■ 32 message objects with individual identifier masks
■ Maskable interrupt
■ Disable Automatic Retransmission mode for Time-Triggered CAN (TTCAN) applications
■ Programmable loopback mode for self-test operation
■ Programmable FIFO mode enables storage of multiple message objects
■ Gluelessly attaches to an external CAN transceiver through the CANnTX and CANnRX signals
1.3.3.2
UART (see page 908)
A Universal Asynchronous Receiver/Transmitter (UART) is an integrated circuit used for RS-232C
serial communications, containing a transmitter (parallel-to-serial converter) and a receiver
(serial-to-parallel converter), each clocked separately.
The TM4C123BH6PGE microcontroller includes eight fully programmable 16C550-type UARTs.
Although the functionality is similar to a 16C550 UART, this UART design is not register compatible.
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The UART can generate individually masked interrupts from the Rx, Tx, modem flow control, modem
status, and error conditions. The module generates a single combined interrupt when any of the
interrupts are asserted and are unmasked.
The eight UARTs have the following features:
■ Programmable baud-rate generator allowing speeds up to 5 Mbps for regular speed (divide by
16) and 10 Mbps for high speed (divide by 8)
■ Separate 16x8 transmit (TX) and receive (RX) FIFOs to reduce CPU interrupt service loading
■ Programmable FIFO length, including 1-byte deep operation providing conventional
double-buffered interface
■ FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8
■ Standard asynchronous communication bits for start, stop, and parity
■ Line-break generation and detection
■ Fully programmable serial interface characteristics
– 5, 6, 7, or 8 data bits
– Even, odd, stick, or no-parity bit generation/detection
– 1 or 2 stop bit generation
■ IrDA serial-IR (SIR) encoder/decoder providing
– Programmable use of IrDA Serial Infrared (SIR) or UART input/output
– Support of IrDA SIR encoder/decoder functions for data rates up to 115.2 Kbps half-duplex
– Support of normal 3/16 and low-power (1.41-2.23 μs) bit durations
– Programmable internal clock generator enabling division of reference clock by 1 to 256 for
low-power mode bit duration
■ Support for communication with ISO 7816 smart cards
■ Modem flow control and status (on UART1)
■ EIA-485 9-bit support
■ Standard FIFO-level and End-of-Transmission interrupts
■ Efficient transfers using Micro Direct Memory Access Controller (µDMA)
– Separate channels for transmit and receive
– Receive single request asserted when data is in the FIFO; burst request asserted at
programmed FIFO level
– Transmit single request asserted when there is space in the FIFO; burst request asserted at
programmed FIFO level
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1.3.3.3
I2C (see page 1014)
The Inter-Integrated Circuit (I2C) bus provides bi-directional data transfer through a two-wire design
(a serial data line SDA and a serial clock line SCL). The I2C bus interfaces to external I2C devices
such as serial memory (RAMs and ROMs), networking devices, LCDs, tone generators, and so on.
The I2C bus may also be used for system testing and diagnostic purposes in product development
and manufacture.
Each device on the I2C bus can be designated as either a master or a slave. I2C module supports
both sending and receiving data as either a master or a slave and can operate simultaneously as
both a master and a slave. Both the I2C master and slave can generate interrupts.
The TM4C123BH6PGE microcontroller includes six I2C modules with the following features:
■ Devices on the I2C bus can be designated as either a master or a slave
– Supports both transmitting and receiving data as either a master or a slave
– Supports simultaneous master and slave operation
■ Four I2C modes
– Master transmit
– Master receive
– Slave transmit
– Slave receive
■ Four transmission speeds:
– Standard (100 Kbps)
– Fast-mode (400 Kbps)
– Fast-mode plus (1 Mbps)
– High-speed mode (3.33 Mbps)
■ Clock low timeout interrupt
■ Dual slave address capability
■ Glitch suppression
■ Master and slave interrupt generation
– Master generates interrupts when a transmit or receive operation completes (or aborts due
to an error)
– Slave generates interrupts when data has been transferred or requested by a master or when
a START or STOP condition is detected
■ Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing
mode
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1.3.3.4
SSI (see page 969)
Synchronous Serial Interface (SSI) is a four-wire bi-directional communications interface that converts
data between parallel and serial. The SSI module performs serial-to-parallel conversion on data
received from a peripheral device, and parallel-to-serial conversion on data transmitted to a peripheral
device. The SSI module can be configured as either a master or slave device. As a slave device,
the SSI module can also be configured to disable its output, which allows a master device to be
coupled with multiple slave devices. The TX and RX paths are buffered with separate internal FIFOs.
The SSI module also includes a programmable bit rate clock divider and prescaler to generate the
output serial clock derived from the SSI module's input clock. Bit rates are generated based on the
input clock and the maximum bit rate is determined by the connected peripheral.
The TM4C123BH6PGE microcontroller includes four SSI modules with the following features:
■ Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments
synchronous serial interfaces
■ Master or slave operation
■ Programmable clock bit rate and prescaler
■ Separate transmit and receive FIFOs, each 16 bits wide and 8 locations deep
■ Programmable data frame size from 4 to 16 bits
■ Internal loopback test mode for diagnostic/debug testing
■ Standard FIFO-based interrupts and End-of-Transmission interrupt
■ Efficient transfers using Micro Direct Memory Access Controller (µDMA)
– Separate channels for transmit and receive
– Receive single request asserted when data is in the FIFO; burst request asserted when FIFO
contains 4 entries
– Transmit single request asserted when there is space in the FIFO; burst request asserted
when four or more entries are available to be written in the FIFO
1.3.4
System Integration
The TM4C123BH6PGE microcontroller provides a variety of standard system functions integrated
into the device, including:
■ Direct Memory Access Controller (DMA)
■ System control and clocks including on-chip precision 16-MHz oscillator
■ Six 32-bit timers (up to twelve 16-bit)
■ Six wide 64-bit timers (up to twelve 32-bit)
■ Twelve 32/64-bit Capture Compare PWM (CCP) pins
■ Lower-power battery-backed Hibernation module
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■ Real-Time Clock in Hibernation module
■ Two Watchdog Timers
– One timer runs off the main oscillator
– One timer runs off the precision internal oscillator
■ Up to 105 GPIOs, depending on configuration
– Highly flexible pin muxing allows use as GPIO or one of several peripheral functions
– Independently configurable to 2-, 4- or 8-mA drive capability
– Up to 4 GPIOs can have 18-mA drive capability
The following sections provide more detail on each of these functions.
1.3.4.1
Direct Memory Access (see page 583)
The TM4C123BH6PGE microcontroller includes a Direct Memory Access (DMA) controller, known
as micro-DMA (μDMA). The μDMA controller provides a way to offload data transfer tasks from the
Cortex-M4F processor, allowing for more efficient use of the processor and the available bus
bandwidth. The μDMA controller can perform transfers between memory and peripherals. It has
dedicated channels for each supported on-chip module and can be programmed to automatically
perform transfers between peripherals and memory as the peripheral is ready to transfer more data.
The μDMA controller provides the following features:
®
■ ARM PrimeCell 32-channel configurable µDMA controller
■ Support for memory-to-memory, memory-to-peripheral, and peripheral-to-memory in multiple
transfer modes
– Basic for simple transfer scenarios
– Ping-pong for continuous data flow
– Scatter-gather for a programmable list of up to 256 arbitrary transfers initiated from a single
request
■ Highly flexible and configurable channel operation
– Independently configured and operated channels
– Dedicated channels for supported on-chip modules
– Flexible channel assignments
– One channel each for receive and transmit path for bidirectional modules
– Dedicated channel for software-initiated transfers
– Per-channel configurable priority scheme
– Optional software-initiated requests for any channel
■ Two levels of priority
■ Design optimizations for improved bus access performance between µDMA controller and the
processor core
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– µDMA controller access is subordinate to core access
– RAM striping
– Peripheral bus segmentation
■ Data sizes of 8, 16, and 32 bits
■ Transfer size is programmable in binary steps from 1 to 1024
■ Source and destination address increment size of byte, half-word, word, or no increment
■ Maskable peripheral requests
■ Interrupt on transfer completion, with a separate interrupt per channel
1.3.4.2
System Control and Clocks (see page 208)
System control determines the overall operation of the device. It provides information about the
device, controls power-saving features, controls the clocking of the device and individual peripherals,
and handles reset detection and reporting.
■ Device identification information: version, part number, SRAM size, Flash memory size, and so
on
■ Power control
– On-chip fixed Low Drop-Out (LDO) voltage regulator
– Hibernation module handles the power-up/down 3.3 V sequencing and control for the core
digital logic and analog circuits
– Low-power options for microcontroller: Sleep and Deep-Sleep modes with clock gating
– Low-power options for on-chip modules: software controls shutdown of individual peripherals
and memory
– 3.3-V supply brown-out detection and reporting via interrupt or reset
■ Multiple clock sources for microcontroller system clock. The following clock sources are provided
to the TM4C123BH6PGE microcontroller:
– Precision Internal Oscillator (PIOSC) providing a 16-MHz frequency
• 16 MHz ±3% across temperature and voltage
• Can be recalibrated with 7-bit trim resolution to achieve better accuracy (16 MHz ±1%)
• Software power down control for low power modes
– Main Oscillator (MOSC): A frequency-accurate clock source by one of two means: an external
single-ended clock source is connected to the OSC0 input pin, or an external crystal is
connected across the OSC0 input and OSC1 output pins.
– Low Frequency Internal Oscillator (LFIOSC): On-chip resource used during power-saving
modes
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– Hibernate RTC oscillator (RTCOSC) clock that can be configured to be the 32.768-kHz
external oscillator source from the Hibernation (HIB) module or the HIB Low Frequency clock
source (HIB LFIOSC), which is located within the Hibernation Module.
■ Flexible reset sources
– Power-on reset (POR)
– Reset pin assertion
– Brown-out reset (BOR) detector alerts to system power drops
– Software reset
– Watchdog timer reset
– MOSC failure
1.3.4.3
Programmable Timers (see page 712)
Programmable timers can be used to count or time external events that drive the Timer input pins.
Each 16/32-bit GPTM block provides two 16-bit timers/counters that can be configured to operate
independently as timers or event counters, or configured to operate as one 32-bit timer or one 32-bit
Real-Time Clock (RTC). Each 32/64-bit Wide GPTM block provides two 32-bit timers/counters that
can be configured to operate independently as timersor event counters, or configured to operate
as one 64-bit timer or one 64-bit Real-Time Clock (RTC). Timers can also be used to trigger
analog-to-digital (ADC) conversions and DMA transfers.
The General-Purpose Timer Module (GPTM) contains six 16/32-bit GPTM blocks and six 32/64-bit
Wide GPTM blocks with the following functional options:
■ 16/32-bit operating modes:
– 16- or 32-bit programmable one-shot timer
– 16- or 32-bit programmable periodic timer
– 16-bit general-purpose timer with an 8-bit prescaler
– 32-bit Real-Time Clock (RTC) when using an external 32.768-KHz clock as the input
– 16-bit input-edge count- or time-capture modes with an 8-bit prescaler
– 16-bit PWM mode with an 8-bit prescaler and software-programmable output inversion of the
PWM signal
■ 32/64-bit operating modes:
– 32- or 64-bit programmable one-shot timer
– 32- or 64-bit programmable periodic timer
– 32-bit general-purpose timer with a 16-bit prescaler
– 64-bit Real-Time Clock (RTC) when using an external 32.768-KHz clock as the input
– 32-bit input-edge count- or time-capture modes with a16-bit prescaler
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– 32-bit PWM mode with a 16-bit prescaler and software-programmable output inversion of the
PWM signal
■ Count up or down
■ Twelve 16/32-bit Capture Compare PWM pins (CCP)
■ Twelve 32/64-bit Capture Compare PWM pins (CCP)
■ Daisy chaining of timer modules to allow a single timer to initiate multiple timing events
■ Timer synchronization allows selected timers to start counting on the same clock cycle
■ ADC event trigger
■ User-enabled stalling when the microcontroller asserts CPU Halt flag during debug (excluding
RTC mode)
■ Ability to determine the elapsed time between the assertion of the timer interrupt and entry into
the interrupt service routine
■ Efficient transfers using Micro Direct Memory Access Controller (µDMA)
– Dedicated channel for each timer
– Burst request generated on timer interrupt
1.3.4.4
CCP Pins (see page 721)
Capture Compare PWM pins (CCP) can be used by the General-Purpose Timer Module to time/count
external events using the CCP pin as an input. Alternatively, the GPTM can generate a simple PWM
output on the CCP pin.
The TM4C123BH6PGE microcontroller includes twelve 16/32-bit CCP pins that can be programmed
to operate in the following modes:
■ Capture: The GP Timer is incremented/decremented by programmed events on the CCP input.
The GP Timer captures and stores the current timer value when a programmed event occurs.
■ Compare: The GP Timer is incremented/decremented by programmed events on the CCP input.
The GP Timer compares the current value with a stored value and generates an interrupt when
a match occurs.
■ PWM: The GP Timer is incremented/decremented by the system clock. A PWM signal is generated
based on a match between the counter value and a value stored in a match register and is output
on the CCP pin.
1.3.4.5
Hibernation Module (HIB) (see page 491)
The Hibernation module provides logic to switch power off to the main processor and peripherals
and to wake on external or time-based events. The Hibernation module includes power-sequencing
logic and has the following features:
■ 32-bit real-time seconds counter (RTC) with 1/32,768 second resolution and a 15-bit sub-seconds
counter
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– 32-bit RTC seconds match register and a 15-bit sub seconds match for timed wake-up and
interrupt generation with 1/32,768 second resolution
– RTC predivider trim for making fine adjustments to the clock rate
■ Two mechanisms for power control
– System power control using discrete external regulator
– On-chip power control using internal switches under register control
■ Dedicated pin for waking using an external signal
■ RTC operational and hibernation memory valid as long as VDD or VBAT is valid
■ Low-battery detection, signaling, and interrupt generation, with optional wake on low battery
■ GPIO pin state can be retained during hibernation
■ Clock source from a 32.768-kHz external crystal or oscillator
■ Sixteen 32-bit words of battery-backed memory to save state during hibernation
■ Programmable interrupts for:
– RTC match
– External wake
– Low battery
1.3.4.6
Watchdog Timers (see page 783)
A watchdog timer is used to regain control when a system has failed due to a software error or to
the failure of an external device to respond in the expected way. The TM4C123BH6PGE Watchdog
Timer can generate an interrupt, a non-maskable interrupt, or a reset when a time-out value is
reached. In addition, the Watchdog Timer is ARM FiRM-compliant and can be configured to generate
an interrupt to the microcontroller on its first time-out, and to generate a reset signal on its second
timeout. Once the Watchdog Timer has been configured, the lock register can be written to prevent
the timer configuration from being inadvertently altered.
The TM4C123BH6PGE microcontroller has two Watchdog Timer modules: Watchdog Timer 0 uses
the system clock for its timer clock; Watchdog Timer 1 uses the PIOSC as its timer clock. The
Watchdog Timer module has the following features:
■ 32-bit down counter with a programmable load register
■ Separate watchdog clock with an enable
■ Programmable interrupt generation logic with interrupt masking and optional NMI function
■ Lock register protection from runaway software
■ Reset generation logic with an enable/disable
■ User-enabled stalling when the microcontroller asserts the CPU Halt flag during debug
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Architectural Overview
1.3.4.7
Programmable GPIOs (see page 647)
General-purpose input/output (GPIO) pins offer flexibility for a variety of connections. The
TM4C123BH6PGE GPIO module is comprised of 14 physical GPIO blocks, each corresponding to
an individual GPIO port. The GPIO module is FiRM-compliant (compliant to the ARM Foundation
IP for Real-Time Microcontrollers specification) and supports 0-105 programmable input/output pins.
The number of GPIOs available depends on the peripherals being used (see “Signal
Tables” on page 1235 for the signals available to each GPIO pin).
■ Up to 105 GPIOs, depending on configuration
■ Highly flexible pin muxing allows use as GPIO or one of several peripheral functions
■ 5-V-tolerant in input configuration
■ Fast toggle capable of a change every clock cycle for ports on AHB, every two clock cycles for
ports on APB
■ Programmable control for GPIO interrupts
– Interrupt generation masking
– Edge-triggered on rising, falling, or both
– Level-sensitive on High or Low values
– Per-pin interrupts available on Port P
■ Bit masking in both read and write operations through address lines
■ Can be used to initiate an ADC sample sequence or a μDMA transfer
■ Pin state can be retained during Hibernation mode
■ Pins configured as digital inputs are Schmitt-triggered
■ Programmable control for GPIO pad configuration
– Weak pull-up or pull-down resistors
– 2-mA, 4-mA, and 8-mA pad drive for digital communication; up to four pads can sink 18-mA
for high-current applications
– Slew rate control for 8-mA pad drive
– Open drain enables
– Digital input enables
1.3.5
Advanced Motion Control
The TM4C123BH6PGE microcontroller provides motion control functions integrated into the device,
including:
■ Two PWM modules, with a total of 16 advanced PWM outputs for motion and energy applications
■ Eight fault inputs to promote low-latency shutdown
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■ Two Quadrature Encoder Inputs (QEI)
The following provides more detail on these motion control functions.
1.3.5.1
PWM (see page 1132)
The TM4C123BH6PGE microcontroller contains two PWM modules, each with four PWM generator
blocks and a control block, for a total of 16 PWM outputs. Pulse width modulation (PWM) is a
powerful technique for digitally encoding analog signal levels. High-resolution counters are used to
generate a square wave, and the duty cycle of the square wave is modulated to encode an analog
signal. Typical applications include switching power supplies and motor control. Each
TM4C123BH6PGE PWM module consists of four PWM generator block and a control block. Each
PWM generator block contains one timer (16-bit down or up/down counter), two comparators, a
PWM signal generator, a dead-band generator, and an interrupt/ADC-trigger selector. Each PWM
generator block produces two PWM signals that can either be independent signals or a single pair
of complementary signals with dead-band delays inserted.
Each PWM generator has the following features:
■ Four fault-condition handling inputs to quickly provide low-latency shutdown and prevent damage
to the motor being controlled, for a total of eight inputs
■ One 16-bit counter
– Runs in Down or Up/Down mode
– Output frequency controlled by a 16-bit load value
– Load value updates can be synchronized
– Produces output signals at zero and load value
■ Two PWM comparators
– Comparator value updates can be synchronized
– Produces output signals on match
■ PWM signal generator
– Output PWM signal is constructed based on actions taken as a result of the counter and
PWM comparator output signals
– Produces two independent PWM signals
■ Dead-band generator
– Produces two PWM signals with programmable dead-band delays suitable for driving a half-H
bridge
– Can be bypassed, leaving input PWM signals unmodified
■ Can initiate an ADC sample sequence
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The control block determines the polarity of the PWM signals and which signals are passed through
to the pins. The output of the PWM generation blocks are managed by the output control block
before being passed to the device pins. The PWM control block has the following options:
■ PWM output enable of each PWM signal
■ Optional output inversion of each PWM signal (polarity control)
■ Optional fault handling for each PWM signal
■ Synchronization of timers in the PWM generator blocks
■ Synchronization of timer/comparator updates across the PWM generator blocks
■ Extended PWM synchronization of timer/comparator updates across the PWM generator blocks
■ Interrupt status summary of the PWM generator blocks
■ Extended PWM fault handling, with multiple fault signals, programmable polarities, and filtering
■ PWM generators can be operated independently or synchronized with other generators
1.3.5.2
QEI (see page 1211)
A quadrature encoder, also known as a 2-channel incremental encoder, converts linear displacement
into a pulse signal. By monitoring both the number of pulses and the relative phase of the two signals,
the position, direction of rotation, and speed can be tracked. In addition, a third channel, or index
signal, can be used to reset the position counter. The TM4C123BH6PGE quadrature encoder with
index (QEI) module interprets the code produced by a quadrature encoder wheel to integrate position
over time and determine direction of rotation. In addition, it can capture a running estimate of the
velocity of the encoder wheel. The input frequency of the QEI inputs may be as high as 1/4 of the
processor frequency (for example, 20 MHz for a 80-MHz system).
The TM4C123BH6PGE microcontroller includes two QEI modules providing control of two motors
at the same time with the following features:
■ Position integrator that tracks the encoder position
■ Programmable noise filter on the inputs
■ Velocity capture using built-in timer
■ The input frequency of the QEI inputs may be as high as 1/4 of the processor frequency (for
example, 12.5 MHz for a 50-MHz system)
■ Interrupt generation on:
– Index pulse
– Velocity-timer expiration
– Direction change
– Quadrature error detection
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1.3.6
Analog
The TM4C123BH6PGE microcontroller provides analog functions integrated into the device, including:
■ Two 12-bit Analog-to-Digital Converters (ADC), with a total of 24 analog input channels and each
with a sample rate of one million samples/second
■ Three analog comparators
■ On-chip voltage regulator
The following provides more detail on these analog functions.
1.3.6.1
ADC (see page 808)
An analog-to-digital converter (ADC) is a peripheral that converts a continuous analog voltage to a
discrete digital number. The TM4C123BH6PGE ADC module features 12-bit conversion resolution
and supports 24 input channels plus an internal temperature sensor. Four buffered sample
sequencers allow rapid sampling of up to 24 analog input sources without controller intervention.
Each sample sequencer provides flexible programming with fully configurable input source, trigger
events, interrupt generation, and sequencer priority. Each ADC module has a digital comparator
function that allows the conversion value to be diverted to a comparison unit that provides eight
digital comparators.
The TM4C123BH6PGE microcontroller provides two ADC modules, each with the following features:
■ 24 shared analog input channels
■ 12-bit precision ADC
■ Single-ended and differential-input configurations
■ On-chip internal temperature sensor
■ Maximum sample rate of one million samples/second
■ Optional phase shift in sample time programmable from 22.5º to 337.5º
■ Four programmable sample conversion sequencers from one to eight entries long, with
corresponding conversion result FIFOs
■ Flexible trigger control
– Controller (software)
– Timers
– Analog Comparators
– PWM
– GPIO
■ Hardware averaging of up to 64 samples
■ Eight digital comparators
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■ Converter uses two external reference signals (VREFA+ and VREFA-) or VDDA and GNDA as the
voltage reference
■ Power and ground for the analog circuitry is separate from the digital power and ground
■ Efficient transfers using Micro Direct Memory Access Controller (µDMA)
– Dedicated channel for each sample sequencer
– ADC module uses burst requests for DMA
1.3.6.2
Analog Comparators (see page 1116)
An analog comparator is a peripheral that compares two analog voltages and provides a logical
output that signals the comparison result. The TM4C123BH6PGE microcontroller provides three
independent integrated analog comparators that can be configured to drive an output or generate
an interrupt or ADC event.
The comparator can provide its output to a device pin, acting as a replacement for an analog
comparator on the board, or it can be used to signal the application via interrupts or triggers to the
ADC to cause it to start capturing a sample sequence. The interrupt generation and ADC triggering
logic is separate. This means, for example, that an interrupt can be generated on a rising edge and
the ADC triggered on a falling edge.
The TM4C123BH6PGE microcontroller provides three independent integrated analog comparators
with the following functions:
■ Compare external pin input to external pin input or to internal programmable voltage reference
■ Compare a test voltage against any one of the following voltages:
– An individual external reference voltage
– A shared single external reference voltage
– A shared internal reference voltage
1.3.7
JTAG and ARM Serial Wire Debug (see page 196)
The Joint Test Action Group (JTAG) port is an IEEE standard that defines a Test Access Port and
Boundary Scan Architecture for digital integrated circuits and provides a standardized serial interface
for controlling the associated test logic. The TAP, Instruction Register (IR), and Data Registers (DR)
can be used to test the interconnections of assembled printed circuit boards and obtain manufacturing
information on the components. The JTAG Port also provides a means of accessing and controlling
design-for-test features such as I/O pin observation and control, scan testing, and debugging. Texas
Instruments replaces the ARM SW-DP and JTAG-DP with the ARM Serial Wire JTAG Debug Port
(SWJ-DP) interface. The SWJ-DP interface combines the SWD and JTAG debug ports into one
module providing all the normal JTAG debug and test functionality plus real-time access to system
memory without halting the core or requiring any target resident code. The SWJ-DP interface has
the following features:
■ IEEE 1149.1-1990 compatible Test Access Port (TAP) controller
■ Four-bit Instruction Register (IR) chain for storing JTAG instructions
■ IEEE standard instructions: BYPASS, IDCODE, SAMPLE/PRELOAD, and EXTEST
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■ ARM additional instructions: APACC, DPACC and ABORT
■ Integrated ARM Serial Wire Debug (SWD)
– Serial Wire JTAG Debug Port (SWJ-DP)
– Flash Patch and Breakpoint (FPB) unit for implementing breakpoints
– Data Watchpoint and Trace (DWT) unit for implementing watchpoints, trigger resources, and
system profiling
– Instrumentation Trace Macrocell (ITM) for support of printf style debugging
– Embedded Trace Macrocell (ETM) for instruction trace capture
– Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer
1.3.8
Packaging and Temperature
■ 144-pin RoHS-compliant LQFP package
■ Industrial (-40°C to 85°C) ambient temperature range
1.4
TM4C123BH6PGE Microcontroller Hardware Details
Details on the pins and package can be found in the following sections:
■ “Pin Diagram” on page 1234
■ “Signal Tables” on page 1235
■ “Electrical Characteristics” on page 1282
■ “Package Information” on page 1327
1.5
Kits
The Tiva™ C Series provides the hardware and software tools that engineers need to begin
development quickly.
■ Reference Design Kits accelerate product development by providing ready-to-run hardware and
comprehensive documentation including hardware design files
■ Evaluation Kits provide a low-cost and effective means of evaluating TM4C123BH6PGE
microcontrollers before purchase
■ Development Kits provide you with all the tools you need to develop and prototype embedded
applications right out of the box
See the Tiva series website at http://www.ti.com/tiva-c for the latest tools available, or ask your
distributor.
1.6
Support Information
For support on Tiva™ C Series products, contact the TI Worldwide Product Information Center
nearest you.
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The Cortex-M4F Processor
2
The Cortex-M4F Processor
The ARM® Cortex™-M4F processor provides a high-performance, low-cost platform that meets the
system requirements of minimal memory implementation, reduced pin count, and low power
consumption, while delivering outstanding computational performance and exceptional system
response to interrupts. Features include:
®
■ 32-bit ARM Cortex™-M4F architecture optimized for small-footprint embedded applications
■ 80-MHz operation; 100 DMIPS performance
■ Outstanding processing performance combined with fast interrupt handling
■ Thumb-2 mixed 16-/32-bit instruction set delivers the high performance expected of a 32-bit
ARM core in a compact memory size usually associated with 8- and 16-bit devices, typically in
the range of a few kilobytes of memory for microcontroller-class applications
– Single-cycle multiply instruction and hardware divide
– Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined
peripheral control
– Unaligned data access, enabling data to be efficiently packed into memory
■ IEEE754-compliant single-precision Floating-Point Unit (FPU)
■ 16-bit SIMD vector processing unit
■ Fast code execution permits slower processor clock or increases sleep mode time
■ Harvard architecture characterized by separate buses for instruction and data
■ Efficient processor core, system and memories
■ Hardware division and fast digital-signal-processing orientated multiply accumulate
■ Saturating arithmetic for signal processing
■ Deterministic, high-performance interrupt handling for time-critical applications
■ Memory protection unit (MPU) to provide a privileged mode for protected operating system
functionality
■ Enhanced system debug with extensive breakpoint and trace capabilities
■ Serial Wire Debug and Serial Wire Trace reduce the number of pins required for debugging and
tracing
■ Migration from the ARM7™ processor family for better performance and power efficiency
■ Optimized for single-cycle Flash memory usage up to specific frequencies; see “Internal
Memory” on page 522 for more information.
■ Ultra-low power consumption with integrated sleep modes
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The Tiva™ C Series microcontrollers builds on this core to bring high-performance 32-bit computing
to
This chapter provides information on the Tiva™ C Series implementation of the Cortex-M4F
processor, including the programming model, the memory model, the exception model, fault handling,
and power management.
For technical details on the instruction set, see the Cortex™-M4 instruction set chapter in the ARM®
Cortex™-M4 Devices Generic User Guide (literature number ARM DUI 0553A).
2.1
Block Diagram
The Cortex-M4F processor is built on a high-performance processor core, with a 3-stage pipeline
Harvard architecture, making it ideal for demanding embedded applications. The processor delivers
exceptional power efficiency through an efficient instruction set and extensively optimized design,
providing high-end processing hardware including IEEE754-compliant single-precision floating-point
computation, a range of single-cycle and SIMD multiplication and multiply-with-accumulate
capabilities, saturating arithmetic and dedicated hardware division.
To facilitate the design of cost-sensitive devices, the Cortex-M4F processor implements tightly
coupled system components that reduce processor area while significantly improving interrupt
handling and system debug capabilities. The Cortex-M4F processor implements a version of the
Thumb® instruction set based on Thumb-2 technology, ensuring high code density and reduced
program memory requirements. The Cortex-M4F instruction set provides the exceptional performance
expected of a modern 32-bit architecture, with the high code density of 8-bit and 16-bit
microcontrollers.
The Cortex-M4F processor closely integrates a nested interrupt controller (NVIC), to deliver
industry-leading interrupt performance. The TM4C123BH6PGE NVIC includes a non-maskable
interrupt (NMI) and provides eight interrupt priority levels. The tight integration of the processor core
and NVIC provides fast execution of interrupt service routines (ISRs), dramatically reducing interrupt
latency. The hardware stacking of registers and the ability to suspend load-multiple and store-multiple
operations further reduce interrupt latency. Interrupt handlers do not require any assembler stubs
which removes code overhead from the ISRs. Tail-chaining optimization also significantly reduces
the overhead when switching from one ISR to another. To optimize low-power designs, the NVIC
integrates with the sleep modes, including Deep-sleep mode, which enables the entire device to be
rapidly powered down.
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Figure 2-1. CPU Block Diagram
Nested
Vectored
Interrupt
Controller
FPU
Interrupts
Sleep
ARM
Cortex-M4F
CM4 Core
Debug
Instructions
Data
Embedded
Trace
Macrocell
Memory
Protection
Unit
Flash
Patch and
Breakpoint
Instrumentation
Data
Watchpoint Trace Macrocell
and Trace
ROM
Table
Private Peripheral
Bus
(internal)
Adv. Peripheral
Bus
Bus
Matrix
Serial Wire JTAG
Debug Port
Debug
Access Port
2.2
Overview
2.2.1
System-Level Interface
Trace
Port
Interface
Unit
Serial
Wire
Output
Trace
Port
(SWO)
I-code bus
D-code bus
System bus
The Cortex-M4F processor provides multiple interfaces using AMBA® technology to provide
high-speed, low-latency memory accesses. The core supports unaligned data accesses and
implements atomic bit manipulation that enables faster peripheral controls, system spinlocks, and
thread-safe Boolean data handling.
The Cortex-M4F processor has a memory protection unit (MPU) that provides fine-grain memory
control, enabling applications to implement security privilege levels and separate code, data and
stack on a task-by-task basis.
2.2.2
Integrated Configurable Debug
The Cortex-M4F processor implements a complete hardware debug solution, providing high system
visibility of the processor and memory through either a traditional JTAG port or a 2-pin Serial Wire
Debug (SWD) port that is ideal for microcontrollers and other small package devices. The Tiva™
C Series implementation replaces the ARM SW-DP and JTAG-DP with the ARM
CoreSight™-compliant Serial Wire JTAG Debug Port (SWJ-DP) interface. The SWJ-DP interface
combines the SWD and JTAG debug ports into one module. See the ARM® Debug Interface V5
Architecture Specification for details on SWJ-DP.
For system trace, the processor integrates an Instrumentation Trace Macrocell (ITM) alongside data
watchpoints and a profiling unit. To enable simple and cost-effective profiling of the system trace
events, a Serial Wire Viewer (SWV) can export a stream of software-generated messages, data
trace, and profiling information through a single pin.
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The Embedded Trace Macrocell (ETM) delivers unrivaled instruction trace capture in an area smaller
than traditional trace units, enabling full instruction trace. For more details on the ARM ETM, see
the ARM® Embedded Trace Macrocell Architecture Specification.
The Flash Patch and Breakpoint Unit (FPB) provides up to eight hardware breakpoint comparators
that debuggers can use. The comparators in the FPB also provide remap functions for up to eight
words of program code in the code memory region. This FPB enables applications stored in a
read-only area of Flash memory to be patched in another area of on-chip SRAM or Flash memory.
If a patch is required, the application programs the FPB to remap a number of addresses. When
those addresses are accessed, the accesses are redirected to a remap table specified in the FPB
configuration.
For more information on the Cortex-M4F debug capabilities, see theARM® Debug Interface V5
Architecture Specification.
2.2.3
Trace Port Interface Unit (TPIU)
The TPIU acts as a bridge between the Cortex-M4F trace data from the ITM, and an off-chip Trace
Port Analyzer, as shown in Figure 2-2 on page 67.
Figure 2-2. TPIU Block Diagram
2.2.4
Debug
ATB
Slave
Port
ARM® Trace
Bus (ATB)
Interface
APB
Slave
Port
Advance
Peripheral
Bus (APB)
Interface
Asynchronous FIFO
Trace Out
(serializer)
Serial Wire
Trace Port
(SWO)
Cortex-M4F System Component Details
The Cortex-M4F includes the following system components:
■ SysTick
A 24-bit count-down timer that can be used as a Real-Time Operating System (RTOS) tick timer
or as a simple counter (see “System Timer (SysTick)” on page 119).
■ Nested Vectored Interrupt Controller (NVIC)
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An embedded interrupt controller that supports low latency interrupt processing (see “Nested
Vectored Interrupt Controller (NVIC)” on page 120).
■ System Control Block (SCB)
The programming model interface to the processor. The SCB provides system implementation
information and system control, including configuration, control, and reporting of system exceptions
(see “System Control Block (SCB)” on page 121).
■ Memory Protection Unit (MPU)
Improves system reliability by defining the memory attributes for different memory regions. The
MPU provides up to eight different regions and an optional predefined background region (see
“Memory Protection Unit (MPU)” on page 121).
■ Floating-Point Unit (FPU)
Fully supports single-precision add, subtract, multiply, divide, multiply and accumulate, and
square-root operations. It also provides conversions between fixed-point and floating-point data
formats, and floating-point constant instructions (see “Floating-Point Unit (FPU)” on page 126).
2.3
Programming Model
This section describes the Cortex-M4F programming model. In addition to the individual core register
descriptions, information about the processor modes and privilege levels for software execution and
stacks is included.
2.3.1
Processor Mode and Privilege Levels for Software Execution
The Cortex-M4F has two modes of operation:
■ Thread mode
Used to execute application software. The processor enters Thread mode when it comes out of
reset.
■ Handler mode
Used to handle exceptions. When the processor has finished exception processing, it returns to
Thread mode.
In addition, the Cortex-M4F has two privilege levels:
■ Unprivileged
In this mode, software has the following restrictions:
– Limited access to the MSR and MRS instructions and no use of the CPS instruction
– No access to the system timer, NVIC, or system control block
– Possibly restricted access to memory or peripherals
■ Privileged
In this mode, software can use all the instructions and has access to all resources.
In Thread mode, the CONTROL register (see page 83) controls whether software execution is
privileged or unprivileged. In Handler mode, software execution is always privileged.
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Only privileged software can write to the CONTROL register to change the privilege level for software
execution in Thread mode. Unprivileged software can use the SVC instruction to make a supervisor
call to transfer control to privileged software.
2.3.2
Stacks
The processor uses a full descending stack, meaning that the stack pointer indicates the last stacked
item on the memory. When the processor pushes a new item onto the stack, it decrements the stack
pointer and then writes the item to the new memory location. The processor implements two stacks:
the main stack and the process stack, with a pointer for each held in independent registers (see the
SP register on page 73).
In Thread mode, the CONTROL register (see page 83) controls whether the processor uses the
main stack or the process stack. In Handler mode, the processor always uses the main stack. The
options for processor operations are shown in Table 2-1 on page 69.
Table 2-1. Summary of Processor Mode, Privilege Level, and Stack Use
Processor Mode
Use
Privilege Level
Thread
Applications
Privileged or unprivileged
Handler
Exception handlers
Always privileged
Stack Used
a
Main stack or process stack
a
Main stack
a. See CONTROL (page 83).
2.3.3
Register Map
Figure 2-3 on page 70 shows the Cortex-M4F register set. Table 2-2 on page 70 lists the Core
registers. The core registers are not memory mapped and are accessed by register name, so the
base address is n/a (not applicable) and there is no offset.
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Figure 2-3. Cortex-M4F Register Set
R0
R1
R2
R3
Low registers
R4
R5
General-purpose registers
R6
R7
R8
R9
High registers
R10
R11
R12
Stack Pointer
SP (R13)
Link Register
LR (R14)
Program Counter
PC (R15)
PSP‡
PSR
MSP‡
‡
Banked version of SP
Program status register
PRIMASK
FAULTMASK
Exception mask registers
Special registers
BASEPRI
CONTROL
CONTROL register
Table 2-2. Processor Register Map
Offset
Name
Type
Reset
Description
See
page
-
R0
RW
-
Cortex General-Purpose Register 0
72
-
R1
RW
-
Cortex General-Purpose Register 1
72
-
R2
RW
-
Cortex General-Purpose Register 2
72
-
R3
RW
-
Cortex General-Purpose Register 3
72
-
R4
RW
-
Cortex General-Purpose Register 4
72
-
R5
RW
-
Cortex General-Purpose Register 5
72
-
R6
RW
-
Cortex General-Purpose Register 6
72
-
R7
RW
-
Cortex General-Purpose Register 7
72
-
R8
RW
-
Cortex General-Purpose Register 8
72
-
R9
RW
-
Cortex General-Purpose Register 9
72
-
R10
RW
-
Cortex General-Purpose Register 10
72
-
R11
RW
-
Cortex General-Purpose Register 11
72
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Table 2-2. Processor Register Map (continued)
Offset
Name
Type
Reset
Description
See
page
-
R12
RW
-
Cortex General-Purpose Register 12
72
-
SP
RW
-
Stack Pointer
73
-
LR
RW
0xFFFF.FFFF
Link Register
74
-
PC
RW
-
Program Counter
75
-
PSR
RW
0x0100.0000
Program Status Register
76
-
PRIMASK
RW
0x0000.0000
Priority Mask Register
80
-
FAULTMASK
RW
0x0000.0000
Fault Mask Register
81
-
BASEPRI
RW
0x0000.0000
Base Priority Mask Register
82
-
CONTROL
RW
0x0000.0000
Control Register
83
-
FPSC
RW
-
Floating-Point Status Control
85
2.3.4
Register Descriptions
This section lists and describes the Cortex-M4F registers, in the order shown in Figure
2-3 on page 70. The core registers are not memory mapped and are accessed by register name
rather than offset.
Note:
The register type shown in the register descriptions refers to type during program execution
in Thread mode and Handler mode. Debug access can differ.
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Register 1: Cortex General-Purpose Register 0 (R0)
Register 2: Cortex General-Purpose Register 1 (R1)
Register 3: Cortex General-Purpose Register 2 (R2)
Register 4: Cortex General-Purpose Register 3 (R3)
Register 5: Cortex General-Purpose Register 4 (R4)
Register 6: Cortex General-Purpose Register 5 (R5)
Register 7: Cortex General-Purpose Register 6 (R6)
Register 8: Cortex General-Purpose Register 7 (R7)
Register 9: Cortex General-Purpose Register 8 (R8)
Register 10: Cortex General-Purpose Register 9 (R9)
Register 11: Cortex General-Purpose Register 10 (R10)
Register 12: Cortex General-Purpose Register 11 (R11)
Register 13: Cortex General-Purpose Register 12 (R12)
The Rn registers are 32-bit general-purpose registers for data operations and can be accessed
from either privileged or unprivileged mode.
Cortex General-Purpose Register 0 (R0)
Type RW, reset 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
DATA
Type
Reset
DATA
Type
Reset
Bit/Field
Name
Type
Reset
31:0
DATA
RW
-
Description
Register data.
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Register 14: Stack Pointer (SP)
The Stack Pointer (SP) is register R13. In Thread mode, the function of this register changes
depending on the ASP bit in the Control Register (CONTROL) register. When the ASP bit is clear,
this register is the Main Stack Pointer (MSP). When the ASP bit is set, this register is the Process
Stack Pointer (PSP). On reset, the ASP bit is clear, and the processor loads the MSP with the value
from address 0x0000.0000. The MSP can only be accessed in privileged mode; the PSP can be
accessed in either privileged or unprivileged mode.
Stack Pointer (SP)
Type RW, reset 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
SP
Type
Reset
SP
Type
Reset
Bit/Field
Name
Type
Reset
31:0
SP
RW
-
Description
This field is the address of the stack pointer.
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Register 15: Link Register (LR)
The Link Register (LR) is register R14, and it stores the return information for subroutines, function
calls, and exceptions. The Link Register can be accessed from either privileged or unprivileged
mode.
EXC_RETURN is loaded into the LR on exception entry. See Table 2-10 on page 107 for the values
and description.
Link Register (LR)
Type RW, reset 0xFFFF.FFFF
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
7
6
5
4
3
2
1
0
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
LINK
Type
Reset
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
15
14
13
12
11
10
9
8
LINK
Type
Reset
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
Bit/Field
Name
Type
31:0
LINK
RW
RW
1
Reset
RW
1
Description
0xFFFF.FFFF This field is the return address.
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Register 16: Program Counter (PC)
The Program Counter (PC) is register R15, and it contains the current program address. On reset,
the processor loads the PC with the value of the reset vector, which is at address 0x0000.0004. Bit
0 of the reset vector is loaded into the THUMB bit of the EPSR at reset and must be 1. The PC register
can be accessed in either privileged or unprivileged mode.
Program Counter (PC)
Type RW, reset 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
PC
Type
Reset
PC
Type
Reset
Bit/Field
Name
Type
Reset
31:0
PC
RW
-
Description
This field is the current program address.
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Register 17: Program Status Register (PSR)
Note:
This register is also referred to as xPSR.
The Program Status Register (PSR) has three functions, and the register bits are assigned to the
different functions:
■ Application Program Status Register (APSR), bits 31:27, bits 19:16
■ Execution Program Status Register (EPSR), bits 26:24, 15:10
■ Interrupt Program Status Register (IPSR), bits 7:0
The PSR, IPSR, and EPSR registers can only be accessed in privileged mode; the APSR register
can be accessed in either privileged or unprivileged mode.
APSR contains the current state of the condition flags from previous instruction executions.
EPSR contains the Thumb state bit and the execution state bits for the If-Then (IT) instruction or
the Interruptible-Continuable Instruction (ICI) field for an interrupted load multiple or store multiple
instruction. Attempts to read the EPSR directly through application software using the MSR instruction
always return zero. Attempts to write the EPSR using the MSR instruction in application software
are always ignored. Fault handlers can examine the EPSR value in the stacked PSR to determine
the operation that faulted (see “Exception Entry and Return” on page 104).
IPSR contains the exception type number of the current Interrupt Service Routine (ISR).
These registers can be accessed individually or as a combination of any two or all three registers,
using the register name as an argument to the MSR or MRS instructions. For example, all of the
registers can be read using PSR with the MRS instruction, or APSR only can be written to using
APSR with the MSR instruction. page 76 shows the possible register combinations for the PSR. See
the MRS and MSR instruction descriptions in the Cortex™-M4 instruction set chapter in the ARM®
Cortex™-M4 Devices Generic User Guide (literature number ARM DUI 0553A) for more information
about how to access the program status registers.
Table 2-3. PSR Register Combinations
Register
Type
PSR
RW
Combination
APSR, EPSR, and IPSR
IEPSR
RO
EPSR and IPSR
a, b
a
APSR and IPSR
b
APSR and EPSR
IAPSR
RW
EAPSR
RW
a. The processor ignores writes to the IPSR bits.
b. Reads of the EPSR bits return zero, and the processor ignores writes to these bits.
Program Status Register (PSR)
Type RW, reset 0x0100.0000
Type
Reset
31
30
29
28
27
N
Z
C
V
Q
26
RW
0
RW
0
RW
0
RW
0
RW
0
RO
0
RO
0
RO
1
RO
0
RO
0
RO
0
RO
0
RW
0
15
14
13
12
11
10
9
8
7
6
5
4
ICI / IT
Type
Reset
RO
0
RO
0
RO
0
25
ICI / IT
24
23
22
THUMB
21
RO
0
RO
0
RO
0
RO
0
19
18
17
16
RW
0
RW
0
RW
0
3
2
1
0
RO
0
RO
0
RO
0
RO
0
GE
reserved
RO
0
20
reserved
ISRNUM
RO
0
RO
0
76
RO
0
RO
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Bit/Field
Name
Type
Reset
31
N
RW
0
Description
APSR Negative or Less Flag
Value Description
1
The previous operation result was negative or less than.
0
The previous operation result was positive, zero, greater than,
or equal.
The value of this bit is only meaningful when accessing PSR or APSR.
30
Z
RW
0
APSR Zero Flag
Value Description
1
The previous operation result was zero.
0
The previous operation result was non-zero.
The value of this bit is only meaningful when accessing PSR or APSR.
29
C
RW
0
APSR Carry or Borrow Flag
Value Description
1
The previous add operation resulted in a carry bit or the previous
subtract operation did not result in a borrow bit.
0
The previous add operation did not result in a carry bit or the
previous subtract operation resulted in a borrow bit.
The value of this bit is only meaningful when accessing PSR or APSR.
28
V
RW
0
APSR Overflow Flag
Value Description
1
The previous operation resulted in an overflow.
0
The previous operation did not result in an overflow.
The value of this bit is only meaningful when accessing PSR or APSR.
27
Q
RW
0
APSR DSP Overflow and Saturation Flag
Value Description
1
DSP Overflow or saturation has occurred when using a SIMD
instruction.
0
DSP overflow or saturation has not occurred since reset or since
the bit was last cleared.
The value of this bit is only meaningful when accessing PSR or APSR.
This bit is cleared by software using an MRS instruction.
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Bit/Field
Name
Type
Reset
26:25
ICI / IT
RO
0x0
Description
EPSR ICI / IT status
These bits, along with bits 15:10, contain the Interruptible-Continuable
Instruction (ICI) field for an interrupted load multiple or store multiple
instruction or the execution state bits of the IT instruction.
When EPSR holds the ICI execution state, bits 26:25 are zero.
The If-Then block contains up to four instructions following an IT
instruction. Each instruction in the block is conditional. The conditions
for the instructions are either all the same, or some can be the inverse
of others. See the Cortex™-M4 instruction set chapter in the ARM®
Cortex™-M4 Devices Generic User Guide (literature number ARM DUI
0553A) for more information.
The value of this field is only meaningful when accessing PSR or EPSR.
Note that these EPSR bits cannot be accessed using MRS and MSR
instructions but the definitions are provided to allow the stacked (E)PSR
value to be decoded within an exception handler.
24
THUMB
RO
1
EPSR Thumb State
This bit indicates the Thumb state and should always be set.
The following can clear the THUMB bit:
■
The BLX, BX and POP{PC} instructions
■
Restoration from the stacked xPSR value on an exception return
■
Bit 0 of the vector value on an exception entry or reset
Attempting to execute instructions when this bit is clear results in a fault
or lockup. See “Lockup” on page 109 for more information.
The value of this bit is only meaningful when accessing PSR or EPSR.
23:20
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
19:16
GE
RW
0x0
Greater Than or Equal Flags
See the description of the SEL instruction in the Cortex™-M4 instruction
set chapter in the ARM® Cortex™-M4 Devices Generic User Guide
(literature number ARM DUI 0553A) for more information.
The value of this field is only meaningful when accessing PSR or APSR.
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Bit/Field
Name
Type
Reset
15:10
ICI / IT
RO
0x0
Description
EPSR ICI / IT status
These bits, along with bits 26:25, contain the Interruptible-Continuable
Instruction (ICI) field for an interrupted load multiple or store multiple
instruction or the execution state bits of the IT instruction.
When an interrupt occurs during the execution of an LDM, STM, PUSH
POP, VLDM, VSTM, VPUSH, or VPOP instruction, the processor stops the
load multiple or store multiple instruction operation temporarily and
stores the next register operand in the multiple operation to bits 15:12.
After servicing the interrupt, the processor returns to the register pointed
to by bits 15:12 and resumes execution of the multiple load or store
instruction. When EPSR holds the ICI execution state, bits 11:10 are
zero.
The If-Then block contains up to four instructions following a 16-bit IT
instruction. Each instruction in the block is conditional. The conditions
for the instructions are either all the same, or some can be the inverse
of others. See the Cortex™-M4 instruction set chapter in the ARM®
Cortex™-M4 Devices Generic User Guide (literature number ARM DUI
0553A) for more information.
The value of this field is only meaningful when accessing PSR or EPSR.
9:8
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
ISRNUM
RO
0x00
IPSR ISR Number
This field contains the exception type number of the current Interrupt
Service Routine (ISR).
Value
Description
0x00
Thread mode
0x01
Reserved
0x02
NMI
0x03
Hard fault
0x04
Memory management fault
0x05
Bus fault
0x06
Usage fault
0x07-0x0A Reserved
0x0B
SVCall
0x0C
Reserved for Debug
0x0D
Reserved
0x0E
PendSV
0x0F
SysTick
0x10
Interrupt Vector 0
0x11
Interrupt Vector 1
...
...
0x9A
Interrupt Vector 138
See “Exception Types” on page 97 for more information.
The value of this field is only meaningful when accessing PSR or IPSR.
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Register 18: Priority Mask Register (PRIMASK)
The PRIMASK register prevents activation of all exceptions with programmable priority. Reset,
non-maskable interrupt (NMI), and hard fault are the only exceptions with fixed priority. Exceptions
should be disabled when they might impact the timing of critical tasks. This register is only accessible
in privileged mode. The MSR and MRS instructions are used to access the PRIMASK register, and
the CPS instruction may be used to change the value of the PRIMASK register. See the Cortex™-M4
instruction set chapter in the ARM® Cortex™-M4 Devices Generic User Guide (literature number
ARM DUI 0553A) for more information on these instructions. For more information on exception
priority levels, see “Exception Types” on page 97.
Priority Mask Register (PRIMASK)
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:1
reserved
RO
0x0000.000
0
PRIMASK
RW
0
RO
0
PRIMASK
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Priority Mask
Value Description
1
Prevents the activation of all exceptions with configurable
priority.
0
No effect.
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Register 19: Fault Mask Register (FAULTMASK)
The FAULTMASK register prevents activation of all exceptions except for the Non-Maskable Interrupt
(NMI). Exceptions should be disabled when they might impact the timing of critical tasks. This register
is only accessible in privileged mode. The MSR and MRS instructions are used to access the
FAULTMASK register, and the CPS instruction may be used to change the value of the FAULTMASK
register. See the Cortex™-M4 instruction set chapter in the ARM® Cortex™-M4 Devices Generic
User Guide (literature number ARM DUI 0553A) for more information on these instructions. For
more information on exception priority levels, see “Exception Types” on page 97.
Fault Mask Register (FAULTMASK)
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:1
reserved
RO
0x0000.000
0
FAULTMASK
RW
0
RO
0
FAULTMASK
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Fault Mask
Value Description
1
Prevents the activation of all exceptions except for NMI.
0
No effect.
The processor clears the FAULTMASK bit on exit from any exception
handler except the NMI handler.
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Register 20: Base Priority Mask Register (BASEPRI)
The BASEPRI register defines the minimum priority for exception processing. When BASEPRI is
set to a nonzero value, it prevents the activation of all exceptions with the same or lower priority
level as the BASEPRI value. Exceptions should be disabled when they might impact the timing of
critical tasks. This register is only accessible in privileged mode. For more information on exception
priority levels, see “Exception Types” on page 97.
Base Priority Mask Register (BASEPRI)
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RW
0
RW
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
BASEPRI
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:5
BASEPRI
RW
0x0
RW
0
reserved
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Base Priority
Any exception that has a programmable priority level with the same or
lower priority as the value of this field is masked. The PRIMASK register
can be used to mask all exceptions with programmable priority levels.
Higher priority exceptions have lower priority levels.
Value Description
4:0
reserved
RO
0x0
0x0
All exceptions are unmasked.
0x1
All exceptions with priority level 1-7 are masked.
0x2
All exceptions with priority level 2-7 are masked.
0x3
All exceptions with priority level 3-7 are masked.
0x4
All exceptions with priority level 4-7 are masked.
0x5
All exceptions with priority level 5-7 are masked.
0x6
All exceptions with priority level 6-7 are masked.
0x7
All exceptions with priority level 7 are masked.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Register 21: Control Register (CONTROL)
The CONTROL register controls the stack used and the privilege level for software execution when
the processor is in Thread mode, and indicates whether the FPU state is active. This register is only
accessible in privileged mode.
Handler mode always uses the MSP, so the processor ignores explicit writes to the ASP bit of the
CONTROL register when in Handler mode. The exception entry and return mechanisms automatically
update the CONTROL register based on the EXC_RETURN value (see Table 2-10 on page 107).
In an OS environment, threads running in Thread mode should use the process stack and the kernel
and exception handlers should use the main stack. By default, Thread mode uses the MSP. To
switch the stack pointer used in Thread mode to the PSP, either use the MSR instruction to set the
ASP bit, as detailed in the Cortex™-M4 instruction set chapter in the ARM® Cortex™-M4 Devices
Generic User Guide (literature number ARM DUI 0553A), or perform an exception return to Thread
mode with the appropriate EXC_RETURN value, as shown in Table 2-10 on page 107.
Note:
When changing the stack pointer, software must use an ISB instruction immediately after
the MSR instruction, ensuring that instructions after the ISB execute use the new stack
pointer. See the Cortex™-M4 instruction set chapter in the ARM® Cortex™-M4 Devices
Generic User Guide (literature number ARM DUI 0553A).
Control Register (CONTROL)
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
FPCA
ASP
TMPL
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
RW
0
RW
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
Bit/Field
Name
Type
Reset
31:3
reserved
RO
0x0000.000
2
FPCA
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Floating-Point Context Active
Value Description
1
Floating-point context active
0
No floating-point context active
The Cortex-M4F uses this bit to determine whether to preserve
floating-point state when processing an exception.
Important:
Two bits control when FPCA can be enabled: the ASPEN
bit in the Floating-Point Context Control (FPCC)
register and the DISFPCA bit in the Auxiliary Control
(ACTLR) register.
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Bit/Field
Name
Type
Reset
1
ASP
RW
0
Description
Active Stack Pointer
Value Description
1
The PSP is the current stack pointer.
0
The MSP is the current stack pointer
In Handler mode, this bit reads as zero and ignores writes. The
Cortex-M4F updates this bit automatically on exception return.
0
TMPL
RW
0
Thread Mode Privilege Level
Value Description
1
Unprivileged software can be executed in Thread mode.
0
Only privileged software can be executed in Thread mode.
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Register 22: Floating-Point Status Control (FPSC)
The FPSC register provides all necessary user-level control of the floating-point system.
Floating-Point Status Control (FPSC)
Type RW, reset 31
Type
Reset
30
29
28
27
26
25
24
22
21
20
19
RMODE
18
17
16
N
Z
C
V
reserved
AHP
DN
FZ
RW
-
RW
-
RW
-
RW
-
RO
0
RW
-
RW
-
RW
-
RW
-
RW
-
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
IXC
UFC
OFC
DZC
IOC
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW
-
RW
-
RW
-
RW
-
RW
-
reserved
Type
Reset
23
IDC
RO
0
Bit/Field
Name
Type
Reset
31
N
RW
-
RW
-
reserved
reserved
RO
0
RO
0
Description
Negative Condition Code Flag
Floating-point comparison operations update this condition code flag.
30
Z
RW
-
Zero Condition Code Flag
Floating-point comparison operations update this condition code flag.
29
C
RW
-
Carry Condition Code Flag
Floating-point comparison operations update this condition code flag.
28
V
RW
-
Overflow Condition Code Flag
Floating-point comparison operations update this condition code flag.
27
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
26
AHP
RW
-
Alternative Half-Precision
When set, alternative half-precision format is selected. When clear,
IEEE half-precision format is selected.
The AHP bit in the FPDSC register holds the default value for this bit.
25
DN
RW
-
Default NaN Mode
When set, any operation involving one or more NaNs returns the Default
NaN. When clear, NaN operands propagate through to the output of a
floating-point operation.
The DN bit in the FPDSC register holds the default value for this bit.
24
FZ
RW
-
Flush-to-Zero Mode
When set, Flush-to-Zero mode is enabled. When clear, Flush-to-Zero
mode is disabled and the behavior of the floating-point system is fully
compliant with the IEEE 754 standard.
The FZ bit in the FPDSC register holds the default value for this bit.
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Bit/Field
Name
Type
Reset
23:22
RMODE
RW
-
Description
Rounding Mode
The specified rounding mode is used by almost all floating-point
instructions.
The RMODE bit in the FPDSC register holds the default value for this bit.
Value Description
21:8
reserved
RO
0x0
7
IDC
RW
-
0x0
Round to Nearest (RN) mode
0x1
Round towards Plus Infinity (RP) mode
0x2
Round towards Minus Infinity (RM) mode
0x3
Round towards Zero (RZ) mode
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Input Denormal Cumulative Exception
When set, indicates this exception has occurred since 0 was last written
to this bit.
6:5
reserved
RO
0x0
4
IXC
RW
-
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Inexact Cumulative Exception
When set, indicates this exception has occurred since 0 was last written
to this bit.
3
UFC
RW
-
Underflow Cumulative Exception
When set, indicates this exception has occurred since 0 was last written
to this bit.
2
OFC
RW
-
Overflow Cumulative Exception
When set, indicates this exception has occurred since 0 was last written
to this bit.
1
DZC
RW
-
Division by Zero Cumulative Exception
When set, indicates this exception has occurred since 0 was last written
to this bit.
0
IOC
RW
-
Invalid Operation Cumulative Exception
When set, indicates this exception has occurred since 0 was last written
to this bit.
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2.3.5
Exceptions and Interrupts
The Cortex-M4F processor supports interrupts and system exceptions. The processor and the
Nested Vectored Interrupt Controller (NVIC) prioritize and handle all exceptions. An exception
changes the normal flow of software control. The processor uses Handler mode to handle all
exceptions except for reset. See “Exception Entry and Return” on page 104 for more information.
The NVIC registers control interrupt handling. See “Nested Vectored Interrupt Controller
(NVIC)” on page 120 for more information.
2.3.6
Data Types
The Cortex-M4F supports 32-bit words, 16-bit halfwords, and 8-bit bytes. The processor also supports
64-bit data transfer instructions. All instruction and data memory accesses are little endian. See
“Memory Regions, Types and Attributes” on page 90 for more information.
2.4
Memory Model
This section describes the processor memory map, the behavior of memory accesses, and the
bit-banding features. The processor has a fixed memory map that provides up to 4 GB of addressable
memory.
The memory map for the TM4C123BH6PGE controller is provided in Table 2-4 on page 87. In this
manual, register addresses are given as a hexadecimal increment, relative to the module's base
address as shown in the memory map.
The regions for SRAM and peripherals include bit-band regions. Bit-banding provides atomic
operations to bit data (see “Bit-Banding” on page 92).
The processor reserves regions of the Private peripheral bus (PPB) address range for core peripheral
registers (see “Cortex-M4 Peripherals” on page 118).
Note:
Within the memory map, attempts to read or write addresses in reserved spaces result in
a bus fault. In addition, attempts to write addresses in the flash range also result in a bus
fault.
Table 2-4. Memory Map
Start
End
Description
For details,
see page ...
0x0000.0000
0x0003.FFFF
On-chip Flash
538
0x0004.0000
0x1FFF.FFFF
Reserved
-
0x2000.0000
0x2000.7FFF
Bit-banded on-chip SRAM
523
0x2000.8000
0x21FF.FFFF
Reserved
-
0x2200.0000
0x220F.FFFF
Bit-band alias of bit-banded on-chip SRAM starting at
0x2000.0000
523
0x2210.0000
0x3FFF.FFFF
Reserved
-
0x4000.0000
0x4000.0FFF
Watchdog timer 0
785
0x4000.1000
0x4000.1FFF
Watchdog timer 1
785
0x4000.2000
0x4000.3FFF
Reserved
-
0x4000.4000
0x4000.4FFF
GPIO Port A
658
0x4000.5000
0x4000.5FFF
GPIO Port B
658
Memory
Peripherals
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Table 2-4. Memory Map (continued)
Start
End
Description
For details,
see page ...
0x4000.6000
0x4000.6FFF
GPIO Port C
658
0x4000.7000
0x4000.7FFF
GPIO Port D
658
0x4000.8000
0x4000.8FFF
SSI0
984
0x4000.9000
0x4000.9FFF
SSI1
984
0x4000.A000
0x4000.AFFF
SSI2
984
0x4000.B000
0x4000.BFFF
SSI3
984
0x4000.C000
0x4000.CFFF
UART0
919
0x4000.D000
0x4000.DFFF
UART1
919
0x4000.E000
0x4000.EFFF
UART2
919
0x4000.F000
0x4000.FFFF
UART3
919
0x4001.0000
0x4001.0FFF
UART4
919
0x4001.1000
0x4001.1FFF
UART5
919
0x4001.2000
0x4001.2FFF
UART6
919
0x4001.3000
0x4001.3FFF
UART7
919
0x4001.4000
0x4001.FFFF
Reserved
-
0x4002.0FFF
I2C 0
1034
0x4002.1FFF
I2C
1
1034
0x4002.2000
0x4002.2FFF
I2C
2
1034
0x4002.3000
0x4002.3FFF
I2C 3
1034
0x4002.4000
0x4002.4FFF
GPIO Port E
658
0x4002.5000
0x4002.5FFF
GPIO Port F
658
0x4002.6000
0x4002.6FFF
GPIO Port G
658
0x4002.7000
0x4002.7FFF
GPIO Port H
658
0x4002.8000
0x4002.8FFF
PWM 0
1143
0x4002.9000
0x4002.9FFF
PWM 1
1143
0x4002.A000
0x4002.BFFF
Reserved
-
0x4002.C000
0x4002.CFFF
QEI0
1217
0x4002.D000
0x4002.DFFF
QEI1
1217
0x4002.E000
0x4002.FFFF
Reserved
-
0x4003.0000
0x4003.0FFF
16/32-bit Timer 0
734
0x4003.1000
0x4003.1FFF
16/32-bit Timer 1
734
0x4003.2000
0x4003.2FFF
16/32-bit Timer 2
734
0x4003.3000
0x4003.3FFF
16/32-bit Timer 3
734
0x4003.4000
0x4003.4FFF
16/32-bit Timer 4
734
0x4003.5000
0x4003.5FFF
16/32-bit Timer 5
734
0x4003.6000
0x4003.6FFF
32/64-bit Timer 0
734
0x4003.7000
0x4003.7FFF
32/64-bit Timer 1
734
0x4003.8000
0x4003.8FFF
ADC0
828
0x4003.9000
0x4003.9FFF
ADC1
828
0x4003.A000
0x4003.BFFF
Reserved
-
Peripherals
0x4002.0000
0x4002.1000
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Table 2-4. Memory Map (continued)
Start
End
Description
For details,
see page ...
0x4003.C000
0x4003.CFFF
Analog Comparators
1122
0x4003.D000
0x4003.DFFF
GPIO Port J
658
0x4003.E000
0x4003.FFFF
Reserved
-
0x4004.0000
0x4004.0FFF
CAN0 Controller
1084
0x4004.1000
0x4004.1FFF
CAN1 Controller
1084
0x4004.2000
0x4004.BFFF
Reserved
-
0x4004.C000
0x4004.CFFF
32/64-bit Timer 2
734
0x4004.D000
0x4004.DFFF
32/64-bit Timer 3
734
0x4004.E000
0x4004.EFFF
32/64-bit Timer 4
734
0x4004.F000
0x4004.FFFF
32/64-bit Timer 5
734
0x4005.0000
0x4005.7FFF
Reserved
-
0x4005.8000
0x4005.8FFF
GPIO Port A (AHB aperture)
658
0x4005.9000
0x4005.9FFF
GPIO Port B (AHB aperture)
658
0x4005.A000
0x4005.AFFF
GPIO Port C (AHB aperture)
658
0x4005.B000
0x4005.BFFF
GPIO Port D (AHB aperture)
658
0x4005.C000
0x4005.CFFF
GPIO Port E (AHB aperture)
658
0x4005.D000
0x4005.DFFF
GPIO Port F (AHB aperture)
658
0x4005.E000
0x4005.EFFF
GPIO Port G (AHB aperture)
658
0x4005.F000
0x4005.FFFF
GPIO Port H (AHB aperture)
658
0x4006.0000
0x4006.0FFF
GPIO Port J (AHB aperture)
658
0x4006.1000
0x4006.1FFF
GPIO Port K (AHB aperture)
658
0x4006.2000
0x4006.2FFF
GPIO Port L (AHB aperture)
658
0x4006.3000
0x4006.3FFF
GPIO Port M (AHB aperture)
658
0x4006.4000
0x4006.4FFF
GPIO Port N (AHB aperture)
658
0x4006.5000
0x4006.5FFF
GPIO Port P (AHB aperture)
658
0x4006.6000
0x400A.EFFF
Reserved
-
0x400A.F000
0x400A.FFFF
EEPROM and Key Locker
538
0x400B.0000
0x400B.FFFF
Reserved
-
0x400C.0FFF
I2C
4
1034
5
1034
0x400C.0000
0x400C.1000
0x400C.1FFF
I2C
0x400C.2000
0x400F.8FFF
Reserved
-
0x400F.9000
0x400F.9FFF
System Exception Module
483
0x400F.A000
0x400F.BFFF
Reserved
-
0x400F.C000
0x400F.CFFF
Hibernation Module
503
0x400F.D000
0x400F.DFFF
Flash memory control
538
0x400F.E000
0x400F.EFFF
System control
227
0x400F.F000
0x400F.FFFF
µDMA
604
0x4010.0000
0x41FF.FFFF
Reserved
-
0x4200.0000
0x43FF.FFFF
Bit-banded alias of 0x4000.0000 through 0x400F.FFFF
-
0x4400.0000
0xDFFF.FFFF
Reserved
-
Private Peripheral Bus
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Table 2-4. Memory Map (continued)
Start
End
Description
For details,
see page ...
0xE000.0000
0xE000.0FFF
Instrumentation Trace Macrocell (ITM)
66
0xE000.1000
0xE000.1FFF
Data Watchpoint and Trace (DWT)
66
0xE000.2000
0xE000.2FFF
Flash Patch and Breakpoint (FPB)
66
0xE000.3000
0xE000.DFFF
Reserved
-
0xE000.E000
0xE000.EFFF
Cortex-M4F Peripherals (SysTick, NVIC, MPU, FPU and SCB) 130
0xE000.F000
0xE003.FFFF
Reserved
-
0xE004.0000
0xE004.0FFF
Trace Port Interface Unit (TPIU)
67
0xE004.1000
0xE004.1FFF
Embedded Trace Macrocell (ETM)
66
0xE004.2000
0xFFFF.FFFF
Reserved
-
2.4.1
Memory Regions, Types and Attributes
The memory map and the programming of the MPU split the memory map into regions. Each region
has a defined memory type, and some regions have additional memory attributes. The memory
type and attributes determine the behavior of accesses to the region.
The memory types are:
■ Normal: The processor can re-order transactions for efficiency and perform speculative reads.
■ Device: The processor preserves transaction order relative to other transactions to Device or
Strongly Ordered memory.
■ Strongly Ordered: The processor preserves transaction order relative to all other transactions.
The different ordering requirements for Device and Strongly Ordered memory mean that the memory
system can buffer a write to Device memory but must not buffer a write to Strongly Ordered memory.
An additional memory attribute is Execute Never (XN), which means the processor prevents
instruction accesses. A fault exception is generated only on execution of an instruction executed
from an XN region.
2.4.2
Memory System Ordering of Memory Accesses
For most memory accesses caused by explicit memory access instructions, the memory system
does not guarantee that the order in which the accesses complete matches the program order of
the instructions, providing the order does not affect the behavior of the instruction sequence. Normally,
if correct program execution depends on two memory accesses completing in program order,
software must insert a memory barrier instruction between the memory access instructions (see
“Software Ordering of Memory Accesses” on page 91).
However, the memory system does guarantee ordering of accesses to Device and Strongly Ordered
memory. For two memory access instructions A1 and A2, if both A1 and A2 are accesses to either
Device or Strongly Ordered memory, and if A1 occurs before A2 in program order, A1 is always
observed before A2.
2.4.3
Behavior of Memory Accesses
Table 2-5 on page 91 shows the behavior of accesses to each region in the memory map. See
“Memory Regions, Types and Attributes” on page 90 for more information on memory types and
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the XN attribute. Tiva™ C Series devices may have reserved memory areas within the address
ranges shown below (refer to Table 2-4 on page 87 for more information).
Table 2-5. Memory Access Behavior
Address Range
Memory Region
Memory Type
Execute
Never
(XN)
Description
0x0000.0000 - 0x1FFF.FFFF Code
Normal
-
This executable region is for program code.
Data can also be stored here.
0x2000.0000 - 0x3FFF.FFFF SRAM
Normal
-
This executable region is for data. Code
can also be stored here. This region
includes bit band and bit band alias areas
(see Table 2-6 on page 93).
0x4000.0000 - 0x5FFF.FFFF Peripheral
Device
XN
This region includes bit band and bit band
alias areas (see Table 2-7 on page 93).
0x6000.0000 - 0x9FFF.FFFF External RAM
Normal
-
This executable region is for data.
0xA000.0000 - 0xDFFF.FFFF External device
Device
XN
This region is for external device memory.
0xE000.0000- 0xE00F.FFFF Private peripheral
bus
Strongly
Ordered
XN
This region includes the NVIC, system
timer, and system control block.
0xE010.0000- 0xFFFF.FFFF Reserved
-
-
-
The Code, SRAM, and external RAM regions can hold programs. However, it is recommended that
programs always use the Code region because the Cortex-M4F has separate buses that can perform
instruction fetches and data accesses simultaneously.
The MPU can override the default memory access behavior described in this section. For more
information, see “Memory Protection Unit (MPU)” on page 121.
The Cortex-M4F prefetches instructions ahead of execution and speculatively prefetches from
branch target addresses.
2.4.4
Software Ordering of Memory Accesses
The order of instructions in the program flow does not always guarantee the order of the
corresponding memory transactions for the following reasons:
■ The processor can reorder some memory accesses to improve efficiency, providing this does
not affect the behavior of the instruction sequence.
■ The processor has multiple bus interfaces.
■ Memory or devices in the memory map have different wait states.
■ Some memory accesses are buffered or speculative.
“Memory System Ordering of Memory Accesses” on page 90 describes the cases where the memory
system guarantees the order of memory accesses. Otherwise, if the order of memory accesses is
critical, software must include memory barrier instructions to force that ordering. The Cortex-M4F
has the following memory barrier instructions:
■ The Data Memory Barrier (DMB) instruction ensures that outstanding memory transactions
complete before subsequent memory transactions.
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■ The Data Synchronization Barrier (DSB) instruction ensures that outstanding memory transactions
complete before subsequent instructions execute.
■ The Instruction Synchronization Barrier (ISB) instruction ensures that the effect of all completed
memory transactions is recognizable by subsequent instructions.
Memory barrier instructions can be used in the following situations:
■ MPU programming
– If the MPU settings are changed and the change must be effective on the very next instruction,
use a DSB instruction to ensure the effect of the MPU takes place immediately at the end of
context switching.
– Use an ISB instruction to ensure the new MPU setting takes effect immediately after
programming the MPU region or regions, if the MPU configuration code was accessed using
a branch or call. If the MPU configuration code is entered using exception mechanisms, then
an ISB instruction is not required.
■ Vector table
If the program changes an entry in the vector table and then enables the corresponding exception,
use a DMB instruction between the operations. The DMB instruction ensures that if the exception
is taken immediately after being enabled, the processor uses the new exception vector.
■ Self-modifying code
If a program contains self-modifying code, use an ISB instruction immediately after the code
modification in the program. The ISB instruction ensures subsequent instruction execution uses
the updated program.
■ Memory map switching
If the system contains a memory map switching mechanism, use a DSB instruction after switching
the memory map in the program. The DSB instruction ensures subsequent instruction execution
uses the updated memory map.
■ Dynamic exception priority change
When an exception priority has to change when the exception is pending or active, use DSB
instructions after the change. The change then takes effect on completion of the DSB instruction.
Memory accesses to Strongly Ordered memory, such as the System Control Block, do not require
the use of DMB instructions.
For more information on the memory barrier instructions, see the Cortex™-M4 instruction set chapter
in the ARM® Cortex™-M4 Devices Generic User Guide (literature number ARM DUI 0553A).
2.4.5
Bit-Banding
A bit-band region maps each word in a bit-band alias region to a single bit in the bit-band region.
The bit-band regions occupy the lowest 1 MB of the SRAM and peripheral memory regions. Accesses
to the 32-MB SRAM alias region map to the 1-MB SRAM bit-band region, as shown in Table
2-6 on page 93. Accesses to the 32-MB peripheral alias region map to the 1-MB peripheral bit-band
region, as shown in Table 2-7 on page 93. For the specific address range of the bit-band regions,
see Table 2-4 on page 87.
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Note:
A word access to the SRAM or the peripheral bit-band alias region maps to a single bit in
the SRAM or peripheral bit-band region.
A word access to a bit band address results in a word access to the underlying memory,
and similarly for halfword and byte accesses. This allows bit band accesses to match the
access requirements of the underlying peripheral.
Table 2-6. SRAM Memory Bit-Banding Regions
Address Range
Memory Region
Instruction and Data Accesses
Start
End
0x2000.0000
0x2000.7FFF
SRAM bit-band region Direct accesses to this memory range behave as SRAM
memory accesses, but this region is also bit addressable
through bit-band alias.
0x2200.0000
0x220F.FFFF
SRAM bit-band alias
Data accesses to this region are remapped to bit band
region. A write operation is performed as
read-modify-write. Instruction accesses are not remapped.
Table 2-7. Peripheral Memory Bit-Banding Regions
Address Range
Memory Region
Instruction and Data Accesses
0x400F.FFFF
Peripheral bit-band
region
Direct accesses to this memory range behave as
peripheral memory accesses, but this region is also bit
addressable through bit-band alias.
0x43FF.FFFF
Peripheral bit-band alias Data accesses to this region are remapped to bit band
region. A write operation is performed as
read-modify-write. Instruction accesses are not permitted.
Start
End
0x4000.0000
0x4200.0000
The following formula shows how the alias region maps onto the bit-band region:
bit_word_offset = (byte_offset x 32) + (bit_number x 4)
bit_word_addr = bit_band_base + bit_word_offset
where:
bit_word_offset
The position of the target bit in the bit-band memory region.
bit_word_addr
The address of the word in the alias memory region that maps to the targeted bit.
bit_band_base
The starting address of the alias region.
byte_offset
The number of the byte in the bit-band region that contains the targeted bit.
bit_number
The bit position, 0-7, of the targeted bit.
Figure 2-4 on page 94 shows examples of bit-band mapping between the SRAM bit-band alias
region and the SRAM bit-band region:
■ The alias word at 0x23FF.FFE0 maps to bit 0 of the bit-band byte at 0x200F.FFFF:
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0x23FF.FFE0 = 0x2200.0000 + (0x000F.FFFF*32) + (0*4)
■ The alias word at 0x23FF.FFFC maps to bit 7 of the bit-band byte at 0x200F.FFFF:
0x23FF.FFFC = 0x2200.0000 + (0x000F.FFFF*32) + (7*4)
■ The alias word at 0x2200.0000 maps to bit 0 of the bit-band byte at 0x2000.0000:
0x2200.0000 = 0x2200.0000 + (0*32) + (0*4)
■ The alias word at 0x2200.001C maps to bit 7 of the bit-band byte at 0x2000.0000:
0x2200.001C = 0x2200.0000+ (0*32) + (7*4)
Figure 2-4. Bit-Band Mapping
32-MB Alias Region
0x23FF.FFFC
0x23FF.FFF8
0x23FF.FFF4
0x23FF.FFF0
0x23FF.FFEC
0x23FF.FFE8
0x23FF.FFE4
0x23FF.FFE0
0x2200.001C
0x2200.0018
0x2200.0014
0x2200.0010
0x2200.000C
0x2200.0008
0x2200.0004
0x2200.0000
7
3
1-MB SRAM Bit-Band Region
7
6
5
4
3
2
1
0
7
6
0x200F.FFFF
7
6
5
4
3
2
0x2000.0003
2.4.5.1
5
4
3
2
1
0
7
6
0x200F.FFFE
1
0
7
6
5
4
3
2
5
4
3
2
1
0
6
0x200F.FFFD
1
0x2000.0002
0
7
6
5
4
3
2
0x2000.0001
5
4
2
1
0
1
0
0x200F.FFFC
1
0
7
6
5
4
3
2
0x2000.0000
Directly Accessing an Alias Region
Writing to a word in the alias region updates a single bit in the bit-band region.
Bit 0 of the value written to a word in the alias region determines the value written to the targeted
bit in the bit-band region. Writing a value with bit 0 set writes a 1 to the bit-band bit, and writing a
value with bit 0 clear writes a 0 to the bit-band bit.
Bits 31:1 of the alias word have no effect on the bit-band bit. Writing 0x01 has the same effect as
writing 0xFF. Writing 0x00 has the same effect as writing 0x0E.
When reading a word in the alias region, 0x0000.0000 indicates that the targeted bit in the bit-band
region is clear and 0x0000.0001 indicates that the targeted bit in the bit-band region is set.
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2.4.5.2
Directly Accessing a Bit-Band Region
“Behavior of Memory Accesses” on page 90 describes the behavior of direct byte, halfword, or word
accesses to the bit-band regions.
2.4.6
Data Storage
The processor views memory as a linear collection of bytes numbered in ascending order from zero.
For example, bytes 0-3 hold the first stored word, and bytes 4-7 hold the second stored word. Data
is stored in little-endian format, with the least-significant byte (lsbyte) of a word stored at the
lowest-numbered byte, and the most-significant byte (msbyte) stored at the highest-numbered byte.
Figure 2-5 on page 95 illustrates how data is stored.
Figure 2-5. Data Storage
Memory
7
Register
0
31
2.4.7
Address A
B0
A+1
B1
A+2
B2
A+3
B3
lsbyte
24 23
B3
16 15
B2
8 7
B1
0
B0
msbyte
Synchronization Primitives
The Cortex-M4F instruction set includes pairs of synchronization primitives which provide a
non-blocking mechanism that a thread or process can use to obtain exclusive access to a memory
location. Software can use these primitives to perform a guaranteed read-modify-write memory
update sequence or for a semaphore mechanism.
A pair of synchronization primitives consists of:
■ A Load-Exclusive instruction, which is used to read the value of a memory location and requests
exclusive access to that location.
■ A Store-Exclusive instruction, which is used to attempt to write to the same memory location and
returns a status bit to a register. If this status bit is clear, it indicates that the thread or process
gained exclusive access to the memory and the write succeeds; if this status bit is set, it indicates
that the thread or process did not gain exclusive access to the memory and no write was
performed.
The pairs of Load-Exclusive and Store-Exclusive instructions are:
■ The word instructions LDREX and STREX
■ The halfword instructions LDREXH and STREXH
■ The byte instructions LDREXB and STREXB
Software must use a Load-Exclusive instruction with the corresponding Store-Exclusive instruction.
To perform an exclusive read-modify-write of a memory location, software must:
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1. Use a Load-Exclusive instruction to read the value of the location.
2. Modify the value, as required.
3. Use a Store-Exclusive instruction to attempt to write the new value back to the memory location.
4. Test the returned status bit.
If the status bit is clear, the read-modify-write completed successfully. If the status bit is set, no
write was performed, which indicates that the value returned at step 1 might be out of date. The
software must retry the entire read-modify-write sequence.
Software can use the synchronization primitives to implement a semaphore as follows:
1. Use a Load-Exclusive instruction to read from the semaphore address to check whether the
semaphore is free.
2. If the semaphore is free, use a Store-Exclusive to write the claim value to the semaphore
address.
3. If the returned status bit from step 2 indicates that the Store-Exclusive succeeded, then the
software has claimed the semaphore. However, if the Store-Exclusive failed, another process
might have claimed the semaphore after the software performed step 1.
The Cortex-M4F includes an exclusive access monitor that tags the fact that the processor has
executed a Load-Exclusive instruction. The processor removes its exclusive access tag if:
■ It executes a CLREX instruction.
■ It executes a Store-Exclusive instruction, regardless of whether the write succeeds.
■ An exception occurs, which means the processor can resolve semaphore conflicts between
different threads.
For more information about the synchronization primitive instructions, see the Cortex™-M4 instruction
set chapter in the ARM® Cortex™-M4 Devices Generic User Guide (literature number ARM DUI
0553A).
2.5
Exception Model
The ARM Cortex-M4F processor and the Nested Vectored Interrupt Controller (NVIC) prioritize and
handle all exceptions in Handler Mode. The processor state is automatically stored to the stack on
an exception and automatically restored from the stack at the end of the Interrupt Service Routine
(ISR). The vector is fetched in parallel to the state saving, enabling efficient interrupt entry. The
processor supports tail-chaining, which enables back-to-back interrupts to be performed without the
overhead of state saving and restoration.
Table 2-8 on page 99 lists all exception types. Software can set eight priority levels on seven of
these exceptions (system handlers) as well as on 95 interrupts (listed in Table 2-9 on page 99).
Priorities on the system handlers are set with the NVIC System Handler Priority n (SYSPRIn)
registers. Interrupts are enabled through the NVIC Interrupt Set Enable n (ENn) register and
prioritized with the NVIC Interrupt Priority n (PRIn) registers. Priorities can be grouped by splitting
priority levels into preemption priorities and subpriorities. All the interrupt registers are described in
“Nested Vectored Interrupt Controller (NVIC)” on page 120.
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Internally, the highest user-programmable priority (0) is treated as fourth priority, after a Reset,
Non-Maskable Interrupt (NMI), and a Hard Fault, in that order. Note that 0 is the default priority for
all the programmable priorities.
Important: After a write to clear an interrupt source, it may take several processor cycles for the
NVIC to see the interrupt source deassert. Thus if the interrupt clear is done as the last
action in an interrupt handler, it is possible for the interrupt handler to complete while
the NVIC sees the interrupt as still asserted, causing the interrupt handler to be
re-entered errantly. This situation can be avoided by either clearing the interrupt source
at the beginning of the interrupt handler or by performing a read or write after the write
to clear the interrupt source (and flush the write buffer).
See “Nested Vectored Interrupt Controller (NVIC)” on page 120 for more information on exceptions
and interrupts.
2.5.1
Exception States
Each exception is in one of the following states:
■ Inactive. The exception is not active and not pending.
■ Pending. The exception is waiting to be serviced by the processor. An interrupt request from a
peripheral or from software can change the state of the corresponding interrupt to pending.
■ Active. An exception that is being serviced by the processor but has not completed.
Note:
An exception handler can interrupt the execution of another exception handler. In this
case, both exceptions are in the active state.
■ Active and Pending. The exception is being serviced by the processor, and there is a pending
exception from the same source.
2.5.2
Exception Types
The exception types are:
■ Reset. Reset is invoked on power up or a warm reset. The exception model treats reset as a
special form of exception. When reset is asserted, the operation of the processor stops, potentially
at any point in an instruction. When reset is deasserted, execution restarts from the address
provided by the reset entry in the vector table. Execution restarts as privileged execution in
Thread mode.
■ NMI. A non-maskable Interrupt (NMI) can be signaled using the NMI signal or triggered by
software using the Interrupt Control and State (INTCTRL) register. This exception has the
highest priority other than reset. NMI is permanently enabled and has a fixed priority of -2. NMIs
cannot be masked or prevented from activation by any other exception or preempted by any
exception other than reset.
■ Hard Fault. A hard fault is an exception that occurs because of an error during exception
processing, or because an exception cannot be managed by any other exception mechanism.
Hard faults have a fixed priority of -1, meaning they have higher priority than any exception with
configurable priority.
■ Memory Management Fault. A memory management fault is an exception that occurs because
of a memory protection related fault, including access violation and no match. The MPU or the
fixed memory protection constraints determine this fault, for both instruction and data memory
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transactions. This fault is used to abort instruction accesses to Execute Never (XN) memory
regions, even if the MPU is disabled.
■ Bus Fault. A bus fault is an exception that occurs because of a memory-related fault for an
instruction or data memory transaction such as a prefetch fault or a memory access fault. This
fault can be enabled or disabled.
■ Usage Fault. A usage fault is an exception that occurs because of a fault related to instruction
execution, such as:
– An undefined instruction
– An illegal unaligned access
– Invalid state on instruction execution
– An error on exception return
An unaligned address on a word or halfword memory access or division by zero can cause a
usage fault when the core is properly configured.
■ SVCall. A supervisor call (SVC) is an exception that is triggered by the SVC instruction. In an
OS environment, applications can use SVC instructions to access OS kernel functions and device
drivers.
■ Debug Monitor. This exception is caused by the debug monitor (when not halting). This exception
is only active when enabled. This exception does not activate if it is a lower priority than the
current activation.
■ PendSV. PendSV is a pendable, interrupt-driven request for system-level service. In an OS
environment, use PendSV for context switching when no other exception is active. PendSV is
triggered using the Interrupt Control and State (INTCTRL) register.
■ SysTick. A SysTick exception is an exception that the system timer generates when it reaches
zero when it is enabled to generate an interrupt. Software can also generate a SysTick exception
using the Interrupt Control and State (INTCTRL) register. In an OS environment, the processor
can use this exception as system tick.
■ Interrupt (IRQ). An interrupt, or IRQ, is an exception signaled by a peripheral or generated by
a software request and fed through the NVIC (prioritized). All interrupts are asynchronous to
instruction execution. In the system, peripherals use interrupts to communicate with the processor.
Table 2-9 on page 99 lists the interrupts on the TM4C123BH6PGE controller.
For an asynchronous exception, other than reset, the processor can execute another instruction
between when the exception is triggered and when the processor enters the exception handler.
Privileged software can disable the exceptions that Table 2-8 on page 99 shows as having
configurable priority (see the SYSHNDCTRL register on page 169 and the DIS0 register on page 140).
For more information about hard faults, memory management faults, bus faults, and usage faults,
see “Fault Handling” on page 107.
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Table 2-8. Exception Types
Exception Type
a
Vector
Number
Priority
Vector Address or
b
Offset
-
0
-
0x0000.0000
Stack top is loaded from the first
entry of the vector table on reset.
Reset
1
-3 (highest)
0x0000.0004
Asynchronous
Non-Maskable Interrupt
(NMI)
2
-2
0x0000.0008
Asynchronous
Hard Fault
3
-1
0x0000.000C
-
c
0x0000.0010
Synchronous
c
0x0000.0014
Synchronous when precise and
asynchronous when imprecise
c
Synchronous
Memory Management
4
programmable
Bus Fault
5
programmable
Usage Fault
6
programmable
0x0000.0018
7-10
-
-
-
0x0000.002C
Synchronous
c
0x0000.0030
Synchronous
c
0x0000.0038
Asynchronous
c
0x0000.003C
Asynchronous
SVCall
11
programmable
12
programmable
-
13
-
PendSV
14
programmable
15
Interrupts
-
programmable
16 and above
Reserved
c
Debug Monitor
SysTick
Activation
d
programmable
Reserved
0x0000.0040 and above Asynchronous
a. 0 is the default priority for all the programmable priorities.
b. See “Vector Table” on page 102.
c. See SYSPRI1 on page 166.
d. See PRIn registers on page 148.
Table 2-9. Interrupts
Vector Number
Interrupt Number (Bit
in Interrupt Registers)
Vector Address or
Offset
Description
0-15
-
0x0000.0000 0x0000.003C
16
0
0x0000.0040
GPIO Port A
17
1
0x0000.0044
GPIO Port B
18
2
0x0000.0048
GPIO Port C
19
3
0x0000.004C
GPIO Port D
20
4
0x0000.0050
GPIO Port E
21
5
0x0000.0054
UART0
22
6
0x0000.0058
UART1
23
7
0x0000.005C
SSI0
24
8
0x0000.0060
I2C0
25
9
0x0000.0064
PWM0 Fault
26
10
0x0000.0068
PWM0 Generator 0
27
11
0x0000.006C
PWM0 Generator 1
28
12
0x0000.0070
PWM0 Generator 2
29
13
0x0000.0074
QEI0
30
14
0x0000.0078
ADC0 Sequence 0
31
15
0x0000.007C
ADC0 Sequence 1
Processor exceptions
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Table 2-9. Interrupts (continued)
Vector Number
Interrupt Number (Bit
in Interrupt Registers)
Vector Address or
Offset
Description
32
16
0x0000.0080
ADC0 Sequence 2
33
17
0x0000.0084
ADC0 Sequence 3
34
18
0x0000.0088
Watchdog Timers 0 and 1
35
19
0x0000.008C
16/32-Bit Timer 0A
36
20
0x0000.0090
16/32-Bit Timer 0B
37
21
0x0000.0094
16/32-Bit Timer 1A
38
22
0x0000.0098
16/32-Bit Timer 1B
39
23
0x0000.009C
16/32-Bit Timer 2A
40
24
0x0000.00A0
16/32-Bit Timer 2B
41
25
0x0000.00A4
Analog Comparator 0
42
26
0x0000.00A8
Analog Comparator 1
43
27
0x0000.00AC
Analog Comparator 2
44
28
0x0000.00B0
System Control
45
29
0x0000.00B4
Flash Memory Control and EEPROM Control
46
30
0x0000.00B8
GPIO Port F
47
31
0x0000.00BC
GPIO Port G
48
32
0x0000.00C0
GPIO Port H
49
33
0x0000.00C4
UART2
50
34
0x0000.00C8
SSI1
51
35
0x0000.00CC
16/32-Bit Timer 3A
52
36
0x0000.00D0
16/32-Bit Timer 3B
53
37
0x0000.00D4
I2C1
54
38
0x0000.00D8
QEI1
55
39
0x0000.00DC
CAN0
CAN1
56
40
0x0000.00E0
57-58
41-42
-
59
43
0x0000.00EC
60
44
-
61
45
0x0000.00F4
PWM Generator 3
Reserved
Hibernation Module
Reserved
62
46
0x0000.00F8
µDMA Software
63
47
0x0000.00FC
µDMA Error
64
48
0x0000.0100
ADC1 Sequence 0
65
49
0x0000.0104
ADC1 Sequence 1
66
50
0x0000.0108
ADC1 Sequence 2
67
51
0x0000.010C
ADC1 Sequence 3
68-69
52-53
-
70
54
0x0000.0118
GPIO Port J
71
55
0x0000.011C
GPIO Port K
72
56
0x0000.0120
GPIO Port L
73
57
0x0000.0124
SSI2
74
58
0x0000.0128
SSI3
Reserved
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Table 2-9. Interrupts (continued)
Vector Number
Interrupt Number (Bit
in Interrupt Registers)
Vector Address or
Offset
Description
75
59
0x0000.012C
UART3
76
60
0x0000.0130
UART4
77
61
0x0000.0134
UART5
78
62
0x0000.0138
UART6
79
63
0x0000.013C
UART7
80-83
64-67
0x0000.0140 0x0000.014C
Reserved
84
68
0x0000.0150
I2C2
85
69
0x0000.0154
I2C3
86
70
0x0000.0158
16/32-Bit Timer 4A
87
71
0x0000.015C
16/32-Bit Timer 4B
88-107
72-91
0x0000.0160 0x0000.01AC
Reserved
108
92
0x0000.01B0
16/32-Bit Timer 5A
109
93
0x0000.01B4
16/32-Bit Timer 5B
110
94
0x0000.01B8
32/64-Bit Timer 0A
111
95
0x0000.01BC
32/64-Bit Timer 0B
112
96
0x0000.01C0
32/64-Bit Timer 1A
113
97
0x0000.01C4
32/64-Bit Timer 1B
114
98
0x0000.01C8
32/64-Bit Timer 2A
115
99
0x0000.01CC
32/64-Bit Timer 2B
116
100
0x0000.01D0
32/64-Bit Timer 3A
117
101
0x0000.01D4
32/64-Bit Timer 3B
118
102
0x0000.01D8
32/64-Bit Timer 4A
119
103
0x0000.01DC
32/64-Bit Timer 4B
120
104
0x0000.01E0
32/64-Bit Timer 5A
121
105
0x0000.01E4
32/64-Bit Timer 5B
122
106
0x0000.01E8
System Exception (imprecise)
123-124
107-108
-
125
109
0x0000.01F4
I2C4
126
110
0x0000.01F8
I2C5
127
111
0x0000.01FC
GPIO Port M
GPIO Port N
Reserved
128
112
0x0000.0200
129-131
113-115
-
132
116
0x0000.0210
GPIO Port P (Summary or P0)
133
117
0x0000.0214
GPIO Port P1
134
118
0x0000.0218
GPIO Port P2
135
119
0x0000.021C
GPIO Port P3
136
120
0x0000.0220
GPIO Port P4
137
121
0x0000.0224
GPIO Port P5
138
122
0x0000.0228
GPIO Port P6
Reserved
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Table 2-9. Interrupts (continued)
2.5.3
Vector Number
Interrupt Number (Bit
in Interrupt Registers)
Vector Address or
Offset
Description
139
123
0x0000.022C
140-149
124-133
-
150
134
0x0000.0258
PWM1 Generator 0
GPIO Port P7
Reserved
151
135
0x0000.025C
PWM1 Generator 1
152
136
0x0000.0260
PWM1 Generator 2
153
137
0x0000.0264
PWM1 Generator 3
154
138
0x0000.0268
PWM1 Fault
Exception Handlers
The processor handles exceptions using:
■ Interrupt Service Routines (ISRs). Interrupts (IRQx) are the exceptions handled by ISRs.
■ Fault Handlers. Hard fault, memory management fault, usage fault, and bus fault are fault
exceptions handled by the fault handlers.
■ System Handlers. NMI, PendSV, SVCall, SysTick, and the fault exceptions are all system
exceptions that are handled by system handlers.
2.5.4
Vector Table
The vector table contains the reset value of the stack pointer and the start addresses, also called
exception vectors, for all exception handlers. The vector table is constructed using the vector address
or offset shown in Table 2-8 on page 99. Figure 2-6 on page 103 shows the order of the exception
vectors in the vector table. The least-significant bit of each vector must be 1, indicating that the
exception handler is Thumb code
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Figure 2-6. Vector Table
Exception number IRQ number
154
138
.
.
.
18
2
17
1
16
0
15
-1
14
-2
13
Offset
0x0268
.
.
.
0x004C
0x0048
0x0044
0x0040
0x003C
0x0038
12
11
Vector
IRQ131
.
.
.
IRQ2
IRQ1
IRQ0
Systick
PendSV
Reserved
Reserved for Debug
-5
10
0x002C
9
SVCall
Reserved
8
7
6
-10
5
-11
4
-12
3
-13
2
-14
1
0x0018
0x0014
0x0010
0x000C
0x0008
0x0004
0x0000
Usage fault
Bus fault
Memory management fault
Hard fault
NMI
Reset
Initial SP value
On system reset, the vector table is fixed at address 0x0000.0000. Privileged software can write to
the Vector Table Offset (VTABLE) register to relocate the vector table start address to a different
memory location, in the range 0x0000.0400 to 0x3FFF.FC00 (see “Vector Table” on page 102). Note
that when configuring the VTABLE register, the offset must be aligned on a 1024-byte boundary.
2.5.5
Exception Priorities
As Table 2-8 on page 99 shows, all exceptions have an associated priority, with a lower priority
value indicating a higher priority and configurable priorities for all exceptions except Reset, Hard
fault, and NMI. If software does not configure any priorities, then all exceptions with a configurable
priority have a priority of 0. For information about configuring exception priorities, see page 166 and
page 148.
Note:
Configurable priority values for the Tiva™ C Series implementation are in the range 0-7.
This means that the Reset, Hard fault, and NMI exceptions, with fixed negative priority
values, always have higher priority than any other exception.
For example, assigning a higher priority value to IRQ[0] and a lower priority value to IRQ[1] means
that IRQ[1] has higher priority than IRQ[0]. If both IRQ[1] and IRQ[0] are asserted, IRQ[1] is processed
before IRQ[0].
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If multiple pending exceptions have the same priority, the pending exception with the lowest exception
number takes precedence. For example, if both IRQ[0] and IRQ[1] are pending and have the same
priority, then IRQ[0] is processed before IRQ[1].
When the processor is executing an exception handler, the exception handler is preempted if a
higher priority exception occurs. If an exception occurs with the same priority as the exception being
handled, the handler is not preempted, irrespective of the exception number. However, the status
of the new interrupt changes to pending.
2.5.6
Interrupt Priority Grouping
To increase priority control in systems with interrupts, the NVIC supports priority grouping. This
grouping divides each interrupt priority register entry into two fields:
■ An upper field that defines the group priority
■ A lower field that defines a subpriority within the group
Only the group priority determines preemption of interrupt exceptions. When the processor is
executing an interrupt exception handler, another interrupt with the same group priority as the
interrupt being handled does not preempt the handler.
If multiple pending interrupts have the same group priority, the subpriority field determines the order
in which they are processed. If multiple pending interrupts have the same group priority and
subpriority, the interrupt with the lowest IRQ number is processed first.
For information about splitting the interrupt priority fields into group priority and subpriority, see
page 160.
2.5.7
Exception Entry and Return
Descriptions of exception handling use the following terms:
■ Preemption. When the processor is executing an exception handler, an exception can preempt
the exception handler if its priority is higher than the priority of the exception being handled. See
“Interrupt Priority Grouping” on page 104 for more information about preemption by an interrupt.
When one exception preempts another, the exceptions are called nested exceptions. See
“Exception Entry” on page 105 more information.
■ Return. Return occurs when the exception handler is completed, and there is no pending
exception with sufficient priority to be serviced and the completed exception handler was not
handling a late-arriving exception. The processor pops the stack and restores the processor
state to the state it had before the interrupt occurred. See “Exception Return” on page 106 for
more information.
■ Tail-Chaining. This mechanism speeds up exception servicing. On completion of an exception
handler, if there is a pending exception that meets the requirements for exception entry, the
stack pop is skipped and control transfers to the new exception handler.
■ Late-Arriving. This mechanism speeds up preemption. If a higher priority exception occurs
during state saving for a previous exception, the processor switches to handle the higher priority
exception and initiates the vector fetch for that exception. State saving is not affected by late
arrival because the state saved is the same for both exceptions. Therefore, the state saving
continues uninterrupted. The processor can accept a late arriving exception until the first instruction
of the exception handler of the original exception enters the execute stage of the processor. On
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return from the exception handler of the late-arriving exception, the normal tail-chaining rules
apply.
2.5.7.1
Exception Entry
Exception entry occurs when there is a pending exception with sufficient priority and either the
processor is in Thread mode or the new exception is of higher priority than the exception being
handled, in which case the new exception preempts the original exception.
When one exception preempts another, the exceptions are nested.
Sufficient priority means the exception has more priority than any limits set by the mask registers
(see PRIMASK on page 80, FAULTMASK on page 81, and BASEPRI on page 82). An exception
with less priority than this is pending but is not handled by the processor.
When the processor takes an exception, unless the exception is a tail-chained or a late-arriving
exception, the processor pushes information onto the current stack. This operation is referred to as
stacking and the structure of eight data words is referred to as stack frame.
When using floating-point routines, the Cortex-M4F processor automatically stacks the architected
floating-point state on exception entry. Figure 2-7 on page 106 shows the Cortex-M4F stack frame
layout when floating-point state is preserved on the stack as the result of an interrupt or an exception.
Note:
Where stack space for floating-point state is not allocated, the stack frame is the same as
that of ARMv7-M implementations without an FPU. Figure 2-7 on page 106 shows this stack
frame also.
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Figure 2-7. Exception Stack Frame
...
{aligner}
FPSCR
S15
S14
S13
S12
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
xPSR
PC
LR
R12
R3
R2
R1
R0
Exception frame with
floating-point storage
Pre-IRQ top of stack
Decreasing
memory
address
IRQ top of stack
...
{aligner}
xPSR
PC
LR
R12
R3
R2
R1
R0
Pre-IRQ top of stack
IRQ top of stack
Exception frame without
floating-point storage
Immediately after stacking, the stack pointer indicates the lowest address in the stack frame.
The stack frame includes the return address, which is the address of the next instruction in the
interrupted program. This value is restored to the PC at exception return so that the interrupted
program resumes.
In parallel with the stacking operation, the processor performs a vector fetch that reads the exception
handler start address from the vector table. When stacking is complete, the processor starts executing
the exception handler. At the same time, the processor writes an EXC_RETURN value to the LR,
indicating which stack pointer corresponds to the stack frame and what operation mode the processor
was in before the entry occurred.
If no higher-priority exception occurs during exception entry, the processor starts executing the
exception handler and automatically changes the status of the corresponding pending interrupt to
active.
If another higher-priority exception occurs during exception entry, known as late arrival, the processor
starts executing the exception handler for this exception and does not change the pending status
of the earlier exception.
2.5.7.2
Exception Return
Exception return occurs when the processor is in Handler mode and executes one of the following
instructions to load the EXC_RETURN value into the PC:
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■ An LDM or POP instruction that loads the PC
■ A BX instruction using any register
■ An LDR instruction with the PC as the destination
EXC_RETURN is the value loaded into the LR on exception entry. The exception mechanism relies
on this value to detect when the processor has completed an exception handler. The lowest five
bits of this value provide information on the return stack and processor mode. Table 2-10 on page 107
shows the EXC_RETURN values with a description of the exception return behavior.
EXC_RETURN bits 31:5 are all set. When this value is loaded into the PC, it indicates to the processor
that the exception is complete, and the processor initiates the appropriate exception return sequence.
Table 2-10. Exception Return Behavior
EXC_RETURN[31:0]
Description
0xFFFF.FFE0
Reserved
0xFFFF.FFE1
Return to Handler mode.
Exception return uses floating-point state from MSP.
Execution uses MSP after return.
0xFFFF.FFE2 - 0xFFFF.FFE8
Reserved
0xFFFF.FFE9
Return to Thread mode.
Exception return uses floating-point state from MSP.
Execution uses MSP after return.
0xFFFF.FFEA - 0xFFFF.FFEC
Reserved
0xFFFF.FFED
Return to Thread mode.
Exception return uses floating-point state from PSP.
Execution uses PSP after return.
0xFFFF.FFEE - 0xFFFF.FFF0
Reserved
0xFFFF.FFF1
Return to Handler mode.
Exception return uses non-floating-point state from MSP.
Execution uses MSP after return.
0xFFFF.FFF2 - 0xFFFF.FFF8
Reserved
0xFFFF.FFF9
Return to Thread mode.
Exception return uses non-floating-point state from MSP.
Execution uses MSP after return.
0xFFFF.FFFA - 0xFFFF.FFFC
Reserved
0xFFFF.FFFD
Return to Thread mode.
Exception return uses non-floating-point state from PSP.
Execution uses PSP after return.
0xFFFF.FFFE - 0xFFFF.FFFF
2.6
Reserved
Fault Handling
Faults are a subset of the exceptions (see “Exception Model” on page 96). The following conditions
generate a fault:
■ A bus error on an instruction fetch or vector table load or a data access.
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■ An internally detected error such as an undefined instruction or an attempt to change state with
a BX instruction.
■ Attempting to execute an instruction from a memory region marked as Non-Executable (XN).
■ An MPU fault because of a privilege violation or an attempt to access an unmanaged region.
2.6.1
Fault Types
Table 2-11 on page 108 shows the types of fault, the handler used for the fault, the corresponding
fault status register, and the register bit that indicates the fault has occurred. See page 173 for more
information about the fault status registers.
Table 2-11. Faults
Fault
Handler
Fault Status Register
Bit Name
Bus error on a vector read
Hard fault
Hard Fault Status (HFAULTSTAT)
VECT
Fault escalated to a hard fault
Hard fault
Hard Fault Status (HFAULTSTAT)
FORCED
MPU or default memory mismatch on
instruction access
Memory management
fault
Memory Management Fault Status
(MFAULTSTAT)
IERR
MPU or default memory mismatch on
data access
Memory management
fault
Memory Management Fault Status
(MFAULTSTAT)
DERR
MPU or default memory mismatch on
exception stacking
Memory management
fault
Memory Management Fault Status
(MFAULTSTAT)
MSTKE
MPU or default memory mismatch on
exception unstacking
Memory management
fault
Memory Management Fault Status
(MFAULTSTAT)
MUSTKE
MPU or default memory mismatch
during lazy floating-point state
preservation
Memory management
fault
Memory Management Fault Status
(MFAULTSTAT)
MLSPERR
Bus error during exception stacking
Bus fault
Bus Fault Status (BFAULTSTAT)
BSTKE
Bus error during exception unstacking Bus fault
Bus Fault Status (BFAULTSTAT)
BUSTKE
Bus error during instruction prefetch
Bus fault
Bus Fault Status (BFAULTSTAT)
IBUS
Bus error during lazy floating-point state Bus fault
preservation
Bus Fault Status (BFAULTSTAT)
BLSPE
Precise data bus error
Bus fault
Bus Fault Status (BFAULTSTAT)
PRECISE
Imprecise data bus error
Bus fault
Bus Fault Status (BFAULTSTAT)
IMPRE
Attempt to access a coprocessor
Usage fault
Usage Fault Status (UFAULTSTAT)
NOCP
Undefined instruction
Usage fault
Usage Fault Status (UFAULTSTAT)
UNDEF
Attempt to enter an invalid instruction
b
set state
Usage fault
Usage Fault Status (UFAULTSTAT)
INVSTAT
Invalid EXC_RETURN value
Usage fault
Usage Fault Status (UFAULTSTAT)
INVPC
Illegal unaligned load or store
Usage fault
Usage Fault Status (UFAULTSTAT)
UNALIGN
Divide by 0
Usage fault
Usage Fault Status (UFAULTSTAT)
DIV0
a
a. Occurs on an access to an XN region even if the MPU is disabled.
b. Attempting to use an instruction set other than the Thumb instruction set, or returning to a non load-store-multiply instruction
with ICI continuation.
2.6.2
Fault Escalation and Hard Faults
All fault exceptions except for hard fault have configurable exception priority (see SYSPRI1 on
page 166). Software can disable execution of the handlers for these faults (see SYSHNDCTRL on
page 169).
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Usually, the exception priority, together with the values of the exception mask registers, determines
whether the processor enters the fault handler, and whether a fault handler can preempt another
fault handler as described in “Exception Model” on page 96.
In some situations, a fault with configurable priority is treated as a hard fault. This process is called
priority escalation, and the fault is described as escalated to hard fault. Escalation to hard fault
occurs when:
■ A fault handler causes the same kind of fault as the one it is servicing. This escalation to hard
fault occurs because a fault handler cannot preempt itself because it must have the same priority
as the current priority level.
■ A fault handler causes a fault with the same or lower priority as the fault it is servicing. This
situation happens because the handler for the new fault cannot preempt the currently executing
fault handler.
■ An exception handler causes a fault for which the priority is the same as or lower than the currently
executing exception.
■ A fault occurs and the handler for that fault is not enabled.
If a bus fault occurs during a stack push when entering a bus fault handler, the bus fault does not
escalate to a hard fault. Thus if a corrupted stack causes a fault, the fault handler executes even
though the stack push for the handler failed. The fault handler operates but the stack contents are
corrupted.
Note:
2.6.3
Only Reset and NMI can preempt the fixed priority hard fault. A hard fault can preempt any
exception other than Reset, NMI, or another hard fault.
Fault Status Registers and Fault Address Registers
The fault status registers indicate the cause of a fault. For bus faults and memory management
faults, the fault address register indicates the address accessed by the operation that caused the
fault, as shown in Table 2-12 on page 109.
Table 2-12. Fault Status and Fault Address Registers
Handler
Status Register Name
Address Register Name
Register Description
Hard fault
Hard Fault Status (HFAULTSTAT)
-
page 179
Memory management Memory Management Fault Status
fault
(MFAULTSTAT)
Memory Management Fault
Address (MMADDR)
page 173
Bus fault
Bus Fault Address
(FAULTADDR)
page 173
-
page 173
Bus Fault Status (BFAULTSTAT)
Usage fault
2.6.4
Usage Fault Status (UFAULTSTAT)
page 180
page 181
Lockup
The processor enters a lockup state if a hard fault occurs when executing the NMI or hard fault
handlers. When the processor is in the lockup state, it does not execute any instructions. The
processor remains in lockup state until it is reset, an NMI occurs, or it is halted by a debugger.
Note:
If the lockup state occurs from the NMI handler, a subsequent NMI does not cause the
processor to leave the lockup state.
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2.7
Power Management
The Cortex-M4F processor sleep modes reduce power consumption:
■ Sleep mode stops the processor clock.
■ Deep-sleep mode stops the system clock and switches off the PLL and Flash memory.
The SLEEPDEEP bit of the System Control (SYSCTRL) register selects which sleep mode is used
(see page 162). For more information about the behavior of the sleep modes, see “System
Control” on page 222.
This section describes the mechanisms for entering sleep mode and the conditions for waking up
from sleep mode, both of which apply to Sleep mode and Deep-sleep mode.
2.7.1
Entering Sleep Modes
This section describes the mechanisms software can use to put the processor into one of the sleep
modes.
The system can generate spurious wake-up events, for example a debug operation wakes up the
processor. Therefore, software must be able to put the processor back into sleep mode after such
an event. A program might have an idle loop to put the processor back to sleep mode.
2.7.1.1
Wait for Interrupt
The wait for interrupt instruction, WFI, causes immediate entry to sleep mode unless the wake-up
condition is true (see “Wake Up from WFI or Sleep-on-Exit” on page 111). When the processor
executes a WFI instruction, it stops executing instructions and enters sleep mode. See the
Cortex™-M4 instruction set chapter in the ARM® Cortex™-M4 Devices Generic User Guide (literature
number ARM DUI 0553A) for more information.
2.7.1.2
Wait for Event
The wait for event instruction, WFE, causes entry to sleep mode conditional on the value of a one-bit
event register. When the processor executes a WFE instruction, it checks the event register. If the
register is 0, the processor stops executing instructions and enters sleep mode. If the register is 1,
the processor clears the register and continues executing instructions without entering sleep mode.
If the event register is 1, the processor must not enter sleep mode on execution of a WFE instruction.
Typically, this situation occurs if an SEV instruction has been executed. Software cannot access
this register directly.
See the Cortex™-M4 instruction set chapter in the ARM® Cortex™-M4 Devices Generic User Guide
(literature number ARM DUI 0553A) for more information.
2.7.1.3
Sleep-on-Exit
If the SLEEPEXIT bit of the SYSCTRL register is set, when the processor completes the execution
of all exception handlers, it returns to Thread mode and immediately enters sleep mode. This
mechanism can be used in applications that only require the processor to run when an exception
occurs.
2.7.2
Wake Up from Sleep Mode
The conditions for the processor to wake up depend on the mechanism that caused it to enter sleep
mode.
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2.7.2.1
Wake Up from WFI or Sleep-on-Exit
Normally, the processor wakes up only when the NVIC detects an exception with sufficient priority
to cause exception entry. Some embedded systems might have to execute system restore tasks
after the processor wakes up and before executing an interrupt handler. Entry to the interrupt handler
can be delayed by setting the PRIMASK bit and clearing the FAULTMASK bit. If an interrupt arrives
that is enabled and has a higher priority than current exception priority, the processor wakes up but
does not execute the interrupt handler until the processor clears PRIMASK. For more information
about PRIMASK and FAULTMASK, see page 80 and page 81.
2.7.2.2
Wake Up from WFE
The processor wakes up if it detects an exception with sufficient priority to cause exception entry.
In addition, if the SEVONPEND bit in the SYSCTRL register is set, any new pending interrupt triggers
an event and wakes up the processor, even if the interrupt is disabled or has insufficient priority to
cause exception entry. For more information about SYSCTRL, see page 162.
2.8
Instruction Set Summary
The processor implements a version of the Thumb instruction set. Table 2-13 on page 111 lists the
supported instructions.
Note:
In Table 2-13 on page 111:
■
■
■
■
■
Angle brackets, , enclose alternative forms of the operand
Braces, {}, enclose optional operands
The Operands column is not exhaustive
Op2 is a flexible second operand that can be either a register or a constant
Most instructions can use an optional condition code suffix
For more information on the instructions and operands, see the instruction descriptions in
the ARM® Cortex™-M4 Technical Reference Manual.
Table 2-13. Cortex-M4F Instruction Summary
Mnemonic
Operands
Brief Description
Flags
ADC, ADCS
{Rd,} Rn, Op2
Add with carry
N,Z,C,V
ADD, ADDS
{Rd,} Rn, Op2
Add
N,Z,C,V
ADD, ADDW
{Rd,} Rn , #imm12
Add
-
ADR
Rd, label
Load PC-relative address
-
AND, ANDS
{Rd,} Rn, Op2
Logical AND
N,Z,C
ASR, ASRS
Rd, Rm,
Arithmetic shift right
N,Z,C
B
label
Branch
-
BFC
Rd, #lsb, #width
Bit field clear
-
BFI
Rd, Rn, #lsb, #width
Bit field insert
-
BIC, BICS
{Rd,} Rn, Op2
Bit clear
N,Z,C
BKPT
#imm
Breakpoint
-
BL
label
Branch with link
-
BLX
Rm
Branch indirect with link
-
BX
Rm
Branch indirect
-
CBNZ
Rn, label
Compare and branch if non-zero
-
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Table 2-13. Cortex-M4F Instruction Summary (continued)
Mnemonic
Operands
Brief Description
Flags
CBZ
Rn, label
Compare and branch if zero
-
CLREX
-
Clear exclusive
-
CLZ
Rd, Rm
Count leading zeros
-
CMN
Rn, Op2
Compare negative
N,Z,C,V
CMP
Rn, Op2
Compare
N,Z,C,V
CPSID
i
Change processor state, disable
interrupts
-
CPSIE
i
Change processor state, enable
interrupts
-
DMB
-
Data memory barrier
-
DSB
-
Data synchronization barrier
-
EOR, EORS
{Rd,} Rn, Op2
Exclusive OR
N,Z,C
ISB
-
Instruction synchronization barrier
-
IT
-
If-Then condition block
-
LDM
Rn{!}, reglist
Load multiple registers, increment after -
LDMDB, LDMEA
Rn{!}, reglist
Load multiple registers, decrement
before
LDMFD, LDMIA
Rn{!}, reglist
Load multiple registers, increment after -
LDR
Rt, [Rn, #offset]
Load register with word
-
LDRB, LDRBT
Rt, [Rn, #offset]
Load register with byte
-
LDRD
Rt, Rt2, [Rn, #offset]
Load register with two bytes
-
LDREX
Rt, [Rn, #offset]
Load register exclusive
-
LDREXB
Rt, [Rn]
Load register exclusive with byte
-
LDREXH
Rt, [Rn]
Load register exclusive with halfword
-
LDRH, LDRHT
Rt, [Rn, #offset]
Load register with halfword
-
LDRSB, LDRSBT
Rt, [Rn, #offset]
Load register with signed byte
-
LDRSH, LDRSHT
Rt, [Rn, #offset]
Load register with signed halfword
-
LDRT
Rt, [Rn, #offset]
Load register with word
-
LSL, LSLS
Rd, Rm,
Logical shift left
N,Z,C
LSR, LSRS
Rd, Rm,
Logical shift right
N,Z,C
MLA
Rd, Rn, Rm, Ra
Multiply with accumulate, 32-bit result
-
MLS
Rd, Rn, Rm, Ra
Multiply and subtract, 32-bit result
-
MOV, MOVS
Rd, Op2
Move
N,Z,C
MOV, MOVW
Rd, #imm16
Move 16-bit constant
N,Z,C
MOVT
Rd, #imm16
Move top
-
MRS
Rd, spec_reg
Move from special register to general
register
-
MSR
spec_reg, Rm
Move from general register to special
register
N,Z,C,V
MUL, MULS
{Rd,} Rn, Rm
Multiply, 32-bit result
N,Z
MVN, MVNS
Rd, Op2
Move NOT
N,Z,C
NOP
-
No operation
-
ORN, ORNS
{Rd,} Rn, Op2
Logical OR NOT
N,Z,C
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Table 2-13. Cortex-M4F Instruction Summary (continued)
Mnemonic
Operands
Brief Description
Flags
ORR, ORRS
{Rd,} Rn, Op2
Logical OR
N,Z,C
PKHTB, PKHBT
{Rd,} Rn, Rm, Op2
Pack halfword
-
POP
reglist
Pop registers from stack
-
PUSH
reglist
Push registers onto stack
-
QADD
{Rd,} Rn, Rm
Saturating add
Q
QADD16
{Rd,} Rn, Rm
Saturating add 16
-
QADD8
{Rd,} Rn, Rm
Saturating add 8
-
QASX
{Rd,} Rn, Rm
Saturating add and subtract with
exchange
-
QDADD
{Rd,} Rn, Rm
Saturating double and add
Q
QDSUB
{Rd,} Rn, Rm
Saturating double and subtract
Q
QSAX
{Rd,} Rn, Rm
Saturating subtract and add with
exchange
-
QSUB
{Rd,} Rn, Rm
Saturating subtract
Q
QSUB16
{Rd,} Rn, Rm
Saturating subtract 16
-
QSUB8
{Rd,} Rn, Rm
Saturating subtract 8
-
RBIT
Rd, Rn
Reverse bits
-
REV
Rd, Rn
Reverse byte order in a word
-
REV16
Rd, Rn
Reverse byte order in each halfword
-
REVSH
Rd, Rn
Reverse byte order in bottom halfword
and sign extend
-
ROR, RORS
Rd, Rm,
Rotate right
N,Z,C
RRX, RRXS
Rd, Rm
Rotate right with extend
N,Z,C
RSB, RSBS
{Rd,} Rn, Op2
Reverse subtract
N,Z,C,V
SADD16
{Rd,} Rn, Rm
Signed add 16
GE
SADD8
{Rd,} Rn, Rm
Signed add 8
GE
SASX
{Rd,} Rn, Rm
Signed add and subtract with exchange GE
SBC, SBCS
{Rd,} Rn, Op2
Subtract with carry
N,Z,C,V
SBFX
Rd, Rn, #lsb, #width
Signed bit field extract
-
SDIV
{Rd,} Rn, Rm
Signed divide
-
SEL
{Rd,} Rn, Rm
Select bytes
-
SEV
-
Send event
-
SHADD16
{Rd,} Rn, Rm
Signed halving add 16
-
SHADD8
{Rd,} Rn, Rm
Signed halving add 8
-
SHASX
{Rd,} Rn, Rm
Signed halving add and subtract with
exchange
-
SHSAX
{Rd,} Rn, Rm
Signed halving add and subtract with
exchange
-
SHSUB16
{Rd,} Rn, Rm
Signed halving subtract 16
-
SHSUB8
{Rd,} Rn, Rm
Signed halving subtract 8
-
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Table 2-13. Cortex-M4F Instruction Summary (continued)
Mnemonic
Operands
Brief Description
Flags
SMLABB,
Rd, Rn, Rm, Ra
Signed multiply accumulate long
(halfwords)
Q
Rd, Rn, Rm, Ra
Signed multiply accumulate dual
Q
SMLAL
RdLo, RdHi, Rn, Rm
Signed multiply with accumulate
(32x32+64), 64-bit result
-
SMLALBB,
RdLo, RdHi, Rn, Rm
Signed multiply accumulate long
(halfwords)
-
SMLALD, SMLALDX
RdLo, RdHi, Rn, Rm
Signed multiply accumulate long dual
-
SMLAWB,SMLAWT
Rd, Rn, Rm, Ra
Signed multiply accumulate, word by
halfword
Q
SMLSD
Rd, Rn, Rm, Ra
Signed multiply subtract dual
Q
RdLo, RdHi, Rn, Rm
Signed multiply subtract long dual
SMMLA
Rd, Rn, Rm, Ra
Signed most significant word multiply
accumulate
-
SMMLS,
Rd, Rn, Rm, Ra
Signed most significant word multiply
subtract
-
{Rd,} Rn, Rm
Signed most significant word multiply
-
{Rd,} Rn, Rm
Signed dual multiply add
Q
{Rd,} Rn, Rm
Signed multiply halfwords
-
SMULL
RdLo, RdHi, Rn, Rm
Signed multiply (32x32), 64-bit result
-
SMULWB,
{Rd,} Rn, Rm
Signed multiply by halfword
-
{Rd,} Rn, Rm
Signed dual multiply subtract
-
SSAT
Rd, #n, Rm {,shift #s}
Signed saturate
Q
SSAT16
Rd, #n, Rm
Signed saturate 16
Q
SSAX
{Rd,} Rn, Rm
Saturating subtract and add with
exchange
GE
SSUB16
{Rd,} Rn, Rm
Signed subtract 16
-
SSUB8
{Rd,} Rn, Rm
Signed subtract 8
-
STM
Rn{!}, reglist
Store multiple registers, increment after -
SMLABT,
SMLATB,
SMLATT
SMLAD,
SMLADX
SMLALBT,
SMLALTB,
SMLALTT
SMLSDX
SMLSLD
SMLSLDX
SMMLR
SMMUL,
SMMULR
SMUAD
SMUADX
SMULBB,
SMULBT,
SMULTB,
SMULTT
SMULWT
SMUSD,
SMUSDX
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Table 2-13. Cortex-M4F Instruction Summary (continued)
Mnemonic
Operands
Brief Description
Flags
STMDB, STMEA
Rn{!}, reglist
Store multiple registers, decrement
before
-
STMFD, STMIA
Rn{!}, reglist
Store multiple registers, increment after -
STR
Rt, [Rn {, #offset}]
Store register word
-
STRB, STRBT
Rt, [Rn {, #offset}]
Store register byte
-
STRD
Rt, Rt2, [Rn {, #offset}]
Store register two words
-
STREX
Rt, Rt, [Rn {, #offset}]
Store register exclusive
-
STREXB
Rd, Rt, [Rn]
Store register exclusive byte
-
STREXH
Rd, Rt, [Rn]
Store register exclusive halfword
-
STRH, STRHT
Rt, [Rn {, #offset}]
Store register halfword
-
STRSB, STRSBT
Rt, [Rn {, #offset}]
Store register signed byte
-
STRSH, STRSHT
Rt, [Rn {, #offset}]
Store register signed halfword
-
STRT
Rt, [Rn {, #offset}]
Store register word
-
SUB, SUBS
{Rd,} Rn, Op2
Subtract
N,Z,C,V
SUB, SUBW
{Rd,} Rn, #imm12
Subtract 12-bit constant
N,Z,C,V
SVC
#imm
Supervisor call
-
SXTAB
{Rd,} Rn, Rm, {,ROR #}
Extend 8 bits to 32 and add
-
SXTAB16
{Rd,} Rn, Rm,{,ROR #}
Dual extend 8 bits to 16 and add
-
SXTAH
{Rd,} Rn, Rm,{,ROR #}
Extend 16 bits to 32 and add
-
SXTB16
{Rd,} Rm {,ROR #n}
Signed extend byte 16
-
SXTB
{Rd,} Rm {,ROR #n}
Sign extend a byte
-
SXTH
{Rd,} Rm {,ROR #n}
Sign extend a halfword
-
TBB
[Rn, Rm]
Table branch byte
-
TBH
[Rn, Rm, LSL #1]
Table branch halfword
-
TEQ
Rn, Op2
Test equivalence
N,Z,C
TST
Rn, Op2
Test
N,Z,C
UADD16
{Rd,} Rn, Rm
Unsigned add 16
GE
UADD8
{Rd,} Rn, Rm
Unsigned add 8
GE
UASX
{Rd,} Rn, Rm
Unsigned add and subtract with
exchange
GE
UHADD16
{Rd,} Rn, Rm
Unsigned halving add 16
-
UHADD8
{Rd,} Rn, Rm
Unsigned halving add 8
-
UHASX
{Rd,} Rn, Rm
Unsigned halving add and subtract with exchange
UHSAX
{Rd,} Rn, Rm
Unsigned halving subtract and add with exchange
UHSUB16
{Rd,} Rn, Rm
Unsigned halving subtract 16
-
UHSUB8
{Rd,} Rn, Rm
Unsigned halving subtract 8
-
UBFX
Rd, Rn, #lsb, #width
Unsigned bit field extract
-
UDIV
{Rd,} Rn, Rm
Unsigned divide
-
UMAAL
RdLo, RdHi, Rn, Rm
Unsigned multiply accumulate
accumulate long (32x32+64), 64-bit
result
-
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Table 2-13. Cortex-M4F Instruction Summary (continued)
Mnemonic
Operands
Brief Description
Flags
UMLAL
RdLo, RdHi, Rn, Rm
Unsigned multiply with accumulate
(32x32+32+32), 64-bit result
-
UMULL
RdLo, RdHi, Rn, Rm
Unsigned multiply (32x 2), 64-bit result -
UQADD16
{Rd,} Rn, Rm
Unsigned Saturating Add 16
-
UQADD8
{Rd,} Rn, Rm
Unsigned Saturating Add 8
-
UQASX
{Rd,} Rn, Rm
Unsigned Saturating Add and Subtract with Exchange
UQSAX
{Rd,} Rn, Rm
Unsigned Saturating Subtract and Add with Exchange
UQSUB16
{Rd,} Rn, Rm
Unsigned Saturating Subtract 16
-
UQSUB8
{Rd,} Rn, Rm
Unsigned Saturating Subtract 8
-
USAD8
{Rd,} Rn, Rm
Unsigned Sum of Absolute Differences -
USADA8
{Rd,} Rn, Rm, Ra
Unsigned Sum of Absolute Differences and Accumulate
USAT
Rd, #n, Rm {,shift #s}
Unsigned Saturate
Q
USAT16
Rd, #n, Rm
Unsigned Saturate 16
Q
USAX
{Rd,} Rn, Rm
Unsigned Subtract and add with
Exchange
GE
USUB16
{Rd,} Rn, Rm
Unsigned Subtract 16
GE
USUB8
{Rd,} Rn, Rm
Unsigned Subtract 8
GE
UXTAB
{Rd,} Rn, Rm, {,ROR #}
Rotate, extend 8 bits to 32 and Add
-
UXTAB16
{Rd,} Rn, Rm, {,ROR #}
Rotate, dual extend 8 bits to 16 and Add -
UXTAH
{Rd,} Rn, Rm, {,ROR #}
Rotate, unsigned extend and Add
Halfword
-
UXTB
{Rd,} Rm, {,ROR #n}
Zero extend a Byte
-
UXTB16
{Rd,} Rm, {,ROR #n}
Unsigned Extend Byte 16
-
UXTH
{Rd,} Rm, {,ROR #n}
Zero extend a Halfword
-
VABS.F32
Sd, Sm
Floating-point Absolute
-
VADD.F32
{Sd,} Sn, Sm
Floating-point Add
-
VCMP.F32
Sd,
Compare two floating-point registers, or FPSCR
one floating-point register and zero
VCMPE.F32
Sd,
Compare two floating-point registers, or FPSCR
one floating-point register and zero with
Invalid Operation check
VCVT.S32.F32
Sd, Sm
Convert between floating-point and
integer
VCVT.S16.F32
Sd, Sd, #fbits
Convert between floating-point and fixed point
VCVTR.S32.F32
Sd, Sm
Convert between floating-point and
integer with rounding
-
VCVT.F32.F16
Sd, Sm
Converts half-precision value to
single-precision
-
VCVTT.F32.F16
Sd, Sm
Converts single-precision register to
half-precision
-
VDIV.F32
{Sd,} Sn, Sm
Floating-point Divide
-
VFMA.F32
{Sd,} Sn, Sm
Floating-point Fused Multiply Accumulate -
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Table 2-13. Cortex-M4F Instruction Summary (continued)
Mnemonic
Operands
Brief Description
Flags
VFNMA.F32
{Sd,} Sn, Sm
Floating-point Fused Negate Multiply
Accumulate
-
VFMS.F32
{Sd,} Sn, Sm
Floating-point Fused Multiply Subtract
-
VFNMS.F32
{Sd,} Sn, Sm
Floating-point Fused Negate Multiply
Subtract
-
VLDM.F
Rn{!}, list
Load Multiple extension registers
-
VLDR.F
, [Rn]
Load an extension register from memory -
VLMA.F32
{Sd,} Sn, Sm
Floating-point Multiply Accumulate
-
VLMS.F32
{Sd,} Sn, Sm
Floating-point Multiply Subtract
-
VMOV.F32
Sd, #imm
Floating-point Move immediate
-
VMOV
Sd, Sm
Floating-point Move register
-
VMOV
Sn, Rt
Copy ARM core register to single
precision
-
VMOV
Sm, Sm1, Rt, Rt2
Copy 2 ARM core registers to 2 single
precision
-
VMOV
Dd[x], Rt
Copy ARM core register to scalar
-
VMOV
Rt, Dn[x]
Copy scalar to ARM core register
-
VMRS
Rt, FPSCR
Move FPSCR to ARM core register or
APSR
N,Z,C,V
VMSR
FPSCR, Rt
Move to FPSCR from ARM Core register FPSCR
VMUL.F32
{Sd,} Sn, Sm
Floating-point Multiply
-
VNEG.F32
Sd, Sm
Floating-point Negate
-
VNMLA.F32
{Sd,} Sn, Sm
Floating-point Multiply and Add
-
VNMLS.F32
{Sd,} Sn, Sm
Floating-point Multiply and Subtract
-
VNMUL
{Sd,} Sn, Sm
Floating-point Multiply
-
VPOP
list
Pop extension registers
-
VPUSH
list
Push extension registers
-
VSQRT.F32
Sd, Sm
Calculates floating-point Square Root
-
VSTM
Rn{!}, list
Floating-point register Store Multiple
-
VSTR.F3
Sd, [Rn]
Stores an extension register to memory -
VSUB.F
{Sd,} Sn, Sm
Floating-point Subtract
-
WFE
-
Wait for event
-
WFI
-
Wait for interrupt
-
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3
Cortex-M4 Peripherals
This chapter provides information on the Tiva™ C Series implementation of the Cortex-M4 processor
peripherals, including:
■ SysTick (see page 119)
Provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible
control mechanism.
■ Nested Vectored Interrupt Controller (NVIC) (see page 120)
– Facilitates low-latency exception and interrupt handling
– Controls power management
– Implements system control registers
■ System Control Block (SCB) (see page 121)
Provides system implementation information and system control, including configuration, control,
and reporting of system exceptions.
■ Memory Protection Unit (MPU) (see page 121)
Supports the standard ARMv7 Protected Memory System Architecture (PMSA) model. The MPU
provides full support for protection regions, overlapping protection regions, access permissions,
and exporting memory attributes to the system.
■ Floating-Point Unit (FPU) (see page 126)
Fully supports single-precision add, subtract, multiply, divide, multiply and accumulate, and
square root operations. It also provides conversions between fixed-point and floating-point data
formats, and floating-point constant instructions.
Table 3-1 on page 118 shows the address map of the Private Peripheral Bus (PPB). Some peripheral
register regions are split into two address regions, as indicated by two addresses listed.
Table 3-1. Core Peripheral Register Regions
Address
Core Peripheral
Description (see page ...)
0xE000.E010-0xE000.E01F
System Timer
119
0xE000.E100-0xE000.E4EF
Nested Vectored Interrupt Controller
120
System Control Block
121
0xE000.ED90-0xE000.EDB8
Memory Protection Unit
121
0xE000.EF30-0xE000.EF44
Floating Point Unit
126
0xE000.EF00-0xE000.EF03
0xE000.E008-0xE000.E00F
0xE000.ED00-0xE000.ED3F
3.1
Functional Description
This chapter provides information on the Tiva™ C Series implementation of the Cortex-M4 processor
peripherals: SysTick, NVIC, SCB, MPU, FPU.
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3.1.1
System Timer (SysTick)
Cortex-M4 includes an integrated system timer, SysTick, which provides a simple, 24-bit
clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter
can be used in several different ways, for example as:
■ An RTOS tick timer that fires at a programmable rate (for example, 100 Hz) and invokes a SysTick
routine.
■ A high-speed alarm timer using the system clock.
■ A variable rate alarm or signal timer—the duration is range-dependent on the reference clock
used and the dynamic range of the counter.
■ A simple counter used to measure time to completion and time used.
■ An internal clock source control based on missing/meeting durations. The COUNT bit in the
STCTRL control and status register can be used to determine if an action completed within a
set duration, as part of a dynamic clock management control loop.
The timer consists of three registers:
■ SysTick Control and Status (STCTRL): A control and status counter to configure its clock,
enable the counter, enable the SysTick interrupt, and determine counter status.
■ SysTick Reload Value (STRELOAD): The reload value for the counter, used to provide the
counter's wrap value.
■ SysTick Current Value (STCURRENT): The current value of the counter.
When enabled, the timer counts down on each clock from the reload value to zero, reloads (wraps)
to the value in the STRELOAD register on the next clock edge, then decrements on subsequent
clocks. Clearing the STRELOAD register disables the counter on the next wrap. When the counter
reaches zero, the COUNT status bit is set. The COUNT bit clears on reads.
Writing to the STCURRENT register clears the register and the COUNT status bit. The write does
not trigger the SysTick exception logic. On a read, the current value is the value of the register at
the time the register is accessed.
The SysTick counter runs on either the system clock or the precision internal oscillator (PIOSC)
divided by 4. If this clock signal is stopped for low power mode, the SysTick counter stops. SysTick
can be kept running during Deep-sleep mode by setting the CLK_SRC bit in the SysTick Control
and Status Register (STCTRL) register and ensuring that the PIOSCPD bit in the Deep Sleep
Clock Configuration (DSLPCLKCFG) register is clear. Ensure software uses aligned word accesses
to access the SysTick registers.
The SysTick counter reload and current value are undefined at reset; the correct initialization
sequence for the SysTick counter is:
1. Program the value in the STRELOAD register.
2. Clear the STCURRENT register by writing to it with any value.
3. Configure the STCTRL register for the required operation.
Note:
When the processor is halted for debugging, the counter does not decrement.
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3.1.2
Nested Vectored Interrupt Controller (NVIC)
This section describes the Nested Vectored Interrupt Controller (NVIC) and the registers it uses.
The NVIC supports:
■ 95 interrupts.
■ A programmable priority level of 0-7 for each interrupt. A higher level corresponds to a lower
priority, so level 0 is the highest interrupt priority.
■ Low-latency exception and interrupt handling.
■ Level and pulse detection of interrupt signals.
■ Dynamic reprioritization of interrupts.
■ Grouping of priority values into group priority and subpriority fields.
■ Interrupt tail-chaining.
■ An external Non-maskable interrupt (NMI).
The processor automatically stacks its state on exception entry and unstacks this state on exception
exit, with no instruction overhead, providing low latency exception handling.
3.1.2.1
Level-Sensitive and Pulse Interrupts
The processor supports both level-sensitive and pulse interrupts. Pulse interrupts are also described
as edge-triggered interrupts.
A level-sensitive interrupt is held asserted until the peripheral deasserts the interrupt signal. Typically
this happens because the ISR accesses the peripheral, causing it to clear the interrupt request. A
pulse interrupt is an interrupt signal sampled synchronously on the rising edge of the processor
clock. To ensure the NVIC detects the interrupt, the peripheral must assert the interrupt signal for
at least one clock cycle, during which the NVIC detects the pulse and latches the interrupt.
When the processor enters the ISR, it automatically removes the pending state from the interrupt
(see “Hardware and Software Control of Interrupts” on page 120 for more information). For a
level-sensitive interrupt, if the signal is not deasserted before the processor returns from the ISR,
the interrupt becomes pending again, and the processor must execute its ISR again. As a result,
the peripheral can hold the interrupt signal asserted until it no longer needs servicing.
3.1.2.2
Hardware and Software Control of Interrupts
The Cortex-M4 latches all interrupts. A peripheral interrupt becomes pending for one of the following
reasons:
■ The NVIC detects that the interrupt signal is High and the interrupt is not active.
■ The NVIC detects a rising edge on the interrupt signal.
■ Software writes to the corresponding interrupt set-pending register bit, or to the Software Trigger
Interrupt (SWTRIG) register to make a Software-Generated Interrupt pending. See the INT bit
in the PEND0 register on page 142 or SWTRIG on page 152.
A pending interrupt remains pending until one of the following:
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■ The processor enters the ISR for the interrupt, changing the state of the interrupt from pending
to active. Then:
– For a level-sensitive interrupt, when the processor returns from the ISR, the NVIC samples
the interrupt signal. If the signal is asserted, the state of the interrupt changes to pending,
which might cause the processor to immediately re-enter the ISR. Otherwise, the state of the
interrupt changes to inactive.
– For a pulse interrupt, the NVIC continues to monitor the interrupt signal, and if this is pulsed
the state of the interrupt changes to pending and active. In this case, when the processor
returns from the ISR the state of the interrupt changes to pending, which might cause the
processor to immediately re-enter the ISR.
If the interrupt signal is not pulsed while the processor is in the ISR, when the processor
returns from the ISR the state of the interrupt changes to inactive.
■ Software writes to the corresponding interrupt clear-pending register bit
– For a level-sensitive interrupt, if the interrupt signal is still asserted, the state of the interrupt
does not change. Otherwise, the state of the interrupt changes to inactive.
– For a pulse interrupt, the state of the interrupt changes to inactive, if the state was pending
or to active, if the state was active and pending.
3.1.3
System Control Block (SCB)
The System Control Block (SCB) provides system implementation information and system control,
including configuration, control, and reporting of the system exceptions.
3.1.4
Memory Protection Unit (MPU)
This section describes the Memory protection unit (MPU). The MPU divides the memory map into
a number of regions and defines the location, size, access permissions, and memory attributes of
each region. The MPU supports independent attribute settings for each region, overlapping regions,
and export of memory attributes to the system.
The memory attributes affect the behavior of memory accesses to the region. The Cortex-M4 MPU
defines eight separate memory regions, 0-7, and a background region.
When memory regions overlap, a memory access is affected by the attributes of the region with the
highest number. For example, the attributes for region 7 take precedence over the attributes of any
region that overlaps region 7.
The background region has the same memory access attributes as the default memory map, but is
accessible from privileged software only.
The Cortex-M4 MPU memory map is unified, meaning that instruction accesses and data accesses
have the same region settings.
If a program accesses a memory location that is prohibited by the MPU, the processor generates
a memory management fault, causing a fault exception and possibly causing termination of the
process in an OS environment. In an OS environment, the kernel can update the MPU region setting
dynamically based on the process to be executed. Typically, an embedded OS uses the MPU for
memory protection.
Configuration of MPU regions is based on memory types (see “Memory Regions, Types and
Attributes” on page 90 for more information).
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Table 3-2 on page 122 shows the possible MPU region attributes. See the section called “MPU
Configuration for a Tiva™ C Series Microcontroller” on page 126 for guidelines for programming a
microcontroller implementation.
Table 3-2. Memory Attributes Summary
Memory Type
Description
Strongly Ordered
All accesses to Strongly Ordered memory occur in program order.
Device
Memory-mapped peripherals
Normal
Normal memory
To avoid unexpected behavior, disable the interrupts before updating the attributes of a region that
the interrupt handlers might access.
Ensure software uses aligned accesses of the correct size to access MPU registers:
■ Except for the MPU Region Attribute and Size (MPUATTR) register, all MPU registers must
be accessed with aligned word accesses.
■ The MPUATTR register can be accessed with byte or aligned halfword or word accesses.
The processor does not support unaligned accesses to MPU registers.
When setting up the MPU, and if the MPU has previously been programmed, disable unused regions
to prevent any previous region settings from affecting the new MPU setup.
3.1.4.1
Updating an MPU Region
To update the attributes for an MPU region, the MPU Region Number (MPUNUMBER), MPU
Region Base Address (MPUBASE) and MPUATTR registers must be updated. Each register can
be programmed separately or with a multiple-word write to program all of these registers. You can
use the MPUBASEx and MPUATTRx aliases to program up to four regions simultaneously using
an STM instruction.
Updating an MPU Region Using Separate Words
This example simple code configures one region:
; R1 = region number
; R2 = size/enable
; R3 = attributes
; R4 = address
LDR R0,=MPUNUMBER
STR R1, [R0, #0x0]
STR R4, [R0, #0x4]
STRH R2, [R0, #0x8]
STRH R3, [R0, #0xA]
;
;
;
;
;
0xE000ED98, MPU region number register
Region Number
Region Base Address
Region Size and Enable
Region Attribute
Disable a region before writing new region settings to the MPU if you have previously enabled the
region being changed. For example:
; R1 = region number
; R2 = size/enable
; R3 = attributes
; R4 = address
LDR R0,=MPUNUMBER
; 0xE000ED98, MPU region number register
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STR R1, [R0, #0x0]
BIC R2, R2, #1
STRH R2, [R0, #0x8]
STR R4, [R0, #0x4]
STRH R3, [R0, #0xA]
ORR R2, #1
STRH R2, [R0, #0x8]
;
;
;
;
;
;
;
Region Number
Disable
Region Size and Enable
Region Base Address
Region Attribute
Enable
Region Size and Enable
Software must use memory barrier instructions:
■ Before MPU setup, if there might be outstanding memory transfers, such as buffered writes, that
might be affected by the change in MPU settings.
■ After MPU setup, if it includes memory transfers that must use the new MPU settings.
However, memory barrier instructions are not required if the MPU setup process starts by entering
an exception handler, or is followed by an exception return, because the exception entry and
exception return mechanism cause memory barrier behavior.
Software does not need any memory barrier instructions during MPU setup, because it accesses
the MPU through the Private Peripheral Bus (PPB), which is a Strongly Ordered memory region.
For example, if all of the memory access behavior is intended to take effect immediately after the
programming sequence, then a DSB instruction and an ISB instruction should be used. A DSB is
required after changing MPU settings, such as at the end of context switch. An ISB is required if
the code that programs the MPU region or regions is entered using a branch or call. If the
programming sequence is entered using a return from exception, or by taking an exception, then
an ISB is not required.
Updating an MPU Region Using Multi-Word Writes
The MPU can be programmed directly using multi-word writes, depending how the information is
divided. Consider the following reprogramming:
; R1 = region number
; R2 = address
; R3 = size, attributes in one
LDR R0, =MPUNUMBER ; 0xE000ED98, MPU region number register
STR R1, [R0, #0x0] ; Region Number
STR R2, [R0, #0x4] ; Region Base Address
STR R3, [R0, #0x8] ; Region Attribute, Size and Enable
An STM instruction can be used to optimize this:
; R1 = region number
; R2 = address
; R3 = size, attributes in one
LDR R0, =MPUNUMBER ; 0xE000ED98, MPU region number register
STM R0, {R1-R3}
; Region number, address, attribute, size and enable
This operation can be done in two words for prepacked information, meaning that the MPU Region
Base Address (MPUBASE) register (see page 186) contains the required region number and has
the VALID bit set. This method can be used when the data is statically packed, for example in a
boot loader:
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; R1 = address and region number in one
; R2 = size and attributes in one
LDR R0, =MPUBASE
; 0xE000ED9C, MPU Region Base register
STR R1, [R0, #0x0] ; Region base address and region number combined
; with VALID (bit 4) set
STR R2, [R0, #0x4] ; Region Attribute, Size and Enable
Subregions
Regions of 256 bytes or more are divided into eight equal-sized subregions. Set the corresponding
bit in the SRD field of the MPU Region Attribute and Size (MPUATTR) register (see page 188) to
disable a subregion. The least-significant bit of the SRD field controls the first subregion, and the
most-significant bit controls the last subregion. Disabling a subregion means another region
overlapping the disabled range matches instead. If no other enabled region overlaps the disabled
subregion, the MPU issues a fault.
Regions of 32, 64, and 128 bytes do not support subregions. With regions of these sizes, the SRD
field must be configured to 0x00, otherwise the MPU behavior is unpredictable.
Example of SRD Use
Two regions with the same base address overlap. Region one is 128 KB, and region two is 512 KB.
To ensure the attributes from region one apply to the first 128 KB region, configure the SRD field for
region two to 0x03 to disable the first two subregions, as Figure 3-1 on page 124 shows.
Figure 3-1. SRD Use Example
Region 2, with
subregions
Region 1
Base address of both regions
3.1.4.2
Offset from
base address
512KB
448KB
384KB
320KB
256KB
192KB
128KB
Disabled subregion
64KB
Disabled subregion
0
MPU Access Permission Attributes
The access permission bits, TEX, S, C, B, AP, and XN of the MPUATTR register, control access to
the corresponding memory region. If an access is made to an area of memory without the required
permissions, then the MPU generates a permission fault.
Table 3-3 on page 124 shows the encodings for the TEX, C, B, and S access permission bits. All
encodings are shown for completeness, however the current implementation of the Cortex-M4 does
not support the concept of cacheability or shareability. Refer to the section called “MPU Configuration
for a Tiva™ C Series Microcontroller” on page 126 for information on programming the MPU for
TM4C123BH6PGE implementations.
Table 3-3. TEX, S, C, and B Bit Field Encoding
TEX
S
000b
x
000
B
Memory Type
Shareability
Other Attributes
0
0
Strongly Ordered
Shareable
-
a
0
1
Device
Shareable
-
x
C
a
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Table 3-3. TEX, S, C, and B Bit Field Encoding (continued)
TEX
S
C
B
Memory Type
Shareability
000
0
1
0
Normal
Not shareable
000
1
1
0
Normal
Shareable
000
0
1
1
Normal
Not shareable
000
1
1
1
Normal
Shareable
Other Attributes
Outer and inner
write-through. No write
allocate.
001
0
0
0
Normal
Not shareable
001
1
0
0
Normal
Shareable
Outer and inner
non-cacheable.
001
x
a
0
1
Reserved encoding
-
-
a
001
x
1
0
Reserved encoding
-
-
001
0
1
1
Normal
Not shareable
001
1
1
1
Normal
Shareable
Outer and inner
write-back. Write and
read allocate.
010
x
a
0
0
Device
Not shareable
Nonshared Device.
a
a
010
x
0
1
Reserved encoding
-
-
010
x
1
x
Reserved encoding
-
-
1BB
0
A
A
Normal
Not shareable
1BB
1
A
A
Normal
Shareable
Cached memory (BB =
outer policy, AA = inner
policy).
a
See Table 3-4 for the
encoding of the AA and
BB bits.
a. The MPU ignores the value of this bit.
Table 3-4 on page 125 shows the cache policy for memory attribute encodings with a TEX value in
the range of 0x4-0x7.
Table 3-4. Cache Policy for Memory Attribute Encoding
Encoding, AA or BB
Corresponding Cache Policy
00
Non-cacheable
01
Write back, write and read allocate
10
Write through, no write allocate
11
Write back, no write allocate
Table 3-5 on page 125 shows the AP encodings in the MPUATTR register that define the access
permissions for privileged and unprivileged software.
Table 3-5. AP Bit Field Encoding
AP Bit Field
Privileged
Permissions
Unprivileged
Permissions
Description
000
No access
No access
All accesses generate a permission fault.
001
RW
No access
Access from privileged software only.
010
RW
RO
Writes by unprivileged software generate a
permission fault.
011
RW
RW
Full access.
100
Unpredictable
Unpredictable
Reserved.
101
RO
No access
Reads by privileged software only.
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Table 3-5. AP Bit Field Encoding (continued)
AP Bit Field
Privileged
Permissions
Unprivileged
Permissions
Description
110
RO
RO
Read-only, by privileged or unprivileged software.
111
RO
RO
Read-only, by privileged or unprivileged software.
MPU Configuration for a Tiva™ C Series Microcontroller
Tiva™ C Series microcontrollers have only a single processor and no caches. As a result, the MPU
should be programmed as shown in Table 3-6 on page 126.
Table 3-6. Memory Region Attributes for Tiva™ C Series Microcontrollers
Memory Region
TEX
S
C
B
Memory Type and Attributes
Flash memory
000b
0
1
0
Normal memory, non-shareable, write-through
Internal SRAM
000b
1
1
0
Normal memory, shareable, write-through
External SRAM
000b
1
1
1
Normal memory, shareable, write-back,
write-allocate
Peripherals
000b
1
0
1
Device memory, shareable
In current Tiva™ C Series microcontroller implementations, the shareability and cache policy
attributes do not affect the system behavior. However, using these settings for the MPU regions
can make the application code more portable. The values given are for typical situations.
3.1.4.3
MPU Mismatch
When an access violates the MPU permissions, the processor generates a memory management
fault (see “Exceptions and Interrupts” on page 87 for more information). The MFAULTSTAT register
indicates the cause of the fault. See page 173 for more information.
3.1.5
Floating-Point Unit (FPU)
This section describes the Floating-Point Unit (FPU) and the registers it uses. The FPU provides:
■ 32-bit instructions for single-precision (C float) data-processing operations
■ Combined multiply and accumulate instructions for increased precision (Fused MAC)
■ Hardware support for conversion, addition, subtraction, multiplication with optional accumulate,
division, and square-root
■ Hardware support for denormals and all IEEE rounding modes
■ 32 dedicated 32-bit single-precision registers, also addressable as 16 double-word registers
■ Decoupled three stage pipeline
The Cortex-M4F FPU fully supports single-precision add, subtract, multiply, divide, multiply and
accumulate, and square root operations. It also provides conversions between fixed-point and
floating-point data formats, and floating-point constant instructions. The FPU provides floating-point
computation functionality that is compliant with the ANSI/IEEE Std 754-2008, IEEE Standard for
Binary Floating-Point Arithmetic, referred to as the IEEE 754 standard. The FPU's single-precision
extension registers can also be accessed as 16 doubleword registers for load, store, and move
operations.
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3.1.5.1
FPU Views of the Register Bank
The FPU provides an extension register file containing 32 single-precision registers. These can be
viewed as:
■ Sixteen 64-bit doubleword registers, D0-D15
■ Thirty-two 32-bit single-word registers, S0-S31
■ A combination of registers from the above views
Figure 3-2. FPU Register Bank
S0
S1
S2
S3
S4
S5
S6
S7
...
S28
S29
S30
S31
D0
D1
D2
D3
...
D14
D15
The mapping between the registers is as follows:
■ S maps to the least significant half of D
■ S maps to the most significant half of D
For example, you can access the least significant half of the value in D6 by accessing S12, and the
most significant half of the elements by accessing S13.
3.1.5.2
Modes of Operation
The FPU provides three modes of operation to accommodate a variety of applications.
Full-Compliance mode. In Full-Compliance mode, the FPU processes all operations according to
the IEEE 754 standard in hardware.
Flush-to-Zero mode. Setting the FZ bit of the Floating-Point Status and Control (FPSC) register
enables Flush-to-Zero mode. In this mode, the FPU treats all subnormal input operands of arithmetic
CDP operations as zeros in the operation. Exceptions that result from a zero operand are signalled
appropriately. VABS, VNEG, and VMOV are not considered arithmetic CDP operations and are not
affected by Flush-to-Zero mode. A result that is tiny, as described in the IEEE 754 standard, where
the destination precision is smaller in magnitude than the minimum normal value before rounding,
is replaced with a zero. The IDC bit in FPSC indicates when an input flush occurs. The UFC bit in
FPSC indicates when a result flush occurs.
Default NaN mode. Setting the DN bit in the FPSC register enables default NaN mode. In this mode,
the result of any arithmetic data processing operation that involves an input NaN, or that generates
a NaN result, returns the default NaN. Propagation of the fraction bits is maintained only by VABS,
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VNEG, and VMOV operations. All other CDP operations ignore any information in the fraction bits
of an input NaN.
3.1.5.3
Compliance with the IEEE 754 standard
When Default NaN (DN) and Flush-to-Zero (FZ) modes are disabled, FPv4 functionality is compliant
with the IEEE 754 standard in hardware. No support code is required to achieve this compliance.
3.1.5.4
Complete Implementation of the IEEE 754 standard
The Cortex-M4F floating point instruction set does not support all operations defined in the IEEE
754-2008 standard. Unsupported operations include, but are not limited to the following:
■ Remainder
■ Round floating-point number to integer-valued floating-point number
■ Binary-to-decimal conversions
■ Decimal-to-binary conversions
■ Direct comparison of single-precision and double-precision values
The Cortex-M4 FPU supports fused MAC operations as described in the IEEE standard. For complete
implementation of the IEEE 754-2008 standard, floating-point functionality must be augmented with
library functions.
3.1.5.5
IEEE 754 standard implementation choices
NaN handling
All single-precision values with the maximum exponent field value and a nonzero fraction field are
valid NaNs. A most-significant fraction bit of zero indicates a Signaling NaN (SNaN). A one indicates
a Quiet NaN (QNaN). Two NaN values are treated as different NaNs if they differ in any bit. The
below table shows the default NaN values.
Sign
Fraction
Fraction
0
0xFF
bit [22] = 1, bits [21:0] are all zeros
Processing of input NaNs for ARM floating-point functionality and libraries is defined as follows:
■ In full-compliance mode, NaNs are handled as described in the ARM Architecture Reference
Manual. The hardware processes the NaNs directly for arithmetic CDP instructions. For data
transfer operations, NaNs are transferred without raising the Invalid Operation exception. For
the non-arithmetic CDP instructions, VABS, VNEG, and VMOV, NaNs are copied, with a change
of sign if specified in the instructions, without causing the Invalid Operation exception.
■ In default NaN mode, arithmetic CDP instructions involving NaN operands return the default
NaN regardless of the fractions of any NaN operands. SNaNs in an arithmetic CDP operation
set the IOC flag, FPSCR[0]. NaN handling by data transfer and non-arithmetic CDP instructions
is the same as in full-compliance mode.
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Table 3-7. QNaN and SNaN Handling
Instruction Type
Default NaN
Mode
With QNaN Operand
With SNaN Operand
Off
The QNaN or one of the QNaN operands,
if there is more than one, is returned
according to the rules given in the ARM
Architecture Reference Manual.
IOC set. The SNaN is quieted and the
result NaN is determined by the rules
given in the ARM Architecture Reference
Manual.
On
Default NaN returns.
IOC set. Default NaN returns.
Arithmetic CDP
Non-arithmetic CDP Off/On
a
a
NaN passes to destination with sign changed as appropriate.
FCMP(Z)
-
Unordered compare.
IOC set. Unordered compare.
FCMPE(Z)
-
IOC set. Unordered compare.
IOC set. Unordered compare.
Load/store
Off/On
All NaNs transferred.
a. IOC is the Invalid Operation exception flag, FPSCR[0].
Comparisons
Comparison results modify the flags in the FPSCR. You can use the MVRS APSR_nzcv instruction
(formerly FMSTAT) to transfer the current flags from the FPSCR to the APSR. See the ARM
Architecture Reference Manual for mapping of IEEE 754-2008 standard predicates to ARM conditions.
The flags used are chosen so that subsequent conditional execution of ARM instructions can test
the predicates defined in the IEEE standard.
Underflow
The Cortex-M4F FPU uses the before rounding form of tininess and the inexact result form of loss
of accuracy as described in the IEEE 754-2008 standard to generate Underflow exceptions.
In flush-to-zero mode, results that are tiny before rounding, as described in the IEEE standard, are
flushed to a zero, and the UFC flag, FPSCR[3], is set. See the ARM Architecture Reference Manual
for information on flush-to-zero mode.
When the FPU is not in flush-to-zero mode, operations are performed on subnormal operands. If
the operation does not produce a tiny result, it returns the computed result, and the UFC flag,
FPSCR[3], is not set. The IXC flag, FPSCR[4], is set if the operation is inexact. If the operation
produces a tiny result, the result is a subnormal or zero value, and the UFC flag, FPSCR[3], is set
if the result was also inexact.
3.1.5.6
Exceptions
The FPU sets the cumulative exception status flag in the FPSCR register as required for each
instruction, in accordance with the FPv4 architecture. The FPU does not support user-mode traps.
The exception enable bits in the FPSCR read-as-zero, and writes are ignored. The processor also
has six output pins, FPIXC, FPUFC, FPOFC, FPDZC, FPIDC, and FPIOC, that each reflect the
status of one of the cumulative exception flags. For a description of these outputs, see the ARM
Cortex-M4 Integration and Implementation Manual (ARM DII 0239, available from ARM).
The processor can reduce the exception latency by using lazy stacking. See Auxiliary Control
Register, ACTLR on page 4-5. This means that the processor reserves space on the stack for the
FP state, but does not save that state information to the stack. See the ARMv7-M Architecture
Reference Manual (available from ARM) for more information.
3.1.5.7
Enabling the FPU
The FPU is disabled from reset. You must enable it before you can use any floating-point instructions.
The processor must be in privileged mode to read from and write to the Coprocessor Access
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Control (CPAC) register. The below example code sequence enables the FPU in both privileged
and user modes.
; CPACR is located at address 0xE000ED88
LDR.W R0, =0xE000ED88
; Read CPACR
LDR R1, [R0]
; Set bits 20-23 to enable CP10 and CP11 coprocessors
ORR R1, R1, #(0xF 0, then the conversion result > 0x800 (range is 0x800–0xFFF)
■ If VIND < 0, then the conversion result < 0x800 (range is 0–0x800)
When using differential sampling, the following definitions are relevant:
■ Input Common Mode Voltage: VINCM = (VIN+ + VIN-) / 2
■ Reference Positive Voltage: VREFP
■ Reference Negative Voltage: VREFN
■ Reference Differential Voltage: VREFD = VREFP - VREFN
■ Reference Common Mode Voltage: VREFCM = (VREFP + VREFN) / 2
The following conditions provide optimal results in differential mode:
■ Both VIN_EVEN and VIN_ODD must be in the range of (VREFP to VREFN) for a valid conversion
result
■ The maximum possible differential input swing, or the maximum differential range, is: -VREFDto
+VREFD, so the maximum peak-to-peak input differential signal is (+VREFD - -VREFD) = 2 *
VREFD= 2 * (VREFP - VREFN)
■ In order to take advantage of the maximum possible differential input swing, VINCM should be
very close to VREFCM, see Table 23-32 on page 1314.
If VINCM is not equal to VREFCM, the differential input signal may clip at either maximum or minimum
voltage, because either single ended input can never be larger than VREFP or smaller than VREFN,
and it is not possible to achieve full swing. Thus any difference in common mode between the input
voltage and the reference voltage limits the differential dynamic range of the ADC.
Because the maximum peak-to-peak differential signal voltage is 2 * (VREFP - VREFN), the ADC
codes are interpreted as:
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mV per ADC code = (2 *(VREFP - VREFN)) / 4096
Figure 13-10 shows how the differential voltage, ∆V, is represented in ADC codes.
Figure 13-10. Differential Voltage Representation
0xFFF
0x800
-(VREFP - VREFN)
0
VREFP - VREFN
V
- Input Saturation
13.3.6
Internal Temperature Sensor
The temperature sensor serves two primary purposes: 1) to notify the system that internal temperature
is too high or low for reliable operation and 2) to provide temperature measurements for calibration
of the Hibernate module RTC trim value.
The temperature sensor does not have a separate enable, because it also contains the bandgap
reference and must always be enabled. The reference is supplied to other analog modules; not just
the ADC. In addition, the temperature sensor has a second power-down input in the 3.3 V domain
which provides control by the Hibernation module.
The internal temperature sensor converts a temperature measurement into a voltage. This voltage
value, VTSENS, is given by the following equation (where TEMP is the temperature in °C):
VTSENS = 2.7 - ((TEMP + 55) / 75)
This relation is shown in Figure 13-11 on page 823.
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Figure 13-11. Internal Temperature Sensor Characteristic
VTSENS
VTSENS = 2.7 V – (TEMP+55)
75
2.5 V
1.633 V
0.833 V
-40° C
25° C
85° C
Temp
The temperature sensor reading can be sampled in a sample sequence by setting the TSn bit in
the ADCSSCTLn register. The temperature reading from the temperature sensor can also be given
as a function of the ADC value. The following formula calculates temperature (TEMP in ℃) based
on the ADC reading (ADCCODE, given as an unsigned decimal number from 0 to 4095) and the
maximum ADC voltage range (VREFP - VREFN):
TEMP = 147.5 - ((75 * (VREFP - VREFN) × ADCCODE) / 4096)
13.3.7
Digital Comparator Unit
An ADC is commonly used to sample an external signal and to monitor its value to ensure that it
remains in a given range. To automate this monitoring procedure and reduce the amount of processor
overhead that is required, each module provides eight digital comparators.
Conversions from the ADC that are sent to the digital comparators are compared against the user
programmable limits in the ADC Digital Comparator Range (ADCDCCMPn) registers. The ADC
can be configured to generate an interrupt depending on whether the ADC is operating within the
low, mid or high-band region configured in the ADCDCCMPn bit fields. The digital comparators four
operational modes (Once, Always, Hysteresis Once, Hysteresis Always) can be additionally applied
to the interrupt configuration.
13.3.7.1
Output Functions
ADC conversions can either be stored in the ADC Sample Sequence FIFOs or compared using the
digital comparator resources as defined by the SnDCOP bits in the ADC Sample Sequence n
Operation (ADCSSOPn) register. These selected ADC conversions are used by their respective
digital comparator to monitor the external signal. Each comparator has two possible output functions:
processor interrupts and triggers.
Each function has its own state machine to track the monitored signal. Even though the interrupt
and trigger functions can be enabled individually or both at the same time, the same conversion
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data is used by each function to determine if the right conditions have been met to assert the
associated output.
Interrupts
The digital comparator interrupt function is enabled by setting the CIE bit in the ADC Digital
Comparator Control (ADCDCCTLn) register. This bit enables the interrupt function state machine
to start monitoring the incoming ADC conversions. When the appropriate set of conditions is met,
and the DCONSSx bit is set in the ADCIM register, an interrupt is sent to the interrupt controller.
Note:
Only a single DCONSSn bit should be set at any given time. Setting more than one of these
bits results in the INRDC bit from the ADCRIS register being masked, and no interrupt is
generated on any of the sample sequencer interrupt lines. It is recommended that when
interrupts are used, they are enabled on alternating samples or at the end of the sample
sequence.
Triggers
The digital comparator trigger function is enabled by setting the CTE bit in the ADCDCCTLn register.
This bit enables the trigger function state machine to start monitoring the incoming ADC conversions.
When the appropriate set of conditions is met, the corresponding digital comparator trigger to the
PWM module is asserted.
13.3.7.2
Operational Modes
Four operational modes are provided to support a broad range of applications and multiple possible
signaling requirements: Always, Once, Hysteresis Always, and Hysteresis Once. The operational
mode is selected using the CIM or CTM field in the ADCDCCTLn register.
Always Mode
In the Always operational mode, the associated interrupt or trigger is asserted whenever the ADC
conversion value meets its comparison criteria. The result is a string of assertions on the interrupt
or trigger while the conversions are within the appropriate range.
Once Mode
In the Once operational mode, the associated interrupt or trigger is asserted whenever the ADC
conversion value meets its comparison criteria, and the previous ADC conversion value did not.
The result is a single assertion of the interrupt or trigger when the conversions are within the
appropriate range.
Hysteresis-Always Mode
The Hysteresis-Always operational mode can only be used in conjunction with the low-band or
high-band regions because the mid-band region must be crossed and the opposite region entered
to clear the hysteresis condition. In the Hysteresis-Always mode, the associated interrupt or trigger
is asserted in the following cases: 1) the ADC conversion value meets its comparison criteria or 2)
a previous ADC conversion value has met the comparison criteria, and the hysteresis condition has
not been cleared by entering the opposite region. The result is a string of assertions on the interrupt
or trigger that continue until the opposite region is entered.
Hysteresis-Once Mode
The Hysteresis-Once operational mode can only be used in conjunction with the low-band or
high-band regions because the mid-band region must be crossed and the opposite region entered
to clear the hysteresis condition. In the Hysteresis-Once mode, the associated interrupt or trigger
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is asserted only when the ADC conversion value meets its comparison criteria, the hysteresis
condition is clear, and the previous ADC conversion did not meet the comparison criteria. The result
is a single assertion on the interrupt or trigger.
13.3.7.3
Function Ranges
The two comparison values, COMP0 and COMP1, in the ADC Digital Comparator Range
(ADCDCCMPn) register effectively break the conversion area into three distinct regions. These
regions are referred to as the low-band (less than COMP0), mid-band (greater than COMP0 but less
than or equal to COMP1), and high-band (greater than or equal to COMP1) regions. COMP0 and COMP1
may be programmed to the same value, effectively creating two regions, but COMP1 must always
be greater than or equal to the value of COMP0. A COMP1 value that is less than COMP0 generates
unpredictable results.
Low-Band Operation
To operate in the low-band region, the CIC field or the CTC field in the ADCDCCTLn register must
be programmed to 0x0. This setting causes interrupts or triggers to be generated in the low-band
region as defined by the programmed operational mode. An example of the state of the
interrupt/trigger signal in the low-band region for each of the operational modes is shown in Figure
13-12 on page 825. Note that a "0" in a column following the operational mode name (Always, Once,
Hysteresis Always, and Hysteresis Once) indicates that the interrupt or trigger signal is deasserted
and a "1" indicates that the signal is asserted.
Figure 13-12. Low-Band Operation (CIC=0x0 and/or CTC=0x0)
COMP1
COMP0
Always –
0
0
0
0
1
1
1
0
0
1
1
0
0
0
0
1
Once –
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
1
Hysteresis Always –
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
Hysteresis Once –
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
Mid-Band Operation
To operate in the mid-band region, the CIC field or the CTC field in the ADCDCCTLn register must
be programmed to 0x1. This setting causes interrupts or triggers to be generated in the mid-band
region according the operation mode. Only the Always and Once operational modes are available
in the mid-band region. An example of the state of the interrupt/trigger signal in the mid-band region
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for each of the allowed operational modes is shown in Figure 13-13 on page 826. Note that a "0" in
a column following the operational mode name (Always or Once) indicates that the interrupt or
trigger signal is deasserted and a "1" indicates that the signal is asserted.
Figure 13-13. Mid-Band Operation (CIC=0x1 and/or CTC=0x1)
COMP1
COMP0
Always –
0
0
1
1
0
0
0
1
1
1
0
0
1
1
0
0
Once –
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
Hysteresis Always –
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Hysteresis Once –
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
High-Band Operation
To operate in the high-band region, the CIC field or the CTC field in the ADCDCCTLn register must
be programmed to 0x3. This setting causes interrupts or triggers to be generated in the high-band
region according the operation mode. An example of the state of the interrupt/trigger signal in the
high-band region for each of the allowed operational modes is shown in Figure 13-14 on page 827.
Note that a "0" in a column following the operational mode name (Always, Once, Hysteresis Always,
and Hysteresis Once) indicates that the interrupt or trigger signal is deasserted and a "1" indicates
that the signal is asserted.
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Figure 13-14. High-Band Operation (CIC=0x3 and/or CTC=0x3)
COMP1
COMP0
13.4
Always –
0
0
0
0
1
1
1
0
0
1
1
0
0
0
1
1
Once –
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
Hysteresis Always –
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
Hysteresis Once –
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
Initialization and Configuration
In order for the ADC module to be used, the PLL must be enabled and programmed to a supported
crystal frequency in the RCC register (see page 248). Using unsupported frequencies can cause
faulty operation in the ADC module.
13.4.1
Module Initialization
Initialization of the ADC module is a simple process with very few steps: enabling the clock to the
ADC, disabling the analog isolation circuit associated with all inputs that are to be used, and
reconfiguring the sample sequencer priorities (if needed).
The initialization sequence for the ADC is as follows:
1. Enable the ADC clock using the RCGCADC register (see page 347).
2. Enable the clock to the appropriate GPIO modules via the RCGCGPIO register (see page 335).
To find out which GPIO ports to enable, refer to “Signal Description” on page 810.
3. Set the GPIO AFSEL bits for the ADC input pins (see page 676). To determine which GPIOs to
configure, see Table 22-4 on page 1262.
4. Configure the AINx signals to be analog inputs by clearing the corresponding DEN bit in the
GPIO Digital Enable (GPIODEN) register (see page 688).
5. Disable the analog isolation circuit for all ADC input pins that are to be used by writing a 1 to
the appropriate bits of the GPIOAMSEL register (see page 693) in the associated GPIO block.
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6. If required by the application, reconfigure the sample sequencer priorities in the ADCSSPRI
register. The default configuration has Sample Sequencer 0 with the highest priority and Sample
Sequencer 3 as the lowest priority.
13.4.2
Sample Sequencer Configuration
Configuration of the sample sequencers is slightly more complex than the module initialization
because each sample sequencer is completely programmable.
The configuration for each sample sequencer should be as follows:
1. Ensure that the sample sequencer is disabled by clearing the corresponding ASENn bit in the
ADCACTSS register. Programming of the sample sequencers is allowed without having them
enabled. Disabling the sequencer during programming prevents erroneous execution if a trigger
event were to occur during the configuration process.
2. Configure the trigger event for the sample sequencer in the ADCEMUX register.
3. When using a PWM generator as the trigger source, use the ADC Trigger Source Select
(ADCTSSEL) register to specify in which PWM module the generator is located. The default
register reset selects PWM module 0 for all generators.
4. For each sample in the sample sequence, configure the corresponding input source in the
ADCSSMUXn and ADCSSEMUXn registers.
5. For each sample in the sample sequence, configure the sample control bits in the corresponding
nibble in the ADCSSCTLn register. When programming the last nibble, ensure that the END bit
is set. Failure to set the END bit causes unpredictable behavior.
6. If interrupts are to be used, set the corresponding MASK bit in the ADCIM register.
7. Enable the sample sequencer logic by setting the corresponding ASENn bit in the ADCACTSS
register.
13.5
Register Map
Table 13-4 on page 828 lists the ADC registers. The offset listed is a hexadecimal increment to the
register's address, relative to that ADC module's base address of:
■ ADC0: 0x4003.8000
■ ADC1: 0x4003.9000
Note that the ADC module clock must be enabled before the registers can be programmed (see
page 347). There must be a delay of 3 system clocks after the ADC module clock is enabled before
any ADC module registers are accessed.
Table 13-4. ADC Register Map
Offset
Name
0x000
Description
See
page
Type
Reset
ADCACTSS
RW
0x0000.0000
ADC Active Sample Sequencer
831
0x004
ADCRIS
RO
0x0000.0000
ADC Raw Interrupt Status
833
0x008
ADCIM
RW
0x0000.0000
ADC Interrupt Mask
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Table 13-4. ADC Register Map (continued)
Offset
Name
0x00C
Description
See
page
Type
Reset
ADCISC
RW1C
0x0000.0000
ADC Interrupt Status and Clear
838
0x010
ADCOSTAT
RW1C
0x0000.0000
ADC Overflow Status
841
0x014
ADCEMUX
RW
0x0000.0000
ADC Event Multiplexer Select
843
0x018
ADCUSTAT
RW1C
0x0000.0000
ADC Underflow Status
848
0x01C
ADCTSSEL
RW
0x0000.0000
ADC Trigger Source Select
849
0x020
ADCSSPRI
RW
0x0000.3210
ADC Sample Sequencer Priority
851
0x024
ADCSPC
RW
0x0000.0000
ADC Sample Phase Control
853
0x028
ADCPSSI
RW
-
ADC Processor Sample Sequence Initiate
855
0x030
ADCSAC
RW
0x0000.0000
ADC Sample Averaging Control
857
0x034
ADCDCISC
RW1C
0x0000.0000
ADC Digital Comparator Interrupt Status and Clear
858
0x038
ADCCTL
RW
0x0000.0000
ADC Control
860
0x040
ADCSSMUX0
RW
0x0000.0000
ADC Sample Sequence Input Multiplexer Select 0
861
0x044
ADCSSCTL0
RW
0x0000.0000
ADC Sample Sequence Control 0
863
0x048
ADCSSFIFO0
RO
-
ADC Sample Sequence Result FIFO 0
870
0x04C
ADCSSFSTAT0
RO
0x0000.0100
ADC Sample Sequence FIFO 0 Status
871
0x050
ADCSSOP0
RW
0x0000.0000
ADC Sample Sequence 0 Operation
873
0x054
ADCSSDC0
RW
0x0000.0000
ADC Sample Sequence 0 Digital Comparator Select
875
0x058
ADCSSEMUX0
RW
0x0000.0000
ADC Sample Sequence Extended Input Multiplexer Select
0
877
0x060
ADCSSMUX1
RW
0x0000.0000
ADC Sample Sequence Input Multiplexer Select 1
879
0x064
ADCSSCTL1
RW
0x0000.0000
ADC Sample Sequence Control 1
880
0x068
ADCSSFIFO1
RO
-
ADC Sample Sequence Result FIFO 1
870
0x06C
ADCSSFSTAT1
RO
0x0000.0100
ADC Sample Sequence FIFO 1 Status
871
0x070
ADCSSOP1
RW
0x0000.0000
ADC Sample Sequence 1 Operation
884
0x074
ADCSSDC1
RW
0x0000.0000
ADC Sample Sequence 1 Digital Comparator Select
885
0x078
ADCSSEMUX1
RW
0x0000.0000
ADC Sample Sequence Extended Input Multiplexer Select
1
887
0x080
ADCSSMUX2
RW
0x0000.0000
ADC Sample Sequence Input Multiplexer Select 2
879
0x084
ADCSSCTL2
RW
0x0000.0000
ADC Sample Sequence Control 2
880
0x088
ADCSSFIFO2
RO
-
ADC Sample Sequence Result FIFO 2
870
0x08C
ADCSSFSTAT2
RO
0x0000.0100
ADC Sample Sequence FIFO 2 Status
871
0x090
ADCSSOP2
RW
0x0000.0000
ADC Sample Sequence 2 Operation
884
0x094
ADCSSDC2
RW
0x0000.0000
ADC Sample Sequence 2 Digital Comparator Select
885
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Analog-to-Digital Converter (ADC)
Table 13-4. ADC Register Map (continued)
Offset
Name
0x098
See
page
Type
Reset
ADCSSEMUX2
RW
0x0000.0000
ADC Sample Sequence Extended Input Multiplexer Select
2
887
0x0A0
ADCSSMUX3
RW
0x0000.0000
ADC Sample Sequence Input Multiplexer Select 3
889
0x0A4
ADCSSCTL3
RW
0x0000.0000
ADC Sample Sequence Control 3
890
0x0A8
ADCSSFIFO3
RO
-
ADC Sample Sequence Result FIFO 3
870
0x0AC
ADCSSFSTAT3
RO
0x0000.0100
ADC Sample Sequence FIFO 3 Status
871
0x0B0
ADCSSOP3
RW
0x0000.0000
ADC Sample Sequence 3 Operation
892
0x0B4
ADCSSDC3
RW
0x0000.0000
ADC Sample Sequence 3 Digital Comparator Select
893
0x0B8
ADCSSEMUX3
RW
0x0000.0000
ADC Sample Sequence Extended Input Multiplexer Select
3
894
0xD00
ADCDCRIC
WO
0x0000.0000
ADC Digital Comparator Reset Initial Conditions
895
0xE00
ADCDCCTL0
RW
0x0000.0000
ADC Digital Comparator Control 0
900
0xE04
ADCDCCTL1
RW
0x0000.0000
ADC Digital Comparator Control 1
900
0xE08
ADCDCCTL2
RW
0x0000.0000
ADC Digital Comparator Control 2
900
0xE0C
ADCDCCTL3
RW
0x0000.0000
ADC Digital Comparator Control 3
900
0xE10
ADCDCCTL4
RW
0x0000.0000
ADC Digital Comparator Control 4
900
0xE14
ADCDCCTL5
RW
0x0000.0000
ADC Digital Comparator Control 5
900
0xE18
ADCDCCTL6
RW
0x0000.0000
ADC Digital Comparator Control 6
900
0xE1C
ADCDCCTL7
RW
0x0000.0000
ADC Digital Comparator Control 7
900
0xE40
ADCDCCMP0
RW
0x0000.0000
ADC Digital Comparator Range 0
903
0xE44
ADCDCCMP1
RW
0x0000.0000
ADC Digital Comparator Range 1
903
0xE48
ADCDCCMP2
RW
0x0000.0000
ADC Digital Comparator Range 2
903
0xE4C
ADCDCCMP3
RW
0x0000.0000
ADC Digital Comparator Range 3
903
0xE50
ADCDCCMP4
RW
0x0000.0000
ADC Digital Comparator Range 4
903
0xE54
ADCDCCMP5
RW
0x0000.0000
ADC Digital Comparator Range 5
903
0xE58
ADCDCCMP6
RW
0x0000.0000
ADC Digital Comparator Range 6
903
0xE5C
ADCDCCMP7
RW
0x0000.0000
ADC Digital Comparator Range 7
903
0xFC0
ADCPP
RO
0x00B0.2187
ADC Peripheral Properties
904
0xFC4
ADCPC
RW
0x0000.0007
ADC Peripheral Configuration
906
0xFC8
ADCCC
RW
0x0000.0000
ADC Clock Configuration
907
13.6
Description
Register Descriptions
The remainder of this section lists and describes the ADC registers, in numerical order by address
offset.
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Tiva™ TM4C123BH6PGE Microcontroller
Register 1: ADC Active Sample Sequencer (ADCACTSS), offset 0x000
This register controls the activation of the sample sequencers. Each sample sequencer can be
enabled or disabled independently.
ADC Active Sample Sequencer (ADCACTSS)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x000
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
24
23
22
21
20
19
18
17
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
9
8
7
6
5
4
3
2
1
0
ASEN3
ASEN2
ASEN1
ASEN0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
BUSY
reserved
Type
Reset
16
Bit/Field
Name
Type
Reset
Description
31:17
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
16
BUSY
RO
0
ADC Busy
Value Description
0
ADC is idle
1
ADC is busy
15:4
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
ASEN3
RW
0
ADC SS3 Enable
Value Description
2
ASEN2
RW
0
0
Sample Sequencer 3 is disabled.
1
Sample Sequencer 3 is enabled.
ADC SS2 Enable
Value Description
1
ASEN1
RW
0
0
Sample Sequencer 2 is disabled.
1
Sample Sequencer 2 is enabled.
ADC SS1 Enable
Value Description
0
Sample Sequencer 1 is disabled.
1
Sample Sequencer 1 is enabled.
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Analog-to-Digital Converter (ADC)
Bit/Field
Name
Type
Reset
0
ASEN0
RW
0
Description
ADC SS0 Enable
Value Description
0
Sample Sequencer 0 is disabled.
1
Sample Sequencer 0 is enabled.
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Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Register 2: ADC Raw Interrupt Status (ADCRIS), offset 0x004
This register shows the status of the raw interrupt signal of each sample sequencer. These bits may
be polled by software to look for interrupt conditions without sending the interrupts to the interrupt
controller.
ADC Raw Interrupt Status (ADCRIS)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x004
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
24
23
22
21
20
19
18
17
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
9
8
7
6
5
4
3
2
1
0
INR3
INR2
INR1
INR0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
INRDC
reserved
Type
Reset
16
Bit/Field
Name
Type
Reset
Description
31:17
reserved
RO
0x000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
16
INRDC
RO
0
Digital Comparator Raw Interrupt Status
Value Description
0
All bits in the ADCDCISC register are clear.
1
At least one bit in the ADCDCISC register is set, meaning that
a digital comparator interrupt has occurred.
15:4
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
INR3
RO
0
SS3 Raw Interrupt Status
Value Description
0
An interrupt has not occurred.
1
A sample has completed conversion and the respective
ADCSSCTL3 IEn bit is set, enabling a raw interrupt.
This bit is cleared by writing a 1 to the IN3 bit in the ADCISC register.
2
INR2
RO
0
SS2 Raw Interrupt Status
Value Description
0
An interrupt has not occurred.
1
A sample has completed conversion and the respective
ADCSSCTL2 IEn bit is set, enabling a raw interrupt.
This bit is cleared by writing a 1 to the IN2 bit in the ADCISC register.
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Analog-to-Digital Converter (ADC)
Bit/Field
Name
Type
Reset
1
INR1
RO
0
Description
SS1 Raw Interrupt Status
Value Description
0
An interrupt has not occurred.
1
A sample has completed conversion and the respective
ADCSSCTL1 IEn bit is set, enabling a raw interrupt.
This bit is cleared by writing a 1 to the IN1 bit in the ADCISC register.
0
INR0
RO
0
SS0 Raw Interrupt Status
Value Description
0
An interrupt has not occurred.
1
A sample has completed conversion and the respective
ADCSSCTL0 IEn bit is set, enabling a raw interrupt.
This bit is cleared by writing a 1 to the IN0 bit in the ADCISC register.
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Tiva™ TM4C123BH6PGE Microcontroller
Register 3: ADC Interrupt Mask (ADCIM), offset 0x008
This register controls whether the sample sequencer and digital comparator raw interrupt signals
are sent to the interrupt controller. Each raw interrupt signal can be masked independently.
Note:
Only a single DCONSSn bit should be set at any given time. Setting more than one of these
bits results in the INRDC bit from the ADCRIS register being masked, and no interrupt is
generated on any of the sample sequencer interrupt lines. It is recommended that when
interrupts are used, they are enabled on alternating samples or at the end of the sample
sequence.
ADC Interrupt Mask (ADCIM)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x008
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
19
18
17
16
DCONSS3 DCONSS2 DCONSS1 DCONSS0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
RW
0
RW
0
RW
0
3
2
1
0
MASK3
MASK2
MASK1
MASK0
RW
0
RW
0
RW
0
RW
0
Bit/Field
Name
Type
Reset
Description
31:20
reserved
RO
0x000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
19
DCONSS3
RW
0
Digital Comparator Interrupt on SS3
Value Description
18
DCONSS2
RW
0
0
The status of the digital comparators does not affect the SS3
interrupt status.
1
The raw interrupt signal from the digital comparators (INRDC
bit in the ADCRIS register) is sent to the interrupt controller on
the SS3 interrupt line.
Digital Comparator Interrupt on SS2
Value Description
0
The status of the digital comparators does not affect the SS2
interrupt status.
1
The raw interrupt signal from the digital comparators (INRDC
bit in the ADCRIS register) is sent to the interrupt controller on
the SS2 interrupt line.
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Analog-to-Digital Converter (ADC)
Bit/Field
Name
Type
Reset
17
DCONSS1
RW
0
Description
Digital Comparator Interrupt on SS1
Value Description
16
DCONSS0
RW
0
0
The status of the digital comparators does not affect the SS1
interrupt status.
1
The raw interrupt signal from the digital comparators (INRDC
bit in the ADCRIS register) is sent to the interrupt controller on
the SS1 interrupt line.
Digital Comparator Interrupt on SS0
Value Description
0
The status of the digital comparators does not affect the SS0
interrupt status.
1
The raw interrupt signal from the digital comparators (INRDC
bit in the ADCRIS register) is sent to the interrupt controller on
the SS0 interrupt line.
15:4
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
MASK3
RW
0
SS3 Interrupt Mask
Value Description
2
MASK2
RW
0
0
The status of Sample Sequencer 3 does not affect the SS3
interrupt status.
1
The raw interrupt signal from Sample Sequencer 3 (ADCRIS
register INR3 bit) is sent to the interrupt controller.
SS2 Interrupt Mask
Value Description
1
MASK1
RW
0
0
The status of Sample Sequencer 2 does not affect the SS2
interrupt status.
1
The raw interrupt signal from Sample Sequencer 2 (ADCRIS
register INR2 bit) is sent to the interrupt controller.
SS1 Interrupt Mask
Value Description
0
The status of Sample Sequencer 1 does not affect the SS1
interrupt status.
1
The raw interrupt signal from Sample Sequencer 1 (ADCRIS
register INR1 bit) is sent to the interrupt controller.
836
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Bit/Field
Name
Type
Reset
0
MASK0
RW
0
Description
SS0 Interrupt Mask
Value Description
0
The status of Sample Sequencer 0 does not affect the SS0
interrupt status.
1
The raw interrupt signal from Sample Sequencer 0 (ADCRIS
register INR0 bit) is sent to the interrupt controller.
June 12, 2014
837
Texas Instruments-Production Data
Analog-to-Digital Converter (ADC)
Register 4: ADC Interrupt Status and Clear (ADCISC), offset 0x00C
This register provides the mechanism for clearing sample sequencer interrupt conditions and shows
the status of interrupts generated by the sample sequencers and the digital comparators which have
been sent to the interrupt controller. When read, each bit field is the logical AND of the respective
INR and MASK bits. Sample sequencer interrupts are cleared by writing a 1 to the corresponding
bit position. Digital comparator interrupts are cleared by writing a 1 to the appropriate bits in the
ADCDCISC register. If software is polling the ADCRIS instead of generating interrupts, the sample
sequence INRn bits are still cleared via the ADCISC register, even if the INn bit is not set.
ADC Interrupt Status and Clear (ADCISC)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x00C
Type RW1C, reset 0x0000.0000
31
30
29
28
27
26
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
25
24
23
22
21
20
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
9
8
7
6
5
4
3
2
1
0
IN3
IN2
IN1
IN0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW1C
0
RW1C
0
RW1C
0
RW1C
0
reserved
Type
Reset
18
17
16
DCINSS3 DCINSS2 DCINSS1 DCINSS0
reserved
Type
Reset
19
Bit/Field
Name
Type
Reset
Description
31:20
reserved
RO
0x000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
19
DCINSS3
RO
0
Digital Comparator Interrupt Status on SS3
Value Description
0
No interrupt has occurred or the interrupt is masked.
1
Both the INRDC bit in the ADCRIS register and the DCONSS3
bit in the ADCIM register are set, providing a level-based
interrupt to the interrupt controller.
This bit is cleared by writing a 1 to it. Clearing this bit also clears the
INRDC bit in the ADCRIS register.
18
DCINSS2
RO
0
Digital Comparator Interrupt Status on SS2
Value Description
0
No interrupt has occurred or the interrupt is masked.
1
Both the INRDC bit in the ADCRIS register and the DCONSS2
bit in the ADCIM register are set, providing a level-based
interrupt to the interrupt controller.
This bit is cleared by writing a 1 to it. Clearing this bit also clears the
INRDC bit in the ADCRIS register.
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June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Bit/Field
Name
Type
Reset
17
DCINSS1
RO
0
Description
Digital Comparator Interrupt Status on SS1
Value Description
0
No interrupt has occurred or the interrupt is masked.
1
Both the INRDC bit in the ADCRIS register and the DCONSS1
bit in the ADCIM register are set, providing a level-based
interrupt to the interrupt controller.
This bit is cleared by writing a 1 to it. Clearing this bit also clears the
INRDC bit in the ADCRIS register.
16
DCINSS0
RO
0
Digital Comparator Interrupt Status on SS0
Value Description
0
No interrupt has occurred or the interrupt is masked.
1
Both the INRDC bit in the ADCRIS register and the DCONSS0
bit in the ADCIM register are set, providing a level-based
interrupt to the interrupt controller.
This bit is cleared by writing a 1 to it. Clearing this bit also clears the
INRDC bit in the ADCRIS register.
15:4
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
IN3
RW1C
0
SS3 Interrupt Status and Clear
Value Description
0
No interrupt has occurred or the interrupt is masked.
1
Both the INR3 bit in the ADCRIS register and the MASK3 bit in
the ADCIM register are set, providing a level-based interrupt to
the interrupt controller.
This bit is cleared by writing a 1. Clearing this bit also clears the INR3
bit in the ADCRIS register.
2
IN2
RW1C
0
SS2 Interrupt Status and Clear
Value Description
0
No interrupt has occurred or the interrupt is masked.
1
Both the INR2 bit in the ADCRIS register and the MASK2 bit in
the ADCIM register are set, providing a level-based interrupt to
the interrupt controller.
This bit is cleared by writing a 1. Clearing this bit also clears the INR2
bit in the ADCRIS register.
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Analog-to-Digital Converter (ADC)
Bit/Field
Name
Type
Reset
1
IN1
RW1C
0
Description
SS1 Interrupt Status and Clear
Value Description
0
No interrupt has occurred or the interrupt is masked.
1
Both the INR1 bit in the ADCRIS register and the MASK1 bit in
the ADCIM register are set, providing a level-based interrupt to
the interrupt controller.
This bit is cleared by writing a 1. Clearing this bit also clears the INR1
bit in the ADCRIS register.
0
IN0
RW1C
0
SS0 Interrupt Status and Clear
Value Description
0
No interrupt has occurred or the interrupt is masked.
1
Both the INR0 bit in the ADCRIS register and the MASK0 bit in
the ADCIM register are set, providing a level-based interrupt to
the interrupt controller.
This bit is cleared by writing a 1. Clearing this bit also clears the INR0
bit in the ADCRIS register.
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June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Register 5: ADC Overflow Status (ADCOSTAT), offset 0x010
This register indicates overflow conditions in the sample sequencer FIFOs. Once the overflow
condition has been handled by software, the condition can be cleared by writing a 1 to the
corresponding bit position.
ADC Overflow Status (ADCOSTAT)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x010
Type RW1C, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
OV3
OV2
OV1
OV0
RO
0
RO
0
RO
0
RO
0
RO
0
RW1C
0
RW1C
0
RW1C
0
RW1C
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:4
reserved
RO
0x0000.000
3
OV3
RW1C
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SS3 FIFO Overflow
Value Description
0
The FIFO has not overflowed.
1
The FIFO for Sample Sequencer 3 has hit an overflow condition,
meaning that the FIFO is full and a write was requested. When
an overflow is detected, the most recent write is dropped.
This bit is cleared by writing a 1.
2
OV2
RW1C
0
SS2 FIFO Overflow
Value Description
0
The FIFO has not overflowed.
1
The FIFO for Sample Sequencer 2 has hit an overflow condition,
meaning that the FIFO is full and a write was requested. When
an overflow is detected, the most recent write is dropped.
This bit is cleared by writing a 1.
1
OV1
RW1C
0
SS1 FIFO Overflow
Value Description
0
The FIFO has not overflowed.
1
The FIFO for Sample Sequencer 1 has hit an overflow condition,
meaning that the FIFO is full and a write was requested. When
an overflow is detected, the most recent write is dropped.
This bit is cleared by writing a 1.
June 12, 2014
841
Texas Instruments-Production Data
Analog-to-Digital Converter (ADC)
Bit/Field
Name
Type
Reset
0
OV0
RW1C
0
Description
SS0 FIFO Overflow
Value Description
0
The FIFO has not overflowed.
1
The FIFO for Sample Sequencer 0 has hit an overflow condition,
meaning that the FIFO is full and a write was requested. When
an overflow is detected, the most recent write is dropped.
This bit is cleared by writing a 1.
842
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Register 6: ADC Event Multiplexer Select (ADCEMUX), offset 0x014
The ADCEMUX selects the event (trigger) that initiates sampling for each sample sequencer. Each
sample sequencer can be configured with a unique trigger source. When using a PWM generator
as the trigger source, the ADCEMUX register selects which generator within a PWM module is used
as a trigger and the PSn field in the ADC Trigger Source Select (ADCTSSEL) register specifies
the PWM module instance in which the generator is located.
ADC Event Multiplexer Select (ADCEMUX)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x014
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
EM3
Type
Reset
EM2
EM1
Bit/Field
Name
Type
Reset
31:16
reserved
RO
0x0000
EM0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
June 12, 2014
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Texas Instruments-Production Data
Analog-to-Digital Converter (ADC)
Bit/Field
Name
Type
Reset
15:12
EM3
RW
0x0
Description
SS3 Trigger Select
This field selects the trigger source for Sample Sequencer 3.
The valid configurations for this field are:
Value
Event
0x0
Processor (default)
The trigger is initiated by setting the SSn bit in the ADCPSSI
register.
0x1
Analog Comparator 0
This trigger is configured by the Analog Comparator Control
0 (ACCTL0) register (page 1128).
0x2
Analog Comparator 1
This trigger is configured by the Analog Comparator Control
1 (ACCTL1) register (page 1128).
0x3
Analog Comparator 2
This trigger is configured by the Analog Comparator Control
2 (ACCTL2) register (page 1128).
0x4
External (GPIO Pins)
This trigger is connected to the GPIO interrupt for the
corresponding GPIO (see “ADC Trigger Source” on page 655).
0x5
Timer
In addition, the trigger must be enabled with the TnOTE bit
in the GPTMCTL register (page 746).
0x6
PWM generator 0
The PWM generator 0 trigger can be configured with the
PWM0 Interrupt and Trigger Enable (PWM0INTEN) register
(page 1177).
0x7
PWM generator 1
The PWM generator 1 trigger can be configured with the
PWM1INTEN register (page 1177).
0x8
PWM generator 2
The PWM generator 2 trigger can be configured with the
PWM2INTEN register (page 1177).
0x9
PWM generator 3
The PWM generator 3 trigger can be configured with the
PWM3INTEN register (page 1177).
0xA-0xE reserved
0xF
Always (continuously sample)
844
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Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Bit/Field
Name
Type
Reset
11:8
EM2
RW
0x0
Description
SS2 Trigger Select
This field selects the trigger source for Sample Sequencer 2.
The valid configurations for this field are:
Value
Event
0x0
Processor (default)
The trigger is initiated by setting the SSn bit in the ADCPSSI
register.
0x1
Analog Comparator 0
This trigger is configured by the Analog Comparator Control
0 (ACCTL0) register (page 1128).
0x2
Analog Comparator 1
This trigger is configured by the Analog Comparator Control
1 (ACCTL1) register (page 1128).
0x3
Analog Comparator 2
This trigger is configured by the Analog Comparator Control
2 (ACCTL2) register (page 1128).
0x4
External (GPIO Pins)
This trigger is connected to the GPIO interrupt for the
corresponding GPIO (see “ADC Trigger Source” on page 655).
0x5
Timer
In addition, the trigger must be enabled with the TnOTE bit
in the GPTMCTL register (page 746).
0x6
PWM generator 0
The PWM generator 0 trigger can be configured with the
PWM0 Interrupt and Trigger Enable (PWM0INTEN) register
(page 1177).
0x7
PWM generator 1
The PWM generator 1 trigger can be configured with the
PWM1INTEN register (page 1177).
0x8
PWM generator 2
The PWM generator 2 trigger can be configured with the
PWM2INTEN register (page 1177).
0x9
PWM generator 3
The PWM generator 3 trigger can be configured with the
PWM3INTEN register (page 1177).
0xA-0xE reserved
0xF
Always (continuously sample)
June 12, 2014
845
Texas Instruments-Production Data
Analog-to-Digital Converter (ADC)
Bit/Field
Name
Type
Reset
7:4
EM1
RW
0x0
Description
SS1 Trigger Select
This field selects the trigger source for Sample Sequencer 1.
The valid configurations for this field are:
Value
Event
0x0
Processor (default)
The trigger is initiated by setting the SSn bit in the ADCPSSI
register.
0x1
Analog Comparator 0
This trigger is configured by the Analog Comparator Control
0 (ACCTL0) register (page 1128).
0x2
Analog Comparator 1
This trigger is configured by the Analog Comparator Control
1 (ACCTL1) register (page 1128).
0x3
Analog Comparator 2
This trigger is configured by the Analog Comparator Control
2 (ACCTL2) register (page 1128).
0x4
External (GPIO Pins)
This trigger is connected to the GPIO interrupt for the
corresponding GPIO (see “ADC Trigger Source” on page 655).
0x5
Timer
In addition, the trigger must be enabled with the TnOTE bit
in the GPTMCTL register (page 746).
0x6
PWM generator 0
The PWM generator 0 trigger can be configured with the
PWM0 Interrupt and Trigger Enable (PWM0INTEN) register
(page 1177).
0x7
PWM generator 1
The PWM generator 1 trigger can be configured with the
PWM1INTEN register (page 1177).
0x8
PWM generator 2
The PWM generator 2 trigger can be configured with the
PWM2INTEN register (page 1177).
0x9
PWM generator 3
The PWM generator 3 trigger can be configured with the
PWM3INTEN register (page 1177).
0xA-0xE reserved
0xF
Always (continuously sample)
846
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Bit/Field
Name
Type
Reset
3:0
EM0
RW
0x0
Description
SS0 Trigger Select
This field selects the trigger source for Sample Sequencer 0
The valid configurations for this field are:
Value
Event
0x0
Processor (default)
The trigger is initiated by setting the SSn bit in the ADCPSSI
register.
0x1
Analog Comparator 0
This trigger is configured by the Analog Comparator Control
0 (ACCTL0) register (page 1128).
0x2
Analog Comparator 1
This trigger is configured by the Analog Comparator Control
1 (ACCTL1) register (page 1128).
0x3
Analog Comparator 2
This trigger is configured by the Analog Comparator Control
2 (ACCTL2) register (page 1128).
0x4
External (GPIO Pins)
This trigger is connected to the GPIO interrupt for the
corresponding GPIO (see “ADC Trigger Source” on page 655).
0x5
Timer
In addition, the trigger must be enabled with the TnOTE bit
in the GPTMCTL register (page 746).
0x6
PWM generator 0
The PWM generator 0 trigger can be configured with the
PWM0 Interrupt and Trigger Enable (PWM0INTEN) register
(page 1177).
0x7
PWM generator 1
The PWM generator 1 trigger can be configured with the
PWM1INTEN register (page 1177).
0x8
PWM generator 2
The PWM generator 2 trigger can be configured with the
PWM2INTEN register (page 1177).
0x9
PWM generator 3
The PWM generator 3 trigger can be configured with the
PWM3INTEN register (page 1177).
0xA-0xE reserved
0xF
Always (continuously sample)
June 12, 2014
847
Texas Instruments-Production Data
Analog-to-Digital Converter (ADC)
Register 7: ADC Underflow Status (ADCUSTAT), offset 0x018
This register indicates underflow conditions in the sample sequencer FIFOs. The corresponding
underflow condition is cleared by writing a 1 to the relevant bit position.
ADC Underflow Status (ADCUSTAT)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x018
Type RW1C, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
UV3
UV2
UV1
UV0
RO
0
RO
0
RO
0
RO
0
RO
0
RW1C
0
RW1C
0
RW1C
0
RW1C
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:4
reserved
RO
0x0000.000
3
UV3
RW1C
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SS3 FIFO Underflow
The valid configurations for this field are shown below. This bit is cleared
by writing a 1.
Value Description
2
UV2
RW1C
0
0
The FIFO has not underflowed.
1
The FIFO for the Sample Sequencer has hit an underflow
condition, meaning that the FIFO is empty and a read was
requested. The problematic read does not move the FIFO
pointers, and 0s are returned.
SS2 FIFO Underflow
The valid configurations are the same as those for the UV3 field. This
bit is cleared by writing a 1.
1
UV1
RW1C
0
SS1 FIFO Underflow
The valid configurations are the same as those for the UV3 field. This
bit is cleared by writing a 1.
0
UV0
RW1C
0
SS0 FIFO Underflow
The valid configurations are the same as those for the UV3 field. This
bit is cleared by writing a 1.
848
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Register 8: ADC Trigger Source Select (ADCTSSEL), offset 0x01C
If a PWM Generator n is selected as a trigger source through the EMn bit field in the ADC Event
Multiplexer Select (ADCEMUX) register, the ADCTSSEL register is programmed to identify in
which PWM module instance the generator creating the trigger is located. The register resets to
0x0000.0000, which selects PWM module 0 for all generators. Note that field PS3 selects the PWM
module that maps to Generator 3; PS2 selects the PWM module that maps to Generator 2, and so
on.
ADC Trigger Source Select (ADCTSSEL)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x01C
Type RW, reset 0x0000.0000
31
30
29
reserved
Type
Reset
27
26
25
PS3
24
23
22
21
reserved
20
19
18
PS2
17
16
reserved
RO
0
RO
0
RW
0
RW
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
RW
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RW
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
RW
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
28
RO
0
RO
0
PS1
RW
0
reserved
PS0
reserved
Bit/Field
Name
Type
Reset
Description
31:30
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
29:28
PS3
RW
0x0
Generator 3 PWM Module Trigger Select
This field selects in which PWM module the generator 3 trigger is located.
Value
Description
0x0
Use Generator 3 (and its trigger) in PWM module 0
0x1
Use Generator 3 (and its trigger) in PWM module 1
0x2 - 0x3 reserved
27:22
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
21:20
PS2
RW
0x0
Generator 2 PWM Module Trigger Select
This field selects in which PWM module the Generator 2 trigger is
located.
Value
Description
0x0
Use Generator 2 (and its trigger) in PWM module 0
0x1
Use Generator 2 (and its trigger) in PWM module 1
0x2 - 0x3 reserved
19:14
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
June 12, 2014
849
Texas Instruments-Production Data
Analog-to-Digital Converter (ADC)
Bit/Field
Name
Type
Reset
13:12
PS1
RW
0x0
Description
Generator 1 PWM Module Trigger Select
This field selects in which PWM module the Generator 1 trigger is
located.
Value
Description
0x0
Use Generator 1 (and its trigger) in PWM module 0
0x1
Use Generator 1 (and its trigger) in PWM module 1
0x2 - 0x3 reserved
11:6
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5:4
PS0
RW
0x0
Generator 0 PWM Module Trigger Select
This field selects in which PWM module the Generator 0 trigger is
located.
Value
Description
0x0
Use Generator 0 (and its trigger) in PWM module 0
0x1
Use Generator 0 (and its trigger) in PWM module 1
0x2 - 0x3 reserved
3:0
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
850
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Register 9: ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020
This register sets the priority for each of the sample sequencers. Out of reset, Sequencer 0 has the
highest priority, and Sequencer 3 has the lowest priority. When reconfiguring sequence priorities,
each sequence must have a unique priority for the ADC to operate properly.
ADC Sample Sequencer Priority (ADCSSPRI)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x020
Type RW, reset 0x0000.3210
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RW
1
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RW
0
RO
0
RO
0
RW
0
RW
1
RO
0
RO
0
RW
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
RO
0
SS3
RW
1
reserved
RO
0
SS2
RW
1
Bit/Field
Name
Type
Reset
31:14
reserved
RO
0x0000.0
13:12
SS3
RW
0x3
reserved
SS1
reserved
SS0
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SS3 Priority
This field contains a binary-encoded value that specifies the priority
encoding of Sample Sequencer 3. A priority encoding of 0x0 is highest
and 0x3 is lowest. The priorities assigned to the sequencers must be
uniquely mapped. The ADC may not operate properly if two or more
fields are equal.
11:10
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
9:8
SS2
RW
0x2
SS2 Priority
This field contains a binary-encoded value that specifies the priority
encoding of Sample Sequencer 2. A priority encoding of 0x0 is highest
and 0x3 is lowest. The priorities assigned to the sequencers must be
uniquely mapped. The ADC may not operate properly if two or more
fields are equal.
7:6
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5:4
SS1
RW
0x1
SS1 Priority
This field contains a binary-encoded value that specifies the priority
encoding of Sample Sequencer 1. A priority encoding of 0x0 is highest
and 0x3 is lowest. The priorities assigned to the sequencers must be
uniquely mapped. The ADC may not operate properly if two or more
fields are equal.
3:2
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
June 12, 2014
851
Texas Instruments-Production Data
Analog-to-Digital Converter (ADC)
Bit/Field
Name
Type
Reset
Description
1:0
SS0
RW
0x0
SS0 Priority
This field contains a binary-encoded value that specifies the priority
encoding of Sample Sequencer 0. A priority encoding of 0x0 is highest
and 0x3 is lowest. The priorities assigned to the sequencers must be
uniquely mapped. The ADC may not operate properly if two or more
fields are equal.
852
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Register 10: ADC Sample Phase Control (ADCSPC), offset 0x024
This register allows the ADC module to sample at one of 16 different discrete phases from 0.0°
through 337.5°. For example, the sample rate could be effectively doubled by sampling a signal
using one ADC module configured with the standard sample time and the second ADC module
configured with a 180.0° phase lag.
Note:
Care should be taken when the PHASE field is non-zero, as the resulting delay in sampling
the AINx input may result in undesirable system consequences. The time from ADC trigger
to sample is increased and could make the response time longer than anticipated. The
added latency could have ramifications in the system design. Designers should carefully
consider the impact of this delay.
ADC Sample Phase Control (ADCSPC)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x024
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
1
0
RW
0
RW
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:4
reserved
RO
0x0000.000
PHASE
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
June 12, 2014
853
Texas Instruments-Production Data
Analog-to-Digital Converter (ADC)
Bit/Field
Name
Type
Reset
3:0
PHASE
RW
0x0
Description
Phase Difference
This field selects the sample phase difference from the standard sample
time.
Value Description
0x0
ADC sample lags by 0.0°
0x1
ADC sample lags by 22.5°
0x2
ADC sample lags by 45.0°
0x3
ADC sample lags by 67.5°
0x4
ADC sample lags by 90.0°
0x5
ADC sample lags by 112.5°
0x6
ADC sample lags by 135.0°
0x7
ADC sample lags by 157.5°
0x8
ADC sample lags by 180.0°
0x9
ADC sample lags by 202.5°
0xA
ADC sample lags by 225.0°
0xB
ADC sample lags by 247.5°
0xC
ADC sample lags by 270.0°
0xD
ADC sample lags by 292.5°
0xE
ADC sample lags by 315.0°
0xF
ADC sample lags by 337.5°
854
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Register 11: ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028
This register provides a mechanism for application software to initiate sampling in the sample
sequencers. Sample sequences can be initiated individually or in any combination. When multiple
sequences are triggered simultaneously, the priority encodings in ADCSSPRI dictate execution
order.
This register also provides a means to configure and then initiate concurrent sampling on all ADC
modules. To do this, the first ADC module should be configured. The ADCPSSI register for that
module should then be written. The appropriate SS bits should be set along with the SYNCWAIT bit.
Additional ADC modules should then be configured following the same procedure. Once the final
ADC module is configured, its ADCPSSI register should be written with the appropriate SS bits set
along with the GSYNC bit. All of the ADC modules then begin concurrent sampling according to their
configuration.
ADC Processor Sample Sequence Initiate (ADCPSSI)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x028
Type RW, reset 31
30
GSYNC
Type
Reset
29
28
reserved
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
reserved
SYNCWAIT
RW
0
RO
0
RO
0
RO
0
RW
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31
GSYNC
RW
0
RO
0
RO
0
RO
0
RO
0
RO
0
3
2
1
0
SS3
SS2
SS1
SS0
WO
-
WO
-
WO
-
WO
-
Description
Global Synchronize
Value Description
30:28
reserved
RO
0x0
27
SYNCWAIT
RW
0
0
This bit is cleared once sampling has been initiated.
1
This bit initiates sampling in multiple ADC modules at the same
time. Any ADC module that has been initialized by setting an
SSn bit and the SYNCWAIT bit starts sampling once this bit is
written.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Synchronize Wait
Value Description
26:4
reserved
RO
0x0000.0
0
Sampling begins when a sample sequence has been initiated.
1
This bit allows the sample sequences to be initiated, but delays
sampling until the GSYNC bit is set.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
June 12, 2014
855
Texas Instruments-Production Data
Analog-to-Digital Converter (ADC)
Bit/Field
Name
Type
Reset
Description
3
SS3
WO
-
SS3 Initiate
Value Description
0
No effect.
1
Begin sampling on Sample Sequencer 3, if the sequencer is
enabled in the ADCACTSS register.
Only a write by software is valid; a read of this register returns no
meaningful data.
2
SS2
WO
-
SS2 Initiate
Value Description
0
No effect.
1
Begin sampling on Sample Sequencer 2, if the sequencer is
enabled in the ADCACTSS register.
Only a write by software is valid; a read of this register returns no
meaningful data.
1
SS1
WO
-
SS1 Initiate
Value Description
0
No effect.
1
Begin sampling on Sample Sequencer 1, if the sequencer is
enabled in the ADCACTSS register.
Only a write by software is valid; a read of this register returns no
meaningful data.
0
SS0
WO
-
SS0 Initiate
Value Description
0
No effect.
1
Begin sampling on Sample Sequencer 0, if the sequencer is
enabled in the ADCACTSS register.
Only a write by software is valid; a read of this register returns no
meaningful data.
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Tiva™ TM4C123BH6PGE Microcontroller
Register 12: ADC Sample Averaging Control (ADCSAC), offset 0x030
This register controls the amount of hardware averaging applied to conversion results. The final
conversion result stored in the FIFO is averaged from 2 AVG consecutive ADC samples at the specified
ADC speed. If AVG is 0, the sample is passed directly through without any averaging. If AVG=6,
then 64 consecutive ADC samples are averaged to generate one result in the sequencer FIFO. An
AVG=7 provides unpredictable results.
ADC Sample Averaging Control (ADCSAC)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x030
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
Bit/Field
Name
Type
Reset
31:3
reserved
RO
0x0000.000
2:0
AVG
RW
0x0
AVG
RW
0
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Hardware Averaging Control
Specifies the amount of hardware averaging that will be applied to ADC
samples. The AVG field can be any value between 0 and 6. Entering a
value of 7 creates unpredictable results.
Value Description
0x0
No hardware oversampling
0x1
2x hardware oversampling
0x2
4x hardware oversampling
0x3
8x hardware oversampling
0x4
16x hardware oversampling
0x5
32x hardware oversampling
0x6
64x hardware oversampling
0x7
reserved
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Analog-to-Digital Converter (ADC)
Register 13: ADC Digital Comparator Interrupt Status and Clear (ADCDCISC),
offset 0x034
This register provides status and acknowledgement of digital comparator interrupts. One bit is
provided for each comparator.
ADC Digital Comparator Interrupt Status and Clear (ADCDCISC)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x034
Type RW1C, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7
DCINT7
RW1C
0
RO
0
RO
0
7
6
5
4
3
2
1
0
DCINT7
DCINT6
DCINT5
DCINT4
DCINT3
DCINT2
DCINT1
DCINT0
RW1C
0
RW1C
0
RW1C
0
RW1C
0
RW1C
0
RW1C
0
RW1C
0
RW1C
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Digital Comparator 7 Interrupt Status and Clear
Value Description
0
No interrupt.
1
Digital Comparator 7 has generated an interrupt.
This bit is cleared by writing a 1.
6
DCINT6
RW1C
0
Digital Comparator 6 Interrupt Status and Clear
Value Description
0
No interrupt.
1
Digital Comparator 6 has generated an interrupt.
This bit is cleared by writing a 1.
5
DCINT5
RW1C
0
Digital Comparator 5 Interrupt Status and Clear
Value Description
0
No interrupt.
1
Digital Comparator 5 has generated an interrupt.
This bit is cleared by writing a 1.
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Bit/Field
Name
Type
Reset
4
DCINT4
RW1C
0
Description
Digital Comparator 4 Interrupt Status and Clear
Value Description
0
No interrupt.
1
Digital Comparator 4 has generated an interrupt.
This bit is cleared by writing a 1.
3
DCINT3
RW1C
0
Digital Comparator 3 Interrupt Status and Clear
Value Description
0
No interrupt.
1
Digital Comparator 3 has generated an interrupt.
This bit is cleared by writing a 1.
2
DCINT2
RW1C
0
Digital Comparator 2 Interrupt Status and Clear
Value Description
0
No interrupt.
1
Digital Comparator 2 has generated an interrupt.
This bit is cleared by writing a 1.
1
DCINT1
RW1C
0
Digital Comparator 1 Interrupt Status and Clear
Value Description
0
No interrupt.
1
Digital Comparator 1 has generated an interrupt.
This bit is cleared by writing a 1.
0
DCINT0
RW1C
0
Digital Comparator 0 Interrupt Status and Clear
Value Description
0
No interrupt.
1
Digital Comparator 0 has generated an interrupt.
This bit is cleared by writing a 1.
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Analog-to-Digital Converter (ADC)
Register 14: ADC Control (ADCCTL), offset 0x038
This register configures the voltage reference. The voltage references for the conversion can be
VREFA+ and VREFA- or VDDA and GNDA. Note that values set in this register apply to all ADC
modules, it is not possible to set one module to use internal references and another to use external
references.
ADC Control (ADCCTL)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x038
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
DITHER
RO
0
Bit/Field
Name
Type
Reset
31:7
reserved
RO
0x0000.000
6
DITHER
RW
0
RW
0
reserved
RO
0
VREF
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Dither Mode Enable
Value Description
5:1
reserved
RO
0
0
VREF
RW
0x0
0
Dither mode disabled
1
Dither mode enabled
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Voltage Reference Select
Value Description
0x0
VDDA and GNDA are the voltage references for all ADC modules.
0x1
The external VREFA+ and VREFA- inputs are the voltage
references for all ADC modules.
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Tiva™ TM4C123BH6PGE Microcontroller
Register 15: ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0),
offset 0x040
This register, along with the ADCSSEMUX0 register, defines the analog input configuration for each
sample in a sequence executed with Sample Sequencer 0. If the corresponding EMUXn bit in the
ADCSSEMUX0 register is set, the MUXn field in this register selects from AIN[23:16]. When the
corresponding EMUXn bit is clear, the MUXn field selects from AIN[15:0]. This register is 32 bits
wide and contains information for eight possible samples.
Note:
Channels AIN[31:24] do not exist on this microcontroller. Configuring MUXn to be 0x8-0xF
when the corresponding EMUXn bit is set results in undefined behavior.
ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x040
Type RW, reset 0x0000.0000
31
30
29
28
27
26
RW
0
25
24
23
22
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
15
14
13
12
11
10
9
8
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
MUX7
Type
Reset
20
19
18
RW
0
RW
0
RW
0
RW
0
7
6
5
4
RW
0
RW
0
RW
0
RW
0
MUX6
MUX3
Type
Reset
21
17
16
RW
0
RW
0
RW
0
3
2
1
0
RW
0
RW
0
RW
0
RW
0
MUX5
MUX2
MUX4
MUX1
Bit/Field
Name
Type
Reset
31:28
MUX7
RW
0x0
MUX0
Description
8th Sample Input Select
The MUX7 field is used during the eighth sample of a sequence executed
with the sample sequencer. It specifies which of the analog inputs is
sampled for the analog-to-digital conversion. The value set here indicates
the corresponding pin, for example, a value of 0x1 when EMUX7 is clear
indicates the input is AIN1. A value of 0x1 when EMUX7 is set indicates
the input is AIN17.
If differential sampling is enabled (the D7 bit in the ADCSSCTL0 register
is set), this field must be set to the pair number "i", where the paired
inputs are "2i and 2i+1".
27:24
MUX6
RW
0x0
7th Sample Input Select
The MUX6 field is used during the seventh sample of a sequence
executed with the sample sequencer. It specifies which of the analog
inputs is sampled for the analog-to-digital conversion.
23:20
MUX5
RW
0x0
6th Sample Input Select
The MUX5 field is used during the sixth sample of a sequence executed
with the sample sequencer. It specifies which of the analog inputs is
sampled for the analog-to-digital conversion.
19:16
MUX4
RW
0x0
5th Sample Input Select
The MUX4 field is used during the fifth sample of a sequence executed
with the sample sequencer. It specifies which of the analog inputs is
sampled for the analog-to-digital conversion.
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Analog-to-Digital Converter (ADC)
Bit/Field
Name
Type
Reset
15:12
MUX3
RW
0x0
Description
4th Sample Input Select
The MUX3 field is used during the fourth sample of a sequence executed
with the sample sequencer. It specifies which of the analog inputs is
sampled for the analog-to-digital conversion.
11:8
MUX2
RW
0x0
3rd Sample Input Select
The MUX2 field is used during the third sample of a sequence executed
with the sample sequencer. It specifies which of the analog inputs is
sampled for the analog-to-digital conversion.
7:4
MUX1
RW
0x0
2nd Sample Input Select
The MUX1 field is used during the second sample of a sequence
executed with the sample sequencer. It specifies which of the analog
inputs is sampled for the analog-to-digital conversion.
3:0
MUX0
RW
0x0
1st Sample Input Select
The MUX0 field is used during the first sample of a sequence executed
with the sample sequencer. It specifies which of the analog inputs is
sampled for the analog-to-digital conversion.
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Tiva™ TM4C123BH6PGE Microcontroller
Register 16: ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044
This register contains the configuration information for each sample for a sequence executed with
a sample sequencer. When configuring a sample sequence, the END bit must be set for the final
sample, whether it be after the first sample, eighth sample, or any sample in between. This register
is 32 bits wide and contains information for eight possible samples.
ADC Sample Sequence Control 0 (ADCSSCTL0)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x044
Type RW, reset 0x0000.0000
31
Type
Reset
Type
Reset
30
29
28
27
26
25
TS7
IE7
RW
0
RW
0
15
24
23
END7
D7
RW
0
RW
0
14
13
TS3
IE3
RW
0
RW
0
22
21
TS6
IE6
RW
0
RW
0
12
11
END3
D3
RW
0
RW
0
END6
D6
RW
0
RW
0
TS5
IE5
RW
0
RW
0
10
9
8
7
TS2
IE2
RW
0
RW
0
END2
D2
RW
0
RW
0
Bit/Field
Name
Type
Reset
31
TS7
RW
0
20
19
18
17
END5
D5
RW
0
RW
0
6
5
TS1
IE1
RW
0
RW
0
16
TS4
IE4
END4
D4
RW
0
RW
0
RW
0
RW
0
4
3
2
1
0
END1
D1
TS0
IE0
END0
D0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Description
8th Sample Temp Sensor Select
Value Description
30
IE7
RW
0
0
The input pin specified by the ADCSSMUXn register is read
during the eighth sample of the sample sequence.
1
The temperature sensor is read during the eighth sample of the
sample sequence.
8th Sample Interrupt Enable
Value Description
0
The raw interrupt is not asserted to the interrupt controller.
1
The raw interrupt signal (INR0 bit) is asserted at the end of the
eighth sample's conversion. If the MASK0 bit in the ADCIM
register is set, the interrupt is promoted to the interrupt controller.
It is legal to have multiple samples within a sequence generate interrupts.
29
END7
RW
0
8th Sample is End of Sequence
Value Description
0
Another sample in the sequence is the final sample.
1
The eighth sample is the last sample of the sequence.
It is possible to end the sequence on any sample position. Software
must set an ENDn bit somewhere within the sequence. Samples defined
after the sample containing a set ENDn bit are not requested for
conversion even though the fields may be non-zero.
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Analog-to-Digital Converter (ADC)
Bit/Field
Name
Type
Reset
28
D7
RW
0
Description
8th Sample Differential Input Select
Value Description
0
The analog inputs are not differentially sampled.
1
The analog input is differentially sampled. The corresponding
ADCSSMUXn nibble must be set to the pair number "i", where
the paired inputs are "2i and 2i+1".
Because the temperature sensor does not have a differential option,
this bit must not be set when the TS7 bit is set.
27
TS6
RW
0
7th Sample Temp Sensor Select
Value Description
26
IE6
RW
0
0
The input pin specified by the ADCSSMUXn register is read
during the seventh sample of the sample sequence.
1
The temperature sensor is read during the seventh sample of
the sample sequence.
7th Sample Interrupt Enable
Value Description
0
The raw interrupt is not asserted to the interrupt controller.
1
The raw interrupt signal (INR0 bit) is asserted at the end of the
seventh sample's conversion. If the MASK0 bit in the ADCIM
register is set, the interrupt is promoted to the interrupt controller.
It is legal to have multiple samples within a sequence generate interrupts.
25
END6
RW
0
7th Sample is End of Sequence
Value Description
0
Another sample in the sequence is the final sample.
1
The seventh sample is the last sample of the sequence.
It is possible to end the sequence on any sample position. Software
must set an ENDn bit somewhere within the sequence. Samples defined
after the sample containing a set ENDn bit are not requested for
conversion even though the fields may be non-zero.
24
D6
RW
0
7th Sample Differential Input Select
Value Description
0
The analog inputs are not differentially sampled.
1
The analog input is differentially sampled. The corresponding
ADCSSMUXn nibble must be set to the pair number "i", where
the paired inputs are "2i and 2i+1".
Because the temperature sensor does not have a differential option,
this bit must not be set when the TS6 bit is set.
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Tiva™ TM4C123BH6PGE Microcontroller
Bit/Field
Name
Type
Reset
23
TS5
RW
0
Description
6th Sample Temp Sensor Select
Value Description
22
IE5
RW
0
0
The input pin specified by the ADCSSMUXn register is read
during the sixth sample of the sample sequence.
1
The temperature sensor is read during the sixth sample of the
sample sequence.
6th Sample Interrupt Enable
Value Description
0
The raw interrupt is not asserted to the interrupt controller.
1
The raw interrupt signal (INR0 bit) is asserted at the end of the
sixth sample's conversion. If the MASK0 bit in the ADCIM register
is set, the interrupt is promoted to the interrupt controller.
It is legal to have multiple samples within a sequence generate interrupts.
21
END5
RW
0
6th Sample is End of Sequence
Value Description
0
Another sample in the sequence is the final sample.
1
The sixth sample is the last sample of the sequence.
It is possible to end the sequence on any sample position. Software
must set an ENDn bit somewhere within the sequence. Samples defined
after the sample containing a set ENDn bit are not requested for
conversion even though the fields may be non-zero.
20
D5
RW
0
6th Sample Differential Input Select
Value Description
0
The analog inputs are not differentially sampled.
1
The analog input is differentially sampled. The corresponding
ADCSSMUXn nibble must be set to the pair number "i", where
the paired inputs are "2i and 2i+1".
Because the temperature sensor does not have a differential option,
this bit must not be set when the TS5 bit is set.
19
TS4
RW
0
5th Sample Temp Sensor Select
Value Description
0
The input pin specified by the ADCSSMUXn register is read
during the fifth sample of the sample sequence.
1
The temperature sensor is read during the fifth sample of the
sample sequence.
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Analog-to-Digital Converter (ADC)
Bit/Field
Name
Type
Reset
18
IE4
RW
0
Description
5th Sample Interrupt Enable
Value Description
0
The raw interrupt is not asserted to the interrupt controller.
1
The raw interrupt signal (INR0 bit) is asserted at the end of the
fifth sample's conversion. If the MASK0 bit in the ADCIM register
is set, the interrupt is promoted to the interrupt controller.
It is legal to have multiple samples within a sequence generate interrupts.
17
END4
RW
0
5th Sample is End of Sequence
Value Description
0
Another sample in the sequence is the final sample.
1
The fifth sample is the last sample of the sequence.
It is possible to end the sequence on any sample position. Software
must set an ENDn bit somewhere within the sequence. Samples defined
after the sample containing a set ENDn bit are not requested for
conversion even though the fields may be non-zero.
16
D4
RW
0
5th Sample Differential Input Select
Value Description
0
The analog inputs are not differentially sampled.
1
The analog input is differentially sampled. The corresponding
ADCSSMUXn nibble must be set to the pair number "i", where
the paired inputs are "2i and 2i+1".
Because the temperature sensor does not have a differential option,
this bit must not be set when the TS4 bit is set.
15
TS3
RW
0
4th Sample Temp Sensor Select
Value Description
14
IE3
RW
0
0
The input pin specified by the ADCSSMUXn register is read
during the fourth sample of the sample sequence.
1
The temperature sensor is read during the fourth sample of the
sample sequence.
4th Sample Interrupt Enable
Value Description
0
The raw interrupt is not asserted to the interrupt controller.
1
The raw interrupt signal (INR0 bit) is asserted at the end of the
fourth sample's conversion. If the MASK0 bit in the ADCIM
register is set, the interrupt is promoted to the interrupt controller.
It is legal to have multiple samples within a sequence generate interrupts.
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Tiva™ TM4C123BH6PGE Microcontroller
Bit/Field
Name
Type
Reset
13
END3
RW
0
Description
4th Sample is End of Sequence
Value Description
0
Another sample in the sequence is the final sample.
1
The fourth sample is the last sample of the sequence.
It is possible to end the sequence on any sample position. Software
must set an ENDn bit somewhere within the sequence. Samples defined
after the sample containing a set ENDn bit are not requested for
conversion even though the fields may be non-zero.
12
D3
RW
0
4th Sample Differential Input Select
Value Description
0
The analog inputs are not differentially sampled.
1
The analog input is differentially sampled. The corresponding
ADCSSMUXn nibble must be set to the pair number "i", where
the paired inputs are "2i and 2i+1".
Because the temperature sensor does not have a differential option,
this bit must not be set when the TS3 bit is set.
11
TS2
RW
0
3rd Sample Temp Sensor Select
Value Description
10
IE2
RW
0
0
The input pin specified by the ADCSSMUXn register is read
during the third sample of the sample sequence.
1
The temperature sensor is read during the third sample of the
sample sequence.
3rd Sample Interrupt Enable
Value Description
0
The raw interrupt is not asserted to the interrupt controller.
1
The raw interrupt signal (INR0 bit) is asserted at the end of the
third sample's conversion. If the MASK0 bit in the ADCIM register
is set, the interrupt is promoted to the interrupt controller.
It is legal to have multiple samples within a sequence generate interrupts.
9
END2
RW
0
3rd Sample is End of Sequence
Value Description
0
Another sample in the sequence is the final sample.
1
The third sample is the last sample of the sequence.
It is possible to end the sequence on any sample position. Software
must set an ENDn bit somewhere within the sequence. Samples defined
after the sample containing a set ENDn bit are not requested for
conversion even though the fields may be non-zero.
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Analog-to-Digital Converter (ADC)
Bit/Field
Name
Type
Reset
8
D2
RW
0
Description
3rd Sample Differential Input Select
Value Description
0
The analog inputs are not differentially sampled.
1
The analog input is differentially sampled. The corresponding
ADCSSMUXn nibble must be set to the pair number "i", where
the paired inputs are "2i and 2i+1".
Because the temperature sensor does not have a differential option,
this bit must not be set when the TS2 bit is set.
7
TS1
RW
0
2nd Sample Temp Sensor Select
Value Description
6
IE1
RW
0
0
The input pin specified by the ADCSSMUXn register is read
during the second sample of the sample sequence.
1
The temperature sensor is read during the second sample of
the sample sequence.
2nd Sample Interrupt Enable
Value Description
0
The raw interrupt is not asserted to the interrupt controller.
1
The raw interrupt signal (INR0 bit) is asserted at the end of the
second sample's conversion. If the MASK0 bit in the ADCIM
register is set, the interrupt is promoted to the interrupt controller.
It is legal to have multiple samples within a sequence generate interrupts.
5
END1
RW
0
2nd Sample is End of Sequence
Value Description
0
Another sample in the sequence is the final sample.
1
The second sample is the last sample of the sequence.
It is possible to end the sequence on any sample position. Software
must set an ENDn bit somewhere within the sequence. Samples defined
after the sample containing a set ENDn bit are not requested for
conversion even though the fields may be non-zero.
4
D1
RW
0
2nd Sample Differential Input Select
Value Description
0
The analog inputs are not differentially sampled.
1
The analog input is differentially sampled. The corresponding
ADCSSMUXn nibble must be set to the pair number "i", where
the paired inputs are "2i and 2i+1".
Because the temperature sensor does not have a differential option,
this bit must not be set when the TS1 bit is set.
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Tiva™ TM4C123BH6PGE Microcontroller
Bit/Field
Name
Type
Reset
3
TS0
RW
0
Description
1st Sample Temp Sensor Select
Value Description
2
IE0
RW
0
0
The input pin specified by the ADCSSMUXn register is read
during the first sample of the sample sequence.
1
The temperature sensor is read during the first sample of the
sample sequence.
1st Sample Interrupt Enable
Value Description
0
The raw interrupt is not asserted to the interrupt controller.
1
The raw interrupt signal (INR0 bit) is asserted at the end of the
first sample's conversion. If the MASK0 bit in the ADCIM register
is set, the interrupt is promoted to the interrupt controller.
It is legal to have multiple samples within a sequence generate interrupts.
1
END0
RW
0
1st Sample is End of Sequence
Value Description
0
Another sample in the sequence is the final sample.
1
The first sample is the last sample of the sequence.
It is possible to end the sequence on any sample position. Software
must set an ENDn bit somewhere within the sequence. Samples defined
after the sample containing a set ENDn bit are not requested for
conversion even though the fields may be non-zero.
0
D0
RW
0
1st Sample Differential Input Select
Value Description
0
The analog inputs are not differentially sampled.
1
The analog input is differentially sampled. The corresponding
ADCSSMUXn nibble must be set to the pair number "i", where
the paired inputs are "2i and 2i+1".
Because the temperature sensor does not have a differential option,
this bit must not be set when the TS0 bit is set.
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Analog-to-Digital Converter (ADC)
Register 17: ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048
Register 18: ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068
Register 19: ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088
Register 20: ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset
0x0A8
Important: This register is read-sensitive. See the register description for details.
This register contains the conversion results for samples collected with the sample sequencer (the
ADCSSFIFO0 register is used for Sample Sequencer 0, ADCSSFIFO1 for Sequencer 1,
ADCSSFIFO2 for Sequencer 2, and ADCSSFIFO3 for Sequencer 3). Reads of this register return
conversion result data in the order sample 0, sample 1, and so on, until the FIFO is empty. If the
FIFO is not properly handled by software, overflow and underflow conditions are registered in the
ADCOSTAT and ADCUSTAT registers.
ADC Sample Sequence Result FIFO n (ADCSSFIFOn)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x048
Type RO, reset 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
5
4
3
2
1
0
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
reserved
Type
Reset
RO
0
RO
0
DATA
RO
0
RO
0
RO
-
RO
-
RO
-
Bit/Field
Name
Type
Reset
31:12
reserved
RO
0x0000.0
11:0
DATA
RO
-
RO
-
RO
-
RO
-
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Conversion Result Data
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Tiva™ TM4C123BH6PGE Microcontroller
Register 21: ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset
0x04C
Register 22: ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset
0x06C
Register 23: ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset
0x08C
Register 24: ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset
0x0AC
This register provides a window into the sample sequencer, providing full/empty status information
as well as the positions of the head and tail pointers. The reset value of 0x100 indicates an empty
FIFO with the head and tail pointers both pointing to index 0. The ADCSSFSTAT0 register provides
status on FIFO0, which has 8 entries; ADCSSFSTAT1 on FIFO1, which has 4 entries;
ADCSSFSTAT2 on FIFO2, which has 4 entries; and ADCSSFSTAT3 on FIFO3 which has a single
entry.
ADC Sample Sequence FIFO n Status (ADCSSFSTATn)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x04C
Type RO, reset 0x0000.0100
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
RO
0
FULL
RO
0
RO
0
reserved
RO
0
RO
0
EMPTY
RO
0
Bit/Field
Name
Type
Reset
31:13
reserved
RO
0x0000.0
12
FULL
RO
0
RO
1
HPTR
TPTR
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
FIFO Full
Value Description
11:9
reserved
RO
0x0
8
EMPTY
RO
1
0
The FIFO is not currently full.
1
The FIFO is currently full.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
FIFO Empty
Value Description
0
The FIFO is not currently empty.
1
The FIFO is currently empty.
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Analog-to-Digital Converter (ADC)
Bit/Field
Name
Type
Reset
7:4
HPTR
RO
0x0
Description
FIFO Head Pointer
This field contains the current "head" pointer index for the FIFO, that is,
the next entry to be written.
Valid values are 0x0-0x7 for FIFO0; 0x0-0x3 for FIFO1 and FIFO2; and
0x0 for FIFO3.
3:0
TPTR
RO
0x0
FIFO Tail Pointer
This field contains the current "tail" pointer index for the FIFO, that is,
the next entry to be read.
Valid values are 0x0-0x7 for FIFO0; 0x0-0x3 for FIFO1 and FIFO2; and
0x0 for FIFO3.
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Tiva™ TM4C123BH6PGE Microcontroller
Register 25: ADC Sample Sequence 0 Operation (ADCSSOP0), offset 0x050
This register determines whether the sample from the given conversion on Sample Sequence 0 is
saved in the Sample Sequence FIFO0 or sent to the digital comparator unit.
ADC Sample Sequence 0 Operation (ADCSSOP0)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x050
Type RW, reset 0x0000.0000
31
30
29
reserved
Type
Reset
27
S7DCOP
26
25
reserved
24
23
S6DCOP
22
21
reserved
20
19
S5DCOP
18
17
reserved
16
S4DCOP
RO
0
RO
0
RO
0
RW
0
RO
0
RO
0
RO
0
RW
0
RO
0
RO
0
RO
0
RW
0
RO
0
RO
0
RO
0
RW
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
Type
Reset
28
RO
0
RO
0
S3DCOP
RO
0
RW
0
reserved
RO
0
RO
0
S2DCOP
RO
0
Bit/Field
Name
Type
Reset
31:29
reserved
RO
0x0
28
S7DCOP
RW
0
RW
0
reserved
RO
0
RO
0
S1DCOP
RO
0
RW
0
reserved
RO
0
RO
0
S0DCOP
RO
0
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Sample 7 Digital Comparator Operation
Value Description
27:25
reserved
RO
0x0
24
S6DCOP
RW
0
0
The eighth sample is saved in Sample Sequence FIFO0.
1
The eighth sample is sent to the digital comparator unit specified
by the S7DCSEL bit in the ADCSSDC0 register, and the value
is not written to the FIFO.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Sample 6 Digital Comparator Operation
Same definition as S7DCOP but used during the seventh sample.
23:21
reserved
RO
0x0
20
S5DCOP
RW
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Sample 5 Digital Comparator Operation
Same definition as S7DCOP but used during the sixth sample.
19:17
reserved
RO
0x0
16
S4DCOP
RW
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Sample 4 Digital Comparator Operation
Same definition as S7DCOP but used during the fifth sample.
15:13
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Analog-to-Digital Converter (ADC)
Bit/Field
Name
Type
Reset
12
S3DCOP
RW
0
Description
Sample 3 Digital Comparator Operation
Same definition as S7DCOP but used during the fourth sample.
11:9
reserved
RO
0x0
8
S2DCOP
RW
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Sample 2 Digital Comparator Operation
Same definition as S7DCOP but used during the third sample.
7:5
reserved
RO
0x0
4
S1DCOP
RW
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Sample 1 Digital Comparator Operation
Same definition as S7DCOP but used during the second sample.
3:1
reserved
RO
0x0
0
S0DCOP
RW
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Sample 0 Digital Comparator Operation
Same definition as S7DCOP but used during the first sample.
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Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Register 26: ADC Sample Sequence 0 Digital Comparator Select (ADCSSDC0),
offset 0x054
This register determines which digital comparator receives the sample from the given conversion
on Sample Sequence 0, if the corresponding SnDCOP bit in the ADCSSOP0 register is set.
ADC Sample Sequence 0 Digital Comparator Select (ADCSSDC0)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x054
Type RW, reset 0x0000.0000
31
30
29
28
27
26
S7DCSEL
Type
Reset
24
23
22
21
20
19
S5DCSEL
18
17
16
S4DCSEL
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
S3DCSEL
Type
Reset
25
S6DCSEL
RW
0
RW
0
S2DCSEL
RW
0
RW
0
RW
0
RW
0
RW
0
Bit/Field
Name
Type
Reset
31:28
S7DCSEL
RW
0x0
S1DCSEL
RW
0
RW
0
RW
0
RW
0
S0DCSEL
RW
0
RW
0
RW
0
RW
0
RW
0
Description
Sample 7 Digital Comparator Select
When the S7DCOP bit in the ADCSSOP0 register is set, this field
indicates which digital comparator unit (and its associated set of control
registers) receives the eighth sample from Sample Sequencer 0.
Note:
Values not listed are reserved.
Value Description
27:24
S6DCSEL
RW
0x0
0x0
Digital Comparator Unit 0 (ADCDCCMP0 and ADCDCCTL0)
0x1
Digital Comparator Unit 1 (ADCDCCMP1 and ADCDCCTL1)
0x2
Digital Comparator Unit 2 (ADCDCCMP2 and ADCDCCTL2)
0x3
Digital Comparator Unit 3 (ADCDCCMP3 and ADCDCCTL3)
0x4
Digital Comparator Unit 4 (ADCDCCMP4 and ADCDCCTL4)
0x5
Digital Comparator Unit 5 (ADCDCCMP5 and ADCDCCTL5)
0x6
Digital Comparator Unit 6 (ADCDCCMP6 and ADCDCCTL6)
0x7
Digital Comparator Unit 7 (ADCDCCMP7 and ADCDCCTL7)
Sample 6 Digital Comparator Select
This field has the same encodings as S7DCSEL but is used during the
seventh sample.
23:20
S5DCSEL
RW
0x0
Sample 5 Digital Comparator Select
This field has the same encodings as S7DCSEL but is used during the
sixth sample.
19:16
S4DCSEL
RW
0x0
Sample 4 Digital Comparator Select
This field has the same encodings as S7DCSEL but is used during the
fifth sample.
15:12
S3DCSEL
RW
0x0
Sample 3 Digital Comparator Select
This field has the same encodings as S7DCSEL but is used during the
fourth sample.
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Analog-to-Digital Converter (ADC)
Bit/Field
Name
Type
Reset
11:8
S2DCSEL
RW
0x0
Description
Sample 2 Digital Comparator Select
This field has the same encodings as S7DCSEL but is used during the
third sample.
7:4
S1DCSEL
RW
0x0
Sample 1 Digital Comparator Select
This field has the same encodings as S7DCSEL but is used during the
second sample.
3:0
S0DCSEL
RW
0x0
Sample 0 Digital Comparator Select
This field has the same encodings as S7DCSEL but is used during the
first sample.
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Tiva™ TM4C123BH6PGE Microcontroller
Register 27: ADC Sample Sequence Extended Input Multiplexer Select 0
(ADCSSEMUX0), offset 0x058
This register, along with the ADCSSMUX0 register, defines the analog input configuration for each
sample in a sequence executed with Sample Sequencer 0. If a bit in this register is set, the
corresponding MUXn field in the ADCSSMUX0 register selects from AIN[23:16]. When a bit in
this register is clear, the corresponding MUXn field selects from AIN[15:0]. This register is 32 bits
wide and contains information for eight possible samples.
Note that this register is not used when the differential channel designation is used (the Dn bit is set
in the ADCSSCTL0 register) because the ADCSSMUX0 register can select all the available pairs.
ADC Sample Sequence Extended Input Multiplexer Select 0 (ADCSSEMUX0)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x058
Type RW, reset 0x0000.0000
31
30
29
reserved
Type
Reset
27
EMUX7
26
25
reserved
24
23
EMUX6
22
21
reserved
20
19
EMUX5
18
17
reserved
16
EMUX4
RO
0
RO
0
RO
0
RW
0
RO
0
RO
0
RO
0
RW
0
RO
0
RO
0
RO
0
RW
0
RO
0
RO
0
RO
0
RW
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
Type
Reset
28
RO
0
RO
0
EMUX3
RO
0
RW
0
reserved
RO
0
RO
0
EMUX2
RO
0
RW
0
reserved
RO
0
RO
0
EMUX1
RO
0
RW
0
reserved
RO
0
RO
0
EMUX0
RO
0
RW
0
Bit/Field
Name
Type
Reset
Description
31:29
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
28
EMUX7
RW
0x0
8th Sample Input Select (Upper Bit)
The EMUX7 field is used during the eighth sample of a sequence
executed with the sample sequencer.
Value Description
0
The eighth sample input is selected from AIN[15:0] using the
ADCSSMUX0 register. For example, if the MUX7 field is 0x0,
AIN0 is selected.
1
The eighth sample input is selected from AIN[23:16] using
the ADCSSMUX0 register. For example, if the MUX7 field is 0x0,
AIN16 is selected.
27:25
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
24
EMUX6
RW
0x0
7th Sample Input Select (Upper Bit)
The EMUX6 field is used during the seventh sample of a sequence
executed with the sample sequencer. This bit has the same description
as EMUX7.
23:21
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Analog-to-Digital Converter (ADC)
Bit/Field
Name
Type
Reset
20
EMUX5
RW
0x0
Description
6th Sample Input Select (Upper Bit)
The EMUX5 field is used during the sixth sample of a sequence executed
with the sample sequencer. This bit has the same description as EMUX7.
19:17
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
16
EMUX4
RW
0x0
5th Sample Input Select (Upper Bit)
The EMUX4 field is used during the fifth sample of a sequence executed
with the sample sequencer. This bit has the same description as EMUX7.
15:13
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
12
EMUX3
RW
0x0
4th Sample Input Select (Upper Bit)
The EMUX3 field is used during the fourth sample of a sequence executed
with the sample sequencer. This bit has the same description as EMUX7.
11:9
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
8
EMUX2
RW
0x0
3rd Sample Input Select (Upper Bit)
The EMUX2 field is used during the third sample of a sequence executed
with the sample sequencer. This bit has the same description as EMUX7.
7:5
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
4
EMUX1
RW
0x0
2th Sample Input Select (Upper Bit)
The EMUX1 field is used during the second sample of a sequence
executed with the sample sequencer. This bit has the same description
as EMUX7.
3:1
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
EMUX0
RW
0x0
1st Sample Input Select (Upper Bit)
The EMUX0 field is used during the first sample of a sequence executed
with the sample sequencer. This bit has the same description as EMUX7.
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Tiva™ TM4C123BH6PGE Microcontroller
Register 28: ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1),
offset 0x060
Register 29: ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2),
offset 0x080
This register, along with the ADCSSEMUX1 or ADCSSEMUX2 register, defines the analog input
configuration for each sample in a sequence executed with Sample Sequencer 1 or 2. If the
corresponding EMUXn bit in the ADCSSEMUX1 or ADCSSEMUX2 register is set, the MUXn field in
this register selects from AIN[23:16]. When the corresponding EMUXn bit is clear, the MUXn field
selects from AIN[15:0]. These registers are 16 bits wide and contain information for four possible
samples. See the ADCSSMUX0 register on page 861 for detailed bit descriptions. The ADCSSMUX1
register affects Sample Sequencer 1 and the ADCSSMUX2 register affects Sample Sequencer 2.
Note:
Channels AIN[31:24] do not exist on this microcontroller. Configuring MUXn to be 0x8-0xF
when the corresponding EMUXn bit is set results in undefined behavior.
ADC Sample Sequence Input Multiplexer Select n (ADCSSMUXn)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x060
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
5
4
3
2
1
0
RW
0
RW
0
reserved
Type
Reset
RO
0
RO
0
15
14
RO
0
RO
0
RO
0
RO
0
13
12
11
10
MUX3
Type
Reset
RW
0
RW
0
RO
0
RO
0
RO
0
RO
0
9
8
7
6
MUX2
RW
0
RW
0
RW
0
RW
0
MUX1
RW
0
RW
0
RW
0
RW
0
MUX0
RW
0
Bit/Field
Name
Type
Reset
31:16
reserved
RO
0x0000
15:12
MUX3
RW
0x0
4th Sample Input Select
11:8
MUX2
RW
0x0
3rd Sample Input Select
7:4
MUX1
RW
0x0
2nd Sample Input Select
3:0
MUX0
RW
0x0
1st Sample Input Select
RW
0
RW
0
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Analog-to-Digital Converter (ADC)
Register 30: ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064
Register 31: ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084
These registers contain the configuration information for each sample for a sequence executed with
Sample Sequencer 1 or 2. When configuring a sample sequence, the END bit must be set for the
final sample, whether it be after the first sample, fourth sample, or any sample in between. These
registers are 16-bits wide and contain information for four possible samples. See the ADCSSCTL0
register on page 863 for detailed bit descriptions. The ADCSSCTL1 register configures Sample
Sequencer 1 and the ADCSSCTL2 register configures Sample Sequencer 2.
ADC Sample Sequence Control n (ADCSSCTLn)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x064
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
TS3
IE3
END3
D3
TS2
IE2
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
END2
D2
TS1
IE1
END1
D1
TS0
IE0
END0
D0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
Type
Reset
Bit/Field
Name
Type
Reset
31:16
reserved
RO
0x0000
15
TS3
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
4th Sample Temp Sensor Select
Value Description
14
IE3
RW
0
0
The input pin specified by the ADCSSMUXn register is read
during the fourth sample of the sample sequence.
1
The temperature sensor is read during the fourth sample of the
sample sequence.
4th Sample Interrupt Enable
Value Description
0
The raw interrupt is not asserted to the interrupt controller.
1
The raw interrupt signal (INR0 bit) is asserted at the end of the
fourth sample's conversion. If the MASK0 bit in the ADCIM
register is set, the interrupt is promoted to the interrupt controller.
It is legal to have multiple samples within a sequence generate interrupts.
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Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Bit/Field
Name
Type
Reset
13
END3
RW
0
Description
4th Sample is End of Sequence
Value Description
0
Another sample in the sequence is the final sample.
1
The fourth sample is the last sample of the sequence.
It is possible to end the sequence on any sample position. Software
must set an ENDn bit somewhere within the sequence. Samples defined
after the sample containing a set ENDn bit are not requested for
conversion even though the fields may be non-zero.
12
D3
RW
0
4th Sample Differential Input Select
Value Description
0
The analog inputs are not differentially sampled.
1
The analog input is differentially sampled. The corresponding
ADCSSMUXn nibble must be set to the pair number "i", where
the paired inputs are "2i and 2i+1".
Because the temperature sensor does not have a differential option,
this bit must not be set when the TS3 bit is set.
11
TS2
RW
0
3rd Sample Temp Sensor Select
Value Description
10
IE2
RW
0
0
The input pin specified by the ADCSSMUXn register is read
during the third sample of the sample sequence.
1
The temperature sensor is read during the third sample of the
sample sequence.
3rd Sample Interrupt Enable
Value Description
0
The raw interrupt is not asserted to the interrupt controller.
1
The raw interrupt signal (INR0 bit) is asserted at the end of the
third sample's conversion. If the MASK0 bit in the ADCIM register
is set, the interrupt is promoted to the interrupt controller.
It is legal to have multiple samples within a sequence generate interrupts.
9
END2
RW
0
3rd Sample is End of Sequence
Value Description
0
Another sample in the sequence is the final sample.
1
The third sample is the last sample of the sequence.
It is possible to end the sequence on any sample position. Software
must set an ENDn bit somewhere within the sequence. Samples defined
after the sample containing a set ENDn bit are not requested for
conversion even though the fields may be non-zero.
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Texas Instruments-Production Data
Analog-to-Digital Converter (ADC)
Bit/Field
Name
Type
Reset
8
D2
RW
0
Description
3rd Sample Differential Input Select
Value Description
0
The analog inputs are not differentially sampled.
1
The analog input is differentially sampled. The corresponding
ADCSSMUXn nibble must be set to the pair number "i", where
the paired inputs are "2i and 2i+1".
Because the temperature sensor does not have a differential option,
this bit must not be set when the TS2 bit is set.
7
TS1
RW
0
2nd Sample Temp Sensor Select
Value Description
6
IE1
RW
0
0
The input pin specified by the ADCSSMUXn register is read
during the second sample of the sample sequence.
1
The temperature sensor is read during the second sample of
the sample sequence.
2nd Sample Interrupt Enable
Value Description
0
The raw interrupt is not asserted to the interrupt controller.
1
The raw interrupt signal (INR0 bit) is asserted at the end of the
second sample's conversion. If the MASK0 bit in the ADCIM
register is set, the interrupt is promoted to the interrupt controller.
It is legal to have multiple samples within a sequence generate interrupts.
5
END1
RW
0
2nd Sample is End of Sequence
Value Description
0
Another sample in the sequence is the final sample.
1
The second sample is the last sample of the sequence.
It is possible to end the sequence on any sample position. Software
must set an ENDn bit somewhere within the sequence. Samples defined
after the sample containing a set ENDn bit are not requested for
conversion even though the fields may be non-zero.
4
D1
RW
0
2nd Sample Differential Input Select
Value Description
0
The analog inputs are not differentially sampled.
1
The analog input is differentially sampled. The corresponding
ADCSSMUXn nibble must be set to the pair number "i", where
the paired inputs are "2i and 2i+1".
Because the temperature sensor does not have a differential option,
this bit must not be set when the TS1 bit is set.
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Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Bit/Field
Name
Type
Reset
3
TS0
RW
0
Description
1st Sample Temp Sensor Select
Value Description
2
IE0
RW
0
0
The input pin specified by the ADCSSMUXn register is read
during the first sample of the sample sequence.
1
The temperature sensor is read during the first sample of the
sample sequence.
1st Sample Interrupt Enable
Value Description
0
The raw interrupt is not asserted to the interrupt controller.
1
The raw interrupt signal (INR0 bit) is asserted at the end of the
first sample's conversion. If the MASK0 bit in the ADCIM register
is set, the interrupt is promoted to the interrupt controller.
It is legal to have multiple samples within a sequence generate interrupts.
1
END0
RW
0
1st Sample is End of Sequence
Value Description
0
Another sample in the sequence is the final sample.
1
The first sample is the last sample of the sequence.
It is possible to end the sequence on any sample position. Software
must set an ENDn bit somewhere within the sequence. Samples defined
after the sample containing a set ENDn bit are not requested for
conversion even though the fields may be non-zero.
0
D0
RW
0
1st Sample Differential Input Select
Value Description
0
The analog inputs are not differentially sampled.
1
The analog input is differentially sampled. The corresponding
ADCSSMUXn nibble must be set to the pair number "i", where
the paired inputs are "2i and 2i+1".
Because the temperature sensor does not have a differential option,
this bit must not be set when the TS0 bit is set.
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Texas Instruments-Production Data
Analog-to-Digital Converter (ADC)
Register 32: ADC Sample Sequence 1 Operation (ADCSSOP1), offset 0x070
Register 33: ADC Sample Sequence 2 Operation (ADCSSOP2), offset 0x090
This register determines whether the sample from the given conversion on Sample Sequence n is
saved in the Sample Sequence n FIFO or sent to the digital comparator unit. The ADCSSOP1
register controls Sample Sequencer 1 and the ADCSSOP2 register controls Sample Sequencer 2.
ADC Sample Sequence n Operation (ADCSSOPn)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x070
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
RO
0
S3DCOP
RO
0
RW
0
reserved
RO
0
RO
0
S2DCOP
RO
0
Bit/Field
Name
Type
Reset
31:13
reserved
RO
0x0000.0
12
S3DCOP
RW
0
RW
0
reserved
RO
0
RO
0
S1DCOP
RO
0
RW
0
reserved
RO
0
RO
0
S0DCOP
RO
0
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Sample 3 Digital Comparator Operation
Value Description
11:9
reserved
RO
0x0
8
S2DCOP
RW
0
0
The fourth sample is saved in Sample Sequence FIFOn.
1
The fourth sample is sent to the digital comparator unit specified
by the S3DCSEL bit in the ADCSSDC0n register, and the value
is not written to the FIFO.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Sample 2 Digital Comparator Operation
Same definition as S3DCOP but used during the third sample.
7:5
reserved
RO
0x0
4
S1DCOP
RW
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Sample 1 Digital Comparator Operation
Same definition as S3DCOP but used during the second sample.
3:1
reserved
RO
0x0
0
S0DCOP
RW
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Sample 0 Digital Comparator Operation
Same definition as S3DCOP but used during the first sample.
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Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Register 34: ADC Sample Sequence 1 Digital Comparator Select (ADCSSDC1),
offset 0x074
Register 35: ADC Sample Sequence 2 Digital Comparator Select (ADCSSDC2),
offset 0x094
These registers determine which digital comparator receives the sample from the given conversion
on Sample Sequence n if the corresponding SnDCOP bit in the ADCSSOPn register is set. The
ADCSSDC1 register controls the selection for Sample Sequencer 1 and the ADCSSDC2 register
controls the selection for Sample Sequencer 2.
ADC Sample Sequence n Digital Comparator Select (ADCSSDCn)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x074
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RW
0
RW
0
RW
0
RW
0
RW
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
S3DCSEL
Type
Reset
S2DCSEL
RW
0
RW
0
Bit/Field
Name
Type
Reset
31:16
reserved
RO
0x0000
15:12
S3DCSEL
RW
0x0
S1DCSEL
RW
0
S0DCSEL
RW
0
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Sample 3 Digital Comparator Select
When the S3DCOP bit in the ADCSSOPn register is set, this field
indicates which digital comparator unit (and its associated set of control
registers) receives the eighth sample from Sample Sequencer n.
Note:
Values not listed are reserved.
Value Description
11:8
S2DCSEL
RW
0x0
0x0
Digital Comparator Unit 0 (ADCDCCMP0 and ADCCCTL0)
0x1
Digital Comparator Unit 1 (ADCDCCMP1 and ADCCCTL1)
0x2
Digital Comparator Unit 2 (ADCDCCMP2 and ADCCCTL2)
0x3
Digital Comparator Unit 3 (ADCDCCMP3 and ADCCCTL3)
0x4
Digital Comparator Unit 4 (ADCDCCMP4 and ADCCCTL4)
0x5
Digital Comparator Unit 5 (ADCDCCMP5 and ADCCCTL5)
0x6
Digital Comparator Unit 6 (ADCDCCMP6 and ADCCCTL6)
0x7
Digital Comparator Unit 7 (ADCDCCMP7 and ADCCCTL7)
Sample 2 Digital Comparator Select
This field has the same encodings as S3DCSEL but is used during the
third sample.
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Analog-to-Digital Converter (ADC)
Bit/Field
Name
Type
Reset
7:4
S1DCSEL
RW
0x0
Description
Sample 1 Digital Comparator Select
This field has the same encodings as S3DCSEL but is used during the
second sample.
3:0
S0DCSEL
RW
0x0
Sample 0 Digital Comparator Select
This field has the same encodings as S3DCSEL but is used during the
first sample.
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June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Register 36: ADC Sample Sequence Extended Input Multiplexer Select 1
(ADCSSEMUX1), offset 0x078
Register 37: ADC Sample Sequence Extended Input Multiplexer Select 2
(ADCSSEMUX2), offset 0x098
This register, along with the ADCSSMUX1 or ADCSSMUX2 register, defines the analog input
configuration for each sample in a sequence executed with either Sample Sequencer 1 or 2. If a bit
in this register is set, the corresponding MUXn field in the ADCSSMUX1 or ADCSSMUX2 register
selects from AIN[23:16]. When a bit in this register is clear, the corresponding MUXn field selects
from AIN[15:0]. This register is 16 bits wide and contains information for four possible samples.
The ADCSSEMUX1 register controls Sample Sequencer 1 and the ADCSSEMUX2 register controls
Sample Sequencer 2.
Note that this register is not used when the differential channel designation is used (the Dn bit is set
in the ADCSSCTL1 or ADCSSCTL2 register) because the ADCSSMUX1 or ADCSSMUX2 register
can select all the available pairs.
ADC Sample Sequence Extended Input Multiplexer Select n (ADCSSEMUXn)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x078
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
6
5
4
3
2
1
reserved
Type
Reset
RO
0
15
RO
0
RO
0
14
13
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
12
11
EMUX3
RO
0
RW
0
RO
0
RO
0
10
9
reserved
RO
0
RO
0
RO
0
RO
0
8
7
EMUX2
RO
0
Bit/Field
Name
Type
Reset
31:13
reserved
RO
0x0000
12
EMUX3
RW
0x0
RW
0
reserved
RO
0
RO
0
EMUX1
RO
0
RW
0
reserved
RO
0
RO
0
0
EMUX0
RO
0
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
4th Sample Input Select (Upper Bit)
The EMUX3 field is used during the fourth sample of a sequence executed
with the sample sequencer.
Value Description
11:9
reserved
RO
0x0
0
The fourth sample input is selected from AIN[15:0] using the
ADCSSMUX1 or ADCSSMUX2 register. For example, if the
MUX3 field is 0x0, AIN0 is selected.
1
The fourth sample input is selected from AIN[23:16] using
the ADCSSMUX1 or ADCSSMUX2 register. For example, if the
MUX3 field is 0x0, AIN16 is selected.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Texas Instruments-Production Data
Analog-to-Digital Converter (ADC)
Bit/Field
Name
Type
Reset
8
EMUX2
RW
0x0
Description
3rd Sample Input Select (Upper Bit)
The EMUX2 field is used during the third sample of a sequence executed
with the sample sequencer. This bit has the same description as EMUX3.
7:5
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
4
EMUX1
RW
0x0
2th Sample Input Select (Upper Bit)
The EMUX1 field is used during the second sample of a sequence
executed with the sample sequencer. This bit has the same description
as EMUX3.
3:1
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
EMUX0
RW
0x0
1st Sample Input Select (Upper Bit)
The EMUX0 field is used during the first sample of a sequence executed
with the sample sequencer. This bit has the same description as EMUX3.
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June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Register 38: ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3),
offset 0x0A0
This register, along with the ADCSSEMUX3 register, defines the analog input configuration for the
sample in a sequence executed with Sample Sequencer 3. If the EMUX0 bit in the ADCSSEMUX3
register is set, the MUX0 field in this register selects from AIN[23:16]. When the EMUX0 bit is clear,
the MUX0 field selects from AIN[15:0]. This register is four bits wide and contains information for
one possible sample. See the ADCSSMUX0 register on page 861 for detailed bit descriptions.
ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x0A0
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
1
0
RW
0
RW
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
MUX0
RO
0
Bit/Field
Name
Type
Reset
31:4
reserved
RO
0x0000.000
3:0
MUX0
RW
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1st Sample Input Select
June 12, 2014
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Texas Instruments-Production Data
Analog-to-Digital Converter (ADC)
Register 39: ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4
This register contains the configuration information for a sample executed with Sample Sequencer
3. This register is 4 bits wide and contains information for one possible sample. See the ADCSSCTL0
register on page 863 for detailed bit descriptions.
Note:
When configuring a sample sequence in this register, the END0 bit must be set.
ADC Sample Sequence Control 3 (ADCSSCTL3)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x0A4
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:4
reserved
RO
0x0000.000
3
TS0
RW
0
RO
0
RO
0
RO
0
RO
0
RO
0
3
2
1
0
TS0
IE0
END0
D0
RW
0
RW
0
RW
0
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1st Sample Temp Sensor Select
Value Description
2
IE0
RW
0
0
The input pin specified by the ADCSSMUXn register is read
during the first sample of the sample sequence.
1
The temperature sensor is read during the first sample of the
sample sequence.
Sample Interrupt Enable
Value Description
0
The raw interrupt is not asserted to the interrupt controller.
1
The raw interrupt signal (INR0 bit) is asserted at the end of this
sample's conversion. If the MASK0 bit in the ADCIM register is
set, the interrupt is promoted to the interrupt controller.
It is legal to have multiple samples within a sequence generate interrupts.
1
END0
RW
0
End of Sequence
This bit must be set before initiating a single sample sequence.
Value Description
0
Sampling and conversion continues.
1
This is the end of sequence.
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Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Bit/Field
Name
Type
Reset
0
D0
RW
0
Description
Sample Differential Input Select
Value Description
0
The analog inputs are not differentially sampled.
1
The analog input is differentially sampled. The corresponding
ADCSSMUXn nibble must be set to the pair number "i", where
the paired inputs are "2i and 2i+1".
Because the temperature sensor does not have a differential option,
this bit must not be set when the TS0 bit is set.
June 12, 2014
891
Texas Instruments-Production Data
Analog-to-Digital Converter (ADC)
Register 40: ADC Sample Sequence 3 Operation (ADCSSOP3), offset 0x0B0
This register determines whether the sample from the given conversion on Sample Sequence 3 is
saved in the Sample Sequence 3 FIFO or sent to the digital comparator unit.
ADC Sample Sequence 3 Operation (ADCSSOP3)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x0B0
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:1
reserved
RO
0x0000.000
0
S0DCOP
RW
0
RO
0
S0DCOP
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Sample 0 Digital Comparator Operation
Value Description
0
The sample is saved in Sample Sequence FIFO3.
1
The sample is sent to the digital comparator unit specified by
the S0DCSEL bit in the ADCSSDC03 register, and the value is
not written to the FIFO.
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Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Register 41: ADC Sample Sequence 3 Digital Comparator Select (ADCSSDC3),
offset 0x0B4
This register determines which digital comparator receives the sample from the given conversion
on Sample Sequence 3 if the corresponding SnDCOP bit in the ADCSSOP3 register is set.
ADC Sample Sequence 3 Digital Comparator Select (ADCSSDC3)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x0B4
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:4
reserved
RO
0x0000.000
3:0
S0DCSEL
RW
0x0
S0DCSEL
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
RW
0
RW
0
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Sample 0 Digital Comparator Select
When the S0DCOP bit in the ADCSSOP3 register is set, this field
indicates which digital comparator unit (and its associated set of control
registers) receives the sample from Sample Sequencer 3.
Note:
Values not listed are reserved.
Value Description
0x0
Digital Comparator Unit 0 (ADCDCCMP0 and ADCCCTL0)
0x1
Digital Comparator Unit 1 (ADCDCCMP1 and ADCCCTL1)
0x2
Digital Comparator Unit 2 (ADCDCCMP2 and ADCCCTL2)
0x3
Digital Comparator Unit 3 (ADCDCCMP3 and ADCCCTL3)
0x4
Digital Comparator Unit 4 (ADCDCCMP4 and ADCCCTL4)
0x5
Digital Comparator Unit 5 (ADCDCCMP5 and ADCCCTL5)
0x6
Digital Comparator Unit 6 (ADCDCCMP6 and ADCCCTL6)
0x7
Digital Comparator Unit 7 (ADCDCCMP7 and ADCCCTL7)
June 12, 2014
893
Texas Instruments-Production Data
Analog-to-Digital Converter (ADC)
Register 42: ADC Sample Sequence Extended Input Multiplexer Select 3
(ADCSSEMUX3), offset 0x0B8
This register, along with the ADCSSMUX3 register, defines the analog input configuration for the
sample in a sequence executed with Sample Sequencer 3. If EMUX0 is set, the MUX0 field in the
ADCSSMUX3 register selects from AIN[23:16]. When EMUX0 is clear, the MUX0 field selects from
AIN[15:0]. This register is 1 bit wide and contains information for one possible sample.
Note that this register is not used when the differential channel designation is used (the Dn bit is set
in the ADCSSCTL3 register) because the ADCSSMUX3 register can select all the available pairs.
ADC Sample Sequence Extended Input Multiplexer Select 3 (ADCSSEMUX3)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x0B8
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:1
reserved
RO
0x0000.000
0
EMUX0
RW
0x0
RO
0
EMUX0
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1st Sample Input Select (Upper Bit)
The EMUX0 field is used during the only sample of a sequence executed
with the sample sequencer.
Value Description
0
The sample input is selected from AIN[15:0] using the
ADCSSMUX3 register. For example, if the MUX0 field is 0x0,
AIN0 is selected.
1
The sample input is selected from AIN[23:16] using the
ADCSSMUX3 register. For example, if the MUX0 field is 0x0,
AIN16 is selected.
894
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Register 43: ADC Digital Comparator Reset Initial Conditions (ADCDCRIC),
offset 0xD00
This register provides the ability to reset any of the digital comparator interrupt or trigger functions
back to their initial conditions. Resetting these functions ensures that the data that is being used by
the interrupt and trigger functions in the digital comparator unit is not stale.
ADC Digital Comparator Reset Initial Conditions (ADCDCRIC)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0xD00
Type WO, reset 0x0000.0000
31
30
29
28
27
26
25
24
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
DCTRIG7 DCTRIG6 DCTRIG5 DCTRIG4 DCTRIG3 DCTRIG2 DCTRIG1 DCTRIG0
RO
0
RO
0
RO
0
RO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
7
6
5
4
3
2
1
0
DCINT7
DCINT6
DCINT5
DCINT4
DCINT3
DCINT2
DCINT1
DCINT0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
Bit/Field
Name
Type
Reset
Description
31:24
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
23
DCTRIG7
WO
0
Digital Comparator Trigger 7
Value Description
0
No effect.
1
Resets the Digital Comparator 7 trigger unit to its initial
conditions.
When the trigger has been cleared, this bit is automatically cleared.
Because the digital comparators use the current and previous ADC
conversion values to determine when to assert the trigger, it is important
to reset the digital comparator to initial conditions when starting a new
sequence so that stale data is not used. After setting this bit, software
should wait until the bit clears before continuing.
22
DCTRIG6
WO
0
Digital Comparator Trigger 6
Value Description
0
No effect.
1
Resets the Digital Comparator 6 trigger unit to its initial
conditions.
When the trigger has been cleared, this bit is automatically cleared.
Because the digital comparators use the current and previous ADC
conversion values to determine when to assert the trigger, it is important
to reset the digital comparator to initial conditions when starting a new
sequence so that stale data is not used.
June 12, 2014
895
Texas Instruments-Production Data
Analog-to-Digital Converter (ADC)
Bit/Field
Name
Type
Reset
21
DCTRIG5
WO
0
Description
Digital Comparator Trigger 5
Value Description
0
No effect.
1
Resets the Digital Comparator 5 trigger unit to its initial
conditions.
When the trigger has been cleared, this bit is automatically cleared.
Because the digital comparators use the current and previous ADC
conversion values to determine when to assert the trigger, it is important
to reset the digital comparator to initial conditions when starting a new
sequence so that stale data is not used.
20
DCTRIG4
WO
0
Digital Comparator Trigger 4
Value Description
0
No effect.
1
Resets the Digital Comparator 4 trigger unit to its initial
conditions.
When the trigger has been cleared, this bit is automatically cleared.
Because the digital comparators use the current and previous ADC
conversion values to determine when to assert the trigger, it is important
to reset the digital comparator to initial conditions when starting a new
sequence so that stale data is not used.
19
DCTRIG3
WO
0
Digital Comparator Trigger 3
Value Description
0
No effect.
1
Resets the Digital Comparator 3 trigger unit to its initial
conditions.
When the trigger has been cleared, this bit is automatically cleared.
Because the digital comparators use the current and previous ADC
conversion values to determine when to assert the trigger, it is important
to reset the digital comparator to initial conditions when starting a new
sequence so that stale data is not used.
18
DCTRIG2
WO
0
Digital Comparator Trigger 2
Value Description
0
No effect.
1
Resets the Digital Comparator 2 trigger unit to its initial
conditions.
When the trigger has been cleared, this bit is automatically cleared.
Because the digital comparators use the current and previous ADC
conversion values to determine when to assert the trigger, it is important
to reset the digital comparator to initial conditions when starting a new
sequence so that stale data is not used.
896
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Bit/Field
Name
Type
Reset
17
DCTRIG1
WO
0
Description
Digital Comparator Trigger 1
Value Description
0
No effect.
1
Resets the Digital Comparator 1 trigger unit to its initial
conditions.
When the trigger has been cleared, this bit is automatically cleared.
Because the digital comparators use the current and previous ADC
conversion values to determine when to assert the trigger, it is important
to reset the digital comparator to initial conditions when starting a new
sequence so that stale data is not used.
16
DCTRIG0
WO
0
Digital Comparator Trigger 0
Value Description
0
No effect.
1
Resets the Digital Comparator 0 trigger unit to its initial
conditions.
When the trigger has been cleared, this bit is automatically cleared.
Because the digital comparators use the current and previous ADC
conversion values to determine when to assert the trigger, it is important
to reset the digital comparator to initial conditions when starting a new
sequence so that stale data is not used.
15:8
reserved
RO
0x00
7
DCINT7
WO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Digital Comparator Interrupt 7
Value Description
0
No effect.
1
Resets the Digital Comparator 7 interrupt unit to its initial
conditions.
When the interrupt has been cleared, this bit is automatically cleared.
Because the digital comparators use the current and previous ADC
conversion values to determine when to assert the interrupt, it is
important to reset the digital comparator to initial conditions when starting
a new sequence so that stale data is not used.
6
DCINT6
WO
0
Digital Comparator Interrupt 6
Value Description
0
No effect.
1
Resets the Digital Comparator 6 interrupt unit to its initial
conditions.
When the interrupt has been cleared, this bit is automatically cleared.
Because the digital comparators use the current and previous ADC
conversion values to determine when to assert the interrupt, it is
important to reset the digital comparator to initial conditions when starting
a new sequence so that stale data is not used.
June 12, 2014
897
Texas Instruments-Production Data
Analog-to-Digital Converter (ADC)
Bit/Field
Name
Type
Reset
5
DCINT5
WO
0
Description
Digital Comparator Interrupt 5
Value Description
0
No effect.
1
Resets the Digital Comparator 5 interrupt unit to its initial
conditions.
When the interrupt has been cleared, this bit is automatically cleared.
Because the digital comparators use the current and previous ADC
conversion values to determine when to assert the interrupt, it is
important to reset the digital comparator to initial conditions when starting
a new sequence so that stale data is not used.
4
DCINT4
WO
0
Digital Comparator Interrupt 4
Value Description
0
No effect.
1
Resets the Digital Comparator 4 interrupt unit to its initial
conditions.
When the interrupt has been cleared, this bit is automatically cleared.
Because the digital comparators use the current and previous ADC
conversion values to determine when to assert the interrupt, it is
important to reset the digital comparator to initial conditions when starting
a new sequence so that stale data is not used.
3
DCINT3
WO
0
Digital Comparator Interrupt 3
Value Description
0
No effect.
1
Resets the Digital Comparator 3 interrupt unit to its initial
conditions.
When the interrupt has been cleared, this bit is automatically cleared.
Because the digital comparators use the current and previous ADC
conversion values to determine when to assert the interrupt, it is
important to reset the digital comparator to initial conditions when starting
a new sequence so that stale data is not used.
2
DCINT2
WO
0
Digital Comparator Interrupt 2
Value Description
0
No effect.
1
Resets the Digital Comparator 2 interrupt unit to its initial
conditions.
When the interrupt has been cleared, this bit is automatically cleared.
Because the digital comparators use the current and previous ADC
conversion values to determine when to assert the interrupt, it is
important to reset the digital comparator to initial conditions when starting
a new sequence so that stale data is not used.
898
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Bit/Field
Name
Type
Reset
1
DCINT1
WO
0
Description
Digital Comparator Interrupt 1
Value Description
0
No effect.
1
Resets the Digital Comparator 1 interrupt unit to its initial
conditions.
When the interrupt has been cleared, this bit is automatically cleared.
Because the digital comparators use the current and previous ADC
conversion values to determine when to assert the interrupt, it is
important to reset the digital comparator to initial conditions when starting
a new sequence so that stale data is not used.
0
DCINT0
WO
0
Digital Comparator Interrupt 0
Value Description
0
No effect.
1
Resets the Digital Comparator 0 interrupt unit to its initial
conditions.
When the interrupt has been cleared, this bit is automatically cleared.
Because the digital comparators use the current and previous ADC
conversion values to determine when to assert the interrupt, it is
important to reset the digital comparator to initial conditions when starting
a new sequence so that stale data is not used.
June 12, 2014
899
Texas Instruments-Production Data
Analog-to-Digital Converter (ADC)
Register 44: ADC Digital Comparator Control 0 (ADCDCCTL0), offset 0xE00
Register 45: ADC Digital Comparator Control 1 (ADCDCCTL1), offset 0xE04
Register 46: ADC Digital Comparator Control 2 (ADCDCCTL2), offset 0xE08
Register 47: ADC Digital Comparator Control 3 (ADCDCCTL3), offset 0xE0C
Register 48: ADC Digital Comparator Control 4 (ADCDCCTL4), offset 0xE10
Register 49: ADC Digital Comparator Control 5 (ADCDCCTL5), offset 0xE14
Register 50: ADC Digital Comparator Control 6 (ADCDCCTL6), offset 0xE18
Register 51: ADC Digital Comparator Control 7 (ADCDCCTL7), offset 0xE1C
This register provides the comparison encodings that generate an interrupt and/or PWM trigger.
See “Interrupt/ADC-Trigger Selector” on page 1139 for more information on using the ADC digital
comparators to trigger a PWM generator.
ADC Digital Comparator Control n (ADCDCCTLn)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0xE00
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RW
0
RW
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RW
0
RO
0
RW
0
RW
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
RO
0
CTE
RO
0
RW
0
CTC
RW
0
CTM
Bit/Field
Name
Type
Reset
31:13
reserved
RO
0x0000.0
12
CTE
RW
0
reserved
RO
0
CIE
RO
0
RW
0
CIC
RW
0
CIM
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Comparison Trigger Enable
Value Description
0
Disables the trigger function state machine. ADC conversion
data is ignored by the trigger function.
1
Enables the trigger function state machine. The ADC conversion
data is used to determine if a trigger should be generated
according to the programming of the CTC and CTM fields.
900
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Bit/Field
Name
Type
Reset
11:10
CTC
RW
0x0
Description
Comparison Trigger Condition
This field specifies the operational region in which a trigger is generated
when the ADC conversion data is compared against the values of COMP0
and COMP1. The COMP0 and COMP1 fields are defined in the
ADCDCCMPx registers.
Value Description
0x0
Low Band
ADC Data < COMP0 ≤ COMP1
0x1
Mid Band
COMP0 < ADC Data ≤ COMP1
0x2
reserved
0x3
High Band
COMP0 ≤ COMP1 ≤ ADC Data
9:8
CTM
RW
0x0
Comparison Trigger Mode
This field specifies the mode by which the trigger comparison is made.
Value Description
0x0
Always
This mode generates a trigger every time the ADC conversion
data falls within the selected operational region.
0x1
Once
This mode generates a trigger the first time that the ADC
conversion data enters the selected operational region.
0x2
Hysteresis Always
This mode generates a trigger when the ADC conversion data
falls within the selected operational region and continues to
generate the trigger until the hysteresis condition is cleared by
entering the opposite operational region.
Note that the hysteresis modes are only defined for CTC
encodings of 0x0 and 0x3.
0x3
Hysteresis Once
This mode generates a trigger the first time that the ADC
conversion data falls within the selected operational region. No
additional triggers are generated until the hysteresis condition
is cleared by entering the opposite operational region.
Note that the hysteresis modes are only defined for CTC
encodings of 0x0 and 0x3.
7:5
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
June 12, 2014
901
Texas Instruments-Production Data
Analog-to-Digital Converter (ADC)
Bit/Field
Name
Type
Reset
4
CIE
RW
0
Description
Comparison Interrupt Enable
Value Description
3:2
CIC
RW
0x0
0
Disables the comparison interrupt. ADC conversion data has
no effect on interrupt generation.
1
Enables the comparison interrupt. The ADC conversion data is
used to determine if an interrupt should be generated according
to the programming of the CIC and CIM fields.
Comparison Interrupt Condition
This field specifies the operational region in which an interrupt is
generated when the ADC conversion data is compared against the
values of COMP0 and COMP1. The COMP0 and COMP1 fields are defined
in the ADCDCCMPx registers.
Value Description
0x0
Low Band
ADC Data < COMP0 ≤ COMP1
0x1
Mid Band
COMP0 ≤ ADC Data < COMP1
0x2
reserved
0x3
High Band
COMP0 < COMP1 ≤ ADC Data
1:0
CIM
RW
0x0
Comparison Interrupt Mode
This field specifies the mode by which the interrupt comparison is made.
Value Description
0x0
Always
This mode generates an interrupt every time the ADC conversion
data falls within the selected operational region.
0x1
Once
This mode generates an interrupt the first time that the ADC
conversion data enters the selected operational region.
0x2
Hysteresis Always
This mode generates an interrupt when the ADC conversion
data falls within the selected operational region and continues
to generate the interrupt until the hysteresis condition is cleared
by entering the opposite operational region.
Note that the hysteresis modes are only defined for CTC
encodings of 0x0 and 0x3.
0x3
Hysteresis Once
This mode generates an interrupt the first time that the ADC
conversion data falls within the selected operational region. No
additional interrupts are generated until the hysteresis condition
is cleared by entering the opposite operational region.
Note that the hysteresis modes are only defined for CTC
encodings of 0x0 and 0x3.
902
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Register 52: ADC Digital Comparator Range 0 (ADCDCCMP0), offset 0xE40
Register 53: ADC Digital Comparator Range 1 (ADCDCCMP1), offset 0xE44
Register 54: ADC Digital Comparator Range 2 (ADCDCCMP2), offset 0xE48
Register 55: ADC Digital Comparator Range 3 (ADCDCCMP3), offset 0xE4C
Register 56: ADC Digital Comparator Range 4 (ADCDCCMP4), offset 0xE50
Register 57: ADC Digital Comparator Range 5 (ADCDCCMP5), offset 0xE54
Register 58: ADC Digital Comparator Range 6 (ADCDCCMP6), offset 0xE58
Register 59: ADC Digital Comparator Range 7 (ADCDCCMP7), offset 0xE5C
This register defines the comparison values that are used to determine if the ADC conversion data
falls in the appropriate operating region.
Note:
The value in the COMP1 field must be greater than or equal to the value in the COMP0 field
or unexpected results can occur.
ADC Digital Comparator Range n (ADCDCCMPn)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0xE40
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
reserved
Type
Reset
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
21
COMP1
RO
0
RO
0
COMP0
RO
0
RO
0
RW
0
RW
0
RW
0
Bit/Field
Name
Type
Reset
31:28
reserved
RO
0x0
27:16
COMP1
RW
0x000
RW
0
RW
0
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Compare 1
The value in this field is compared against the ADC conversion data.
The result of the comparison is used to determine if the data lies within
the high-band region.
Note that the value of COMP1 must be greater than or equal to the value
of COMP0.
15:12
reserved
RO
0x0
11:0
COMP0
RW
0x000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Compare 0
The value in this field is compared against the ADC conversion data.
The result of the comparison is used to determine if the data lies within
the low-band region.
June 12, 2014
903
Texas Instruments-Production Data
Analog-to-Digital Converter (ADC)
Register 60: ADC Peripheral Properties (ADCPP), offset 0xFC0
The ADCPP register provides information regarding the properties of the ADC module.
ADC Peripheral Properties (ADCPP)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0xFC0
Type RO, reset 0x00B0.2187
31
30
29
28
RO
0
RO
0
RO
0
RO
0
15
14
13
RO
0
RO
0
RO
1
27
26
25
24
23
22
21
RO
0
RO
0
RO
0
RO
0
RO
1
RO
0
RO
1
12
11
10
9
8
7
6
RO
0
RO
0
RO
0
RO
0
RO
1
RO
1
RO
0
reserved
Type
Reset
DC
Type
Reset
19
18
17
RO
1
RO
0
RO
0
RO
0
RO
0
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
1
RO
1
RO
1
TS
20
RSL
TYPE
CH
Bit/Field
Name
Type
Reset
31:24
reserved
RO
0
23
TS
RO
0x1
16
MSR
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Temperature Sensor
Value Description
0
The ADC module does not have a temperature sensor.
1
The ADC module has a temperature sensor.
This field provides the similar information as the legacy DC1 register
TEMPSNS bit.
22:18
RSL
RO
0xC
Resolution
This field specifies the maximum number of binary bits used to represent
the converted sample. The field is encoded as a binary value, in the
range of 0 to 32 bits.
17:16
TYPE
RO
0x0
ADC Architecture
Value
Description
0x0
SAR
0x1 - 0x3 Reserved
15:10
DC
RO
0x8
Digital Comparator Count
This field specifies the number of ADC digital comparators available to
the converter. The field is encoded as a binary value, in the range of 0
to 63.
This field provides similar information to the legacy DC9 register
ADCnDCn bits.
904
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Bit/Field
Name
Type
Reset
Description
9:4
CH
RO
0x18
ADC Channel Count
This field specifies the number of ADC input channels available to the
converter. This field is encoded as a binary value, in the range of 0 to
63.
This field provides similar information to the legacy DC3 and DC8 register
ADCnAINn bits.
3:0
MSR
RO
0x7
Maximum ADC Sample Rate
This field specifies the maximum number of ADC conversions per
second. The MSR field is encoded as follows:
Value
Description
0x0
Reserved
0x1
125 ksps
0x2
Reserved
0x3
250 ksps
0x4
Reserved
0x5
500 ksps
0x6
Reserved
0x7
1 Msps
0x8 - 0xF Reserved
June 12, 2014
905
Texas Instruments-Production Data
Analog-to-Digital Converter (ADC)
Register 61: ADC Peripheral Configuration (ADCPC), offset 0xFC4
The ADCPC register provides information regarding the configuration of the peripheral.
ADC Peripheral Configuration (ADCPC)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0xFC4
Type RW, reset 0x0000.0007
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
RW
1
RW
1
RW
1
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
31:4
reserved
RO
3:0
SR
RW
Reset
SR
Description
0x0000.0000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x7
ADC Sample Rate
This field specifies the number of ADC conversions per second and is
used in Run, Sleep, and Deep-Sleep modes. The field encoding is based
on the legacy RCGC0 register encoding. The programmed sample rate
cannot exceed the maximum sample rate specified by the MSR field in
the ADCPP register. The SR field is encoded as follows:
Value
Description
0x0
Reserved
0x1
125 ksps
0x2
Reserved
0x3
250 ksps
0x4
Reserved
0x5
500 ksps
0x6
Reserved
0x7
1 Msps
0x8 - 0xF Reserved
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Register 62: ADC Clock Configuration (ADCCC), offset 0xFC8
The ADCCC register controls the clock source for the ADC module.
To use the PIOSC to clock the ADC, first power up the PLL and then enable the PIOSC in the CS
bit field, then disable the PLL.
To use the MOSC to clock the ADC, first power up the PLL and then enable the clock to the ADC
module, then disable the PLL and switch to the MOSC for the system clock.
ADC Clock Configuration (ADCCC)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0xFC8
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
reserved
Type
Reset
CS
Bit/Field
Name
Type
Reset
31:4
reserved
RO
0x0000.000
3:0
CS
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
ADC Clock Source
The following table specifies the clock source that generates the ADC
clock input, see Figure 5-5 on page 218.
Value
Description
0x0
Either the 16-MHz system clock (if the PLL bypass is in
effect) or the 16 MHz clock derived from PLL ÷ 25 (default).
Note that when the PLL is bypassed, the system clock must
be at least 16 MHz.
0x1
PIOSC
The PIOSC provides a 16-MHz clock source for the ADC.
If the PIOSC is used as the clock source, the ADC module
can continue to operate in Deep-Sleep mode.
0x2 - 0xF Reserved
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14
Universal Asynchronous Receivers/Transmitters
(UARTs)
The TM4C123BH6PGE controller includes eight Universal Asynchronous Receiver/Transmitter
(UART) with the following features:
■ Programmable baud-rate generator allowing speeds up to 5 Mbps for regular speed (divide by
16) and 10 Mbps for high speed (divide by 8)
■ Separate 16x8 transmit (TX) and receive (RX) FIFOs to reduce CPU interrupt service loading
■ Programmable FIFO length, including 1-byte deep operation providing conventional
double-buffered interface
■ FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8
■ Standard asynchronous communication bits for start, stop, and parity
■ Line-break generation and detection
■ Fully programmable serial interface characteristics
– 5, 6, 7, or 8 data bits
– Even, odd, stick, or no-parity bit generation/detection
– 1 or 2 stop bit generation
■ IrDA serial-IR (SIR) encoder/decoder providing
– Programmable use of IrDA Serial Infrared (SIR) or UART input/output
– Support of IrDA SIR encoder/decoder functions for data rates up to 115.2 Kbps half-duplex
– Support of normal 3/16 and low-power (1.41-2.23 μs) bit durations
– Programmable internal clock generator enabling division of reference clock by 1 to 256 for
low-power mode bit duration
■ Support for communication with ISO 7816 smart cards
■ Modem flow control and status (on UART1)
■ EIA-485 9-bit support
■ Standard FIFO-level and End-of-Transmission interrupts
■ Efficient transfers using Micro Direct Memory Access Controller (µDMA)
– Separate channels for transmit and receive
– Receive single request asserted when data is in the FIFO; burst request asserted at
programmed FIFO level
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– Transmit single request asserted when there is space in the FIFO; burst request asserted at
programmed FIFO level
14.1
Block Diagram
Figure 14-1. UART Module Block Diagram
PIOSC
Clock Control
UARTCC
UARTCTL
System Clock
DMA Request
Baud Clock
DMA Control
UARTDMACTL
Interrupt
Interrupt Control
TxFIFO
16 x 8
UARTIFLS
UARTIM
UARTMIS
UARTRIS
UARTICR
Identification Registers
.
.
.
UARTPCellID0
Transmitter
(with SIR
Transmit
Encoder)
UARTPCellID1
UnTx
Baud Rate
Generator
UARTPCellID2
UARTPCellID3
UARTDR
UARTPeriphID0
UARTIBRD
UARTFBRD
UARTPeriphID1
Receiver
(with SIR
Receive
Decoder)
Control/Status
UnRx
UARTRSR/ECR
UARTPeriphID2
UARTFR
UARTPeriphID3
RxFIFO
16 x 8
UARTLCRH
UARTPeriphID4
UARTCTL
UARTPeriphID5
UARTILPR
UART9BITADDR
UARTPeriphID6
.
.
.
UART9BITAMASK
UARTPeriphID7
14.2
UARTPP
Signal Description
The following table lists the external signals of the UART module and describes the function of each.
The UART signals are alternate functions for some GPIO signals and default to be GPIO signals at
reset, with the exception of the U0Rx and U0Tx pins which default to the UART function. The column
in the table below titled "Pin Mux/Pin Assignment" lists the possible GPIO pin placements for these
UART signals. The AFSEL bit in the GPIO Alternate Function Select (GPIOAFSEL) register
(page 676) should be set to choose the UART function. The number in parentheses is the encoding
that must be programmed into the PMCn field in the GPIO Port Control (GPIOPCTL) register
(page 695) to assign the UART signal to the specified GPIO port pin. For more information on
configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 647.
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Table 14-1. UART Signals (144LQFP)
Pin Name
Pin Number Pin Mux / Pin
Assignment
U0Rx
37
a
Pin Type
Buffer Type
Description
PA0 (1)
I
TTL
UART module 0 receive.
U0Tx
38
PA1 (1)
O
TTL
UART module 0 transmit.
U1CTS
35
63
PC5 (8)
PF1 (1)
I
TTL
UART module 1 Clear To Send modem flow control
input signal.
U1DCD
64
PF2 (1)
I
TTL
UART module 1 Data Carrier Detect modem status
input signal.
U1DSR
65
PF3 (1)
I
TTL
UART module 1 Data Set Ready modem output
control line.
U1DTR
61
PF4 (1)
O
TTL
UART module 1 Data Terminal Ready modem
status input signal.
U1RI
134
PE7 (1)
I
TTL
UART module 1 Ring Indicator modem status input
signal.
U1RTS
36
62
PC4 (8)
PF0 (1)
O
TTL
UART module 1 Request to Send modem flow
control output line.
U1Rx
36
97
PC4 (2)
PB0 (1)
I
TTL
UART module 1 receive.
U1Tx
35
98
PC5 (2)
PB1 (1)
O
TTL
UART module 1 transmit.
U2Rx
51
143
PG4 (1)
PD6 (1)
I
TTL
UART module 2 receive.
U2Tx
50
144
PG5 (1)
PD7 (1)
O
TTL
UART module 2 transmit.
U3Rx
34
PC6 (1)
I
TTL
UART module 3 receive.
U3Tx
33
PC7 (1)
O
TTL
UART module 3 transmit.
U4Rx
36
120
PC4 (1)
PJ0 (1)
I
TTL
UART module 4 receive.
U4Tx
35
121
PC5 (1)
PJ1 (1)
O
TTL
UART module 4 transmit.
U5Rx
122
139
PJ2 (1)
PE4 (1)
I
TTL
UART module 5 receive.
U5Tx
123
140
PJ3 (1)
PE5 (1)
O
TTL
UART module 5 transmit.
U6Rx
127
141
PJ4 (1)
PD4 (1)
I
TTL
UART module 6 receive.
U6Tx
128
142
PJ5 (1)
PD5 (1)
O
TTL
UART module 6 transmit.
U7Rx
15
112
PE0 (1)
PK4 (1)
I
TTL
UART module 7 receive.
U7Tx
14
111
PE1 (1)
PK5 (1)
O
TTL
UART module 7 transmit.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
14.3
Functional Description
Each TM4C123BH6PGE UART performs the functions of parallel-to-serial and serial-to-parallel
conversions. It is similar in functionality to a 16C550 UART, but is not register compatible.
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The UART is configured for transmit and/or receive via the TXE and RXE bits of the UART Control
(UARTCTL) register (see page 935). Transmit and receive are both enabled out of reset. Before any
control registers are programmed, the UART must be disabled by clearing the UARTEN bit in
UARTCTL. If the UART is disabled during a TX or RX operation, the current transaction is completed
prior to the UART stopping.
The UART module also includes a serial IR (SIR) encoder/decoder block that can be connected to
an infrared transceiver to implement an IrDA SIR physical layer. The SIR function is programmed
using the UARTCTL register.
14.3.1
Transmit/Receive Logic
The transmit logic performs parallel-to-serial conversion on the data read from the transmit FIFO.
The control logic outputs the serial bit stream beginning with a start bit and followed by the data bits
(LSB first), parity bit, and the stop bits according to the programmed configuration in the control
registers. See Figure 14-2 on page 911 for details.
The receive logic performs serial-to-parallel conversion on the received bit stream after a valid start
pulse has been detected. Overrun, parity, frame error checking, and line-break detection are also
performed, and their status accompanies the data that is written to the receive FIFO.
Figure 14-2. UART Character Frame
UnTX
LSB
1
5-8 data bits
0
n
Parity bit
if enabled
Start
14.3.2
1-2
stop bits
MSB
Baud-Rate Generation
The baud-rate divisor is a 22-bit number consisting of a 16-bit integer and a 6-bit fractional part.
The number formed by these two values is used by the baud-rate generator to determine the bit
period. Having a fractional baud-rate divisor allows the UART to generate all the standard baud
rates.
The 16-bit integer is loaded through the UART Integer Baud-Rate Divisor (UARTIBRD) register
(see page 931) and the 6-bit fractional part is loaded with the UART Fractional Baud-Rate Divisor
(UARTFBRD) register (see page 932). The baud-rate divisor (BRD) has the following relationship
to the system clock (where BRDI is the integer part of the BRD and BRDF is the fractional part,
separated by a decimal place.)
BRD = BRDI + BRDF = UARTSysClk / (ClkDiv * Baud Rate)
where UARTSysClk is the system clock connected to the UART, and ClkDiv is either 16 (if HSE
in UARTCTL is clear) or 8 (if HSE is set). By default, this will be the main system clock described
in “Clock Control” on page 215. Alternatively, the UART may be clocked from the internal precision
oscillator (PIOSC), independent of the system clock selection. This will allow the UART clock to be
programmed independently of the system clock PLL settings. See the UARTCC register for more
details.
The 6-bit fractional number (that is to be loaded into the DIVFRAC bit field in the UARTFBRD register)
can be calculated by taking the fractional part of the baud-rate divisor, multiplying it by 64, and
adding 0.5 to account for rounding errors:
UARTFBRD[DIVFRAC] = integer(BRDF * 64 + 0.5)
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The UART generates an internal baud-rate reference clock at 8x or 16x the baud-rate (referred to
as Baud8 and Baud16, depending on the setting of the HSE bit (bit 5) in UARTCTL). This reference
clock is divided by 8 or 16 to generate the transmit clock, and is used for error detection during
receive operations. Note that the state of the HSE bit has no effect on clock generation in ISO 7816
smart card mode (when the SMART bit in the UARTCTL register is set).
Along with the UART Line Control, High Byte (UARTLCRH) register (see page 933), the UARTIBRD
and UARTFBRD registers form an internal 30-bit register. This internal register is only updated
when a write operation to UARTLCRH is performed, so any changes to the baud-rate divisor must
be followed by a write to the UARTLCRH register for the changes to take effect.
To update the baud-rate registers, there are four possible sequences:
■ UARTIBRD write, UARTFBRD write, and UARTLCRH write
■ UARTFBRD write, UARTIBRD write, and UARTLCRH write
■ UARTIBRD write and UARTLCRH write
■ UARTFBRD write and UARTLCRH write
14.3.3
Data Transmission
Data received or transmitted is stored in two 16-byte FIFOs, though the receive FIFO has an extra
four bits per character for status information. For transmission, data is written into the transmit FIFO.
If the UART is enabled, it causes a data frame to start transmitting with the parameters indicated
in the UARTLCRH register. Data continues to be transmitted until there is no data left in the transmit
FIFO. The BUSY bit in the UART Flag (UARTFR) register (see page 927) is asserted as soon as
data is written to the transmit FIFO (that is, if the FIFO is non-empty) and remains asserted while
data is being transmitted. The BUSY bit is negated only when the transmit FIFO is empty, and the
last character has been transmitted from the shift register, including the stop bits. The UART can
indicate that it is busy even though the UART may no longer be enabled.
When the receiver is idle (the UnRx signal is continuously 1), and the data input goes Low (a start
bit has been received), the receive counter begins running and data is sampled on the eighth cycle
of Baud16 or fourth cycle of Baud8 depending on the setting of the HSE bit (bit 5) in UARTCTL
(described in “Transmit/Receive Logic” on page 911).
The start bit is valid and recognized if the UnRx signal is still low on the eighth cycle of Baud16 (HSE
clear) or the fourth cycle of Baud 8 (HSE set), otherwise it is ignored. After a valid start bit is detected,
successive data bits are sampled on every 16th cycle of Baud16 or 8th cycle of Baud8 (that is, one
bit period later) according to the programmed length of the data characters and value of the HSE
bit in UARTCTL. The parity bit is then checked if parity mode is enabled. Data length and parity are
defined in the UARTLCRH register.
Lastly, a valid stop bit is confirmed if the UnRx signal is High, otherwise a framing error has occurred.
When a full word is received, the data is stored in the receive FIFO along with any error bits
associated with that word.
14.3.4
Serial IR (SIR)
The UART peripheral includes an IrDA serial-IR (SIR) encoder/decoder block. The IrDA SIR block
provides functionality that converts between an asynchronous UART data stream and a half-duplex
serial SIR interface. No analog processing is performed on-chip. The role of the SIR block is to
provide a digital encoded output and decoded input to the UART. When enabled, the SIR block
uses the UnTx and UnRx pins for the SIR protocol. These signals should be connected to an infrared
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transceiver to implement an IrDA SIR physical layer link. The SIR block can receive and transmit,
but it is only half-duplex so it cannot do both at the same time. Transmission must be stopped before
data can be received. The IrDA SIR physical layer specifies a minimum 10-ms delay between
transmission and reception. The SIR block has two modes of operation:
■ In normal IrDA mode, a zero logic level is transmitted as a high pulse of 3/16th duration of the
selected baud rate bit period on the output pin, while logic one levels are transmitted as a static
LOW signal. These levels control the driver of an infrared transmitter, sending a pulse of light
for each zero. On the reception side, the incoming light pulses energize the photo transistor base
of the receiver, pulling its output LOW and driving the UART input pin LOW.
■ In low-power IrDA mode, the width of the transmitted infrared pulse is set to three times the
period of the internally generated IrLPBaud16 signal (1.63 µs, assuming a nominal 1.8432 MHz
frequency) by changing the appropriate bit in the UARTCTL register (see page 935).
Whether the device is in normal or low-power IrDA mode, a start bit is deemed valid if the decoder
is still Low, one period of IrLPBaud16 after the Low was first detected. This enables a normal-mode
UART to receive data from a low-power mode UART that can transmit pulses as small as 1.41 µs.
Thus, for both low-power and normal mode operation, the ILPDVSR field in the UARTILPR register
must be programmed such that 1.42 MHz < FIrLPBaud16 < 2.12 MHz, resulting in a low-power pulse
duration of 1.41–2.11 μs (three times the period of IrLPBaud16). The minimum frequency of
IrLPBaud16 ensures that pulses less than one period of IrLPBaud16 are rejected, but pulses
greater than 1.4 μs are accepted as valid pulses.
Figure 14-3 on page 913 shows the UART transmit and receive signals, with and without IrDA
modulation.
Figure 14-3. IrDA Data Modulation
Data bits
Start
bit
UnTx
1
0
0
0
1
Stop
bit
0
0
1
1
1
UnTx with IrDA
3
16 Bit period
Bit period
UnRx with IrDA
UnRx
0
1
0
Start
1
0
0
1
1
Data bits
0
1
Stop
In both normal and low-power IrDA modes:
■ During transmission, the UART data bit is used as the base for encoding
■ During reception, the decoded bits are transferred to the UART receive logic
The IrDA SIR physical layer specifies a half-duplex communication link, with a minimum 10-ms
delay between transmission and reception. This delay must be generated by software because it
is not automatically supported by the UART. The delay is required because the infrared receiver
electronics might become biased or even saturated from the optical power coupled from the adjacent
transmitter LED. This delay is known as latency or receiver setup time.
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14.3.5
ISO 7816 Support
The UART offers basic support to allow communication with an ISO 7816 smartcard. When bit 3
(SMART) of the UARTCTL register is set, the UnTx signal is used as a bit clock, and the UnRx signal
is used as the half-duplex communication line connected to the smartcard. A GPIO signal can be
used to generate the reset signal to the smartcard. The remaining smartcard signals should be
provided by the system design. The maximum clock rate in this mode is system clock / 16.
When using ISO 7816 mode, the UARTLCRH register must be set to transmit 8-bit words (WLEN
bits 6:5 configured to 0x3) with EVEN parity (PEN set and EPS set). In this mode, the UART
automatically uses 2 stop bits, and the STP2 bit of the UARTLCRH register is ignored.
If a parity error is detected during transmission, UnRx is pulled Low during the second stop bit. In
this case, the UART aborts the transmission, flushes the transmit FIFO and discards any data it
contains, and raises a parity error interrupt, allowing software to detect the problem and initiate
retransmission of the affected data. Note that the UART does not support automatic retransmission
in this case.
14.3.6
Modem Handshake Support
This section describes how to configure and use the modem flow control and status signals for
UART1 when connected as a DTE (data terminal equipment) or as a DCE (data communications
equipment). In general, a modem is a DCE and a computing device that connects to a modem is
the DTE.
14.3.6.1
Signaling
The status signals provided by UART1 differ based on whether the UART is used as a DTE or DCE.
When used as a DTE, the modem flow control and status signals are defined as:
■ U1CTS is Clear To Send
■ U1DSR is Data Set Ready
■ U1DCD is Data Carrier Detect
■ U1RI is Ring Indicator
■ U1RTS is Request To Send
■ U1DTR is Data Terminal Ready
When used as a DCE, the modem flow control and status signals are defined as:
■ U1CTS is Request To Send
■ U1DSR is Data Terminal Ready
■ U1RTS is Clear To Send
■ U1DTR is Data Set Ready
Note that the support for DCE functions Data Carrier Detect and Ring Indicator are not provided. If
these signals are required, their function can be emulated by using a general-purpose I/O signal
and providing software support.
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14.3.6.2
Flow Control
Flow control can be accomplished by either hardware or software. The following sections describe
the different methods.
Hardware Flow Control (RTS/CTS)
Hardware flow control between two devices is accomplished by connecting the U1RTS output to the
Clear-To-Send input on the receiving device, and connecting the Request-To-Send output on the
receiving device to the U1CTS input.
The U1CTS input controls the transmitter. The transmitter may only transmit data when the U1CTS
input is asserted. The U1RTS output signal indicates the state of the receive FIFO. U1CTS remains
asserted until the preprogrammed watermark level is reached, indicating that the Receive FIFO has
no space to store additional characters.
The UARTCTL register bits 15 (CTSEN) and 14 (RTSEN) specify the flow control mode as shown in
Table 14-2 on page 915.
Table 14-2. Flow Control Mode
Description
CTSEN
RTSEN
1
1
RTS and CTS flow control enabled
1
0
Only CTS flow control enabled
0
1
Only RTS flow control enabled
0
0
Both RTS and CTS flow control disabled
Note that when RTSEN is 1, software cannot modify the U1RTS output value through the UARTCTL
register Request to Send (RTS) bit, and the status of the RTS bit should be ignored.
Software Flow Control (Modem Status Interrupts)
Software flow control between two devices is accomplished by using interrupts to indicate the status
of the UART. Interrupts may be generated for the U1DSR, U1DCD, U1CTS, and U1RI signals using
bits 3:0 of the UARTIM register, respectively. The raw and masked interrupt status may be checked
using the UARTRIS and UARTMIS register. These interrupts may be cleared using the UARTICR
register.
14.3.7
9-Bit UART Mode
The UART provides a 9-bit mode that is enabled with the 9BITEN bit in the UART9BITADDR
register. This feature is useful in a multi-drop configuration of the UART where a single master
connected to multiple slaves can communicate with a particular slave through its address or set of
addresses along with a qualifier for an address byte. All the slaves check for the address qualifier
in the place of the parity bit and, if set, then compare the byte received with the preprogrammed
address. If the address matches, then it receives or sends further data. If the address does not
match, it drops the address byte and any subsequent data bytes. If the UART is in 9-bit mode, then
the receiver operates with no parity mode. The address can be predefined to match with the received
byte and it can be configured with the UART9BITADDR register. The matching can be extended
to a set of addresses using the address mask in the UART9BITAMASK register. By default, the
UART9BITAMASK is 0xFF, meaning that only the specified address is matched.
When not finding a match, the rest of the data bytes with the 9th bit cleared are dropped. If a match
is found, then an interrupt is generated to the NVIC for further action. The subsequent data bytes
with the cleared 9th bit are stored in the FIFO. Software can mask this interrupt in case μDMA and/or
FIFO operations are enabled for this instance and processor intervention is not required. All the
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send transactions with 9-bit mode are data bytes and the 9th bit is cleared. Software can override
the 9th bit to be set (to indicate address) by overriding the parity settings to sticky parity with odd
parity enabled for a particular byte. To match the transmission time with correct parity settings, the
address byte can be transmitted as a single then a burst transfer. The Transmit FIFO does not hold
the address/data bit, hence software should take care of enabling the address bit appropriately.
14.3.8
FIFO Operation
The UART has two 16x8 FIFOs; one for transmit and one for receive. Both FIFOs are accessed via
the UART Data (UARTDR) register (see page 922). Read operations of the UARTDR register return
a 12-bit value consisting of 8 data bits and 4 error flags while write operations place 8-bit data in
the transmit FIFO.
Out of reset, both FIFOs are disabled and act as 1-byte-deep holding registers. The FIFOs are
enabled by setting the FEN bit in UARTLCRH (page 933).
FIFO status can be monitored via the UART Flag (UARTFR) register (see page 927) and the UART
Receive Status (UARTRSR) register. Hardware monitors empty, full and overrun conditions. The
UARTFR register contains empty and full flags (TXFE, TXFF, RXFE, and RXFF bits), and the
UARTRSR register shows overrun status via the OE bit. If the FIFOs are disabled, the empty and
full flags are set according to the status of the 1-byte-deep holding registers.
The trigger points at which the FIFOs generate interrupts is controlled via the UART Interrupt FIFO
Level Select (UARTIFLS) register (see page 939). Both FIFOs can be individually configured to
trigger interrupts at different levels. Available configurations include ⅛, ¼, ½, ¾, and ⅞. For example,
if the ¼ option is selected for the receive FIFO, the UART generates a receive interrupt after 4 data
bytes are received. Out of reset, both FIFOs are configured to trigger an interrupt at the ½ mark.
14.3.9
Interrupts
The UART can generate interrupts when the following conditions are observed:
■ Overrun Error
■ Break Error
■ Parity Error
■ Framing Error
■ Receive Timeout
■ Transmit (when condition defined in the TXIFLSEL bit in the UARTIFLS register is met, or if the
EOT bit in UARTCTL is set, when the last bit of all transmitted data leaves the serializer)
■ Receive (when condition defined in the RXIFLSEL bit in the UARTIFLS register is met)
All of the interrupt events are ORed together before being sent to the interrupt controller, so the
UART can only generate a single interrupt request to the controller at any given time. Software can
service multiple interrupt events in a single interrupt service routine by reading the UART Masked
Interrupt Status (UARTMIS) register (see page 947).
The interrupt events that can trigger a controller-level interrupt are defined in the UART Interrupt
Mask (UARTIM) register (see page 941) by setting the corresponding IM bits. If interrupts are not
used, the raw interrupt status is visible via the UART Raw Interrupt Status (UARTRIS) register
(see page 944).
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Note:
For receive timeout, the RTIM bit in the UARTIM register must be set to see the RTMIS and
RTRIS status in the UARTMIS and UARTRIS registers.
Interrupts are always cleared (for both the UARTMIS and UARTRIS registers) by writing a 1 to the
corresponding bit in the UART Interrupt Clear (UARTICR) register (see page 950).
The receive timeout interrupt is asserted when the receive FIFO is not empty, and no further data
is received over a 32-bit period when the HSE bit is clear or over a 64-bit period when the HSE bit
is set. The receive timeout interrupt is cleared either when the FIFO becomes empty through reading
all the data (or by reading the holding register), or when a 1 is written to the corresponding bit in the
UARTICR register.
The receive interrupt changes state when one of the following events occurs:
■ If the FIFOs are enabled and the receive FIFO reaches the programmed trigger level, the RXRIS
bit is set. The receive interrupt is cleared by reading data from the receive FIFO until it becomes
less than the trigger level, or by clearing the interrupt by writing a 1 to the RXIC bit.
■ If the FIFOs are disabled (have a depth of one location) and data is received thereby filling the
location, the RXRIS bit is set. The receive interrupt is cleared by performing a single read of the
receive FIFO, or by clearing the interrupt by writing a 1 to the RXIC bit.
The transmit interrupt changes state when one of the following events occurs:
■ If the FIFOs are enabled and the transmit FIFO progresses through the programmed trigger
level, the TXRIS bit is set. The transmit interrupt is based on a transition through level, therefore
the FIFO must be written past the programmed trigger level otherwise no further transmit interrupts
will be generated. The transmit interrupt is cleared by writing data to the transmit FIFO until it
becomes greater than the trigger level, or by clearing the interrupt by writing a 1 to the TXIC bit.
■ If the FIFOs are disabled (have a depth of one location) and there is no data present in the
transmitters single location, the TXRIS bit is set. It is cleared by performing a single write to the
transmit FIFO, or by clearing the interrupt by writing a 1 to the TXIC bit.
14.3.10
Loopback Operation
The UART can be placed into an internal loopback mode for diagnostic or debug work by setting
the LBE bit in the UARTCTL register (see page 935). In loopback mode, data transmitted on the
UnTx output is received on the UnRx input. Note that the LBE bit should be set before the UART is
enabled.
14.3.11
DMA Operation
The UART provides an interface to the μDMA controller with separate channels for transmit and
receive. The DMA operation of the UART is enabled through the UART DMA Control
(UARTDMACTL) register. When DMA operation is enabled, the UART asserts a DMA request on
the receive or transmit channel when the associated FIFO can transfer data. For the receive channel,
a single transfer request is asserted whenever any data is in the receive FIFO. A burst transfer
request is asserted whenever the amount of data in the receive FIFO is at or above the FIFO trigger
level configured in the UARTIFLS register. For the transmit channel, a single transfer request is
asserted whenever there is at least one empty location in the transmit FIFO. The burst request is
asserted whenever the transmit FIFO contains fewer characters than the FIFO trigger level. The
single and burst DMA transfer requests are handled automatically by the μDMA controller depending
on how the DMA channel is configured.
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To enable DMA operation for the receive channel, set the RXDMAE bit of the DMA Control
(UARTDMACTL) register. To enable DMA operation for the transmit channel, set the TXDMAE bit
of the UARTDMACTL register. The UART can also be configured to stop using DMA for the receive
channel if a receive error occurs. If the DMAERR bit of the UARTDMACR register is set and a receive
error occurs, the DMA receive requests are automatically disabled. This error condition can be
cleared by clearing the appropriate UART error interrupt.
If the µDMA is enabled, then the controller triggers an interrupt when the TX FIFO or RX FIFO has
reached a trigger point as programmed in the UARTIFLS register. The interrupt occurs on the UART
interrupt vector. Therefore, if interrupts are used for UART operation and DMA is enabled, the UART
interrupt handler must be designed to handle the μDMA completion interrupt.
Note:
To trigger an interrupt on transmit completion from the UART's serializer, the EOT bit must
be set in the UARTCTL register. In this configuration, the transmit interrupt is generated
once the FIFO is completely empty and all data including the stop bits have left the transmit
serializer. In this case, setting the TXIFLSEL bit in the UARTIFLS register is ignored.
When transfers are performed from a FIFO of the UART using the μDMA, and any interrupt is
generated from the UART, the UART module's status bit in the DMA Channel Interrupt Status
(DMACHIS) register must be checked at the end of the interrupt service routine. If the status bit is
set, clear the interrupt by writing a 1 to it.
See “Micro Direct Memory Access (μDMA)” on page 583 for more details about programming the
μDMA controller.
14.4
Initialization and Configuration
To enable and initialize the UART, the following steps are necessary:
1. Enable the UART module using the RCGCUART register (see page 340).
2. Enable the clock to the appropriate GPIO module via the RCGCGPIO register (see page 335).
To find out which GPIO port to enable, refer to Table 22-5 on page 1273.
3. Set the GPIO AFSEL bits for the appropriate pins (see page 676). To determine which GPIOs to
configure, see Table 22-4 on page 1262.
4. Configure the GPIO current level and/or slew rate as specified for the mode selected (see
page 678 and page 687).
5. Configure the PMCn fields in the GPIOPCTL register to assign the UART signals to the appropriate
pins (see page 695 and Table 22-5 on page 1273).
To use the UART, the peripheral clock must be enabled by setting the appropriate bit in the
RCGCUART register (page 340). In addition, the clock to the appropriate GPIO module must be
enabled via the RCGCGPIO register (page 335) in the System Control module. To find out which
GPIO port to enable, refer to Table 22-5 on page 1273.
This section discusses the steps that are required to use a UART module. For this example, the
UART clock is assumed to be 20 MHz, and the desired UART configuration is:
■ 115200 baud rate
■ Data length of 8 bits
■ One stop bit
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■ No parity
■ FIFOs disabled
■ No interrupts
The first thing to consider when programming the UART is the baud-rate divisor (BRD), because
the UARTIBRD and UARTFBRD registers must be written before the UARTLCRH register. Using
the equation described in “Baud-Rate Generation” on page 911, the BRD can be calculated:
BRD = 20,000,000 / (16 * 115,200) = 10.8507
which means that the DIVINT field of the UARTIBRD register (see page 931) should be set to 10
decimal or 0xA. The value to be loaded into the UARTFBRD register (see page 932) is calculated
by the equation:
UARTFBRD[DIVFRAC] = integer(0.8507 * 64 + 0.5) = 54
With the BRD values in hand, the UART configuration is written to the module in the following order:
1. Disable the UART by clearing the UARTEN bit in the UARTCTL register.
2. Write the integer portion of the BRD to the UARTIBRD register.
3. Write the fractional portion of the BRD to the UARTFBRD register.
4. Write the desired serial parameters to the UARTLCRH register (in this case, a value of
0x0000.0060).
5. Configure the UART clock source by writing to the UARTCC register.
6. Optionally, configure the µDMA channel (see “Micro Direct Memory Access (μDMA)” on page 583)
and enable the DMA option(s) in the UARTDMACTL register.
7. Enable the UART by setting the UARTEN bit in the UARTCTL register.
14.5
Register Map
Table 14-3 on page 920 lists the UART registers. The offset listed is a hexadecimal increment to the
register's address, relative to that UART's base address:
■
■
■
■
■
■
■
■
UART0: 0x4000.C000
UART1: 0x4000.D000
UART2: 0x4000.E000
UART3: 0x4000.F000
UART4: 0x4001.0000
UART5: 0x4001.1000
UART6: 0x4001.2000
UART7: 0x4001.3000
The UART module clock must be enabled before the registers can be programmed (see page 340).
There must be a delay of 3 system clocks after the UART module clock is enabled before any UART
module registers are accessed.
The UART must be disabled (see the UARTEN bit in the UARTCTL register on page 935) before any
of the control registers are reprogrammed. When the UART is disabled during a TX or RX operation,
the current transaction is completed prior to the UART stopping.
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Table 14-3. UART Register Map
Type
Reset
Description
See
page
UARTDR
RW
0x0000.0000
UART Data
922
0x004
UARTRSR/UARTECR
RW
0x0000.0000
UART Receive Status/Error Clear
924
0x018
UARTFR
RO
0x0000.0090
UART Flag
927
0x020
UARTILPR
RW
0x0000.0000
UART IrDA Low-Power Register
930
0x024
UARTIBRD
RW
0x0000.0000
UART Integer Baud-Rate Divisor
931
0x028
UARTFBRD
RW
0x0000.0000
UART Fractional Baud-Rate Divisor
932
0x02C
UARTLCRH
RW
0x0000.0000
UART Line Control
933
0x030
UARTCTL
RW
0x0000.0300
UART Control
935
0x034
UARTIFLS
RW
0x0000.0012
UART Interrupt FIFO Level Select
939
0x038
UARTIM
RW
0x0000.0000
UART Interrupt Mask
941
0x03C
UARTRIS
RO
0x0000.0000
UART Raw Interrupt Status
944
0x040
UARTMIS
RO
0x0000.0000
UART Masked Interrupt Status
947
0x044
UARTICR
W1C
0x0000.0000
UART Interrupt Clear
950
0x048
UARTDMACTL
RW
0x0000.0000
UART DMA Control
952
0x0A4
UART9BITADDR
RW
0x0000.0000
UART 9-Bit Self Address
953
0x0A8
UART9BITAMASK
RW
0x0000.00FF
UART 9-Bit Self Address Mask
954
0xFC0
UARTPP
RO
0x0000.0003
UART Peripheral Properties
955
0xFC8
UARTCC
RW
0x0000.0000
UART Clock Configuration
956
0xFD0
UARTPeriphID4
RO
0x0000.0000
UART Peripheral Identification 4
957
0xFD4
UARTPeriphID5
RO
0x0000.0000
UART Peripheral Identification 5
958
0xFD8
UARTPeriphID6
RO
0x0000.0000
UART Peripheral Identification 6
959
0xFDC
UARTPeriphID7
RO
0x0000.0000
UART Peripheral Identification 7
960
0xFE0
UARTPeriphID0
RO
0x0000.0060
UART Peripheral Identification 0
961
0xFE4
UARTPeriphID1
RO
0x0000.0000
UART Peripheral Identification 1
962
0xFE8
UARTPeriphID2
RO
0x0000.0018
UART Peripheral Identification 2
963
0xFEC
UARTPeriphID3
RO
0x0000.0001
UART Peripheral Identification 3
964
0xFF0
UARTPCellID0
RO
0x0000.000D
UART PrimeCell Identification 0
965
0xFF4
UARTPCellID1
RO
0x0000.00F0
UART PrimeCell Identification 1
966
0xFF8
UARTPCellID2
RO
0x0000.0005
UART PrimeCell Identification 2
967
0xFFC
UARTPCellID3
RO
0x0000.00B1
UART PrimeCell Identification 3
968
Offset
Name
0x000
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14.6
Register Descriptions
The remainder of this section lists and describes the UART registers, in numerical order by address
offset.
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Register 1: UART Data (UARTDR), offset 0x000
Important: This register is read-sensitive. See the register description for details.
This register is the data register (the interface to the FIFOs).
For transmitted data, if the FIFO is enabled, data written to this location is pushed onto the transmit
FIFO. If the FIFO is disabled, data is stored in the transmitter holding register (the bottom word of
the transmit FIFO). A write to this register initiates a transmission from the UART.
For received data, if the FIFO is enabled, the data byte and the 4-bit status (break, frame, parity,
and overrun) is pushed onto the 12-bit wide receive FIFO. If the FIFO is disabled, the data byte and
status are stored in the receiving holding register (the bottom word of the receive FIFO). The received
data can be retrieved by reading this register.
UART Data (UARTDR)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
UART3 base: 0x4000.F000
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0x000
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
15
14
13
12
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
11
10
9
8
OE
BE
PE
FE
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:12
reserved
RO
0x0000.0
11
OE
RO
0
DATA
RW
0
RW
0
RW
0
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
UART Overrun Error
Value Description
0
No data has been lost due to a FIFO overrun.
1
New data was received when the FIFO was full, resulting in
data loss.
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Bit/Field
Name
Type
Reset
10
BE
RO
0
Description
UART Break Error
Value Description
0
No break condition has occurred
1
A break condition has been detected, indicating that the receive
data input was held Low for longer than a full-word transmission
time (defined as start, data, parity, and stop bits).
In FIFO mode, this error is associated with the character at the top of
the FIFO. When a break occurs, only one 0 character is loaded into the
FIFO. The next character is only enabled after the received data input
goes to a 1 (marking state), and the next valid start bit is received.
9
PE
RO
0
UART Parity Error
Value Description
0
No parity error has occurred
1
The parity of the received data character does not match the
parity defined by bits 2 and 7 of the UARTLCRH register.
In FIFO mode, this error is associated with the character at the top of
the FIFO.
8
FE
RO
0
UART Framing Error
Value Description
7:0
DATA
RW
0x00
0
No framing error has occurred
1
The received character does not have a valid stop bit (a valid
stop bit is 1).
Data Transmitted or Received
Data that is to be transmitted via the UART is written to this field.
When read, this field contains the data that was received by the UART.
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Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset
0x004
The UARTRSR/UARTECR register is the receive status register/error clear register.
In addition to the UARTDR register, receive status can also be read from the UARTRSR register.
If the status is read from this register, then the status information corresponds to the entry read from
UARTDR prior to reading UARTRSR. The status information for overrun is set immediately when
an overrun condition occurs.
The UARTRSR register cannot be written.
A write of any value to the UARTECR register clears the framing, parity, break, and overrun errors.
All the bits are cleared on reset.
Read-Only Status Register
UART Receive Status/Error Clear (UARTRSR/UARTECR)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
UART3 base: 0x4000.F000
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0x004
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
OE
BE
PE
FE
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:4
reserved
RO
0x0000.000
3
OE
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
UART Overrun Error
Value Description
0
No data has been lost due to a FIFO overrun.
1
New data was received when the FIFO was full, resulting in
data loss.
This bit is cleared by a write to UARTECR.
The FIFO contents remain valid because no further data is written when
the FIFO is full, only the contents of the shift register are overwritten.
The CPU must read the data in order to empty the FIFO.
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Bit/Field
Name
Type
Reset
2
BE
RO
0
Description
UART Break Error
Value Description
0
No break condition has occurred
1
A break condition has been detected, indicating that the receive
data input was held Low for longer than a full-word transmission
time (defined as start, data, parity, and stop bits).
This bit is cleared to 0 by a write to UARTECR.
In FIFO mode, this error is associated with the character at the top of
the FIFO. When a break occurs, only one 0 character is loaded into the
FIFO. The next character is only enabled after the receive data input
goes to a 1 (marking state) and the next valid start bit is received.
1
PE
RO
0
UART Parity Error
Value Description
0
No parity error has occurred
1
The parity of the received data character does not match the
parity defined by bits 2 and 7 of the UARTLCRH register.
This bit is cleared to 0 by a write to UARTECR.
0
FE
RO
0
UART Framing Error
Value Description
0
No framing error has occurred
1
The received character does not have a valid stop bit (a valid
stop bit is 1).
This bit is cleared to 0 by a write to UARTECR.
In FIFO mode, this error is associated with the character at the top of
the FIFO.
Write-Only Error Clear Register
UART Receive Status/Error Clear (UARTRSR/UARTECR)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
UART3 base: 0x4000.F000
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0x004
Type WO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
WO
0
WO
0
WO
0
WO
0
3
2
1
0
WO
0
WO
0
WO
0
WO
0
reserved
Type
Reset
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
WO
0
WO
0
WO
0
WO
0
WO
0
DATA
WO
0
WO
0
WO
0
WO
0
WO
0
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0
WO
0
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Bit/Field
Name
Type
Reset
31:8
reserved
WO
0x0000.00
7:0
DATA
WO
0x00
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Error Clear
A write to this register of any data clears the framing, parity, break, and
overrun flags.
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Register 3: UART Flag (UARTFR), offset 0x018
The UARTFR register is the flag register. After reset, the TXFF, RXFF, and BUSY bits are 0, and
TXFE and RXFE bits are 1. The RI, DCD, DSR and CTS bits indicate the modem flow control and
status. Note that the modem bits are only implemented on UART1 and are reserved on UART0 and
UART2.
UART Flag (UARTFR)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
UART3 base: 0x4000.F000
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0x018
Type RO, reset 0x0000.0090
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
15
14
13
RO
0
RO
0
RO
0
RO
0
12
11
10
9
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:9
reserved
RO
0x0000.00
8
RI
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RI
TXFE
RXFF
TXFF
RXFE
BUSY
DCD
DSR
CTS
RO
0
RO
1
RO
0
RO
0
RO
1
RO
0
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Ring Indicator
Value Description
0
The U1RI signal is not asserted.
1
The U1RI signal is asserted.
This bit is implemented only on UART1 and is reserved for UART0 and
UART2.
7
TXFE
RO
1
UART Transmit FIFO Empty
The meaning of this bit depends on the state of the FEN bit in the
UARTLCRH register.
Value Description
0
The transmitter has data to transmit.
1
If the FIFO is disabled (FEN is 0), the transmit holding register
is empty.
If the FIFO is enabled (FEN is 1), the transmit FIFO is empty.
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Bit/Field
Name
Type
Reset
6
RXFF
RO
0
Description
UART Receive FIFO Full
The meaning of this bit depends on the state of the FEN bit in the
UARTLCRH register.
Value Description
0
The receiver can receive data.
1
If the FIFO is disabled (FEN is 0), the receive holding register
is full.
If the FIFO is enabled (FEN is 1), the receive FIFO is full.
5
TXFF
RO
0
UART Transmit FIFO Full
The meaning of this bit depends on the state of the FEN bit in the
UARTLCRH register.
Value Description
0
The transmitter is not full.
1
If the FIFO is disabled (FEN is 0), the transmit holding register
is full.
If the FIFO is enabled (FEN is 1), the transmit FIFO is full.
4
RXFE
RO
1
UART Receive FIFO Empty
The meaning of this bit depends on the state of the FEN bit in the
UARTLCRH register.
Value Description
0
The receiver is not empty.
1
If the FIFO is disabled (FEN is 0), the receive holding register
is empty.
If the FIFO is enabled (FEN is 1), the receive FIFO is empty.
3
BUSY
RO
0
UART Busy
Value Description
0
The UART is not busy.
1
The UART is busy transmitting data. This bit remains set until
the complete byte, including all stop bits, has been sent from
the shift register.
This bit is set as soon as the transmit FIFO becomes non-empty
(regardless of whether UART is enabled).
2
DCD
RO
0
Data Carrier Detect
Value Description
0
The U1DCD signal is not asserted.
1
The U1DCD signal is asserted.
This bit is implemented only on UART1 and is reserved for UART0 and
UART2.
928
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Bit/Field
Name
Type
Reset
1
DSR
RO
0
Description
Data Set Ready
Value Description
0
The U1DSR signal is not asserted.
1
The U1DSR signal is asserted.
This bit is implemented only on UART1 and is reserved for UART0 and
UART2.
0
CTS
RO
0
Clear To Send
Value Description
0
The U1CTS signal is not asserted.
1
The U1CTS signal is asserted.
This bit is implemented only on UART1 and is reserved for UART0 and
UART2.
June 12, 2014
929
Texas Instruments-Production Data
Universal Asynchronous Receivers/Transmitters (UARTs)
Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020
The UARTILPR register stores the 8-bit low-power counter divisor value used to derive the low-power
SIR pulse width clock by dividing down the system clock (SysClk). All the bits are cleared when
reset.
The internal IrLPBaud16 clock is generated by dividing down SysClk according to the low-power
divisor value written to UARTILPR. The duration of SIR pulses generated when low-power mode
is enabled is three times the period of the IrLPBaud16 clock. The low-power divisor value is
calculated as follows:
ILPDVSR = SysClk / FIrLPBaud16
where FIrLPBaud16 is nominally 1.8432 MHz.
Because the IrLPBaud16 clock is used to sample transmitted data irrespective of mode, the
ILPDVSR field must be programmed in both low power and normal mode,such that 1.42 MHz <
FIrLPBaud16 < 2.12 MHz, resulting in a low-power pulse duration of 1.41–2.11 μs (three times the
period of IrLPBaud16). The minimum frequency of IrLPBaud16 ensures that pulses less than
one period of IrLPBaud16 are rejected, but pulses greater than 1.4 μs are accepted as valid pulses.
Note:
Zero is an illegal value. Programming a zero value results in no IrLPBaud16 pulses being
generated.
UART IrDA Low-Power Register (UARTILPR)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
UART3 base: 0x4000.F000
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0x020
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
reserved
Type
Reset
ILPDVSR
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
ILPDVSR
RW
0x00
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
IrDA Low-Power Divisor
This field contains the 8-bit low-power divisor value.
930
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024
The UARTIBRD register is the integer part of the baud-rate divisor value. All the bits are cleared
on reset. The minimum possible divide ratio is 1 (when UARTIBRD=0), in which case the UARTFBRD
register is ignored. When changing the UARTIBRD register, the new value does not take effect until
transmission/reception of the current character is complete. Any changes to the baud-rate divisor
must be followed by a write to the UARTLCRH register. See “Baud-Rate Generation” on page 911
for configuration details.
UART Integer Baud-Rate Divisor (UARTIBRD)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
UART3 base: 0x4000.F000
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0x024
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
DIVINT
Type
Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bit/Field
Name
Type
Reset
Description
31:16
reserved
RO
0x0000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:0
DIVINT
RW
0x0000
Integer Baud-Rate Divisor
June 12, 2014
931
Texas Instruments-Production Data
Universal Asynchronous Receivers/Transmitters (UARTs)
Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028
The UARTFBRD register is the fractional part of the baud-rate divisor value. All the bits are cleared
on reset. When changing the UARTFBRD register, the new value does not take effect until
transmission/reception of the current character is complete. Any changes to the baud-rate divisor
must be followed by a write to the UARTLCRH register. See “Baud-Rate Generation” on page 911
for configuration details.
UART Fractional Baud-Rate Divisor (UARTFBRD)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
UART3 base: 0x4000.F000
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0x028
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RW
0
RW
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
DIVFRAC
RO
0
Bit/Field
Name
Type
Reset
31:6
reserved
RO
0x0000.000
5:0
DIVFRAC
RW
0x0
RO
0
RO
0
RO
0
RW
0
RW
0
RW
0
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Fractional Baud-Rate Divisor
932
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Register 7: UART Line Control (UARTLCRH), offset 0x02C
The UARTLCRH register is the line control register. Serial parameters such as data length, parity,
and stop bit selection are implemented in this register.
When updating the baud-rate divisor (UARTIBRD and/or UARTIFRD), the UARTLCRH register
must also be written. The write strobe for the baud-rate divisor registers is tied to the UARTLCRH
register.
UART Line Control (UARTLCRH)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
UART3 base: 0x4000.F000
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0x02C
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
FEN
STP2
EPS
PEN
BRK
RW
0
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
reserved
Type
Reset
SPS
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7
SPS
RW
0
RW
0
WLEN
RW
0
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
UART Stick Parity Select
When bits 1, 2, and 7 of UARTLCRH are set, the parity bit is transmitted
and checked as a 0. When bits 1 and 7 are set and 2 is cleared, the
parity bit is transmitted and checked as a 1.
When this bit is cleared, stick parity is disabled.
6:5
WLEN
RW
0x0
UART Word Length
The bits indicate the number of data bits transmitted or received in a
frame as follows:
Value Description
0x0
5 bits (default)
0x1
6 bits
0x2
7 bits
0x3
8 bits
June 12, 2014
933
Texas Instruments-Production Data
Universal Asynchronous Receivers/Transmitters (UARTs)
Bit/Field
Name
Type
Reset
4
FEN
RW
0
Description
UART Enable FIFOs
Value Description
3
STP2
RW
0
0
The FIFOs are disabled (Character mode). The FIFOs become
1-byte-deep holding registers.
1
The transmit and receive FIFO buffers are enabled (FIFO mode).
UART Two Stop Bits Select
Value Description
0
One stop bit is transmitted at the end of a frame.
1
Two stop bits are transmitted at the end of a frame. The receive
logic does not check for two stop bits being received.
When in 7816 smartcard mode (the SMART bit is set in the
UARTCTL register), the number of stop bits is forced to 2.
2
EPS
RW
0
UART Even Parity Select
Value Description
0
Odd parity is performed, which checks for an odd number of 1s.
1
Even parity generation and checking is performed during
transmission and reception, which checks for an even number
of 1s in data and parity bits.
This bit has no effect when parity is disabled by the PEN bit.
1
PEN
RW
0
UART Parity Enable
Value Description
0
BRK
RW
0
0
Parity is disabled and no parity bit is added to the data frame.
1
Parity checking and generation is enabled.
UART Send Break
Value Description
0
Normal use.
1
A Low level is continually output on the UnTx signal, after
completing transmission of the current character. For the proper
execution of the break command, software must set this bit for
at least two frames (character periods).
934
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Register 8: UART Control (UARTCTL), offset 0x030
The UARTCTL register is the control register. All the bits are cleared on reset except for the Transmit
Enable (TXE) and Receive Enable (RXE) bits, which are set.
To enable the UART module, the UARTEN bit must be set. If software requires a configuration change
in the module, the UARTEN bit must be cleared before the configuration changes are written. If the
UART is disabled during a transmit or receive operation, the current transaction is completed prior
to the UART stopping.
Note that bits [15:14,11:10] are only implemented on UART1. These bits are reserved on UART0
and UART2.
Note:
The UARTCTL register should not be changed while the UART is enabled or else the results
are unpredictable. The following sequence is recommended for making changes to the
UARTCTL register.
1. Disable the UART.
2. Wait for the end of transmission or reception of the current character.
3. Flush the transmit FIFO by clearing bit 4 (FEN) in the line control register (UARTLCRH).
4. Reprogram the control register.
5. Enable the UART.
UART Control (UARTCTL)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
UART3 base: 0x4000.F000
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0x030
Type RW, reset 0x0000.0300
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
CTSEN
RTSEN
RTS
DTR
RW
0
RW
0
RW
0
RW
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RXE
TXE
LBE
reserved
HSE
EOT
SMART
SIRLP
SIREN
UARTEN
RW
1
RW
1
RW
0
RO
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
Type
Reset
reserved
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:16
reserved
RO
0x0000
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
June 12, 2014
935
Texas Instruments-Production Data
Universal Asynchronous Receivers/Transmitters (UARTs)
Bit/Field
Name
Type
Reset
15
CTSEN
RW
0
Description
Enable Clear To Send
Value Description
0
CTS hardware flow control is disabled.
1
CTS hardware flow control is enabled. Data is only transmitted
when the U1CTS signal is asserted.
This bit is implemented only on UART1 and is reserved for UART0 and
UART2.
14
RTSEN
RW
0
Enable Request to Send
Value Description
0
RTS hardware flow control is disabled.
1
RTS hardware flow control is enabled. Data is only requested
(by asserting U1RTS) when the receive FIFO has available
entries.
This bit is implemented only on UART1 and is reserved for UART0 and
UART2.
13:12
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
11
RTS
RW
0
Request to Send
When RTSEN is clear, the status of this bit is reflected on the U1RTS
signal. If RTSEN is set, this bit is ignored on a write and should be ignored
on read.
This bit is implemented only on UART1 and is reserved for UART0 and
UART2.
10
DTR
RW
0
Data Terminal Ready
This bit sets the state of the U1DTR output.
This bit is implemented only on UART1 and is reserved for UART0 and
UART2.
9
RXE
RW
1
UART Receive Enable
Value Description
0
The receive section of the UART is disabled.
1
The receive section of the UART is enabled.
If the UART is disabled in the middle of a receive, it completes the current
character before stopping.
Note:
To enable reception, the UARTEN bit must also be set.
936
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Bit/Field
Name
Type
Reset
8
TXE
RW
1
Description
UART Transmit Enable
Value Description
0
The transmit section of the UART is disabled.
1
The transmit section of the UART is enabled.
If the UART is disabled in the middle of a transmission, it completes the
current character before stopping.
Note:
7
LBE
RW
0
To enable transmission, the UARTEN bit must also be set.
UART Loop Back Enable
Value Description
0
Normal operation.
1
The UnTx path is fed through the UnRx path.
6
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5
HSE
RW
0
High-Speed Enable
Value Description
0
The UART is clocked using the system clock divided by 16.
1
The UART is clocked using the system clock divided by 8.
Note:
System clock used is also dependent on the baud-rate divisor
configuration (see page 931) and page 932).
The state of this bit has no effect on clock generation in ISO
7816 smart card mode (the SMART bit is set).
4
EOT
RW
0
End of Transmission
This bit determines the behavior of the TXRIS bit in the UARTRIS
register.
Value Description
0
The TXRIS bit is set when the transmit FIFO condition specified
in UARTIFLS is met.
1
The TXRIS bit is set only after all transmitted data, including
stop bits, have cleared the serializer.
June 12, 2014
937
Texas Instruments-Production Data
Universal Asynchronous Receivers/Transmitters (UARTs)
Bit/Field
Name
Type
Reset
3
SMART
RW
0
Description
ISO 7816 Smart Card Support
Value Description
0
Normal operation.
1
The UART operates in Smart Card mode.
The application must ensure that it sets 8-bit word length (WLEN set to
0x3) and even parity (PEN set to 1, EPS set to 1, SPS set to 0) in
UARTLCRH when using ISO 7816 mode.
In this mode, the value of the STP2 bit in UARTLCRH is ignored and
the number of stop bits is forced to 2. Note that the UART does not
support automatic retransmission on parity errors. If a parity error is
detected on transmission, all further transmit operations are aborted
and software must handle retransmission of the affected byte or
message.
2
SIRLP
RW
0
UART SIR Low-Power Mode
This bit selects the IrDA encoding mode.
Value Description
0
Low-level bits are transmitted as an active High pulse with a
width of 3/16th of the bit period.
1
The UART operates in SIR Low-Power mode. Low-level bits
are transmitted with a pulse width which is 3 times the period
of the IrLPBaud16 input signal, regardless of the selected bit
rate.
Setting this bit uses less power, but might reduce transmission distances.
See page 930 for more information.
1
SIREN
RW
0
UART SIR Enable
Value Description
0
UARTEN
RW
0
0
Normal operation.
1
The IrDA SIR block is enabled, and the UART will transmit and
receive data using SIR protocol.
UART Enable
Value Description
0
The UART is disabled.
1
The UART is enabled.
If the UART is disabled in the middle of transmission or reception, it
completes the current character before stopping.
938
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Register 9: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034
The UARTIFLS register is the interrupt FIFO level select register. You can use this register to define
the FIFO level at which the TXRIS and RXRIS bits in the UARTRIS register are triggered.
The interrupts are generated based on a transition through a level rather than being based on the
level. That is, the interrupts are generated when the fill level progresses through the trigger level.
For example, if the receive trigger level is set to the half-way mark, the interrupt is triggered as the
module is receiving the 9th character.
Out of reset, the TXIFLSEL and RXIFLSEL bits are configured so that the FIFOs trigger an interrupt
at the half-way mark.
UART Interrupt FIFO Level Select (UARTIFLS)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
UART3 base: 0x4000.F000
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0x034
Type RW, reset 0x0000.0012
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
4
3
2
1
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RXIFLSEL
RO
0
Bit/Field
Name
Type
Reset
31:6
reserved
RO
0x0000.00
5:3
RXIFLSEL
RW
0x2
RO
0
RO
0
RO
0
RW
0
RW
1
TXIFLSEL
RW
0
RW
0
RW
1
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
UART Receive Interrupt FIFO Level Select
The trigger points for the receive interrupt are as follows:
Value
Description
0x0
RX FIFO ≥ ⅛ full
0x1
RX FIFO ≥ ¼ full
0x2
RX FIFO ≥ ½ full (default)
0x3
RX FIFO ≥ ¾ full
0x4
RX FIFO ≥ ⅞ full
0x5-0x7 Reserved
June 12, 2014
939
Texas Instruments-Production Data
Universal Asynchronous Receivers/Transmitters (UARTs)
Bit/Field
Name
Type
Reset
2:0
TXIFLSEL
RW
0x2
Description
UART Transmit Interrupt FIFO Level Select
The trigger points for the transmit interrupt are as follows:
Value
Description
0x0
TX FIFO ≤ ⅞ empty
0x1
TX FIFO ≤ ¾ empty
0x2
TX FIFO ≤ ½ empty (default)
0x3
TX FIFO ≤ ¼ empty
0x4
TX FIFO ≤ ⅛ empty
0x5-0x7 Reserved
Note:
If the EOT bit in UARTCTL is set (see page 935), the transmit
interrupt is generated once the FIFO is completely empty and
all data including stop bits have left the transmit serializer. In
this case, the setting of TXIFLSEL is ignored.
940
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Register 10: UART Interrupt Mask (UARTIM), offset 0x038
The UARTIM register is the interrupt mask set/clear register.
On a read, this register gives the current value of the mask on the relevant interrupt. Setting a bit
allows the corresponding raw interrupt signal to be routed to the interrupt controller. Clearing a bit
prevents the raw interrupt signal from being sent to the interrupt controller.
Note that bits [3:0] are only implemented on UART1. These bits are reserved on UART0 and UART2.
UART Interrupt Mask (UARTIM)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
UART3 base: 0x4000.F000
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0x038
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
15
RO
0
RO
0
14
13
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
12
11
10
9
8
7
6
5
4
3
2
1
0
9BITIM
reserved
OEIM
BEIM
PEIM
FEIM
RTIM
TXIM
RXIM
DSRIM
DCDIM
CTSIM
RIIM
RW
0
RO
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:13
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
12
9BITIM
RW
0
9-Bit Mode Interrupt Mask
Value Description
0
The 9BITRIS interrupt is suppressed and not sent to the
interrupt controller.
1
An interrupt is sent to the interrupt controller when the 9BITRIS
bit in the UARTRIS register is set.
11
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
10
OEIM
RW
0
UART Overrun Error Interrupt Mask
Value Description
0
The OERIS interrupt is suppressed and not sent to the interrupt
controller.
1
An interrupt is sent to the interrupt controller when the OERIS
bit in the UARTRIS register is set.
June 12, 2014
941
Texas Instruments-Production Data
Universal Asynchronous Receivers/Transmitters (UARTs)
Bit/Field
Name
Type
Reset
9
BEIM
RW
0
Description
UART Break Error Interrupt Mask
Value Description
8
PEIM
RW
0
0
The BERIS interrupt is suppressed and not sent to the interrupt
controller.
1
An interrupt is sent to the interrupt controller when the BERIS
bit in the UARTRIS register is set.
UART Parity Error Interrupt Mask
Value Description
7
FEIM
RW
0
0
The PERIS interrupt is suppressed and not sent to the interrupt
controller.
1
An interrupt is sent to the interrupt controller when the PERIS
bit in the UARTRIS register is set.
UART Framing Error Interrupt Mask
Value Description
6
RTIM
RW
0
0
The FERIS interrupt is suppressed and not sent to the interrupt
controller.
1
An interrupt is sent to the interrupt controller when the FERIS
bit in the UARTRIS register is set.
UART Receive Time-Out Interrupt Mask
Value Description
5
TXIM
RW
0
0
The RTRIS interrupt is suppressed and not sent to the interrupt
controller.
1
An interrupt is sent to the interrupt controller when the RTRIS
bit in the UARTRIS register is set.
UART Transmit Interrupt Mask
Value Description
4
RXIM
RW
0
0
The TXRIS interrupt is suppressed and not sent to the interrupt
controller.
1
An interrupt is sent to the interrupt controller when the TXRIS
bit in the UARTRIS register is set.
UART Receive Interrupt Mask
Value Description
0
The RXRIS interrupt is suppressed and not sent to the interrupt
controller.
1
An interrupt is sent to the interrupt controller when the RXRIS
bit in the UARTRIS register is set.
942
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Bit/Field
Name
Type
Reset
3
DSRIM
RW
0
Description
UART Data Set Ready Modem Interrupt Mask
Value Description
0
The DSRRIS interrupt is suppressed and not sent to the interrupt
controller.
1
An interrupt is sent to the interrupt controller when the DSRRIS
bit in the UARTRIS register is set.
This bit is implemented only on UART1 and is reserved for UART0 and
UART2.
2
DCDIM
RW
0
UART Data Carrier Detect Modem Interrupt Mask
Value Description
0
The DCDRIS interrupt is suppressed and not sent to the interrupt
controller.
1
An interrupt is sent to the interrupt controller when the DCDRIS
bit in the UARTRIS register is set.
This bit is implemented only on UART1 and is reserved for UART0 and
UART2.
1
CTSIM
RW
0
UART Clear to Send Modem Interrupt Mask
Value Description
0
The CTSRIS interrupt is suppressed and not sent to the interrupt
controller.
1
An interrupt is sent to the interrupt controller when the CTSRIS
bit in the UARTRIS register is set.
This bit is implemented only on UART1 and is reserved for UART0 and
UART2.
0
RIIM
RW
0
UART Ring Indicator Modem Interrupt Mask
Value Description
0
The RIRIS interrupt is suppressed and not sent to the interrupt
controller.
1
An interrupt is sent to the interrupt controller when the RIRIS
bit in the UARTRIS register is set.
This bit is implemented only on UART1 and is reserved for UART0 and
UART2.
June 12, 2014
943
Texas Instruments-Production Data
Universal Asynchronous Receivers/Transmitters (UARTs)
Register 11: UART Raw Interrupt Status (UARTRIS), offset 0x03C
The UARTRIS register is the raw interrupt status register. On a read, this register gives the current
raw status value of the corresponding interrupt. A write has no effect.
Note that bits [3:0] are only implemented on UART1. These bits are reserved on UART0 and UART2.
UART Raw Interrupt Status (UARTRIS)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
UART3 base: 0x4000.F000
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0x03C
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
9BITRIS
reserved
OERIS
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
BERIS
PERIS
FERIS
RTRIS
TXRIS
RXRIS
DSRRIS
DCDRIS
CTSRIS
RIRIS
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:13
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
12
9BITRIS
RO
0
9-Bit Mode Raw Interrupt Status
Value Description
0
No interrupt
1
A receive address match has occurred.
This bit is cleared by writing a 1 to the 9BITIC bit in the UARTICR
register.
11
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
10
OERIS
RO
0
UART Overrun Error Raw Interrupt Status
Value Description
0
No interrupt
1
An overrun error has occurred.
This bit is cleared by writing a 1 to the OEIC bit in the UARTICR register.
944
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Bit/Field
Name
Type
Reset
9
BERIS
RO
0
Description
UART Break Error Raw Interrupt Status
Value Description
0
No interrupt
1
A break error has occurred.
This bit is cleared by writing a 1 to the BEIC bit in the UARTICR register.
8
PERIS
RO
0
UART Parity Error Raw Interrupt Status
Value Description
0
No interrupt
1
A parity error has occurred.
This bit is cleared by writing a 1 to the PEIC bit in the UARTICR register.
7
FERIS
RO
0
UART Framing Error Raw Interrupt Status
Value Description
0
No interrupt
1
A framing error has occurred.
This bit is cleared by writing a 1 to the FEIC bit in the UARTICR register.
6
RTRIS
RO
0
UART Receive Time-Out Raw Interrupt Status
Value Description
0
No interrupt
1
A receive time out has occurred.
This bit is cleared by writing a 1 to the RTIC bit in the UARTICR register.
For receive timeout, the RTIM bit in the UARTIM register must be set
to see the RTRIS status.
5
TXRIS
RO
0
UART Transmit Raw Interrupt Status
Value Description
0
No interrupt
1
If the EOT bit in the UARTCTL register is clear, the transmit
FIFO level has passed through the condition defined in the
UARTIFLS register.
If the EOT bit is set, the last bit of all transmitted data and flags
has left the serializer.
This bit is cleared by writing a 1 to the TXIC bit in the UARTICR register
or by writing data to the transmit FIFO until it becomes greater than the
trigger level, if the FIFO is enabled, or by writing a single byte if the FIFO
is disabled.
June 12, 2014
945
Texas Instruments-Production Data
Universal Asynchronous Receivers/Transmitters (UARTs)
Bit/Field
Name
Type
Reset
4
RXRIS
RO
0
Description
UART Receive Raw Interrupt Status
Value Description
0
No interrupt
1
The receive FIFO level has passed through the condition defined
in the UARTIFLS register.
This bit is cleared by writing a 1 to the RXIC bit in the UARTICR register
or by reading data from the receive FIFO until it becomes less than the
trigger level, if the FIFO is enabled, or by reading a single byte if the
FIFO is disabled.
3
DSRRIS
RO
0
UART Data Set Ready Modem Raw Interrupt Status
Value Description
0
No interrupt
1
Data Set Ready used for software flow control.
This bit is cleared by writing a 1 to the DSRIC bit in the UARTICR
register.
This bit is implemented only on UART1 and is reserved for UART0 and
UART2.
2
DCDRIS
RO
0
UART Data Carrier Detect Modem Raw Interrupt Status
Value Description
0
No interrupt
1
Data Carrier Detect used for software flow control.
This bit is cleared by writing a 1 to the DCDIC bit in the UARTICR
register.
This bit is implemented only on UART1 and is reserved for UART0 and
UART2.
1
CTSRIS
RO
0
UART Clear to Send Modem Raw Interrupt Status
Value Description
0
No interrupt
1
Clear to Send used for software flow control.
This bit is cleared by writing a 1 to the CTSIC bit in the UARTICR
register.
This bit is implemented only on UART1 and is reserved for UART0 and
UART2.
0
RIRIS
RO
0
UART Ring Indicator Modem Raw Interrupt Status
Value Description
0
No interrupt
1
Ring Indicator used for software flow control.
This bit is cleared by writing a 1 to the RIIC bit in the UARTICR register.
This bit is implemented only on UART1 and is reserved for UART0 and
UART2.
946
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040
The UARTMIS register is the masked interrupt status register. On a read, this register gives the
current masked status value of the corresponding interrupt. A write has no effect.
Note that bits [3:0] are only implemented on UART1. These bits are reserved on UART0 and UART2.
UART Masked Interrupt Status (UARTMIS)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
UART3 base: 0x4000.F000
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0x040
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
9BITMIS
reserved
OEMIS
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
BEMIS
PEMIS
FEMIS
RTMIS
TXMIS
RXMIS
CTSMIS
RIMIS
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
RO
0
RO
0
DSRMIS DCDMIS
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:13
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
12
9BITMIS
RO
0
9-Bit Mode Masked Interrupt Status
Value Description
0
An interrupt has not occurred or is masked.
1
An unmasked interrupt was signaled due to a receive address
match.
This bit is cleared by writing a 1 to the 9BITIC bit in the UARTICR
register.
11
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
10
OEMIS
RO
0
UART Overrun Error Masked Interrupt Status
Value Description
0
An interrupt has not occurred or is masked.
1
An unmasked interrupt was signaled due to an overrun error.
This bit is cleared by writing a 1 to the OEIC bit in the UARTICR register.
June 12, 2014
947
Texas Instruments-Production Data
Universal Asynchronous Receivers/Transmitters (UARTs)
Bit/Field
Name
Type
Reset
9
BEMIS
RO
0
Description
UART Break Error Masked Interrupt Status
Value Description
0
An interrupt has not occurred or is masked.
1
An unmasked interrupt was signaled due to a break error.
This bit is cleared by writing a 1 to the BEIC bit in the UARTICR register.
8
PEMIS
RO
0
UART Parity Error Masked Interrupt Status
Value Description
0
An interrupt has not occurred or is masked.
1
An unmasked interrupt was signaled due to a parity error.
This bit is cleared by writing a 1 to the PEIC bit in the UARTICR register.
7
FEMIS
RO
0
UART Framing Error Masked Interrupt Status
Value Description
0
An interrupt has not occurred or is masked.
1
An unmasked interrupt was signaled due to a framing error.
This bit is cleared by writing a 1 to the FEIC bit in the UARTICR register.
6
RTMIS
RO
0
UART Receive Time-Out Masked Interrupt Status
Value Description
0
An interrupt has not occurred or is masked.
1
An unmasked interrupt was signaled due to a receive time out.
This bit is cleared by writing a 1 to the RTIC bit in the UARTICR register.
For receive timeout, the RTIM bit in the UARTIM register must be set
to see the RTMIS status.
5
TXMIS
RO
0
UART Transmit Masked Interrupt Status
Value Description
0
An interrupt has not occurred or is masked.
1
An unmasked interrupt was signaled due to passing through
the specified transmit FIFO level (if the EOT bit is clear) or due
to the transmission of the last data bit (if the EOT bit is set).
This bit is cleared by writing a 1 to the TXIC bit in the UARTICR register
or by writing data to the transmit FIFO until it becomes greater than the
trigger level, if the FIFO is enabled, or by writing a single byte if the FIFO
is disabled.
948
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Bit/Field
Name
Type
Reset
4
RXMIS
RO
0
Description
UART Receive Masked Interrupt Status
Value Description
0
An interrupt has not occurred or is masked.
1
An unmasked interrupt was signaled due to passing through
the specified receive FIFO level.
This bit is cleared by writing a 1 to the RXIC bit in the UARTICR register
or by reading data from the receive FIFO until it becomes less than the
trigger level, if the FIFO is enabled, or by reading a single byte if the
FIFO is disabled.
3
DSRMIS
RO
0
UART Data Set Ready Modem Masked Interrupt Status
Value Description
0
An interrupt has not occurred or is masked.
1
An unmasked interrupt was signaled due to Data Set Ready.
This bit is cleared by writing a 1 to the DSRIC bit in the UARTICR
register.
This bit is implemented only on UART1 and is reserved for UART0 and
UART2.
2
DCDMIS
RO
0
UART Data Carrier Detect Modem Masked Interrupt Status
Value Description
0
An interrupt has not occurred or is masked.
1
An unmasked interrupt was signaled due to Data Carrier Detect.
This bit is cleared by writing a 1 to the DCDIC bit in the UARTICR
register.
This bit is implemented only on UART1 and is reserved for UART0 and
UART2.
1
CTSMIS
RO
0
UART Clear to Send Modem Masked Interrupt Status
Value Description
0
An interrupt has not occurred or is masked.
1
An unmasked interrupt was signaled due to Clear to Send.
This bit is cleared by writing a 1 to the CTSIC bit in the UARTICR
register.
This bit is implemented only on UART1 and is reserved for UART0 and
UART2.
0
RIMIS
RO
0
UART Ring Indicator Modem Masked Interrupt Status
Value Description
0
An interrupt has not occurred or is masked.
1
An unmasked interrupt was signaled due to Ring Indicator.
This bit is cleared by writing a 1 to the RIIC bit in the UARTICR register.
This bit is implemented only on UART1 and is reserved for UART0 and
UART2.
June 12, 2014
949
Texas Instruments-Production Data
Universal Asynchronous Receivers/Transmitters (UARTs)
Register 13: UART Interrupt Clear (UARTICR), offset 0x044
The UARTICR register is the interrupt clear register. On a write of 1, the corresponding interrupt
(both raw interrupt and masked interrupt, if enabled) is cleared. A write of 0 has no effect.
Note that bits [3:0] are only implemented on UART1. These bits are reserved on UART0 and UART2.
UART Interrupt Clear (UARTICR)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
UART3 base: 0x4000.F000
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0x044
Type W1C, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
9BITIC
reserved
OEIC
RW
0
RO
0
W1C
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
BEIC
PEIC
FEIC
RTIC
TXIC
RXIC
W1C
0
W1C
0
W1C
0
W1C
0
W1C
0
W1C
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
RO
0
RO
0
DSRMIC DCDMIC CTSMIC
W1C
0
W1C
0
W1C
0
RIMIC
W1C
0
Bit/Field
Name
Type
Reset
Description
31:13
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
12
9BITIC
RW
0
9-Bit Mode Interrupt Clear
Writing a 1 to this bit clears the 9BITRIS bit in the UARTRIS register
and the 9BITMIS bit in the UARTMIS register.
11
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
10
OEIC
W1C
0
Overrun Error Interrupt Clear
Writing a 1 to this bit clears the OERIS bit in the UARTRIS register and
the OEMIS bit in the UARTMIS register.
9
BEIC
W1C
0
Break Error Interrupt Clear
Writing a 1 to this bit clears the BERIS bit in the UARTRIS register and
the BEMIS bit in the UARTMIS register.
8
PEIC
W1C
0
Parity Error Interrupt Clear
Writing a 1 to this bit clears the PERIS bit in the UARTRIS register and
the PEMIS bit in the UARTMIS register.
7
FEIC
W1C
0
Framing Error Interrupt Clear
Writing a 1 to this bit clears the FERIS bit in the UARTRIS register and
the FEMIS bit in the UARTMIS register.
950
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Bit/Field
Name
Type
Reset
6
RTIC
W1C
0
Description
Receive Time-Out Interrupt Clear
Writing a 1 to this bit clears the RTRIS bit in the UARTRIS register and
the RTMIS bit in the UARTMIS register.
5
TXIC
W1C
0
Transmit Interrupt Clear
Writing a 1 to this bit clears the TXRIS bit in the UARTRIS register and
the TXMIS bit in the UARTMIS register.
4
RXIC
W1C
0
Receive Interrupt Clear
Writing a 1 to this bit clears the RXRIS bit in the UARTRIS register and
the RXMIS bit in the UARTMIS register.
3
DSRMIC
W1C
0
UART Data Set Ready Modem Interrupt Clear
Writing a 1 to this bit clears the DSRRIS bit in the UARTRIS register
and the DSRMIS bit in the UARTMIS register.
This bit is implemented only on UART1 and is reserved for UART0 and
UART2.
2
DCDMIC
W1C
0
UART Data Carrier Detect Modem Interrupt Clear
Writing a 1 to this bit clears the DCDRIS bit in the UARTRIS register
and the DCDMIS bit in the UARTMIS register.
This bit is implemented only on UART1 and is reserved for UART0 and
UART2.
1
CTSMIC
W1C
0
UART Clear to Send Modem Interrupt Clear
Writing a 1 to this bit clears the CTSRIS bit in the UARTRIS register
and the CTSMIS bit in the UARTMIS register.
This bit is implemented only on UART1 and is reserved for UART0 and
UART2.
0
RIMIC
W1C
0
UART Ring Indicator Modem Interrupt Clear
Writing a 1 to this bit clears the RIRIS bit in the UARTRIS register and
the RIMIS bit in the UARTMIS register.
This bit is implemented only on UART1 and is reserved for UART0 and
UART2.
June 12, 2014
951
Texas Instruments-Production Data
Universal Asynchronous Receivers/Transmitters (UARTs)
Register 14: UART DMA Control (UARTDMACTL), offset 0x048
The UARTDMACTL register is the DMA control register.
UART DMA Control (UARTDMACTL)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
UART3 base: 0x4000.F000
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0x048
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
2
1
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
9
8
7
6
5
4
3
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
31:3
reserved
RO
2
DMAERR
RW
RO
0
Reset
DMAERR TXDMAE RXDMAE
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
RW
0
RW
0
Description
0x00000.000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
DMA on Error
Value Description
1
TXDMAE
RW
0
0
µDMA receive requests are unaffected when a receive error
occurs.
1
µDMA receive requests are automatically disabled when a
receive error occurs.
Transmit DMA Enable
Value Description
0
RXDMAE
RW
0
0
µDMA for the transmit FIFO is disabled.
1
µDMA for the transmit FIFO is enabled.
Receive DMA Enable
Value Description
0
µDMA for the receive FIFO is disabled.
1
µDMA for the receive FIFO is enabled.
952
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Register 15: UART 9-Bit Self Address (UART9BITADDR), offset 0x0A4
The UART9BITADDR register is used to write the specific address that should be matched with the
receiving byte when the 9-bit Address Mask (UART9BITAMASK) is set to 0xFF. This register is
used in conjunction with UART9BITAMASK to form a match for address-byte received.
UART 9-Bit Self Address (UART9BITADDR)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
UART3 base: 0x4000.F000
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0x0A4
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
15
14
13
12
9BITEN
Type
Reset
RW
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
11
10
9
8
7
6
5
4
reserved
RO
0
RO
0
RO
0
ADDR
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:16
reserved
RO
0x0000
15
9BITEN
RW
0
RO
0
RW
0
RW
0
RW
0
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Enable 9-Bit Mode
Value Description
0
9-bit mode is disabled.
1
9-bit mode is enabled.
14:8
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
ADDR
RW
0x00
Self Address for 9-Bit Mode
This field contains the address that should be matched when
UART9BITAMASK is 0xFF.
June 12, 2014
953
Texas Instruments-Production Data
Universal Asynchronous Receivers/Transmitters (UARTs)
Register 16: UART 9-Bit Self Address Mask (UART9BITAMASK), offset 0x0A8
The UART9BITAMASK register is used to enable the address mask for 9-bit mode. The address
bits are masked to create a set of addresses to be matched with the received address byte.
UART 9-Bit Self Address Mask (UART9BITAMASK)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
UART3 base: 0x4000.F000
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0x0A8
Type RW, reset 0x0000.00FF
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RW
1
RW
1
RW
1
RW
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
MASK
RO
0
RO
0
RO
0
RO
0
RW
1
RW
1
RW
1
RW
1
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
MASK
RW
0xFF
Self Address Mask for 9-Bit Mode
This field contains the address mask that creates a set of addresses
that should be matched.
954
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Register 17: UART Peripheral Properties (UARTPP), offset 0xFC0
The UARTPP register provides information regarding the properties of the UART module.
UART Peripheral Properties (UARTPP)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
UART3 base: 0x4000.F000
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0xFC0
Type RO, reset 0x0000.0003
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:2
reserved
RO
0x0000.000
1
NB
RO
0x1
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
1
0
NB
SC
RO
1
RO
1
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
9-Bit Support
Value Description
0
SC
RO
0x1
0
The UART module does not provide support for the transmission
of 9-bit data for RS-485 support.
1
The UART module provides support for the transmission of 9-bit
data for RS-485 support.
Smart Card Support
Value Description
0
The UART module does not provide smart card support.
1
The UART module provides smart card support.
June 12, 2014
955
Texas Instruments-Production Data
Universal Asynchronous Receivers/Transmitters (UARTs)
Register 18: UART Clock Configuration (UARTCC), offset 0xFC8
The UARTCC register controls the baud clock source for the UART module. For more information,
see the section called “Communication Clock Sources” on page 218.
Note:
If the PIOSC is used for the UART baud clock, the system clock frequency must be at least
9 MHz in Run mode.
UART Clock Configuration (UARTCC)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
UART3 base: 0x4000.F000
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0xFC8
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
reserved
Type
Reset
CS
Bit/Field
Name
Type
Reset
31:4
reserved
RO
0x0000.000
3:0
CS
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
UART Baud Clock Source
The following table specifies the source that generates for the UART
baud clock:
Value
Description
0x0
System clock (based on clock source and divisor factor)
0x1-0x4 reserved
0x5
PIOSC
0x5-0xF Reserved
956
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Register 19: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 4 (UARTPeriphID4)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
UART3 base: 0x4000.F000
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0xFD0
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
PID4
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
PID4
RO
0x00
RO
0
RO
0
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
UART Peripheral ID Register [7:0]
Can be used by software to identify the presence of this peripheral.
June 12, 2014
957
Texas Instruments-Production Data
Universal Asynchronous Receivers/Transmitters (UARTs)
Register 20: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 5 (UARTPeriphID5)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
UART3 base: 0x4000.F000
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0xFD4
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
PID5
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
PID5
RO
0x00
RO
0
RO
0
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
UART Peripheral ID Register [15:8]
Can be used by software to identify the presence of this peripheral.
958
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Register 21: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 6 (UARTPeriphID6)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
UART3 base: 0x4000.F000
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0xFD8
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
PID6
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
PID6
RO
0x00
RO
0
RO
0
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
UART Peripheral ID Register [23:16]
Can be used by software to identify the presence of this peripheral.
June 12, 2014
959
Texas Instruments-Production Data
Universal Asynchronous Receivers/Transmitters (UARTs)
Register 22: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 7 (UARTPeriphID7)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
UART3 base: 0x4000.F000
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0xFDC
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
PID7
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
PID7
RO
0x00
RO
0
RO
0
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
UART Peripheral ID Register [31:24]
Can be used by software to identify the presence of this peripheral.
960
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Register 23: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 0 (UARTPeriphID0)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
UART3 base: 0x4000.F000
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0xFE0
Type RO, reset 0x0000.0060
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
PID0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
PID0
RO
0x60
RO
0
RO
0
RO
1
RO
1
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
UART Peripheral ID Register [7:0]
Can be used by software to identify the presence of this peripheral.
June 12, 2014
961
Texas Instruments-Production Data
Universal Asynchronous Receivers/Transmitters (UARTs)
Register 24: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 1 (UARTPeriphID1)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
UART3 base: 0x4000.F000
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0xFE4
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
PID1
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
PID1
RO
0x00
RO
0
RO
0
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
UART Peripheral ID Register [15:8]
Can be used by software to identify the presence of this peripheral.
962
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Register 25: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 2 (UARTPeriphID2)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
UART3 base: 0x4000.F000
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0xFE8
Type RO, reset 0x0000.0018
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
1
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
PID2
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
PID2
RO
0x18
RO
0
RO
0
RO
0
RO
0
RO
1
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
UART Peripheral ID Register [23:16]
Can be used by software to identify the presence of this peripheral.
June 12, 2014
963
Texas Instruments-Production Data
Universal Asynchronous Receivers/Transmitters (UARTs)
Register 26: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 3 (UARTPeriphID3)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
UART3 base: 0x4000.F000
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0xFEC
Type RO, reset 0x0000.0001
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
0
RO
0
RO
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
PID3
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
PID3
RO
0x01
RO
0
RO
0
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
UART Peripheral ID Register [31:24]
Can be used by software to identify the presence of this peripheral.
964
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Register 27: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0
The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset
values.
UART PrimeCell Identification 0 (UARTPCellID0)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
UART3 base: 0x4000.F000
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0xFF0
Type RO, reset 0x0000.000D
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
1
RO
1
RO
0
RO
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
CID0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
CID0
RO
0x0D
RO
0
RO
0
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
UART PrimeCell ID Register [7:0]
Provides software a standard cross-peripheral identification system.
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Universal Asynchronous Receivers/Transmitters (UARTs)
Register 28: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4
The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset
values.
UART PrimeCell Identification 1 (UARTPCellID1)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
UART3 base: 0x4000.F000
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0xFF4
Type RO, reset 0x0000.00F0
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
CID1
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
CID1
RO
0xF0
RO
0
RO
1
RO
1
RO
1
RO
1
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
UART PrimeCell ID Register [15:8]
Provides software a standard cross-peripheral identification system.
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Register 29: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8
The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset
values.
UART PrimeCell Identification 2 (UARTPCellID2)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
UART3 base: 0x4000.F000
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0xFF8
Type RO, reset 0x0000.0005
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
1
RO
0
RO
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
CID2
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
CID2
RO
0x05
RO
0
RO
0
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
UART PrimeCell ID Register [23:16]
Provides software a standard cross-peripheral identification system.
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Universal Asynchronous Receivers/Transmitters (UARTs)
Register 30: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC
The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset
values.
UART PrimeCell Identification 3 (UARTPCellID3)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
UART3 base: 0x4000.F000
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0xFFC
Type RO, reset 0x0000.00B1
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
0
RO
0
RO
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
CID3
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
CID3
RO
0xB1
RO
0
RO
1
RO
0
RO
1
RO
1
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
UART PrimeCell ID Register [31:24]
Provides software a standard cross-peripheral identification system.
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15
Synchronous Serial Interface (SSI)
The TM4C123BH6PGE microcontroller includes four Synchronous Serial Interface (SSI) modules.
Each SSI module is a master or slave interface for synchronous serial communication with peripheral
devices that have either Freescale SPI, MICROWIRE, or Texas Instruments synchronous serial
interfaces.
The TM4C123BH6PGE SSI modules have the following features:
■ Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments
synchronous serial interfaces
■ Master or slave operation
■ Programmable clock bit rate and prescaler
■ Separate transmit and receive FIFOs, each 16 bits wide and 8 locations deep
■ Programmable data frame size from 4 to 16 bits
■ Internal loopback test mode for diagnostic/debug testing
■ Standard FIFO-based interrupts and End-of-Transmission interrupt
■ Efficient transfers using Micro Direct Memory Access Controller (µDMA)
– Separate channels for transmit and receive
– Receive single request asserted when data is in the FIFO; burst request asserted when FIFO
contains 4 entries
– Transmit single request asserted when there is space in the FIFO; burst request asserted
when four or more entries are available to be written in the FIFO
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15.1
Block Diagram
Figure 15-1. SSI Module Block Diagram
DMA Request
DMA Control
SSIDMACTL
Interrupt
Interrupt Control
TxFIFO
8 x 16
SSIIM
SSIMIS
SSIRIS
SSIICR
.
.
.
Control/Status
SSInTx
SSICR0
SSICR1
SSISR
SSInRx
Transmit/
Receive
Logic
SSIDR
RxFIFO
8 x 16
Clock Prescaler
System Clock
SSInClk
SSInFss
.
.
.
Clock Control
SSICPSR
SSICC
PIOSC
SSI Baud Clock
Identification Registers
SSIPCellID0
SSIPCellID1
SSIPCellID2
SSIPCellID3
15.2
SSIPeriphID0
SSIPeriphID1
SSIPeriphID2
SSIPeriphID3
SSIPeriphID4
SSIPeriphID5
SSIPeriphID6
SSIPeriphID7
Signal Description
The following table lists the external signals of the SSI module and describes the function of each.
Most SSI signals are alternate functions for some GPIO signals and default to be GPIO signals at
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reset. The exceptions to this rule are the SSI0Clk, SSI0Fss, SSI0Rx, and SSI0Tx pins, which
default to the SSI function. The "Pin Mux/Pin Assignment" column in the following table lists the
possible GPIO pin placements for the SSI signals. The AFSEL bit in the GPIO Alternate Function
Select (GPIOAFSEL) register (page 676) should be set to choose the SSI function. The number in
parentheses is the encoding that must be programmed into the PMCn field in the GPIO Port Control
(GPIOPCTL) register (page 695) to assign the SSI signal to the specified GPIO port pin. For more
information on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 647.
Table 15-1. SSI Signals (144LQFP)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
SSI0Clk
39
PA2 (2)
I/O
TTL
SSI module 0 clock
SSI0Fss
40
PA3 (2)
I/O
TTL
SSI module 0 frame signal
SSI0Rx
41
PA4 (2)
I
TTL
SSI module 0 receive
SSI0Tx
42
PA5 (2)
O
TTL
SSI module 0 transmit
SSI1Clk
1
64
PD0 (2)
PF2 (2)
I/O
TTL
SSI module 1 clock.
SSI1Fss
2
65
PD1 (2)
PF3 (2)
I/O
TTL
SSI module 1 frame signal.
SSI1Rx
3
62
PD2 (2)
PF0 (2)
I
TTL
SSI module 1 receive.
SSI1Tx
4
63
PD3 (2)
PF1 (2)
O
TTL
SSI module 1 transmit.
SSI2Clk
26
136
PH4 (2)
PB4 (2)
I/O
TTL
SSI module 2 clock.
SSI2Fss
23
135
PH5 (2)
PB5 (2)
I/O
TTL
SSI module 2 frame signal.
SSI2Rx
22
PH6 (2)
I
TTL
SSI module 2 receive.
SSI2Tx
21
PH7 (2)
O
TTL
SSI module 2 transmit.
SSI3Clk
1
16
32
PD0 (1)
PK0 (2)
PH0 (2)
I/O
TTL
SSI module 3 clock.
SSI3Fss
2
17
31
PD1 (1)
PK1 (2)
PH1 (2)
I/O
TTL
SSI module 3 frame signal.
SSI3Rx
3
18
28
PD2 (1)
PK2 (2)
PH2 (2)
I
TTL
SSI module 3 receive.
SSI3Tx
4
19
27
PD3 (1)
PK3 (2)
PH3 (2)
O
TTL
SSI module 3 transmit.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
15.3
Functional Description
The SSI performs serial-to-parallel conversion on data received from a peripheral device. The CPU
accesses data, control, and status information. The transmit and receive paths are buffered with
internal FIFO memories allowing up to eight 16-bit values to be stored independently in both transmit
and receive modes. The SSI also supports the µDMA interface. The transmit and receive FIFOs
can be programmed as destination/source addresses in the µDMA module. µDMA operation is
enabled by setting the appropriate bit(s) in the SSIDMACTL register (see page 1000).
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15.3.1
Bit Rate Generation
The SSI includes a programmable bit rate clock divider and prescaler to generate the serial output
clock. Bit rates are supported to 2 MHz and higher, although maximum bit rate is determined by
peripheral devices.
The serial bit rate is derived by dividing down the input clock (SysClk). The clock is first divided by
an even prescale value CPSDVSR from 2 to 254, which is programmed in the SSI Clock Prescale
(SSICPSR) register (see page 993). The clock is further divided by a value from 1 to 256, which is
1 + SCR, where SCR is the value programmed in the SSI Control 0 (SSICR0) register (see page 986).
The frequency of the output clock SSInClk is defined by:
SSInClk = SysClk / (CPSDVSR * (1 + SCR))
Note:
The System Clock or the PIOSC can be used as the source for the SSInClk. When the
CS field in the SSI Clock Configuration (SSICC) register is configured to 0x5, PIOSC is
selected as the source. For master mode, the system clock or the PIOSC must be at least
two times faster than the SSInClk, with the restriction that SSInClk cannot be faster than
25 MHz. For slave mode, the system clock or the PIOSC must be at least 12 times faster
than the SSInClk, with the restriction that SSInClk cannot be faster than 6.67 MHz.
See “Synchronous Serial Interface (SSI)” on page 1318 to view SSI timing parameters.
15.3.2
FIFO Operation
15.3.2.1
Transmit FIFO
The common transmit FIFO is a 16-bit wide, 8-locations deep, first-in, first-out memory buffer. The
CPU writes data to the FIFO by writing the SSI Data (SSIDR) register (see page 990), and data is
stored in the FIFO until it is read out by the transmission logic.
When configured as a master or a slave, parallel data is written into the transmit FIFO prior to serial
conversion and transmission to the attached slave or master, respectively, through the SSInTx pin.
In slave mode, the SSI transmits data each time the master initiates a transaction. If the transmit
FIFO is empty and the master initiates, the slave transmits the 8th most recent value in the transmit
FIFO. If less than 8 values have been written to the transmit FIFO since the SSI module clock was
enabled using the Rn bit in the RCGCSSI register, then 0 is transmitted. Care should be taken to
ensure that valid data is in the FIFO as needed. The SSI can be configured to generate an interrupt
or a µDMA request when the FIFO is empty.
15.3.2.2
Receive FIFO
The common receive FIFO is a 16-bit wide, 8-locations deep, first-in, first-out memory buffer.
Received data from the serial interface is stored in the buffer until read out by the CPU, which
accesses the read FIFO by reading the SSIDR register.
When configured as a master or slave, serial data received through the SSInRx pin is registered
prior to parallel loading into the attached slave or master receive FIFO, respectively.
15.3.3
Interrupts
The SSI can generate interrupts when the following conditions are observed:
■ Transmit FIFO service (when the transmit FIFO is half full or less)
■ Receive FIFO service (when the receive FIFO is half full or more)
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■ Receive FIFO time-out
■ Receive FIFO overrun
■ End of transmission
■ Receive DMA transfer complete
■ Transmit DMA transfer complete
All of the interrupt events are ORed together before being sent to the interrupt controller, so the SSI
generates a single interrupt request to the controller regardless of the number of active interrupts.
Each of the four individual maskable interrupts can be masked by clearing the appropriate bit in the
SSI Interrupt Mask (SSIIM) register (see page 994). Setting the appropriate mask bit enables the
interrupt.
The individual outputs, along with a combined interrupt output, allow use of either a global interrupt
service routine or modular device drivers to handle interrupts. The transmit and receive dynamic
dataflow interrupts have been separated from the status interrupts so that data can be read or written
in response to the FIFO trigger levels. The status of the individual interrupt sources can be read
from the SSI Raw Interrupt Status (SSIRIS) and SSI Masked Interrupt Status (SSIMIS) registers
(see page 995 and page 997, respectively).
The receive FIFO has a time-out period that is 32 periods at the rate of SSInClk (whether or not
SSInClk is currently active) and is started when the RX FIFO goes from EMPTY to not-EMPTY. If
the RX FIFO is emptied before 32 clocks have passed, the time-out period is reset. As a result, the
ISR should clear the Receive FIFO Time-out Interrupt just after reading out the RX FIFO by writing
a 1 to the RTIC bit in the SSI Interrupt Clear (SSIICR) register. The interrupt should not be cleared
so late that the ISR returns before the interrupt is actually cleared, or the ISR may be re-activated
unnecessarily.
The End-of-Transmission (EOT) interrupt indicates that the data has been transmitted completely
and is only valid for Master mode devices/operations. This interrupt can be used to indicate when
it is safe to turn off the SSI module clock or enter sleep mode. In addition, because transmitted data
and received data complete at exactly the same time, the interrupt can also indicate that read data
is ready immediately, without waiting for the receive FIFO time-out period to complete.
Note:
15.3.4
In Freescale SPI mode only, a condition can be created where an EOT interrupt is generated
for every byte transferred even if the FIFO is full. If the EOT bit has been set to 0 in an
integrated slave SSI and the µDMA has been configured to transfer data from this SSI to
a Master SSI on the device using external loopback, an EOT interrupt is generated by the
SSI slave for every byte even if the FIFO is full.
Frame Formats
Each data frame is between 4 and 16 bits long depending on the size of data programmed and is
transmitted starting with the MSB. There are three basic frame types that can be selected by
programming the FRF bit in the SSICR0 register:
■ Texas Instruments synchronous serial
■ Freescale SPI
■ MICROWIRE
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For all three formats, the serial clock (SSInClk) is held inactive while the SSI is idle, and SSInClk
transitions at the programmed frequency only during active transmission or reception of data. The
idle state of SSInClk is utilized to provide a receive timeout indication that occurs when the receive
FIFO still contains data after a timeout period.
For Freescale SPI and MICROWIRE frame formats, the serial frame (SSInFss) pin is active Low,
and is asserted (pulled down) during the entire transmission of the frame.
For Texas Instruments synchronous serial frame format, the SSInFss pin is pulsed for one serial
clock period starting at its rising edge, prior to the transmission of each frame. For this frame format,
both the SSI and the off-chip slave device drive their output data on the rising edge of SSInClk
and latch data from the other device on the falling edge.
Unlike the full-duplex transmission of the other two frame formats, the MICROWIRE format uses a
special master-slave messaging technique which operates at half-duplex. In this mode, when a
frame begins, an 8-bit control message is transmitted to the off-chip slave. During this transmit, no
incoming data is received by the SSI. After the message has been sent, the off-chip slave decodes
it and, after waiting one serial clock after the last bit of the 8-bit control message has been sent,
responds with the requested data. The returned data can be 4 to 16 bits in length, making the total
frame length anywhere from 13 to 25 bits.
15.3.4.1
Texas Instruments Synchronous Serial Frame Format
Figure 15-2 on page 974 shows the Texas Instruments synchronous serial frame format for a single
transmitted frame.
Figure 15-2. TI Synchronous Serial Frame Format (Single Transfer)
SSInClk
SSInFss
SSInTx/SSInRx
MSB
LSB
4 to 16 bits
In this mode, SSInClk and SSInFss are forced Low, and the transmit data line SSInTx is tristated
whenever the SSI is idle. Once the bottom entry of the transmit FIFO contains data, SSInFss is
pulsed High for one SSInClk period. The value to be transmitted is also transferred from the transmit
FIFO to the serial shift register of the transmit logic. On the next rising edge of SSInClk, the MSB
of the 4 to 16-bit data frame is shifted out on the SSInTx pin. Likewise, the MSB of the received
data is shifted onto the SSInRx pin by the off-chip serial slave device.
Both the SSI and the off-chip serial slave device then clock each data bit into their serial shifter on
each falling edge of SSInClk. The received data is transferred from the serial shifter to the receive
FIFO on the first rising edge of SSInClk after the LSB has been latched.
Figure 15-3 on page 975 shows the Texas Instruments synchronous serial frame format when
back-to-back frames are transmitted.
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Figure 15-3. TI Synchronous Serial Frame Format (Continuous Transfer)
SSInClk
SSInFss
SSInTx/SSInRx
MSB
LSB
4 to 16 bits
15.3.4.2
Freescale SPI Frame Format
The Freescale SPI interface is a four-wire interface where the SSInFss signal behaves as a slave
select. The main feature of the Freescale SPI format is that the inactive state and phase of the
SSInClk signal are programmable through the SPO and SPH bits in the SSICR0 control register.
SPO Clock Polarity Bit
When the SPO clock polarity control bit is clear, it produces a steady state Low value on the SSInClk
pin. If the SPO bit is set, a steady state High value is placed on the SSInClk pin when data is not
being transferred.
SPH Phase Control Bit
The SPH phase control bit selects the clock edge that captures data and allows it to change state.
The state of this bit has the most impact on the first bit transmitted by either allowing or not allowing
a clock transition before the first data capture edge. When the SPH phase control bit is clear, data
is captured on the first clock edge transition. If the SPH bit is set, data is captured on the second
clock edge transition.
15.3.4.3
Freescale SPI Frame Format with SPO=0 and SPH=0
Single and continuous transmission signal sequences for Freescale SPI format with SPO=0 and
SPH=0 are shown in Figure 15-4 on page 976 and Figure 15-5 on page 976.
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Figure 15-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0
SSInClk
SSInFss
SSInRx
LSB
MSB
Q
4 to 16 bits
SSInTx
MSB
Note:
LSB
Q is undefined.
Figure 15-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0
SSInClk
SSInFss
SSInRx LSB
LSB
MSB
MSB
4 to16 bits
SSInTx LSB
MSB
LSB
MSB
In this configuration, during idle periods:
■ SSInClk is forced Low
■ SSInFss is forced High
■ The transmit data line SSInTx is tristated
■ When the SSI is configured as a master, it enables the SSInClk pad
■ When the SSI is configured as a slave, it disables the SSInClk pad
If the SSI is enabled and valid data is in the transmit FIFO, the start of transmission is signified by
the SSInFss master signal being driven Low, causing slave data to be enabled onto the SSInRx
input line of the master. The master SSInTx output pad is enabled.
One half SSInClk period later, valid master data is transferred to the SSInTx pin. Once both the
master and slave data have been set, the SSInClk master clock pin goes High after one additional
half SSInClk period.
The data is now captured on the rising and propagated on the falling edges of the SSInClk signal.
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In the case of a single word transmission, after all bits of the data word have been transferred, the
SSInFss line is returned to its idle High state one SSInClk period after the last bit has been
captured.
However, in the case of continuous back-to-back transmissions, the SSInFss signal must be pulsed
High between each data word transfer because the slave select pin freezes the data in its serial
peripheral register and does not allow it to be altered if the SPH bit is clear. Therefore, the master
device must raise the SSInFss pin of the slave device between each data transfer to enable the
serial peripheral data write. On completion of the continuous transfer, the SSInFss pin is returned
to its idle state one SSInClk period after the last bit has been captured.
15.3.4.4
Freescale SPI Frame Format with SPO=0 and SPH=1
The transfer signal sequence for Freescale SPI format with SPO=0 and SPH=1 is shown in Figure
15-6 on page 977, which covers both single and continuous transfers.
Figure 15-6. Freescale SPI Frame Format with SPO=0 and SPH=1
SSInClk
SSInFss
SSInRx
Q
Q
MSB
LSB
Q
4 to 16 bits
SSInTx
LSB
MSB
Note:
Q is undefined.
In this configuration, during idle periods:
■ SSInClk is forced Low
■ SSInFss is forced High
■ The transmit data line SSInTx is tristated
■ When the SSI is configured as a master, it enables the SSInClk pad
■ When the SSI is configured as a slave, it disables the SSInClk pad
If the SSI is enabled and valid data is in the transmit FIFO, the start of transmission is signified by
the SSInFss master signal being driven Low. The master SSInTx output is enabled. After an
additional one-half SSInClk period, both master and slave valid data are enabled onto their
respective transmission lines. At the same time, the SSInClk is enabled with a rising edge transition.
Data is then captured on the falling edges and propagated on the rising edges of the SSInClk
signal.
In the case of a single word transfer, after all bits have been transferred, the SSInFss line is returned
to its idle High state one SSInClk period after the last bit has been captured.
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For continuous back-to-back transfers, the SSInFss pin is held Low between successive data
words, and termination is the same as that of the single word transfer.
15.3.4.5
Freescale SPI Frame Format with SPO=1 and SPH=0
Single and continuous transmission signal sequences for Freescale SPI format with SPO=1 and
SPH=0 are shown in Figure 15-7 on page 978 and Figure 15-8 on page 978.
Figure 15-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0
SSInClk
SSInFss
SSInRx
MSB
LSB
Q
4 to 16 bits
SSInTx
LSB
MSB
Note:
Q is undefined.
Figure 15-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0
SSInClk
SSInFss
SSInTx/SSInRx LSB
MSB
LSB
MSB
4 to 16 bits
In this configuration, during idle periods:
■ SSInClk is forced High
■ SSInFss is forced High
■ The transmit data line SSInTx is tristated
■ When the SSI is configured as a master, it enables the SSInClk pad
■ When the SSI is configured as a slave, it disables the SSInClk pad
If the SSI is enabled and valid data is in the transmit FIFO, the start of transmission is signified by
the SSInFss master signal being driven Low, causing slave data to be immediately transferred
onto the SSInRx line of the master. The master SSInTx output pad is enabled.
One-half period later, valid master data is transferred to the SSInTx line. Once both the master and
slave data have been set, the SSInClk master clock pin becomes Low after one additional half
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SSInClk period, meaning that data is captured on the falling edges and propagated on the rising
edges of the SSInClk signal.
In the case of a single word transmission, after all bits of the data word are transferred, the SSInFss
line is returned to its idle High state one SSInClk period after the last bit has been captured.
However, in the case of continuous back-to-back transmissions, the SSInFss signal must be pulsed
High between each data word transfer because the slave select pin freezes the data in its serial
peripheral register and does not allow it to be altered if the SPH bit is clear. Therefore, the master
device must raise the SSInFss pin of the slave device between each data transfer to enable the
serial peripheral data write. On completion of the continuous transfer, the SSInFss pin is returned
to its idle state one SSInClk period after the last bit has been captured.
15.3.4.6
Freescale SPI Frame Format with SPO=1 and SPH=1
The transfer signal sequence for Freescale SPI format with SPO=1 and SPH=1 is shown in Figure
15-9 on page 979, which covers both single and continuous transfers.
Figure 15-9. Freescale SPI Frame Format with SPO=1 and SPH=1
SSInClk
SSInFss
SSInRx
Q
MSB
LSB
Q
4 to 16 bits
MSB
SSInTx
Note:
LSB
Q is undefined.
In this configuration, during idle periods:
■ SSInClk is forced High
■ SSInFss is forced High
■ The transmit data line SSInTx is tristated
■ When the SSI is configured as a master, it enables the SSInClk pad
■ When the SSI is configured as a slave, it disables the SSInClk pad
If the SSI is enabled and valid data is in the transmit FIFO, the start of transmission is signified by
the SSInFss master signal being driven Low. The master SSInTx output pad is enabled. After an
additional one-half SSInClk period, both master and slave data are enabled onto their respective
transmission lines. At the same time, SSInClk is enabled with a falling edge transition. Data is then
captured on the rising edges and propagated on the falling edges of the SSInClk signal.
After all bits have been transferred, in the case of a single word transmission, the SSInFss line is
returned to its idle high state one SSInClk period after the last bit has been captured.
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For continuous back-to-back transmissions, the SSInFss pin remains in its active Low state until
the final bit of the last word has been captured and then returns to its idle state as described above.
For continuous back-to-back transfers, the SSInFss pin is held Low between successive data words
and termination is the same as that of the single word transfer.
15.3.4.7
MICROWIRE Frame Format
Figure 15-10 on page 980 shows the MICROWIRE frame format for a single frame. Figure
15-11 on page 981 shows the same format when back-to-back frames are transmitted.
Figure 15-10. MICROWIRE Frame Format (Single Frame)
SSInClk
SSInFss
SSInTx
LSB
MSB
8-bit control
0
SSInRx
MSB
LSB
4 to 16 bits
output data
MICROWIRE format is very similar to SPI format, except that transmission is half-duplex instead of
full-duplex and uses a master-slave message passing technique. Each serial transmission begins
with an 8-bit control word that is transmitted from the SSI to the off-chip slave device. During this
transmission, no incoming data is received by the SSI. After the message has been sent, the off-chip
slave decodes it and, after waiting one serial clock after the last bit of the 8-bit control message has
been sent, responds with the required data. The returned data is 4 to 16 bits in length, making the
total frame length anywhere from 13 to 25 bits.
In this configuration, during idle periods:
■ SSInClk is forced Low
■ SSInFss is forced High
■ The transmit data line SSInTx is tristated
A transmission is triggered by writing a control byte to the transmit FIFO. The falling edge of SSInFss
causes the value contained in the bottom entry of the transmit FIFO to be transferred to the serial
shift register of the transmit logic and the MSB of the 8-bit control frame to be shifted out onto the
SSInTx pin. SSInFss remains Low for the duration of the frame transmission. The SSInRx pin
remains tristated during this transmission.
The off-chip serial slave device latches each control bit into its serial shifter on each rising edge of
SSInClk. After the last bit is latched by the slave device, the control byte is decoded during a one
clock wait-state, and the slave responds by transmitting data back to the SSI. Each bit is driven onto
the SSInRx line on the falling edge of SSInClk. The SSI in turn latches each bit on the rising edge
of SSInClk. At the end of the frame, for single transfers, the SSInFss signal is pulled High one
clock period after the last bit has been latched in the receive serial shifter, causing the data to be
transferred to the receive FIFO.
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Note:
The off-chip slave device can tristate the receive line either on the falling edge of SSInClk
after the LSB has been latched by the receive shifter or when the SSInFss pin goes High.
For continuous transfers, data transmission begins and ends in the same manner as a single transfer.
However, the SSInFss line is continuously asserted (held Low) and transmission of data occurs
back-to-back. The control byte of the next frame follows directly after the LSB of the received data
from the current frame. Each of the received values is transferred from the receive shifter on the
falling edge of SSInClk, after the LSB of the frame has been latched into the SSI.
Figure 15-11. MICROWIRE Frame Format (Continuous Transfer)
SSInClk
SSInFss
SSInTx
LSB
MSB
LSB
8-bit control
SSInRx
0
MSB
MSB
LSB
4 to 16 bits
output data
In the MICROWIRE mode, the SSI slave samples the first bit of receive data on the rising edge of
SSInClk after SSInFss has gone Low. Masters that drive a free-running SSInClk must ensure
that the SSInFss signal has sufficient setup and hold margins with respect to the rising edge of
SSInClk.
Figure 15-12 on page 981 illustrates these setup and hold time requirements. With respect to the
SSInClk rising edge on which the first bit of receive data is to be sampled by the SSI slave, SSInFss
must have a setup of at least two times the period of SSInClk on which the SSI operates. With
respect to the SSInClk rising edge previous to this edge, SSInFss must have a hold of at least
one SSInClk period.
Figure 15-12. MICROWIRE Frame Format, SSInFss Input Setup and Hold Requirements
tSetup=(2*tSSIClk)
tHold=tSSIClk
SSInClk
SSInFss
SSInRx
First RX data to be
sampled by SSI slave
15.3.5
DMA Operation
The SSI peripheral provides an interface to the μDMA controller with separate channels for transmit
and receive. The µDMA operation of the SSI is enabled through the SSI DMA Control (SSIDMACTL)
register. When µDMA operation is enabled, the SSI asserts a µDMA request on the receive or
transmit channel when the associated FIFO can transfer data.
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For the receive channel, a single transfer request is asserted whenever any data is in the receive
FIFO. A burst transfer request is asserted whenever the amount of data in the receive FIFO is 4 or
more items. For the transmit channel, a single transfer request is asserted whenever at least one
empty location is in the transmit FIFO. The burst request is asserted whenever the transmit FIFO
has 4 or more empty slots. The single and burst µDMA transfer requests are handled automatically
by the μDMA controller depending how the µDMA channel is configured.
To enable µDMA operation for the receive channel, the RXDMAE bit of the DMA Control
(SSIDMACTL) register should be set after configuring the µDMA. To enable µDMA operation for
the transmit channel, the TXDMAE bit of SSIDMACTL should be set after configuring the µDMA. If
µDMA is enabled, then the μDMA controller triggers an interrupt when a transfer is complete. The
interrupt occurs on the SSI interrupt vector. Therefore, if interrupts are used for SSI operation and
µDMA is enabled, the SSI interrupt handler must be designed to handle the μDMA completion
interrupt.
When transfers are performed from a FIFO of the SSI using the μDMA, and any interrupt is generated
from the SSI, the SSI module's status bit in the DMA Channel Interrupt Status (DMACHIS) register
must be checked at the end of the interrupt service routine. If the status bit is set, clear the interrupt
by writing a 1 to it.
See “Micro Direct Memory Access (μDMA)” on page 583 for more details about programming the
μDMA controller.
15.4
Initialization and Configuration
To enable and initialize the SSI, the following steps are necessary:
1. Enable the SSI module using the RCGCSSI register (see page 342).
2. Enable the clock to the appropriate GPIO module via the RCGCGPIO register (see page 335).
To find out which GPIO port to enable, refer to Table 22-5 on page 1273.
3. Set the GPIO AFSEL bits for the appropriate pins (see page 676). To determine which GPIOs to
configure, see Table 22-4 on page 1262.
4. Configure the PMCn fields in the GPIOPCTL register to assign the SSI signals to the appropriate
pins. See page 695 and Table 22-5 on page 1273.
5. Program the GPIODEN register to enable the pin's digital function. In addition, the drive strength,
drain select and pull-up/pull-down functions must be configured. Refer to “General-Purpose
Input/Outputs (GPIOs)” on page 647 for more information.
Note:
Pull-ups can be used to avoid unnecessary toggles on the SSI pins, which can take the
slave to a wrong state. In addition, if the SSIClk signal is programmed to steady state
High through the SPO bit in the SSICR0 register, then software must also configure the
GPIO port pin corresponding to the SSInClk signal as a pull-up in the GPIO Pull-Up
Select (GPIOPUR) register.
For each of the frame formats, the SSI is configured using the following steps:
1. Ensure that the SSE bit in the SSICR1 register is clear before making any configuration changes.
2. Select whether the SSI is a master or slave:
a. For master operations, set the SSICR1 register to 0x0000.0000.
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b. For slave mode (output enabled), set the SSICR1 register to 0x0000.0004.
c. For slave mode (output disabled), set the SSICR1 register to 0x0000.000C.
3. Configure the SSI clock source by writing to the SSICC register.
4. Configure the clock prescale divisor by writing the SSICPSR register.
5. Write the SSICR0 register with the following configuration:
■ Serial clock rate (SCR)
■ Desired clock phase/polarity, if using Freescale SPI mode (SPH and SPO)
■ The protocol mode: Freescale SPI, TI SSF, MICROWIRE (FRF)
■ The data size (DSS)
6. Optionally, configure the SSI module for μDMA use with the following steps:
a. Configure a μDMA for SSI use. See “Micro Direct Memory Access (μDMA)” on page 583 for
more information.
b. Enable the SSI Module's TX FIFO or RX FIFO by setting the TXDMAE or RXDMAE bit in the
SSIDMACTL register.
7. Enable the SSI by setting the SSE bit in the SSICR1 register.
As an example, assume the SSI must be configured to operate with the following parameters:
■ Master operation
■ Freescale SPI mode (SPO=1, SPH=1)
■ 1 Mbps bit rate
■ 8 data bits
Assuming the system clock is 20 MHz, the bit rate calculation would be:
SSInClk = SysClk / (CPSDVSR * (1 + SCR))
1x106 = 20x106 / (CPSDVSR * (1 + SCR))
In this case, if CPSDVSR=0x2, SCR must be 0x9.
The configuration sequence would be as follows:
1. Ensure that the SSE bit in the SSICR1 register is clear.
2. Write the SSICR1 register with a value of 0x0000.0000.
3. Write the SSICPSR register with a value of 0x0000.0002.
4. Write the SSICR0 register with a value of 0x0000.09C7.
5. The SSI is then enabled by setting the SSE bit in the SSICR1 register.
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15.5
Register Map
Table 15-2 on page 984 lists the SSI registers. The offset listed is a hexadecimal increment to the
register’s address, relative to that SSI module’s base address:
■
■
■
■
SSI0: 0x4000.8000
SSI1: 0x4000.9000
SSI2: 0x4000.A000
SSI3: 0x4000.B000
Note that the SSI module clock must be enabled before the registers can be programmed (see
page 342). The Rn bit of the PRSSI register must be read as 0x1 before any SSI module registers
are accessed.
Note:
The SSI must be disabled (see the SSE bit in the SSICR1 register) before any of the control
registers are reprogrammed.
Table 15-2. SSI Register Map
Type
Reset
Description
See
page
SSICR0
RW
0x0000.0000
SSI Control 0
986
0x004
SSICR1
RW
0x0000.0000
SSI Control 1
988
0x008
SSIDR
RW
0x0000.0000
SSI Data
990
0x00C
SSISR
RO
0x0000.0003
SSI Status
991
0x010
SSICPSR
RW
0x0000.0000
SSI Clock Prescale
993
0x014
SSIIM
RW
0x0000.0000
SSI Interrupt Mask
994
0x018
SSIRIS
RO
0x0000.0008
SSI Raw Interrupt Status
995
0x01C
SSIMIS
RO
0x0000.0000
SSI Masked Interrupt Status
997
0x020
SSIICR
W1C
0x0000.0000
SSI Interrupt Clear
999
0x024
SSIDMACTL
RW
0x0000.0000
SSI DMA Control
1000
0xFC8
SSICC
RW
0x0000.0000
SSI Clock Configuration
1001
0xFD0
SSIPeriphID4
RO
0x0000.0000
SSI Peripheral Identification 4
1002
0xFD4
SSIPeriphID5
RO
0x0000.0000
SSI Peripheral Identification 5
1003
0xFD8
SSIPeriphID6
RO
0x0000.0000
SSI Peripheral Identification 6
1004
0xFDC
SSIPeriphID7
RO
0x0000.0000
SSI Peripheral Identification 7
1005
0xFE0
SSIPeriphID0
RO
0x0000.0022
SSI Peripheral Identification 0
1006
0xFE4
SSIPeriphID1
RO
0x0000.0000
SSI Peripheral Identification 1
1007
0xFE8
SSIPeriphID2
RO
0x0000.0018
SSI Peripheral Identification 2
1008
0xFEC
SSIPeriphID3
RO
0x0000.0001
SSI Peripheral Identification 3
1009
0xFF0
SSIPCellID0
RO
0x0000.000D
SSI PrimeCell Identification 0
1010
0xFF4
SSIPCellID1
RO
0x0000.00F0
SSI PrimeCell Identification 1
1011
Offset
Name
0x000
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Table 15-2. SSI Register Map (continued)
Offset
Name
0xFF8
0xFFC
15.6
Description
See
page
0x0000.0005
SSI PrimeCell Identification 2
1012
0x0000.00B1
SSI PrimeCell Identification 3
1013
Type
Reset
SSIPCellID2
RO
SSIPCellID3
RO
Register Descriptions
The remainder of this section lists and describes the SSI registers, in numerical order by address
offset.
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Register 1: SSI Control 0 (SSICR0), offset 0x000
The SSICR0 register contains bit fields that control various functions within the SSI module.
Functionality such as protocol mode, clock rate, and data size are configured in this register.
SSI Control 0 (SSICR0)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
SSI2 base: 0x4000.A000
SSI3 base: 0x4000.B000
Offset 0x000
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
5
4
3
2
1
0
RW
0
RW
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
15
14
13
12
RO
0
RO
0
RO
0
RO
0
11
10
9
8
SCR
Type
Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bit/Field
Name
Type
Reset
31:16
reserved
RO
0x0000
15:8
SCR
RW
0x00
RW
0
RO
0
7
6
SPH
SPO
RW
0
RW
0
FRF
RW
0
DSS
RW
0
RW
0
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SSI Serial Clock Rate
This bit field is used to generate the transmit and receive bit rate of the
SSI. The bit rate is:
BR=SysClk/(CPSDVSR * (1 + SCR))
where CPSDVSR is an even value from 2-254 programmed in the
SSICPSR register, and SCR is a value from 0-255.
7
SPH
RW
0
SSI Serial Clock Phase
This bit is only applicable to the Freescale SPI Format.
The SPH control bit selects the clock edge that captures data and allows
it to change state. This bit has the most impact on the first bit transmitted
by either allowing or not allowing a clock transition before the first data
capture edge.
Value Description
6
SPO
RW
0
0
Data is captured on the first clock edge transition.
1
Data is captured on the second clock edge transition.
SSI Serial Clock Polarity
Value Description
0
A steady state Low value is placed on the SSInClk pin.
1
A steady state High value is placed on the SSInClk pin when
data is not being transferred.
Note:
If this bit is set, then software must also configure the
GPIO port pin corresponding to the SSInClk signal
as a pull-up in the GPIO Pull-Up Select (GPIOPUR)
register.
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Bit/Field
Name
Type
Reset
5:4
FRF
RW
0x0
Description
SSI Frame Format Select
Value Frame Format
3:0
DSS
RW
0x0
0x0
Freescale SPI Frame Format
0x1
Texas Instruments Synchronous Serial Frame Format
0x2
MICROWIRE Frame Format
0x3
Reserved
SSI Data Size Select
Value
Data Size
0x0-0x2 Reserved
0x3
4-bit data
0x4
5-bit data
0x5
6-bit data
0x6
7-bit data
0x7
8-bit data
0x8
9-bit data
0x9
10-bit data
0xA
11-bit data
0xB
12-bit data
0xC
13-bit data
0xD
14-bit data
0xE
15-bit data
0xF
16-bit data
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Register 2: SSI Control 1 (SSICR1), offset 0x004
The SSICR1 register contains bit fields that control various functions within the SSI module. Master
and slave mode functionality is controlled by this register.
SSI Control 1 (SSICR1)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
SSI2 base: 0x4000.A000
SSI3 base: 0x4000.B000
Offset 0x004
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
10
9
8
7
6
5
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:5
reserved
RO
0x0000.0
4
EOT
RW
0
RO
0
RO
0
RO
0
RO
0
4
3
2
1
0
EOT
reserved
MS
SSE
LBM
RW
0
RO
0
RW
0
RW
0
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
End of Transmission
This bit is only valid for Master mode devices and operations (MS = 0x0).
Value Description
0
The TXRIS interrupt indicates that the transmit FIFO is half full
or less.
1
The End of Transmit interrupt mode for the TXRIS interrupt is
enabled.
Note:
In Freescale SPI mode only, a condition can be created where
an EOT interrupt is generated for every byte transferred even
if the FIFO is full. If the EOT bit has been set to 0 in an
integrated slave SSI and the µDMA has been configured to
transfer data from this SSI to a Master SSI on the device using
external loopback, an EOT interrupt is generated by the SSI
slave for every byte even if the FIFO is full.
3
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2
MS
RW
0
SSI Master/Slave Select
This bit selects Master or Slave mode and can be modified only when
the SSI is disabled (SSE=0).
Value Description
0
The SSI is configured as a master.
1
The SSI is configured as a slave.
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Bit/Field
Name
Type
Reset
1
SSE
RW
0
Description
SSI Synchronous Serial Port Enable
Value Description
0
SSI operation is disabled.
1
SSI operation is enabled.
Note:
0
LBM
RW
0
This bit must be cleared before any control registers
are reprogrammed.
SSI Loopback Mode
Value Description
0
Normal serial port operation enabled.
1
Output of the transmit serial shift register is connected internally
to the input of the receive serial shift register.
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Register 3: SSI Data (SSIDR), offset 0x008
Important: This register is read-sensitive. See the register description for details.
The SSIDR register is 16-bits wide. When the SSIDR register is read, the entry in the receive FIFO
that is pointed to by the current FIFO read pointer is accessed. When a data value is removed by
the SSI receive logic from the incoming data frame, it is placed into the entry in the receive FIFO
pointed to by the current FIFO write pointer.
When the SSIDR register is written to, the entry in the transmit FIFO that is pointed to by the write
pointer is written to. Data values are removed from the transmit FIFO one value at a time by the
transmit logic. Each data value is loaded into the transmit serial shifter, then serially shifted out onto
the SSInTx pin at the programmed bit rate.
When a data size of less than 16 bits is selected, the user must right-justify data written to the
transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is
automatically right-justified in the receive buffer.
When the SSI is programmed for MICROWIRE frame format, the default size for transmit data is
eight bits (the most significant byte is ignored). The receive data size is controlled by the programmer.
The transmit FIFO and the receive FIFO are not cleared even when the SSE bit in the SSICR1
register is cleared, allowing the software to fill the transmit FIFO before enabling the SSI.
SSI Data (SSIDR)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
SSI2 base: 0x4000.A000
SSI3 base: 0x4000.B000
Offset 0x008
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
DATA
Type
Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bit/Field
Name
Type
Reset
Description
31:16
reserved
RO
0x0000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:0
DATA
RW
0x0000
SSI Receive/Transmit Data
A read operation reads the receive FIFO. A write operation writes the
transmit FIFO.
Software must right-justify data when the SSI is programmed for a data
size that is less than 16 bits. Unused bits at the top are ignored by the
transmit logic. The receive logic automatically right-justifies the data.
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Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Register 4: SSI Status (SSISR), offset 0x00C
The SSISR register contains bits that indicate the FIFO fill status and the SSI busy status.
SSI Status (SSISR)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
SSI2 base: 0x4000.A000
SSI3 base: 0x4000.B000
Offset 0x00C
Type RO, reset 0x0000.0003
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
10
9
8
7
6
5
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:5
reserved
RO
0x0000.00
4
BSY
RO
0
RO
0
RO
0
RO
0
RO
0
4
3
2
1
0
BSY
RFF
RNE
TNF
TFE
RO
0
RO
0
RO
0
RO
1
RO
1
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SSI Busy Bit
Value Description
3
RFF
RO
0
0
The SSI is idle.
1
The SSI is currently transmitting and/or receiving a frame, or
the transmit FIFO is not empty.
SSI Receive FIFO Full
Value Description
2
RNE
RO
0
0
The receive FIFO is not full.
1
The receive FIFO is full.
SSI Receive FIFO Not Empty
Value Description
1
TNF
RO
1
0
The receive FIFO is empty.
1
The receive FIFO is not empty.
SSI Transmit FIFO Not Full
Value Description
0
The transmit FIFO is full.
1
The transmit FIFO is not full.
June 12, 2014
991
Texas Instruments-Production Data
Synchronous Serial Interface (SSI)
Bit/Field
Name
Type
Reset
0
TFE
RO
1
Description
SSI Transmit FIFO Empty
Value Description
0
The transmit FIFO is not empty.
1
The transmit FIFO is empty.
992
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Register 5: SSI Clock Prescale (SSICPSR), offset 0x010
The SSICPSR register specifies the division factor which is used to derive the SSInClk from the
system clock. The clock is further divided by a value from 1 to 256, which is 1 + SCR. SCR is
programmed in the SSICR0 register. The frequency of the SSInClk is defined by:
SSInClk = SysClk / (CPSDVSR * (1 + SCR))
The value programmed into this register must be an even number between 2 and 254. The
least-significant bit of the programmed number is hard-coded to zero. If an odd number is written
to this register, data read back from this register has the least-significant bit as zero.
SSI Clock Prescale (SSICPSR)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
SSI2 base: 0x4000.A000
SSI3 base: 0x4000.B000
Offset 0x010
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
reserved
Type
Reset
CPSDVSR
RO
0
RW
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
CPSDVSR
RW
0x00
SSI Clock Prescale Divisor
This value must be an even number from 2 to 254, depending on the
frequency of SSInClk. The LSB always returns 0 on reads.
June 12, 2014
993
Texas Instruments-Production Data
Synchronous Serial Interface (SSI)
Register 6: SSI Interrupt Mask (SSIIM), offset 0x014
The SSIIM register is the interrupt mask set or clear register. It is a read/write register and all bits
are cleared on reset.
On a read, this register gives the current value of the mask on the corresponding interrupt. Setting
a bit clears the mask, enabling the interrupt to be sent to the interrupt controller. Clearing a bit sets
the corresponding mask, preventing the interrupt from being signaled to the controller.
SSI Interrupt Mask (SSIIM)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
SSI2 base: 0x4000.A000
SSI3 base: 0x4000.B000
Offset 0x014
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
TXIM
RXIM
RTIM
RORIM
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
Description
31:4
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
TXIM
RW
0
SSI Transmit FIFO Interrupt Mask
Value Description
2
RXIM
RW
0
0
The transmit FIFO interrupt is masked.
1
The transmit FIFO interrupt is not masked.
SSI Receive FIFO Interrupt Mask
Value Description
1
RTIM
RW
0
0
The receive FIFO interrupt is masked.
1
The receive FIFO interrupt is not masked.
SSI Receive Time-Out Interrupt Mask
Value Description
0
RORIM
RW
0
0
The receive FIFO time-out interrupt is masked.
1
The receive FIFO time-out interrupt is not masked.
SSI Receive Overrun Interrupt Mask
Value Description
0
The receive FIFO overrun interrupt is masked.
1
The receive FIFO overrun interrupt is not masked.
994
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018
The SSIRIS register is the raw interrupt status register. On a read, this register gives the current
raw status value of the corresponding interrupt prior to masking. A write has no effect.
SSI Raw Interrupt Status (SSIRIS)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
SSI2 base: 0x4000.A000
SSI3 base: 0x4000.B000
Offset 0x018
Type RO, reset 0x0000.0008
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
3
2
1
0
TXRIS
RXRIS
RTRIS
RORRIS
RO
1
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:4
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
TXRIS
RO
1
SSI Transmit FIFO Raw Interrupt Status
Value Description
0
No interrupt.
1
If the EOT bit in the SSICR1 register is clear, the transmit FIFO
is half empty or less.
If the EOT bit is set, the transmit FIFO is empty, and the last bit
has been transmitted out of the serializer.
This bit is cleared when the transmit FIFO is more than half full (if the
EOT bit is clear) or when it has any data in it (if the EOT bit is set).
2
RXRIS
RO
0
SSI Receive FIFO Raw Interrupt Status
Value Description
0
No interrupt.
1
The receive FIFO is half full or more.
This bit is cleared when the receive FIFO is less than half full.
1
RTRIS
RO
0
SSI Receive Time-Out Raw Interrupt Status
Value Description
0
No interrupt.
1
The receive time-out has occurred.
This bit is cleared when a 1 is written to the RTIC bit in the SSI Interrupt
Clear (SSIICR) register.
June 12, 2014
995
Texas Instruments-Production Data
Synchronous Serial Interface (SSI)
Bit/Field
Name
Type
Reset
0
RORRIS
RO
0
Description
SSI Receive Overrun Raw Interrupt Status
Value Description
0
No interrupt.
1
The receive FIFO has overflowed
This bit is cleared when a 1 is written to the RORIC bit in the SSI
Interrupt Clear (SSIICR) register.
996
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C
The SSIMIS register is the masked interrupt status register. On a read, this register gives the current
masked status value of the corresponding interrupt. A write has no effect.
SSI Masked Interrupt Status (SSIMIS)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
SSI2 base: 0x4000.A000
SSI3 base: 0x4000.B000
Offset 0x01C
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
3
2
1
0
TXMIS
RXMIS
RTMIS
RORMIS
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:4
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
TXMIS
RO
0
SSI Transmit FIFO Masked Interrupt Status
Value Description
0
An interrupt has not occurred or is masked.
1
An unmasked interrupt was signaled due to the transmit FIFO
being half empty or less (if the EOT bit is clear) or due to the
transmission of the last data bit (if the EOT bit is set).
This bit is cleared when the transmit FIFO is more than half empty (if
the EOT bit is clear) or when it has any data in it (if the EOT bit is set).
2
RXMIS
RO
0
SSI Receive FIFO Masked Interrupt Status
Value Description
0
An interrupt has not occurred or is masked.
1
An unmasked interrupt was signaled due to the receive FIFO
being half full or more.
This bit is cleared when the receive FIFO is less than half full.
1
RTMIS
RO
0
SSI Receive Time-Out Masked Interrupt Status
Value Description
0
An interrupt has not occurred or is masked.
1
An unmasked interrupt was signaled due to the receive time
out.
This bit is cleared when a 1 is written to the RTIC bit in the SSI Interrupt
Clear (SSIICR) register.
June 12, 2014
997
Texas Instruments-Production Data
Synchronous Serial Interface (SSI)
Bit/Field
Name
Type
Reset
0
RORMIS
RO
0
Description
SSI Receive Overrun Masked Interrupt Status
Value Description
0
An interrupt has not occurred or is masked.
1
An unmasked interrupt was signaled due to the receive FIFO
overflowing.
This bit is cleared when a 1 is written to the RORIC bit in the SSI
Interrupt Clear (SSIICR) register.
998
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Register 9: SSI Interrupt Clear (SSIICR), offset 0x020
The SSIICR register is the interrupt clear register. On a write of 1, the corresponding interrupt is
cleared. A write of 0 has no effect.
SSI Interrupt Clear (SSIICR)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
SSI2 base: 0x4000.A000
SSI3 base: 0x4000.B000
Offset 0x020
Type W1C, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
1
0
RTIC
RORIC
W1C
0
W1C
0
Bit/Field
Name
Type
Reset
Description
31:2
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1
RTIC
W1C
0
SSI Receive Time-Out Interrupt Clear
Writing a 1 to this bit clears the RTRIS bit in the SSIRIS register and
the RTMIS bit in the SSIMIS register.
0
RORIC
W1C
0
SSI Receive Overrun Interrupt Clear
Writing a 1 to this bit clears the RORRIS bit in the SSIRIS register and
the RORMIS bit in the SSIMIS register.
June 12, 2014
999
Texas Instruments-Production Data
Synchronous Serial Interface (SSI)
Register 10: SSI DMA Control (SSIDMACTL), offset 0x024
The SSIDMACTL register is the µDMA control register.
SSI DMA Control (SSIDMACTL)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
SSI2 base: 0x4000.A000
SSI3 base: 0x4000.B000
Offset 0x024
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
1
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:2
reserved
RO
0x0000.000
1
TXDMAE
RW
0
TXDMAE RXDMAE
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Transmit DMA Enable
Value Description
0
RXDMAE
RW
0
0
µDMA for the transmit FIFO is disabled.
1
µDMA for the transmit FIFO is enabled.
Receive DMA Enable
Value Description
0
µDMA for the receive FIFO is disabled.
1
µDMA for the receive FIFO is enabled.
1000
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Register 11: SSI Clock Configuration (SSICC), offset 0xFC8
The SSICC register controls the baud clock source for the SSI module.
Note:
If the PIOSC is used for the SSI baud clock, the system clock frequency must be at least
16 MHz in Run mode.
SSI Clock Configuration (SSICC)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
SSI2 base: 0x4000.A000
SSI3 base: 0x4000.B000
Offset 0xFC8
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
reserved
Type
Reset
CS
Bit/Field
Name
Type
Reset
31:4
reserved
RO
0x0000.000
3:0
CS
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SSI Baud Clock Source
The following table specifies the source that generates for the SSI baud
clock:
Value
Description
0x0
System clock (based on clock source and divisor factor)
0x1-0x4
reserved
0x5
PIOSC
0x6 - 0xF Reserved
June 12, 2014
1001
Texas Instruments-Production Data
Synchronous Serial Interface (SSI)
Register 12: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 4 (SSIPeriphID4)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
SSI2 base: 0x4000.A000
SSI3 base: 0x4000.B000
Offset 0xFD0
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
PID4
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
PID4
RO
0x00
RO
0
RO
0
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SSI Peripheral ID Register [7:0]
Can be used by software to identify the presence of this peripheral.
1002
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Register 13: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 5 (SSIPeriphID5)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
SSI2 base: 0x4000.A000
SSI3 base: 0x4000.B000
Offset 0xFD4
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
PID5
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
PID5
RO
0x00
RO
0
RO
0
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SSI Peripheral ID Register [15:8]
Can be used by software to identify the presence of this peripheral.
June 12, 2014
1003
Texas Instruments-Production Data
Synchronous Serial Interface (SSI)
Register 14: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 6 (SSIPeriphID6)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
SSI2 base: 0x4000.A000
SSI3 base: 0x4000.B000
Offset 0xFD8
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
PID6
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
PID6
RO
0x00
RO
0
RO
0
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SSI Peripheral ID Register [23:16]
Can be used by software to identify the presence of this peripheral.
1004
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Register 15: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 7 (SSIPeriphID7)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
SSI2 base: 0x4000.A000
SSI3 base: 0x4000.B000
Offset 0xFDC
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
PID7
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
PID7
RO
0x00
RO
0
RO
0
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SSI Peripheral ID Register [31:24]
Can be used by software to identify the presence of this peripheral.
June 12, 2014
1005
Texas Instruments-Production Data
Synchronous Serial Interface (SSI)
Register 16: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 0 (SSIPeriphID0)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
SSI2 base: 0x4000.A000
SSI3 base: 0x4000.B000
Offset 0xFE0
Type RO, reset 0x0000.0022
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
0
RO
1
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
PID0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
PID0
RO
0x22
RO
0
RO
0
RO
0
RO
1
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SSI Peripheral ID Register [7:0]
Can be used by software to identify the presence of this peripheral.
1006
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Register 17: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 1 (SSIPeriphID1)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
SSI2 base: 0x4000.A000
SSI3 base: 0x4000.B000
Offset 0xFE4
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
PID1
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
PID1
RO
0x00
RO
0
RO
0
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SSI Peripheral ID Register [15:8]
Can be used by software to identify the presence of this peripheral.
June 12, 2014
1007
Texas Instruments-Production Data
Synchronous Serial Interface (SSI)
Register 18: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 2 (SSIPeriphID2)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
SSI2 base: 0x4000.A000
SSI3 base: 0x4000.B000
Offset 0xFE8
Type RO, reset 0x0000.0018
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
1
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
PID2
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
PID2
RO
0x18
RO
0
RO
0
RO
0
RO
0
RO
1
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SSI Peripheral ID Register [23:16]
Can be used by software to identify the presence of this peripheral.
1008
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Register 19: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 3 (SSIPeriphID3)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
SSI2 base: 0x4000.A000
SSI3 base: 0x4000.B000
Offset 0xFEC
Type RO, reset 0x0000.0001
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
0
RO
0
RO
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
PID3
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
PID3
RO
0x01
RO
0
RO
0
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SSI Peripheral ID Register [31:24]
Can be used by software to identify the presence of this peripheral.
June 12, 2014
1009
Texas Instruments-Production Data
Synchronous Serial Interface (SSI)
Register 20: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0
The SSIPCellIDn registers are hard-coded, and the fields within the register determine the reset
value.
SSI PrimeCell Identification 0 (SSIPCellID0)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
SSI2 base: 0x4000.A000
SSI3 base: 0x4000.B000
Offset 0xFF0
Type RO, reset 0x0000.000D
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
1
RO
1
RO
0
RO
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
CID0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
CID0
RO
0x0D
RO
0
RO
0
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SSI PrimeCell ID Register [7:0]
Provides software a standard cross-peripheral identification system.
1010
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Register 21: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4
The SSIPCellIDn registers are hard-coded, and the fields within the register determine the reset
value.
SSI PrimeCell Identification 1 (SSIPCellID1)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
SSI2 base: 0x4000.A000
SSI3 base: 0x4000.B000
Offset 0xFF4
Type RO, reset 0x0000.00F0
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
CID1
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
CID1
RO
0xF0
RO
0
RO
1
RO
1
RO
1
RO
1
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SSI PrimeCell ID Register [15:8]
Provides software a standard cross-peripheral identification system.
June 12, 2014
1011
Texas Instruments-Production Data
Synchronous Serial Interface (SSI)
Register 22: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8
The SSIPCellIDn registers are hard-coded, and the fields within the register determine the reset
value.
SSI PrimeCell Identification 2 (SSIPCellID2)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
SSI2 base: 0x4000.A000
SSI3 base: 0x4000.B000
Offset 0xFF8
Type RO, reset 0x0000.0005
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
1
RO
0
RO
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
CID2
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
CID2
RO
0x05
RO
0
RO
0
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SSI PrimeCell ID Register [23:16]
Provides software a standard cross-peripheral identification system.
1012
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Register 23: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC
The SSIPCellIDn registers are hard-coded, and the fields within the register determine the reset
value.
SSI PrimeCell Identification 3 (SSIPCellID3)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
SSI2 base: 0x4000.A000
SSI3 base: 0x4000.B000
Offset 0xFFC
Type RO, reset 0x0000.00B1
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
0
RO
0
RO
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
CID3
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
CID3
RO
0xB1
RO
0
RO
1
RO
0
RO
1
RO
1
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SSI PrimeCell ID Register [31:24]
Provides software a standard cross-peripheral identification system.
June 12, 2014
1013
Texas Instruments-Production Data
Inter-Integrated Circuit (I2C) Interface
16
Inter-Integrated Circuit (I2C) Interface
The Inter-Integrated Circuit (I2C) bus provides bi-directional data transfer through a two-wire design
(a serial data line SDA and a serial clock line SCL), and interfaces to external I2C devices such as
serial memory (RAMs and ROMs), networking devices, LCDs, tone generators, and so on. The I2C
bus may also be used for system testing and diagnostic purposes in product development and
manufacturing. The TM4C123BH6PGE microcontroller includes providing the ability to communicate
(both transmit and receive) with other I2C devices on the bus.
The TM4C123BH6PGE controller includes I2C modules with the following features:
■ Devices on the I2C bus can be designated as either a master or a slave
– Supports both transmitting and receiving data as either a master or a slave
– Supports simultaneous master and slave operation
■ Four I2C modes
– Master transmit
– Master receive
– Slave transmit
– Slave receive
■ Four transmission speeds:
– Standard (100 Kbps)
– Fast-mode (400 Kbps)
– Fast-mode plus (1 Mbps)
– High-speed mode (3.33 Mbps)
■ Clock low timeout interrupt
■ Dual slave address capability
■ Glitch suppression
■ Master and slave interrupt generation
– Master generates interrupts when a transmit or receive operation completes (or aborts due
to an error)
– Slave generates interrupts when data has been transferred or requested by a master or when
a START or STOP condition is detected
■ Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing
mode
1014
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
16.1
Block Diagram
Figure 16-1. I2C Block Diagram
I2CSCL
I2C Control
Interrupt
I2CMSA
I2CSOAR
I2CMCS
I2CSCSR
I2CMDR
I2CSDR
I2CMTPR
I2CSIMR
I2CMIMR
I2CSRIS
I2CMRIS
I2CSMIS
I2CMMIS
I2CSICR
I2CMICR
I2CPP
I2C Master Core
I2CSDA
I2CSCL
2
I C I/O Select
I2CSDA
I2CSCL
I2C Slave Core
I2CSDA
I2CMCR
16.2
Signal Description
The following table lists the external signals of the I2C interface and describes the function of each.
The I2C interface signals are alternate functions for some GPIO signals and default to be GPIO
signals at reset, with the exception of the I2C0SCL and I2CSDA pins which default to the I2C
function. The column in the table below titled "Pin Mux/Pin Assignment" lists the possible GPIO pin
placements for the I2C signals. The AFSEL bit in the GPIO Alternate Function Select (GPIOAFSEL)
register (page 676) should be set to choose the I2C function. The number in parentheses is the
encoding that must be programmed into the PMCn field in the GPIO Port Control (GPIOPCTL)
register (page 695) to assign the I2C signal to the specified GPIO port pin. Note that the I2CSDA pin
should be set to open drain using the GPIO Open Drain Select (GPIOODR) register. For more
information on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 647.
Table 16-1. I2C Signals (144LQFP)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
I2C0SCL
99
PB2 (3)
I/O
OD
I2C module 0 clock. Note that this signal has an
active pull-up. The corresponding port pin should
not be configured as open drain.
I2C0SDA
100
PB3 (3)
I/O
OD
I2C module 0 data.
I2C1SCL
45
51
PA6 (3)
PG4 (3)
I/O
OD
I2C module 1 clock. Note that this signal has an
active pull-up. The corresponding port pin should
not be configured as open drain.
I2C1SDA
46
50
PA7 (3)
PG5 (3)
I/O
OD
I2C module 1 data.
I2C2SCL
59
139
PF6 (3)
PE4 (3)
I/O
OD
I2C module 2 clock. Note that this signal has an
active pull-up. The corresponding port pin should
not be configured as open drain.
I2C2SDA
58
140
PF7 (3)
PE5 (3)
I/O
OD
I2C module 2 data.
I2C3SCL
1
55
PD0 (3)
PG0 (3)
I/O
OD
I2C module 3 clock. Note that this signal has an
active pull-up. The corresponding port pin should
not be configured as open drain.
June 12, 2014
1015
Texas Instruments-Production Data
Inter-Integrated Circuit (I2C) Interface
Table 16-1. I2C Signals (144LQFP) (continued)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
I2C3SDA
2
54
PD1 (3)
PG1 (3)
I/O
OD
I2C module 3 data.
I2C4SCL
53
PG2 (3)
I/O
OD
I2C module 4 clock. Note that this signal has an
active pull-up. The corresponding port pin should
not be configured as open drain.
I2C4SDA
52
PG3 (3)
I/O
OD
I2C module 4 data.
I2C5SCL
48
PG6 (3)
I/O
OD
I2C module 5 clock. Note that this signal has an
active pull-up. The corresponding port pin should
not be configured as open drain.
I2C5SDA
47
PG7 (3)
I/O
OD
I2C module 5 data.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
16.3
Functional Description
Each I2C module is comprised of both master and slave functions and is identified by a unique
address. A master-initiated communication generates the clock signal, SCL. For proper operation,
the SDA pin must be configured as an open-drain signal. Due to the internal circuitry that supports
high-speed operation, the SCL pin must not be configured as an open-drain signal, although the
internal circuitry causes it to act as if it were an open drain signal. Both SDA and SCL signals must
be connected to a positive supply voltage using a pull-up resistor. A typical I2C bus configuration is
shown in Figure 16-2. Refer to the I2C-bus specification and user manual to determine the size of
the pull-ups needed for proper operation.
See “Inter-Integrated Circuit (I2C) Interface” on page 1321 for I2C timing diagrams.
Figure 16-2. I2C Bus Configuration
RPUP
SCL
SDA
I2C Bus
I2CSCL
I2CSDA
Tiva™
Microcontroller
16.3.1
RPUP
SCL
SDA
3rd Party Device
with I2C Interface
SCL
SDA
3rd Party Device
with I2C Interface
I2C Bus Functional Overview
The I2C bus uses only two signals: SDA and SCL, named I2CSDA and I2CSCL on TM4C123BH6PGE
microcontrollers. SDA is the bi-directional serial data line and SCL is the bi-directional serial clock
line. The bus is considered idle when both lines are High.
Every transaction on the I2C bus is nine bits long, consisting of eight data bits and a single
acknowledge bit. The number of bytes per transfer (defined as the time between a valid START
and STOP condition, described in “START and STOP Conditions” on page 1017) is unrestricted, but
each data byte has to be followed by an acknowledge bit, and data must be transferred MSB first.
When a receiver cannot receive another complete byte, it can hold the clock line SCL Low and force
the transmitter into a wait state. The data transfer continues when the receiver releases the clock
SCL.
1016
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
16.3.1.1
START and STOP Conditions
The protocol of the I2C bus defines two states to begin and end a transaction: START and STOP.
A High-to-Low transition on the SDA line while the SCL is High is defined as a START condition,
and a Low-to-High transition on the SDA line while SCL is High is defined as a STOP condition.
The bus is considered busy after a START condition and free after a STOP condition. See Figure
16-3.
Figure 16-3. START and STOP Conditions
SDA
SDA
SCL
SCL
START
condition
STOP
condition
The STOP bit determines if the cycle stops at the end of the data cycle or continues on to a repeated
START condition. To generate a single transmit cycle, the I2C Master Slave Address (I2CMSA)
register is written with the desired address, the R/S bit is cleared, and the Control register is written
with ACK=X (0 or 1), STOP=1, START=1, and RUN=1 to perform the operation and stop. When the
operation is completed (or aborted due an error), the interrupt pin becomes active and the data may
be read from the I2C Master Data (I2CMDR) register. When the I2C module operates in Master
receiver mode, the ACK bit is normally set causing the I2C bus controller to transmit an acknowledge
automatically after each byte. This bit must be cleared when the I2C bus controller requires no further
data to be transmitted from the slave transmitter.
When operating in slave mode, the STARTRIS and STOPRIS bits in the I2C Slave Raw Interrupt
Status (I2CSRIS) register indicate detection of start and stop conditions on the bus and the I2C
Slave Masked Interrupt Status (I2CSMIS) register can be configured to allow STARTRIS and
STOPRIS to be promoted to controller interrupts (when interrupts are enabled).
16.3.1.2
Data Format with 7-Bit Address
Data transfers follow the format shown in Figure 16-4. After the START condition, a slave address
is transmitted. This address is 7-bits long followed by an eighth bit, which is a data direction bit (R/S
bit in the I2CMSA register). If the R/S bit is clear, it indicates a transmit operation (send), and if it
is set, it indicates a request for data (receive). A data transfer is always terminated by a STOP
condition generated by the master, however, a master can initiate communications with another
device on the bus by generating a repeated START condition and addressing another slave without
first generating a STOP condition. Various combinations of receive/transmit formats are then possible
within a single transfer.
Figure 16-4. Complete Data Transfer with a 7-Bit Address
SDA
MSB
SCL
1
Start
2
LSB
R/S
ACK
7
8
9
MSB
1
2
Slave address
7
Data
LSB
ACK
8
9
Stop
The first seven bits of the first byte make up the slave address (see Figure 16-5). The eighth bit
determines the direction of the message. A zero in the R/S position of the first byte means that the
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master transmits (sends) data to the selected slave, and a one in this position means that the master
receives data from the slave.
Figure 16-5. R/S Bit in First Byte
MSB
LSB
R/S
Slave address
16.3.1.3
Data Validity
The data on the SDA line must be stable during the high period of the clock, and the data line can
only change when SCL is Low (see Figure 16-6).
Figure 16-6. Data Validity During Bit Transfer on the I2C Bus
SDA
SCL
16.3.1.4
Data line Change
stable of data
allowed
Acknowledge
All bus transactions have a required acknowledge clock cycle that is generated by the master. During
the acknowledge cycle, the transmitter (which can be the master or slave) releases the SDA line.
To acknowledge the transaction, the receiver must pull down SDA during the acknowledge clock
cycle. The data transmitted out by the receiver during the acknowledge cycle must comply with the
data validity requirements described in “Data Validity” on page 1018.
When a slave receiver does not acknowledge the slave address, SDA must be left High by the slave
so that the master can generate a STOP condition and abort the current transfer. If the master
device is acting as a receiver during a transfer, it is responsible for acknowledging each transfer
made by the slave. Because the master controls the number of bytes in the transfer, it signals the
end of data to the slave transmitter by not generating an acknowledge on the last data byte. The
slave transmitter must then release SDA to allow the master to generate the STOP or a repeated
START condition.
If the slave is required to provide a manual ACK or NACK, the I2C Slave ACK Control
(I2CSACKCTL) register allows the slave to NACK for invalid data or command or ACK for valid
data or command. When this operation is enabled, the MCU slave module I2C clock is pulled low
after the last data bit until this register is written with the indicated response.
16.3.1.5
Repeated Start
The I2C master module has the capability of executing a repeated START (transmit or receive) after
an initial transfer has occurred.
A repeated start sequence for a Master transmit is as follows:
1. When the device is in the idle state, the Master writes the slave address to the I2CMSA register
and configures the R/S bit for the desired transfer type.
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2. Data is written to the I2CMDR register.
3. When the BUSY bit in the I2CMCS register is 0 , the Master writes 0x3 to the I2CMCS register
to initiate a transfer.
4. The Master does not generate a STOP condition but instead writes another slave address to
the I2CMSA register and then writes 0x3 to initiate the repeated START.
A repeated start sequence for a Master receive is similar:
1. When the device is in idle, the Master writes the slave address to the I2CMSA register and
configures the R/S bit for the desired transfer type.
2. The master reads data from the I2CMDR register.
3. When the BUSY bit in the I2CMCS register is 0 , the Master writes 0x3 to the I2CMCS register
to initiate a transfer.
4. The Master does not generate a STOP condition but instead writes another slave address to
the I2CMSA register and then writes 0x3 to initiate the repeated START.
For more information on repeated START, refer to Figure 16-12 on page 1029 and Figure
16-13 on page 1030.
16.3.1.6
Clock Low Timeout (CLTO)
The I2C slave can extend the transaction by pulling the clock low periodically to create a slow bit
transfer rate. The I2C module has a 12-bit programmable counter that is used to track how long the
clock has been held low. The upper 8 bits of the count value are software programmable through
the I2C Master Clock Low Timeout Count (I2CMCLKOCNT) register. The lower four bits are not
user visible and are 0x0. The CNTL value programmed in the I2CMCLKOCNT register has to be
greater than 0x01. The application can program the eight most significant bits of the counter to
reflect the acceptable cumulative low period in transaction. The count is loaded at the START
condition and counts down on each falling edge of the internal bus clock of the Master. Note that
the internal bus clock generated for this counter keeps running at the programmed I2C speed even
if SCL is held low on the bus. Upon reaching terminal count, the master state machine forces ABORT
on the bus by issuing a STOP condition at the instance of SCL and SDA release.
As an example, if an I2C module was operating at 100 kHz speed, programming the I2CMCLKOCNT
register to 0xDA would translate to the value 0xDA0 since the lower four bits are set to 0x0. This
would translate to a decimal value of 3488 clocks or a cumulative clock low period of 34.88 ms at
100 kHz.
The CLKRIS bit in the I2C Master Raw Interrupt Status (I2CMRIS) register is set when the clock
timeout period is reached, allowing the master to start corrective action to resolve the remote slave
state. In addition, the CLKTO bit in the I2C Master Control/Status (I2CMCS) register is set; this bit
is cleared when a STOP condition is sent or during the I2C master reset. The status of the raw SDA
and SCL signals are readable by software through the SDA and SCL bits in the I2C Master Bus
Monitor (I2CMBMON) register to help determine the state of the remote slave.
In the event of a CLTO condition, application software must choose how it intends to attempt bus
recovery. Most applications may attempt to manually toggle the I2C pins to force the slave to let go
of the clock signal (a common solution is to attempt to force a STOP on the bus). If a CLTO is
detected before the end of a burst transfer, and the bus is successfully recovered by the master,
the master hardware attempts to finish the pending burst operation. Depending on the state of the
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slave after bus recovery, the actual behavior on the bus varies. If the slave resumes in a state where
it can acknowledge the master (essentially, where it was before the bus hang), it continues where
it left off. However, if the slave resumes in a reset state (or if a forced STOP by the master causes
the slave to enter the idle state), it may ignore the master's attempt to complete the burst operation
and NAK the first data byte that the master sends or requests.
Since the behavior of slaves cannot always be predicted, it is suggested that the application software
always write the STOP bit in the I2C Master Configuration (I2CMCR) register during the CLTO
interrupt service routine. This limits the amount of data the master attempts to send or receive upon
bus recovery to a single byte, and after the single byte is on the wire, the master issues a STOP.
An alternative solution is to have the application software reset the I2C peripheral before attempting
to manually recover the bus. This solution allows the I2C master hardware to be returned to a known
good (and idle) state before attempting to recover a stuck bus and prevents any unwanted data
from appearing on the wire.
Note:
16.3.1.7
The Master Clock Low Timeout counter counts for the entire time SCL is held Low
continuously. If SCL is deasserted at any point, the Master Clock Low Timeout Counter is
reloaded with the value in the I2CMCLKOCNT register and begins counting down from this
value.
Dual Address
The I2C interface supports dual address capability for the slave. The additional programmable
address is provided and can be matched if enabled. In legacy mode with dual address disabled,
the I2C slave provides an ACK on the bus if the address matches the OAR field in the I2CSOAR
register. In dual address mode, the I2C slave provides an ACK on the bus if either the OAR field in
the I2CSOAR register or the OAR2 field in the I2CSOAR2 register is matched. The enable for dual
address is programmable through the OAR2EN bit in the I2CSOAR2 register and there is no disable
on the legacy address.
The OAR2SEL bit in the I2CSCSR register indicates if the address that was ACKed is the alternate
address or not. When this bit is clear, it indicates either legacy operation or no address match.
16.3.1.8
Arbitration
A master may start a transfer only if the bus is idle. It's possible for two or more masters to generate
a START condition within minimum hold time of the START condition. In these situations, an
arbitration scheme takes place on the SDA line, while SCL is High. During arbitration, the first of
the competing master devices to place a 1 (High) on SDA, while another master transmits a 0 (Low),
switches off its data output stage and retires until the bus is idle again.
Arbitration can take place over several bits. Its first stage is a comparison of address bits, and if
both masters are trying to address the same device, arbitration continues on to the comparison of
data bits.
16.3.1.9
Glitch Suppression in Multi-Master Configuration
When a multi-master configuration is being used, the GFE bit in the I2C Master Configuration
(I2CMCR) register can be set to enable glitch suppression on the SCL and SDA lines and assure
proper signal values. The filter can be programmed to different filter widths using the GFPW bit in
the I2C Master Configuration 2 (I2CMCR2) register. The glitch suppression value is in terms of
buffered system clocks. Note that all signals will be delayed internally when glitch suppression is
nonzero. For example, if GFPW is set to 0x7, 31 clocks should be added onto the calculation for the
expected transaction time.
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16.3.2
Available Speed Modes
The I2C bus can run in Standard mode (100 kbps), Fast mode (400 kbps), Fast mode plus (1 Mbps)
or High-Speed mode (3.33 Mbps). The selected mode should match the speed of the other I2C
devices on the bus.
16.3.2.1
Standard, Fast, and Fast Plus Modes
Standard, Fast, and Fast Plus modes are selected using a value in the I2C Master Timer Period
(I2CMTPR) register that results in an SCL frequency of 100 kbps for Standard mode, 400 kbps for
Fast mode, or 1 Mbps for Fast mode plus.
The I2C clock rate is determined by the parameters CLK_PRD, TIMER_PRD, SCL_LP, and SCL_HP
where:
CLK_PRD is the system clock period
SCL_LP is the low phase of SCL (fixed at 6)
SCL_HP is the high phase of SCL (fixed at 4)
TIMER_PRD is the programmed value in the I2CMTPR register (see page 1043). This value is
determined by replacing the known variables in the equation below and solving for TIMER_PRD.
The I2C clock period is calculated as follows:
SCL_PERIOD = 2 × (1 + TIMER_PRD) × (SCL_LP + SCL_HP) × CLK_PRD
For example:
CLK_PRD = 50 ns
TIMER_PRD = 2
SCL_LP=6
SCL_HP=4
yields a SCL frequency of:
1/SCL_PERIOD = 333 Khz
Table 16-2 gives examples of the timer periods that should be used to generate Standard, Fast
mode, and Fast mode plus SCL frequencies based on various system clock frequencies.
Table 16-2. Examples of I2C Master Timer Period Versus Speed Mode
System Clock
Timer Period
Standard Mode
Timer Period
Fast Mode
Timer
Period
Fast Mode
Plus
4 MHz
0x01
100 Kbps
-
-
-
-
6 MHz
0x02
100 Kbps
-
-
-
-
12.5 MHz
0x06
89 Kbps
0x01
312 Kbps
-
-
16.7 MHz
0x08
93 Kbps
0x02
278 Kbps
-
-
20 MHz
0x09
100 Kbps
0x02
333 Kbps
-
-
25 MHz
0x0C
96.2 Kbps
0x03
312 Kbps
-
-
33 MHz
0x10
97.1 Kbps
0x04
330 Kbps
-
-
40 MHz
0x13
100 Kbps
0x04
400 Kbps
0x01
1000 Kbps
50 MHz
0x18
100 Kbps
0x06
357 Kbps
0x02
833 Kbps
80 MHz
0x27
100 Kbps
0x09
400 Kbps
0x03
1000 Kbps
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16.3.2.2
High-Speed Mode
The TM4C123BH6PGE I2C peripheral has support for High-speed operation as both a master and
slave. High-Speed mode is configured by setting the HS bit in the I2C Master Control/Status
(I2CMCS) register. High-Speed mode transmits data at a high bit rate with a 66.6%/33.3% duty
cycle, but communication and arbitration are done at Standard, Fast mode, or Fast-mode plus
speed, depending on which is selected by the user. When the HS bit in the I2CMCS register is set,
current mode pull-ups are enabled.
The clock period can be selected using the equation below, but in this case, SCL_LP=2 and
SCL_HP=1.
SCL_PERIOD = 2 × (1 + TIMER_PRD) × (SCL_LP + SCL_HP) × CLK_PRD
So for example:
CLK_PRD = 25 ns
TIMER_PRD = 1
SCL_LP=2
SCL_HP=1
yields a SCL frequency of:
1/T = 3.33 Mhz
Table 16-3 on page 1022 gives examples of timer period and system clock in High-Speed mode. Note
that the HS bit in the I2CMTPR register needs to be set for the TPR value to be used in High-Speed
mode.
Table 16-3. Examples of I2C Master Timer Period in High-Speed Mode
System Clock
Timer Period
Transmission Mode
40 MHz
0x01
3.33 Mbps
50 MHz
0x02
2.77 Mbps
80 MHz
0x03
3.33 Mbps
When operating as a master, the protocol is shown in Figure 16-7. The master is responsible for
sending a master code byte in either Standard (100 Kbps) or Fast-mode (400 Kbps) before it begins
transferring in High-speed mode. The master code byte must contain data in the form of 0000.1XXX
and is used to tell the slave devices to prepare for a High-speed transfer. The master code byte
should never be acknowledged by a slave since it is only used to indicate that the upcoming data
is going to be transferred at a higher data rate. To send the master code byte, software should place
the value of the master code byte into the I2CMSA register and write the I2CMCS register with a
value of 0x13. This places the I2C master peripheral in High-speed mode, and all subsequent
transfers (until STOP) are carried out at High-speed data rate using the normal I2CMCS command
bits, without setting the HS bit in the I2CMCS register. Again, setting the HS bit in the I2CMCS register
is only necessary during the master code byte.
When operating as a High-speed slave, there is no additional software required.
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Figure 16-7. High-Speed Data Format
R/W
SDA
Device-Specific
NAK
Address
Data
SCL
Standard (100 KHz) or Fast Mode (400 KHz)
High Speed
(3.3 Mbps)
Note:
16.3.3
High-Speed mode is 3.4 Mbps, provided correct system clock frequency is set and there is
appropriate pull strength on SCL and SDA lines.
Interrupts
The I2C can generate interrupts when the following conditions are observed:
■ Master transaction completed
■ Master arbitration lost
■ Master transaction error
■ Master bus timeout
■ Slave transaction received
■ Slave transaction requested
■ Stop condition on bus detected
■ Start condition on bus detected
The I2C master and I2C slave modules have separate interrupt signals. While both modules can
generate interrupts for multiple conditions, only a single interrupt signal is sent to the interrupt
controller.
16.3.3.1
I2C Master Interrupts
The I2C master module generates an interrupt when a transaction completes (either transmit or
receive), when arbitration is lost, or when an error occurs during a transaction. To enable the I2C
master interrupt, software must set the IM bit in the I2C Master Interrupt Mask (I2CMIMR) register.
When an interrupt condition is met, software must check the ERROR and ARBLST bits in the I2C
Master Control/Status (I2CMCS) register to verify that an error didn't occur during the last transaction
and to ensure that arbitration has not been lost. An error condition is asserted if the last transaction
wasn't acknowledged by the slave. If an error is not detected and the master has not lost arbitration,
the application can proceed with the transfer. The interrupt is cleared by writing a 1 to the IC bit in
the I2C Master Interrupt Clear (I2CMICR) register.
If the application doesn't require the use of interrupts, the raw interrupt status is always visible via
the I2C Master Raw Interrupt Status (I2CMRIS) register.
16.3.3.2
I2C Slave Interrupts
The slave module can generate an interrupt when data has been received or requested. This interrupt
is enabled by setting the DATAIM bit in the I2C Slave Interrupt Mask (I2CSIMR) register. Software
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determines whether the module should write (transmit) or read (receive) data from the I2C Slave
Data (I2CSDR) register, by checking the RREQ and TREQ bits of the I2C Slave Control/Status
(I2CSCSR) register. If the slave module is in receive mode and the first byte of a transfer is received,
the FBR bit is set along with the RREQ bit. The interrupt is cleared by setting the DATAIC bit in the
I2C Slave Interrupt Clear (I2CSICR) register.
In addition, the slave module can generate an interrupt when a start and stop condition is detected.
These interrupts are enabled by setting the STARTIM and STOPIM bits of the I2C Slave Interrupt
Mask (I2CSIMR) register and cleared by writing a 1 to the STOPIC and STARTIC bits of the I2C
Slave Interrupt Clear (I2CSICR) register.
If the application doesn't require the use of interrupts, the raw interrupt status is always visible via
the I2C Slave Raw Interrupt Status (I2CSRIS) register.
16.3.4
Loopback Operation
The I2C modules can be placed into an internal loopback mode for diagnostic or debug work by
setting the LPBK bit in the I2C Master Configuration (I2CMCR) register. In loopback mode, the
SDA and SCL signals from the master and are tied to the SDA and SCL signals of the slave module
to allow internal testing of the device without having to go through I/O.
16.3.5
Command Sequence Flow Charts
This section details the steps required to perform the various I2C transfer types in both master and
slave mode.
16.3.5.1
I2C Master Command Sequences
The figures that follow show the command sequences available for the I2C master.
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Figure 16-8. Master Single TRANSMIT
Idle
Write Slave
Address to
I2CMSA
Sequence
may be
omitted in a
Single Master
system
Write data to
I2CMDR
Read I2CMCS
NO
BUSBSY bit=0?
YES
Write ---0-111
to I2CMCS
Read I2CMCS
NO
BUSY bit=0?
YES
Error Service
NO
ERROR bit=0?
YES
Idle
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Figure 16-9. Master Single RECEIVE
Idle
Write Slave
Address to
I2CMSA
Sequence may be
omitted in a Single
Master system
Read I2CMCS
NO
BUSBSY bit=0?
YES
Write ---00111
to I2CMCS
Read I2CMCS
NO
BUSY bit=0?
YES
Error Service
NO
ERROR bit=0?
YES
Read data from
I2CMDR
Idle
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Figure 16-10. Master TRANSMIT of Multiple Data Bytes
Idle
Write Slave
Address to
I2CMSA
Sequence
may be
omitted in a
Single Master
system
Read I2CMCS
Write data to
I2CMDR
BUSY bit=0?
YES
Read I2CMCS
ERROR bit=0?
NO
NO
NO
BUSBSY bit=0?
YES
Write data to
I2CMDR
YES
Write ---0-011
to I2CMCS
NO
ARBLST bit=1?
YES
Write ---0-001
to I2CMCS
NO
Index=n?
YES
Write ---0-101
to I2CMCS
Write ---0-100
to I2CMCS
Error Service
Idle
Read I2CMCS
NO
BUSY bit=0?
YES
Error Service
NO
ERROR bit=0?
YES
Idle
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Figure 16-11. Master RECEIVE of Multiple Data Bytes
Idle
Write Slave
Address to
I2CMSA
Sequence
may be
omitted in a
Single Master
system
Read I2CMCS
BUSY bit=0?
Read I2CMCS
NO
YES
NO
BUSBSY bit=0?
ERROR bit=0?
NO
YES
Write ---01011
to I2CMCS
NO
Read data from
I2CMDR
ARBLST bit=1?
YES
Write ---01001
to I2CMCS
NO
Write ---0-100
to I2CMCS
Index=m-1?
Error Service
YES
Write ---00101
to I2CMCS
Idle
Read I2CMCS
BUSY bit=0?
NO
YES
NO
ERROR bit=0?
YES
Error Service
Read data from
I2CMDR
Idle
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Figure 16-12. Master RECEIVE with Repeated START after Master TRANSMIT
Idle
Master operates in
Master Transmit mode
STOP condition is not
generated
Write Slave
Address to
I2CMSA
Write ---01011
to I2CMCS
Master operates in
Master Receive mode
Repeated START
condition is generated
with changing data
direction
Idle
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Figure 16-13. Master TRANSMIT with Repeated START after Master RECEIVE
Idle
Master operates in
Master Receive mode
STOP condition is not
generated
Write Slave
Address to
I2CMSA
Write ---0-011
to I2CMCS
Master operates in
Master Transmit mode
Repeated START
condition is generated
with changing data
direction
Idle
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Figure 16-14. Standard High Speed Mode Master Transmit
IDLE
write slave address
to I2CMSA register
Master code and
arbitration is always
done in FAST or
STANDARD mode
write „---10011”
to I2CMCS register
read I2CMCS register
no
Busy=’0'
yes
no
IDLE
Error=’0'
yes
Normal sequence starts here. The
sequence below covers SINGLE send
write Slave Address
to I2MSA register
write Data
to I2CMDR register
write „---0-111”
to I2CMCS register
read I2CMCS register
no
Busy=’0'
yes
yes
IDLE
Error=’0'
no
Error service
IDLE
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16.3.5.2
I2C Slave Command Sequences
Figure 16-15 on page 1032 presents the command sequence available for the I2C slave.
Figure 16-15. Slave Command Sequence
Idle
Write OWN Slave
Address to
I2CSOAR
Write -------1
to I2CSCSR
Read I2CSCSR
NO
TREQ bit=1?
YES
Write data to
I2CSDR
NO
RREQ bit=1?
FBR is
also valid
YES
Read data from
I2CSDR
16.4
Initialization and Configuration
16.4.1
Configure the I2C Module to Transmit a Single Byte as a Master
The following example shows how to configure the I2C module to transmit a single byte as a master.
This assumes the system clock is 20 MHz.
1. Enable the I2C clock using the RCGCI2C register in the System Control module (see page 344).
2. Enable the clock to the appropriate GPIO module via the RCGCGPIO register in the System
Control module (see page 335). To find out which GPIO port to enable, refer to Table
22-5 on page 1273.
3. In the GPIO module, enable the appropriate pins for their alternate function using the
GPIOAFSEL register (see page 676). To determine which GPIOs to configure, see Table
22-4 on page 1262.
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4. Enable the I2CSDA pin for open-drain operation. See page 682.
5. Configure the PMCn fields in the GPIOPCTL register to assign the I2C signals to the appropriate
pins. See page 695 and Table 22-5 on page 1273.
6. Initialize the I2C Master by writing the I2CMCR register with a value of 0x0000.0010.
7. Set the desired SCL clock speed of 100 Kbps by writing the I2CMTPR register with the correct
value. The value written to the I2CMTPR register represents the number of system clock periods
in one SCL clock period. The TPR value is determined by the following equation:
TPR = (System Clock/(2*(SCL_LP + SCL_HP)*SCL_CLK))-1;
TPR = (20MHz/(2*(6+4)*100000))-1;
TPR = 9
Write the I2CMTPR register with the value of 0x0000.0009.
8. Specify the slave address of the master and that the next operation is a Transmit by writing the
I2CMSA register with a value of 0x0000.0076. This sets the slave address to 0x3B.
9. Place data (byte) to be transmitted in the data register by writing the I2CMDR register with the
desired data.
10. Initiate a single byte transmit of the data from Master to Slave by writing the I2CMCS register
with a value of 0x0000.0007 (STOP, START, RUN).
11. Wait until the transmission completes by polling the I2CMCS register's BUSBSY bit until it has
been cleared.
12. Check the ERROR bit in the I2CMCS register to confirm the transmit was acknowledged.
16.4.2
Configure the I2C Master to High Speed Mode
To configure the I2C master to High Speed mode:
1. Enable the I2C clock using the RCGCI2C register in the System Control module (see page 344).
2. Enable the clock to the appropriate GPIO module via the RCGCGPIO register in the System
Control module (see page 335). To find out which GPIO port to enable, refer to Table
22-5 on page 1273.
3. In the GPIO module, enable the appropriate pins for their alternate function using the
GPIOAFSEL register (see page 676). To determine which GPIOs to configure, see Table
22-4 on page 1262.
4. Enable the I2CSDA pin for open-drain operation. See page 682.
5. Configure the PMCn fields in the GPIOPCTL register to assign the I2C signals to the appropriate
pins. See page 695 and Table 22-5 on page 1273.
6. Initialize the I2C Master by writing the I2CMCR register with a value of 0x0000.0010.
7. Set the desired SCL clock speed of 3.33 Mbps by writing the I2CMTPR register with the correct
value. The value written to the I2CMTPR register represents the number of system clock periods
in one SCL clock period. The TPR value is determined by the following equation:
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Inter-Integrated Circuit (I2C) Interface
TPR = (System Clock/(2*(SCL_LP + SCL_HP)*SCL_CLK))-1;
TPR = (80 MHz/(2*(2+1)*3330000))-1;
TPR = 3
Write the I2CMTPR register with the value of 0x0000.0003.
8. To send the master code byte, software should place the value of the master code byte into the
I2CMSA register and write the I2CMCS register with a value of 0x13.
9. This places the I2C master peripheral in High-speed mode, and all subsequent transfers (until
STOP) are carried out at High-speed data rate using the normal I2CMCS command bits, without
setting the HS bit in the I2CMCS register.
10. The transaction is ended by setting the STOP bit in the I2CMCS register.
11. Wait until the transmission completes by polling the I2CMCS register's BUSBSY bit until it has
been cleared.
12. Check the ERROR bit in the I2CMCS register to confirm the transmit was acknowledged.
16.5
Register Map
Table 16-4 on page 1034 lists the I2C registers. All addresses given are relative to the I2C base address:
■
■
■
■
■
■
I2C 0: 0x4002.0000
I2C 1: 0x4002.1000
I2C 2: 0x4002.2000
I2C 3: 0x4002.3000
I2C 4: 0x400C.0000
I2C 5: 0x400C.1000
Note that the I2C module clock must be enabled before the registers can be programmed (see
page 344). There must be a delay of 3 system clocks after the I2C module clock is enabled before
any I2C module registers are accessed.
The hw_i2c.h file in the TivaWare™ Driver Library uses a base address of 0x800 for the I2C slave
registers. Be aware when using registers with offsets between 0x800 and 0x818 that TivaWare™
for C Series uses an offset between 0x000 and 0x018 with the slave base address.
Table 16-4. Inter-Integrated Circuit (I2C) Interface Register Map
Offset
Name
Type
Reset
Description
See
page
I2C Master
0x000
I2CMSA
RW
0x0000.0000
I2C Master Slave Address
1036
0x004
I2CMCS
RW
0x0000.0020
I2C Master Control/Status
1037
0x008
I2CMDR
RW
0x0000.0000
I2C Master Data
1042
0x00C
I2CMTPR
RW
0x0000.0001
I2C Master Timer Period
1043
0x010
I2CMIMR
RW
0x0000.0000
I2C Master Interrupt Mask
1044
0x014
I2CMRIS
RO
0x0000.0000
I2C Master Raw Interrupt Status
1045
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Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Table 16-4. Inter-Integrated Circuit (I2C) Interface Register Map (continued)
Description
See
page
0x0000.0000
I2C Master Masked Interrupt Status
1046
WO
0x0000.0000
I2C Master Interrupt Clear
1047
I2CMCR
RW
0x0000.0000
I2C Master Configuration
1048
0x024
I2CMCLKOCNT
RW
0x0000.0000
I2C Master Clock Low Timeout Count
1050
0x02C
I2CMBMON
RO
0x0000.0003
I2C Master Bus Monitor
1051
0x038
I2CMCR2
RW
0x0000.0000
I2C Master Configuration 2
1052
0x800
I2CSOAR
RW
0x0000.0000
I2C Slave Own Address
1053
0x804
I2CSCSR
RO
0x0000.0000
I2C Slave Control/Status
1054
0x808
I2CSDR
RW
0x0000.0000
I2C Slave Data
1056
0x80C
I2CSIMR
RW
0x0000.0000
I2C Slave Interrupt Mask
1057
0x810
I2CSRIS
RO
0x0000.0000
I2C Slave Raw Interrupt Status
1058
0x814
I2CSMIS
RO
0x0000.0000
I2C Slave Masked Interrupt Status
1059
0x818
I2CSICR
WO
0x0000.0000
I2C Slave Interrupt Clear
1060
0x81C
I2CSOAR2
RW
0x0000.0000
I2C Slave Own Address 2
1061
0x820
I2CSACKCTL
RW
0x0000.0000
I2C Slave ACK Control
1062
Offset
Name
Type
Reset
0x018
I2CMMIS
RO
0x01C
I2CMICR
0x020
I2C Slave
I2C Status and Control
0xFC0
I2CPP
RO
0x0000.0001
I2C Peripheral Properties
1063
0xFC4
I2CPC
RO
0x0000.0001
I2C Peripheral Configuration
1064
16.6
Register Descriptions (I2C Master)
The remainder of this section lists and describes the I2C master registers, in numerical order by
address offset.
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Inter-Integrated Circuit (I2C) Interface
Register 1: I2C Master Slave Address (I2CMSA), offset 0x000
This register consists of eight bits: seven address bits (A6-A0), and a Receive/Send bit, which
determines if the next operation is a Receive (High), or Transmit (Low).
I2C Master Slave Address (I2CMSA)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
Offset 0x000
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
4
3
2
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
SA
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:1
SA
RW
0x00
RO
0
RW
0
RW
0
RW
0
RW
0
0
R/S
RW
0
RW
0
RW
0
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
I2C Slave Address
This field specifies bits A6 through A0 of the slave address.
0
R/S
RW
0
Receive/Send
The R/S bit specifies if the next master operation is a Receive (High)
or Transmit (Low).
Value Description
0
Transmit
1
Receive
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Tiva™ TM4C123BH6PGE Microcontroller
Register 2: I2C Master Control/Status (I2CMCS), offset 0x004
This register accesses status bits when read and control bits when written. When read, the status
register indicates the state of the I2C bus controller. When written, the control register configures
the I2C controller operation.
The START bit generates the START or REPEATED START condition. The STOP bit determines if
the cycle stops at the end of the data cycle or continues to the next transfer cycle, which could be
a repeated START. To generate a single transmit cycle, the I2C Master Slave Address (I2CMSA)
register is written with the desired address, the R/S bit is cleared, and this register is written with
ACK=X (0 or 1), STOP=1, START=1, and RUN=1 to perform the operation and stop. When the operation
is completed (or aborted due an error), an interrupt becomes active and the data may be read from
the I2CMDR register. When the I2C module operates in Master receiver mode, the ACK bit is normally
set, causing the I2C bus controller to transmit an acknowledge automatically after each byte. This
bit must be cleared when the I2C bus controller requires no further data to be transmitted from the
slave transmitter.
Read-Only Status Register
I2C Master Control/Status (I2CMCS)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
Offset 0x004
Type RO, reset 0x0000.0020
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
CLKTO
BUSBSY
IDLE
ARBLST
ERROR
BUSY
RO
0
RO
0
RO
1
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7
CLKTO
RO
0
DATACK ADRACK
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Clock Timeout Error
Value Description
0
No clock timeout error.
1
The clock timeout error has occurred.
This bit is cleared when the master sends a STOP condition or if the
I2C master is reset.
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Inter-Integrated Circuit (I2C) Interface
Bit/Field
Name
Type
Reset
6
BUSBSY
RO
0
Description
Bus Busy
Value Description
0
The I2C bus is idle.
1
The I2C bus is busy.
The bit changes based on the START and STOP conditions.
5
IDLE
RO
1
I2C Idle
Value Description
4
ARBLST
RO
0
0
The I2C controller is not idle.
1
The I2C controller is idle.
Arbitration Lost
Value Description
3
DATACK
RO
0
0
The I2C controller won arbitration.
1
The I2C controller lost arbitration.
Acknowledge Data
Value Description
2
ADRACK
RO
0
0
The transmitted data was acknowledged
1
The transmitted data was not acknowledged.
Acknowledge Address
Value Description
1
ERROR
RO
0
0
The transmitted address was acknowledged
1
The transmitted address was not acknowledged.
Error
Value Description
0
No error was detected on the last operation.
1
An error occurred on the last operation.
The error can be from the slave address not being acknowledged or the
transmit data not being acknowledged.
0
BUSY
RO
0
I2C Busy
Value Description
0
The controller is idle.
1
The controller is busy.
When the BUSY bit is set, the other status bits are not valid.
1038
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Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Write-Only Control Register
I2C Master Control/Status (I2CMCS)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
Offset 0x004
Type WO, reset 0x0000.0020
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
10
9
8
7
6
5
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
4
3
2
1
0
HS
ACK
STOP
START
RUN
WO
0
WO
0
WO
0
WO
0
WO
0
Bit/Field
Name
Type
Reset
Description
31:5
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
4
HS
WO
0
High-Speed Enable
Value Description
3
ACK
WO
0
0
The master operates in Standard, Fast mode, or Fast mode
plus as selected by using a value in the I2CMTPR register that
results in an SCL frequency of 100 kbps for Standard mode,
400 kbps for Fast mode, or 1 Mpbs for Fast mode plus.
1
The master operates in High-Speed mode with transmission
speeds up to 3.33 Mbps.
Data Acknowledge Enable
Value Description
2
STOP
WO
0
0
The received data byte is not acknowledged automatically by
the master.
1
The received data byte is acknowledged automatically by the
master. See field decoding in Table 16-5 on page 1040.
Generate STOP
Value Description
0
The controller does not generate the STOP condition.
1
The controller generates the STOP condition. See field decoding
in Table 16-5 on page 1040.
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Inter-Integrated Circuit (I2C) Interface
Bit/Field
Name
Type
Reset
1
START
WO
0
Description
Generate START
Value Description
0
RUN
WO
0
The controller does not generate the START condition.
1
The controller generates the START or repeated START
condition. See field decoding in Table 16-5 on page 1040.
I2C Master Enable
0
Value Description
0
This encoding means the master is unable to transmit or receive
data.
1
The master is able to transmit or receive data.
See field decoding in Table 16-5 on page 1040.
Table 16-5. Write Field Decoding for I2CMCS[3:0] Field
Current I2CMSA[0]
State
R/S
Idle
I2CMCS[3:0]
ACK
STOP
START
RUN
Description
0
X
a
0
1
1
START condition followed by TRANSMIT (master goes
to the Master Transmit state).
0
X
1
1
1
START condition followed by a TRANSMIT and STOP
condition (master remains in Idle state).
1
0
0
1
1
START condition followed by RECEIVE operation with
negative ACK (master goes to the Master Receive state).
1
0
1
1
1
START condition followed by RECEIVE and STOP
condition (master remains in Idle state).
1
1
0
1
1
START condition followed by RECEIVE (master goes to
the Master Receive state).
1
1
1
1
1
Illegal
All other combinations not listed are non-operations.
NOP
1040
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Tiva™ TM4C123BH6PGE Microcontroller
Table 16-5. Write Field Decoding for I2CMCS[3:0] Field (continued)
Current I2CMSA[0]
State
R/S
Master
Transmit
I2CMCS[3:0]
Description
ACK
STOP
START
RUN
X
X
0
0
1
TRANSMIT operation (master remains in Master
Transmit state).
X
X
1
0
0
STOP condition (master goes to Idle state).
X
X
1
0
1
TRANSMIT followed by STOP condition (master goes
to Idle state).
0
X
0
1
1
Repeated START condition followed by a TRANSMIT
(master remains in Master Transmit state).
0
X
1
1
1
Repeated START condition followed by TRANSMIT and
STOP condition (master goes to Idle state).
1
0
0
1
1
Repeated START condition followed by a RECEIVE
operation with a negative ACK (master goes to Master
Receive state).
1
0
1
1
1
Repeated START condition followed by a TRANSMIT
and STOP condition (master goes to Idle state).
1
1
0
1
1
Repeated START condition followed by RECEIVE
(master goes to Master Receive state).
1
1
1
1
1
Illegal.
All other combinations not listed are non-operations.
NOP.
X
0
0
0
1
RECEIVE operation with negative ACK (master remains
in Master Receive state).
X
X
1
0
0
STOP condition (master goes to Idle state).
X
0
1
0
1
RECEIVE followed by STOP condition (master goes to
Idle state).
X
1
0
0
1
RECEIVE operation (master remains in Master Receive
state).
X
1
1
0
1
Illegal.
1
0
0
1
1
Repeated START condition followed by RECEIVE
operation with a negative ACK (master remains in Master
Receive state).
1
0
1
1
1
Repeated START condition followed by RECEIVE and
STOP condition (master goes to Idle state).
1
1
0
1
1
Repeated START condition followed by RECEIVE
(master remains in Master Receive state).
0
X
0
1
1
Repeated START condition followed by TRANSMIT
(master goes to Master Transmit state).
0
X
1
1
1
Repeated START condition followed by TRANSMIT and
STOP condition (master goes to Idle state).
Master
Receive
All other combinations not listed are non-operations.
b
NOP.
a. An X in a table cell indicates the bit can be 0 or 1.
b. In Master Receive mode, a STOP condition should be generated only after a Data Negative Acknowledge executed by
the master or an Address Negative Acknowledge executed by the slave.
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Inter-Integrated Circuit (I2C) Interface
Register 3: I2C Master Data (I2CMDR), offset 0x008
Important: This register is read-sensitive. See the register description for details.
This register contains the data to be transmitted when in the Master Transmit state and the data
received when in the Master Receive state.
I2C Master Data (I2CMDR)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
Offset 0x008
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
reserved
Type
Reset
DATA
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
DATA
RW
0x00
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
This byte contains the data transferred during a transaction.
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Tiva™ TM4C123BH6PGE Microcontroller
Register 4: I2C Master Timer Period (I2CMTPR), offset 0x00C
This register is programmed to set the timer period for the SCL clock and assign the SCL clock to
either standard or high-speed mode.
I2C Master Timer Period (I2CMTPR)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
Offset 0x00C
Type RW, reset 0x0000.0001
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RW
0
RW
0
RW
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
HS
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7
HS
WO
0x0
RO
0
WO
0
TPR
RW
0
RW
0
RW
0
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
High-Speed Enable
Value Description
6:0
TPR
RW
0x1
0
The SCL Clock Period set by TPR applies to Standard mode
(100 Kbps), Fast-mode (400 Kbps), or Fast-mode plus (1 Mbps).
1
The SCL Clock Period set by TPR applies to High-speed mode
(3.33 Mbps).
Timer Period
This field is used in the equation to configure SCL_PERIOD:
SCL_PERIOD = 2×(1 + TPR)×(SCL_LP + SCL_HP)×CLK_PRD
where:
SCL_PRD is the SCL line period (I2C clock).
TPR is the Timer Period register value (range of 1 to 127).
SCL_LP is the SCL Low period (fixed at 6).
SCL_HP is the SCL High period (fixed at 4).
CLK_PRD is the system clock period in ns.
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Inter-Integrated Circuit (I2C) Interface
Register 5: I2C Master Interrupt Mask (I2CMIMR), offset 0x010
This register controls whether a raw interrupt is promoted to a controller interrupt.
I2C Master Interrupt Mask (I2CMIMR)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
Offset 0x010
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
1
0
CLKIM
IM
RW
0
RW
0
Bit/Field
Name
Type
Reset
Description
31:2
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1
CLKIM
RW
0
Clock Timeout Interrupt Mask
Value Description
0
IM
RW
0
0
The CLKRIS interrupt is suppressed and not sent to the interrupt
controller.
1
The clock timeout interrupt is sent to the interrupt controller
when the CLKRIS bit in the I2CMRIS register is set.
Master Interrupt Mask
Value Description
0
The RIS interrupt is suppressed and not sent to the interrupt
controller.
1
The master interrupt is sent to the interrupt controller when the
RIS bit in the I2CMRIS register is set.
1044
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Register 6: I2C Master Raw Interrupt Status (I2CMRIS), offset 0x014
This register specifies whether an interrupt is pending.
I2C Master Raw Interrupt Status (I2CMRIS)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
Offset 0x014
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
1
0
CLKRIS
RIS
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:2
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1
CLKRIS
RO
0
Clock Timeout Raw Interrupt Status
Value Description
0
No interrupt.
1
The clock timeout interrupt is pending.
This bit is cleared by writing a 1 to the CLKIC bit in the I2CMICR register.
0
RIS
RO
0
Master Raw Interrupt Status
Value Description
0
No interrupt.
1
A master interrupt is pending.
This bit is cleared by writing a 1 to the IC bit in the I2CMICR register.
June 12, 2014
1045
Texas Instruments-Production Data
Inter-Integrated Circuit (I2C) Interface
Register 7: I2C Master Masked Interrupt Status (I2CMMIS), offset 0x018
This register specifies whether an interrupt was signaled.
I2C Master Masked Interrupt Status (I2CMMIS)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
Offset 0x018
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
1
0
CLKMIS
MIS
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:2
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1
CLKMIS
RO
0
Clock Timeout Masked Interrupt Status
Value Description
0
No interrupt.
1
An unmasked clock timeout interrupt was signaled and is
pending.
This bit is cleared by writing a 1 to the CLKIC bit in the I2CMICR register.
0
MIS
RO
0
Masked Interrupt Status
Value Description
0
An interrupt has not occurred or is masked.
1
An unmasked master interrupt was signaled and is pending.
This bit is cleared by writing a 1 to the IC bit in the I2CMICR register.
1046
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Register 8: I2C Master Interrupt Clear (I2CMICR), offset 0x01C
This register clears the raw and masked interrupts.
I2C Master Interrupt Clear (I2CMICR)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
Offset 0x01C
Type WO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
1
0
CLKIC
IC
WO
0
WO
0
Bit/Field
Name
Type
Reset
Description
31:2
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1
CLKIC
WO
0
Clock Timeout Interrupt Clear
Writing a 1 to this bit clears the CLKRIS bit in the I2CMRIS register and
the CLKMIS bit in the I2CMMIS register.
A read of this register returns no meaningful data.
0
IC
WO
0
Master Interrupt Clear
Writing a 1 to this bit clears the RIS bit in the I2CMRIS register and the
MIS bit in the I2CMMIS register.
A read of this register returns no meaningful data.
June 12, 2014
1047
Texas Instruments-Production Data
Inter-Integrated Circuit (I2C) Interface
Register 9: I2C Master Configuration (I2CMCR), offset 0x020
This register configures the mode (Master or Slave), enables the glitch filter, and sets the interface
for test mode loopback.
I2C Master Configuration (I2CMCR)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
Offset 0x020
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
3
2
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
15
14
13
12
RO
0
RO
0
RO
0
RO
0
RO
0
11
10
9
8
7
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:7
reserved
RO
0x0000.00
6
GFE
RW
0
RO
0
RO
0
6
5
4
GFE
SFE
MFE
RW
0
RW
0
RW
0
reserved
RO
0
RO
0
0
LPBK
RO
0
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
I2C Glitch Filter Enable
Value Description
0
I2C glitch filter is disabled.
1
I2C glitch filter is enabled.
Use the GFPW bit in the I2C Master Configuration 2 (I2CMCR2) register
to program the pulse width.
5
SFE
RW
0
I2C Slave Function Enable
Value Description
4
MFE
RW
0
0
Slave mode is disabled.
1
Slave mode is enabled.
I2C Master Function Enable
Value Description
3:1
reserved
RO
0x0
0
Master mode is disabled.
1
Master mode is enabled.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1048
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Bit/Field
Name
Type
Reset
0
LPBK
RW
0
Description
I2C Loopback
Value Description
0
Normal operation.
1
The controller in a test mode loopback configuration.
June 12, 2014
1049
Texas Instruments-Production Data
Inter-Integrated Circuit (I2C) Interface
Register 10: I2C Master Clock Low Timeout Count (I2CMCLKOCNT), offset
0x024
This register contains the upper 8 bits of a 12-bit counter that can be used to keep the timeout limit
for clock stretching by a remote slave. The lower four bits of the counter are not user visible and
are always 0x0.
Note:
The Master Clock Low Timeout counter counts for the entire time SCL is held Low
continuously. If SCL is deasserted at any point, the Master Clock Low Timeout Counter is
reloaded with the value in the I2CMCLKOCNT register and begins counting down from this
value.
I2C Master Clock Low Timeout Count (I2CMCLKOCNT)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
Offset 0x024
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
reserved
Type
Reset
CNTL
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
CNTL
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
I2C Master Count
This field contains the upper 8 bits of a 12-bit counter for the clock low
timeout count.
Note:
The value of CNTL must be greater than 0x1.
1050
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Register 11: I2C Master Bus Monitor (I2CMBMON), offset 0x02C
This register is used to determine the SCL and SDA signal status.
I2C Master Bus Monitor (I2CMBMON)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
Offset 0x02C
Type RO, reset 0x0000.0003
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:2
reserved
RO
0x0000.000
1
SDA
RO
1
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
1
0
SDA
SCL
RO
1
RO
1
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
I2C SDA Status
Value Description
0
SCL
RO
1
0
The I2CSDA signal is low.
1
The I2CSDA signal is high.
I2C SCL Status
Value Description
0
The I2CSCL signal is low.
1
The I2CSCL signal is high.
June 12, 2014
1051
Texas Instruments-Production Data
Inter-Integrated Circuit (I2C) Interface
Register 12: I2C Master Configuration 2 (I2CMCR2), offset 0x038
This register can be programmed to select the pulse width for glitch suppression, measured in
system clocks.
I2C Master Configuration 2 (I2CMCR2)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
Offset 0x038
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
5
4
3
2
1
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
15
14
13
12
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
11
10
9
8
7
6
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
GFPW
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
RW
0
reserved
RW
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:7
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
6:4
GFPW
RW
0
I2C Glitch Filter Pulse Width
This field controls the pulse width select for glitch suppression on the
SCL and SDA lines. Glitch suppression values can be programmed
relative to system clocks.
Value Description
3:0
16.7
reserved
RO
0
0x0
Bypass
0x1
1 clock
0x2
2 clocks
0x3
3 clocks
0x4
4 clocks
0x5
8 clocks
0x6
16 clocks
0x7
31 clocks
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Register Descriptions (I2C Slave)
The remainder of this section lists and describes the I2C slave registers, in numerical order by
address offset.
1052
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Register 13: I2C Slave Own Address (I2CSOAR), offset 0x800
This register consists of seven address bits that identify the TM4C123BH6PGE I2C device on the
I2C bus.
I2C Slave Own Address (I2CSOAR)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
Offset 0x800
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
reserved
Type
Reset
OAR
RO
0
Bit/Field
Name
Type
Reset
31:7
reserved
RO
0x0000.00
6:0
OAR
RW
0x00
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
I2C Slave Own Address
This field specifies bits A6 through A0 of the slave address.
June 12, 2014
1053
Texas Instruments-Production Data
Inter-Integrated Circuit (I2C) Interface
Register 14: I2C Slave Control/Status (I2CSCSR), offset 0x804
This register functions as a control register when written, and a status register when read.
Read-Only Status Register
I2C Slave Control/Status (I2CSCSR)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
Offset 0x804
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
OAR2SEL
FBR
TREQ
RREQ
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:4
reserved
RO
0x0000.000
3
OAR2SEL
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
OAR2 Address Matched
Value Description
0
Either the address is not matched or the match is in legacy
mode.
1
OAR2 address matched and ACKed by the slave.
This bit gets reevaluated after every address comparison.
2
FBR
RO
0
First Byte Received
Value Description
0
The first byte has not been received.
1
The first byte following the slave's own address has been
received.
This bit is only valid when the RREQ bit is set and is automatically cleared
when data has been read from the I2CSDR register.
Note:
This bit is not used for slave transmit operations.
1054
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Bit/Field
Name
Type
Reset
1
TREQ
RO
0
Description
Transmit Request
Value Description
0
RREQ
RO
0
0
No outstanding transmit request.
1
The I2C controller has been addressed as a slave transmitter
and is using clock stretching to delay the master until data has
been written to the I2CSDR register.
Receive Request
Value Description
0
No outstanding receive data.
1
The I2C controller has outstanding receive data from the I2C
master and is using clock stretching to delay the master until
the data has been read from the I2CSDR register.
Write-Only Control Register
I2C Slave Control/Status (I2CSCSR)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
Offset 0x804
Type WO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:1
reserved
RO
0x0000.000
0
DA
WO
0
RO
0
0
DA
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
WO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Device Active
Value Description
0
Disables the I2C slave operation.
1
Enables the I2C slave operation.
Once this bit has been set, it should not be set again unless it has been
cleared by writing a 0 or by a reset, otherwise transfer failures may
occur.
June 12, 2014
1055
Texas Instruments-Production Data
Inter-Integrated Circuit (I2C) Interface
Register 15: I2C Slave Data (I2CSDR), offset 0x808
Important: This register is read-sensitive. See the register description for details.
This register contains the data to be transmitted when in the Slave Transmit state, and the data
received when in the Slave Receive state.
I2C Slave Data (I2CSDR)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
Offset 0x808
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
reserved
Type
Reset
DATA
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
DATA
RW
0x00
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Data for Transfer
This field contains the data for transfer during a slave receive or transmit
operation.
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Register 16: I2C Slave Interrupt Mask (I2CSIMR), offset 0x80C
This register controls whether a raw interrupt is promoted to a controller interrupt.
I2C Slave Interrupt Mask (I2CSIMR)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
Offset 0x80C
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
2
1
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
9
8
7
6
5
4
3
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
STOPIM STARTIM DATAIM
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
RW
0
RW
0
Bit/Field
Name
Type
Reset
Description
31:3
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2
STOPIM
RW
0
Stop Condition Interrupt Mask
Value Description
1
STARTIM
RW
0
0
The STOPRIS interrupt is suppressed and not sent to the
interrupt controller.
1
The STOP condition interrupt is sent to the interrupt controller
when the STOPRIS bit in the I2CSRIS register is set.
Start Condition Interrupt Mask
Value Description
0
DATAIM
RW
0
0
The STARTRIS interrupt is suppressed and not sent to the
interrupt controller.
1
The START condition interrupt is sent to the interrupt controller
when the STARTRIS bit in the I2CSRIS register is set.
Data Interrupt Mask
Value Description
0
The DATARIS interrupt is suppressed and not sent to the
interrupt controller.
1
The data received or data requested interrupt is sent to the
interrupt controller when the DATARIS bit in the I2CSRIS register
is set.
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Inter-Integrated Circuit (I2C) Interface
Register 17: I2C Slave Raw Interrupt Status (I2CSRIS), offset 0x810
This register specifies whether an interrupt is pending.
I2C Slave Raw Interrupt Status (I2CSRIS)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
Offset 0x810
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
2
1
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
9
8
7
6
5
4
3
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
STOPRIS STARTRIS DATARIS
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:3
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2
STOPRIS
RO
0
Stop Condition Raw Interrupt Status
Value Description
0
No interrupt.
1
A STOP condition interrupt is pending.
This bit is cleared by writing a 1 to the STOPIC bit in the I2CSICR
register.
1
STARTRIS
RO
0
Start Condition Raw Interrupt Status
Value Description
0
No interrupt.
1
A START condition interrupt is pending.
This bit is cleared by writing a 1 to the STARTIC bit in the I2CSICR
register.
0
DATARIS
RO
0
Data Raw Interrupt Status
Value Description
0
No interrupt.
1
A data received or data requested interrupt is pending.
This bit is cleared by writing a 1 to the DATAIC bit in the I2CSICR
register.
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Register 18: I2C Slave Masked Interrupt Status (I2CSMIS), offset 0x814
This register specifies whether an interrupt was signaled.
I2C Slave Masked Interrupt Status (I2CSMIS)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
Offset 0x814
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
2
1
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
9
8
7
6
5
4
3
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
STOPMIS STARTMIS DATAMIS
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:3
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2
STOPMIS
RO
0
Stop Condition Masked Interrupt Status
Value Description
0
An interrupt has not occurred or is masked.
1
An unmasked STOP condition interrupt was signaled is pending.
This bit is cleared by writing a 1 to the STOPIC bit in the I2CSICR
register.
1
STARTMIS
RO
0
Start Condition Masked Interrupt Status
Value Description
0
An interrupt has not occurred or is masked.
1
An unmasked START condition interrupt was signaled is
pending.
This bit is cleared by writing a 1 to the STARTIC bit in the I2CSICR
register.
0
DATAMIS
RO
0
Data Masked Interrupt Status
Value Description
0
An interrupt has not occurred or is masked.
1
An unmasked data received or data requested interrupt was
signaled is pending.
This bit is cleared by writing a 1 to the DATAIC bit in the I2CSICR
register.
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Inter-Integrated Circuit (I2C) Interface
Register 19: I2C Slave Interrupt Clear (I2CSICR), offset 0x818
This register clears the raw interrupt. A read of this register returns no meaningful data.
I2C Slave Interrupt Clear (I2CSICR)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
Offset 0x818
Type WO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
2
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
9
8
7
6
5
4
3
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
STOPIC STARTIC
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
WO
0
WO
0
0
DATAIC
WO
0
Bit/Field
Name
Type
Reset
Description
31:3
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2
STOPIC
WO
0
Stop Condition Interrupt Clear
Writing a 1 to this bit clears the STOPRIS bit in the I2CSRIS register
and the STOPMIS bit in the I2CSMIS register.
A read of this register returns no meaningful data.
1
STARTIC
WO
0
Start Condition Interrupt Clear
Writing a 1 to this bit clears the STARTRIS bit in the I2CSRIS register
and the STARTMIS bit in the I2CSMIS register.
A read of this register returns no meaningful data.
0
DATAIC
WO
0
Data Interrupt Clear
Writing a 1 to this bit clears the STOPRIS bit in the I2CSRIS register
and the STOPMIS bit in the I2CSMIS register.
A read of this register returns no meaningful data.
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Register 20: I2C Slave Own Address 2 (I2CSOAR2), offset 0x81C
This register consists of seven address bits that identify the alternate address for the I2C device on
the I2C bus.
I2C Slave Own Address 2 (I2CSOAR2)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
Offset 0x81C
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
reserved
Type
Reset
OAR2EN
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7
OAR2EN
RW
0
RW
0
OAR2
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
I2C Slave Own Address 2 Enable
Value Description
6:0
OAR2
RW
0x00
0
The alternate address is disabled.
1
Enables the use of the alternate address in the OAR2 field.
I2C Slave Own Address 2
This field specifies the alternate OAR2 address.
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Inter-Integrated Circuit (I2C) Interface
Register 21: I2C Slave ACK Control (I2CSACKCTL), offset 0x820
This register enables the I2C slave to NACK for invalid data or command or ACK for valid data or
command. The I2C clock is pulled low after the last data bit until this register is written.
I2C Slave ACK Control (I2CSACKCTL)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
Offset 0x820
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:2
reserved
RO
0x0000.000
1
ACKOVAL
RW
0
ACKOVAL ACKOEN
RW
0
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
I2C Slave ACK Override Value
Value Description
0
ACKOEN
RW
0
0
An ACK is sent indicating valid data or command.
1
A NACK is sent indicating invalid data or command.
I2C Slave ACK Override Enable
Value Description
16.8
0
A response in not provided.
1
An ACK or NACK is sent according to the value written to the
ACKOVAL bit.
Register Descriptions (I2C Status and Control)
The remainder of this section lists and describes the I2C status and control registers, in numerical
order by address offset.
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Register 22: I2C Peripheral Properties (I2CPP), offset 0xFC0
The I2CPP register provides information regarding the properties of the I2C module.
I2C Peripheral Properties (I2CPP)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
Offset 0xFC0
Type RO, reset 0x0000.0001
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
reserved
Type
Reset
reserved
Type
Reset
RO
0
HS
Bit/Field
Name
Type
Reset
Description
31:1
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
HS
RO
0x1
High-Speed Capable
Value Description
0
The interface is capable of Standard, Fast, or Fast mode plus
operation.
1
The interface is capable of High-Speed operation.
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Inter-Integrated Circuit (I2C) Interface
Register 23: I2C Peripheral Configuration (I2CPC), offset 0xFC4
The I2CPC register allows software to enable features present in the I2C module.
I2C Peripheral Configuration (I2CPC)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
Offset 0xFC4
Type RO, reset 0x0000.0001
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW
1
reserved
Type
Reset
reserved
Type
Reset
RO
0
HS
Bit/Field
Name
Type
Reset
Description
31:1
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
HS
RW
1
High-Speed Capable
Value Description
0
The interface is set to Standard, Fast or Fast mode plus
operation.
1
The interface is set to High-Speed operation. Note that this
encoding may only be used if the HS bit in the I2CPP register
is set. Otherwise, this encoding is not available.
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17
Controller Area Network (CAN) Module
Controller Area Network (CAN) is a multicast, shared serial bus standard for connecting electronic
control units (ECUs). CAN was specifically designed to be robust in electromagnetically-noisy
environments and can utilize a differential balanced line like RS-485 or a more robust twisted-pair
wire. Originally created for automotive purposes, it is also used in many embedded control
applications (such as industrial and medical). Bit rates up to 1 Mbps are possible at network lengths
less than 40 meters. Decreased bit rates allow longer network distances (for example, 125 Kbps at
500 meters).
The TM4C123BH6PGE microcontroller includes two CAN units with the following features:
■ CAN protocol version 2.0 part A/B
■ Bit rates up to 1 Mbps
■ 32 message objects with individual identifier masks
■ Maskable interrupt
■ Disable Automatic Retransmission mode for Time-Triggered CAN (TTCAN) applications
■ Programmable loopback mode for self-test operation
■ Programmable FIFO mode enables storage of multiple message objects
■ Gluelessly attaches to an external CAN transceiver through the CANnTX and CANnRX signals
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Controller Area Network (CAN) Module
17.1
Block Diagram
Figure 17-1. CAN Controller Block Diagram
CAN Control
CANCTL
CANSTS
CANERR
CANBIT
CANINT
CANTST
CANBRPE
CAN Tx
CAN Interface 1
APB Pins
APB
Interface
CANIF1CRQ
CANIF1CMSK
CANIF1MSK1
CANIF1MSK2
CANIF1ARB1
CANIF1ARB2
CANIF1MCTL
CANIF1DA1
CANIF1DA2
CANIF1DB1
CANIF1DB2
CAN Core
CAN Rx
CAN Interface 2
CANIF2CRQ
CANIF2CMSK
CANIF2MSK1
CANIF2MSK2
CANIF2ARB1
CANIF2ARB2
CANIF2MCTL
CANIF2DA1
CANIF2DA2
CANIF2DB1
CANIF2DB2
Message Object
Registers
CANTXRQ1
CANTXRQ2
CANNWDA1
CANNWDA2
CANMSG1INT
CANMSG2INT
CANMSG1VAL
CANMSG2VAL
Message RAM
32 Message Objects
17.2
Signal Description
The following table lists the external signals of the CAN controller and describes the function of
each. The CAN controller signals are alternate functions for some GPIO signals and default to be
GPIO signals at reset. The column in the table below titled "Pin Mux/Pin Assignment" lists the
possible GPIO pin placements for the CAN signals. The AFSEL bit in the GPIO Alternate Function
Select (GPIOAFSEL) register (page 676) should be set to choose the CAN controller function. The
number in parentheses is the encoding that must be programmed into the PMCn field in the GPIO
Port Control (GPIOPCTL) register (page 695) to assign the CAN signal to the specified GPIO port
pin. For more information on configuring GPIOs, see “General-Purpose Input/Outputs
(GPIOs)” on page 647.
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Table 17-1. Controller Area Network Signals (144LQFP)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
CAN0Rx
62
81
136
139
PF0 (3)
PN0 (1)
PB4 (8)
PE4 (8)
I
TTL
CAN module 0 receive.
CAN0Tx
65
80
135
140
PF3 (3)
PN1 (1)
PB5 (8)
PE5 (8)
O
TTL
CAN module 0 transmit.
CAN1Rx
37
133
PA0 (8)
PE6 (8)
I
TTL
CAN module 1 receive.
CAN1Tx
38
134
PA1 (8)
PE7 (8)
O
TTL
CAN module 1 transmit.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
17.3
Functional Description
The TM4C123BH6PGE CAN controller conforms to the CAN protocol version 2.0 (parts A and B).
Message transfers that include data, remote, error, and overload frames with an 11-bit identifier
(standard) or a 29-bit identifier (extended) are supported. Transfer rates can be programmed up to
1 Mbps.
The CAN module consists of three major parts:
■ CAN protocol controller and message handler
■ Message memory
■ CAN register interface
A data frame contains data for transmission, whereas a remote frame contains no data and is used
to request the transmission of a specific message object. The CAN data/remote frame is constructed
as shown in Figure 17-2.
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Controller Area Network (CAN) Module
Figure 17-2. CAN Data/Remote Frame
Remote
Transmission
Request
Start
Of Frame
Bus
Idle
R
S
Control
O Message Delimiter T Field
R
F
Number 1
Of Bits
11 or 29
1
6
Delimiter
Bits
Data Field
CRC
Sequence
A
C
K
EOP
IFS
0 . . . 64
15
1 1 1
7
3
CRC Sequence
CRC
Field
Arbitration Field
Bit Stuffing
End of
Frame
Field
Bus
Idle
Interframe
Field
Acknowledgement
Field
CAN Data Frame
The protocol controller transfers and receives the serial data from the CAN bus and passes the data
on to the message handler. The message handler then loads this information into the appropriate
message object based on the current filtering and identifiers in the message object memory. The
message handler is also responsible for generating interrupts based on events on the CAN bus.
The message object memory is a set of 32 identical memory blocks that hold the current configuration,
status, and actual data for each message object. These memory blocks are accessed via either of
the CAN message object register interfaces.
The message memory is not directly accessible in the TM4C123BH6PGE memory map, so the
TM4C123BH6PGE CAN controller provides an interface to communicate with the message memory
via two CAN interface register sets for communicating with the message objects. These two interfaces
must be used to read or write to each message object. The two message object interfaces allow
parallel access to the CAN controller message objects when multiple objects may have new
information that must be processed. In general, one interface is used for transmit data and one for
receive data.
17.3.1
Initialization
To use the CAN controller, the peripheral clock must be enabled using the RCGC0 register (see
page 451). In addition, the clock to the appropriate GPIO module must be enabled via the RCGC2
register (see page 459). To find out which GPIO port to enable, refer to Table 22-4 on page 1262. Set
the GPIO AFSEL bits for the appropriate pins (see page 676). Configure the PMCn fields in the
GPIOPCTL register to assign the CAN signals to the appropriate pins. See page 695 and Table
22-5 on page 1273.
Software initialization is started by setting the INIT bit in the CAN Control (CANCTL) register (with
software or by a hardware reset) or by going bus-off, which occurs when the transmitter's error
counter exceeds a count of 255. While INIT is set, all message transfers to and from the CAN bus
are stopped and the CANnTX signal is held High. Entering the initialization state does not change
the configuration of the CAN controller, the message objects, or the error counters. However, some
configuration registers are only accessible while in the initialization state.
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To initialize the CAN controller, set the CAN Bit Timing (CANBIT) register and configure each
message object. If a message object is not needed, label it as not valid by clearing the MSGVAL bit
in the CAN IFn Arbitration 2 (CANIFnARB2) register. Otherwise, the whole message object must
be initialized, as the fields of the message object may not have valid information, causing unexpected
results. Both the INIT and CCE bits in the CANCTL register must be set in order to access the
CANBIT register and the CAN Baud Rate Prescaler Extension (CANBRPE) register to configure
the bit timing. To leave the initialization state, the INIT bit must be cleared. Afterwards, the internal
Bit Stream Processor (BSP) synchronizes itself to the data transfer on the CAN bus by waiting for
the occurrence of a sequence of 11 consecutive recessive bits (indicating a bus idle condition)
before it takes part in bus activities and starts message transfers. Message object initialization does
not require the CAN to be in the initialization state and can be done on the fly. However, message
objects should all be configured to particular identifiers or set to not valid before message transfer
starts. To change the configuration of a message object during normal operation, clear the MSGVAL
bit in the CANIFnARB2 register to indicate that the message object is not valid during the change.
When the configuration is completed, set the MSGVAL bit again to indicate that the message object
is once again valid.
17.3.2
Operation
Two sets of CAN Interface Registers (CANIF1x and CANIF2x) are used to access the message
objects in the Message RAM. The CAN controller coordinates transfers to and from the Message
RAM to and from the registers. The two sets are independent and identical and can be used to
queue transactions. Generally, one interface is used to transmit data and one is used to receive
data.
Once the CAN module is initialized and the INIT bit in the CANCTL register is cleared, the CAN
module synchronizes itself to the CAN bus and starts the message transfer. As each message is
received, it goes through the message handler's filtering process, and if it passes through the filter,
is stored in the message object specified by the MNUM bit in the CAN IFn Command Request
(CANIFnCRQ) register. The whole message (including all arbitration bits, data-length code, and
eight data bytes) is stored in the message object. If the Identifier Mask (the MSK bits in the CAN IFn
Mask 1 and CAN IFn Mask 2 (CANIFnMSKn) registers) is used, the arbitration bits that are masked
to "don't care" may be overwritten in the message object.
The CPU may read or write each message at any time via the CAN Interface Registers. The message
handler guarantees data consistency in case of concurrent accesses.
The transmission of message objects is under the control of the software that is managing the CAN
hardware. Message objects can be used for one-time data transfers or can be permanent message
objects used to respond in a more periodic manner. Permanent message objects have all arbitration
and control set up, and only the data bytes are updated. At the start of transmission, the appropriate
TXRQST bit in the CAN Transmission Request n (CANTXRQn) register and the NEWDAT bit in the
CAN New Data n (CANNWDAn) register are set. If several transmit messages are assigned to the
same message object (when the number of message objects is not sufficient), the whole message
object has to be configured before the transmission of this message is requested.
The transmission of any number of message objects may be requested at the same time; they are
transmitted according to their internal priority, which is based on the message identifier (MNUM) for
the message object, with 1 being the highest priority and 32 being the lowest priority. Messages
may be updated or set to not valid any time, even when their requested transmission is still pending.
The old data is discarded when a message is updated before its pending transmission has started.
Depending on the configuration of the message object, the transmission of a message may be
requested autonomously by the reception of a remote frame with a matching identifier.
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Transmission can be automatically started by the reception of a matching remote frame. To enable
this mode, set the RMTEN bit in the CAN IFn Message Control (CANIFnMCTL) register. A matching
received remote frame causes the TXRQST bit to be set, and the message object automatically
transfers its data or generates an interrupt indicating a remote frame was requested. A remote frame
can be strictly a single message identifier, or it can be a range of values specified in the message
object. The CAN mask registers, CANIFnMSKn, configure which groups of frames are identified
as remote frame requests. The UMASK bit in the CANIFnMCTL register enables the MSK bits in the
CANIFnMSKn register to filter which frames are identified as a remote frame request. The MXTD
bit in the CANIFnMSK2 register should be set if a remote frame request is expected to be triggered
by 29-bit extended identifiers.
17.3.3
Transmitting Message Objects
If the internal transmit shift register of the CAN module is ready for loading, and if a data transfer is
not occurring between the CAN Interface Registers and message RAM, the valid message object
with the highest priority that has a pending transmission request is loaded into the transmit shift
register by the message handler and the transmission is started. The message object's NEWDAT bit
in the CANNWDAn register is cleared. After a successful transmission, and if no new data was
written to the message object since the start of the transmission, the TXRQST bit in the CANTXRQn
register is cleared. If the CAN controller is configured to interrupt on a successful transmission of a
message object, (the TXIE bit in the CAN IFn Message Control (CANIFnMCTL) register is set),
the INTPND bit in the CANIFnMCTL register is set after a successful transmission. If the CAN
module has lost the arbitration or if an error occurred during the transmission, the message is
re-transmitted as soon as the CAN bus is free again. If, meanwhile, the transmission of a message
with higher priority has been requested, the messages are transmitted in the order of their priority.
17.3.4
Configuring a Transmit Message Object
The following steps illustrate how to configure a transmit message object.
1. In the CAN IFn Command Mask (CANIFnCMASK) register:
■ Set the WRNRD bit to specify a write to the CANIFnCMASK register; specify whether to
transfer the IDMASK, DIR, and MXTD of the message object into the CAN IFn registers using
the MASK bit
■ Specify whether to transfer the ID, DIR, XTD, and MSGVAL of the message object into the
interface registers using the ARB bit
■ Specify whether to transfer the control bits into the interface registers using the CONTROL
bit
■ Specify whether to clear the INTPND bit in the CANIFnMCTL register using the CLRINTPND
bit
■ Specify whether to clear the NEWDAT bit in the CANNWDAn register using the NEWDAT bit
■ Specify which bits to transfer using the DATAA and DATAB bits
2. In the CANIFnMSK1 register, use the MSK[15:0] bits to specify which of the bits in the 29-bit
or 11-bit message identifier are used for acceptance filtering. Note that MSK[15:0] in this
register are used for bits [15:0] of the 29-bit message identifier and are not used for an 11-bit
identifier. A value of 0x00 enables all messages to pass through the acceptance filtering. Also
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note that in order for these bits to be used for acceptance filtering, they must be enabled by
setting the UMASK bit in the CANIFnMCTL register.
3. In the CANIFnMSK2 register, use the MSK[12:0] bits to specify which of the bits in the 29-bit
or 11-bit message identifier are used for acceptance filtering. Note that MSK[12:0] are used
for bits [28:16] of the 29-bit message identifier; whereas MSK[12:2] are used for bits [10:0] of
the 11-bit message identifier. Use the MXTD and MDIR bits to specify whether to use XTD and
DIR for acceptance filtering. A value of 0x00 enables all messages to pass through the
acceptance filtering. Also note that in order for these bits to be used for acceptance filtering,
they must be enabled by setting the UMASK bit in the CANIFnMCTL register.
4. For a 29-bit identifier, configure ID[15:0] in the CANIFnARB1 register for bits [15:0] of the
message identifier and ID[12:0] in the CANIFnARB2 register for bits [28:16] of the message
identifier. Set the XTD bit to indicate an extended identifier; set the DIR bit to indicate transmit;
and set the MSGVAL bit to indicate that the message object is valid.
5. For an 11-bit identifier, disregard the CANIFnARB1 register and configure ID[12:2] in the
CANIFnARB2 register for bits [10:0] of the message identifier. Clear the XTD bit to indicate a
standard identifier; set the DIR bit to indicate transmit; and set the MSGVAL bit to indicate that
the message object is valid.
6. In the CANIFnMCTL register:
■ Optionally set the UMASK bit to enable the mask (MSK, MXTD, and MDIR specified in the
CANIFnMSK1 and CANIFnMSK2 registers) for acceptance filtering
■ Optionally set the TXIE bit to enable the INTPND bit to be set after a successful transmission
■ Optionally set the RMTEN bit to enable the TXRQST bit to be set on the reception of a matching
remote frame allowing automatic transmission
■ Set the EOB bit for a single message object
■ Configure the DLC[3:0] field to specify the size of the data frame. Take care during this
configuration not to set the NEWDAT, MSGLST, INTPND or TXRQST bits.
7. Load the data to be transmitted into the CAN IFn Data (CANIFnDA1, CANIFnDA2, CANIFnDB1,
CANIFnDB2) registers. Byte 0 of the CAN data frame is stored in DATA[7:0] in the CANIFnDA1
register.
8. Program the number of the message object to be transmitted in the MNUM field in the CAN IFn
Command Request (CANIFnCRQ) register.
9. When everything is properly configured, set the TXRQST bit in the CANIFnMCTL register. Once
this bit is set, the message object is available to be transmitted, depending on priority and bus
availability. Note that setting the RMTEN bit in the CANIFnMCTL register can also start message
transmission if a matching remote frame has been received.
17.3.5
Updating a Transmit Message Object
The CPU may update the data bytes of a Transmit Message Object any time via the CAN Interface
Registers and neither the MSGVAL bit in the CANIFnARB2 register nor the TXRQST bits in the
CANIFnMCTL register have to be cleared before the update.
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Even if only some of the data bytes are to be updated, all four bytes of the corresponding
CANIFnDAn/CANIFnDBn register have to be valid before the content of that register is transferred
to the message object. Either the CPU must write all four bytes into the CANIFnDAn/CANIFnDBn
register or the message object is transferred to the CANIFnDAn/CANIFnDBn register before the
CPU writes the new data bytes.
In order to only update the data in a message object, the WRNRD, DATAA and DATAB bits in the
CANIFnMSKn register are set, followed by writing the updated data into CANIFnDA1, CANIFnDA2,
CANIFnDB1, and CANIFnDB2 registers, and then the number of the message object is written to
the MNUM field in the CAN IFn Command Request (CANIFnCRQ) register. To begin transmission
of the new data as soon as possible, set the TXRQST bit in the CANIFnMSKn register.
To prevent the clearing of the TXRQST bit in the CANIFnMCTL register at the end of a transmission
that may already be in progress while the data is updated, the NEWDAT and TXRQST bits have to be
set at the same time in the CANIFnMCTL register. When these bits are set at the same time, NEWDAT
is cleared as soon as the new transmission has started.
17.3.6
Accepting Received Message Objects
When the arbitration and control field (the ID and XTD bits in the CANIFnARB2 and the RMTEN and
DLC[3:0] bits of the CANIFnMCTL register) of an incoming message is completely shifted into
the CAN controller, the message handling capability of the controller starts scanning the message
RAM for a matching valid message object. To scan the message RAM for a matching message
object, the controller uses the acceptance filtering programmed through the mask bits in the
CANIFnMSKn register and enabled using the UMASK bit in the CANIFnMCTL register. Each valid
message object, starting with object 1, is compared with the incoming message to locate a matching
message object in the message RAM. If a match occurs, the scanning is stopped and the message
handler proceeds depending on whether it is a data frame or remote frame that was received.
17.3.7
Receiving a Data Frame
The message handler stores the message from the CAN controller receive shift register into the
matching message object in the message RAM. The data bytes, all arbitration bits, and the DLC bits
are all stored into the corresponding message object. In this manner, the data bytes are connected
with the identifier even if arbitration masks are used. The NEWDAT bit of the CANIFnMCTL register
is set to indicate that new data has been received. The CPU should clear this bit when it reads the
message object to indicate to the controller that the message has been received, and the buffer is
free to receive more messages. If the CAN controller receives a message and the NEWDAT bit is
already set, the MSGLST bit in the CANIFnMCTL register is set to indicate that the previous data
was lost. If the system requires an interrupt on successful reception of a frame, the RXIE bit of the
CANIFnMCTL register should be set. In this case, the INTPND bit of the same register is set, causing
the CANINT register to point to the message object that just received a message. The TXRQST bit
of this message object should be cleared to prevent the transmission of a remote frame.
17.3.8
Receiving a Remote Frame
A remote frame contains no data, but instead specifies which object should be transmitted. When
a remote frame is received, three different configurations of the matching message object have to
be considered:
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Table 17-2. Message Object Configurations
Configuration in CANIFnMCTL
■
■
DIR = 1 (direction = transmit); programmed in the At the reception of a matching remote frame, the TXRQST bit of this
CANIFnARB2 register
message object is set. The rest of the message object remains
unchanged, and the controller automatically transfers the data in
RMTEN = 1 (set the TXRQST bit of the
the message object as soon as possible.
CANIFnMCTL register at reception of the frame
to enable transmission)
■
UMASK = 1 or 0
■
DIR = 1 (direction = transmit); programmed in the At the reception of a matching remote frame, the TXRQST bit of this
CANIFnARB2 register
message object remains unchanged, and the remote frame is
ignored. This remote frame is disabled, the data is not transferred
RMTEN = 0 (do not change the TXRQST bit of the and nothing indicates that the remote frame ever happened.
CANIFnMCTL register at reception of the frame)
■
■
UMASK = 0 (ignore mask in the CANIFnMSKn
register)
■
DIR = 1 (direction = transmit); programmed in the At the reception of a matching remote frame, the TXRQST bit of this
message object is cleared. The arbitration and control field (ID +
CANIFnARB2 register
XTD + RMTEN + DLC) from the shift register is stored into the message
RMTEN = 0 (do not change the TXRQST bit of the object in the message RAM, and the NEWDAT bit of this message
CANIFnMCTL register at reception of the frame) object is set. The data field of the message object remains
unchanged; the remote frame is treated similar to a received data
UMASK = 1 (use mask (MSK, MXTD, and MDIR in
frame. This mode is useful for a remote data request from another
the CANIFnMSKn register) for acceptance filtering)
CAN device for which the TM4C123BH6PGE controller does not
have readily available data. The software must fill the data and
answer the frame manually.
■
■
17.3.9
Description
Receive/Transmit Priority
The receive/transmit priority for the message objects is controlled by the message number. Message
object 1 has the highest priority, while message object 32 has the lowest priority. If more than one
transmission request is pending, the message objects are transmitted in order based on the message
object with the lowest message number. This prioritization is separate from that of the message
identifier which is enforced by the CAN bus. As a result, if message object 1 and message object
2 both have valid messages to be transmitted, message object 1 is always transmitted first regardless
of the message identifier in the message object itself.
17.3.10
Configuring a Receive Message Object
The following steps illustrate how to configure a receive message object.
1. Program the CAN IFn Command Mask (CANIFnCMASK) register as described in the
“Configuring a Transmit Message Object” on page 1070 section, except that the WRNRD bit is set
to specify a write to the message RAM.
2. Program the CANIFnMSK1and CANIFnMSK2 registers as described in the “Configuring a
Transmit Message Object” on page 1070 section to configure which bits are used for acceptance
filtering. Note that in order for these bits to be used for acceptance filtering, they must be enabled
by setting the UMASK bit in the CANIFnMCTL register.
3. In the CANIFnMSK2 register, use the MSK[12:0] bits to specify which of the bits in the 29-bit
or 11-bit message identifier are used for acceptance filtering. Note that MSK[12:0] are used
for bits [28:16] of the 29-bit message identifier; whereas MSK[12:2] are used for bits [10:0] of
the 11-bit message identifier. Use the MXTD and MDIR bits to specify whether to use XTD and
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DIR for acceptance filtering. A value of 0x00 enables all messages to pass through the
acceptance filtering. Also note that in order for these bits to be used for acceptance filtering,
they must be enabled by setting the UMASK bit in the CANIFnMCTL register.
4. Program the CANIFnARB1 and CANIFnARB2 registers as described in the “Configuring a
Transmit Message Object” on page 1070 section to program XTD and ID bits for the message
identifier to be received; set the MSGVAL bit to indicate a valid message; and clear the DIR bit
to specify receive.
5. In the CANIFnMCTL register:
■ Optionally set the UMASK bit to enable the mask (MSK, MXTD, and MDIR specified in the
CANIFnMSK1 and CANIFnMSK2 registers) for acceptance filtering
■ Optionally set the RXIE bit to enable the INTPND bit to be set after a successful reception
■ Clear the RMTEN bit to leave the TXRQST bit unchanged
■ Set the EOB bit for a single message object
■ Configure the DLC[3:0] field to specify the size of the data frame
Take care during this configuration not to set the NEWDAT, MSGLST, INTPND or TXRQST bits.
6. Program the number of the message object to be received in the MNUM field in the CAN IFn
Command Request (CANIFnCRQ) register. Reception of the message object begins as soon
as a matching frame is available on the CAN bus.
When the message handler stores a data frame in the message object, it stores the received Data
Length Code and eight data bytes in the CANIFnDA1, CANIFnDA2, CANIFnDB1, and CANIFnDB2
register. Byte 0 of the CAN data frame is stored in DATA[7:0] in the CANIFnDA1 register. If the
Data Length Code is less than 8, the remaining bytes of the message object are overwritten by
unspecified values.
The CAN mask registers can be used to allow groups of data frames to be received by a message
object. The CAN mask registers, CANIFnMSKn, configure which groups of frames are received by
a message object. The UMASK bit in the CANIFnMCTL register enables the MSK bits in the
CANIFnMSKn register to filter which frames are received. The MXTD bit in the CANIFnMSK2 register
should be set if only 29-bit extended identifiers are expected by this message object.
17.3.11
Handling of Received Message Objects
The CPU may read a received message any time via the CAN Interface registers because the data
consistency is guaranteed by the message handler state machine.
Typically, the CPU first writes 0x007F to the CANIFnCMSK register and then writes the number of
the message object to the CANIFnCRQ register. That combination transfers the whole received
message from the message RAM into the Message Buffer registers (CANIFnMSKn, CANIFnARBn,
and CANIFnMCTL). Additionally, the NEWDAT and INTPND bits are cleared in the message RAM,
acknowledging that the message has been read and clearing the pending interrupt generated by
this message object.
If the message object uses masks for acceptance filtering, the CANIFnARBn registers show the
full, unmasked ID for the received message.
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The NEWDAT bit in the CANIFnMCTL register shows whether a new message has been received
since the last time this message object was read. The MSGLST bit in the CANIFnMCTL register
shows whether more than one message has been received since the last time this message object
was read. MSGLST is not automatically cleared, and should be cleared by software after reading its
status.
Using a remote frame, the CPU may request new data from another CAN node on the CAN bus.
Setting the TXRQST bit of a receive object causes the transmission of a remote frame with the receive
object's identifier. This remote frame triggers the other CAN node to start the transmission of the
matching data frame. If the matching data frame is received before the remote frame could be
transmitted, the TXRQST bit is automatically reset. This prevents the possible loss of data when the
other device on the CAN bus has already transmitted the data slightly earlier than expected.
17.3.11.1 Configuration of a FIFO Buffer
With the exception of the EOB bit in the CANIFnMCTL register, the configuration of receive message
objects belonging to a FIFO buffer is the same as the configuration of a single receive message
object (see “Configuring a Receive Message Object” on page 1073). To concatenate two or more
message objects into a FIFO buffer, the identifiers and masks (if used) of these message objects
have to be programmed to matching values. Due to the implicit priority of the message objects, the
message object with the lowest message object number is the first message object in a FIFO buffer.
The EOB bit of all message objects of a FIFO buffer except the last one must be cleared. The EOB
bit of the last message object of a FIFO buffer is set, indicating it is the last entry in the buffer.
17.3.11.2 Reception of Messages with FIFO Buffers
Received messages with identifiers matching to a FIFO buffer are stored starting with the message
object with the lowest message number. When a message is stored into a message object of a
FIFO buffer, the NEWDAT of the CANIFnMCTL register bit of this message object is set. By setting
NEWDAT while EOB is clear, the message object is locked and cannot be written to by the message
handler until the CPU has cleared the NEWDAT bit. Messages are stored into a FIFO buffer until the
last message object of this FIFO buffer is reached. Until all of the preceding message objects have
been released by clearing the NEWDAT bit, all further messages for this FIFO buffer are written into
the last message object of the FIFO buffer and therefore overwrite previous messages.
17.3.11.3 Reading from a FIFO Buffer
When the CPU transfers the contents of a message object from a FIFO buffer by writing its number
to the CANIFnCRQ register, the TXRQST and CLRINTPND bits in the CANIFnCMSK register should
be set such that the NEWDAT and INTPEND bits in the CANIFnMCTL register are cleared after the
read. The values of these bits in the CANIFnMCTL register always reflect the status of the message
object before the bits are cleared. To assure the correct function of a FIFO buffer, the CPU should
read out the message objects starting with the message object with the lowest message number.
When reading from the FIFO buffer, the user should be aware that a new received message is
placed in the message object with the lowest message number for which the NEWDAT bit of the
CANIFnMCTL register is clear. As a result, the order of the received messages in the FIFO is not
guaranteed. Figure 17-3 on page 1076 shows how a set of message objects which are concatenated
to a FIFO Buffer can be handled by the CPU.
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Figure 17-3. Message Objects in a FIFO Buffer
START
Message Interrupt
Read Interrupt Pointer
0x0000
Case Interrupt Pointer
else
0x8000
END
Status Change
Interrupt Handling
MNUM = Interrupt Pointer
Write MNUM to IFn Command Request
(Read Message to IFn Registers,
Reset NEWDAT = 0,
Reset INTPND = 0
Read IFn Message Control
Yes
No
NEWDAT = 1
Read Data from IFn Data A,B
EOB = 1
Yes
No
MNUM = MNUM + 1
17.3.12
Handling of Interrupts
If several interrupts are pending, the CAN Interrupt (CANINT) register points to the pending interrupt
with the highest priority, disregarding their chronological order. The status interrupt has the highest
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priority. Among the message interrupts, the message object's interrupt with the lowest message
number has the highest priority. A message interrupt is cleared by clearing the message object's
INTPND bit in the CANIFnMCTL register or by reading the CAN Status (CANSTS) register. The
status Interrupt is cleared by reading the CANSTS register.
The interrupt identifier INTID in the CANINT register indicates the cause of the interrupt. When no
interrupt is pending, the register reads as 0x0000. If the value of the INTID field is different from 0,
then an interrupt is pending. If the IE bit is set in the CANCTL register, the interrupt line to the
interrupt controller is active. The interrupt line remains active until the INTID field is 0, meaning
that all interrupt sources have been cleared (the cause of the interrupt is reset), or until IE is cleared,
which disables interrupts from the CAN controller.
The INTID field of the CANINT register points to the pending message interrupt with the highest
interrupt priority. The SIE bit in the CANCTL register controls whether a change of the RXOK, TXOK,
and LEC bits in the CANSTS register can cause an interrupt. The EIE bit in the CANCTLregister
controls whether a change of the BOFF and EWARN bits in the CANSTS register can cause an
interrupt. The IE bit in the CANCTL register controls whether any interrupt from the CAN controller
actually generates an interrupt to the interrupt controller. The CANINT register is updated even
when the IE bit in the CANCTL register is clear, but the interrupt is not indicated to the CPU.
A value of 0x8000 in the CANINT register indicates that an interrupt is pending because the CAN
module has updated, but not necessarily changed, the CANSTS register, indicating that either an
error or status interrupt has been generated. A write access to the CANSTS register can clear the
RXOK, TXOK, and LEC bits in that same register; however, the only way to clear the source of a
status interrupt is to read the CANSTS register.
The source of an interrupt can be determined in two ways during interrupt handling. The first is to
read the INTID bit in the CANINT register to determine the highest priority interrupt that is pending,
and the second is to read the CAN Message Interrupt Pending (CANMSGnINT) register to see
all of the message objects that have pending interrupts.
An interrupt service routine reading the message that is the source of the interrupt may read the
message and clear the message object's INTPND bit at the same time by setting the CLRINTPND
bit in the CANIFnCMSK register. Once the INTPND bit has been cleared, the CANINT register
contains the message number for the next message object with a pending interrupt.
17.3.13
Test Mode
A Test Mode is provided which allows various diagnostics to be performed. Test Mode is entered
by setting the TEST bit in the CANCTL register. Once in Test Mode, the TX[1:0], LBACK, SILENT
and BASIC bits in the CAN Test (CANTST) register can be used to put the CAN controller into the
various diagnostic modes. The RX bit in the CANTST register allows monitoring of the CANnRX
signal. All CANTST register functions are disabled when the TEST bit is cleared.
17.3.13.1 Silent Mode
Silent Mode can be used to analyze the traffic on a CAN bus without affecting it by the transmission
of dominant bits (Acknowledge Bits, Error Frames). The CAN Controller is put in Silent Mode setting
the SILENT bit in the CANTST register. In Silent Mode, the CAN controller is able to receive valid
data frames and valid remote frames, but it sends only recessive bits on the CAN bus and cannot
start a transmission. If the CAN Controller is required to send a dominant bit (ACK bit, overload flag,
or active error flag), the bit is rerouted internally so that the CAN Controller monitors this dominant
bit, although the CAN bus remains in recessive state.
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17.3.13.2 Loopback Mode
Loopback mode is useful for self-test functions. In Loopback Mode, the CAN Controller internally
routes the CANnTX signal on to the CANnRX signal and treats its own transmitted messages as
received messages and stores them (if they pass acceptance filtering) into the message buffer. The
CAN Controller is put in Loopback Mode by setting the LBACK bit in the CANTST register. To be
independent from external stimulation, the CAN Controller ignores acknowledge errors (a recessive
bit sampled in the acknowledge slot of a data/remote frame) in Loopback Mode. The actual value
of the CANnRX signal is disregarded by the CAN Controller. The transmitted messages can be
monitored on the CANnTX signal.
17.3.13.3 Loopback Combined with Silent Mode
Loopback Mode and Silent Mode can be combined to allow the CAN Controller to be tested without
affecting a running CAN system connected to the CANnTX and CANnRX signals. In this mode, the
CANnRX signal is disconnected from the CAN Controller and the CANnTX signal is held recessive.
This mode is enabled by setting both the LBACK and SILENT bits in the CANTST register.
17.3.13.4 Basic Mode
Basic Mode allows the CAN Controller to be operated without the Message RAM. In Basic Mode,
The CANIF1 registers are used as the transmit buffer. The transmission of the contents of the IF1
registers is requested by setting the BUSY bit of the CANIF1CRQ register. The CANIF1 registers
are locked while the BUSY bit is set. The BUSY bit indicates that a transmission is pending. As soon
the CAN bus is idle, the CANIF1 registers are loaded into the shift register of the CAN Controller
and transmission is started. When the transmission has completed, the BUSY bit is cleared and the
locked CANIF1 registers are released. A pending transmission can be aborted at any time by clearing
the BUSY bit in the CANIF1CRQ register while the CANIF1 registers are locked. If the CPU has
cleared the BUSY bit, a possible retransmission in case of lost arbitration or an error is disabled.
The CANIF2 Registers are used as a receive buffer. After the reception of a message, the contents
of the shift register are stored in the CANIF2 registers, without any acceptance filtering. Additionally,
the actual contents of the shift register can be monitored during the message transfer. Each time a
read message object is initiated by setting the BUSY bit of the CANIF2CRQ register, the contents
of the shift register are stored into the CANIF2 registers.
In Basic Mode, all message-object-related control and status bits and of the control bits of the
CANIFnCMSK registers are not evaluated. The message number of the CANIFnCRQ registers is
also not evaluated. In the CANIF2MCTL register, the NEWDAT and MSGLST bits retain their function,
the DLC[3:0] field shows the received DLC, the other control bits are cleared.
Basic Mode is enabled by setting the BASIC bit in the CANTST register.
17.3.13.5 Transmit Control
Software can directly override control of the CANnTX signal in four different ways.
■ CANnTX is controlled by the CAN Controller
■ The sample point is driven on the CANnTX signal to monitor the bit timing
■ CANnTX drives a low value
■ CANnTX drives a high value
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The last two functions, combined with the readable CAN receive pin CANnRX, can be used to check
the physical layer of the CAN bus.
The Transmit Control function is enabled by programming the TX[1:0] field in the CANTST register.
The three test functions for the CANnTX signal interfere with all CAN protocol functions. TX[1:0]
must be cleared when CAN message transfer or Loopback Mode, Silent Mode, or Basic Mode are
selected.
17.3.14
Bit Timing Configuration Error Considerations
Even if minor errors in the configuration of the CAN bit timing do not result in immediate failure, the
performance of a CAN network can be reduced significantly. In many cases, the CAN bit
synchronization amends a faulty configuration of the CAN bit timing to such a degree that only
occasionally an error frame is generated. In the case of arbitration, however, when two or more
CAN nodes simultaneously try to transmit a frame, a misplaced sample point may cause one of the
transmitters to become error passive. The analysis of such sporadic errors requires a detailed
knowledge of the CAN bit synchronization inside a CAN node and of the CAN nodes' interaction on
the CAN bus.
17.3.15
Bit Time and Bit Rate
The CAN system supports bit rates in the range of lower than 1 Kbps up to 1000 Kbps. Each member
of the CAN network has its own clock generator. The timing parameter of the bit time can be
configured individually for each CAN node, creating a common bit rate even though the CAN nodes'
oscillator periods may be different.
Because of small variations in frequency caused by changes in temperature or voltage and by
deteriorating components, these oscillators are not absolutely stable. As long as the variations
remain inside a specific oscillator's tolerance range, the CAN nodes are able to compensate for the
different bit rates by periodically resynchronizing to the bit stream.
According to the CAN specification, the bit time is divided into four segments (see Figure
17-4 on page 1080): the Synchronization Segment, the Propagation Time Segment, the Phase Buffer
Segment 1, and the Phase Buffer Segment 2. Each segment consists of a specific, programmable
number of time quanta (see Table 17-3 on page 1080). The length of the time quantum (tq), which is
the basic time unit of the bit time, is defined by the CAN controller's input clock (fsys) and the Baud
Rate Prescaler (BRP):
tq = BRP / fsys
The fsys input clock is the system clock frequency as configured by the RCC or RCC2 registers
(see page 248 or page 255).
The Synchronization Segment Sync is that part of the bit time where edges of the CAN bus level
are expected to occur; the distance between an edge that occurs outside of Sync and the Sync is
called the phase error of that edge.
The Propagation Time Segment Prop is intended to compensate for the physical delay times within
the CAN network.
The Phase Buffer Segments Phase1 and Phase2 surround the Sample Point.
The (Re-)Synchronization Jump Width (SJW) defines how far a resynchronization may move the
Sample Point inside the limits defined by the Phase Buffer Segments to compensate for edge phase
errors.
A given bit rate may be met by different bit-time configurations, but for the proper function of the
CAN network, the physical delay times and the oscillator's tolerance range have to be considered.
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Figure 17-4. CAN Bit Time
Nominal CAN Bit Time
a
b
TSEG1
Sync
Prop
TSEG2
Phase1
c
1 Time
Quantum
q)
(tq
Phase2
Sample
Point
a. TSEG1 = Prop + Phase1
b. TSEG2 = Phase2
c. Phase1 = Phase2 or Phase1 + 1 = Phase2
a
Table 17-3. CAN Protocol Ranges
Parameter
Range
Remark
BRP
[1 .. 64]
Defines the length of the time quantum tq. The CANBRPE register can
be used to extend the range to 1024.
Sync
1 tq
Fixed length, synchronization of bus input to system clock
Prop
[1 .. 8] tq
Compensates for the physical delay times
Phase1
[1 .. 8] tq
May be lengthened temporarily by synchronization
Phase2
[1 .. 8] tq
May be shortened temporarily by synchronization
SJW
[1 .. 4] tq
May not be longer than either Phase Buffer Segment
a. This table describes the minimum programmable ranges required by the CAN protocol.
The bit timing configuration is programmed in two register bytes in the CANBIT register. In the
CANBIT register, the four components TSEG2, TSEG1, SJW, and BRP have to be programmed to a
numerical value that is one less than its functional value; so instead of values in the range of [1..n],
values in the range of [0..n-1] are programmed. That way, for example, SJW (functional range of
[1..4]) is represented by only two bits in the SJW bit field. Table 17-4 shows the relationship between
the CANBIT register values and the parameters.
Table 17-4. CANBIT Register Values
CANBIT Register Field
Setting
TSEG2
Phase2 - 1
TSEG1
Prop + Phase1 - 1
SJW
SJW - 1
BRP
BRP
Therefore, the length of the bit time is (programmed values):
[TSEG1 + TSEG2 + 3] × tq
or (functional values):
[Sync + Prop + Phase1 + Phase2] × tq
The data in the CANBIT register is the configuration input of the CAN protocol controller. The baud
rate prescaler (configured by the BRP field) defines the length of the time quantum, the basic time
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unit of the bit time; the bit timing logic (configured by TSEG1, TSEG2, and SJW) defines the number
of time quanta in the bit time.
The processing of the bit time, the calculation of the position of the sample point, and occasional
synchronizations are controlled by the CAN controller and are evaluated once per time quantum.
The CAN controller translates messages to and from frames. In addition, the controller generates
and discards the enclosing fixed format bits, inserts and extracts stuff bits, calculates and checks
the CRC code, performs the error management, and decides which type of synchronization is to be
used. The bit value is received or transmitted at the sample point. The information processing time
(IPT) is the time after the sample point needed to calculate the next bit to be transmitted on the CAN
bus. The IPT includes any of the following: retrieving the next data bit, handling a CRC bit, determining
if bit stuffing is required, generating an error flag or simply going idle.
The IPT is application-specific but may not be longer than 2 tq; the CAN's IPT is 0 tq. Its length is
the lower limit of the programmed length of Phase2. In case of synchronization, Phase2 may be
shortened to a value less than IPT, which does not affect bus timing.
17.3.16
Calculating the Bit Timing Parameters
Usually, the calculation of the bit timing configuration starts with a required bit rate or bit time. The
resulting bit time (1/bit rate) must be an integer multiple of the system clock period.
The bit time may consist of 4 to 25 time quanta. Several combinations may lead to the required bit
time, allowing iterations of the following steps.
The first part of the bit time to be defined is Prop. Its length depends on the delay times measured
in the system. A maximum bus length as well as a maximum node delay has to be defined for
expandable CAN bus systems. The resulting time for Prop is converted into time quanta (rounded
up to the nearest integer multiple of tq).
Sync is 1 tq long (fixed), which leaves (bit time - Prop - 1) tq for the two Phase Buffer Segments. If
the number of remaining tq is even, the Phase Buffer Segments have the same length, that is,
Phase2 = Phase1, else Phase2 = Phase1 + 1.
The minimum nominal length of Phase2 has to be regarded as well. Phase2 may not be shorter
than the CAN controller's Information Processing Time, which is, depending on the actual
implementation, in the range of [0..2] tq.
The length of the synchronization jump width is set to the least of 4, Phase1 or Phase2.
The oscillator tolerance range necessary for the resulting configuration is calculated by the formula
given below:
(1 − df ) × fnom ≤ fosc ≤ (1 + df ) × fnom
where:
df
≤
(Phase _ seg1, Phase _ seg2) min
2 × (13 × tbit − Phase _ Seg 2)
■ df = Maximum tolerance of oscillator frequency
■ fosc
Actual=oscillator
df =max
2 × dffrequency
× fnom
■ fnom = Nominal oscillator frequency
Maximum frequency tolerance must take into account the following formulas:
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− )df
× fnom
≤ fosc
+ )df
× fnom
(1 −(1df
× )fnom
≤ fosc
≤ (1≤ +(1df
× )fnom
(Phase
_ seg
1, Phase
_ seg
2) min
(Phase
_ seg
1, Phase
_ seg
2) min
df df
≤ ≤ 2 × (13 × tbit − Phase _ Seg 2)
2 × (13 × tbit − Phase _ Seg 2)
× df
× fnom
df df
maxmax
= 2=× 2df
× fnom
where:
■ Phase1 and Phase2 are from Table 17-3 on page 1080
■ tbit = Bit Time
■ dfmax = Maximum difference between two oscillators
If more than one configuration is possible, that configuration allowing the highest oscillator tolerance
range should be chosen.
CAN nodes with different system clocks require different configurations to come to the same bit
rate. The calculation of the propagation time in the CAN network, based on the nodes with the
longest delay times, is done once for the whole network.
The CAN system's oscillator tolerance range is limited by the node with the lowest tolerance range.
The calculation may show that bus length or bit rate have to be decreased or that the oscillator
frequencies' stability has to be increased in order to find a protocol-compliant configuration of the
CAN bit timing.
17.3.16.1 Example for Bit Timing at High Baud Rate
In this example, the frequency of CAN clock is 25 MHz, and the bit rate is 1 Mbps.
bit time = 1 µs = n * tq = 5 *
tq = 200 ns
tq = (Baud rate Prescaler)/CAN
Baud rate Prescaler = tq * CAN
Baud rate Prescaler = 200E-9 *
tq
Clock
Clock
25E6 = 5
tSync = 1 * tq = 200 ns
\\fixed at 1 time quanta
delay
delay
delay
tProp
\\400 is next integer multiple of tq
of bus driver 50 ns
of receiver circuit 30 ns
of bus line (40m) 220 ns
400 ns = 2 * tq
bit time = tSync +
bit time = tSync +
tPhase 1 + tPhase2
tPhase 1 + tPhase2
tPhase 1 + tPhase2
tPhase1 = 1 * tq
tPhase2 = 1 * tq
tTSeg1 + tTSeg2 = 5 * tq
tProp + tPhase 1 + tPhase2
= bit time - tSync - tProp
= (5 * tq) - (1 * tq) - (2 * tq)
= 2 * tq
\\tPhase2 = tPhase1
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tTSeg1 = tProp + tPhase1
tTSeg1 = (2 * tq) + (1 * tq)
tTSeg1 = 3 * tq
tTSeg2 = tPhase2
tTSeg2 = (Information Processing Time + 1) * tq
tTSeg2 = 1 * tq
\\Assumes IPT=0
tSJW = 1 * tq
\\Least of 4, Phase1 and Phase2
In the above example, the bit field values for the CANBIT register are:
= TSeg2 -1
TSEG2
= 1-1
=0
= TSeg1 -1
TSEG1
= 3-1
=2
= SJW -1
SJW
= 1-1
=0
= Baud rate prescaler - 1
BRP
= 5-1
=4
The final value programmed into the CANBIT register = 0x0204.
17.3.16.2 Example for Bit Timing at Low Baud Rate
In this example, the frequency of the CAN clock is 50 MHz, and the bit rate is 100 Kbps.
bit time = 10 µs = n * tq = 10 * tq
tq = 1 µs
tq = (Baud rate Prescaler)/CAN Clock
Baud rate Prescaler = tq * CAN Clock
Baud rate Prescaler = 1E-6 * 50E6 = 50
tSync = 1 * tq = 1 µs
\\fixed at 1 time quanta
delay
delay
delay
tProp
\\1 µs is next integer multiple of tq
of bus driver 200 ns
of receiver circuit 80 ns
of bus line (40m) 220 ns
1 µs = 1 * tq
bit time = tSync +
bit time = tSync +
tPhase 1 + tPhase2
tPhase 1 + tPhase2
tPhase 1 + tPhase2
tPhase1 = 4 * tq
tPhase2 = 4 * tq
tTSeg1 + tTSeg2 = 10 * tq
tProp + tPhase 1 + tPhase2
= bit time - tSync - tProp
= (10 * tq) - (1 * tq) - (1 * tq)
= 8 * tq
\\tPhase1 = tPhase2
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tTSeg1
tTSeg1
tTSeg1
tTSeg2
tTSeg2
tTSeg2
=
=
=
=
=
=
tProp + tPhase1
(1 * tq) + (4 * tq)
5 * tq
tPhase2
(Information Processing Time + 4) × tq
4 * tq
\\Assumes IPT=0
tSJW = 4 * tq
\\Least of 4, Phase1, and Phase2
= TSeg2 -1
TSEG2
= 4-1
=3
= TSeg1 -1
TSEG1
= 5-1
=4
= SJW -1
SJW
= 4-1
=3
= Baud rate prescaler - 1
BRP
= 50-1
=49
The final value programmed into the CANBIT register = 0x34F1.
17.4
Register Map
Table 17-5 on page 1084 lists the registers. All addresses given are relative to the CAN base address
of:
■ CAN0: 0x4004.0000
■ CAN1: 0x4004.1000
Note that the CAN controller clock must be enabled before the registers can be programmed (see
page 346). There must be a delay of 3 system clocks after the CAN module clock is enabled before
any CAN module registers are accessed.
Table 17-5. CAN Register Map
Type
Reset
Description
See
page
CANCTL
RW
0x0000.0001
CAN Control
1087
0x004
CANSTS
RW
0x0000.0000
CAN Status
1089
0x008
CANERR
RO
0x0000.0000
CAN Error Counter
1092
0x00C
CANBIT
RW
0x0000.2301
CAN Bit Timing
1093
0x010
CANINT
RO
0x0000.0000
CAN Interrupt
1094
0x014
CANTST
RW
0x0000.0000
CAN Test
1095
0x018
CANBRPE
RW
0x0000.0000
CAN Baud Rate Prescaler Extension
1097
0x020
CANIF1CRQ
RW
0x0000.0001
CAN IF1 Command Request
1098
Offset
Name
0x000
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Table 17-5. CAN Register Map (continued)
Description
See
page
0x0000.0000
CAN IF1 Command Mask
1099
RW
0x0000.FFFF
CAN IF1 Mask 1
1102
CANIF1MSK2
RW
0x0000.FFFF
CAN IF1 Mask 2
1103
0x030
CANIF1ARB1
RW
0x0000.0000
CAN IF1 Arbitration 1
1105
0x034
CANIF1ARB2
RW
0x0000.0000
CAN IF1 Arbitration 2
1106
0x038
CANIF1MCTL
RW
0x0000.0000
CAN IF1 Message Control
1108
0x03C
CANIF1DA1
RW
0x0000.0000
CAN IF1 Data A1
1111
0x040
CANIF1DA2
RW
0x0000.0000
CAN IF1 Data A2
1111
0x044
CANIF1DB1
RW
0x0000.0000
CAN IF1 Data B1
1111
0x048
CANIF1DB2
RW
0x0000.0000
CAN IF1 Data B2
1111
0x080
CANIF2CRQ
RW
0x0000.0001
CAN IF2 Command Request
1098
0x084
CANIF2CMSK
RW
0x0000.0000
CAN IF2 Command Mask
1099
0x088
CANIF2MSK1
RW
0x0000.FFFF
CAN IF2 Mask 1
1102
0x08C
CANIF2MSK2
RW
0x0000.FFFF
CAN IF2 Mask 2
1103
0x090
CANIF2ARB1
RW
0x0000.0000
CAN IF2 Arbitration 1
1105
0x094
CANIF2ARB2
RW
0x0000.0000
CAN IF2 Arbitration 2
1106
0x098
CANIF2MCTL
RW
0x0000.0000
CAN IF2 Message Control
1108
0x09C
CANIF2DA1
RW
0x0000.0000
CAN IF2 Data A1
1111
0x0A0
CANIF2DA2
RW
0x0000.0000
CAN IF2 Data A2
1111
0x0A4
CANIF2DB1
RW
0x0000.0000
CAN IF2 Data B1
1111
0x0A8
CANIF2DB2
RW
0x0000.0000
CAN IF2 Data B2
1111
0x100
CANTXRQ1
RO
0x0000.0000
CAN Transmission Request 1
1112
0x104
CANTXRQ2
RO
0x0000.0000
CAN Transmission Request 2
1112
0x120
CANNWDA1
RO
0x0000.0000
CAN New Data 1
1113
0x124
CANNWDA2
RO
0x0000.0000
CAN New Data 2
1113
0x140
CANMSG1INT
RO
0x0000.0000
CAN Message 1 Interrupt Pending
1114
0x144
CANMSG2INT
RO
0x0000.0000
CAN Message 2 Interrupt Pending
1114
0x160
CANMSG1VAL
RO
0x0000.0000
CAN Message 1 Valid
1115
0x164
CANMSG2VAL
RO
0x0000.0000
CAN Message 2 Valid
1115
Offset
Name
Type
Reset
0x024
CANIF1CMSK
RW
0x028
CANIF1MSK1
0x02C
17.5
CAN Register Descriptions
The remainder of this section lists and describes the CAN registers, in numerical order by address
offset. There are two sets of Interface Registers that are used to access the Message Objects in
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the Message RAM: CANIF1x and CANIF2x. The function of the two sets are identical and are used
to queue transactions.
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Register 1: CAN Control (CANCTL), offset 0x000
This control register initializes the module and enables test mode and interrupts.
The bus-off recovery sequence (see CAN Specification Rev. 2.0) cannot be shortened by setting
or clearing INIT. If the device goes bus-off, it sets INIT, stopping all bus activities. Once INIT
has been cleared by the CPU, the device then waits for 129 occurrences of Bus Idle (129 * 11
consecutive High bits) before resuming normal operations. At the end of the bus-off recovery
sequence, the Error Management Counters are reset.
During the waiting time after INIT is cleared, each time a sequence of 11 High bits has been
monitored, a BITERROR0 code is written to the CANSTS register (the LEC field = 0x5), enabling
the CPU to readily check whether the CAN bus is stuck Low or continuously disturbed, and to monitor
the proceeding of the bus-off recovery sequence.
CAN Control (CANCTL)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
Offset 0x000
Type RW, reset 0x0000.0001
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
TEST
CCE
DAR
reserved
EIE
SIE
IE
INIT
RW
0
RW
0
RW
0
RO
0
RW
0
RW
0
RW
0
RW
1
reserved
Type
Reset
reserved
Type
Reset
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7
TEST
RW
0
6
5
CCE
DAR
RW
RW
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Test Mode Enable
Value
Description
0
The CAN controller is operating normally.
1
The CAN controller is in test mode.
Configuration Change Enable
Value
Description
0
Write accesses to the CANBIT register are not allowed.
1
Write accesses to the CANBIT register are allowed if the
INIT bit is 1.
Disable Automatic-Retransmission
Value
Description
0
Auto-retransmission of disturbed messages is enabled.
1
Auto-retransmission is disabled.
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Bit/Field
Name
Type
Reset
4
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
EIE
RW
0
Error Interrupt Enable
2
1
0
SIE
IE
INIT
RW
RW
RW
0
0
1
Description
Value
Description
0
No error status interrupt is generated.
1
A change in the BOFF or EWARN bits in the CANSTS
register generates an interrupt.
Status Interrupt Enable
Value
Description
0
No status interrupt is generated.
1
An interrupt is generated when a message has successfully
been transmitted or received, or a CAN bus error has been
detected. A change in the TXOK, RXOK or LEC bits in the
CANSTS register generates an interrupt.
CAN Interrupt Enable
Value
Description
0
Interrupts disabled.
1
Interrupts enabled.
Initialization
Value
Description
0
Normal operation.
1
Initialization started.
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Register 2: CAN Status (CANSTS), offset 0x004
Important: This register is read-sensitive. See the register description for details.
The status register contains information for interrupt servicing such as Bus-Off, error count threshold,
and error types.
The LEC field holds the code that indicates the type of the last error to occur on the CAN bus. This
field is cleared when a message has been transferred (reception or transmission) without error. The
unused error code 0x7 may be written by the CPU to manually set this field to an invalid error so
that it can be checked for a change later.
An error interrupt is generated by the BOFF and EWARN bits, and a status interrupt is generated by
the RXOK, TXOK, and LEC bits, if the corresponding enable bits in the CAN Control (CANCTL)
register are set. A change of the EPASS bit or a write to the RXOK, TXOK, or LEC bits does not
generate an interrupt.
Reading the CAN Status (CANSTS) register clears the CAN Interrupt (CANINT) register, if it is
pending.
CAN Status (CANSTS)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
Offset 0x004
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
2
1
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7
BOFF
RO
0
6
EWARN
RO
0
RO
0
7
6
5
4
3
BOFF
EWARN
EPASS
RXOK
TXOK
RO
0
RO
0
RO
0
RW
0
RW
0
RO
0
LEC
RW
0
RW
0
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Bus-Off Status
Value
Description
0
The CAN controller is not in bus-off state.
1
The CAN controller is in bus-off state.
Warning Status
Value
Description
0
Both error counters are below the error warning limit of
96.
1
At least one of the error counters has reached the error
warning limit of 96.
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Bit/Field
Name
Type
Reset
5
EPASS
RO
0
4
RXOK
RW
0
Description
Error Passive
Value
Description
0
The CAN module is in the Error Active state, that is, the
receive or transmit error count is less than or equal to 127.
1
The CAN module is in the Error Passive state, that is, the
receive or transmit error count is greater than 127.
Received a Message Successfully
Value
Description
0
Since this bit was last cleared, no message has been
successfully received.
1
Since this bit was last cleared, a message has been
successfully received, independent of the result of the
acceptance filtering.
This bit must be cleared by writing a 0 to it.
3
TXOK
RW
0
Transmitted a Message Successfully
Value
Description
0
Since this bit was last cleared, no message has been
successfully transmitted.
1
Since this bit was last cleared, a message has been
successfully transmitted error-free and acknowledged by
at least one other node.
This bit must be cleared by writing a 0 to it.
1090
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Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Bit/Field
Name
Type
Reset
2:0
LEC
RW
0x0
Description
Last Error Code
This is the type of the last error to occur on the CAN bus.
Value
Description
0x0
No Error
0x1
Stuff Error
More than 5 equal bits in a sequence have occurred in a part
of a received message where this is not allowed.
0x2
Format Error
A fixed format part of the received frame has the wrong
format.
0x3
ACK Error
The message transmitted was not acknowledged by another
node.
0x4
Bit 1 Error
When a message is transmitted, the CAN controller monitors
the data lines to detect any conflicts. When the arbitration
field is transmitted, data conflicts are a part of the arbitration
protocol. When other frame fields are transmitted, data
conflicts are considered errors.
A Bit 1 Error indicates that the device wanted to send a High
level (logical 1) but the monitored bus value was Low (logical
0).
0x5
Bit 0 Error
A Bit 0 Error indicates that the device wanted to send a Low
level (logical 0), but the monitored bus value was High (logical
1).
During bus-off recovery, this status is set each time a
sequence of 11 High bits has been monitored. By checking
for this status, software can monitor the proceeding of the
bus-off recovery sequence without any disturbances to the
bus.
0x6
CRC Error
The CRC checksum was incorrect in the received message,
indicating that the calculated value received did not match
the calculated CRC of the data.
0x7
No Event
When the LEC bit shows this value, no CAN bus event was
detected since this value was written to the LEC field.
June 12, 2014
1091
Texas Instruments-Production Data
Controller Area Network (CAN) Module
Register 3: CAN Error Counter (CANERR), offset 0x008
This register contains the error counter values, which can be used to analyze the cause of an error.
CAN Error Counter (CANERR)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
Offset 0x008
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RP
Type
Reset
RO
0
REC
TEC
RO
0
Bit/Field
Name
Type
Reset
31:16
reserved
RO
0x0000
15
RP
RO
0
14:8
REC
RO
0x00
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Received Error Passive
Value
Description
0
The Receive Error counter is below the Error Passive
level (127 or less).
1
The Receive Error counter has reached the Error Passive
level (128 or greater).
Receive Error Counter
This field contains the state of the receiver error counter (0 to 127).
7:0
TEC
RO
0x00
Transmit Error Counter
This field contains the state of the transmit error counter (0 to 255).
1092
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Register 4: CAN Bit Timing (CANBIT), offset 0x00C
This register is used to program the bit width and bit quantum. Values are programmed to the system
clock frequency. This register is write-enabled by setting the CCE and INIT bits in the CANCTL
register. See “Bit Time and Bit Rate” on page 1079 for more information.
CAN Bit Timing (CANBIT)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
Offset 0x00C
Type RW, reset 0x0000.2301
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RW
0
RW
0
RW
0
RW
1
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RW
1
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
1
reserved
Type
Reset
reserved
Type
Reset
RO
0
TSEG2
RW
0
RW
1
TSEG1
Bit/Field
Name
Type
Reset
31:15
reserved
RO
0x0000
14:12
TSEG2
RW
0x2
SJW
BRP
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Time Segment after Sample Point
0x00-0x07: The actual interpretation by the hardware of this value is
such that one more than the value programmed here is used.
So, for example, the reset value of 0x2 means that 3 (2+1) bit time
quanta are defined for Phase2 (see Figure 17-4 on page 1080). The bit
time quanta is defined by the BRP field.
11:8
TSEG1
RW
0x3
Time Segment Before Sample Point
0x00-0x0F: The actual interpretation by the hardware of this value is
such that one more than the value programmed here is used.
So, for example, the reset value of 0x3 means that 4 (3+1) bit time
quanta are defined for Phase1 (see Figure 17-4 on page 1080). The bit
time quanta is defined by the BRP field.
7:6
SJW
RW
0x0
(Re)Synchronization Jump Width
0x00-0x03: The actual interpretation by the hardware of this value is
such that one more than the value programmed here is used.
During the start of frame (SOF), if the CAN controller detects a phase
error (misalignment), it can adjust the length of TSEG2 or TSEG1 by the
value in SJW. So the reset value of 0 adjusts the length by 1 bit time
quanta.
5:0
BRP
RW
0x1
Baud Rate Prescaler
The value by which the oscillator frequency is divided for generating the
bit time quanta. The bit time is built up from a multiple of this quantum.
0x00-0x03F: The actual interpretation by the hardware of this value is
such that one more than the value programmed here is used.
BRP defines the number of CAN clock periods that make up 1 bit time
quanta, so the reset value is 2 bit time quanta (1+1).
The CANBRPE register can be used to further divide the bit time.
June 12, 2014
1093
Texas Instruments-Production Data
Controller Area Network (CAN) Module
Register 5: CAN Interrupt (CANINT), offset 0x010
This register indicates the source of the interrupt.
If several interrupts are pending, the CAN Interrupt (CANINT) register points to the pending interrupt
with the highest priority, disregarding the order in which the interrupts occurred. An interrupt remains
pending until the CPU has cleared it. If the INTID field is not 0x0000 (the default) and the IE bit in
the CANCTL register is set, the interrupt is active. The interrupt line remains active until the INTID
field is cleared by reading the CANSTS register, or until the IE bit in the CANCTL register is cleared.
Note:
Reading the CAN Status (CANSTS) register clears the CAN Interrupt (CANINT) register,
if it is pending.
CAN Interrupt (CANINT)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
Offset 0x010
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
INTID
Type
Reset
Bit/Field
Name
Type
Reset
Description
31:16
reserved
RO
0x0000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:0
INTID
RO
0x0000
Interrupt Identifier
The number in this field indicates the source of the interrupt.
Value
Description
0x0000
No interrupt pending
0x0001-0x0020
Number of the message object that
caused the interrupt
0x0021-0x7FFF
Reserved
0x8000
Status Interrupt
0x8001-0xFFFF
Reserved
1094
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Register 6: CAN Test (CANTST), offset 0x014
This register is used for self-test and external pin access. It is write-enabled by setting the TEST bit
in the CANCTL register. Different test functions may be combined, however, CAN transfers are
affected if the TX bits in this register are not zero.
CAN Test (CANTST)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
Offset 0x014
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
LBACK
SILENT
BASIC
RO
0
RO
0
RW
0
RW
0
RW
0
reserved
Type
Reset
reserved
Type
Reset
RX
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7
RX
RO
0
6:5
TX
RW
0x0
TX
RW
0
RW
0
reserved
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Receive Observation
Value
Description
0
The CANnRx pin is low.
1
The CANnRx pin is high.
Transmit Control
Overrides control of the CANnTx pin.
Value
Description
0x0
CAN Module Control
CANnTx is controlled by the CAN module; default
operation
0x1
Sample Point
The sample point is driven on the CANnTx signal. This
mode is useful to monitor bit timing.
0x2
Driven Low
CANnTx drives a low value. This mode is useful for
checking the physical layer of the CAN bus.
0x3
Driven High
CANnTx drives a high value. This mode is useful for
checking the physical layer of the CAN bus.
June 12, 2014
1095
Texas Instruments-Production Data
Controller Area Network (CAN) Module
Bit/Field
Name
Type
Reset
4
LBACK
RW
0
3
2
1:0
SILENT
BASIC
reserved
RW
RW
RO
0
0
0x0
Description
Loopback Mode
Value
Description
0
Loopback mode is disabled.
1
Loopback mode is enabled. In loopback mode, the data
from the transmitter is routed into the receiver. Any data
on the receive input is ignored.
Silent Mode
Value
Description
0
Silent mode is disabled.
1
Silent mode is enabled. In silent mode, the CAN controller
does not transmit data but instead monitors the bus. This
mode is also known as Bus Monitor mode.
Basic Mode
Value
Description
0
Basic mode is disabled.
1
Basic mode is enabled. In basic mode, software should
use the CANIF1 registers as the transmit buffer and use
the CANIF2 registers as the receive buffer.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1096
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Register 7: CAN Baud Rate Prescaler Extension (CANBRPE), offset 0x018
This register is used to further divide the bit time set with the BRP bit in the CANBIT register. It is
write-enabled by setting the CCE bit in the CANCTL register.
CAN Baud Rate Prescaler Extension (CANBRPE)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
Offset 0x018
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:4
reserved
RO
0x0000.000
3:0
BRPE
RW
0x0
BRPE
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Baud Rate Prescaler Extension
0x00-0x0F: Extend the BRP bit in the CANBIT register to values up to
1023. The actual interpretation by the hardware is one more than the
value programmed by BRPE (MSBs) and BRP (LSBs).
June 12, 2014
1097
Texas Instruments-Production Data
Controller Area Network (CAN) Module
Register 8: CAN IF1 Command Request (CANIF1CRQ), offset 0x020
Register 9: CAN IF2 Command Request (CANIF2CRQ), offset 0x080
A message transfer is started as soon as there is a write of the message object number to the MNUM
field when the TXRQST bit in the CANIF1MCTL register is set. With this write operation, the BUSY
bit is automatically set to indicate that a transfer between the CAN Interface Registers and the
internal message RAM is in progress. After a wait time of 3 to 6 CAN_CLK periods, the transfer
between the interface register and the message RAM completes, which then clears the BUSY bit.
CAN IFn Command Request (CANIFnCRQ)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
Offset 0x020
Type RW, reset 0x0000.0001
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
1
reserved
Type
Reset
BUSY
Type
Reset
RO
0
reserved
RO
0
MNUM
Bit/Field
Name
Type
Reset
31:16
reserved
RO
0x0000
15
BUSY
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Busy Flag
Value
Description
0
This bit is cleared when read/write action has finished.
1
This bit is set when a write occurs to the message
number in this register.
14:6
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5:0
MNUM
RW
0x01
Message Number
Selects one of the 32 message objects in the message RAM for data
transfer. The message objects are numbered from 1 to 32.
Value
Description
0x00
Reserved
0 is not a valid message number; it is interpreted
as 0x20, or object 32.
0x01-0x20
Message Number
Indicates specified message object 1 to 32.
0x21-0x3F
Reserved
Not a valid message number; values are shifted and
it is interpreted as 0x01-0x1F.
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June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Register 10: CAN IF1 Command Mask (CANIF1CMSK), offset 0x024
Register 11: CAN IF2 Command Mask (CANIF2CMSK), offset 0x084
Reading the Command Mask registers provides status for various functions. Writing to the Command
Mask registers specifies the transfer direction and selects which buffer registers are the source or
target of the data transfer.
Note that when a read from the message object buffer occurs when the WRNRD bit is clear and the
CLRINTPND and/or NEWDAT bits are set, the interrupt pending and/or new data flags in the message
object buffer are cleared.
CAN IFn Command Mask (CANIFnCMSK)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
Offset 0x024
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
WRNRD
MASK
ARB
CONTROL
CLRINTPND
NEWDAT / TXRQST
reserved
DATAA
DATAB
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7
WRNRD
RW
0
6
MASK
RW
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Write, Not Read
Value
Description
0
Transfer the data in the CAN message object specified by
the MNUM field in the CANIFnCRQ register into the CANIFn
registers.
1
Transfer the data in the CANIFn registers to the CAN
message object specified by the MNUM field in the CAN
Command Request (CANIFnCRQ).
Note:
Interrupt pending and new data conditions in the message
buffer can be cleared by reading from the buffer (WRNRD = 0)
when the CLRINTPND and/or NEWDAT bits are set.
Access Mask Bits
Value
Description
0
Mask bits unchanged.
1
Transfer IDMASK + DIR + MXTD of the message object
into the Interface registers.
June 12, 2014
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Texas Instruments-Production Data
Controller Area Network (CAN) Module
Bit/Field
Name
Type
Reset
5
ARB
RW
0
4
3
CONTROL
CLRINTPND
RW
RW
0
0
Description
Access Arbitration Bits
Value
Description
0
Arbitration bits unchanged.
1
Transfer ID + DIR + XTD + MSGVAL of the message
object into the Interface registers.
Access Control Bits
Value
Description
0
Control bits unchanged.
1
Transfer control bits from the CANIFnMCTL register
into the Interface registers.
Clear Interrupt Pending Bit
The function of this bit depends on the configuration of the WRNRD bit.
Value
Description
0
If WRNRD is clear, the interrupt pending status is transferred
from the message buffer into the CANIFnMCTL register.
If WRNRD is set, the INTPND bit in the message object remains
unchanged.
1
If WRNRD is clear, the interrupt pending status is cleared in the
message buffer. Note the value of this bit that is transferred
to the CANIFnMCTL register always reflects the status of the
bits before clearing.
If WRNRD is set, the INTPND bit is cleared in the message
object.
2
NEWDAT / TXRQST
RW
0
NEWDAT / TXRQST Bit
The function of this bit depends on the configuration of the WRNRD bit.
Value
Description
0
If WRNRD is clear, the value of the new data status is transferred
from the message buffer into the CANIFnMCTL register.
If WRNRD is set, a transmission is not requested.
1
If WRNRD is clear, the new data status is cleared in the message
buffer. Note the value of this bit that is transferred to the
CANIFnMCTL register always reflects the status of the bits
before clearing.
If WRNRD is set, a transmission is requested. Note that when
this bit is set, the TXRQST bit in the CANIFnMCTL register is
ignored.
1100
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Bit/Field
Name
Type
Reset
1
DATAA
RW
0
Description
Access Data Byte 0 to 3
The function of this bit depends on the configuration of the WRNRD bit.
Value
Description
0
Data bytes 0-3 are unchanged.
1
If WRNRD is clear, transfer data bytes 0-3 in CANIFnDA1
and CANIFnDA2 to the message object.
If WRNRD is set, transfer data bytes 0-3 in message object
to CANIFnDA1 and CANIFnDA2.
0
DATAB
RW
0
Access Data Byte 4 to 7
The function of this bit depends on the configuration of the WRNRD bit
as follows:
Value
Description
0
Data bytes 4-7 are unchanged.
1
If WRNRD is clear, transfer data bytes 4-7 in CANIFnDA1
and CANIFnDA2 to the message object.
If WRNRD is set, transfer data bytes 4-7 in message object
to CANIFnDA1 and CANIFnDA2.
June 12, 2014
1101
Texas Instruments-Production Data
Controller Area Network (CAN) Module
Register 12: CAN IF1 Mask 1 (CANIF1MSK1), offset 0x028
Register 13: CAN IF2 Mask 1 (CANIF2MSK1), offset 0x088
The mask information provided in this register accompanies the data (CANIFnDAn), arbitration
information (CANIFnARBn), and control information (CANIFnMCTL) to the message object in the
message RAM. The mask is used with the ID bit in the CANIFnARBn register for acceptance
filtering. Additional mask information is contained in the CANIFnMSK2 register.
CAN IFn Mask 1 (CANIFnMSK1)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
Offset 0x028
Type RW, reset 0x0000.FFFF
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
reserved
Type
Reset
MSK
Type
Reset
Bit/Field
Name
Type
Reset
Description
31:16
reserved
RO
0x0000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:0
MSK
RW
0xFFFF
Identifier Mask
When using a 29-bit identifier, these bits are used for bits [15:0] of the
ID. The MSK field in the CANIFnMSK2 register are used for bits [28:16]
of the ID. When using an 11-bit identifier, these bits are ignored.
Value
Description
0
The corresponding identifier field (ID) in the message
object cannot inhibit the match in acceptance filtering.
1
The corresponding identifier field (ID) is used for
acceptance filtering.
1102
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Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Register 14: CAN IF1 Mask 2 (CANIF1MSK2), offset 0x02C
Register 15: CAN IF2 Mask 2 (CANIF2MSK2), offset 0x08C
This register holds extended mask information that accompanies the CANIFnMSK1 register.
CAN IFn Mask 2 (CANIFnMSK2)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
Offset 0x02C
Type RW, reset 0x0000.FFFF
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
MXTD
MDIR
reserved
RW
1
RW
1
RO
1
RW
0
RW
0
RW
0
RW
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RW
0
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
reserved
Type
Reset
Type
Reset
MSK
Bit/Field
Name
Type
Reset
31:16
reserved
RO
0x0000
15
MXTD
RW
1
14
13
MDIR
reserved
RW
RO
1
1
RW
1
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Mask Extended Identifier
Value
Description
0
The extended identifier bit (XTD in the CANIFnARB2
register) has no effect on the acceptance filtering.
1
The extended identifier bit XTD is used for acceptance
filtering.
Mask Message Direction
Value
Description
0
The message direction bit (DIR in the CANIFnARB2
register) has no effect for acceptance filtering.
1
The message direction bit DIR is used for acceptance
filtering.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
June 12, 2014
1103
Texas Instruments-Production Data
Controller Area Network (CAN) Module
Bit/Field
Name
Type
Reset
Description
12:0
MSK
RW
0xFF
Identifier Mask
When using a 29-bit identifier, these bits are used for bits [28:16] of the
ID. The MSK field in the CANIFnMSK1 register are used for bits [15:0]
of the ID. When using an 11-bit identifier, MSK[12:2] are used for bits
[10:0] of the ID.
Value
Description
0
The corresponding identifier field (ID) in the message
object cannot inhibit the match in acceptance filtering.
1
The corresponding identifier field (ID) is used for
acceptance filtering.
1104
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Register 16: CAN IF1 Arbitration 1 (CANIF1ARB1), offset 0x030
Register 17: CAN IF2 Arbitration 1 (CANIF2ARB1), offset 0x090
These registers hold the identifiers for acceptance filtering.
CAN IFn Arbitration 1 (CANIFnARB1)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
Offset 0x030
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
ID
Type
Reset
Bit/Field
Name
Type
Reset
Description
31:16
reserved
RO
0x0000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:0
ID
RW
0x0000
Message Identifier
This bit field is used with the ID field in the CANIFnARB2 register to
create the message identifier.
When using a 29-bit identifier, bits 15:0 of the CANIFnARB1 register
are [15:0] of the ID, while bits 12:0 of the CANIFnARB2 register are
[28:16] of the ID.
When using an 11-bit identifier, these bits are not used.
June 12, 2014
1105
Texas Instruments-Production Data
Controller Area Network (CAN) Module
Register 18: CAN IF1 Arbitration 2 (CANIF1ARB2), offset 0x034
Register 19: CAN IF2 Arbitration 2 (CANIF2ARB2), offset 0x094
These registers hold information for acceptance filtering.
CAN IFn Arbitration 2 (CANIFnARB2)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
Offset 0x034
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
MSGVAL
XTD
DIR
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
Type
Reset
ID
Bit/Field
Name
Type
Reset
31:16
reserved
RO
0x0000
15
MSGVAL
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Message Valid
Value
Description
0
The message object is ignored by the message handler.
1
The message object is configured and ready to be
considered by the message handler within the CAN
controller.
All unused message objects should have this bit cleared during
initialization and before clearing the INIT bit in the CANCTL register.
The MSGVAL bit must also be cleared before any of the following bits
are modified or if the message object is no longer required: the ID fields
in the CANIFnARBn registers, the XTD and DIR bits in the CANIFnARB2
register, or the DLC field in the CANIFnMCTL register.
14
XTD
RW
0
Extended Identifier
Value
Description
0
An 11-bit Standard Identifier is used for this message
object.
1
A 29-bit Extended Identifier is used for this message
object.
1106
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Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Bit/Field
Name
Type
Reset
13
DIR
RW
0
12:0
ID
RW
0x000
Description
Message Direction
Value
Description
0
Receive. When the TXRQST bit in the CANIFnMCTL register
is set, a remote frame with the identifier of this message object
is received. On reception of a data frame with matching
identifier, that message is stored in this message object.
1
Transmit. When the TXRQST bit in the CANIFnMCTL register
is set, the respective message object is transmitted as a data
frame. On reception of a remote frame with matching identifier,
the TXRQST bit of this message object is set (if RMTEN=1).
Message Identifier
This bit field is used with the ID field in the CANIFnARB2 register to
create the message identifier.
When using a 29-bit identifier, ID[15:0] of the CANIFnARB1 register
are [15:0] of the ID, while these bits, ID[12:0], are [28:16] of the ID.
When using an 11-bit identifier, ID[12:2] are used for bits [10:0] of
the ID. The ID field in the CANIFnARB1 register is ignored.
June 12, 2014
1107
Texas Instruments-Production Data
Controller Area Network (CAN) Module
Register 20: CAN IF1 Message Control (CANIF1MCTL), offset 0x038
Register 21: CAN IF2 Message Control (CANIF2MCTL), offset 0x098
This register holds the control information associated with the message object to be sent to the
Message RAM.
CAN IFn Message Control (CANIFnMCTL)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
Offset 0x038
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
UMASK
TXIE
RXIE
RW
0
RW
0
RW
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RMTEN
TXRQST
EOB
RW
0
RW
0
RW
0
RO
0
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
NEWDAT MSGLST INTPND
Type
Reset
RW
0
RW
0
RW
0
Bit/Field
Name
Type
Reset
31:16
reserved
RO
0x0000
15
NEWDAT
RW
0
14
MSGLST
RW
0
reserved
RO
0
RO
0
DLC
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
New Data
Value
Description
0
No new data has been written into the data portion of this
message object by the message handler since the last time
this flag was cleared by the CPU.
1
The message handler or the CPU has written new data into
the data portion of this message object.
Message Lost
Value
Description
0
No message was lost since the last time this bit was
cleared by the CPU.
1
The message handler stored a new message into this
object when NEWDAT was set; the CPU has lost a message.
This bit is only valid for message objects when the DIR bit in the
CANIFnARB2 register is clear (receive).
13
INTPND
RW
0
Interrupt Pending
Value
Description
0
This message object is not the source of an interrupt.
1
This message object is the source of an interrupt. The
interrupt identifier in the CANINT register points to this
message object if there is not another interrupt source with
a higher priority.
1108
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Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Bit/Field
Name
Type
Reset
12
UMASK
RW
0
11
10
9
8
TXIE
RXIE
RMTEN
TXRQST
RW
RW
RW
RW
0
0
0
0
Description
Use Acceptance Mask
Value
Description
0
Mask is ignored.
1
Use mask (MSK, MXTD, and MDIR bits in the
CANIFnMSKn registers) for acceptance filtering.
Transmit Interrupt Enable
Value
Description
0
The INTPND bit in the CANIFnMCTL register is unchanged
after a successful transmission of a frame.
1
The INTPND bit in the CANIFnMCTL register is set after
a successful transmission of a frame.
Receive Interrupt Enable
Value
Description
0
The INTPND bit in the CANIFnMCTL register is unchanged
after a successful reception of a frame.
1
The INTPND bit in the CANIFnMCTL register is set after
a successful reception of a frame.
Remote Enable
Value
Description
0
At the reception of a remote frame, the TXRQST bit in the
CANIFnMCTL register is left unchanged.
1
At the reception of a remote frame, the TXRQST bit in the
CANIFnMCTL register is set.
Transmit Request
Value
Description
0
This message object is not waiting for transmission.
1
The transmission of this message object is requested
and is not yet done.
Note:
If the WRNRD and TXRQST bits in the CANIFnCMSK register
are set, this bit is ignored.
June 12, 2014
1109
Texas Instruments-Production Data
Controller Area Network (CAN) Module
Bit/Field
Name
Type
Reset
7
EOB
RW
0
Description
End of Buffer
Value
Description
0
Message object belongs to a FIFO Buffer and is not the
last message object of that FIFO Buffer.
1
Single message object or last message object of a FIFO
Buffer.
This bit is used to concatenate two or more message objects (up to 32)
to build a FIFO buffer. For a single message object (thus not belonging
to a FIFO buffer), this bit must be set.
6:4
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3:0
DLC
RW
0x0
Data Length Code
Value
Description
0x0-0x8
Specifies the number of bytes in the data frame.
0x9-0xF
Defaults to a data frame with 8 bytes.
The DLC field in the CANIFnMCTL register of a message object must
be defined the same as in all the corresponding objects with the same
identifier at other nodes. When the message handler stores a data frame,
it writes DLC to the value given by the received message.
1110
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Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Register 22: CAN IF1 Data A1 (CANIF1DA1), offset 0x03C
Register 23: CAN IF1 Data A2 (CANIF1DA2), offset 0x040
Register 24: CAN IF1 Data B1 (CANIF1DB1), offset 0x044
Register 25: CAN IF1 Data B2 (CANIF1DB2), offset 0x048
Register 26: CAN IF2 Data A1 (CANIF2DA1), offset 0x09C
Register 27: CAN IF2 Data A2 (CANIF2DA2), offset 0x0A0
Register 28: CAN IF2 Data B1 (CANIF2DB1), offset 0x0A4
Register 29: CAN IF2 Data B2 (CANIF2DB2), offset 0x0A8
These registers contain the data to be sent or that has been received. In a CAN data frame, data
byte 0 is the first byte to be transmitted or received and data byte 7 is the last byte to be transmitted
or received. In CAN's serial bit stream, the MSB of each byte is transmitted first.
CAN IFn Data nn (CANIFnDnn)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
Offset 0x03C
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
DATA
Type
Reset
Bit/Field
Name
Type
Reset
Description
31:16
reserved
RO
0x0000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:0
DATA
RW
0x0000
Data
The CANIFnDA1 registers contain data bytes 1 and 0; CANIFnDA2
data bytes 3 and 2; CANIFnDB1 data bytes 5 and 4; and CANIFnDB2
data bytes 7 and 6.
June 12, 2014
1111
Texas Instruments-Production Data
Controller Area Network (CAN) Module
Register 30: CAN Transmission Request 1 (CANTXRQ1), offset 0x100
Register 31: CAN Transmission Request 2 (CANTXRQ2), offset 0x104
The CANTXRQ1 and CANTXRQ2 registers hold the TXRQST bits of the 32 message objects. By
reading out these bits, the CPU can check which message object has a transmission request pending.
The TXRQST bit of a specific message object can be changed by three sources: (1) the CPU via the
CANIFnMCTL register, (2) the message handler state machine after the reception of a remote
frame, or (3) the message handler state machine after a successful transmission.
The CANTXRQ1 register contains the TXRQST bits of the first 16 message objects in the message
RAM; the CANTXRQ2 register contains the TXRQST bits of the second 16 message objects.
CAN Transmission Request n (CANTXRQn)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
Offset 0x100
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
TXRQST
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:16
reserved
RO
0x0000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:0
TXRQST
RO
0x0000
Transmission Request Bits
Value
Description
0
The corresponding message object is not waiting for
transmission.
1
The transmission of the corresponding message object
is requested and is not yet done.
1112
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Register 32: CAN New Data 1 (CANNWDA1), offset 0x120
Register 33: CAN New Data 2 (CANNWDA2), offset 0x124
The CANNWDA1 and CANNWDA2 registers hold the NEWDAT bits of the 32 message objects. By
reading these bits, the CPU can check which message object has its data portion updated. The
NEWDAT bit of a specific message object can be changed by three sources: (1) the CPU via the
CANIFnMCTL register, (2) the message handler state machine after the reception of a data frame,
or (3) the message handler state machine after a successful transmission.
The CANNWDA1 register contains the NEWDAT bits of the first 16 message objects in the message
RAM; the CANNWDA2 register contains the NEWDAT bits of the second 16 message objects.
CAN New Data n (CANNWDAn)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
Offset 0x120
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
NEWDAT
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:16
reserved
RO
0x0000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:0
NEWDAT
RO
0x0000
New Data Bits
Value
Description
0
No new data has been written into the data portion of the
corresponding message object by the message handler since
the last time this flag was cleared by the CPU.
1
The message handler or the CPU has written new data into
the data portion of the corresponding message object.
June 12, 2014
1113
Texas Instruments-Production Data
Controller Area Network (CAN) Module
Register 34: CAN Message 1 Interrupt Pending (CANMSG1INT), offset 0x140
Register 35: CAN Message 2 Interrupt Pending (CANMSG2INT), offset 0x144
The CANMSG1INT and CANMSG2INT registers hold the INTPND bits of the 32 message objects.
By reading these bits, the CPU can check which message object has an interrupt pending. The
INTPND bit of a specific message object can be changed through two sources: (1) the CPU via the
CANIFnMCTL register, or (2) the message handler state machine after the reception or transmission
of a frame.
This field is also encoded in the CANINT register.
The CANMSG1INT register contains the INTPND bits of the first 16 message objects in the message
RAM; the CANMSG2INT register contains the INTPND bits of the second 16 message objects.
CAN Message n Interrupt Pending (CANMSGnINT)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
Offset 0x140
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
INTPND
Type
Reset
Bit/Field
Name
Type
Reset
Description
31:16
reserved
RO
0x0000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:0
INTPND
RO
0x0000
Interrupt Pending Bits
Value
Description
0
The corresponding message object is not the source of
an interrupt.
1
The corresponding message object is the source of an
interrupt.
1114
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Register 36: CAN Message 1 Valid (CANMSG1VAL), offset 0x160
Register 37: CAN Message 2 Valid (CANMSG2VAL), offset 0x164
The CANMSG1VAL and CANMSG2VAL registers hold the MSGVAL bits of the 32 message objects.
By reading these bits, the CPU can check which message object is valid. The message valid bit of
a specific message object can be changed with the CANIFnARB2 register.
The CANMSG1VAL register contains the MSGVAL bits of the first 16 message objects in the message
RAM; the CANMSG2VAL register contains the MSGVAL bits of the second 16 message objects in
the message RAM.
CAN Message n Valid (CANMSGnVAL)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
Offset 0x160
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
MSGVAL
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:16
reserved
RO
0x0000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:0
MSGVAL
RO
0x0000
Message Valid Bits
Value
Description
0
The corresponding message object is not configured and
is ignored by the message handler.
1
The corresponding message object is configured and
should be considered by the message handler.
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Analog Comparators
18
Analog Comparators
An analog comparator is a peripheral that compares two analog voltages and provides a logical
output that signals the comparison result.
Note:
Not all comparators have the option to drive an output pin. See “Signal
Description” on page 1117 for more information.
The comparator can provide its output to a device pin, acting as a replacement for an analog
comparator on the board. In addition, the comparator can signal the application via interrupts or
trigger the start of a sample sequence in the ADC. The interrupt generation and ADC triggering logic
is separate and independent. This flexibility means, for example, that an interrupt can be generated
on a rising edge and the ADC triggered on a falling edge.
The TM4C123BH6PGE microcontroller provides three independent integrated analog comparators
with the following functions:
■ Compare external pin input to external pin input or to internal programmable voltage reference
■ Compare a test voltage against any one of the following voltages:
– An individual external reference voltage
– A shared single external reference voltage
– A shared internal reference voltage
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18.1
Block Diagram
Figure 18-1. Analog Comparator Module Block Diagram
C2-
-ve input
C2+
+ve input
Comparator 2
output
+ve input (alternate)
ACCTL2
trigger
ACSTAT2
C2o
trigger
interrupt
reference input
C1-
-ve input
C1+
+ve input
Comparator 1
output
C1o
+ve input (alternate)
ACCTL1
trigger
trigger
ACSTAT1
interrupt
reference input
C0-
-ve input
C0+
+ve input
Comparator 0
output
C0o
+ve input (alternate)
ACCTL0
ACSTAT0
trigger
trigger
interrupt
reference input
Voltage
Ref
Interrupt Control
ACRIS
Internal
Bus
Interrupt
ACREFCTL
ACMIS
ACINTEN
Module
Status
ACMPPP
Note:
18.2
This block diagram depicts the maximum number of analog comparators and comparator outputs
for the family of microcontrollers; the number for this specific device may vary. See page 1130 for
what is included on this device.
Signal Description
The following table lists the external signals of the Analog Comparators and describes the function
of each. The Analog Comparator output signals are alternate functions for some GPIO signals and
default to be GPIO signals at reset. The column in the table below titled "Pin Mux/Pin Assignment"
lists the possible GPIO pin placements for the Analog Comparator signals. The AFSEL bit in the
GPIO Alternate Function Select (GPIOAFSEL) register (page 676) should be set to choose the
Analog Comparator function. The number in parentheses is the encoding that must be programmed
into the PMCn field in the GPIO Port Control (GPIOPCTL) register (page 695) to assign the Analog
Comparator signal to the specified GPIO port pin. The positive and negative input signals are
configured by clearing the DEN bit in the GPIO Digital Enable (GPIODEN) register. For more
information on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 647.
Table 18-1. Analog Comparators Signals (144LQFP)
Pin Name
C0+
Pin Number Pin Mux / Pin
Assignment
34
PC6
a
Pin Type
Buffer Type
I
Analog
Description
Analog comparator 0 positive input.
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Table 18-1. Analog Comparators Signals (144LQFP) (continued)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
C0-
33
PC7
I
Analog
Analog comparator 0 negative input.
C0o
62
112
PF0 (9)
PK4 (8)
O
TTL
C1+
35
PC5
I
Analog
Analog comparator 1 positive input.
C1-
36
PC4
I
Analog
Analog comparator 1 negative input.
C1o
63
111
PF1 (9)
PK5 (8)
O
TTL
C2+
127
PJ4
I
Analog
Analog comparator 2 positive input.
C2-
128
PJ5
I
Analog
Analog comparator 2 negative input.
C2o
64
110
PF2 (9)
PK6 (8)
O
TTL
Analog comparator 0 output.
Analog comparator 1 output.
Analog comparator 2 output.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
18.3
Functional Description
The comparator compares the VIN- and VIN+ inputs to produce an output, VOUT.
VIN- < VIN+, VOUT = 1
VIN- > VIN+, VOUT = 0
As shown in Figure 18-2 on page 1118, the input source for VIN- is an external input, Cn-, where n
is the analog comparator number. In addition to an external input, Cn+, input sources for VIN+ can
be the C0+ or an internal reference, VIREF.
Figure 18-2. Structure of Comparator Unit
-ve input
reference input
output
CINV
1
IntGen
2
TrigGen
ACCTL
ACSTAT
trigger
interrupt
+ve input (alternate)
0
internal
bus
+ve input
A comparator is configured through two status/control registers, Analog Comparator Control
(ACCTL) and Analog Comparator Status (ACSTAT). The internal reference is configured through
one control register, Analog Comparator Reference Voltage Control (ACREFCTL). Interrupt
status and control are configured through three registers, Analog Comparator Masked Interrupt
Status (ACMIS), Analog Comparator Raw Interrupt Status (ACRIS), and Analog Comparator
Interrupt Enable (ACINTEN).
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Typically, the comparator output is used internally to generate an interrupt as controlled by the ISEN
bit in the ACCTL register. The output may also be used to drive one of the external pins (Cno), or
generate an analog-to-digital converter (ADC) trigger.
Important: The ASRCP bits in the ACCTL register must be set before using the analog comparators.
18.3.1
Internal Reference Programming
The structure of the internal reference is shown in Figure 18-3 on page 1119. The internal reference
is controlled by a single configuration register (ACREFCTL).
Figure 18-3. Comparator Internal Reference Structure
N*R
N*R
0xF
0xE
0x1
0x0
Decoder
Note:
internal
reference
VIREF
In the figure above, N*R represents a multiple of the R value that produces the results specified
in Table 18-2 on page 1119.
The internal reference can be programmed in one of two modes (low range or high range) depending
on the RNG bit in the ACREFCTL register. When RNG is clear, the internal reference is in high-range
mode, and when RNG is set the internal reference is in low-range mode.
In each range, the internal reference, VIREF, has 16 preprogrammed thresholds or step values. The
threshold to be used to compare the external input voltage against is selected using the VREF field
in the ACREFCTL register.
In the high-range mode, the VIREF threshold voltages start at the ideal high-range starting voltage
of VDDA/4.2 and increase in ideal constant voltage steps of VDDA/29.4.
In the low-range mode, the VIREF threshold voltages start at 0 V and increase in ideal constant
voltage steps of VDDA/22.12. The ideal VIREF step voltages for each mode and their dependence
on the RNG and VREF fields are summarized in Table 18-2.
Table 18-2. Internal Reference Voltage and ACREFCTL Field Values
ACREFCTL Register
EN Bit Value
EN=0
RNG Bit Value
RNG=X
Output Reference Voltage Based on VREF Field Value
0 V (GND) for any value of VREF. It is recommended that RNG=1 and VREF=0 to
minimize noise on the reference ground.
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Table 18-2. Internal Reference Voltage and ACREFCTL Field Values (continued)
ACREFCTL Register
EN Bit Value
RNG Bit Value
RNG=0
Output Reference Voltage Based on VREF Field Value
VIREF High Range: 16 voltage threshold values indexed by VREF = 0x0 .. 0xF
Ideal starting voltage (VREF=0): VDDA / 4.2
Ideal step size: VDDA/ 29.4
Ideal VIREF threshold values: VIREF (VREF) = VDDA / 4.2 + VREF * (VDDA/ 29.4), for
VREF = 0x0 .. 0xF
For minimum and maximum VIREF threshold values, see Table 18-3 on page 1120.
EN=1
RNG=1
VIREF Low Range: 16 voltage threshold values indexed by VREF = 0x0 .. 0xF
Ideal starting voltage (VREF=0): 0 V
Ideal step size: VDDA/ 22.12
Ideal VIREF threshold values: VIREF (VREF) = VREF * (VDDA/ 22.12), for VREF = 0x0 ..
0xF
For minimum and maximum VIREF threshold values, see Table 18-4 on page 1121.
Note that the values shown in Table 18-2 are the ideal values of the VIREF thresholds. These values
actually vary between minimum and maximum values for each threshold step, depending on process
and temperature. The minimum and maximum values for each step are given by:
■ VIREF(VREF) [Min] = Ideal VIREF(VREF) – (Ideal Step size – 2 mV) / 2
■ VIREF(VREF) [Max] = Ideal VIREF(VREF) + (Ideal Step size – 2 mV) / 2
Examples of minimum and maximum VIREF values for VDDA = 3.3V for high and low ranges, are
shown inTable 18-3 and Table 18-4. Note that these examples are only valid for VDDA = 3.3V; values
scale up and down with VDDA.
Table 18-3. Analog Comparator Voltage Reference Characteristics, VDDA = 3.3V, EN= 1, and
RNG = 0
VREF Value
VIREF Min
Ideal VIREF
VIREF Max
Unit
0x0
0.731
0.786
0.841
V
0x1
0.843
0.898
0.953
V
0x2
0.955
1.010
1.065
V
0x3
1.067
1.122
1.178
V
0x4
1.180
1.235
1.290
V
0x5
1.292
1.347
1.402
V
0x6
1.404
1.459
1.514
V
0x7
1.516
1.571
1.627
V
0x8
1.629
1.684
1.739
V
0x9
1.741
1.796
1.851
V
0xA
1.853
1.908
1.963
V
0xB
1.965
2.020
2.076
V
0xC
2.078
2.133
2.188
V
0xD
2.190
2.245
2.300
V
0xE
2.302
2.357
2.412
V
0xF
2.414
2.469
2.525
V
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Table 18-4. Analog Comparator Voltage Reference Characteristics, VDDA = 3.3V, EN= 1, and
RNG = 1
18.4
VREF Value
VIREF Min
Ideal VIREF
VIREF Max
Unit
0x0
0.000
0.000
0.074
V
0x1
0.076
0.149
0.223
V
0x2
0.225
0.298
0.372
V
0x3
0.374
0.448
0.521
V
0x4
0.523
0.597
0.670
V
0x5
0.672
0.746
0.820
V
0x6
0.822
0.895
0.969
V
0x7
0.971
1.044
1.118
V
0x8
1.120
1.193
1.267
V
0x9
1.269
1.343
1.416
V
0xA
1.418
1.492
1.565
V
0xB
1.567
1.641
1.715
V
0xC
1.717
1.790
1.864
V
0xD
1.866
1.939
2.013
V
0xE
2.015
2.089
2.162
V
0xF
2.164
2.238
2.311
V
Initialization and Configuration
The following example shows how to configure an analog comparator to read back its output value
from an internal register.
1. Enable the analog comparator clock by writing a value of 0x0000.0001 to the RCGCACMP
register in the System Control module (see page 348).
2. Enable the clock to the appropriate GPIO modules via the RCGCGPIO register (see page 335).
To find out which GPIO ports to enable, refer to Table 22-5 on page 1273.
3. In the GPIO module, enable the GPIO port/pin associated with the input signals as GPIO inputs.
To determine which GPIO to configure, see Table 22-4 on page 1262.
4. Configure the PMCn fields in the GPIOPCTL register to assign the analog comparator output
signals to the appropriate pins (see page 695 and Table 22-5 on page 1273).
5. Configure the internal voltage reference to 1.65 V by writing the ACREFCTL register with the
value 0x0000.030C.
6. Configure the comparator to use the internal voltage reference and to not invert the output by
writing the ACCTLn register with the value of 0x0000.040C.
7. Delay for 10 µs.
8. Read the comparator output value by reading the ACSTATn register's OVAL value.
Change the level of the comparator negative input signal C- to see the OVAL value change.
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18.5
Register Map
Table 18-5 on page 1122 lists the comparator registers. The offset listed is a hexadecimal increment
to the register's address, relative to the Analog Comparator base address of 0x4003.C000. Note
that the analog comparator clock must be enabled before the registers can be programmed (see
page 348). There must be a delay of 3 system clocks after the analog comparator module clock is
enabled before any analog comparator module registers are accessed.
Table 18-5. Analog Comparators Register Map
Description
See
page
0x0000.0000
Analog Comparator Masked Interrupt Status
1123
RO
0x0000.0000
Analog Comparator Raw Interrupt Status
1124
ACINTEN
RW
0x0000.0000
Analog Comparator Interrupt Enable
1125
0x010
ACREFCTL
RW
0x0000.0000
Analog Comparator Reference Voltage Control
1126
0x020
ACSTAT0
RO
0x0000.0000
Analog Comparator Status 0
1127
0x024
ACCTL0
RW
0x0000.0000
Analog Comparator Control 0
1128
0x040
ACSTAT1
RO
0x0000.0000
Analog Comparator Status 1
1127
0x044
ACCTL1
RW
0x0000.0000
Analog Comparator Control 1
1128
0x060
ACSTAT2
RO
0x0000.0000
Analog Comparator Status 2
1127
0x064
ACCTL2
RW
0x0000.0000
Analog Comparator Control 2
1128
0xFC0
ACMPPP
RO
0x0007.0007
Analog Comparator Peripheral Properties
1130
Offset
Name
Type
Reset
0x000
ACMIS
RW1C
0x004
ACRIS
0x008
18.6
Register Descriptions
The remainder of this section lists and describes the Analog Comparator registers, in numerical
order by address offset.
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Register 1: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x000
This register provides a summary of the interrupt status (masked) of the comparators.
Analog Comparator Masked Interrupt Status (ACMIS)
Base 0x4003.C000
Offset 0x000
Type RW1C, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
IN2
IN1
IN0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW1C
0
RW1C
0
RW1C
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
Bit/Field
Name
Type
Reset
31:3
reserved
RO
0x0000.000
2
IN2
RW1C
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Comparator 2 Masked Interrupt Status
Value Description
0
No interrupt has occurred or the interrupt is masked.
1
The IN2 bits in the ACRIS register and the ACINTEN registers
are set, providing an interrupt to the interrupt controller.
This bit is cleared by writing a 1. Clearing this bit also clears the IN2 bit
in the ACRIS register.
1
IN1
RW1C
0
Comparator 1 Masked Interrupt Status
Value Description
0
No interrupt has occurred or the interrupt is masked.
1
The IN1 bits in the ACRIS register and the ACINTEN registers
are set, providing an interrupt to the interrupt controller.
This bit is cleared by writing a 1. Clearing this bit also clears the IN1 bit
in the ACRIS register.
0
IN0
RW1C
0
Comparator 0 Masked Interrupt Status
Value Description
0
No interrupt has occurred or the interrupt is masked.
1
The IN0 bits in the ACRIS register and the ACINTEN registers
are set, providing an interrupt to the interrupt controller.
This bit is cleared by writing a 1. Clearing this bit also clears the IN0 bit
in the ACRIS register.
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Register 2: Analog Comparator Raw Interrupt Status (ACRIS), offset 0x004
This register provides a summary of the interrupt status (raw) of the comparators. The bits in this
register must be enabled to generate interrupts using the ACINTEN register.
Analog Comparator Raw Interrupt Status (ACRIS)
Base 0x4003.C000
Offset 0x004
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
IN2
IN1
IN0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
Bit/Field
Name
Type
Reset
31:3
reserved
RO
0x0000.000
2
IN2
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Comparator 2 Interrupt Status
Value Description
0
An interrupt has not occurred.
1
Comparator 2 has generated an interrupt for an event as
configured by the ISEN bit in the ACCTL2 register.
This bit is cleared by writing a 1 to the IN2 bit in the ACMIS register.
1
IN1
RO
0
Comparator 1 Interrupt Status
Value Description
0
An interrupt has not occurred.
1
Comparator 1 has generated an interruptfor an event as
configured by the ISEN bit in the ACCTL1 register.
This bit is cleared by writing a 1 to the IN1 bit in the ACMIS register.
0
IN0
RO
0
Comparator 0 Interrupt Status
Value Description
0
An interrupt has not occurred.
1
Comparator 0 has generated an interrupt for an event as
configured by the ISEN bit in the ACCTL0 register.
This bit is cleared by writing a 1 to the IN0 bit in the ACMIS register.
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Register 3: Analog Comparator Interrupt Enable (ACINTEN), offset 0x008
This register provides the interrupt enable for the comparators.
Analog Comparator Interrupt Enable (ACINTEN)
Base 0x4003.C000
Offset 0x008
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
IN2
IN1
IN0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
RW
0
RW
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
Bit/Field
Name
Type
Reset
Description
31:3
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2
IN2
RW
0
Comparator 2 Interrupt Enable
Value Description
1
IN1
RW
0
0
A comparator 2 interrupt does not affect the interrupt status.
1
The raw interrupt signal comparator 2 is sent to the interrupt
controller.
Comparator 1 Interrupt Enable
Value Description
0
IN0
RW
0
0
A comparator 1 interrupt does not affect the interrupt status.
1
The raw interrupt signal comparator 1 is sent to the interrupt
controller.
Comparator 0 Interrupt Enable
Value Description
0
A comparator 0 interrupt does not affect the interrupt status.
1
The raw interrupt signal comparator 0 is sent to the interrupt
controller.
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Register 4: Analog Comparator Reference Voltage Control (ACREFCTL), offset
0x010
This register specifies whether the resistor ladder is powered on as well as the range and tap.
Analog Comparator Reference Voltage Control (ACREFCTL)
Base 0x4003.C000
Offset 0x010
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
1
0
RW
0
RW
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
9
8
EN
RNG
RW
0
RW
0
Bit/Field
Name
Type
Reset
31:10
reserved
RO
0x0000.0
9
EN
RW
0
reserved
RO
0
RO
0
RO
0
VREF
RO
0
RW
0
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Resistor Ladder Enable
Value Description
0
The resistor ladder is unpowered.
1
Powers on the resistor ladder. The resistor ladder is connected
to VDDA.
This bit is cleared at reset so that the internal reference consumes the
least amount of power if it is not used.
8
RNG
RW
0
Resistor Ladder Range
Value Description
0
The ideal step size for the internal reference is VDDA / 29.4.
1
The ideal step size for the internal reference is VDDA / 22.12.
7:4
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3:0
VREF
RW
0x0
Resistor Ladder Voltage Ref
The VREF bit field specifies the resistor ladder tap that is passed through
an analog multiplexer. The voltage corresponding to the tap position is
the internal reference voltage available for comparison. See Table
18-2 on page 1119 for some output reference voltage examples.
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Register 5: Analog Comparator Status 0 (ACSTAT0), offset 0x020
Register 6: Analog Comparator Status 1 (ACSTAT1), offset 0x040
Register 7: Analog Comparator Status 2 (ACSTAT2), offset 0x060
These registers specify the current output value of the comparator.
Analog Comparator Status n (ACSTATn)
Base 0x4003.C000
Offset 0x020
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
OVAL
reserved
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:2
reserved
RO
0x0000.000
1
OVAL
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Comparator Output Value
Value Description
0
VIN- > VIN+
1
VIN- < VIN+
VIN - is the voltage on the Cn- pin. VIN+ is the voltage on the Cn+ pin,
the C0+ pin, or the internal voltage reference (VIREF) as defined by the
ASRCP bit in the ACCTL register.
0
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Analog Comparators
Register 8: Analog Comparator Control 0 (ACCTL0), offset 0x024
Register 9: Analog Comparator Control 1 (ACCTL1), offset 0x044
Register 10: Analog Comparator Control 2 (ACCTL2), offset 0x064
These registers configure the comparator's input and output.
Analog Comparator Control n (ACCTLn)
Base 0x4003.C000
Offset 0x024
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
reserved
TSLVAL
CINV
reserved
RO
0
RW
0
RW
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
TOEN
RO
0
RO
0
ASRCP
RW
0
RW
0
RW
0
Bit/Field
Name
Type
Reset
31:12
reserved
RO
0x0000.0
11
TOEN
RW
0
TSEN
RW
0
ISLVAL
RW
0
RW
0
ISEN
RW
0
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Trigger Output Enable
Value Description
10:9
ASRCP
RW
0x0
0
ADC events are suppressed and not sent to the ADC.
1
ADC events are sent to the ADC.
Analog Source Positive
The ASRCP field specifies the source of input voltage to the VIN+ terminal
of the comparator. The encodings for this field are as follows:
Value Description
0x0
Pin value of Cn+
0x1
Pin value of C0+
0x2
Internal voltage reference (VIREF)
0x3
Reserved
8
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7
TSLVAL
RW
0
Trigger Sense Level Value
Value Description
0
An ADC event is generated if the comparator output is Low.
1
An ADC event is generated if the comparator output is High.
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Bit/Field
Name
Type
Reset
6:5
TSEN
RW
0x0
Description
Trigger Sense
The TSEN field specifies the sense of the comparator output that
generates an ADC event. The sense conditioning is as follows:
Value Description
4
ISLVAL
RW
0
0x0
Level sense, see TSLVAL
0x1
Falling edge
0x2
Rising edge
0x3
Either edge
Interrupt Sense Level Value
Value Description
3:2
ISEN
RW
0x0
0
An interrupt is generated if the comparator output is Low.
1
An interrupt is generated if the comparator output is High.
Interrupt Sense
The ISEN field specifies the sense of the comparator output that
generates an interrupt. The sense conditioning is as follows:
Value Description
1
CINV
RW
0
0x0
Level sense, see ISLVAL
0x1
Falling edge
0x2
Rising edge
0x3
Either edge
Comparator Output Invert
Value Description
0
reserved
RO
0
0
The output of the comparator is unchanged.
1
The output of the comparator is inverted prior to being processed
by hardware.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Analog Comparators
Register 11: Analog Comparator Peripheral Properties (ACMPPP), offset 0xFC0
The ACMPPP register provides information regarding the properties of the analog comparator
module.
Analog Comparator Peripheral Properties (ACMPPP)
Base 0x4003.C000
Offset 0xFC0
Type RO, reset 0x0007.0007
31
30
29
28
27
26
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
25
24
23
22
21
20
19
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
9
8
7
6
5
4
3
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
18
17
16
C2O
C1O
C0O
RO
1
RO
1
RO
1
2
1
0
CMP2
CMP1
CMP0
RO
1
RO
1
RO
1
Bit/Field
Name
Type
Reset
Description
31:19
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
18
C2O
RO
0x1
Comparator Output 2 Present
Value Description
17
C1O
RO
0x1
0
Comparator output 2 is not present.
1
Comparator output 2 is present.
Comparator Output 1 Present
Value Description
16
C0O
RO
0x1
0
Comparator output 1 is not present.
1
Comparator output 1 is present.
Comparator Output 0 Present
Value Description
0
Comparator output 0 is not present.
1
Comparator output 0 is present.
15:3
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2
CMP2
RO
0x1
Comparator 2 Present
Value Description
0
Comparator 2 is not present.
1
Comparator 2 is present.
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Bit/Field
Name
Type
Reset
1
CMP1
RO
0x1
Description
Comparator 1 Present
Value Description
0
CMP0
RO
0x1
0
Comparator 1 is not present.
1
Comparator 1 is present.
Comparator 0 Present
Value Description
0
Comparator 0 is not present.
1
Comparator 0 is present.
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Pulse Width Modulator (PWM)
19
Pulse Width Modulator (PWM)
Pulse width modulation (PWM) is a powerful technique for digitally encoding analog signal levels.
High-resolution counters are used to generate a square wave, and the duty cycle of the square
wave is modulated to encode an analog signal. Typical applications include switching power supplies
and motor control.
The TM4C123BH6PGE microcontroller contains two PWM modules, each with four PWM generator
blocks and a control block, for a total of 16 PWM outputs. The control block determines the polarity
of the PWM signals, and which signals are passed through to the pins.
Each PWM generator block produces two PWM signals that share the same timer and frequency
and can either be programmed with independent actions or as a single pair of complementary signals
with dead-band delays inserted. The output signals, pwmA' and pwmB', of the PWM generation
blocks are managed by the output control block before being passed to the device pins as MnPWM0
and MnPWM1 or MnPWM2 and MnPWM3, and so on.
Each TM4C123BH6PGE PWM module provides a great deal of flexibility and can generate simple
PWM signals, such as those required by a simple charge pump as well as paired PWM signals with
dead-band delays, such as those required by a half-H bridge driver. Three generator blocks can
also generate the full six channels of gate controls required by a 3-phase inverter bridge.
Each PWM generator block has the following features:
■ Four fault-condition handling inputs to quickly provide low-latency shutdown and prevent damage
to the motor being controlled, for a total of eight inputs
■ One 16-bit counter
– Runs in Down or Up/Down mode
– Output frequency controlled by a 16-bit load value
– Load value updates can be synchronized
– Produces output signals at zero and load value
■ Two PWM comparators
– Comparator value updates can be synchronized
– Produces output signals on match
■ PWM signal generator
– Output PWM signal is constructed based on actions taken as a result of the counter and
PWM comparator output signals
– Produces two independent PWM signals
■ Dead-band generator
– Produces two PWM signals with programmable dead-band delays suitable for driving a half-H
bridge
– Can be bypassed, leaving input PWM signals unmodified
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■ Can initiate an ADC sample sequence
The control block determines the polarity of the PWM signals and which signals are passed through
to the pins. The output of the PWM generation blocks are managed by the output control block
before being passed to the device pins. The PWM control block has the following options:
■ PWM output enable of each PWM signal
■ Optional output inversion of each PWM signal (polarity control)
■ Optional fault handling for each PWM signal
■ Synchronization of timers in the PWM generator blocks
■ Synchronization of timer/comparator updates across the PWM generator blocks
■ Extended PWM synchronization of timer/comparator updates across the PWM generator blocks
■ Interrupt status summary of the PWM generator blocks
■ Extended PWM fault handling, with multiple fault signals, programmable polarities, and filtering
■ PWM generators can be operated independently or synchronized with other generators
19.1
Block Diagram
Figure 19-1 on page 1134 provides the TM4C123BH6PGE PWM module diagram and Figure
19-2 on page 1134 provides a more detailed diagram of a TM4C123BH6PGE PWM generator. The
TM4C123BH6PGE controller contains two PWM modules, each with four generator blocks that
generate eight independent PWM signals or four paired PWM signals with dead-band delays inserted.
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Pulse Width Modulator (PWM)
Figure 19-1. PWM Module Diagram
PWM Clock
Triggers / Faults
System Clock
pwm0A’
PWM
Generator 0
Control and
Status
PWMCTL
PWMSYNC
PWMSTATUS
PWMPP
PWM 0
pwm0B’
PWM 1
pwm0fault
pwm1A’
PWM
Generator 1
PWM 2
pwm1B’
PWM
PWM 3
pwm1fault
Output
Interrupt
Control
pwm2A’
Interrupts
PWMINTEN
PWMRIS
PWMISC
PWM
Generator 2
PWM 4
Logic
pwm2B’
PWM 5
pwm2fault
Triggers
pwm3A’
Output
PWM
Generator 3
PWMENABLE
PWMINVERT
PWMFAULT
PWMFAULTVAL
PWMENUPD
PWM 6
pwm3B’
PWM 7
pwm3fault
Figure 19-2. PWM Generator Block Diagram
PWM Generator Block
Interrupts /
Triggers
Control
PWMnLOAD
PWMnCOUNT
PWMnFLTSRC0
PWMnFLTSRC1
PWMnMINFLTPER
PWMnFLTSEN
PWMnFLTSTAT0
PWMnFLTSTAT1
PWMnINTEN
PWMnRIS
PWMnISC
PWMnCTL
Timer
Fault
Condition
Interrupt and
Trigger
Generator
load
dir
pwmfault
Signal
Generator
cmpA
cmpB
PWMnGENA
PWMnGENB
Dead-Band
Generator
pwmA
pwmB
PWM Clock
Fault(s)
zero
Comparators
PWMnCMPA
PWMnCMPB
Digital Trigger(s)
PWMnDBCTL
PWMnDBRISE
PWMnDBFALL
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pwmB’
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19.2
Signal Description
The following table lists the external signals of the PWM modules and describes the function of
each. The PWM controller signals are alternate functions for some GPIO signals and default to be
GPIO signals at reset. The column in the table below titled "Pin Mux/Pin Assignment" lists the
possible GPIO pin placements for these PWM signals. The AFSEL bit in the GPIO Alternate Function
Select (GPIOAFSEL) register (page 676) should be set to choose the PWM function. The number
in parentheses is the encoding that must be programmed into the PMCn field in the GPIO Port
Control (GPIOPCTL) register (page 695) to assign the PWM signal to the specified GPIO port pin.
For more information on configuring GPIOs, see “General-Purpose Input/Outputs
(GPIOs)” on page 647.
Table 19-1. PWM Signals (144LQFP)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
M0FAULT0
3
32
64
112
143
PD2 (4)
PH0 (6)
PF2 (4)
PK4 (6)
PD6 (4)
I
TTL
Motion Control Module 0 PWM Fault 0.
M0FAULT1
31
53
65
111
144
PH1 (6)
PG2 (4)
PF3 (4)
PK5 (6)
PD7 (4)
I
TTL
Motion Control Module 0 PWM Fault 1.
M0FAULT2
28
52
61
110
PH2 (6)
PG3 (4)
PF4 (4)
PK6 (6)
I
TTL
Motion Control Module 0 PWM Fault 2.
M0FAULT3
27
60
109
PH3 (6)
PF5 (4)
PK7 (6)
I
TTL
Motion Control Module 0 PWM Fault 3.
M0PWM0
32
131
PH0 (4)
PP0 (1)
O
TTL
Motion Control Module 0 PWM 0. This signal is
controlled by Module 0 PWM Generator 0.
M0PWM1
31
132
PH1 (4)
PP1 (1)
O
TTL
Motion Control Module 0 PWM 1. This signal is
controlled by Module 0 PWM Generator 0.
M0PWM2
11
28
136
PP2 (1)
PH2 (4)
PB4 (4)
O
TTL
Motion Control Module 0 PWM 2. This signal is
controlled by Module 0 PWM Generator 1.
M0PWM3
27
135
PH3 (4)
PB5 (4)
O
TTL
Motion Control Module 0 PWM 3. This signal is
controlled by Module 0 PWM Generator 1.
M0PWM4
26
51
83
139
PH4 (4)
PG4 (4)
PM6 (2)
PE4 (4)
O
TTL
Motion Control Module 0 PWM 4. This signal is
controlled by Module 0 PWM Generator 2.
M0PWM5
23
50
82
140
PH5 (4)
PG5 (4)
PM7 (2)
PE5 (4)
O
TTL
Motion Control Module 0 PWM 5. This signal is
controlled by Module 0 PWM Generator 2.
M0PWM6
1
20
22
36
48
PD0 (4)
PN2 (2)
PH6 (4)
PC4 (4)
PG6 (4)
O
TTL
Motion Control Module 0 PWM 6. This signal is
controlled by Module 0 PWM Generator 3.
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Table 19-1. PWM Signals (144LQFP) (continued)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
M0PWM7
2
21
35
47
119
PD1 (4)
PH7 (4)
PC5 (4)
PG7 (4)
PN3 (2)
O
TTL
Motion Control Module 0 PWM 7. This signal is
controlled by Module 0 PWM Generator 3.
M1FAULT0
16
58
61
PK0 (6)
PF7 (5)
PF4 (5)
I
TTL
Motion Control Module 1 PWM Fault 0.
M1FAULT1
17
55
PK1 (6)
PG0 (5)
I
TTL
Motion Control Module 1 PWM Fault 1.
M1FAULT2
18
54
PK2 (6)
PG1 (5)
I
TTL
Motion Control Module 1 PWM Fault 2.
M1FAULT3
19
PK3 (6)
I
TTL
Motion Control Module 1 PWM Fault 3.
M1PWM0
1
53
PD0 (5)
PG2 (5)
O
TTL
Motion Control Module 1 PWM 0. This signal is
controlled by Module 1 PWM Generator 0.
M1PWM1
2
52
PD1 (5)
PG3 (5)
O
TTL
Motion Control Module 1 PWM 1. This signal is
controlled by Module 1 PWM Generator 0.
M1PWM2
45
51
139
PA6 (5)
PG4 (5)
PE4 (5)
O
TTL
Motion Control Module 1 PWM 2. This signal is
controlled by Module 1 PWM Generator 1.
M1PWM3
46
50
140
PA7 (5)
PG5 (5)
PE5 (5)
O
TTL
Motion Control Module 1 PWM 3. This signal is
controlled by Module 1 PWM Generator 1.
M1PWM4
62
71
PF0 (5)
PN4 (2)
O
TTL
Motion Control Module 1 PWM 4. This signal is
controlled by Module 1 PWM Generator 2.
M1PWM5
63
70
PF1 (5)
PN5 (2)
O
TTL
Motion Control Module 1 PWM 5. This signal is
controlled by Module 1 PWM Generator 2.
M1PWM6
64
69
PF2 (5)
PN6 (2)
O
TTL
Motion Control Module 1 PWM 6. This signal is
controlled by Module 1 PWM Generator 3.
M1PWM7
65
68
PF3 (5)
PN7 (2)
O
TTL
Motion Control Module 1 PWM 7. This signal is
controlled by Module 1 PWM Generator 3.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
19.3
Functional Description
19.3.1
Clock Configuration
The PWM has two clock source options:
■ The System Clock
■ A predivided System Clock
The clock source is selected by programming the USPWMDIV bit in the Run-Mode Clock
Configuration (RCC) register at System Control offset 0x060. The PWMDIV bitfield specifies the
divisor of the System Clock that is used to create the PWM Clock.
19.3.2
PWM Timer
The timer in each PWM generator runs in one of two modes: Count-Down mode or Count-Up/Down
mode. In Count-Down mode, the timer counts from the load value to zero, goes back to the load
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value, and continues counting down. In Count-Up/Down mode, the timer counts from zero up to the
load value, back down to zero, back up to the load value, and so on. Generally, Count-Down mode
is used for generating left- or right-aligned PWM signals, while the Count-Up/Down mode is used
for generating center-aligned PWM signals.
The timers output three signals that are used in the PWM generation process: the direction signal
(this is always Low in Count-Down mode, but alternates between Low and High in Count-Up/Down
mode), a single-clock-cycle-width High pulse when the counter is zero, and a single-clock-cycle-width
High pulse when the counter is equal to the load value. Note that in Count-Down mode, the zero
pulse is immediately followed by the load pulse. In the figures in this chapter, these signals are
labelled "dir," "zero," and "load."
19.3.3
PWM Comparators
Each PWM generator has two comparators that monitor the value of the counter; when either
comparator matches the counter, they output a single-clock-cycle-width High pulse, labeled "cmpA"
and "cmpB" in the figures in this chapter. When in Count-Up/Down mode, these comparators match
both when counting up and when counting down, and thus are qualified by the counter direction
signal. These qualified pulses are used in the PWM generation process. If either comparator match
value is greater than the counter load value, then that comparator never outputs a High pulse.
Figure 19-3 on page 1138 shows the behavior of the counter and the relationship of these pulses
when the counter is in Count-Down mode. Figure 19-4 on page 1138 shows the behavior of the counter
and the relationship of these pulses when the counter is in Count-Up/Down mode. In these figures,
the following definitions apply:
■ LOAD is the value in the PWMnLOAD register
■ COMPA is the value in the PWMnCMPA register
■ COMPB is the value in the PWMnCMPB register
■ 0 is the value zero
■ load is the internal signal that has a single-clock-cycle-width High pulse when the counter is
equal to the load value
■ zero is the internal signal that has a single-clock-cycle-width High pulse when the counter is zero
■ cmpA is the internal signal that has a single-clock-cycle-width High pulse when the counter is
equal to COMPA
■ cmpB is the internal signal that has a single-clock-cycle-width High pulse when the counter is
equal to COMPB
■ dir is the internal signal that indicates the count direction
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Figure 19-3. PWM Count-Down Mode
LOAD
COMPA
COMPB
0
load
zero
cmpA
cmpB
dir
BDown
ADown
Figure 19-4. PWM Count-Up/Down Mode
LOAD
COMPA
COMPB
0
load
zero
cmpA
cmpB
dir
BUp
AUp
19.3.4
BDown
ADown
PWM Signal Generator
Each PWM generator takes the load, zero, cmpA, and cmpB pulses (qualified by the dir signal) and
generates two internal PWM signals, pwmA and pwmB. In Count-Down mode, there are four events
that can affect these signals: zero, load, match A down, and match B down. In Count-Up/Down
mode, there are six events that can affect these signals: zero, load, match A down, match A up,
match B down, and match B up. The match A or match B events are ignored when they coincide
with the zero or load events. If the match A and match B events coincide, the first signal, pwmA, is
generated based only on the match A event, and the second signal, pwmB, is generated based only
on the match B event.
For each event, the effect on each output PWM signal is programmable: it can be left alone (ignoring
the event), it can be toggled, it can be driven Low, or it can be driven High. These actions can be
used to generate a pair of PWM signals of various positions and duty cycles, which do or do not
overlap. Figure 19-5 on page 1139 shows the use of Count-Up/Down mode to generate a pair of
center-aligned, overlapped PWM signals that have different duty cycles. This figure shows the pwmA
and pwmB signals before they have passed through the dead-band generator.
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Figure 19-5. PWM Generation Example In Count-Up/Down Mode
LOAD
COMPA
COMPB
0
pwmA
pwmB
In this example, the first generator is set to drive High on match A up, drive Low on match A down,
and ignore the other four events. The second generator is set to drive High on match B up, drive
Low on match B down, and ignore the other four events. Changing the value of comparator A
changes the duty cycle of the pwmA signal, and changing the value of comparator B changes the
duty cycle of the pwmB signal.
19.3.5
Dead-Band Generator
The pwmA and pwmB signals produced by each PWM generator are passed to the dead-band
generator. If the dead-band generator is disabled, the PWM signals simply pass through to the
pwmA' and pwmB' signals unmodified. If the dead-band generator is enabled, the pwmB signal is
lost and two PWM signals are generated based on the pwmA signal. The first output PWM signal,
pwmA' is the pwmA signal with the rising edge delayed by a programmable amount. The second
output PWM signal, pwmB', is the inversion of the pwmA signal with a programmable delay added
between the falling edge of the pwmA signal and the rising edge of the pwmB' signal.
The resulting signals are a pair of active High signals where one is always High, except for a
programmable amount of time at transitions where both are Low. These signals are therefore suitable
for driving a half-H bridge, with the dead-band delays preventing shoot-through current from damaging
the power electronics. Figure 19-6 on page 1139 shows the effect of the dead-band generator on the
pwmA signal and the resulting pwmA' and pwmB' signals that are transmitted to the output control
block.
Figure 19-6. PWM Dead-Band Generator
pwmA
pwmA’
pwmB’
Rising Edge
Delay
19.3.6
Falling Edge
Delay
Interrupt/ADC-Trigger Selector
Each PWM generator also takes the same four (or six) counter events and uses them to generate
an interrupt or an ADC trigger. Any of these events or a set of these events can be selected as a
source for an interrupt; when any of the selected events occur, an interrupt is generated. Additionally,
the same event, a different event, the same set of events, or a different set of events can be selected
as a source for an ADC trigger; when any of these selected events occur, an ADC trigger pulse is
generated. The selection of events allows the interrupt or ADC trigger to occur at a specific position
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within the pwmA or pwmB signal. Note that interrupts and ADC triggers are based on the raw events;
delays in the PWM signal edges caused by the dead-band generator are not taken into account.
19.3.7
Synchronization Methods
Each PWM module provides four PWM generators, each providing two PWM outputs that may be
used in a wide variety of applications. Generally speaking, the PWM is used in one of two categories
of operation:
■ Unsynchronized. The PWM generator and its two output signals are used alone, independent
of other PWM generators.
■ Synchronized. The PWM generator and its two outputs signals are used in conjunction with
other PWM generators using a common, unified time base. If multiple PWM generators are
configured with the same counter load value, synchronization can be used to guarantee that
they also have the same count value (the PWM generators must be configured before they are
synchronized). With this feature, more than two MnPWMn signals can be produced with a known
relationship between the edges of those signals because the counters always have the same
values. Other states in the module provide mechanisms to maintain the common time base and
mutual synchronization.
The counter in a PWM generator can be reset to zero by writing the PWM Time Base Sync
(PWMSYNC) register and setting the SYNCn bit associated with the generator. Multiple PWM
generators can be synchronized together by setting all necessary SYNCn bits in one access. For
example, setting the SYNC0 and SYNC1 bits in the PWMSYNC register causes the counters in PWM
generators 0 and 1 to reset together.
Additional synchronization can occur between multiple PWM generators by updating register contents
in one of the following three ways:
■ Immediately. The write value has immediate effect, and the hardware reacts immediately.
■ Locally Synchronized. The write value does not affect the logic until the counter reaches the
value zero at the end of the PWM cycle. In this case, the effect of the write is deferred, providing
a guaranteed defined behavior and preventing overly short or overly long output PWM pulses.
■ Globally Synchronized. The write value does not affect the logic until two sequential events
have occurred: (1) the Update mode for the generator function is programmed for global
synchronization in the PWMnCTL register, and (2) the counter reaches zero at the end of the
PWM cycle. In this case, the effect of the write is deferred until the end of the PWM cycle following
the end of all updates. This mode allows multiple items in multiple PWM generators to be updated
simultaneously without odd effects during the update; everything runs from the old values until
a point at which they all run from the new values. The Update mode of the load and comparator
match values can be individually configured in each PWM generator block. It typically makes
sense to use the synchronous update mechanism across PWM generator blocks when the timers
in those blocks are synchronized, although this is not required in order for this mechanism to
function properly.
The following registers provide either local or global synchronization based on the state of various
Update mode bits and fields in the PWMnCTL register (LOADUPD; CMPAUPD; CMPBUPD):
■ Generator Registers: PWMnLOAD, PWMnCMPA, and PWMnCMPB
The following registers default to immediate update, but are provided with the optional functionality
of synchronously updating rather than having all updates take immediate effect:
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■ Module-Level Register: PWMENABLE (based on the state of the ENUPDn bits in the PWMENUPD
register).
■ Generator Register: PWMnGENA, PWMnGENB, PWMnDBCTL, PWMnDBRISE, and
PWMnDBFALL (based on the state of various Update mode bits and fields in the PWMnCTL
register (GENAUPD; GENBUPD; DBCTLUPD; DBRISEUPD; DBFALLUPD)).
All other registers are considered statically provisioned for the execution of an application or are
used dynamically for purposes unrelated to maintaining synchronization and therefore do not need
synchronous update functionality.
19.3.8
Fault Conditions
A fault condition is one in which the controller must be signaled to stop normal PWM function and
then set the MnPWMn signals to a safe state. Two basic situations cause fault conditions:
■ The microcontroller is stalled and cannot perform the necessary computation in the time required
for motion control
■ An external error or event is detected
Each PWM generator can use the following inputs to generate a fault condition, including:
■ MnFAULTn pin assertion
■ A stall of the controller generated by the debugger
■ The trigger of an ADC digital comparator
Fault conditions are calculated on a per-PWM generator basis. Each PWM generator configures
the necessary conditions to indicate a fault condition exists. This method allows the development
of applications with dependent and independent control.
Eight fault input pins (MnFAULTn) are available. These inputs may be used with circuits that generate
an active High or active Low signal to indicate an error condition. A MnFAULTn pins may be
individually programmed for the appropriate logic sense using the PWMnFLTSEN register.
The PWM generator's mode control, including fault condition handling, is provided in the PWMnCTL
register. The PWMnCTL register also selects whether the fault condition is maintained as long as
the external condition lasts or if it is latched until the fault condition until cleared by software. Finally,
this register also enables a counter that may be used to extend the period of a fault condition for
external events to assure that the duration is a minimum length. The minimum fault period count is
specified in the PWMnMINFLTPER register.
Note:
When using an ADC digital comparator as a fault source, the LATCH and MINFLTPER bits
in the PWMnCTL register should be set to 1 to ensure trigger assertions are captured.
Status regarding the specific fault cause is provided in the PWMnFLTSTAT0 and PWMnFLTSTAT1
registers. Note that the fault status registers, PWMnFLTSTAT0 and PWMnFLTSTAT1, reflect the
status of all fault sources, regardless of what fault sources are enabled for that particular generator.
PWM generator fault conditions may be promoted to a controller interrupt using the PWMINTEN
register.
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Pulse Width Modulator (PWM)
19.3.9
Output Control Block
The output control block takes care of the final conditioning of the pwmA' and pwmB' signals before
they go to the pins as the MnPWMn signals. Via a single register, the PWM Output Enable
(PWNENABLE) register, the set of PWM signals that are actually enabled to the pins can be modified.
This function can be used, for example, to perform commutation of a brushless DC motor with a
single register write (and without modifying the individual PWM generators, which are modified by
the feedback control loop). In addition, the updating of the bits in the PWMENABLE register can
be configured to be immediate or locally or globally synchronized to the next synchronous update
using the PWM Enable Update (PWMENUPD) register.
During fault conditions, the PWM output signals, MnPWMn, usually must be driven to safe values so
that external equipment may be safely controlled. The PWMFAULT register specifies whether during
a fault condition, the generated signal continues to be passed driven or to an encoding specified in
the PWMFAULTVAL register.
A final inversion can be applied to any of the MnPWMn signals, making them active Low instead of
the default active High using the PWM Output Inversion (PWMINVERT). The inversion is applied
even if a value has been enabled in the PWMFAULT register and specified in the PWMFAULTVAL
register. In other words, if a bit is set in the PWMFAULT, PWMFAULTVAL, and PWMINVERT
registers, the output on the MnPWMn signal is 0, not 1 as specified in the PWMFAULTVAL register.
19.4
Initialization and Configuration
The following example shows how to initialize PWM Generator 0 with a 25-kHz frequency, a 25%
duty cycle on the MnPWM0 pin, and a 75% duty cycle on the MnPWM1 pin. This example assumes
the system clock is 20 MHz.
1. Enable the PWM clock by writing a value of 0x0010.0000 to the RCGC0 register in the System
Control module (see page 451).
2. Enable the clock to the appropriate GPIO module via the RCGC2 register in the System Control
module (see page 459).
3. In the GPIO module, enable the appropriate pins for their alternate function using the
GPIOAFSEL register. To determine which GPIOs to configure, see Table 22-4 on page 1262.
4. Configure the PMCn fields in the GPIOPCTL register to assign the PWM signals to the appropriate
pins (see page 695 and Table 22-5 on page 1273).
5. Configure the Run-Mode Clock Configuration (RCC) register in the System Control module
to use the PWM divide (USEPWMDIV) and set the divider (PWMDIV) to divide by 2 (000).
6. Configure the PWM generator for countdown mode with immediate updates to the parameters.
■ Write the PWM0CTL register with a value of 0x0000.0000.
■ Write the PWM0GENA register with a value of 0x0000.008C.
■ Write the PWM0GENB register with a value of 0x0000.080C.
7. Set the period. For a 25-KHz frequency, the period = 1/25,000, or 40 microseconds. The PWM
clock source is 10 MHz; the system clock divided by 2. Thus there are 400 clock ticks per period.
Use this value to set the PWM0LOAD register. In Count-Down mode, set the LOAD field in the
PWM0LOAD register to the requested period minus one.
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■ Write the PWM0LOAD register with a value of 0x0000.018F.
8. Set the pulse width of the MnPWM0 pin for a 25% duty cycle.
■ Write the PWM0CMPA register with a value of 0x0000.012B.
9. Set the pulse width of the MnPWM1 pin for a 75% duty cycle.
■ Write the PWM0CMPB register with a value of 0x0000.0063.
10. Start the timers in PWM generator 0.
■ Write the PWM0CTL register with a value of 0x0000.0001.
11. Enable PWM outputs.
■ Write the PWMENABLE register with a value of 0x0000.0003.
19.5
Register Map
Table 19-2 on page 1143 lists the PWM registers. The offset listed is a hexadecimal increment to the
register's address, relative to the PWM module's base address:
■ PWM0: 0x4002.8000
■ PWM1: 0x4002.9000
Note that the PWM module clock must be enabled before the registers can be programmed (see
page 451). There must be a delay of 3 system clocks after the PWM module clock is enabled before
any PWM module registers are accessed.
Table 19-2. PWM Register Map
Description
See
page
0x0000.0000
PWM Master Control
1147
RW
0x0000.0000
PWM Time Base Sync
1149
PWMENABLE
RW
0x0000.0000
PWM Output Enable
1150
0x00C
PWMINVERT
RW
0x0000.0000
PWM Output Inversion
1152
0x010
PWMFAULT
RW
0x0000.0000
PWM Output Fault
1154
0x014
PWMINTEN
RW
0x0000.0000
PWM Interrupt Enable
1156
0x018
PWMRIS
RO
0x0000.0000
PWM Raw Interrupt Status
1158
0x01C
PWMISC
RW1C
0x0000.0000
PWM Interrupt Status and Clear
1161
0x020
PWMSTATUS
RO
0x0000.0000
PWM Status
1164
0x024
PWMFAULTVAL
RW
0x0000.0000
PWM Fault Condition Value
1166
0x028
PWMENUPD
RW
0x0000.0000
PWM Enable Update
1168
0x040
PWM0CTL
RW
0x0000.0000
PWM0 Control
1172
0x044
PWM0INTEN
RW
0x0000.0000
PWM0 Interrupt and Trigger Enable
1177
Offset
Name
Type
Reset
0x000
PWMCTL
RW
0x004
PWMSYNC
0x008
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Pulse Width Modulator (PWM)
Table 19-2. PWM Register Map (continued)
Description
See
page
0x0000.0000
PWM0 Raw Interrupt Status
1180
RW1C
0x0000.0000
PWM0 Interrupt Status and Clear
1182
PWM0LOAD
RW
0x0000.0000
PWM0 Load
1184
0x054
PWM0COUNT
RO
0x0000.0000
PWM0 Counter
1185
0x058
PWM0CMPA
RW
0x0000.0000
PWM0 Compare A
1186
0x05C
PWM0CMPB
RW
0x0000.0000
PWM0 Compare B
1187
0x060
PWM0GENA
RW
0x0000.0000
PWM0 Generator A Control
1188
0x064
PWM0GENB
RW
0x0000.0000
PWM0 Generator B Control
1191
0x068
PWM0DBCTL
RW
0x0000.0000
PWM0 Dead-Band Control
1194
0x06C
PWM0DBRISE
RW
0x0000.0000
PWM0 Dead-Band Rising-Edge Delay
1195
0x070
PWM0DBFALL
RW
0x0000.0000
PWM0 Dead-Band Falling-Edge-Delay
1196
0x074
PWM0FLTSRC0
RW
0x0000.0000
PWM0 Fault Source 0
1197
0x078
PWM0FLTSRC1
RW
0x0000.0000
PWM0 Fault Source 1
1199
0x07C
PWM0MINFLTPER
RW
0x0000.0000
PWM0 Minimum Fault Period
1202
0x080
PWM1CTL
RW
0x0000.0000
PWM1 Control
1172
0x084
PWM1INTEN
RW
0x0000.0000
PWM1 Interrupt and Trigger Enable
1177
0x088
PWM1RIS
RO
0x0000.0000
PWM1 Raw Interrupt Status
1180
0x08C
PWM1ISC
RW1C
0x0000.0000
PWM1 Interrupt Status and Clear
1182
0x090
PWM1LOAD
RW
0x0000.0000
PWM1 Load
1184
0x094
PWM1COUNT
RO
0x0000.0000
PWM1 Counter
1185
0x098
PWM1CMPA
RW
0x0000.0000
PWM1 Compare A
1186
0x09C
PWM1CMPB
RW
0x0000.0000
PWM1 Compare B
1187
0x0A0
PWM1GENA
RW
0x0000.0000
PWM1 Generator A Control
1188
0x0A4
PWM1GENB
RW
0x0000.0000
PWM1 Generator B Control
1191
0x0A8
PWM1DBCTL
RW
0x0000.0000
PWM1 Dead-Band Control
1194
0x0AC
PWM1DBRISE
RW
0x0000.0000
PWM1 Dead-Band Rising-Edge Delay
1195
0x0B0
PWM1DBFALL
RW
0x0000.0000
PWM1 Dead-Band Falling-Edge-Delay
1196
0x0B4
PWM1FLTSRC0
RW
0x0000.0000
PWM1 Fault Source 0
1197
0x0B8
PWM1FLTSRC1
RW
0x0000.0000
PWM1 Fault Source 1
1199
0x0BC
PWM1MINFLTPER
RW
0x0000.0000
PWM1 Minimum Fault Period
1202
0x0C0
PWM2CTL
RW
0x0000.0000
PWM2 Control
1172
0x0C4
PWM2INTEN
RW
0x0000.0000
PWM2 Interrupt and Trigger Enable
1177
Offset
Name
Type
Reset
0x048
PWM0RIS
RO
0x04C
PWM0ISC
0x050
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Table 19-2. PWM Register Map (continued)
Description
See
page
0x0000.0000
PWM2 Raw Interrupt Status
1180
RW1C
0x0000.0000
PWM2 Interrupt Status and Clear
1182
PWM2LOAD
RW
0x0000.0000
PWM2 Load
1184
0x0D4
PWM2COUNT
RO
0x0000.0000
PWM2 Counter
1185
0x0D8
PWM2CMPA
RW
0x0000.0000
PWM2 Compare A
1186
0x0DC
PWM2CMPB
RW
0x0000.0000
PWM2 Compare B
1187
0x0E0
PWM2GENA
RW
0x0000.0000
PWM2 Generator A Control
1188
0x0E4
PWM2GENB
RW
0x0000.0000
PWM2 Generator B Control
1191
0x0E8
PWM2DBCTL
RW
0x0000.0000
PWM2 Dead-Band Control
1194
0x0EC
PWM2DBRISE
RW
0x0000.0000
PWM2 Dead-Band Rising-Edge Delay
1195
0x0F0
PWM2DBFALL
RW
0x0000.0000
PWM2 Dead-Band Falling-Edge-Delay
1196
0x0F4
PWM2FLTSRC0
RW
0x0000.0000
PWM2 Fault Source 0
1197
0x0F8
PWM2FLTSRC1
RW
0x0000.0000
PWM2 Fault Source 1
1199
0x0FC
PWM2MINFLTPER
RW
0x0000.0000
PWM2 Minimum Fault Period
1202
0x100
PWM3CTL
RW
0x0000.0000
PWM3 Control
1172
0x104
PWM3INTEN
RW
0x0000.0000
PWM3 Interrupt and Trigger Enable
1177
0x108
PWM3RIS
RO
0x0000.0000
PWM3 Raw Interrupt Status
1180
0x10C
PWM3ISC
RW1C
0x0000.0000
PWM3 Interrupt Status and Clear
1182
0x110
PWM3LOAD
RW
0x0000.0000
PWM3 Load
1184
0x114
PWM3COUNT
RO
0x0000.0000
PWM3 Counter
1185
0x118
PWM3CMPA
RW
0x0000.0000
PWM3 Compare A
1186
0x11C
PWM3CMPB
RW
0x0000.0000
PWM3 Compare B
1187
0x120
PWM3GENA
RW
0x0000.0000
PWM3 Generator A Control
1188
0x124
PWM3GENB
RW
0x0000.0000
PWM3 Generator B Control
1191
0x128
PWM3DBCTL
RW
0x0000.0000
PWM3 Dead-Band Control
1194
0x12C
PWM3DBRISE
RW
0x0000.0000
PWM3 Dead-Band Rising-Edge Delay
1195
0x130
PWM3DBFALL
RW
0x0000.0000
PWM3 Dead-Band Falling-Edge-Delay
1196
0x134
PWM3FLTSRC0
RW
0x0000.0000
PWM3 Fault Source 0
1197
0x138
PWM3FLTSRC1
RW
0x0000.0000
PWM3 Fault Source 1
1199
0x13C
PWM3MINFLTPER
RW
0x0000.0000
PWM3 Minimum Fault Period
1202
0x800
PWM0FLTSEN
RW
0x0000.0000
PWM0 Fault Pin Logic Sense
1203
0x804
PWM0FLTSTAT0
-
0x0000.0000
PWM0 Fault Status 0
1204
Offset
Name
Type
Reset
0x0C8
PWM2RIS
RO
0x0CC
PWM2ISC
0x0D0
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Pulse Width Modulator (PWM)
Table 19-2. PWM Register Map (continued)
Description
See
page
0x0000.0000
PWM0 Fault Status 1
1206
RW
0x0000.0000
PWM1 Fault Pin Logic Sense
1203
PWM1FLTSTAT0
-
0x0000.0000
PWM1 Fault Status 0
1204
0x888
PWM1FLTSTAT1
-
0x0000.0000
PWM1 Fault Status 1
1206
0x900
PWM2FLTSEN
RW
0x0000.0000
PWM2 Fault Pin Logic Sense
1203
0x904
PWM2FLTSTAT0
-
0x0000.0000
PWM2 Fault Status 0
1204
0x908
PWM2FLTSTAT1
-
0x0000.0000
PWM2 Fault Status 1
1206
0x980
PWM3FLTSEN
RW
0x0000.0000
PWM3 Fault Pin Logic Sense
1203
0x984
PWM3FLTSTAT0
-
0x0000.0000
PWM3 Fault Status 0
1204
0x988
PWM3FLTSTAT1
-
0x0000.0000
PWM3 Fault Status 1
1206
0xFC0
PWMPP
RO
0x0000.0344
PWM Peripheral Properties
1209
Offset
Name
0x808
PWM0FLTSTAT1
0x880
PWM1FLTSEN
0x884
19.6
Type
Reset
-
Register Descriptions
The remainder of this section lists and describes the PWM registers, in numerical order by address
offset.
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Register 1: PWM Master Control (PWMCTL), offset 0x000
This register provides master control over the PWM generation blocks.
PWM Master Control (PWMCTL)
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
GLOBALSYNC3
GLOBALSYNC2
GLOBALSYNC1
GLOBALSYNC0
PWM0 base: 0x4002.8000
PWM1 base: 0x4002.9000
Offset 0x000
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
23
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:4
reserved
RO
0x0000
3
GLOBALSYNC3
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Update PWM Generator 3
Value Description
0
No effect.
1
Any queued update to a load or comparator register in PWM
generator 3 is applied the next time the corresponding counter
becomes zero.
This bit automatically clears when the updates have completed; it cannot
be cleared by software.
2
GLOBALSYNC2
RW
0
Update PWM Generator 2
Value Description
0
No effect.
1
Any queued update to a load or comparator register in PWM
generator 2 is applied the next time the corresponding counter
becomes zero.
This bit automatically clears when the updates have completed; it cannot
be cleared by software.
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Pulse Width Modulator (PWM)
Bit/Field
Name
Type
Reset
1
GLOBALSYNC1
RW
0
Description
Update PWM Generator 1
Value Description
0
No effect.
1
Any queued update to a load or comparator register in PWM
generator 1 is applied the next time the corresponding counter
becomes zero.
This bit automatically clears when the updates have completed; it cannot
be cleared by software.
0
GLOBALSYNC0
RW
0
Update PWM Generator 0
Value Description
0
No effect.
1
Any queued update to a load or comparator register in PWM
generator 0 is applied the next time the corresponding counter
becomes zero.
This bit automatically clears when the updates have completed; it cannot
be cleared by software.
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Register 2: PWM Time Base Sync (PWMSYNC), offset 0x004
This register provides a method to perform synchronization of the counters in the PWM generation
blocks. Setting a bit in this register causes the specified counter to reset back to 0; setting multiple
bits resets multiple counters simultaneously. The bits auto-clear after the reset has occurred; reading
them back as zero indicates that the synchronization has completed.
PWM Time Base Sync (PWMSYNC)
PWM0 base: 0x4002.8000
PWM1 base: 0x4002.9000
Offset 0x004
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
SYNC3
SYNC2
SYNC1
SYNC0
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:4
reserved
RO
0x0000.000
3
SYNC3
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Reset Generator 3 Counter
Value Description
2
SYNC2
RW
0
0
No effect.
1
Resets the PWM generator 3 counter.
Reset Generator 2 Counter
Value Description
1
SYNC1
RW
0
0
No effect.
1
Resets the PWM generator 2 counter.
Reset Generator 1 Counter
Value Description
0
SYNC0
RW
0
0
No effect.
1
Resets the PWM generator 1 counter.
Reset Generator 0 Counter
Value Description
0
No effect.
1
Resets the PWM generator 0 counter.
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Pulse Width Modulator (PWM)
Register 3: PWM Output Enable (PWMENABLE), offset 0x008
This register provides a master control of which generated pwmA' and pwmB' signals are output to
the MnPWMn pins. By disabling a PWM output, the generation process can continue (for example,
when the time bases are synchronized) without driving PWM signals to the pins. When bits in this
register are set, the corresponding pwmA' or pwmB' signal is passed through to the output stage.
When bits are clear, the pwmA' or pwmB' signal is replaced by a zero value which is also passed
to the output stage. The PWMINVERT register controls the output stage, so if the corresponding
bit is set in that register, the value seen on the MnPWMn signal is inverted from what is configured
by the bits in this register. Updates to the bits in this register can be immediate or locally or globally
synchronized to the next synchronous update as controlled by the ENUPDn fields in the PWMENUPD
register.
PWM Output Enable (PWMENABLE)
PWM0 base: 0x4002.8000
PWM1 base: 0x4002.9000
Offset 0x008
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
reserved
Type
Reset
reserved
Type
Reset
PWM7EN PWM6EN PWM5EN PWM4EN PWM3EN PWM2EN PWM1EN PWM0EN
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7
PWM7EN
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
MnPWM7 Output Enable
Value Description
6
PWM6EN
RW
0
0
The MnPWM7 signal has a zero value.
1
The generated pwm3B' signal is passed to the MnPWM7 pin.
MnPWM6 Output Enable
Value Description
5
PWM5EN
RW
0
0
The MnPWM6 signal has a zero value.
1
The generated pwm3A' signal is passed to the MnPWM6 pin.
MnPWM5 Output Enable
Value Description
0
The MnPWM5 signal has a zero value.
1
The generated pwm2B' signal is passed to the MnPWM5 pin.
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Tiva™ TM4C123BH6PGE Microcontroller
Bit/Field
Name
Type
Reset
4
PWM4EN
RW
0
Description
MnPWM4 Output Enable
Value Description
3
PWM3EN
RW
0
0
The MnPWM4 signal has a zero value.
1
The generated pwm2A' signal is passed to the MnPWM4 pin.
MnPWM3 Output Enable
Value Description
2
PWM2EN
RW
0
0
The MnPWM3 signal has a zero value.
1
The generated pwm1B' signal is passed to the MnPWM3 pin.
MnPWM2 Output Enable
Value Description
1
PWM1EN
RW
0
0
The MnPWM2 signal has a zero value.
1
The generated pwm1A' signal is passed to the MnPWM2 pin.
MnPWM1 Output Enable
Value Description
0
PWM0EN
RW
0
0
The MnPWM1 signal has a zero value.
1
The generated pwm0B' signal is passed to the MnPWM1 pin.
MnPWM0 Output Enable
Value Description
0
The MnPWM0 signal has a zero value.
1
The generated pwm0A' signal is passed to the MnPWM0 pin.
June 12, 2014
1151
Texas Instruments-Production Data
Pulse Width Modulator (PWM)
Register 4: PWM Output Inversion (PWMINVERT), offset 0x00C
This register provides a master control of the polarity of the MnPWMn signals on the device pins. The
pwmA' and pwmB' signals generated by the PWM generator are active High; but can be made active
Low via this register. Disabled PWM channels are also passed through the output inverter (if so
configured) so that inactive signals can be High. In addition, if the PWMFAULT register enables a
specific value to be placed on the MnPWMn signals during a fault condition, that value is inverted if
the corresponding bit in this register is set.
PWM Output Inversion (PWMINVERT)
PWM0 base: 0x4002.8000
PWM1 base: 0x4002.9000
Offset 0x00C
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
reserved
Type
Reset
reserved
Type
Reset
PWM7INV PWM6INV PWM5INV PWM4INV PWM3INV PWM2INV PWM1INV PWM0INV
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7
PWM7INV
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Invert MnPWM7 Signal
Value Description
6
PWM6INV
RW
0
0
The MnPWM7 signal is not inverted.
1
The MnPWM7 signal is inverted.
Invert MnPWM6 Signal
Value Description
5
PWM5INV
RW
0
0
The MnPWM6 signal is not inverted.
1
The MnPWM6 signal is inverted.
Invert MnPWM5 Signal
Value Description
4
PWM4INV
RW
0
0
The MnPWM5 signal is not inverted.
1
The MnPWM5 signal is inverted.
Invert MnPWM4 Signal
Value Description
0
The MnPWM4 signal is not inverted.
1
The MnPWM4 signal is inverted.
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Tiva™ TM4C123BH6PGE Microcontroller
Bit/Field
Name
Type
Reset
3
PWM3INV
RW
0
Description
Invert MnPWM3 Signal
Value Description
2
PWM2INV
RW
0
0
The MnPWM3 signal is not inverted.
1
The MnPWM3 signal is inverted.
Invert MnPWM2 Signal
Value Description
1
PWM1INV
RW
0
0
The MnPWM2 signal is not inverted.
1
The MnPWM2 signal is inverted.
Invert MnPWM1 Signal
Value Description
0
PWM0INV
RW
0
0
The MnPWM1 signal is not inverted.
1
The MnPWM1 signal is inverted.
Invert MnPWM0 Signal
Value Description
0
The MnPWM0 signal is not inverted.
1
The MnPWM0 signal is inverted.
June 12, 2014
1153
Texas Instruments-Production Data
Pulse Width Modulator (PWM)
Register 5: PWM Output Fault (PWMFAULT), offset 0x010
This register controls the behavior of the MnPWMn outputs in the presence of fault conditions. Both
the fault inputs (MnFAULTn pins and digital comparator outputs) and debug events are considered
fault conditions. On a fault condition, each pwmA' or pwmB' signal can be passed through unmodified
or driven to the value specified by the corresponding bit in the PWMFAULTVAL register. For outputs
that are configured for pass-through, the debug event handling on the corresponding PWM generator
also determines if the pwmA' or pwmB' signal continues to be generated.
Fault condition control occurs before the output inverter, so PWM signals driven to a specified value
on fault are inverted if the channel is configured for inversion (therefore, the pin is driven to the
logical complement of the specified value on a fault condition).
PWM Output Fault (PWMFAULT)
PWM0 base: 0x4002.8000
PWM1 base: 0x4002.9000
Offset 0x010
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7
FAULT7
RW
0
RO
0
RO
0
7
6
5
4
3
2
1
0
FAULT7
FAULT6
FAULT5
FAULT4
FAULT3
FAULT2
FAULT1
FAULT0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
MnPWM7 Fault
Value Description
6
FAULT6
RW
0
0
The generated pwm3B' signal is passed to the MnPWM7 pin.
1
The MnPWM7 output signal is driven to the value specified by
the PWM7 bit in the PWMFAULTVAL register.
MnPWM6 Fault
Value Description
5
FAULT5
RW
0
0
The generated pwm3A' signal is passed to the MnPWM6 pin.
1
The MnPWM6 output signal is driven to the value specified by
the PWM6 bit in the PWMFAULTVAL register.
MnPWM5 Fault
Value Description
0
The generated pwm2B' signal is passed to the MnPWM5 pin.
1
The MnPWM5 output signal is driven to the value specified by
the PWM5 bit in the PWMFAULTVAL register.
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Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Bit/Field
Name
Type
Reset
4
FAULT4
RW
0
Description
MnPWM4 Fault
Value Description
3
FAULT3
RW
0
0
The generated pwm2A' signal is passed to the MnPWM4 pin.
1
The MnPWM4 output signal is driven to the value specified by
the PWM4 bit in the PWMFAULTVAL register.
MnPWM3 Fault
Value Description
2
FAULT2
RW
0
0
The generated pwm1B' signal is passed to the MnPWM3 pin.
1
The MnPWM3 output signal is driven to the value specified by
the PWM3 bit in the PWMFAULTVAL register.
MnPWM2 Fault
Value Description
1
FAULT1
RW
0
0
The generated pwm1A' signal is passed to the MnPWM2 pin.
1
The MnPWM2 output signal is driven to the value specified by
the PWM2 bit in the PWMFAULTVAL register.
MnPWM1 Fault
Value Description
0
FAULT0
RW
0
0
The generated pwm0B' signal is passed to the MnPWM1 pin.
1
The MnPWM1 output signal is driven to the value specified by
the PWM1 bit in the PWMFAULTVAL register.
MnPWM0 Fault
Value Description
0
The generated pwm0A' signal is passed to the MnPWM0 pin.
1
The MnPWM0 output signal is driven to the value specified by
the PWM0 bit in the PWMFAULTVAL register.
June 12, 2014
1155
Texas Instruments-Production Data
Pulse Width Modulator (PWM)
Register 6: PWM Interrupt Enable (PWMINTEN), offset 0x014
This register controls the global interrupt generation capabilities of the PWM module. The events
that can cause an interrupt are the fault input and the individual interrupts from the PWM generators.
Note:
The "n" in the INTFAULTn and INTPWMn bits in this register correspond to the PWM
generators, not to the FAULTn signals.
PWM Interrupt Enable (PWMINTEN)
PWM0 base: 0x4002.8000
PWM1 base: 0x4002.9000
Offset 0x014
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
19
18
17
16
INTFAULT3
INTFAULT2
INTFAULT1
INTFAULT0
RW
0
RW
0
RW
0
RW
0
3
2
1
0
INTPWM3 INTPWM2 INTPWM1 INTPWM0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
RW
0
RW
0
RW
0
Bit/Field
Name
Type
Reset
Description
31:20
reserved
RO
0x000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
19
INTFAULT3
RW
0
Interrupt Fault 3
Value Description
18
INTFAULT2
RW
0
0
The fault condition for PWM generator 3 is suppressed and not
sent to the interrupt controller.
1
An interrupt is sent to the interrupt controller when the fault
condition for PWM generator 3 is asserted.
Interrupt Fault 2
Value Description
17
INTFAULT1
RW
0
0
The fault condition for PWM generator 2 is suppressed and not
sent to the interrupt controller.
1
An interrupt is sent to the interrupt controller when the fault
condition for PWM generator 2 is asserted.
Interrupt Fault 1
Value Description
0
The fault condition for PWM generator 1 is suppressed and not
sent to the interrupt controller.
1
An interrupt is sent to the interrupt controller when the fault
condition for PWM generator 1 is asserted.
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Tiva™ TM4C123BH6PGE Microcontroller
Bit/Field
Name
Type
Reset
16
INTFAULT0
RW
0
Description
Interrupt Fault 0
Value Description
15:4
reserved
RO
0x000
3
INTPWM3
RW
0
0
The fault condition for PWM generator 0 is suppressed and not
sent to the interrupt controller.
1
An interrupt is sent to the interrupt controller when the fault
condition for PWM generator 0 is asserted.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
PWM3 Interrupt Enable
Value Description
2
INTPWM2
RW
0
0
The PWM generator 3 interrupt is suppressed and not sent to
the interrupt controller.
1
An interrupt is sent to the interrupt controller when the PWM
generator 3 block asserts an interrupt.
PWM2 Interrupt Enable
Value Description
1
INTPWM1
RW
0
0
The PWM generator 2 interrupt is suppressed and not sent to
the interrupt controller.
1
An interrupt is sent to the interrupt controller when the PWM
generator 2 block asserts an interrupt.
PWM1 Interrupt Enable
Value Description
0
INTPWM0
RW
0
0
The PWM generator 1 interrupt is suppressed and not sent to
the interrupt controller.
1
An interrupt is sent to the interrupt controller when the PWM
generator 1 block asserts an interrupt.
PWM0 Interrupt Enable
Value Description
0
The PWM generator 0 interrupt is suppressed and not sent to
the interrupt controller.
1
An interrupt is sent to the interrupt controller when the PWM
generator 0 block asserts an interrupt.
June 12, 2014
1157
Texas Instruments-Production Data
Pulse Width Modulator (PWM)
Register 7: PWM Raw Interrupt Status (PWMRIS), offset 0x018
This register provides the current set of interrupt sources that are asserted, regardless of whether
they are enabled to cause an interrupt to be asserted to the interrupt controller. The fault interrupt
is asserted based on the fault condition source that is specified by the PWMnCTL, PWMnFLTSRC0
and PWMnFLTSRC1 registers. The fault interrupt is latched on detection and must be cleared
through the PWM Interrupt Status and Clear (PWMISC) register. The actual value of the MnFAULTn
signals can be observed using the PWMSTATUS register.
The PWM generator interrupts simply reflect the status of the PWM generators and are cleared via
the interrupt status register in the PWM generator blocks. If a bit is set, the event is active; if a bit
is clear the event is not active.
PWM Raw Interrupt Status (PWMRIS)
PWM0 base: 0x4002.8000
PWM1 base: 0x4002.9000
Offset 0x018
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
19
18
17
16
INTFAULT3
INTFAULT2
INTFAULT1
INTFAULT0
RO
0
RO
0
RO
0
RO
0
3
2
1
0
INTPWM3 INTPWM2 INTPWM1 INTPWM0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:20
reserved
RO
0x000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
19
INTFAULT3
RO
0
Interrupt Fault PWM 3
Value Description
0
The fault condition for PWM generator 3 has not been asserted.
1
The fault condition for PWM generator 3 is asserted.
Note:
18
INTFAULT2
RO
0
If the LATCH bit is set in the PWM3CTL register, the
INTFAULT3 bit in this register can be cleared by writing a 1
to the INTFAULT3 bit in the PWMISC register. If the LATCH
bit is 0 in the PWM3CTL register, writing a 1 to the
INTFAULT3 bit in the PWMISC register has no effect.
Interrupt Fault PWM 2
Value Description
0
The fault condition for PWM generator 2 has not been asserted.
1
The fault condition for PWM generator 2 is asserted.
Note:
If the LATCH bit is set in the PWM2CTL register, the
INTFAULT2 bit in this register can be cleared by writing a 1
to the INTFAULT2 bit in the PWMISC register. If the LATCH
bit is 0 in the PWM2CTL register, writing a 1 to the
INTFAULT2 bit in the PWMISC register has no effect.
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Tiva™ TM4C123BH6PGE Microcontroller
Bit/Field
Name
Type
Reset
17
INTFAULT1
RO
0
Description
Interrupt Fault PWM 1
Value Description
0
The fault condition for PWM generator 1 has not been asserted.
1
The fault condition for PWM generator 1 is asserted.
Note:
16
INTFAULT0
RO
0
If the LATCH bit is set in the PWM1CTL register, the
INTFAULT1 bit in this register can be cleared by writing a 1
to the INTFAULT1 bit in the PWMISC register. If the LATCH
bit is 0 in the PWM1CTL register, writing a 1 to the
INTFAULT1 bit in the PWMISC register has no effect.
Interrupt Fault PWM 0
Value Description
0
The fault condition for PWM generator 0 has not been asserted.
1
The fault condition for PWM generator 0 is asserted.
Note:
15:4
reserved
RO
0x000
3
INTPWM3
RO
0
If the LATCH bit is set in the PWM0CTL register, the
INTFAULT0 bit in this register can be cleared by writing a 1
to the INTFAULT0 bit in the PWMISC register. If the LATCH
bit is 0 in the PWM0CTL register, writing a 1 to the
INTFAULT0 bit in the PWMISC register has no effect.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
PWM3 Interrupt Asserted
Value Description
0
The PWM generator 3 block interrupt has not been asserted.
1
The PWM generator 3 block interrupt is asserted.
The PWM3RIS register shows the source of this interrupt. This bit is
cleared by writing a 1 to the corresponding bit in the PWM3ISC register.
2
INTPWM2
RO
0
PWM2 Interrupt Asserted
Value Description
0
The PWM generator 2 block interrupt has not been asserted.
1
The PWM generator 2 block interrupt is asserted.
The PWM2RIS register shows the source of this interrupt. This bit is
cleared by writing a 1 to the corresponding bit in the PWM2ISC register.
1
INTPWM1
RO
0
PWM1 Interrupt Asserted
Value Description
0
The PWM generator 1 block interrupt has not been asserted.
1
The PWM generator 1 block interrupt is asserted.
The PWM1RIS register shows the source of this interrupt. This bit is
cleared by writing a 1 to the corresponding bit in the PWM1ISC register.
June 12, 2014
1159
Texas Instruments-Production Data
Pulse Width Modulator (PWM)
Bit/Field
Name
Type
Reset
0
INTPWM0
RO
0
Description
PWM0 Interrupt Asserted
Value Description
0
The PWM generator 0 block interrupt has not been asserted.
1
The PWM generator 0 block interrupt is asserted.
The PWM0RIS register shows the source of this interrupt. This bit is
cleared by writing a 1 to the corresponding bit in the PWM0ISC register.
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Tiva™ TM4C123BH6PGE Microcontroller
Register 8: PWM Interrupt Status and Clear (PWMISC), offset 0x01C
This register provides a summary of the interrupt status of the individual PWM generator blocks. If
a fault interrupt is set, the corresponding MnFAULTn input has caused an interrupt. For the fault
interrupt, a write of 1 to that bit position clears the latched interrupt status. If an block interrupt bit
is set, the corresponding generator block is asserting an interrupt. The individual interrupt status
registers, PWMnISC, in each block must be consulted to determine the reason for the interrupt and
used to clear the interrupt.
PWM Interrupt Status and Clear (PWMISC)
PWM0 base: 0x4002.8000
PWM1 base: 0x4002.9000
Offset 0x01C
Type RW1C, reset 0x0000.0000
31
30
29
28
27
26
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
25
24
23
22
21
20
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
9
8
7
6
5
4
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
19
18
17
16
INTFAULT3
INTFAULT2
INTFAULT1
INTFAULT0
RW1C
0
RW1C
0
RW1C
0
RW1C
0
3
2
1
0
INTPWM3 INTPWM2 INTPWM1 INTPWM0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:20
reserved
RO
0x000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
19
INTFAULT3
RW1C
0
FAULT3 Interrupt Asserted
Value Description
0
The fault condition for PWM generator 3 has not been asserted
or is not enabled.
1
An enabled interrupt for the fault condition for PWM generator
3 is asserted or is latched.
Writing a 1 to this bit clears it and the INTFAULT3 bit in the PWMRIS
register.
18
INTFAULT2
RW1C
0
FAULT2 Interrupt Asserted
Value Description
0
The fault condition for PWM generator 2 has not been asserted
or is not enabled.
1
An enabled interrupt for the fault condition for PWM generator
2 is asserted or is latched.
Writing a 1 to this bit clears it and the INTFAULT2 bit in the PWMRIS
register.
June 12, 2014
1161
Texas Instruments-Production Data
Pulse Width Modulator (PWM)
Bit/Field
Name
Type
Reset
17
INTFAULT1
RW1C
0
Description
FAULT1 Interrupt Asserted
Value Description
0
The fault condition for PWM generator 1 has not been asserted
or is not enabled.
1
An enabled interrupt for the fault condition for PWM generator
1 is asserted or is latched.
Writing a 1 to this bit clears it and the INTFAULT1 bit in the PWMRIS
register.
16
INTFAULT0
RW1C
0
FAULT0 Interrupt Asserted
Value Description
0
The fault condition for PWM generator 0 has not been asserted
or is not enabled.
1
An enabled interrupt for the fault condition for PWM generator
0 is asserted or is latched.
Writing a 1 to this bit clears it and the INTFAULT0 bit in the PWMRIS
register.
15:4
reserved
RO
0x000
3
INTPWM3
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
PWM3 Interrupt Status
Value Description
0
The PWM generator 3 block interrupt is not asserted or is not
enabled.
1
An enabled interrupt for the PWM generator 3 block is asserted.
The PWM3RIS register shows the source of this interrupt. This bit is
cleared by writing a 1 to the corresponding bit in the PWM3ISC register.
2
INTPWM2
RO
0
PWM2 Interrupt Status
Value Description
0
The PWM generator 2 block interrupt is not asserted or is not
enabled.
1
An enabled interrupt for the PWM generator 2 block is asserted.
The PWM2RIS register shows the source of this interrupt. This bit is
cleared by writing a 1 to the corresponding bit in the PWM2ISC register.
1
INTPWM1
RO
0
PWM1 Interrupt Status
Value Description
0
The PWM generator 1 block interrupt is not asserted or is not
enabled.
1
An enabled interrupt for the PWM generator 1 block is asserted.
The PWM1RIS register shows the source of this interrupt. This bit is
cleared by writing a 1 to the corresponding bit in the PWM1ISC register.
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Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Bit/Field
Name
Type
Reset
0
INTPWM0
RO
0
Description
PWM0 Interrupt Status
Value Description
0
The PWM generator 0 block interrupt is not asserted or is not
enabled.
1
An enabled interrupt for the PWM generator 0 block is asserted.
The PWM0RIS register shows the source of this interrupt. This bit is
cleared by writing a 1 to the corresponding bit in the PWM0ISC register.
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Pulse Width Modulator (PWM)
Register 9: PWM Status (PWMSTATUS), offset 0x020
This register provides the unlatched status of the PWM generator fault condition.
PWM Status (PWMSTATUS)
PWM0 base: 0x4002.8000
PWM1 base: 0x4002.9000
Offset 0x020
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
FAULT3
FAULT2
FAULT1
FAULT0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:4
reserved
RO
0x0000.000
3
FAULT3
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Generator 3 Fault Status
Value Description
0
The fault condition for PWM generator 3 is not asserted.
1
The fault condition for PWM generator 3 is asserted.
If the FLTSRC bit in the PWM3CTL register is clear, the input
is the source of the fault condition, and is therefore asserted.
2
FAULT2
RO
0
Generator 2 Fault Status
Value Description
0
The fault condition for PWM generator 2 is not asserted.
1
The fault condition for PWM generator 2 is asserted.
If the FLTSRC bit in the PWM2CTL register is clear, the input
is the source of the fault condition, and is therefore asserted.
1
FAULT1
RO
0
Generator 1 Fault Status
Value Description
0
The fault condition for PWM generator 1 is not asserted.
1
The fault condition for PWM generator 1 is asserted.
If the FLTSRC bit in the PWM1CTL register is clear, the input
is the source of the fault condition, and is therefore asserted.
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Tiva™ TM4C123BH6PGE Microcontroller
Bit/Field
Name
Type
Reset
0
FAULT0
RO
0
Description
Generator 0 Fault Status
Value Description
0
The fault condition for PWM generator 0 is not asserted.
1
The fault condition for PWM generator 0 is asserted.
If the FLTSRC bit in the PWM0CTL register is clear, the input
is the source of the fault condition, and is therefore asserted.
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Pulse Width Modulator (PWM)
Register 10: PWM Fault Condition Value (PWMFAULTVAL), offset 0x024
This register specifies the output value driven on the MnPWMn signals during a fault condition if
enabled by the corresponding bit in the PWMFAULT register. Note that if the corresponding bit in
the PWMINVERT register is set, the output value is driven to the logical NOT of the bit value in this
register.
PWM Fault Condition Value (PWMFAULTVAL)
PWM0 base: 0x4002.8000
PWM1 base: 0x4002.9000
Offset 0x024
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
PWM7
PWM6
PWM5
PWM4
PWM3
PWM2
PWM1
PWM0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7
PWM7
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
MnPWM7 Fault Value
Value Description
6
PWM6
RW
0
0
The MnPWM7 output signal is driven Low during fault conditions
if the FAULT7 bit in the PWMFAULT register is set.
1
The MnPWM7 output signal is driven High during fault conditions
if the FAULT7 bit in the PWMFAULT register is set.
MnPWM6 Fault Value
Value Description
5
PWM5
RW
0
0
The MnPWM6 output signal is driven Low during fault conditions
if the FAULT6 bit in the PWMFAULT register is set.
1
The MnPWM6 output signal is driven High during fault conditions
if the FAULT6 bit in the PWMFAULT register is set.
MnPWM5 Fault Value
Value Description
0
The MnPWM5 output signal is driven Low during fault conditions
if the FAULT5 bit in the PWMFAULT register is set.
1
The MnPWM5 output signal is driven High during fault conditions
if the FAULT5 bit in the PWMFAULT register is set.
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Tiva™ TM4C123BH6PGE Microcontroller
Bit/Field
Name
Type
Reset
4
PWM4
RW
0
Description
MnPWM4 Fault Value
Value Description
3
PWM3
RW
0
0
The MnPWM4 output signal is driven Low during fault conditions
if the FAULT4 bit in the PWMFAULT register is set.
1
The MnPWM4 output signal is driven High during fault conditions
if the FAULT4 bit in the PWMFAULT register is set.
MnPWM3 Fault Value
Value Description
2
PWM2
RW
0
0
The MnPWM3 output signal is driven Low during fault conditions
if the FAULT3 bit in the PWMFAULT register is set.
1
The MnPWM3 output signal is driven High during fault conditions
if the FAULT3 bit in the PWMFAULT register is set.
MnPWM2 Fault Value
Value Description
1
PWM1
RW
0
0
The MnPWM2 output signal is driven Low during fault conditions
if the FAULT2 bit in the PWMFAULT register is set.
1
The MnPWM2 output signal is driven High during fault conditions
if the FAULT2 bit in the PWMFAULT register is set.
MnPWM1 Fault Value
Value Description
0
PWM0
RW
0
0
The MnPWM1 output signal is driven Low during fault conditions
if the FAULT1 bit in the PWMFAULT register is set.
1
The MnPWM1 output signal is driven High during fault conditions
if the FAULT1 bit in the PWMFAULT register is set.
MnPWM0 Fault Value
Value Description
0
The MnPWM0 output signal is driven Low during fault conditions
if the FAULT0 bit in the PWMFAULT register is set.
1
The MnPWM0 output signal is driven High during fault conditions
if the FAULT0 bit in the PWMFAULT register is set.
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Pulse Width Modulator (PWM)
Register 11: PWM Enable Update (PWMENUPD), offset 0x028
This register specifies when updates to the PWMnEN bit in the PWMENABLE register are performed.
The PWMnEN bit enables the pwmA' or pwmB' output to be passed to the microcontroller's pin.
Updates can be immediate or locally or globally synchronized to the next synchronous update.
PWM Enable Update (PWMENUPD)
PWM0 base: 0x4002.8000
PWM1 base: 0x4002.9000
Offset 0x028
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
ENUPD7
Type
Reset
RW
0
RW
0
ENUPD6
RW
0
RW
0
ENUPD5
RW
0
RW
0
ENUPD4
RW
0
ENUPD3
ENUPD2
ENUPD1
ENUPD0
RW
0
Bit/Field
Name
Type
Reset
Description
31:16
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:14
ENUPD7
RW
0
MnPWM7 Enable Update Mode
Value Description
0x0
Immediate
Writes to the PWM7EN bit in the PWMENABLE register are used
by the PWM generator immediately.
0x1
Reserved
0x2
Locally Synchronized
Writes to the PWM7EN bit in the PWMENABLE register are used
by the PWM generator the next time the counter is 0.
0x3
Globally Synchronized
Writes to the PWM7EN bit in the PWMENABLE register are used
by the PWM generator the next time the counter is 0 after a
synchronous update has been requested through the PWM
Master Control (PWMCTL) register.
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Tiva™ TM4C123BH6PGE Microcontroller
Bit/Field
Name
Type
Reset
13:12
ENUPD6
RW
0
Description
MnPWM6 Enable Update Mode
Value Description
0x0
Immediate
Writes to the PWM6EN bit in the PWMENABLE register are used
by the PWM generator immediately.
0x1
Reserved
0x2
Locally Synchronized
Writes to the PWM6EN bit in the PWMENABLE register are used
by the PWM generator the next time the counter is 0.
0x3
Globally Synchronized
Writes to the PWM6EN bit in the PWMENABLE register are used
by the PWM generator the next time the counter is 0 after a
synchronous update has been requested through the PWM
Master Control (PWMCTL) register.
11:10
ENUPD5
RW
0
MnPWM5 Enable Update Mode
Value Description
0x0
Immediate
Writes to the PWM5EN bit in the PWMENABLE register are used
by the PWM generator immediately.
0x1
Reserved
0x2
Locally Synchronized
Writes to the PWM5EN bit in the PWMENABLE register are used
by the PWM generator the next time the counter is 0.
0x3
Globally Synchronized
Writes to the PWM5EN bit in the PWMENABLE register are used
by the PWM generator the next time the counter is 0 after a
synchronous update has been requested through the PWM
Master Control (PWMCTL) register.
9:8
ENUPD4
RW
0
MnPWM4 Enable Update Mode
Value Description
0x0
Immediate
Writes to the PWM4EN bit in the PWMENABLE register are used
by the PWM generator immediately.
0x1
Reserved
0x2
Locally Synchronized
Writes to the PWM4EN bit in the PWMENABLE register are used
by the PWM generator the next time the counter is 0.
0x3
Globally Synchronized
Writes to the PWM4EN bit in the PWMENABLE register are used
by the PWM generator the next time the counter is 0 after a
synchronous update has been requested through the PWM
Master Control (PWMCTL) register.
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Pulse Width Modulator (PWM)
Bit/Field
Name
Type
Reset
7:6
ENUPD3
RW
0
Description
MnPWM3 Enable Update Mode
Value Description
0x0
Immediate
Writes to the PWM3EN bit in the PWMENABLE register are used
by the PWM generator immediately.
0x1
Reserved
0x2
Locally Synchronized
Writes to the PWM3EN bit in the PWMENABLE register are used
by the PWM generator the next time the counter is 0.
0x3
Globally Synchronized
Writes to the PWM3EN bit in the PWMENABLE register are used
by the PWM generator the next time the counter is 0 after a
synchronous update has been requested through the PWM
Master Control (PWMCTL) register.
5:4
ENUPD2
RW
0
MnPWM2 Enable Update Mode
Value Description
0x0
Immediate
Writes to the PWM2EN bit in the PWMENABLE register are used
by the PWM generator immediately.
0x1
Reserved
0x2
Locally Synchronized
Writes to the PWM2EN bit in the PWMENABLE register are used
by the PWM generator the next time the counter is 0.
0x3
Globally Synchronized
Writes to the PWM2EN bit in the PWMENABLE register are used
by the PWM generator the next time the counter is 0 after a
synchronous update has been requested through the PWM
Master Control (PWMCTL) register.
3:2
ENUPD1
RW
0
MnPWM1 Enable Update Mode
Value Description
0x0
Immediate
Writes to the PWM1EN bit in the PWMENABLE register are used
by the PWM generator immediately.
0x1
Reserved
0x2
Locally Synchronized
Writes to the PWM1EN bit in the PWMENABLE register are used
by the PWM generator the next time the counter is 0.
0x3
Globally Synchronized
Writes to the PWM1EN bit in the PWMENABLE register are used
by the PWM generator the next time the counter is 0 after a
synchronous update has been requested through the PWM
Master Control (PWMCTL) register.
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Tiva™ TM4C123BH6PGE Microcontroller
Bit/Field
Name
Type
Reset
1:0
ENUPD0
RW
0
Description
MnPWM0 Enable Update Mode
Value Description
0x0
Immediate
Writes to the PWM0EN bit in the PWMENABLE register are used
by the PWM generator immediately.
0x1
Reserved
0x2
Locally Synchronized
Writes to the PWM0EN bit in the PWMENABLE register are used
by the PWM generator the next time the counter is 0.
0x3
Globally Synchronized
Writes to the PWM0EN bit in the PWMENABLE register are used
by the PWM generator the next time the counter is 0 after a
synchronous update has been requested through the PWM
Master Control (PWMCTL) register.
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Pulse Width Modulator (PWM)
Register 12: PWM0 Control (PWM0CTL), offset 0x040
Register 13: PWM1 Control (PWM1CTL), offset 0x080
Register 14: PWM2 Control (PWM2CTL), offset 0x0C0
Register 15: PWM3 Control (PWM3CTL), offset 0x100
These registers configure the PWM signal generation blocks (PWM0CTL controls the PWM generator
0 block, and so on). The Register Update mode, Debug mode, Counting mode, and Block Enable
mode are all controlled via these registers. The blocks produce the PWM signals, which can be
either two independent PWM signals (from the same counter), or a paired set of PWM signals with
dead-band delays added.
The PWM0 block produces the MnPWM0 and MnPWM1 outputs, the PWM1 block produces the MnPWM2
and MnPWM3 outputs, the PWM2 block produces the MnPWM4 and MnPWM5 outputs, and the PWM3
block produces the MnPWM6 and MnPWM7 outputs.
PWMn Control (PWMnCTL)
PWM0 base: 0x4002.8000
PWM1 base: 0x4002.9000
Offset 0x040
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
DBFALLUPD
Type
Reset
RW
0
RW
0
DBRISEUPD
RW
0
RW
0
DBCTLUPD
RW
0
RW
0
GENBUPD
RW
0
GENAUPD
RW
0
RW
0
18
17
16
LATCH
MINFLTPER
FLTSRC
RW
0
RW
0
RO
0
RO
0
RO
0
RW
0
5
4
3
2
CMPBUPD CMPAUPD LOADUPD DEBUG
RW
0
RW
0
RW
0
RW
0
RW
0
1
0
MODE
ENABLE
RW
0
RW
0
Bit/Field
Name
Type
Reset
Description
31:19
reserved
RO
0x000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
18
LATCH
RW
0
Latch Fault Input
Value Description
0
Fault Condition Not Latched
A fault condition is in effect for as long as the generating source
is asserting.
1
Fault Condition Latched
A fault condition is set as the result of the assertion of the
faulting source and is held (latched) while the PWMISC
INTFAULTn bit is set. Clearing the INTFAULTn bit clears the
fault condition.
Note:
When using an ADC digital comparator as a fault source, the
LATCH and MINFLTPER bits in the PWMnCTL register should
be set to 1 to ensure trigger assertions are captured.
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Tiva™ TM4C123BH6PGE Microcontroller
Bit/Field
Name
Type
Reset
17
MINFLTPER
RW
0
Description
Minimum Fault Period
This bit specifies that the PWM generator enables a one-shot counter
to provide a minimum fault condition period.
The timer begins counting on the rising edge of the fault condition to
extend the condition for a minimum duration of the count value. The
timer ignores the state of the fault condition while counting.
The minimum fault delay is in effect only when the MINFLTPER bit is
set. If a detected fault is in the process of being extended when the
MINFLTPER bit is cleared, the fault condition extension is aborted.
The delay time is specified by the PWMnMINFLTPER register MFP field
value. The effect of this is to pulse stretch the fault condition input.
The delay value is defined by the PWM clock period. Because the fault
input is not synchronized to the PWM clock, the period of the time is
PWMClock * (MFP value + 1) or PWMClock * (MFP value + 2).
The delay function makes sense only if the fault source is unlatched. A
latched fault source makes the fault condition appear asserted until
cleared by software and negates the utility of the extend feature. It
applies to all fault condition sources as specified in the FLTSRC field.
Value Description
0
The FAULT input deassertion is unaffected.
1
The PWMnMINFLTPER one-shot counter is active and extends
the period of the fault condition to a minimum period.
Note:
16
FLTSRC
RW
0
When using an ADC digital comparator as a fault source, the
LATCH and MINFLTPER bits in the PWMnCTL register should
be set to 1 to ensure trigger assertions are captured.
Fault Condition Source
Value Description
15:14
DBFALLUPD
RW
0x0
0
The Fault condition is determined by the Fault0 input.
1
The Fault condition is determined by the configuration of the
PWMnFLTSRC0 and PWMnFLTSRC1 registers.
PWMnDBFALL Update Mode
Value Description
0x0
Immediate
The PWMnDBFALL register value is immediately updated on
a write.
0x1
Reserved
0x2
Locally Synchronized
Updates to the register are reflected to the generator the next
time the counter is 0.
0x3
Globally Synchronized
Updates to the register are delayed until the next time the
counter is 0 after a synchronous update has been requested
through the PWMCTL register.
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Pulse Width Modulator (PWM)
Bit/Field
Name
Type
Reset
13:12
DBRISEUPD
RW
0x0
Description
PWMnDBRISE Update Mode
Value Description
0x0
Immediate
The PWMnDBRISE register value is immediately updated on
a write.
0x1
Reserved
0x2
Locally Synchronized
Updates to the register are reflected to the generator the next
time the counter is 0.
0x3
Globally Synchronized
Updates to the register are delayed until the next time the
counter is 0 after a synchronous update has been requested
through the PWMCTL register.
11:10
DBCTLUPD
RW
0x0
PWMnDBCTL Update Mode
Value Description
0x0
Immediate
The PWMnDBCTL register value is immediately updated on a
write.
0x1
Reserved
0x2
Locally Synchronized
Updates to the register are reflected to the generator the next
time the counter is 0.
0x3
Globally Synchronized
Updates to the register are delayed until the next time the
counter is 0 after a synchronous update has been requested
through the PWMCTL register.
9:8
GENBUPD
RW
0x0
PWMnGENB Update Mode
Value Description
0x0
Immediate
The PWMnGENB register value is immediately updated on a
write.
0x1
Reserved
0x2
Locally Synchronized
Updates to the register are reflected to the generator the next
time the counter is 0.
0x3
Globally Synchronized
Updates to the register are delayed until the next time the
counter is 0 after a synchronous update has been requested
through the PWMCTL register.
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Tiva™ TM4C123BH6PGE Microcontroller
Bit/Field
Name
Type
Reset
7:6
GENAUPD
RW
0x0
Description
PWMnGENA Update Mode
Value
Description
0x0
Immediate
The PWMnGENA register value is immediately updated
on a write.
0x1
Reserved
0x2
Locally Synchronized
Updates to the register are reflected to the generator the
next time the counter is 0.
0x3
Globally Synchronized
Updates to the register are delayed until the next time
the counter is 0 after a synchronous update has been
requested through the PWMCTL register.
5
CMPBUPD
RW
0
Comparator B Update Mode
Value Description
0
Locally Synchronized
Updates to the PWMnCMPB register are reflected to the
generator the next time the counter is 0.
1
Globally Synchronized
Updates to the register are delayed until the next time the
counter is 0 after a synchronous update has been requested
through the PWMCTL register.
4
CMPAUPD
RW
0
Comparator A Update Mode
Value Description
0
Locally Synchronized
Updates to the PWMnCMPA register are reflected to the
generator the next time the counter is 0.
1
Globally Synchronized
Updates to the register are delayed until the next time the
counter is 0 after a synchronous update has been requested
through the PWMCTL register.
3
LOADUPD
RW
0
Load Register Update Mode
Value Description
0
Locally Synchronized
Updates to the PWMnLOAD register are reflected to the
generator the next time the counter is 0.
1
Globally Synchronized
Updates to the register are delayed until the next time the
counter is 0 after a synchronous update has been requested
through the PWMCTL register.
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Pulse Width Modulator (PWM)
Bit/Field
Name
Type
Reset
2
DEBUG
RW
0
Description
Debug Mode
Value Description
1
MODE
RW
0
0
The counter stops running when it next reaches 0 and continues
running again when no longer in Debug mode.
1
The counter always runs when in Debug mode.
Counter Mode
Value Description
0
ENABLE
RW
0
0
The counter counts down from the load value to 0 and then
wraps back to the load value (Count-Down mode).
1
The counter counts up from 0 to the load value, back down to
0, and then repeats (Count-Up/Down mode).
PWM Block Enable
Note:
Disabling the PWM by clearing the ENABLE bit does not clear
the COUNT field of the PWMnCOUNT register. Before
re-enabling the PWM (ENABLE = 0x1), the COUNT field should
be cleared by resetting the PWM registers through the
SRPWM register in the System Control Module.
Value Description
0
The entire PWM generation block is disabled and not clocked.
1
The PWM generation block is enabled and produces PWM
signals.
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Tiva™ TM4C123BH6PGE Microcontroller
Register 16: PWM0 Interrupt and Trigger Enable (PWM0INTEN), offset 0x044
Register 17: PWM1 Interrupt and Trigger Enable (PWM1INTEN), offset 0x084
Register 18: PWM2 Interrupt and Trigger Enable (PWM2INTEN), offset 0x0C4
Register 19: PWM3 Interrupt and Trigger Enable (PWM3INTEN), offset 0x104
These registers control the interrupt and ADC trigger generation capabilities of the PWM generators
(PWM0INTEN controls the PWM generator 0 block, and so on). The events that can cause an
interrupt,or an ADC trigger are:
■ The counter being equal to the load register
■ The counter being equal to zero
■ The counter being equal to the PWMnCMPA register while counting up
■ The counter being equal to the PWMnCMPA register while counting down
■ The counter being equal to the PWMnCMPB register while counting up
■ The counter being equal to the PWMnCMPB register while counting down
Any combination of these events can generate either an interrupt or an ADC trigger, though no
determination can be made as to the actual event that caused an ADC trigger if more than one is
specified. The PWMnRIS register provides information about which events have caused raw
interrupts.
PWMn Interrupt and Trigger Enable (PWMnINTEN)
PWM0 base: 0x4002.8000
PWM1 base: 0x4002.9000
Offset 0x044
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
5
4
3
2
1
0
reserved
Type
Reset
RO
0
RO
0
15
14
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
13
12
11
10
9
TRCMPBD TRCMPBU TRCMPAD TRCMPAU TRCNTLOAD
RW
0
RW
0
RW
0
RW
0
RW
0
RO
0
RO
0
RO
0
8
7
6
TRCNTZERO
RW
0
reserved
RO
0
INTCMPBD INTCMPBU INTCMPAD INTCMPAU INTCNTLOAD INTCNTZERO
RO
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bit/Field
Name
Type
Reset
Description
31:14
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
13
TRCMPBD
RW
0
Trigger for Counter=PWMnCMPB Down
Value Description
0
No ADC trigger is output.
1
An ADC trigger pulse is output when the counter matches the
value in the PWMnCMPB register value while counting down.
June 12, 2014
1177
Texas Instruments-Production Data
Pulse Width Modulator (PWM)
Bit/Field
Name
Type
Reset
12
TRCMPBU
RW
0
Description
Trigger for Counter=PWMnCMPB Up
Value Description
11
TRCMPAD
RW
0
0
No ADC trigger is output.
1
An ADC trigger pulse is output when the counter matches the
value in the PWMnCMPB register value while counting up.
Trigger for Counter=PWMnCMPA Down
Value Description
10
TRCMPAU
RW
0
0
No ADC trigger is output.
1
An ADC trigger pulse is output when the counter matches the
value in the PWMnCMPA register value while counting down.
Trigger for Counter=PWMnCMPA Up
Value Description
9
TRCNTLOAD
RW
0
0
No ADC trigger is output.
1
An ADC trigger pulse is output when the counter matches the
value in the PWMnCMPA register value while counting up.
Trigger for Counter=PWMnLOAD
Value Description
8
TRCNTZERO
RW
0
0
No ADC trigger is output.
1
An ADC trigger pulse is output when the counter matches the
PWMnLOAD register.
Trigger for Counter=0
Value Description
7:6
reserved
RO
0x0
5
INTCMPBD
RW
0
0
No ADC trigger is output.
1
An ADC trigger pulse is output when the counter is 0.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Interrupt for Counter=PWMnCMPB Down
Value Description
0
No interrupt.
1
A raw interrupt occurs when the counter matches the value in
the PWMnCMPB register value while counting down.
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Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Bit/Field
Name
Type
Reset
4
INTCMPBU
RW
0
Description
Interrupt for Counter=PWMnCMPB Up
Value Description
3
INTCMPAD
RW
0
0
No interrupt.
1
A raw interrupt occurs when the counter matches the value in
the PWMnCMPB register value while counting up.
Interrupt for Counter=PWMnCMPA Down
Value Description
2
INTCMPAU
RW
0
0
No interrupt.
1
A raw interrupt occurs when the counter matches the value in
the PWMnCMPA register value while counting down.
Interrupt for Counter=PWMnCMPA Up
Value Description
1
INTCNTLOAD
RW
0
0
No interrupt.
1
A raw interrupt occurs when the counter matches the value in
the PWMnCMPA register value while counting up.
Interrupt for Counter=PWMnLOAD
Value Description
0
INTCNTZERO
RW
0
0
No interrupt.
1
A raw interrupt occurs when the counter matches the value in
the PWMnLOAD register value.
Interrupt for Counter=0
Value Description
0
No interrupt.
1
A raw interrupt occurs when the counter is zero.
June 12, 2014
1179
Texas Instruments-Production Data
Pulse Width Modulator (PWM)
Register 20: PWM0 Raw Interrupt Status (PWM0RIS), offset 0x048
Register 21: PWM1 Raw Interrupt Status (PWM1RIS), offset 0x088
Register 22: PWM2 Raw Interrupt Status (PWM2RIS), offset 0x0C8
Register 23: PWM3 Raw Interrupt Status (PWM3RIS), offset 0x108
These registers provide the current set of interrupt sources that are asserted, regardless of whether
they cause an interrupt to be asserted to the controller (PWM0RIS controls the PWM generator 0
block, and so on). If a bit is set, the event has occurred; if a bit is clear, the event has not occurred.
Bits in this register are cleared by writing a 1 to the corresponding bit in the PWMnISC register.
PWMn Raw Interrupt Status (PWMnRIS)
PWM0 base: 0x4002.8000
PWM1 base: 0x4002.9000
Offset 0x048
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
INTCMPBD INTCMPBU INTCMPAD INTCMPAU INTCNTLOAD INTCNTZERO
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:6
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5
INTCMPBD
RO
0
Comparator B Down Interrupt Status
Value Description
0
An interrupt has not occurred.
1
The counter has matched the value in the PWMnCMPB register
while counting down.
This bit is cleared by writing a 1 to the INTCMPBD bit in the PWMnISC
register.
4
INTCMPBU
RO
0
Comparator B Up Interrupt Status
Value Description
0
An interrupt has not occurred.
1
The counter has matched the value in the PWMnCMPB register
while counting up.
This bit is cleared by writing a 1 to the INTCMPBU bit in the PWMnISC
register.
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June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Bit/Field
Name
Type
Reset
3
INTCMPAD
RO
0
Description
Comparator A Down Interrupt Status
Value Description
0
An interrupt has not occurred.
1
The counter has matched the value in the PWMnCMPA register
while counting down.
This bit is cleared by writing a 1 to the INTCMPAD bit in the PWMnISC
register.
2
INTCMPAU
RO
0
Comparator A Up Interrupt Status
Value Description
0
An interrupt has not occurred.
1
The counter has matched the value in the PWMnCMPA register
while counting up.
This bit is cleared by writing a 1 to the INTCMPAU bit in the PWMnISC
register.
1
INTCNTLOAD
RO
0
Counter=Load Interrupt Status
Value Description
0
An interrupt has not occurred.
1
The counter has matched the value in the PWMnLOAD register.
This bit is cleared by writing a 1 to the INTCNTLOAD bit in the PWMnISC
register.
0
INTCNTZERO
RO
0
Counter=0 Interrupt Status
Value Description
0
An interrupt has not occurred.
1
The counter has matched zero.
This bit is cleared by writing a 1 to the INTCNTZERO bit in the PWMnISC
register.
June 12, 2014
1181
Texas Instruments-Production Data
Pulse Width Modulator (PWM)
Register 24: PWM0 Interrupt Status and Clear (PWM0ISC), offset 0x04C
Register 25: PWM1 Interrupt Status and Clear (PWM1ISC), offset 0x08C
Register 26: PWM2 Interrupt Status and Clear (PWM2ISC), offset 0x0CC
Register 27: PWM3 Interrupt Status and Clear (PWM3ISC), offset 0x10C
These registers provide the current set of interrupt sources that are asserted to the interrupt controller
(PWM0ISC controls the PWM generator 0 block, and so on). A bit is set if the event has occurred
and is enabled in the PWMnINTEN register; if a bit is clear, the event has not occurred or is not
enabled. These are RW1C registers; writing a 1 to a bit position clears the corresponding interrupt
reason.
Note:
The interrupt status can only be cleared one PWM Clock cycle after the interrupt occurs.
The larger the PWM Clock Divider (PWMDIV) value in PWMCC register, the longer the
system delay is to clear the interrupt.
PWMn Interrupt Status and Clear (PWMnISC)
PWM0 base: 0x4002.8000
PWM1 base: 0x4002.9000
Offset 0x04C
Type RW1C, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
5
4
3
2
1
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
INTCMPBD INTCMPBU INTCMPAD INTCMPAU INTCNTLOAD INTCNTZERO
RO
0
RO
0
RO
0
RO
0
RW1C
0
RW1C
0
RW1C
0
RW1C
0
RW1C
0
RW1C
0
Bit/Field
Name
Type
Reset
Description
31:6
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5
INTCMPBD
RW1C
0
Comparator B Down Interrupt
Value Description
0
No interrupt has occurred or the interrupt is masked.
1
The INTCMPBD bits in the PWMnRIS and PWMnINTEN registers
are set, providing an interrupt to the interrupt controller.
This bit is cleared by writing a 1. Clearing this bit also clears the
INTCMPBD bit in the PWMnRIS register.
4
INTCMPBU
RW1C
0
Comparator B Up Interrupt
Value Description
0
No interrupt has occurred or the interrupt is masked.
1
The INTCMPBU bits in the PWMnRIS and PWMnINTEN registers
are set, providing an interrupt to the interrupt controller.
This bit is cleared by writing a 1. Clearing this bit also clears the
INTCMPBU bit in the PWMnRIS register.
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June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Bit/Field
Name
Type
Reset
3
INTCMPAD
RW1C
0
Description
Comparator A Down Interrupt
Value Description
0
No interrupt has occurred or the interrupt is masked.
1
The INTCMPAD bits in the PWMnRIS and PWMnINTEN registers
are set, providing an interrupt to the interrupt controller.
This bit is cleared by writing a 1. Clearing this bit also clears the
INTCMPAD bit in the PWMnRIS register.
2
INTCMPAU
RW1C
0
Comparator A Up Interrupt
Value Description
0
No interrupt has occurred or the interrupt is masked.
1
The INTCMPAU bits in the PWMnRIS and PWMnINTEN registers
are set, providing an interrupt to the interrupt controller.
This bit is cleared by writing a 1. Clearing this bit also clears the
INTCMPAU bit in the PWMnRIS register.
1
INTCNTLOAD
RW1C
0
Counter=Load Interrupt
Value Description
0
No interrupt has occurred or the interrupt is masked.
1
The INTCNTLOAD bits in the PWMnRIS and PWMnINTEN
registers are set, providing an interrupt to the interrupt controller.
This bit is cleared by writing a 1. Clearing this bit also clears the
INTCNTLOAD bit in the PWMnRIS register.
0
INTCNTZERO
RW1C
0
Counter=0 Interrupt
Value Description
0
No interrupt has occurred or the interrupt is masked.
1
The INTCNTZERO bits in the PWMnRIS and PWMnINTEN
registers are set, providing an interrupt to the interrupt controller.
This bit is cleared by writing a 1. Clearing this bit also clears the
INTCNTZERO bit in the PWMnRIS register.
June 12, 2014
1183
Texas Instruments-Production Data
Pulse Width Modulator (PWM)
Register 28: PWM0 Load (PWM0LOAD), offset 0x050
Register 29: PWM1 Load (PWM1LOAD), offset 0x090
Register 30: PWM2 Load (PWM2LOAD), offset 0x0D0
Register 31: PWM3 Load (PWM3LOAD), offset 0x110
These registers contain the load value for the PWM counter (PWM0LOAD controls the PWM
generator 0 block, and so on). Based on the counter mode configured by the MODE bit in the
PWMnCTL register, this value is either loaded into the counter after it reaches zero or is the limit
of up-counting after which the counter decrements back to zero. When this value matches the
counter, a pulse is output which can be configured to drive the generation of the pwmA and/or pwmB
signal (via the PWMnGENA/PWMnGENB register) or drive an interruptor ADC trigger (via the
PWMnINTEN register).
If the Load Value Update mode is locally synchronized (based on the LOADUPD field encoding in
the PWMnCTL register), the 16-bit LOAD value is used the next time the counter reaches zero. If
the update mode is globally synchronized, it is used the next time the counter reaches zero after a
synchronous update has been requested through the PWM Master Control (PWMCTL) register
(see page 1147). If this register is re-written before the actual update occurs, the previous value is
never used and is lost.
PWMn Load (PWMnLOAD)
PWM0 base: 0x4002.8000
PWM1 base: 0x4002.9000
Offset 0x050
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
LOAD
Type
Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bit/Field
Name
Type
Reset
Description
31:16
reserved
RO
0x0000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:0
LOAD
RW
0x0000
Counter Load Value
The counter load value.
1184
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Register 32: PWM0 Counter (PWM0COUNT), offset 0x054
Register 33: PWM1 Counter (PWM1COUNT), offset 0x094
Register 34: PWM2 Counter (PWM2COUNT), offset 0x0D4
Register 35: PWM3 Counter (PWM3COUNT), offset 0x114
These registers contain the current value of the PWM counter (PWM0COUNT is the value of the
PWM generator 0 block, and so on). When this value matches zero or the value in the PWMnLOAD,
PWMnCMPA, or PWMnCMPB registers, a pulse is output which can be configured to drive the
generation of a PWM signal or drive an interrupt or ADC trigger.
Note:
Disabling the PWM by clearing the ENABLE bit does not clear the COUNT field of the
PWMnCOUNT register. Before re-enabling the PWM (ENABLE = 0x1), the COUNT field
should be cleared by resetting the PWM registers through the SRPWM register in the System
Control Module.
PWMn Counter (PWMnCOUNT)
PWM0 base: 0x4002.8000
PWM1 base: 0x4002.9000
Offset 0x054
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
COUNT
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:16
reserved
RO
0x0000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:0
COUNT
RO
0x0000
Counter Value
The current value of the counter.
June 12, 2014
1185
Texas Instruments-Production Data
Pulse Width Modulator (PWM)
Register 36: PWM0 Compare A (PWM0CMPA), offset 0x058
Register 37: PWM1 Compare A (PWM1CMPA), offset 0x098
Register 38: PWM2 Compare A (PWM2CMPA), offset 0x0D8
Register 39: PWM3 Compare A (PWM3CMPA), offset 0x118
These registers contain a value to be compared against the counter (PWM0CMPA controls the
PWM generator 0 block, and so on). When this value matches the counter, a pulse is output which
can be configured to drive the generation of the pwmA and pwmB signals (via the PWMnGENA
and PWMnGENB registers) or drive an interrupt or ADC trigger (via the PWMnINTEN register). If
the value of this register is greater than the PWMnLOAD register (see page 1184), then no pulse is
ever output.
If the comparator A update mode is locally synchronized (based on the CMPAUPD bit in the PWMnCTL
register), the 16-bit COMPA value is used the next time the counter reaches zero. If the update mode
is globally synchronized, it is used the next time the counter reaches zero after a synchronous
update has been requested through the PWM Master Control (PWMCTL) register (see page 1147).
If this register is rewritten before the actual update occurs, the previous value is never used and is
lost.
PWMn Compare A (PWMnCMPA)
PWM0 base: 0x4002.8000
PWM1 base: 0x4002.9000
Offset 0x058
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
COMPA
Type
Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bit/Field
Name
Type
Reset
Description
31:16
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:0
COMPA
RW
0x00
Comparator A Value
The value to be compared against the counter.
1186
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Register 40: PWM0 Compare B (PWM0CMPB), offset 0x05C
Register 41: PWM1 Compare B (PWM1CMPB), offset 0x09C
Register 42: PWM2 Compare B (PWM2CMPB), offset 0x0DC
Register 43: PWM3 Compare B (PWM3CMPB), offset 0x11C
These registers contain a value to be compared against the counter (PWM0CMPB controls the
PWM generator 0 block, and so on). When this value matches the counter, a pulse is output which
can be configured to drive the generation of the pwmA and pwmB signals (via the PWMnGENA
and PWMnGENB registers) or drive an interrupt or ADC trigger (via the PWMnINTEN register). If
the value of this register is greater than the PWMnLOAD register, no pulse is ever output.
If the comparator B update mode is locally synchronized (based on the CMPBUPD bit in the PWMnCTL
register), the 16-bit COMPB value is used the next time the counter reaches zero. If the update mode
is globally synchronized, it is used the next time the counter reaches zero after a synchronous
update has been requested through the PWM Master Control (PWMCTL) register (see page 1147).
If this register is rewritten before the actual update occurs, the previous value is never used and is
lost.
PWMn Compare B (PWMnCMPB)
PWM0 base: 0x4002.8000
PWM1 base: 0x4002.9000
Offset 0x05C
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
COMPB
Type
Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bit/Field
Name
Type
Reset
Description
31:16
reserved
RO
0x0000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:0
COMPB
RW
0x0000
Comparator B Value
The value to be compared against the counter.
June 12, 2014
1187
Texas Instruments-Production Data
Pulse Width Modulator (PWM)
Register 44: PWM0 Generator A Control (PWM0GENA), offset 0x060
Register 45: PWM1 Generator A Control (PWM1GENA), offset 0x0A0
Register 46: PWM2 Generator A Control (PWM2GENA), offset 0x0E0
Register 47: PWM3 Generator A Control (PWM3GENA), offset 0x120
These registers control the generation of the pwmA signal based on the load and zero output pulses
from the counter, as well as the compare A and compare B pulses from the comparators
(PWM0GENA controls the PWM generator 0 block, and so on). When the counter is running in
Count-Down mode, only four of these events occur; when running in Count-Up/Down mode, all six
occur. These events provide great flexibility in the positioning and duty cycle of the resulting PWM
signal.
The PWM0GENA register controls generation of the pwm0A signal; PWM1GENA, the pwm1A
signal; PWM2GENA, the pwm2A signal; and PWM3GENA, the pwm3A signal.
If a zero or load event coincides with a compare A or compare B event, the zero or load action is
taken and the compare A or compare B action is ignored. If a compare A event coincides with a
compare B event, the compare A action is taken and the compare B action is ignored.
If the Generator A update mode is immediate (based on the GENAUPD field encoding in the PWMnCTL
register), the ACTCMPBD, ACTCMPBU, ACTCMPAD, ACTCMPAU, ACTLOAD, and ACTZERO values are
used immediately. If the update mode is locally synchronized, these values are used the next time
the counter reaches zero. If the update mode is globally synchronized, these values are used the
next time the counter reaches zero after a synchronous update has been requested through the
PWM Master Control (PWMCTL) register (see page 1147). If this register is rewritten before the
actual update occurs, the previous value is never used and is lost.
PWMn Generator A Control (PWMnGENA)
PWM0 base: 0x4002.8000
PWM1 base: 0x4002.9000
Offset 0x060
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
reserved
Type
Reset
RO
0
RO
0
ACTCMPBD
RO
0
RO
0
RW
0
RW
0
RO
0
RO
0
9
8
ACTCMPBU
RW
0
Bit/Field
Name
Type
Reset
31:12
reserved
RO
0x0000.0
RW
0
ACTCMPAD
RW
0
RW
0
ACTCMPAU
RW
0
RW
0
ACTLOAD
RW
0
RW
0
ACTZERO
RW
0
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1188
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Bit/Field
Name
Type
Reset
11:10
ACTCMPBD
RW
0x0
Description
Action for Comparator B Down
This field specifies the action to be taken when the counter matches
comparator B while counting down.
Value Description
9:8
ACTCMPBU
RW
0x0
0x0
Do nothing.
0x1
Invert pwmA.
0x2
Drive pwmA Low.
0x3
Drive pwmA High.
Action for Comparator B Up
This field specifies the action to be taken when the counter matches
comparator B while counting up. This action can only occur when the
MODE bit in the PWMnCTL register is set.
Value Description
7:6
ACTCMPAD
RW
0x0
0x0
Do nothing.
0x1
Invert pwmA.
0x2
Drive pwmA Low.
0x3
Drive pwmA High.
Action for Comparator A Down
This field specifies the action to be taken when the counter matches
comparator A while counting down.
Value Description
5:4
ACTCMPAU
RW
0x0
0x0
Do nothing.
0x1
Invert pwmA.
0x2
Drive pwmA Low.
0x3
Drive pwmA High.
Action for Comparator A Up
This field specifies the action to be taken when the counter matches
comparator A while counting up. This action can only occur when the
MODE bit in the PWMnCTL register is set.
Value Description
0x0
Do nothing.
0x1
Invert pwmA.
0x2
Drive pwmA Low.
0x3
Drive pwmA High.
June 12, 2014
1189
Texas Instruments-Production Data
Pulse Width Modulator (PWM)
Bit/Field
Name
Type
Reset
3:2
ACTLOAD
RW
0x0
Description
Action for Counter=LOAD
This field specifies the action to be taken when the counter matches the
value in the PWMnLOAD register.
Value Description
1:0
ACTZERO
RW
0x0
0x0
Do nothing.
0x1
Invert pwmA.
0x2
Drive pwmA Low.
0x3
Drive pwmA High.
Action for Counter=0
This field specifies the action to be taken when the counter is zero.
Value Description
0x0
Do nothing.
0x1
Invert pwmA.
0x2
Drive pwmA Low.
0x3
Drive pwmA High.
1190
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Register 48: PWM0 Generator B Control (PWM0GENB), offset 0x064
Register 49: PWM1 Generator B Control (PWM1GENB), offset 0x0A4
Register 50: PWM2 Generator B Control (PWM2GENB), offset 0x0E4
Register 51: PWM3 Generator B Control (PWM3GENB), offset 0x124
These registers control the generation of the pwmB signal based on the load and zero output pulses
from the counter, as well as the compare A and compare B pulses from the comparators
(PWM0GENB controls the PWM generator 0 block, and so on). When the counter is running in
Count-Down mode, only four of these events occur; when running in Count-Up/Down mode, all six
occur. These events provide great flexibility in the positioning and duty cycle of the resulting PWM
signal.
The PWM0GENB register controls generation of the pwm0B signal; PWM1GENB, the pwm1B
signal; PWM2GENB, the pwm2B signal; and PWM3GENB, the pwm3B signal.
If a zero or load event coincides with a compare A or compare B event, the zero or load action is
taken and the compare A or compare B action is ignored. If a compare A event coincides with a
compare B event, the compare B action is taken and the compare A action is ignored.
If the Generator B update mode is immediate (based on the GENBUPD field encoding in the PWMnCTL
register), the ACTCMPBD, ACTCMPBU, ACTCMPAD, ACTCMPAU, ACTLOAD, and ACTZERO values are
used immediately. If the update mode is locally synchronized, these values are used the next time
the counter reaches zero. If the update mode is globally synchronized, these values are used the
next time the counter reaches zero after a synchronous update has been requested through the
PWM Master Control (PWMCTL) register (see page 1147). If this register is rewritten before the
actual update occurs, the previous value is never used and is lost.
PWMn Generator B Control (PWMnGENB), offset 0x064
PWM0 base: 0x4002.8000
PWM1 base: 0x4002.9000
Offset 0x064
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
reserved
Type
Reset
RO
0
RO
0
ACTCMPBD
RO
0
RO
0
RW
0
RW
0
RO
0
RO
0
9
8
ACTCMPBU
RW
0
Bit/Field
Name
Type
Reset
31:12
reserved
RO
0x0000.0
RW
0
ACTCMPAD
RW
0
RW
0
ACTCMPAU
RW
0
RW
0
ACTLOAD
RW
0
RW
0
ACTZERO
RW
0
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
June 12, 2014
1191
Texas Instruments-Production Data
Pulse Width Modulator (PWM)
Bit/Field
Name
Type
Reset
11:10
ACTCMPBD
RW
0x0
Description
Action for Comparator B Down
This field specifies the action to be taken when the counter matches
comparator B while counting down.
Value Description
9:8
ACTCMPBU
RW
0x0
0x0
Do nothing.
0x1
Invert pwmB.
0x2
Drive pwmB Low.
0x3
Drive pwmB High.
Action for Comparator B Up
This field specifies the action to be taken when the counter matches
comparator B while counting up. This action can only occur when the
MODE bit in the PWMnCTL register is set.
Value Description
7:6
ACTCMPAD
RW
0x0
0x0
Do nothing.
0x1
Invert pwmB.
0x2
Drive pwmB Low.
0x3
Drive pwmB High.
Action for Comparator A Down
This field specifies the action to be taken when the counter matches
comparator A while counting down.
Value Description
5:4
ACTCMPAU
RW
0x0
0x0
Do nothing.
0x1
Invert pwmB.
0x2
Drive pwmB Low.
0x3
Drive pwmB High.
Action for Comparator A Up
This field specifies the action to be taken when the counter matches
comparator A while counting up. This action can only occur when the
MODE bit in the PWMnCTL register is set.
Value Description
0x0
Do nothing.
0x1
Invert pwmB.
0x2
Drive pwmB Low.
0x3
Drive pwmB High.
1192
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Bit/Field
Name
Type
Reset
3:2
ACTLOAD
RW
0x0
Description
Action for Counter=LOAD
This field specifies the action to be taken when the counter matches the
load value.
Value Description
1:0
ACTZERO
RW
0x0
0x0
Do nothing.
0x1
Invert pwmB.
0x2
Drive pwmB Low.
0x3
Drive pwmB High.
Action for Counter=0
This field specifies the action to be taken when the counter is 0.
Value Description
0x0
Do nothing.
0x1
Invert pwmB.
0x2
Drive pwmB Low.
0x3
Drive pwmB High.
June 12, 2014
1193
Texas Instruments-Production Data
Pulse Width Modulator (PWM)
Register 52: PWM0 Dead-Band Control (PWM0DBCTL), offset 0x068
Register 53: PWM1 Dead-Band Control (PWM1DBCTL), offset 0x0A8
Register 54: PWM2 Dead-Band Control (PWM2DBCTL), offset 0x0E8
Register 55: PWM3 Dead-Band Control (PWM3DBCTL), offset 0x128
The PWMnDBCTL register controls the dead-band generator, which produces the MnPWMn signals
based on the pwmA and pwmB signals. When disabled, the pwmA signal passes through to the
pwmA' signal and the pwmB signal passes through to the pwmB' signal. When dead-band control
is enabled, the pwmB signal is ignored, the pwmA' signal is generated by delaying the rising edge(s)
of the pwmA signal by the value in the PWMnDBRISE register (see page 1195), and the pwmB' signal
is generated by inverting the pwmA signal and delaying the falling edge(s) of the pwmA signal by
the value in the PWMnDBFALL register (see page 1196). The Output Control block outputs the pwm0A'
signal on the MnPWM0 signal and the pwm0B' signal on the MnPWM1 signal. In a similar manner,
MnPWM2 and MnPWM3 are produced from the pwm1A' and pwm1B' signals, MnPWM4 and MnPWM5
are produced from the pwm2A' and pwm2B' signals, and MnPWM6 and MnPWM7 are produced from
the pwm3A' and pwm3B' signals.
If the Dead-Band Control mode is immediate (based on the DBCTLUPD field encoding in the
PWMnCTL register), the ENABLE bit value is used immediately. If the update mode is locally
synchronized, this value is used the next time the counter reaches zero. If the update mode is
globally synchronized, this value is used the next time the counter reaches zero after a synchronous
update has been requested through the PWM Master Control (PWMCTL) register (see page 1147).
If this register is rewritten before the actual update occurs, the previous value is never used and is
lost.
PWMn Dead-Band Control (PWMnDBCTL)
PWM0 base: 0x4002.8000
PWM1 base: 0x4002.9000
Offset 0x068
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:1
reserved
RO
0x0000.000
0
ENABLE
RW
0
RO
0
0
ENABLE
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Dead-Band Generator Enable
Value Description
0
The pwmA and pwmB signals pass through to the pwmA' and
pwmB' signals unmodified.
1
The dead-band generator modifies the pwmA signal by inserting
dead bands into the pwmA' and pwmB' signals.
1194
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Register 56: PWM0 Dead-Band Rising-Edge Delay (PWM0DBRISE), offset
0x06C
Register 57: PWM1 Dead-Band Rising-Edge Delay (PWM1DBRISE), offset
0x0AC
Register 58: PWM2 Dead-Band Rising-Edge Delay (PWM2DBRISE), offset
0x0EC
Register 59: PWM3 Dead-Band Rising-Edge Delay (PWM3DBRISE), offset
0x12C
The PWMnDBRISE register contains the number of clock cycles to delay the rising edge of the
pwmA signal when generating the pwmA' signal. If the dead-band generator is disabled through the
PWMnDBCTL register, this register is ignored. If the value of this register is larger than the width
of a High pulse on the pwmA signal, the rising-edge delay consumes the entire High time of the
signal, resulting in no High time on the output. Care must be taken to ensure that the pwmA High
time always exceeds the rising-edge delay.
If the Dead-Band Rising-Edge Delay mode is immediate (based on the DBRISEUPD field encoding
in the PWMnCTL register), the 12-bit RISEDELAY value is used immediately. If the update mode
is locally synchronized, this value is used the next time the counter reaches zero. If the update mode
is globally synchronized, this value is used the next time the counter reaches zero after a synchronous
update has been requested through the PWM Master Control (PWMCTL) register (see page 1147).
If this register is rewritten before the actual update occurs, the previous value is never used and is
lost.
PWMn Dead-Band Rising-Edge Delay (PWMnDBRISE)
PWM0 base: 0x4002.8000
PWM1 base: 0x4002.9000
Offset 0x06C
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
6
5
4
3
2
1
0
RW
0
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
reserved
Type
Reset
RO
0
RO
0
RISEDELAY
RO
0
RO
0
RW
0
RW
0
RW
0
Bit/Field
Name
Type
Reset
31:12
reserved
RO
0x0000.0
11:0
RISEDELAY
RW
0x000
RW
0
RW
0
RW
0
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Dead-Band Rise Delay
The number of clock cycles to delay the rising edge of pwmA' after the
rising edge of pwmA.
June 12, 2014
1195
Texas Instruments-Production Data
Pulse Width Modulator (PWM)
Register 60: PWM0 Dead-Band Falling-Edge-Delay (PWM0DBFALL), offset
0x070
Register 61: PWM1 Dead-Band Falling-Edge-Delay (PWM1DBFALL), offset
0x0B0
Register 62: PWM2 Dead-Band Falling-Edge-Delay (PWM2DBFALL), offset
0x0F0
Register 63: PWM3 Dead-Band Falling-Edge-Delay (PWM3DBFALL), offset
0x130
The PWMnDBFALL register contains the number of clock cycles to delay the rising edge of the
pwmB' signal from the falling edge of the pwmA signal. If the dead-band generator is disabled
through the PWMnDBCTL register, this register is ignored. If the value of this register is larger than
the width of a Low pulse on the pwmA signal, the falling-edge delay consumes the entire Low time
of the signal, resulting in no Low time on the output. Care must be taken to ensure that the pwmA
Low time always exceeds the falling-edge delay.
If the Dead-Band Falling-Edge-Delay mode is immediate (based on the DBFALLUP field encoding
in the PWMnCTL register), the 12-bit FALLDELAY value is used immediately. If the update mode
is locally synchronized, this value is used the next time the counter reaches zero. If the update mode
is globally synchronized, this value is used the next time the counter reaches zero after a synchronous
update has been requested through the PWM Master Control (PWMCTL) register (see page 1147).
If this register is rewritten before the actual update occurs, the previous value is never used and is
lost.
PWMn Dead-Band Falling-Edge-Delay (PWMnDBFALL)
PWM0 base: 0x4002.8000
PWM1 base: 0x4002.9000
Offset 0x070
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
6
5
4
3
2
1
0
RW
0
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
reserved
Type
Reset
RO
0
RO
0
FALLDELAY
RO
0
RO
0
RW
0
RW
0
RW
0
Bit/Field
Name
Type
Reset
31:12
reserved
RO
0x0000.0
11:0
FALLDELAY
RW
0x000
RW
0
RW
0
RW
0
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Dead-Band Fall Delay
The number of clock cycles to delay the falling edge of pwmB' from the
rising edge of pwmA.
1196
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Register 64: PWM0 Fault Source 0 (PWM0FLTSRC0), offset 0x074
Register 65: PWM1 Fault Source 0 (PWM1FLTSRC0), offset 0x0B4
Register 66: PWM2 Fault Source 0 (PWM2FLTSRC0), offset 0x0F4
Register 67: PWM3 Fault Source 0 (PWM3FLTSRC0), offset 0x134
This register specifies which fault pin inputs are used to generate a fault condition. Each bit in the
following register indicates whether the corresponding fault pin is included in the fault condition. All
enabled fault pins are ORed together to form the PWMnFLTSRC0 portion of the fault condition.
The PWMnFLTSRC0 fault condition is then ORed with the PWMnFLTSRC1 fault condition to
generate the final fault condition for the PWM generator.
If the FLTSRC bit in the PWMnCTL register (see page 1172) is clear, only the Fault0 signal affects
the fault condition generated. Otherwise, sources defined in PWMnFLTSRC0 and PWMnFLTSRC1
affect the fault condition generated.
PWMn Fault Source 0 (PWMnFLTSRC0)
PWM0 base: 0x4002.8000
PWM1 base: 0x4002.9000
Offset 0x074
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
3
2
1
0
FAULT3
FAULT2
FAULT1
FAULT0
RW
0
RW
0
RW
0
RW
0
Bit/Field
Name
Type
Reset
Description
31:4
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
FAULT3
RW
0
Fault3 Input
Value Description
0
The Fault3 signal is suppressed and cannot generate a fault
condition.
1
The Fault3 signal value is ORed with all other fault condition
generation inputs (Faultn signals and digital comparators).
Note:
The FLTSRC bit in the PWMnCTL register must be set for this
bit to affect fault condition generation.
June 12, 2014
1197
Texas Instruments-Production Data
Pulse Width Modulator (PWM)
Bit/Field
Name
Type
Reset
2
FAULT2
RW
0
Description
Fault2 Input
Value Description
0
The Fault2 signal is suppressed and cannot generate a fault
condition.
1
The Fault2 signal value is ORed with all other fault condition
generation inputs (Faultn signals and digital comparators).
Note:
1
FAULT1
RW
0
The FLTSRC bit in the PWMnCTL register must be set for this
bit to affect fault condition generation.
Fault1 Input
Value Description
0
The Fault1 signal is suppressed and cannot generate a fault
condition.
1
The Fault1 signal value is ORed with all other fault condition
generation inputs (Faultn signals and digital comparators).
Note:
0
FAULT0
RW
0
The FLTSRC bit in the PWMnCTL register must be set for this
bit to affect fault condition generation.
Fault0 Input
Value Description
0
The Fault0 signal is suppressed and cannot generate a fault
condition.
1
The Fault0 signal value is ORed with all other fault condition
generation inputs (Faultn signals and digital comparators).
Note:
The FLTSRC bit in the PWMnCTL register must be set for this
bit to affect fault condition generation.
1198
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Register 68: PWM0 Fault Source 1 (PWM0FLTSRC1), offset 0x078
Register 69: PWM1 Fault Source 1 (PWM1FLTSRC1), offset 0x0B8
Register 70: PWM2 Fault Source 1 (PWM2FLTSRC1), offset 0x0F8
Register 71: PWM3 Fault Source 1 (PWM3FLTSRC1), offset 0x138
This register specifies which digital comparator triggers from the ADC are used to generate a fault
condition. Each bit in the following register indicates whether the corresponding digital comparator
trigger is included in the fault condition. All enabled digital comparator triggers are ORed together
to form the PWMnFLTSRC1 portion of the fault condition. The PWMnFLTSRC1 fault condition is
then ORed with the PWMnFLTSRC0 fault condition to generate the final fault condition for the PWM
generator.
If the FLTSRC bit in the PWMnCTL register (see page 1172) is clear, only the PWM Fault0 pin affects
the fault condition generated. Otherwise, sources defined in PWMnFLTSRC0 and PWMnFLTSRC1
affect the fault condition generated.
PWMn Fault Source 1 (PWMnFLTSRC1)
PWM0 base: 0x4002.8000
PWM1 base: 0x4002.9000
Offset 0x078
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7
DCMP7
RW
0
RO
0
7
6
5
4
3
2
1
0
DCMP7
DCMP6
DCMP5
DCMP4
DCMP3
DCMP2
DCMP1
DCMP0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Digital Comparator 7
Value Description
0
The trigger from digital comparator 7 is suppressed and cannot
generate a fault condition.
1
The trigger from digital comparator 7 is ORed with all other fault
condition generation inputs (Faultn signals and digital
comparators).
Note:
The FLTSRC bit in the PWMnCTL register must be set for this
bit to affect fault condition generation.
June 12, 2014
1199
Texas Instruments-Production Data
Pulse Width Modulator (PWM)
Bit/Field
Name
Type
Reset
6
DCMP6
RW
0
Description
Digital Comparator 6
Value Description
0
The trigger from digital comparator 6 is suppressed and cannot
generate a fault condition.
1
The trigger from digital comparator 6 is ORed with all other fault
condition generation inputs (Faultn signals and digital
comparators).
Note:
5
DCMP5
RW
0
The FLTSRC bit in the PWMnCTL register must be set for this
bit to affect fault condition generation.
Digital Comparator 5
Value Description
0
The trigger from digital comparator 5 is suppressed and cannot
generate a fault condition.
1
The trigger from digital comparator 5 is ORed with all other fault
condition generation inputs (Faultn signals and digital
comparators).
Note:
4
DCMP4
RW
0
The FLTSRC bit in the PWMnCTL register must be set for this
bit to affect fault condition generation.
Digital Comparator 4
Value Description
0
The trigger from digital comparator 4 is suppressed and cannot
generate a fault condition.
1
The trigger from digital comparator 4 is ORed with all other fault
condition generation inputs (Faultn signals and digital
comparators).
Note:
3
DCMP3
RW
0
The FLTSRC bit in the PWMnCTL register must be set for this
bit to affect fault condition generation.
Digital Comparator 3
Value Description
0
The trigger from digital comparator 3 is suppressed and cannot
generate a fault condition.
1
The trigger from digital comparator 3 is ORed with all other fault
condition generation inputs (Faultn signals and digital
comparators).
Note:
The FLTSRC bit in the PWMnCTL register must be set for this
bit to affect fault condition generation.
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Tiva™ TM4C123BH6PGE Microcontroller
Bit/Field
Name
Type
Reset
2
DCMP2
RW
0
Description
Digital Comparator 2
Value Description
0
The trigger from digital comparator 2 is suppressed and cannot
generate a fault condition.
1
The trigger from digital comparator 2 is ORed with all other fault
condition generation inputs (Faultn signals and digital
comparators).
Note:
1
DCMP1
RW
0
The FLTSRC bit in the PWMnCTL register must be set for this
bit to affect fault condition generation.
Digital Comparator 1
Value Description
0
The trigger from digital comparator 1 is suppressed and cannot
generate a fault condition.
1
The trigger from digital comparator 1 is ORed with all other fault
condition generation inputs (Faultn signals and digital
comparators).
Note:
0
DCMP0
RW
0
The FLTSRC bit in the PWMnCTL register must be set for this
bit to affect fault condition generation.
Digital Comparator 0
Value Description
0
The trigger from digital comparator 0 is suppressed and cannot
generate a fault condition.
1
The trigger from digital comparator 0 is ORed with all other fault
condition generation inputs (Faultn signals and digital
comparators).
Note:
The FLTSRC bit in the PWMnCTL register must be set for this
bit to affect fault condition generation.
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Texas Instruments-Production Data
Pulse Width Modulator (PWM)
Register 72: PWM0 Minimum Fault Period (PWM0MINFLTPER), offset 0x07C
Register 73: PWM1 Minimum Fault Period (PWM1MINFLTPER), offset 0x0BC
Register 74: PWM2 Minimum Fault Period (PWM2MINFLTPER), offset 0x0FC
Register 75: PWM3 Minimum Fault Period (PWM3MINFLTPER), offset 0x13C
If the MINFLTPER bit in the PWMnCTL register is set, this register specifies the 16-bit time-extension
value to be used in extending the fault condition. The value is loaded into a 16-bit down counter,
and the counter value is used to extend the fault condition. The fault condition is released in the
clock immediately after the counter value reaches 0. The fault condition is asynchronous to the
PWM clock; and the delay value is the product of the PWM clock period and the (MFP field value
+ 1) or (MFP field value + 2) depending on when the fault condition asserts with respect to the PWM
clock. The counter decrements at the PWM clock rate, without pause or condition.
PWMn Minimum Fault Period (PWMnMINFLTPER)
PWM0 base: 0x4002.8000
PWM1 base: 0x4002.9000
Offset 0x07C
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
MFP
Type
Reset
Bit/Field
Name
Type
Reset
Description
31:16
reserved
RO
0x0000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:0
MFP
RW
0x0000
Minimum Fault Period
The number of PWM clocks by which a fault condition is extended when
the delay is enabled by PWMnCTL MINFLTPER.
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Tiva™ TM4C123BH6PGE Microcontroller
Register 76: PWM0 Fault Pin Logic Sense (PWM0FLTSEN), offset 0x800
Register 77: PWM1 Fault Pin Logic Sense (PWM1FLTSEN), offset 0x880
Register 78: PWM2 Fault Pin Logic Sense (PWM2FLTSEN), offset 0x900
Register 79: PWM3 Fault Pin Logic Sense (PWM3FLTSEN), offset 0x980
This register defines the PWM fault pin logic sense.
PWMn Fault Pin Logic Sense (PWMnFLTSEN)
PWM0 base: 0x4002.8000
PWM1 base: 0x4002.9000
Offset 0x800
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
FAULT3
FAULT2
FAULT1
FAULT0
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:4
reserved
RO
0x0000.000
3
FAULT3
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Fault3 Sense
Value Description
2
FAULT2
RW
0
0
An error is indicated if the Fault3 signal is High.
1
An error is indicated if the Fault3 signal is Low.
Fault2 Sense
Value Description
1
FAULT1
RW
0
0
An error is indicated if the Fault2 signal is High.
1
An error is indicated if the Fault2 signal is Low.
Fault1 Sense
Value Description
0
FAULT0
RW
0
0
An error is indicated if the Fault1 signal is High.
1
An error is indicated if the Fault1 signal is Low.
Fault0 Sense
Value Description
0
An error is indicated if the Fault0 signal is High.
1
An error is indicated if the Fault0 signal is Low.
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Texas Instruments-Production Data
Pulse Width Modulator (PWM)
Register 80: PWM0 Fault Status 0 (PWM0FLTSTAT0), offset 0x804
Register 81: PWM1 Fault Status 0 (PWM1FLTSTAT0), offset 0x884
Register 82: PWM2 Fault Status 0 (PWM2FLTSTAT0), offset 0x904
Register 83: PWM3 Fault Status 0 (PWM3FLTSTAT0), offset 0x984
Along with the PWMnFLTSTAT1 register, this register provides status regarding the fault condition
inputs.
If the LATCH bit in the PWMnCTL register is clear, the contents of the PWMnFLTSTAT0 register
are read-only (RO) and provide the current state of the MnFAULTn inputs.
If the LATCH bit in the PWMnCTL register is set, the contents of the PWMnFLTSTAT0 register are
read / write 1 to clear (RW1C) and provide a latched version of the MnFAULTn inputs. In this mode,
the register bits are cleared by writing a 1 to a set bit. The MnFAULTn inputs are recorded after their
sense is adjusted in the generator.
The contents of this register can only be written if the fault source extensions are enabled (the
FLTSRC bit in the PWMnCTL register is set).
Note:
The fault status registers, PWMnFLTSTAT0 and PWMnFLTSTAT1, reflect the status of all
fault sources, regardless of what fault sources are enabled for that particular generator.
PWMn Fault Status 0 (PWMnFLTSTAT0)
PWM0 base: 0x4002.8000
PWM1 base: 0x4002.9000
Offset 0x804
Type -, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
FAULT3
FAULT2
FAULT1
FAULT0
RO
0
RO
0
RO
0
RO
0
RO
0
0
0
0
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
Description
31:4
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
FAULT3
-
0
Fault Input 3
If the PWMnCTL register LATCH bit is clear, this bit is RO and represents
the current state of the MnFAULT3 input signal after the logic sense
adjustment.
If the PWMnCTL register LATCH bit is set, this bit is RW1C and
represents a sticky version of the MnFAULT3 input signal after the logic
sense adjustment.
■
If FAULT3 is set, the input transitioned to the active state previously.
■
If FAULT3 is clear, the input has not transitioned to the active state
since the last time it was cleared.
■
The FAULT3 bit is cleared by writing it with the value 1.
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Tiva™ TM4C123BH6PGE Microcontroller
Bit/Field
Name
Type
Reset
Description
2
FAULT2
-
0
Fault Input 2
If the PWMnCTL register LATCH bit is clear, this bit is RO and represents
the current state of the MnFAULT2 input signal after the logic sense
adjustment.
If the PWMnCTL register LATCH bit is set, this bit is RW1C and
represents a sticky version of the MnFAULT2 input signal after the logic
sense adjustment.
1
FAULT1
-
0
■
If FAULT2 is set, the input transitioned to the active state previously.
■
If FAULT2 is clear, the input has not transitioned to the active state
since the last time it was cleared.
■
The FAULT2 bit is cleared by writing it with the value 1.
Fault Input 1
If the PWMnCTL register LATCH bit is clear, this bit is RO and represents
the current state of the MnFAULT1 input signal after the logic sense
adjustment.
If the PWMnCTL register LATCH bit is set, this bit is RW1C and
represents a sticky version of the MnFAULT1 input signal after the logic
sense adjustment.
0
FAULT0
-
0
■
If FAULT1 is set, the input transitioned to the active state previously.
■
If FAULT1 is clear, the input has not transitioned to the active state
since the last time it was cleared.
■
The FAULT1 bit is cleared by writing it with the value 1.
Fault Input 0
If the PWMnCTL register LATCH bit is clear, this bit is RO and represents
the current state of the input signal after the logic sense adjustment.
If the PWMnCTL register LATCH bit is set, this bit is RW1C and
represents a sticky version of the input signal after the logic sense
adjustment.
■
If FAULT0 is set, the input transitioned to the active state previously.
■
If FAULT0 is clear, the input has not transitioned to the active state
since the last time it was cleared.
■
The FAULT0 bit is cleared by writing it with the value 1.
June 12, 2014
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Texas Instruments-Production Data
Pulse Width Modulator (PWM)
Register 84: PWM0 Fault Status 1 (PWM0FLTSTAT1), offset 0x808
Register 85: PWM1 Fault Status 1 (PWM1FLTSTAT1), offset 0x888
Register 86: PWM2 Fault Status 1 (PWM2FLTSTAT1), offset 0x908
Register 87: PWM3 Fault Status 1 (PWM3FLTSTAT1), offset 0x988
Along with the PWMnFLTSTAT0 register, this register provides status regarding the fault condition
inputs.
If the LATCH bit in the PWMnCTL register is clear, the contents of the PWMnFLTSTAT1 register
are read-only (RO) and provide the current state of the digital comparator triggers.
If the LATCH bit in the PWMnCTL register is set, the contents of the PWMnFLTSTAT1 register are
read / write 1 to clear (RW1C) and provide a latched version of the digital comparator triggers. In
this mode, the register bits are cleared by writing a 1 to a set bit. The contents of this register can
only be written if the fault source extensions are enabled (the FLTSRC bit in the PWMnCTL register
is set).
Note:
The fault status registers, PWMnFLTSTAT0 and PWMnFLTSTAT1, reflect the status of all
fault sources, regardless of what fault sources are enabled for that particular generator.
PWMn Fault Status 1 (PWMnFLTSTAT1)
PWM0 base: 0x4002.8000
PWM1 base: 0x4002.9000
Offset 0x808
Type -, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7
DCMP7
-
0
RO
0
RO
0
7
6
5
4
3
2
1
0
DCMP7
DCMP6
DCMP5
DCMP4
DCMP3
DCMP2
DCMP1
DCMP0
0
0
0
0
0
0
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Digital Comparator 7 Trigger
If the PWMnCTL register LATCH bit is clear, this bit represents the
current state of the Digital Comparator 7 trigger input.
If the PWMnCTL register LATCH bit is set, this bit represents a sticky
version of the trigger.
■
If DCMP7 is set, the trigger transitioned to the active state previously.
■
If DCMP7 is clear, the trigger has not transitioned to the active state
since the last time it was cleared.
■
The DCMP7 bit is cleared by writing it with the value 1.
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Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Bit/Field
Name
Type
Reset
6
DCMP6
-
0
Description
Digital Comparator 6 Trigger
If the PWMnCTL register LATCH bit is clear, this bit represents the
current state of the Digital Comparator 6 trigger input.
If the PWMnCTL register LATCH bit is set, this bit represents a sticky
version of the trigger.
5
DCMP5
-
0
■
If DCMP6 is set, the trigger transitioned to the active state previously.
■
If DCMP6 is clear, the trigger has not transitioned to the active state
since the last time it was cleared.
■
The DCMP6 bit is cleared by writing it with the value 1.
Digital Comparator 5 Trigger
If the PWMnCTL register LATCH bit is clear, this bit represents the
current state of the Digital Comparator 5 trigger input.
If the PWMnCTL register LATCH bit is set, this bit represents a sticky
version of the trigger.
4
DCMP4
-
0
■
If DCMP5 is set, the trigger transitioned to the active state previously.
■
If DCMP5 is clear, the trigger has not transitioned to the active state
since the last time it was cleared.
■
The DCMP5 bit is cleared by writing it with the value 1.
Digital Comparator 4 Trigger
If the PWMnCTL register LATCH bit is clear, this bit represents the
current state of the Digital Comparator 4 trigger input.
If the PWMnCTL register LATCH bit is set, this bit represents a sticky
version of the trigger.
3
DCMP3
-
0
■
If DCMP4 is set, the trigger transitioned to the active state previously.
■
If DCMP4 is clear, the trigger has not transitioned to the active state
since the last time it was cleared.
■
The DCMP4 bit is cleared by writing it with the value 1.
Digital Comparator 3 Trigger
If the PWMnCTL register LATCH bit is clear, this bit represents the
current state of the Digital Comparator 3 trigger input.
If the PWMnCTL register LATCH bit is set, this bit represents a sticky
version of the trigger.
■
If DCMP3 is set, the trigger transitioned to the active state previously.
■
If DCMP3 is clear, the trigger has not transitioned to the active state
since the last time it was cleared.
■
The DCMP3 bit is cleared by writing it with the value 1.
June 12, 2014
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Texas Instruments-Production Data
Pulse Width Modulator (PWM)
Bit/Field
Name
Type
Reset
2
DCMP2
-
0
Description
Digital Comparator 2 Trigger
If the PWMnCTL register LATCH bit is clear, this bit represents the
current state of the Digital Comparator 2 trigger input.
If the PWMnCTL register LATCH bit is set, this bit represents a sticky
version of the trigger.
1
DCMP1
-
0
■
If DCMP2 is set, the trigger transitioned to the active state previously.
■
If DCMP2 is clear, the trigger has not transitioned to the active state
since the last time it was cleared.
■
The DCMP2 bit is cleared by writing it with the value 1.
Digital Comparator 1 Trigger
If the PWMnCTL register LATCH bit is clear, this bit represents the
current state of the Digital Comparator 1 trigger input.
If the PWMnCTL register LATCH bit is set, this bit represents a sticky
version of the trigger.
0
DCMP0
-
0
■
If DCMP1 is set, the trigger transitioned to the active state previously.
■
If DCMP1 is clear, the trigger has not transitioned to the active state
since the last time it was cleared.
■
The DCMP1 bit is cleared by writing it with the value 1.
Digital Comparator 0 Trigger
If the PWMnCTL register LATCH bit is clear, this bit represents the
current state of the Digital Comparator 0 trigger input.
If the PWMnCTL register LATCH bit is set, this bit represents a sticky
version of the trigger.
■
If DCMP0 is set, the trigger transitioned to the active state previously.
■
If DCMP0 is clear, the trigger has not transitioned to the active state
since the last time it was cleared.
■
The DCMP0 bit is cleared by writing it with the value 1.
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Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Register 88: PWM Peripheral Properties (PWMPP), offset 0xFC0
The PWMPP register provides information regarding the properties of the PWM module.
PWM Peripheral Properties (PWMPP)
PWM0 base: 0x4002.8000
PWM1 base: 0x4002.9000
Offset 0xFC0
Type RO, reset 0x0000.0344
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
ONE
EFAULT
ESYNC
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
1
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
1
RO
0
RO
0
RO
0
RO
1
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
FCNT
GCNT
Bit/Field
Name
Type
Reset
Description
31:11
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
10
ONE
RO
0x0
One-Shot Mode
Value Description
9
EFAULT
RO
0x1
0
One-shot modes are not available.
1
One-shot modes are available.
Extended Fault
Value Description
8
ESYNC
RO
0x1
0
Extended fault capabilities are not available.
1
Extended fault capabilities are available.
Extended Synchronization
Value Description
7:4
FCNT
RO
0x4
0
Extended synchronization is not available.
1
Extended synchronization is available.
Fault Inputs
Value
Description
0x0
No fault inputs.
0x1
1 fault input.
0x2
2 fault input.
0x3
3 fault input.
0x4
4 fault input.
0x5 - 0xF reserved
June 12, 2014
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Texas Instruments-Production Data
Pulse Width Modulator (PWM)
Bit/Field
Name
Type
Reset
Description
3:0
GCNT
RO
0x4
Generators
Value
Description
0x0
No generators.
0x1
1 generator
0x2
2 generators
0x3
3 generators
0x4
4 generators
0x5 - 0xF reserved
The number of PWM outputs is 2 times the number of PWM generators.
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Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
20
Quadrature Encoder Interface (QEI)
A quadrature encoder, also known as a 2-channel incremental encoder, converts linear displacement
into a pulse signal. By monitoring both the number of pulses and the relative phase of the two signals,
you can track the position, direction of rotation, and speed. In addition, a third channel, or index
signal, can be used to reset the position counter.
The TM4C123BH6PGE microcontroller includes two quadrature encoder interface (QEI) modules.
Each QEI module interprets the code produced by a quadrature encoder wheel to integrate position
over time and determine direction of rotation. In addition, it can capture a running estimate of the
velocity of the encoder wheel.
The TM4C123BH6PGE microcontroller includes two QEI modules providing control of two motors
at the same time with the following features:
■ Position integrator that tracks the encoder position
■ Programmable noise filter on the inputs
■ Velocity capture using built-in timer
■ The input frequency of the QEI inputs may be as high as 1/4 of the processor frequency (for
example, 12.5 MHz for a 50-MHz system)
■ Interrupt generation on:
– Index pulse
– Velocity-timer expiration
– Direction change
– Quadrature error detection
20.1
Block Diagram
Figure 20-1 on page 1212 provides an internal block diagram of a TM4C123BH6PGE QEI module.
The PhA and PhB inputs shown in this diagram are the internal signals that enter the Quadrature
Encoder after the external signals, PhAn and PhBn, have passed through inversion and swapping
logic shown in Figure 20-2 on page 1213. The QEI module has the option of inverting and/or swapping
the incoming signals.
Note:
Any references in this chapter to PhA and PhB refer to the internal PhA and PhB inputs that
enter the Quadrature Encoder after the external signals, PhAn and PhBn, have passed
through inversion and swapping logic that is enabled through the QEI Control (QEICTL)
register.
June 12, 2014
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Texas Instruments-Production Data
Quadrature Encoder Interface (QEI)
Figure 20-1. QEI Block Diagram
QEILOAD
Velocity Timer
Control & Status
QEITIME
QEICTL
QEISTAT
Velocity Accumulator
Velocity
Predivider
PhA
PhB
QEICOUNT
QEISPEED
clk
Quadrature
Encoder dir
QEIMAXPOS
Position Integrator
QEIPOS
IDX
QEIINTEN
Interrupt Control
Interrupt
QEIRIS
QEIISC
Figure 20-2 on page 1213 shows the logic that is provided to allow the PhAn and PhBn signals to be
inverted and/or swapped.
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Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Figure 20-2. QEI Input Signal Logic
PhAn
QEICTL.INVA
1
0
QEICTL.INVB
QEICTL.SWAP
PhA
PhBn
1
PhB
clk
Quadrature
Encoder
dir
0
QEICTL.SWAP
20.2
Signal Description
The following table lists the external signals of the QEI module and describes the function of each.
The QEI signals are alternate functions for some GPIO signals and default to be GPIO signals at
reset. The column in the table below titled "Pin Mux/Pin Assignment" lists the possible GPIO pin
placements for these QEI signals. The AFSEL bit in the GPIO Alternate Function Select
(GPIOAFSEL) register (page 676) should be set to choose the QEI function. The number in
parentheses is the encoding that must be programmed into the PMCn field in the GPIO Port Control
(GPIOPCTL) register (page 695) to assign the QEI signal to the specified GPIO port pin. For more
information on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 647.
Table 20-1. QEI Signals (144LQFP)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
IDX0
4
31
61
122
PD3 (6)
PH1 (5)
PF4 (6)
PJ2 (5)
I
TTL
QEI module 0 index.
IDX1
36
47
50
PC4 (6)
PG7 (5)
PG5 (6)
I
TTL
QEI module 1 index.
PhA0
26
62
143
PH4 (5)
PF0 (6)
PD6 (6)
I
TTL
QEI module 0 phase A.
PhA1
35
52
55
PC5 (6)
PG3 (6)
PG0 (6)
I
TTL
QEI module 1 phase A.
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Quadrature Encoder Interface (QEI)
Table 20-1. QEI Signals (144LQFP) (continued)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
PhB0
23
63
144
PH5 (5)
PF1 (6)
PD7 (6)
I
TTL
QEI module 0 phase B.
PhB1
34
51
54
PC6 (6)
PG4 (6)
PG1 (6)
I
TTL
QEI module 1 phase B.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
20.3
Functional Description
The QEI module interprets the two-bit gray code produced by a quadrature encoder wheel to integrate
position over time and determine direction of rotation. In addition, it can capture a running estimate
of the velocity of the encoder wheel.
The position integrator and velocity capture can be independently enabled, though the position
integrator must be enabled before the velocity capture can be enabled. The two phase signals,
PhAn and PhBn, can be swapped before being interpreted by the QEI module to change the meaning
of forward and backward and to correct for miswiring of the system. Alternatively, the phase signals
can be interpreted as a clock and direction signal as output by some encoders.
The QEI module input signals have a digital noise filter on them that can be enabled to prevent
spurious operation. The noise filter requires that the inputs be stable for a specified number of
consecutive clock cycles before updating the edge detector. The filter is enabled by the FILTEN bit
in the QEI Control (QEICTL) register. The frequency of the input update is programmable using
the FILTCNT bit field in the QEICTL register.
The QEI module supports two modes of signal operation: quadrature phase mode and clock/direction
mode. In quadrature phase mode, the encoder produces two clocks that are 90 degrees out of
phase; the edge relationship is used to determine the direction of rotation. In clock/direction mode,
the encoder produces a clock signal to indicate steps and a direction signal to indicate the direction
of rotation. This mode is determined by the SIGMODE bit of the QEICTL register (see page 1218).
When the QEI module is set to use the quadrature phase mode (SIGMODE bit is clear), the capture
mode for the position integrator can be set to update the position counter on every edge of the PhA
signal or to update on every edge of both PhA and PhB. Updating the position counter on every PhA
and PhB edge provides more positional resolution at the cost of less range in the positional counter.
When edges on PhA lead edges on PhB, the position counter is incremented. When edges on PhB
lead edges on PhA, the position counter is decremented. When a rising and falling edge pair is seen
on one of the phases without any edges on the other, the direction of rotation has changed.
The positional counter is automatically reset on one of two conditions: sensing the index pulse or
reaching the maximum position value. The reset mode is determined by the RESMODE bit of the
QEICTL register.
When RESMODE is set, the positional counter is reset when the index pulse is sensed. This mode
limits the positional counter to the values [0:N-1], where N is the number of phase edges in a full
revolution of the encoder wheel. The QEI Maximum Position (QEIMAXPOS) register must be
programmed with N-1 so that the reverse direction from position 0 can move the position counter
to N-1. In this mode, the position register contains the absolute position of the encoder relative to
the index (or home) position once an index pulse has been seen.
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When RESMODE is clear, the positional counter is constrained to the range [0:M], where M is the
programmable maximum value. The index pulse is ignored by the positional counter in this mode.
Velocity capture uses a configurable timer and a count register. The timer counts the number of
phase edges (using the same configuration as for the position integrator) in a given time period.
The edge count from the previous time period is available to the controller via the QEI Velocity
(QEISPEED) register, while the edge count for the current time period is being accumulated in the
QEI Velocity Counter (QEICOUNT) register. As soon as the current time period is complete, the
total number of edges counted in that time period is made available in the QEISPEED register
(overwriting the previous value), the QEICOUNT register is cleared, and counting commences on
a new time period. The number of edges counted in a given time period is directly proportional to
the velocity of the encoder.
Figure 20-3 on page 1215 shows how the TM4C123BH6PGE quadrature encoder converts the phase
input signals into clock pulses, the direction signal, and how the velocity predivider operates (in
Divide by 4 mode).
Figure 20-3. Quadrature Encoder and Velocity Predivider Operation
PhA
PhB
clk
clkdiv
dir
pos -1 -1 -1 -1 -1 -1 -1 -1 -1
rel +1
+1
+1
+1 +1 +1 +1 +1 +1 +1 +1
+1
+1
-1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+1
+1
+1
The period of the timer is configurable by specifying the load value for the timer in the QEI Timer
Load (QEILOAD) register. When the timer reaches zero, an interrupt can be triggered, and the
hardware reloads the timer with the QEILOAD value and continues to count down. At lower encoder
speeds, a longer timer period is required to be able to capture enough edges to have a meaningful
result. At higher encoder speeds, both a shorter timer period and/or the velocity predivider can be
used.
The following equation converts the velocity counter value into an rpm value:
rpm = (clock * (2 ^ VELDIV) * SPEED * 60) ÷ (LOAD * ppr * edges)
where:
clock is the controller clock rate
ppr is the number of pulses per revolution of the physical encoder
edges is 2 or 4, based on the capture mode set in the QEICTL register (2 for CAPMODE clear and
4 for CAPMODE set)
For example, consider a motor running at 600 rpm. A 2048 pulse per revolution quadrature encoder
is attached to the motor, producing 8192 phase edges per revolution. With a velocity predivider of
÷1 (VELDIV is clear) and clocking on both PhA and PhB edges, this results in 81,920 pulses per
second (the motor turns 10 times per second). If the timer were clocked at 10,000 Hz, and the load
value was 2,500 (¼ of a second), it would count 20,480 pulses per update. Using the above equation:
rpm = (10000 * 1 * 20480 * 60) ÷ (2500 * 2048 * 4) = 600 rpm
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Quadrature Encoder Interface (QEI)
Now, consider that the motor is sped up to 3000 rpm. This results in 409,600 pulses per second,
or 102,400 every ¼ of a second. Again, the above equation gives:
rpm = (10000 * 1 * 102400 * 60) ÷ (2500 * 2048 * 4) = 3000 rpm
Care must be taken when evaluating this equation because intermediate values may exceed the
capacity of a 32-bit integer. In the above examples, the clock is 10,000 and the divider is 2,500;
both could be predivided by 100 (at compile time if they are constants) and therefore be 100 and
25. In fact, if they were compile-time constants, they could also be reduced to a simple multiply by
4, cancelled by the ÷4 for the edge-count factor.
Important: Reducing constant factors at compile time is the best way to control the intermediate
values of this equation and reduce the processing requirement of computing this
equation.
The division can be avoided by selecting a timer load value such that the divisor is a power of 2; a
simple shift can therefore be done in place of the division. For encoders with a power of 2 pulses
per revolution, the load value can be a power of 2. For other encoders, a load value must be selected
such that the product is very close to a power of 2. For example, a 100 pulse-per-revolution encoder
could use a load value of 82, resulting in 32,800 as the divisor, which is 0.09% above 214. In this
case a shift by 15 would be an adequate approximation of the divide in most cases. If absolute
accuracy were required, the microcontroller's divide instruction could be used.
The QEI module can produce a controller interrupt on several events: phase error, direction change,
reception of the index pulse, and expiration of the velocity timer. Standard masking, raw interrupt
status, interrupt status, and interrupt clear capabilities are provided.
20.4
Initialization and Configuration
The following example shows how to configure the Quadrature Encoder module to read back an
absolute position:
1. Enable the QEI clock using the RCGCQEI register in the System Control module (see page 350).
2. Enable the clock to the appropriate GPIO module via the RCGCGPIO register in the System
Control module (see page 335).
3. In the GPIO module, enable the appropriate pins for their alternate function using the
GPIOAFSEL register. To determine which GPIOs to configure, see Table 22-4 on page 1262.
4. Configure the PMCn fields in the GPIOPCTL register to assign the QEI signals to the appropriate
pins (see page 695 and Table 22-5 on page 1273).
5. Configure the quadrature encoder to capture edges on both signals and maintain an absolute
position by resetting on index pulses. A 1000-line encoder with four edges per line, results in
4000 pulses per revolution; therefore, set the maximum position to 3999 (0xF9F) as the count
is zero-based.
■ Write the QEICTL register with the value of 0x0000.0018.
■ Write the QEIMAXPOS register with the value of 0x0000.0F9F.
6. Enable the quadrature encoder by setting bit 0 of the QEICTL register.
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Note:
Once the QEI module has been enabled by setting the ENABLE bit in the QEICTL
register, it cannot be disabled. The only way to clear the ENABLE bit is to reset the
module using the Quadrature Encoder Interface Software Reset (SRQEI) register.
7. Delay until the encoder position is required.
8. Read the encoder position by reading the QEI Position (QEIPOS) register value.
Note:
20.5
If the application requires the quadrature encoder to have a specific initial position, this
value must be programmed in the QEIPOS register after the quadrature encoder has been
enabled by setting the ENABLE bit in the QEICTL register.
Register Map
Table 20-2 on page 1217 lists the QEI registers. The offset listed is a hexadecimal increment to the
register's address, relative to the module's base address:
■ QEI0: 0x4002.C000
■ QEI1: 0x4002.D000
Note that the QEI module clock must be enabled before the registers can be programmed (see
page 350). There must be a delay of 3 system clocks after the QEI module clock is enabled before
any QEI module registers are accessed.
Table 20-2. QEI Register Map
Type
Reset
Description
See
page
QEICTL
RW
0x0000.0000
QEI Control
1218
0x004
QEISTAT
RO
0x0000.0000
QEI Status
1221
0x008
QEIPOS
RW
0x0000.0000
QEI Position
1222
0x00C
QEIMAXPOS
RW
0x0000.0000
QEI Maximum Position
1223
0x010
QEILOAD
RW
0x0000.0000
QEI Timer Load
1224
0x014
QEITIME
RO
0x0000.0000
QEI Timer
1225
0x018
QEICOUNT
RO
0x0000.0000
QEI Velocity Counter
1226
0x01C
QEISPEED
RO
0x0000.0000
QEI Velocity
1227
0x020
QEIINTEN
RW
0x0000.0000
QEI Interrupt Enable
1228
0x024
QEIRIS
RO
0x0000.0000
QEI Raw Interrupt Status
1230
0x028
QEIISC
RW1C
0x0000.0000
QEI Interrupt Status and Clear
1232
Offset
Name
0x000
20.6
Register Descriptions
The remainder of this section lists and describes the QEI registers, in numerical order by address
offset.
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Quadrature Encoder Interface (QEI)
Register 1: QEI Control (QEICTL), offset 0x000
This register contains the configuration of the QEI module. Separate enables are provided for the
quadrature encoder and the velocity capture blocks; the quadrature encoder must be enabled in
order to capture the velocity, but the velocity does not need to be captured in applications that do
not need it. The phase signal interpretation, phase swap, Position Update mode, Position Reset
mode, and velocity predivider are all set via this register.
QEI Control (QEICTL)
QEI0 base: 0x4002.C000
QEI1 base: 0x4002.D000
Offset 0x000
Type RW, reset 0x0000.0000
31
30
29
28
27
26
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
FILTEN
STALLEN
RW
0
RW
0
25
24
23
22
21
20
19
18
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
RW
0
RW
0
RW
0
10
9
8
7
6
5
4
3
2
1
0
INVI
INVB
INVA
SWAP
ENABLE
RW
0
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
RO
0
17
16
FILTCNT
VELDIV
RW
0
RW
0
VELEN RESMODE CAPMODE SIGMODE
RW
0
RW
0
RW
0
RW
0
RW
0
Bit/Field
Name
Type
Reset
Description
31:20
reserved
RO
0x000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
19:16
FILTCNT
RW
0x0
Input Filter Prescale Count
This field controls the frequency of the input update.
When this field is clear, the input is sampled after 2 system clocks. When
this field ix 0x1, the input is sampled after 3 system clocks. Similarly,
when this field is 0xF, the input is sampled after 17 clocks.
15:14
reserved
RO
0x0
13
FILTEN
RW
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Enable Input Filter
Value Description
12
STALLEN
RW
0
0
The QEI inputs are not filtered.
1
Enables the digital noise filter on the QEI input signals. Inputs
must be stable for 3 consecutive clock edges before the edge
detector is updated.
Stall QEI
Value Description
0
The QEI module does not stall when the microcontroller is
stopped by a debugger.
1
The QEI module stalls when the microcontroller is stopped by
a debugger.
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Bit/Field
Name
Type
Reset
11
INVI
RW
0
Description
Invert Index Pulse
Value Description
10
INVB
RW
0
0
No effect.
1
Inverts the IDX input.
Invert PhB
Value Description
9
INVA
RW
0
0
No effect.
1
Inverts the PhBn input.
Invert PhA
Value Description
8:6
VELDIV
RW
0x0
0
No effect.
1
Inverts the PhAn input.
Predivide Velocity
This field defines the predivider of the input quadrature pulses before
being applied to the QEICOUNT accumulator.
Value Predivider
5
VELEN
RW
0
0x0
÷1
0x1
÷2
0x2
÷4
0x3
÷8
0x4
÷16
0x5
÷32
0x6
÷64
0x7
÷128
Capture Velocity
Value Description
4
RESMODE
RW
0
0
No effect.
1
Enables capture of the velocity of the quadrature encoder.
Reset Mode
Value Description
0
The position counter is reset when it reaches the maximum as
defined by the MAXPOS field in the QEIMAXPOS register.
1
The position counter is reset when the index pulse is captured.
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Quadrature Encoder Interface (QEI)
Bit/Field
Name
Type
Reset
3
CAPMODE
RW
0
Description
Capture Mode
Note:
When SIGMODE=1, the CAPMODE setting is not applicable and
is reserved.
Value Description
2
SIGMODE
RW
0
0
Only the PhA edges are counted.
1
The PhA and PhB edges are counted, providing twice the
positional resolution but half the range.
Signal Mode
Value Description
1
SWAP
RW
0
0
The internal PhA and PhB signals operate as quadrature phase
signals.
1
The internal PhA input operates as the clock (CLK) signal and
the internal PhB input operates as the direction (DIR) signal.
Swap Signals
Note if the INVA or INVB bit are set, the inversion of the signals occur
prior to the swap.
Value Description
0
ENABLE
RW
0
0
No effect.
1
Swaps the PhAn and PhBn signals.
Enable QEI
Value Description
0
No effect.
1
Enables the quadrature encoder module.
Note:
Once the QEI module has been enabled by setting the
ENABLE bit, it cannot be disabled. The only way to clear the
ENABLE bit is to reset the module using the Quadrature
Encoder Interface Software Reset (SRQEI) register.
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Register 2: QEI Status (QEISTAT), offset 0x004
This register provides status about the operation of the QEI module.
QEI Status (QEISTAT)
QEI0 base: 0x4002.C000
QEI1 base: 0x4002.D000
Offset 0x004
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
reserved
Type
Reset
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:2
reserved
RO
0x0000.000
1
DIRECTION
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
1
0
DIRECTION
ERROR
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Direction of Rotation
Indicates the direction the encoder is rotating.
Value Description
0
ERROR
RO
0
0
The encoder is rotating forward.
1
The encoder is rotating in reverse.
Error Detected
Value Description
0
No error.
1
An error was detected in the gray code sequence (that is, both
signals changing at the same time).
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Quadrature Encoder Interface (QEI)
Register 3: QEI Position (QEIPOS), offset 0x008
This register contains the current value of the position integrator. The value is updated by the status
of the QEI phase inputs and can be set to a specific value by writing to it.
QEI Position (QEIPOS)
QEI0 base: 0x4002.C000
QEI1 base: 0x4002.D000
Offset 0x008
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
15
14
13
12
11
10
9
8
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
23
22
21
20
19
18
17
16
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
7
6
5
4
3
2
1
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
POSITION
Type
Reset
POSITION
Type
Reset
Bit/Field
Name
Type
31:0
POSITION
RW
Reset
RW
0
Description
0x0000.0000 Current Position Integrator Value
The current value of the position integrator.
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Register 4: QEI Maximum Position (QEIMAXPOS), offset 0x00C
This register contains the maximum value of the position integrator. When moving forward, the
position register resets to zero when it increments past this value. When moving in reverse, the
position register resets to this value when it decrements from zero.
QEI Maximum Position (QEIMAXPOS)
QEI0 base: 0x4002.C000
QEI1 base: 0x4002.D000
Offset 0x00C
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
15
14
13
12
11
10
9
8
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
23
22
21
20
19
18
17
16
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
7
6
5
4
3
2
1
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
MAXPOS
Type
Reset
MAXPOS
Type
Reset
Bit/Field
Name
Type
31:0
MAXPOS
RW
Reset
Description
0x0000.0000 Maximum Position Integrator Value
The maximum value of the position integrator.
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Quadrature Encoder Interface (QEI)
Register 5: QEI Timer Load (QEILOAD), offset 0x010
This register contains the load value for the velocity timer. Because this value is loaded into the
timer on the clock cycle after the timer is zero, this value should be one less than the number of
clocks in the desired period. So, for example, to have 2000 decimal clocks per timer period, this
register should contain 1999 decimal.
QEI Timer Load (QEILOAD)
QEI0 base: 0x4002.C000
QEI1 base: 0x4002.D000
Offset 0x010
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
LOAD
Type
Reset
LOAD
Type
Reset
Bit/Field
Name
Type
31:0
LOAD
RW
Reset
Description
0x0000.0000 Velocity Timer Load Value
The load value for the velocity timer.
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Register 6: QEI Timer (QEITIME), offset 0x014
This register contains the current value of the velocity timer. This counter does not increment when
the VELEN bit in the QEICTL register is clear.
QEI Timer (QEITIME)
QEI0 base: 0x4002.C000
QEI1 base: 0x4002.D000
Offset 0x014
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
TIME
Type
Reset
TIME
Type
Reset
Bit/Field
Name
Type
31:0
TIME
RO
Reset
Description
0x0000.0000 Velocity Timer Current Value
The current value of the velocity timer.
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Quadrature Encoder Interface (QEI)
Register 7: QEI Velocity Counter (QEICOUNT), offset 0x018
This register contains the running count of velocity pulses for the current time period. Because this
count is a running total, the time period to which it applies cannot be known with precision (that is,
a read of this register does not necessarily correspond to the time returned by the QEITIME register
because there is a small window of time between the two reads, during which either value may have
changed). The QEISPEED register should be used to determine the actual encoder velocity; this
register is provided for information purposes only. This counter does not increment when the VELEN
bit in the QEICTL register is clear.
QEI Velocity Counter (QEICOUNT)
QEI0 base: 0x4002.C000
QEI1 base: 0x4002.D000
Offset 0x018
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
COUNT
Type
Reset
COUNT
Type
Reset
Bit/Field
Name
Type
31:0
COUNT
RO
Reset
Description
0x0000.0000 Velocity Pulse Count
The running total of encoder pulses during this velocity timer period.
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Register 8: QEI Velocity (QEISPEED), offset 0x01C
This register contains the most recently measured velocity of the quadrature encoder. This value
corresponds to the number of velocity pulses counted in the previous velocity timer period. This
register does not update when the VELEN bit in the QEICTL register is clear.
QEI Velocity (QEISPEED)
QEI0 base: 0x4002.C000
QEI1 base: 0x4002.D000
Offset 0x01C
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
SPEED
Type
Reset
SPEED
Type
Reset
Bit/Field
Name
Type
31:0
SPEED
RO
Reset
Description
0x0000.0000 Velocity
The measured speed of the quadrature encoder in pulses per period.
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Quadrature Encoder Interface (QEI)
Register 9: QEI Interrupt Enable (QEIINTEN), offset 0x020
This register contains enables for each of the QEI module interrupts. An interrupt is asserted to the
interrupt controller if the corresponding bit in this register is set.
QEI Interrupt Enable (QEIINTEN)
QEI0 base: 0x4002.C000
QEI1 base: 0x4002.D000
Offset 0x020
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
INTERROR
INTDIR
INTTIMER
INTINDEX
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:4
reserved
RO
0x0000.000
3
INTERROR
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Phase Error Interrupt Enable
Note:
The INTERROR bit is only applicable when the QEI is operating
in quadrature phase mode (SIGMODE=0) and should be
masked when SIGMODE =1.
Value Description
2
INTDIR
RW
0
0
The INTERROR interrupt is suppressed and not sent to the
interrupt controller.
1
An interrupt is sent to the interrupt controller when the
INTERROR bit in the QEIRIS register is set.
Direction Change Interrupt Enable
Value Description
1
INTTIMER
RW
0
0
The INTDIR interrupt is suppressed and not sent to the interrupt
controller.
1
An interrupt is sent to the interrupt controller when the INTDIR
bit in the QEIRIS register is set.
Timer Expires Interrupt Enable
Value Description
0
The INTTIMER interrupt is suppressed and not sent to the
interrupt controller.
1
An interrupt is sent to the interrupt controller when the
INTTIMER bit in the QEIRIS register is set.
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Tiva™ TM4C123BH6PGE Microcontroller
Bit/Field
Name
Type
Reset
0
INTINDEX
RW
0
Description
Index Pulse Detected Interrupt Enable
Value Description
0
The INTINDEX interrupt is suppressed and not sent to the
interrupt controller.
1
An interrupt is sent to the interrupt controller when the
INTINDEX bit in the QEIRIS register is set.
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Quadrature Encoder Interface (QEI)
Register 10: QEI Raw Interrupt Status (QEIRIS), offset 0x024
This register provides the current set of interrupt sources that are asserted, regardless of whether
they cause an interrupt to be asserted to the controller (configured through the QEIINTEN register).
If a bit is set, the latched event has occurred; if a bit is clear, the event in question has not occurred.
QEI Raw Interrupt Status (QEIRIS)
QEI0 base: 0x4002.C000
QEI1 base: 0x4002.D000
Offset 0x024
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
INTERROR
INTDIR
INTTIMER
INTINDEX
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:4
reserved
RO
0x0000.000
3
INTERROR
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Phase Error Detected
Note:
The INTERROR bit is only applicable when the QEI is operating
in quadrature phase mode (SIGMODE=0).
Value Description
0
An interrupt has not occurred.
1
A phase error has been detected.
This bit is cleared by writing a 1 to the INTERROR bit in the QEIISC
register.
2
INTDIR
RO
0
Direction Change Detected
Value Description
0
An interrupt has not occurred.
1
The rotation direction has changed
This bit is cleared by writing a 1 to the INTDIR bit in the QEIISC register.
1
INTTIMER
RO
0
Velocity Timer Expired
Value Description
0
An interrupt has not occurred.
1
The velocity timer has expired.
This bit is cleared by writing a 1 to the INTTIMER bit in the QEIISC
register.
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Bit/Field
Name
Type
Reset
0
INTINDEX
RO
0
Description
Index Pulse Asserted
Value Description
0
An interrupt has not occurred.
1
The index pulse has occurred.
This bit is cleared by writing a 1 to the INTINDEX bit in the QEIISC
register.
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Quadrature Encoder Interface (QEI)
Register 11: QEI Interrupt Status and Clear (QEIISC), offset 0x028
This register provides the current set of interrupt sources that are asserted to the controller. If a bit
is set, the latched event has occurred and is enabled to generate an interrupt; if a bit is clear the
event in question has not occurred or is not enabled to generate an interrupt. This register is RW1C;
writing a 1 to a bit position clears the bit and the corresponding interrupt reason.
QEI Interrupt Status and Clear (QEIISC)
QEI0 base: 0x4002.C000
QEI1 base: 0x4002.D000
Offset 0x028
Type RW1C, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
INTERROR
INTDIR
INTTIMER
INTINDEX
RO
0
RO
0
RO
0
RO
0
RO
0
RW1C
0
RW1C
0
RW1C
0
RW1C
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:4
reserved
RO
0x0000.000
3
INTERROR
RW1C
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Phase Error Interrupt
Value Description
0
No interrupt has occurred or the interrupt is masked.
1
The INTERROR bits in the QEIRIS register and the QEIINTEN
registers are set, providing an interrupt to the interrupt controller.
This bit is cleared by writing a 1. Clearing this bit also clears the
INTERROR bit in the QEIRIS register.
2
INTDIR
RW1C
0
Direction Change Interrupt
Value Description
0
No interrupt has occurred or the interrupt is masked.
1
The INTDIR bits in the QEIRIS register and the QEIINTEN
registers are set, providing an interrupt to the interrupt controller.
This bit is cleared by writing a 1. Clearing this bit also clears the INTDIR
bit in the QEIRIS register.
1
INTTIMER
RW1C
0
Velocity Timer Expired Interrupt
Value Description
0
No interrupt has occurred or the interrupt is masked.
1
The INTTIMER bits in the QEIRIS register and the QEIINTEN
registers are set, providing an interrupt to the interrupt controller.
This bit is cleared by writing a 1. Clearing this bit also clears the
INTTIMER bit in the QEIRIS register.
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Tiva™ TM4C123BH6PGE Microcontroller
Bit/Field
Name
Type
Reset
0
INTINDEX
RW1C
0
Description
Index Pulse Interrupt
Value Description
0
No interrupt has occurred or the interrupt is masked.
1
The INTINDEX bits in the QEIRIS register and the QEIINTEN
registers are set, providing an interrupt to the interrupt controller.
This bit is cleared by writing a 1. Clearing this bit also clears the
INTINDEX bit in the QEIRIS register.
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Pin Diagram
21
Pin Diagram
The TM4C123BH6PGE microcontroller pin diagram is shown below.
Each GPIO signal is identified by its GPIO port unless it defaults to an alternate function on reset.
In this case, the GPIO port name is followed by the default alternate function. To see a complete
list of possible functions for each pin, see Table 22-5 on page 1273.
Figure 21-1. 144-Pin LQFP Package Pin Diagram
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Tiva™ TM4C123BH6PGE Microcontroller
22
Signal Tables
The following tables list the signals available for each pin. Signals are configured as GPIOs on reset,
except for those noted below. Use the GPIOAMSEL register (see page 693) to select analog mode.
For a GPIO pin to be used for an alternate digital function, the corresponding bit in the GPIOAFSEL
register (see page 676) must be set. Further pin muxing options are provided through the PMCx bit
field in the GPIOPCTL register (see page 695), which selects one of several available peripheral
functions for that GPIO.
Important: Table 10-1 on page 648 shows special consideration GPIO pins. Most GPIO pins are
configured as GPIOs and tri-stated by default (GPIOAFSEL=0, GPIODEN=0,
GPIOPDR=0, GPIOPUR=0, and GPIOPCTL=0). Special consideration pins may be
programed to a non-GPIO function or may have special commit controls out of reset.
In addition, a Power-On-Reset (POR) or asserting RST returns these GPIO to their
original special consideration state.
Table 22-1. GPIO Pins With Special Considerations
GPIO Pins
Default Reset
State
GPIOAFSEL GPIODEN GPIOPDR GPIOPUR GPIOPCTL GPIOCR
PA[1:0]
UART0
0
0
0
0
0x1
1
PA[5:2]
SSI0
0
0
0
0
0x2
1
PB[3:2]
I21C0
0
0
0
0
0x3
1
PC[3:0]
JTAG/SWD
PD[7]
GPIO
PF[0]
1
1
0
1
0x1
0
a
0
0
0
0
0x0
0
a
0
0
0
0
0x0
0
GPIO
a. This pin is configured as a GPIO by default but is locked and can only be reprogrammed by unlocking the
pin in the GPIOLOCK register and uncommitting it by setting the GPIOCR register.
Table 22-2 on page 1236 shows the pin-to-signal-name mapping, including functional characteristics
of the signals. Each possible alternate analog and digital function is listed for each pin.
Table 22-3 on page 1249 lists the signals in alphabetical order by signal name. If it is possible for a
signal to be on multiple pins, each possible pin assignment is listed. The "Pin Mux" column indicates
the GPIO and the encoding needed in the PMCx bit field in the GPIOPCTL register.
Table 22-4 on page 1262 groups the signals by functionality, except for GPIOs. If it is possible for a
signal to be on multiple pins, each possible pin assignment is listed.
Table 22-5 on page 1273 lists the GPIO pins and their analog and digital alternate functions. The AINx
analog signals are not 5-V tolerant and go through an isolation circuit before reaching their circuitry.
These signals are configured by clearing the corresponding DEN bit in the GPIO Digital Enable
(GPIODEN) register and setting the corresponding AMSEL bit in the GPIO Analog Mode Select
(GPIOAMSEL) register. Other analog signals are 5-V tolerant and are connected directly to their
circuitry (C0-, C0+, C1-, C1+, C2-, C2+). These signals are configured by clearing the DEN bit in
the GPIO Digital Enable (GPIODEN) register. The digital signals are enabled by setting the
appropriate bit in the GPIO Alternate Function Select (GPIOAFSEL) and GPIODEN registers and
configuring the PMCx bit field in the GPIO Port Control (GPIOPCTL) register to the numeric enoding
shown in the table below. Table entries that are shaded gray are the default values for the
corresponding GPIO pin.
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Signal Tables
Table 22-6 on page 1276 lists the signals based on number of possible pin assignments. This table
can be used to plan how to configure the pins for a particular functionality. Application Note AN01274
Configuring Tiva™ C Series Microcontrollers with Pin Multiplexing provides an overview of the pin
muxing implementation, an explanation of how a system designer defines a pin configuration, and
examples of the pin configuration process.
Note:
22.1
All digital inputs are Schmitt triggered.
Signals by Pin Number
Table 22-2. Signals by Pin Number
Pin Number
a
Pin Name
Pin Type
Buffer Type
PD0
I/O
TTL
Description
GPIO port D bit 0.
AIN15
I
Analog
I2C3SCL
I/O
OD
I2C module 3 clock. Note that this signal has an active pull-up. The
corresponding port pin should not be configured as open drain.
M0PWM6
O
TTL
Motion Control Module 0 PWM 6. This signal is controlled by
Module 0 PWM Generator 3.
M1PWM0
O
TTL
Motion Control Module 1 PWM 0. This signal is controlled by
Module 1 PWM Generator 0.
SSI1Clk
I/O
TTL
SSI module 1 clock.
SSI3Clk
I/O
TTL
SSI module 3 clock.
WT2CCP0
I/O
TTL
32/64-Bit Wide Timer 2 Capture/Compare/PWM 0.
PD1
I/O
TTL
GPIO port D bit 1.
AIN14
I
Analog
I2C3SDA
I/O
OD
I2C module 3 data.
M0PWM7
O
TTL
Motion Control Module 0 PWM 7. This signal is controlled by
Module 0 PWM Generator 3.
M1PWM1
O
TTL
Motion Control Module 1 PWM 1. This signal is controlled by
Module 1 PWM Generator 0.
SSI1Fss
I/O
TTL
SSI module 1 frame signal.
SSI3Fss
I/O
TTL
SSI module 3 frame signal.
WT2CCP1
I/O
TTL
32/64-Bit Wide Timer 2 Capture/Compare/PWM 1.
PD2
I/O
TTL
GPIO port D bit 2.
1
2
Analog-to-digital converter input 15.
Analog-to-digital converter input 14.
AIN13
I
Analog
M0FAULT0
I
TTL
Motion Control Module 0 PWM Fault 0.
SSI1Rx
I
TTL
SSI module 1 receive.
3
Analog-to-digital converter input 13.
SSI3Rx
I
TTL
SSI module 3 receive.
WT3CCP0
I/O
TTL
32/64-Bit Wide Timer 3 Capture/Compare/PWM 0.
GPIO port D bit 3.
PD3
I/O
TTL
AIN12
I
Analog
IDX0
I
TTL
QEI module 0 index.
SSI1Tx
O
TTL
SSI module 1 transmit.
SSI3Tx
O
TTL
SSI module 3 transmit.
WT3CCP1
I/O
TTL
32/64-Bit Wide Timer 3 Capture/Compare/PWM 1.
5
VDD
-
Power
Positive supply for I/O and some logic.
6
GND
-
Power
Ground reference for logic and I/O pins.
4
Analog-to-digital converter input 12.
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Table 22-2. Signals by Pin Number (continued)
Pin Number
a
Pin Name
Pin Type
Buffer Type
VDDA
-
Power
The positive supply for the analog circuits (ADC, Analog
Comparators, etc.). These are separated from VDD to minimize
the electrical noise contained on VDD from affecting the analog
functions. VDDA pins must be supplied with a voltage that meets
the specification in Table 23-5 on page 1284, regardless of system
implementation.
VREFA+
-
Analog
A reference voltage used to specify the voltage at which the ADC
converts to a maximum value. This pin is used in conjunction with
VREFA-, which specifies the minimum value . The voltage that is
applied to VREFA+ is the voltage with which an AINn signal is
converted to 4095. The VREFA+ voltage is limited to the range
specified in Table 23-32 on page 1314 .
VREFA-
-
Analog
A reference voltage used to specify the input voltage at which the
ADC converts to a minimum value. This pin is used in conjunction
with VREFA+, which specifies the maximum value. In other words,
the voltage that is applied to VREFA- is the voltage with which an
AINn signal is converted to 0, while the voltage that is applied to
VREFA+ is the voltage with which an AINn signal is converted to
4095. The VREFA- voltage is limited to the range specified in Table
23-32 on page 1314 .
GNDA
-
Power
The ground reference for the analog circuits (ADC, Analog
Comparators, etc.). These are separated from GND to minimize
the electrical noise contained on VDD from affecting the analog
functions.
PP2
I/O
TTL
GPIO port P bit 2.
M0PWM2
O
TTL
Motion Control Module 0 PWM 2. This signal is controlled by
Module 0 PWM Generator 1.
T5CCP0
I/O
TTL
16/32-Bit Timer 5 Capture/Compare/PWM 0.
GPIO port E bit 3.
7
8
9
10
11
PE3
I/O
TTL
AIN0
I
Analog
PE2
I/O
TTL
AIN1
I
Analog
PE1
I/O
TTL
AIN2
I
Analog
U7Tx
O
TTL
UART module 7 transmit.
PE0
I/O
TTL
GPIO port E bit 0.
AIN3
I
Analog
U7Rx
I
TTL
UART module 7 receive.
GPIO port K bit 0.
12
13
14
15
Description
Analog-to-digital converter input 0.
GPIO port E bit 2.
Analog-to-digital converter input 1.
GPIO port E bit 1.
Analog-to-digital converter input 2.
Analog-to-digital converter input 3.
PK0
I/O
TTL
AIN16
I
Analog
M1FAULT0
I
TTL
Motion Control Module 1 PWM Fault 0.
SSI3Clk
I/O
TTL
SSI module 3 clock.
PK1
I/O
TTL
GPIO port K bit 1.
16
Analog-to-digital converter input 16.
AIN17
I
Analog
M1FAULT1
I
TTL
Motion Control Module 1 PWM Fault 1.
SSI3Fss
I/O
TTL
SSI module 3 frame signal.
17
Analog-to-digital converter input 17.
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Signal Tables
Table 22-2. Signals by Pin Number (continued)
Pin Number
Pin Name
Pin Type
PK2
I/O
TTL
I
Analog
M1FAULT2
I
TTL
Motion Control Module 1 PWM Fault 2.
SSI3Rx
I
TTL
SSI module 3 receive.
PK3
I/O
TTL
GPIO port K bit 3.
GPIO port K bit 2.
Analog-to-digital converter input 18.
AIN19
I
Analog
M1FAULT3
I
TTL
Motion Control Module 1 PWM Fault 3.
SSI3Tx
O
TTL
SSI module 3 transmit.
19
Analog-to-digital converter input 19.
PN2
I/O
TTL
GPIO port N bit 2.
M0PWM6
O
TTL
Motion Control Module 0 PWM 6. This signal is controlled by
Module 0 PWM Generator 3.
WT2CCP0
I/O
TTL
32/64-Bit Wide Timer 2 Capture/Compare/PWM 0.
PH7
I/O
TTL
GPIO port H bit 7.
M0PWM7
O
TTL
Motion Control Module 0 PWM 7. This signal is controlled by
Module 0 PWM Generator 3.
21
SSI2Tx
O
TTL
SSI module 2 transmit.
WT4CCP1
I/O
TTL
32/64-Bit Wide Timer 4 Capture/Compare/PWM 1.
PH6
I/O
TTL
GPIO port H bit 6.
M0PWM6
O
TTL
Motion Control Module 0 PWM 6. This signal is controlled by
Module 0 PWM Generator 3.
SSI2Rx
I
TTL
SSI module 2 receive.
WT4CCP0
I/O
TTL
32/64-Bit Wide Timer 4 Capture/Compare/PWM 0.
22
23
Description
AIN18
18
20
a
Buffer Type
PH5
I/O
TTL
GPIO port H bit 5.
M0PWM5
O
TTL
Motion Control Module 0 PWM 5. This signal is controlled by
Module 0 PWM Generator 2.
PhB0
I
TTL
QEI module 0 phase B.
SSI2Fss
I/O
TTL
SSI module 2 frame signal.
32/64-Bit Wide Timer 3 Capture/Compare/PWM 1.
WT3CCP1
I/O
TTL
24
VDD
-
Power
Positive supply for I/O and some logic.
25
GND
-
Power
Ground reference for logic and I/O pins.
PH4
I/O
TTL
GPIO port H bit 4.
M0PWM4
O
TTL
Motion Control Module 0 PWM 4. This signal is controlled by
Module 0 PWM Generator 2.
PhA0
I
TTL
QEI module 0 phase A.
SSI2Clk
I/O
TTL
SSI module 2 clock.
WT3CCP0
I/O
TTL
32/64-Bit Wide Timer 3 Capture/Compare/PWM 0.
PH3
I/O
TTL
GPIO port H bit 3.
M0FAULT3
I
TTL
Motion Control Module 0 PWM Fault 3.
M0PWM3
O
TTL
Motion Control Module 0 PWM 3. This signal is controlled by
Module 0 PWM Generator 1.
SSI3Tx
O
TTL
SSI module 3 transmit.
WT5CCP1
I/O
TTL
32/64-Bit Wide Timer 5 Capture/Compare/PWM 1.
26
27
1238
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Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Table 22-2. Signals by Pin Number (continued)
Pin Number
28
a
Pin Name
Pin Type
Buffer Type
Description
PH2
I/O
TTL
GPIO port H bit 2.
M0FAULT2
I
TTL
Motion Control Module 0 PWM Fault 2.
M0PWM2
O
TTL
Motion Control Module 0 PWM 2. This signal is controlled by
Module 0 PWM Generator 1.
SSI3Rx
I
TTL
SSI module 3 receive.
32/64-Bit Wide Timer 5 Capture/Compare/PWM 0.
WT5CCP0
I/O
TTL
29
VDD
-
Power
Positive supply for I/O and some logic.
30
GND
-
Power
Ground reference for logic and I/O pins.
PH1
I/O
TTL
GPIO port H bit 1.
IDX0
I
TTL
QEI module 0 index.
M0FAULT1
I
TTL
Motion Control Module 0 PWM Fault 1.
M0PWM1
O
TTL
Motion Control Module 0 PWM 1. This signal is controlled by
Module 0 PWM Generator 0.
SSI3Fss
I/O
TTL
SSI module 3 frame signal.
WT2CCP1
I/O
TTL
32/64-Bit Wide Timer 2 Capture/Compare/PWM 1.
31
32
PH0
I/O
TTL
GPIO port H bit 0.
M0FAULT0
I
TTL
Motion Control Module 0 PWM Fault 0.
M0PWM0
O
TTL
Motion Control Module 0 PWM 0. This signal is controlled by
Module 0 PWM Generator 0.
SSI3Clk
I/O
TTL
SSI module 3 clock.
WT2CCP0
I/O
TTL
32/64-Bit Wide Timer 2 Capture/Compare/PWM 0.
PC7
I/O
TTL
GPIO port C bit 7.
C0-
I
Analog
U3Tx
O
TTL
UART module 3 transmit.
WT1CCP1
I/O
TTL
32/64-Bit Wide Timer 1 Capture/Compare/PWM 1.
PC6
I/O
TTL
GPIO port C bit 6.
C0+
I
Analog
PhB1
I
TTL
QEI module 1 phase B.
U3Rx
I
TTL
UART module 3 receive.
WT1CCP0
I/O
TTL
32/64-Bit Wide Timer 1 Capture/Compare/PWM 0.
PC5
I/O
TTL
GPIO port C bit 5.
C1+
I
Analog
M0PWM7
O
TTL
Motion Control Module 0 PWM 7. This signal is controlled by
Module 0 PWM Generator 3.
33
34
35
Analog comparator 0 negative input.
Analog comparator 0 positive input.
Analog comparator 1 positive input.
PhA1
I
TTL
QEI module 1 phase A.
U1CTS
I
TTL
UART module 1 Clear To Send modem flow control input signal.
U1Tx
O
TTL
UART module 1 transmit.
U4Tx
O
TTL
UART module 4 transmit.
WT0CCP1
I/O
TTL
32/64-Bit Wide Timer 0 Capture/Compare/PWM 1.
June 12, 2014
1239
Texas Instruments-Production Data
Signal Tables
Table 22-2. Signals by Pin Number (continued)
Pin Number
a
Pin Name
Pin Type
Buffer Type
PC4
I/O
TTL
C1-
I
Analog
IDX1
I
TTL
QEI module 1 index.
M0PWM6
O
TTL
Motion Control Module 0 PWM 6. This signal is controlled by
Module 0 PWM Generator 3.
U1RTS
O
TTL
UART module 1 Request to Send modem flow control output line.
U1Rx
I
TTL
UART module 1 receive.
36
37
38
Description
GPIO port C bit 4.
Analog comparator 1 negative input.
U4Rx
I
TTL
UART module 4 receive.
WT0CCP0
I/O
TTL
32/64-Bit Wide Timer 0 Capture/Compare/PWM 0.
PA0
I/O
TTL
GPIO port A bit 0.
CAN1Rx
I
TTL
CAN module 1 receive.
U0Rx
I
TTL
UART module 0 receive.
PA1
I/O
TTL
GPIO port A bit 1.
CAN1Tx
O
TTL
CAN module 1 transmit.
U0Tx
O
TTL
UART module 0 transmit.
PA2
I/O
TTL
GPIO port A bit 2.
SSI0Clk
I/O
TTL
SSI module 0 clock
PA3
I/O
TTL
GPIO port A bit 3.
SSI0Fss
I/O
TTL
SSI module 0 frame signal
PA4
I/O
TTL
GPIO port A bit 4.
SSI0Rx
I
TTL
SSI module 0 receive
PA5
I/O
TTL
GPIO port A bit 5.
SSI0Tx
O
TTL
SSI module 0 transmit
43
VDD
-
Power
Positive supply for I/O and some logic.
44
GND
-
Power
Ground reference for logic and I/O pins.
39
40
41
42
PA6
I/O
TTL
GPIO port A bit 6.
I2C1SCL
I/O
OD
I2C module 1 clock. Note that this signal has an active pull-up. The
corresponding port pin should not be configured as open drain.
M1PWM2
O
TTL
Motion Control Module 1 PWM 2. This signal is controlled by
Module 1 PWM Generator 1.
45
46
47
PA7
I/O
TTL
GPIO port A bit 7.
I2C1SDA
I/O
OD
I2C module 1 data.
M1PWM3
O
TTL
Motion Control Module 1 PWM 3. This signal is controlled by
Module 1 PWM Generator 1.
PG7
I/O
TTL
GPIO port G bit 7.
I2C5SDA
I/O
OD
I2C module 5 data.
IDX1
I
TTL
QEI module 1 index.
M0PWM7
O
TTL
Motion Control Module 0 PWM 7. This signal is controlled by
Module 0 PWM Generator 3.
WT1CCP1
I/O
TTL
32/64-Bit Wide Timer 1 Capture/Compare/PWM 1.
1240
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Table 22-2. Signals by Pin Number (continued)
Pin Number
a
Pin Name
Pin Type
Buffer Type
PG6
I/O
TTL
GPIO port G bit 6.
I2C5SCL
I/O
OD
I2C module 5 clock. Note that this signal has an active pull-up. The
corresponding port pin should not be configured as open drain.
M0PWM6
O
TTL
Motion Control Module 0 PWM 6. This signal is controlled by
Module 0 PWM Generator 3.
WT1CCP0
I/O
TTL
32/64-Bit Wide Timer 1 Capture/Compare/PWM 0.
VDDC
-
Power
48
49
52
53
Positive supply for most of the logic function, including the
processor core and most peripherals. The voltage on this pin is
1.2 V and is supplied by the on-chip LDO. The VDDC pins should
only be connected to each other and an external capacitor as
specified in Table 23-12 on page 1297 .
PG5
I/O
TTL
GPIO port G bit 5.
I2C1SDA
I/O
OD
I2C module 1 data.
IDX1
I
TTL
QEI module 1 index.
M0PWM5
O
TTL
Motion Control Module 0 PWM 5. This signal is controlled by
Module 0 PWM Generator 2.
M1PWM3
O
TTL
Motion Control Module 1 PWM 3. This signal is controlled by
Module 1 PWM Generator 1.
50
51
Description
U2Tx
O
TTL
UART module 2 transmit.
WT0CCP1
I/O
TTL
32/64-Bit Wide Timer 0 Capture/Compare/PWM 1.
PG4
I/O
TTL
GPIO port G bit 4.
I2C1SCL
I/O
OD
I2C module 1 clock. Note that this signal has an active pull-up. The
corresponding port pin should not be configured as open drain.
M0PWM4
O
TTL
Motion Control Module 0 PWM 4. This signal is controlled by
Module 0 PWM Generator 2.
M1PWM2
O
TTL
Motion Control Module 1 PWM 2. This signal is controlled by
Module 1 PWM Generator 1.
PhB1
I
TTL
QEI module 1 phase B.
U2Rx
I
TTL
UART module 2 receive.
WT0CCP0
I/O
TTL
32/64-Bit Wide Timer 0 Capture/Compare/PWM 0.
PG3
I/O
TTL
GPIO port G bit 3.
I2C4SDA
I/O
OD
I2C module 4 data.
M0FAULT2
I
TTL
Motion Control Module 0 PWM Fault 2.
M1PWM1
O
TTL
Motion Control Module 1 PWM 1. This signal is controlled by
Module 1 PWM Generator 0.
PhA1
I
TTL
QEI module 1 phase A.
T5CCP1
I/O
TTL
16/32-Bit Timer 5 Capture/Compare/PWM 1.
PG2
I/O
TTL
GPIO port G bit 2.
I2C4SCL
I/O
OD
I2C module 4 clock. Note that this signal has an active pull-up. The
corresponding port pin should not be configured as open drain.
M0FAULT1
I
TTL
Motion Control Module 0 PWM Fault 1.
M1PWM0
O
TTL
Motion Control Module 1 PWM 0. This signal is controlled by
Module 1 PWM Generator 0.
T5CCP0
I/O
TTL
16/32-Bit Timer 5 Capture/Compare/PWM 0.
June 12, 2014
1241
Texas Instruments-Production Data
Signal Tables
Table 22-2. Signals by Pin Number (continued)
Pin Number
54
a
Pin Name
Pin Type
Buffer Type
Description
PG1
I/O
TTL
GPIO port G bit 1.
I2C3SDA
I/O
OD
I2C module 3 data.
M1FAULT2
I
TTL
Motion Control Module 1 PWM Fault 2.
PhB1
I
TTL
QEI module 1 phase B.
T4CCP1
I/O
TTL
16/32-Bit Timer 4 Capture/Compare/PWM 1.
PG0
I/O
TTL
GPIO port G bit 0.
I2C3SCL
I/O
OD
I2C module 3 clock. Note that this signal has an active pull-up. The
corresponding port pin should not be configured as open drain.
M1FAULT1
I
TTL
Motion Control Module 1 PWM Fault 1.
PhA1
I
TTL
QEI module 1 phase A.
T4CCP0
I/O
TTL
16/32-Bit Timer 4 Capture/Compare/PWM 0.
56
VDD
-
Power
Positive supply for I/O and some logic.
57
GND
-
Power
Ground reference for logic and I/O pins.
55
PF7
I/O
TTL
GPIO port F bit 7.
I2C2SDA
I/O
OD
I2C module 2 data.
M1FAULT0
I
TTL
Motion Control Module 1 PWM Fault 0.
T3CCP1
I/O
TTL
16/32-Bit Timer 3 Capture/Compare/PWM 1.
PF6
I/O
TTL
GPIO port F bit 6.
I2C2SCL
I/O
OD
I2C module 2 clock. Note that this signal has an active pull-up. The
corresponding port pin should not be configured as open drain.
T3CCP0
I/O
TTL
16/32-Bit Timer 3 Capture/Compare/PWM 0.
58
59
60
61
62
PF5
I/O
TTL
GPIO port F bit 5.
M0FAULT3
I
TTL
Motion Control Module 0 PWM Fault 3.
T2CCP1
I/O
TTL
16/32-Bit Timer 2 Capture/Compare/PWM 1.
PF4
I/O
TTL
GPIO port F bit 4.
IDX0
I
TTL
QEI module 0 index.
M0FAULT2
I
TTL
Motion Control Module 0 PWM Fault 2.
M1FAULT0
I
TTL
Motion Control Module 1 PWM Fault 0.
T2CCP0
I/O
TTL
16/32-Bit Timer 2 Capture/Compare/PWM 0.
TRD3
O
TTL
Trace data 3.
U1DTR
O
TTL
UART module 1 Data Terminal Ready modem status input signal.
PF0
I/O
TTL
GPIO port F bit 0.
C0o
O
TTL
Analog comparator 0 output.
CAN0Rx
I
TTL
CAN module 0 receive.
M1PWM4
O
TTL
Motion Control Module 1 PWM 4. This signal is controlled by
Module 1 PWM Generator 2.
NMI
I
TTL
Non-maskable interrupt.
PhA0
I
TTL
QEI module 0 phase A.
SSI1Rx
I
TTL
SSI module 1 receive.
T0CCP0
I/O
TTL
16/32-Bit Timer 0 Capture/Compare/PWM 0.
TRD2
O
TTL
Trace data 2.
U1RTS
O
TTL
UART module 1 Request to Send modem flow control output line.
1242
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Table 22-2. Signals by Pin Number (continued)
Pin Number
63
a
Pin Name
Pin Type
Buffer Type
Description
PF1
I/O
TTL
GPIO port F bit 1.
C1o
O
TTL
Analog comparator 1 output.
M1PWM5
O
TTL
Motion Control Module 1 PWM 5. This signal is controlled by
Module 1 PWM Generator 2.
PhB0
I
TTL
QEI module 0 phase B.
SSI1Tx
O
TTL
SSI module 1 transmit.
T0CCP1
I/O
TTL
16/32-Bit Timer 0 Capture/Compare/PWM 1.
TRD1
O
TTL
Trace data 1.
U1CTS
I
TTL
UART module 1 Clear To Send modem flow control input signal.
PF2
I/O
TTL
GPIO port F bit 2.
C2o
O
TTL
Analog comparator 2 output.
M0FAULT0
I
TTL
Motion Control Module 0 PWM Fault 0.
M1PWM6
O
TTL
Motion Control Module 1 PWM 6. This signal is controlled by
Module 1 PWM Generator 3.
SSI1Clk
I/O
TTL
SSI module 1 clock.
T1CCP0
I/O
TTL
16/32-Bit Timer 1 Capture/Compare/PWM 0.
TRD0
O
TTL
Trace data 0.
U1DCD
I
TTL
UART module 1 Data Carrier Detect modem status input signal.
PF3
I/O
TTL
GPIO port F bit 3.
CAN0Tx
O
TTL
CAN module 0 transmit.
M0FAULT1
I
TTL
Motion Control Module 0 PWM Fault 1.
M1PWM7
O
TTL
Motion Control Module 1 PWM 7. This signal is controlled by
Module 1 PWM Generator 3.
SSI1Fss
I/O
TTL
SSI module 1 frame signal.
T1CCP1
I/O
TTL
16/32-Bit Timer 1 Capture/Compare/PWM 1.
TRCLK
O
TTL
Trace clock.
U1DSR
I
TTL
UART module 1 Data Set Ready modem output control line.
66
VDD
-
Power
Positive supply for I/O and some logic.
67
GND
-
Power
Ground reference for logic and I/O pins.
PN7
I/O
TTL
GPIO port N bit 7.
M1PWM7
O
TTL
Motion Control Module 1 PWM 7. This signal is controlled by
Module 1 PWM Generator 3.
WT4CCP1
I/O
TTL
32/64-Bit Wide Timer 4 Capture/Compare/PWM 1.
PN6
I/O
TTL
GPIO port N bit 6.
M1PWM6
O
TTL
Motion Control Module 1 PWM 6. This signal is controlled by
Module 1 PWM Generator 3.
WT4CCP0
I/O
TTL
32/64-Bit Wide Timer 4 Capture/Compare/PWM 0.
64
65
68
69
70
PN5
I/O
TTL
GPIO port N bit 5.
M1PWM5
O
TTL
Motion Control Module 1 PWM 5. This signal is controlled by
Module 1 PWM Generator 2.
WT3CCP1
I/O
TTL
32/64-Bit Wide Timer 3 Capture/Compare/PWM 1.
June 12, 2014
1243
Texas Instruments-Production Data
Signal Tables
Table 22-2. Signals by Pin Number (continued)
Pin Number
a
Pin Name
Pin Type
Buffer Type
Description
PN4
I/O
TTL
GPIO port N bit 4.
M1PWM4
O
TTL
Motion Control Module 1 PWM 4. This signal is controlled by
Module 1 PWM Generator 2.
WT3CCP0
I/O
TTL
32/64-Bit Wide Timer 3 Capture/Compare/PWM 0.
WAKE
I
TTL
An external input that brings the processor out of Hibernate mode
when asserted.
HIB
O
TTL
An output that indicates the processor is in Hibernate mode.
XOSC0
I
Analog
Hibernation module oscillator crystal input or an external clock
reference input. Note that this is either a 32.768-kHz crystal or a
32.768-kHz oscillator for the Hibernation module RTC.
GNDX
-
Power
GND for the Hibernation oscillator. When using a crystal clock
source, this pin should be connected to digital ground along with
the crystal load capacitors. When using an external oscillator, this
pin should be connected to digital ground.
XOSC1
O
Analog
Hibernation module oscillator crystal output. Leave unconnected
when using a single-ended clock source.
VBAT
-
Power
Power source for the Hibernation module. It is normally connected
to the positive terminal of a battery and serves as the battery
backup/Hibernation module power-source supply.
78
VDD
-
Power
Positive supply for I/O and some logic.
79
GND
-
Power
Ground reference for logic and I/O pins.
PN1
I/O
TTL
GPIO port N bit 1.
CAN0Tx
O
TTL
CAN module 0 transmit.
PN0
I/O
TTL
GPIO port N bit 0.
CAN0Rx
I
TTL
CAN module 0 receive.
71
72
73
74
75
76
77
80
81
82
83
PM7
I/O
TTL
GPIO port M bit 7.
M0PWM5
O
TTL
Motion Control Module 0 PWM 5. This signal is controlled by
Module 0 PWM Generator 2.
WT0CCP1
I/O
TTL
32/64-Bit Wide Timer 0 Capture/Compare/PWM 1.
PM6
I/O
TTL
GPIO port M bit 6.
M0PWM4
O
TTL
Motion Control Module 0 PWM 4. This signal is controlled by
Module 0 PWM Generator 2.
WT0CCP0
I/O
TTL
32/64-Bit Wide Timer 0 Capture/Compare/PWM 0.
84
PM5
I/O
TTL
GPIO port M bit 5.
85
PM4
I/O
TTL
GPIO port M bit 4.
PM3
I/O
TTL
GPIO port M bit 3.
T5CCP1
I/O
TTL
16/32-Bit Timer 5 Capture/Compare/PWM 1.
WT5CCP1
I/O
TTL
32/64-Bit Wide Timer 5 Capture/Compare/PWM 1.
PM2
I/O
TTL
GPIO port M bit 2.
86
87
88
T5CCP0
I/O
TTL
16/32-Bit Timer 5 Capture/Compare/PWM 0.
WT5CCP0
I/O
TTL
32/64-Bit Wide Timer 5 Capture/Compare/PWM 0.
PM1
I/O
TTL
GPIO port M bit 1.
T4CCP1
I/O
TTL
16/32-Bit Timer 4 Capture/Compare/PWM 1.
WT4CCP1
I/O
TTL
32/64-Bit Wide Timer 4 Capture/Compare/PWM 1.
1244
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Table 22-2. Signals by Pin Number (continued)
a
Pin Number
Pin Name
Pin Type
Buffer Type
Description
PM0
I/O
TTL
GPIO port M bit 0.
89
T4CCP0
I/O
TTL
16/32-Bit Timer 4 Capture/Compare/PWM 0.
WT4CCP0
I/O
TTL
32/64-Bit Wide Timer 4 Capture/Compare/PWM 0.
System reset input.
90
RST
I
TTL
91
GND
-
Power
Ground reference for logic and I/O pins.
92
OSC0
I
Analog
Main oscillator crystal input or an external clock reference input.
OSC1
O
Analog
Main oscillator crystal output. Leave unconnected when using a
single-ended clock source.
VDD
-
Power
Positive supply for I/O and some logic.
PL7
I/O
TTL
GPIO port L bit 7. This pin is not 5-V tolerant.
93
94
95
96
97
98
99
T3CCP1
I/O
TTL
16/32-Bit Timer 3 Capture/Compare/PWM 1.
WT3CCP1
I/O
TTL
32/64-Bit Wide Timer 3 Capture/Compare/PWM 1.
PL6
I/O
TTL
GPIO port L bit 6. This pin is not 5-V tolerant.
T3CCP0
I/O
TTL
16/32-Bit Timer 3 Capture/Compare/PWM 0.
WT3CCP0
I/O
TTL
32/64-Bit Wide Timer 3 Capture/Compare/PWM 0.
PB0
I/O
TTL
GPIO port B bit 0. This pin is not 5-V tolerant.
T2CCP0
I/O
TTL
16/32-Bit Timer 2 Capture/Compare/PWM 0.
U1Rx
I
TTL
UART module 1 receive.
PB1
I/O
TTL
GPIO port B bit 1. This pin is not 5-V tolerant.
T2CCP1
I/O
TTL
16/32-Bit Timer 2 Capture/Compare/PWM 1.
U1Tx
O
TTL
UART module 1 transmit.
PB2
I/O
TTL
GPIO port B bit 2.
I2C0SCL
I/O
OD
I2C module 0 clock. Note that this signal has an active pull-up. The
corresponding port pin should not be configured as open drain.
T3CCP0
I/O
TTL
16/32-Bit Timer 3 Capture/Compare/PWM 0.
PB3
I/O
TTL
GPIO port B bit 3.
I2C0SDA
I/O
OD
I2C module 0 data.
T3CCP1
I/O
TTL
16/32-Bit Timer 3 Capture/Compare/PWM 1.
101
VDD
-
Power
Positive supply for I/O and some logic.
102
GND
-
Power
Ground reference for logic and I/O pins.
PL5
I/O
TTL
GPIO port L bit 5.
100
103
104
105
106
T2CCP1
I/O
TTL
16/32-Bit Timer 2 Capture/Compare/PWM 1.
WT2CCP1
I/O
TTL
32/64-Bit Wide Timer 2 Capture/Compare/PWM 1.
PL4
I/O
TTL
GPIO port L bit 4.
T2CCP0
I/O
TTL
16/32-Bit Timer 2 Capture/Compare/PWM 0.
WT2CCP0
I/O
TTL
32/64-Bit Wide Timer 2 Capture/Compare/PWM 0.
PL3
I/O
TTL
GPIO port L bit 3.
T1CCP1
I/O
TTL
16/32-Bit Timer 1 Capture/Compare/PWM 1.
WT1CCP1
I/O
TTL
32/64-Bit Wide Timer 1 Capture/Compare/PWM 1.
PL2
I/O
TTL
GPIO port L bit 2.
T1CCP0
I/O
TTL
16/32-Bit Timer 1 Capture/Compare/PWM 0.
WT1CCP0
I/O
TTL
32/64-Bit Wide Timer 1 Capture/Compare/PWM 0.
June 12, 2014
1245
Texas Instruments-Production Data
Signal Tables
Table 22-2. Signals by Pin Number (continued)
a
Pin Number
Pin Name
Pin Type
Buffer Type
PL1
I/O
TTL
GPIO port L bit 1.
107
T0CCP1
I/O
TTL
16/32-Bit Timer 0 Capture/Compare/PWM 1.
WT0CCP1
I/O
TTL
32/64-Bit Wide Timer 0 Capture/Compare/PWM 1.
108
109
Description
PL0
I/O
TTL
GPIO port L bit 0.
T0CCP0
I/O
TTL
16/32-Bit Timer 0 Capture/Compare/PWM 0.
WT0CCP0
I/O
TTL
32/64-Bit Wide Timer 0 Capture/Compare/PWM 0.
PK7
I/O
TTL
GPIO port K bit 7.
M0FAULT3
I
TTL
Motion Control Module 0 PWM Fault 3.
WT1CCP1
I/O
TTL
32/64-Bit Wide Timer 1 Capture/Compare/PWM 1.
PK6
I/O
TTL
GPIO port K bit 6.
C2o
O
TTL
Analog comparator 2 output.
M0FAULT2
I
TTL
Motion Control Module 0 PWM Fault 2.
WT1CCP0
I/O
TTL
32/64-Bit Wide Timer 1 Capture/Compare/PWM 0.
PK5
I/O
TTL
GPIO port K bit 5.
C1o
O
TTL
Analog comparator 1 output.
M0FAULT1
I
TTL
Motion Control Module 0 PWM Fault 1.
U7Tx
O
TTL
UART module 7 transmit.
PK4
I/O
TTL
GPIO port K bit 4.
110
111
C0o
O
TTL
Analog comparator 0 output.
M0FAULT0
I
TTL
Motion Control Module 0 PWM Fault 0.
RTCCLK
O
TTL
Buffered version of the Hibernation module's 32.768-kHz clock.
This signal is not output when the part is in Hibernate mode.
U7Rx
I
TTL
UART module 7 receive.
113
VDD
-
Power
Positive supply for I/O and some logic.
114
GND
-
Power
Ground reference for logic and I/O pins.
PC3
I/O
TTL
GPIO port C bit 3.
SWO
O
TTL
JTAG TDO and SWO.
T5CCP1
I/O
TTL
16/32-Bit Timer 5 Capture/Compare/PWM 1.
TDO
O
TTL
JTAG TDO and SWO.
PC2
I/O
TTL
GPIO port C bit 2.
T5CCP0
I/O
TTL
16/32-Bit Timer 5 Capture/Compare/PWM 0.
TDI
I
TTL
JTAG TDI.
PC1
I/O
TTL
GPIO port C bit 1.
112
115
116
SWDIO
I/O
TTL
JTAG TMS and SWDIO.
T4CCP1
I/O
TTL
16/32-Bit Timer 4 Capture/Compare/PWM 1.
TMS
I
TTL
JTAG TMS and SWDIO.
117
PC0
I/O
TTL
GPIO port C bit 0.
SWCLK
I
TTL
JTAG/SWD CLK.
T4CCP0
I/O
TTL
16/32-Bit Timer 4 Capture/Compare/PWM 0.
TCK
I
TTL
JTAG/SWD CLK.
118
1246
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Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Table 22-2. Signals by Pin Number (continued)
Pin Number
119
120
121
Pin Type
Buffer Type
124
125
Description
PN3
I/O
TTL
GPIO port N bit 3.
M0PWM7
O
TTL
Motion Control Module 0 PWM 7. This signal is controlled by
Module 0 PWM Generator 3.
WT2CCP1
I/O
TTL
32/64-Bit Wide Timer 2 Capture/Compare/PWM 1.
PJ0
I/O
TTL
GPIO port J bit 0.
T1CCP0
I/O
TTL
16/32-Bit Timer 1 Capture/Compare/PWM 0.
U4Rx
I
TTL
UART module 4 receive.
PJ1
I/O
TTL
GPIO port J bit 1.
T1CCP1
I/O
TTL
16/32-Bit Timer 1 Capture/Compare/PWM 1.
U4Tx
O
TTL
UART module 4 transmit.
PJ2
I/O
TTL
GPIO port J bit 2.
IDX0
I
TTL
QEI module 0 index.
T2CCP0
I/O
TTL
16/32-Bit Timer 2 Capture/Compare/PWM 0.
U5Rx
I
TTL
UART module 5 receive.
PJ3
I/O
TTL
GPIO port J bit 3.
T2CCP1
I/O
TTL
16/32-Bit Timer 2 Capture/Compare/PWM 1.
U5Tx
O
TTL
UART module 5 transmit.
VDD
-
Power
Positive supply for I/O and some logic.
122
123
a
Pin Name
GND
-
Power
Ground reference for logic and I/O pins.
VDDC
-
Power
Positive supply for most of the logic function, including the
processor core and most peripherals. The voltage on this pin is
1.2 V and is supplied by the on-chip LDO. The VDDC pins should
only be connected to each other and an external capacitor as
specified in Table 23-12 on page 1297 .
PJ4
I/O
TTL
C2+
I
Analog
T3CCP0
I/O
TTL
16/32-Bit Timer 3 Capture/Compare/PWM 0.
U6Rx
I
TTL
UART module 6 receive.
PJ5
I/O
TTL
GPIO port J bit 5.
126
127
GPIO port J bit 4.
Analog comparator 2 positive input.
C2-
I
Analog
T3CCP1
I/O
TTL
16/32-Bit Timer 3 Capture/Compare/PWM 1.
U6Tx
O
TTL
UART module 6 transmit.
129
PJ6
I/O
TTL
GPIO port J bit 6.
130
PJ7
I/O
TTL
GPIO port J bit 7.
GPIO port P bit 0.
128
131
Analog comparator 2 negative input.
PP0
I/O
TTL
AIN23
I
Analog
M0PWM0
O
TTL
Motion Control Module 0 PWM 0. This signal is controlled by
Module 0 PWM Generator 0.
T4CCP0
I/O
TTL
16/32-Bit Timer 4 Capture/Compare/PWM 0.
Analog-to-digital converter input 23.
June 12, 2014
1247
Texas Instruments-Production Data
Signal Tables
Table 22-2. Signals by Pin Number (continued)
Pin Number
132
133
Pin Name
Pin Type
136
Description
PP1
I/O
TTL
AIN22
I
Analog
M0PWM1
O
TTL
Motion Control Module 0 PWM 1. This signal is controlled by
Module 0 PWM Generator 0.
T4CCP1
I/O
TTL
16/32-Bit Timer 4 Capture/Compare/PWM 1.
PE6
I/O
TTL
GPIO port E bit 6.
AIN21
I
Analog
CAN1Rx
I
TTL
CAN module 1 receive.
PE7
I/O
TTL
GPIO port E bit 7.
AIN20
I
Analog
CAN1Tx
O
TTL
CAN module 1 transmit.
U1RI
I
TTL
UART module 1 Ring Indicator modem status input signal.
PB5
I/O
TTL
GPIO port B bit 5.
134
135
a
Buffer Type
GPIO port P bit 1.
Analog-to-digital converter input 22.
Analog-to-digital converter input 21.
Analog-to-digital converter input 20.
AIN11
I
Analog
CAN0Tx
O
TTL
Analog-to-digital converter input 11.
CAN module 0 transmit.
M0PWM3
O
TTL
Motion Control Module 0 PWM 3. This signal is controlled by
Module 0 PWM Generator 1.
SSI2Fss
I/O
TTL
SSI module 2 frame signal.
T1CCP1
I/O
TTL
16/32-Bit Timer 1 Capture/Compare/PWM 1.
PB4
I/O
TTL
GPIO port B bit 4.
AIN10
I
Analog
CAN0Rx
I
TTL
Analog-to-digital converter input 10.
CAN module 0 receive.
M0PWM2
O
TTL
Motion Control Module 0 PWM 2. This signal is controlled by
Module 0 PWM Generator 1.
SSI2Clk
I/O
TTL
SSI module 2 clock.
16/32-Bit Timer 1 Capture/Compare/PWM 0.
T1CCP0
I/O
TTL
137
VDD
-
Power
Positive supply for I/O and some logic.
138
GND
-
Power
Ground reference for logic and I/O pins.
PE4
I/O
TTL
AIN9
I
Analog
GPIO port E bit 4.
Analog-to-digital converter input 9.
CAN0Rx
I
TTL
CAN module 0 receive.
I2C2SCL
I/O
OD
I2C module 2 clock. Note that this signal has an active pull-up. The
corresponding port pin should not be configured as open drain.
M0PWM4
O
TTL
Motion Control Module 0 PWM 4. This signal is controlled by
Module 0 PWM Generator 2.
M1PWM2
O
TTL
Motion Control Module 1 PWM 2. This signal is controlled by
Module 1 PWM Generator 1.
U5Rx
I
TTL
UART module 5 receive.
139
1248
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Table 22-2. Signals by Pin Number (continued)
Pin Number
140
Pin Name
Pin Type
Description
PE5
I/O
TTL
AIN8
I
Analog
CAN0Tx
O
TTL
CAN module 0 transmit.
I2C2SDA
I/O
OD
I2C module 2 data.
M0PWM5
O
TTL
Motion Control Module 0 PWM 5. This signal is controlled by
Module 0 PWM Generator 2.
M1PWM3
O
TTL
Motion Control Module 1 PWM 3. This signal is controlled by
Module 1 PWM Generator 1.
U5Tx
O
TTL
UART module 5 transmit.
PD4
I/O
TTL
GPIO port D bit 4.
AIN7
I
Analog
U6Rx
I
TTL
UART module 6 receive.
WT4CCP0
I/O
TTL
32/64-Bit Wide Timer 4 Capture/Compare/PWM 0.
PD5
I/O
TTL
GPIO port D bit 5.
AIN6
I
Analog
141
142
GPIO port E bit 5.
Analog-to-digital converter input 8.
Analog-to-digital converter input 7.
Analog-to-digital converter input 6.
U6Tx
O
TTL
UART module 6 transmit.
WT4CCP1
I/O
TTL
32/64-Bit Wide Timer 4 Capture/Compare/PWM 1.
GPIO port D bit 6.
PD6
I/O
TTL
AIN5
I
Analog
M0FAULT0
I
TTL
Motion Control Module 0 PWM Fault 0.
PhA0
I
TTL
QEI module 0 phase A.
U2Rx
I
TTL
UART module 2 receive.
WT5CCP0
I/O
TTL
32/64-Bit Wide Timer 5 Capture/Compare/PWM 0.
GPIO port D bit 7.
143
144
a
Buffer Type
Analog-to-digital converter input 5.
PD7
I/O
TTL
AIN4
I
Analog
M0FAULT1
I
TTL
Motion Control Module 0 PWM Fault 1.
NMI
I
TTL
Non-maskable interrupt.
PhB0
I
TTL
QEI module 0 phase B.
U2Tx
O
TTL
UART module 2 transmit.
WT5CCP1
I/O
TTL
32/64-Bit Wide Timer 5 Capture/Compare/PWM 1.
Analog-to-digital converter input 4.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
22.2
Signals by Signal Name
Table 22-3. Signals by Signal Name
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
AIN0
12
PE3
I
Analog
Analog-to-digital converter input 0.
AIN1
13
PE2
I
Analog
Analog-to-digital converter input 1.
AIN2
14
PE1
I
Analog
Analog-to-digital converter input 2.
AIN3
15
PE0
I
Analog
Analog-to-digital converter input 3.
AIN4
144
PD7
I
Analog
Analog-to-digital converter input 4.
June 12, 2014
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Texas Instruments-Production Data
Signal Tables
Table 22-3. Signals by Signal Name (continued)
Pin Name
AIN5
Pin Number Pin Mux / Pin
Assignment
143
PD6
a
Pin Type
Buffer Type
I
Analog
Description
Analog-to-digital converter input 5.
AIN6
142
PD5
I
Analog
Analog-to-digital converter input 6.
AIN7
141
PD4
I
Analog
Analog-to-digital converter input 7.
AIN8
140
PE5
I
Analog
Analog-to-digital converter input 8.
AIN9
139
PE4
I
Analog
Analog-to-digital converter input 9.
AIN10
136
PB4
I
Analog
Analog-to-digital converter input 10.
AIN11
135
PB5
I
Analog
Analog-to-digital converter input 11.
AIN12
4
PD3
I
Analog
Analog-to-digital converter input 12.
AIN13
3
PD2
I
Analog
Analog-to-digital converter input 13.
AIN14
2
PD1
I
Analog
Analog-to-digital converter input 14.
AIN15
1
PD0
I
Analog
Analog-to-digital converter input 15.
AIN16
16
PK0
I
Analog
Analog-to-digital converter input 16.
AIN17
17
PK1
I
Analog
Analog-to-digital converter input 17.
AIN18
18
PK2
I
Analog
Analog-to-digital converter input 18.
AIN19
19
PK3
I
Analog
Analog-to-digital converter input 19.
AIN20
134
PE7
I
Analog
Analog-to-digital converter input 20.
AIN21
133
PE6
I
Analog
Analog-to-digital converter input 21.
AIN22
132
PP1
I
Analog
Analog-to-digital converter input 22.
AIN23
131
PP0
I
Analog
Analog-to-digital converter input 23.
C0+
34
PC6
I
Analog
Analog comparator 0 positive input.
C0-
33
PC7
I
Analog
Analog comparator 0 negative input.
C0o
62
112
PF0 (9)
PK4 (8)
O
TTL
C1+
35
PC5
I
Analog
Analog comparator 1 positive input.
C1-
36
PC4
I
Analog
Analog comparator 1 negative input.
C1o
63
111
PF1 (9)
PK5 (8)
O
TTL
C2+
127
PJ4
I
Analog
Analog comparator 2 positive input.
Analog comparator 2 negative input.
Analog comparator 0 output.
Analog comparator 1 output.
C2-
128
PJ5
I
Analog
C2o
64
110
PF2 (9)
PK6 (8)
O
TTL
Analog comparator 2 output.
CAN0Rx
62
81
136
139
PF0 (3)
PN0 (1)
PB4 (8)
PE4 (8)
I
TTL
CAN module 0 receive.
CAN0Tx
65
80
135
140
PF3 (3)
PN1 (1)
PB5 (8)
PE5 (8)
O
TTL
CAN module 0 transmit.
CAN1Rx
37
133
PA0 (8)
PE6 (8)
I
TTL
CAN module 1 receive.
CAN1Tx
38
134
PA1 (8)
PE7 (8)
O
TTL
CAN module 1 transmit.
1250
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Table 22-3. Signals by Signal Name (continued)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
GND
6
25
30
44
57
67
79
91
102
114
125
138
fixed
-
Power
Ground reference for logic and I/O pins.
GNDA
10
fixed
-
Power
The ground reference for the analog circuits (ADC,
Analog Comparators, etc.). These are separated
from GND to minimize the electrical noise contained
on VDD from affecting the analog functions.
GNDX
75
fixed
-
Power
GND for the Hibernation oscillator. When using a
crystal clock source, this pin should be connected
to digital ground along with the crystal load
capacitors. When using an external oscillator, this
pin should be connected to digital ground.
HIB
73
fixed
O
TTL
An output that indicates the processor is in
Hibernate mode.
I2C0SCL
99
PB2 (3)
I/O
OD
I2C module 0 clock. Note that this signal has an
active pull-up. The corresponding port pin should
not be configured as open drain.
I2C0SDA
100
PB3 (3)
I/O
OD
I2C module 0 data.
I2C1SCL
45
51
PA6 (3)
PG4 (3)
I/O
OD
I2C module 1 clock. Note that this signal has an
active pull-up. The corresponding port pin should
not be configured as open drain.
I2C1SDA
46
50
PA7 (3)
PG5 (3)
I/O
OD
I2C module 1 data.
I2C2SCL
59
139
PF6 (3)
PE4 (3)
I/O
OD
I2C module 2 clock. Note that this signal has an
active pull-up. The corresponding port pin should
not be configured as open drain.
I2C2SDA
58
140
PF7 (3)
PE5 (3)
I/O
OD
I2C module 2 data.
I2C3SCL
1
55
PD0 (3)
PG0 (3)
I/O
OD
I2C module 3 clock. Note that this signal has an
active pull-up. The corresponding port pin should
not be configured as open drain.
I2C3SDA
2
54
PD1 (3)
PG1 (3)
I/O
OD
I2C module 3 data.
I2C4SCL
53
PG2 (3)
I/O
OD
I2C module 4 clock. Note that this signal has an
active pull-up. The corresponding port pin should
not be configured as open drain.
I2C4SDA
52
PG3 (3)
I/O
OD
I2C module 4 data.
I2C5SCL
48
PG6 (3)
I/O
OD
I2C module 5 clock. Note that this signal has an
active pull-up. The corresponding port pin should
not be configured as open drain.
I2C5SDA
47
PG7 (3)
I/O
OD
I2C module 5 data.
June 12, 2014
1251
Texas Instruments-Production Data
Signal Tables
Table 22-3. Signals by Signal Name (continued)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
IDX0
4
31
61
122
PD3 (6)
PH1 (5)
PF4 (6)
PJ2 (5)
I
TTL
QEI module 0 index.
IDX1
36
47
50
PC4 (6)
PG7 (5)
PG5 (6)
I
TTL
QEI module 1 index.
M0FAULT0
3
32
64
112
143
PD2 (4)
PH0 (6)
PF2 (4)
PK4 (6)
PD6 (4)
I
TTL
Motion Control Module 0 PWM Fault 0.
M0FAULT1
31
53
65
111
144
PH1 (6)
PG2 (4)
PF3 (4)
PK5 (6)
PD7 (4)
I
TTL
Motion Control Module 0 PWM Fault 1.
M0FAULT2
28
52
61
110
PH2 (6)
PG3 (4)
PF4 (4)
PK6 (6)
I
TTL
Motion Control Module 0 PWM Fault 2.
M0FAULT3
27
60
109
PH3 (6)
PF5 (4)
PK7 (6)
I
TTL
Motion Control Module 0 PWM Fault 3.
M0PWM0
32
131
PH0 (4)
PP0 (1)
O
TTL
Motion Control Module 0 PWM 0. This signal is
controlled by Module 0 PWM Generator 0.
M0PWM1
31
132
PH1 (4)
PP1 (1)
O
TTL
Motion Control Module 0 PWM 1. This signal is
controlled by Module 0 PWM Generator 0.
M0PWM2
11
28
136
PP2 (1)
PH2 (4)
PB4 (4)
O
TTL
Motion Control Module 0 PWM 2. This signal is
controlled by Module 0 PWM Generator 1.
M0PWM3
27
135
PH3 (4)
PB5 (4)
O
TTL
Motion Control Module 0 PWM 3. This signal is
controlled by Module 0 PWM Generator 1.
M0PWM4
26
51
83
139
PH4 (4)
PG4 (4)
PM6 (2)
PE4 (4)
O
TTL
Motion Control Module 0 PWM 4. This signal is
controlled by Module 0 PWM Generator 2.
M0PWM5
23
50
82
140
PH5 (4)
PG5 (4)
PM7 (2)
PE5 (4)
O
TTL
Motion Control Module 0 PWM 5. This signal is
controlled by Module 0 PWM Generator 2.
M0PWM6
1
20
22
36
48
PD0 (4)
PN2 (2)
PH6 (4)
PC4 (4)
PG6 (4)
O
TTL
Motion Control Module 0 PWM 6. This signal is
controlled by Module 0 PWM Generator 3.
M0PWM7
2
21
35
47
119
PD1 (4)
PH7 (4)
PC5 (4)
PG7 (4)
PN3 (2)
O
TTL
Motion Control Module 0 PWM 7. This signal is
controlled by Module 0 PWM Generator 3.
1252
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Table 22-3. Signals by Signal Name (continued)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
M1FAULT0
16
58
61
PK0 (6)
PF7 (5)
PF4 (5)
I
TTL
Motion Control Module 1 PWM Fault 0.
M1FAULT1
17
55
PK1 (6)
PG0 (5)
I
TTL
Motion Control Module 1 PWM Fault 1.
M1FAULT2
18
54
PK2 (6)
PG1 (5)
I
TTL
Motion Control Module 1 PWM Fault 2.
M1FAULT3
19
PK3 (6)
I
TTL
Motion Control Module 1 PWM Fault 3.
M1PWM0
1
53
PD0 (5)
PG2 (5)
O
TTL
Motion Control Module 1 PWM 0. This signal is
controlled by Module 1 PWM Generator 0.
M1PWM1
2
52
PD1 (5)
PG3 (5)
O
TTL
Motion Control Module 1 PWM 1. This signal is
controlled by Module 1 PWM Generator 0.
M1PWM2
45
51
139
PA6 (5)
PG4 (5)
PE4 (5)
O
TTL
Motion Control Module 1 PWM 2. This signal is
controlled by Module 1 PWM Generator 1.
M1PWM3
46
50
140
PA7 (5)
PG5 (5)
PE5 (5)
O
TTL
Motion Control Module 1 PWM 3. This signal is
controlled by Module 1 PWM Generator 1.
M1PWM4
62
71
PF0 (5)
PN4 (2)
O
TTL
Motion Control Module 1 PWM 4. This signal is
controlled by Module 1 PWM Generator 2.
M1PWM5
63
70
PF1 (5)
PN5 (2)
O
TTL
Motion Control Module 1 PWM 5. This signal is
controlled by Module 1 PWM Generator 2.
M1PWM6
64
69
PF2 (5)
PN6 (2)
O
TTL
Motion Control Module 1 PWM 6. This signal is
controlled by Module 1 PWM Generator 3.
M1PWM7
65
68
PF3 (5)
PN7 (2)
O
TTL
Motion Control Module 1 PWM 7. This signal is
controlled by Module 1 PWM Generator 3.
NMI
62
144
PF0 (8)
PD7 (8)
I
TTL
Non-maskable interrupt.
OSC0
92
fixed
I
Analog
Main oscillator crystal input or an external clock
reference input.
OSC1
93
fixed
O
Analog
Main oscillator crystal output. Leave unconnected
when using a single-ended clock source.
PA0
37
-
I/O
TTL
GPIO port A bit 0.
PA1
38
-
I/O
TTL
GPIO port A bit 1.
PA2
39
-
I/O
TTL
GPIO port A bit 2.
PA3
40
-
I/O
TTL
GPIO port A bit 3.
PA4
41
-
I/O
TTL
GPIO port A bit 4.
PA5
42
-
I/O
TTL
GPIO port A bit 5.
PA6
45
-
I/O
TTL
GPIO port A bit 6.
PA7
46
-
I/O
TTL
GPIO port A bit 7.
PB0
97
-
I/O
TTL
GPIO port B bit 0. This pin is not 5-V tolerant.
PB1
98
-
I/O
TTL
GPIO port B bit 1. This pin is not 5-V tolerant.
PB2
99
-
I/O
TTL
GPIO port B bit 2.
PB3
100
-
I/O
TTL
GPIO port B bit 3.
PB4
136
-
I/O
TTL
GPIO port B bit 4.
PB5
135
-
I/O
TTL
GPIO port B bit 5.
June 12, 2014
1253
Texas Instruments-Production Data
Signal Tables
Table 22-3. Signals by Signal Name (continued)
Pin Name
PC0
Pin Number Pin Mux / Pin
Assignment
118
-
a
Pin Type
Buffer Type
I/O
TTL
Description
GPIO port C bit 0.
PC1
117
-
I/O
TTL
GPIO port C bit 1.
PC2
116
-
I/O
TTL
GPIO port C bit 2.
PC3
115
-
I/O
TTL
GPIO port C bit 3.
PC4
36
-
I/O
TTL
GPIO port C bit 4.
PC5
35
-
I/O
TTL
GPIO port C bit 5.
PC6
34
-
I/O
TTL
GPIO port C bit 6.
PC7
33
-
I/O
TTL
GPIO port C bit 7.
PD0
1
-
I/O
TTL
GPIO port D bit 0.
PD1
2
-
I/O
TTL
GPIO port D bit 1.
PD2
3
-
I/O
TTL
GPIO port D bit 2.
PD3
4
-
I/O
TTL
GPIO port D bit 3.
PD4
141
-
I/O
TTL
GPIO port D bit 4.
PD5
142
-
I/O
TTL
GPIO port D bit 5.
PD6
143
-
I/O
TTL
GPIO port D bit 6.
PD7
144
-
I/O
TTL
GPIO port D bit 7.
PE0
15
-
I/O
TTL
GPIO port E bit 0.
PE1
14
-
I/O
TTL
GPIO port E bit 1.
PE2
13
-
I/O
TTL
GPIO port E bit 2.
PE3
12
-
I/O
TTL
GPIO port E bit 3.
PE4
139
-
I/O
TTL
GPIO port E bit 4.
PE5
140
-
I/O
TTL
GPIO port E bit 5.
PE6
133
-
I/O
TTL
GPIO port E bit 6.
PE7
134
-
I/O
TTL
GPIO port E bit 7.
PF0
62
-
I/O
TTL
GPIO port F bit 0.
PF1
63
-
I/O
TTL
GPIO port F bit 1.
PF2
64
-
I/O
TTL
GPIO port F bit 2.
PF3
65
-
I/O
TTL
GPIO port F bit 3.
PF4
61
-
I/O
TTL
GPIO port F bit 4.
PF5
60
-
I/O
TTL
GPIO port F bit 5.
PF6
59
-
I/O
TTL
GPIO port F bit 6.
PF7
58
-
I/O
TTL
GPIO port F bit 7.
PG0
55
-
I/O
TTL
GPIO port G bit 0.
PG1
54
-
I/O
TTL
GPIO port G bit 1.
PG2
53
-
I/O
TTL
GPIO port G bit 2.
PG3
52
-
I/O
TTL
GPIO port G bit 3.
PG4
51
-
I/O
TTL
GPIO port G bit 4.
PG5
50
-
I/O
TTL
GPIO port G bit 5.
PG6
48
-
I/O
TTL
GPIO port G bit 6.
PG7
47
-
I/O
TTL
GPIO port G bit 7.
PH0
32
-
I/O
TTL
GPIO port H bit 0.
1254
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Table 22-3. Signals by Signal Name (continued)
Pin Name
PH1
Pin Number Pin Mux / Pin
Assignment
31
-
a
Pin Type
Buffer Type
I/O
TTL
Description
GPIO port H bit 1.
PH2
28
-
I/O
TTL
GPIO port H bit 2.
PH3
27
-
I/O
TTL
GPIO port H bit 3.
PH4
26
-
I/O
TTL
GPIO port H bit 4.
PH5
23
-
I/O
TTL
GPIO port H bit 5.
PH6
22
-
I/O
TTL
GPIO port H bit 6.
PH7
21
-
I/O
TTL
GPIO port H bit 7.
PhA0
26
62
143
PH4 (5)
PF0 (6)
PD6 (6)
I
TTL
QEI module 0 phase A.
PhA1
35
52
55
PC5 (6)
PG3 (6)
PG0 (6)
I
TTL
QEI module 1 phase A.
PhB0
23
63
144
PH5 (5)
PF1 (6)
PD7 (6)
I
TTL
QEI module 0 phase B.
PhB1
34
51
54
PC6 (6)
PG4 (6)
PG1 (6)
I
TTL
QEI module 1 phase B.
PJ0
120
-
I/O
TTL
GPIO port J bit 0.
PJ1
121
-
I/O
TTL
GPIO port J bit 1.
PJ2
122
-
I/O
TTL
GPIO port J bit 2.
PJ3
123
-
I/O
TTL
GPIO port J bit 3.
PJ4
127
-
I/O
TTL
GPIO port J bit 4.
PJ5
128
-
I/O
TTL
GPIO port J bit 5.
PJ6
129
-
I/O
TTL
GPIO port J bit 6.
PJ7
130
-
I/O
TTL
GPIO port J bit 7.
PK0
16
-
I/O
TTL
GPIO port K bit 0.
PK1
17
-
I/O
TTL
GPIO port K bit 1.
PK2
18
-
I/O
TTL
GPIO port K bit 2.
PK3
19
-
I/O
TTL
GPIO port K bit 3.
PK4
112
-
I/O
TTL
GPIO port K bit 4.
PK5
111
-
I/O
TTL
GPIO port K bit 5.
PK6
110
-
I/O
TTL
GPIO port K bit 6.
PK7
109
-
I/O
TTL
GPIO port K bit 7.
PL0
108
-
I/O
TTL
GPIO port L bit 0.
PL1
107
-
I/O
TTL
GPIO port L bit 1.
PL2
106
-
I/O
TTL
GPIO port L bit 2.
PL3
105
-
I/O
TTL
GPIO port L bit 3.
PL4
104
-
I/O
TTL
GPIO port L bit 4.
PL5
103
-
I/O
TTL
GPIO port L bit 5.
PL6
96
-
I/O
TTL
GPIO port L bit 6. This pin is not 5-V tolerant.
PL7
95
-
I/O
TTL
GPIO port L bit 7. This pin is not 5-V tolerant.
June 12, 2014
1255
Texas Instruments-Production Data
Signal Tables
Table 22-3. Signals by Signal Name (continued)
Pin Name
PM0
Pin Number Pin Mux / Pin
Assignment
89
-
a
Pin Type
Buffer Type
I/O
TTL
Description
GPIO port M bit 0.
PM1
88
-
I/O
TTL
GPIO port M bit 1.
PM2
87
-
I/O
TTL
GPIO port M bit 2.
PM3
86
-
I/O
TTL
GPIO port M bit 3.
PM4
85
-
I/O
TTL
GPIO port M bit 4.
PM5
84
-
I/O
TTL
GPIO port M bit 5.
PM6
83
-
I/O
TTL
GPIO port M bit 6.
PM7
82
-
I/O
TTL
GPIO port M bit 7.
PN0
81
-
I/O
TTL
GPIO port N bit 0.
PN1
80
-
I/O
TTL
GPIO port N bit 1.
PN2
20
-
I/O
TTL
GPIO port N bit 2.
PN3
119
-
I/O
TTL
GPIO port N bit 3.
PN4
71
-
I/O
TTL
GPIO port N bit 4.
PN5
70
-
I/O
TTL
GPIO port N bit 5.
PN6
69
-
I/O
TTL
GPIO port N bit 6.
PN7
68
-
I/O
TTL
GPIO port N bit 7.
PP0
131
-
I/O
TTL
GPIO port P bit 0.
PP1
132
-
I/O
TTL
GPIO port P bit 1.
PP2
11
-
I/O
TTL
GPIO port P bit 2.
RST
90
fixed
I
TTL
System reset input.
RTCCLK
112
PK4 (7)
O
TTL
Buffered version of the Hibernation module's
32.768-kHz clock. This signal is not output when
the part is in Hibernate mode.
SSI0Clk
39
PA2 (2)
I/O
TTL
SSI module 0 clock
SSI0Fss
40
PA3 (2)
I/O
TTL
SSI module 0 frame signal
SSI0Rx
41
PA4 (2)
I
TTL
SSI module 0 receive
SSI0Tx
42
PA5 (2)
O
TTL
SSI module 0 transmit
SSI1Clk
1
64
PD0 (2)
PF2 (2)
I/O
TTL
SSI module 1 clock.
SSI1Fss
2
65
PD1 (2)
PF3 (2)
I/O
TTL
SSI module 1 frame signal.
SSI1Rx
3
62
PD2 (2)
PF0 (2)
I
TTL
SSI module 1 receive.
SSI1Tx
4
63
PD3 (2)
PF1 (2)
O
TTL
SSI module 1 transmit.
SSI2Clk
26
136
PH4 (2)
PB4 (2)
I/O
TTL
SSI module 2 clock.
SSI2Fss
23
135
PH5 (2)
PB5 (2)
I/O
TTL
SSI module 2 frame signal.
SSI2Rx
22
PH6 (2)
I
TTL
SSI module 2 receive.
SSI2Tx
21
PH7 (2)
O
TTL
SSI module 2 transmit.
SSI3Clk
1
16
32
PD0 (1)
PK0 (2)
PH0 (2)
I/O
TTL
SSI module 3 clock.
1256
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Table 22-3. Signals by Signal Name (continued)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
SSI3Fss
2
17
31
PD1 (1)
PK1 (2)
PH1 (2)
I/O
TTL
SSI module 3 frame signal.
SSI3Rx
3
18
28
PD2 (1)
PK2 (2)
PH2 (2)
I
TTL
SSI module 3 receive.
SSI3Tx
4
19
27
PD3 (1)
PK3 (2)
PH3 (2)
O
TTL
SSI module 3 transmit.
SWCLK
118
PC0 (1)
I
TTL
JTAG/SWD CLK.
SWDIO
117
PC1 (1)
I/O
TTL
JTAG TMS and SWDIO.
SWO
115
PC3 (1)
O
TTL
JTAG TDO and SWO.
T0CCP0
62
108
PF0 (7)
PL0 (7)
I/O
TTL
16/32-Bit Timer 0 Capture/Compare/PWM 0.
T0CCP1
63
107
PF1 (7)
PL1 (7)
I/O
TTL
16/32-Bit Timer 0 Capture/Compare/PWM 1.
T1CCP0
64
106
120
136
PF2 (7)
PL2 (7)
PJ0 (7)
PB4 (7)
I/O
TTL
16/32-Bit Timer 1 Capture/Compare/PWM 0.
T1CCP1
65
105
121
135
PF3 (7)
PL3 (7)
PJ1 (7)
PB5 (7)
I/O
TTL
16/32-Bit Timer 1 Capture/Compare/PWM 1.
T2CCP0
61
97
104
122
PF4 (7)
PB0 (7)
PL4 (7)
PJ2 (7)
I/O
TTL
16/32-Bit Timer 2 Capture/Compare/PWM 0.
T2CCP1
60
98
103
123
PF5 (7)
PB1 (7)
PL5 (7)
PJ3 (7)
I/O
TTL
16/32-Bit Timer 2 Capture/Compare/PWM 1.
T3CCP0
59
96
99
127
PF6 (7)
PL6 (7)
PB2 (7)
PJ4 (7)
I/O
TTL
16/32-Bit Timer 3 Capture/Compare/PWM 0.
T3CCP1
58
95
100
128
PF7 (7)
PL7 (7)
PB3 (7)
PJ5 (7)
I/O
TTL
16/32-Bit Timer 3 Capture/Compare/PWM 1.
T4CCP0
55
89
118
131
PG0 (7)
PM0 (7)
PC0 (7)
PP0 (7)
I/O
TTL
16/32-Bit Timer 4 Capture/Compare/PWM 0.
T4CCP1
54
88
117
132
PG1 (7)
PM1 (7)
PC1 (7)
PP1 (7)
I/O
TTL
16/32-Bit Timer 4 Capture/Compare/PWM 1.
June 12, 2014
1257
Texas Instruments-Production Data
Signal Tables
Table 22-3. Signals by Signal Name (continued)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
T5CCP0
11
53
87
116
PP2 (7)
PG2 (7)
PM2 (7)
PC2 (7)
I/O
TTL
16/32-Bit Timer 5 Capture/Compare/PWM 0.
T5CCP1
52
86
115
PG3 (7)
PM3 (7)
PC3 (7)
I/O
TTL
16/32-Bit Timer 5 Capture/Compare/PWM 1.
TCK
118
PC0 (1)
I
TTL
JTAG/SWD CLK.
TDI
116
PC2 (1)
I
TTL
JTAG TDI.
TDO
115
PC3 (1)
O
TTL
JTAG TDO and SWO.
TMS
117
PC1 (1)
I
TTL
JTAG TMS and SWDIO.
TRCLK
65
PF3 (14)
O
TTL
Trace clock.
TRD0
64
PF2 (14)
O
TTL
Trace data 0.
TRD1
63
PF1 (14)
O
TTL
Trace data 1.
TRD2
62
PF0 (14)
O
TTL
Trace data 2.
TRD3
61
PF4 (14)
O
TTL
Trace data 3.
U0Rx
37
PA0 (1)
I
TTL
UART module 0 receive.
U0Tx
38
PA1 (1)
O
TTL
UART module 0 transmit.
U1CTS
35
63
PC5 (8)
PF1 (1)
I
TTL
UART module 1 Clear To Send modem flow control
input signal.
U1DCD
64
PF2 (1)
I
TTL
UART module 1 Data Carrier Detect modem status
input signal.
U1DSR
65
PF3 (1)
I
TTL
UART module 1 Data Set Ready modem output
control line.
U1DTR
61
PF4 (1)
O
TTL
UART module 1 Data Terminal Ready modem
status input signal.
U1RI
134
PE7 (1)
I
TTL
UART module 1 Ring Indicator modem status input
signal.
U1RTS
36
62
PC4 (8)
PF0 (1)
O
TTL
UART module 1 Request to Send modem flow
control output line.
U1Rx
36
97
PC4 (2)
PB0 (1)
I
TTL
UART module 1 receive.
U1Tx
35
98
PC5 (2)
PB1 (1)
O
TTL
UART module 1 transmit.
U2Rx
51
143
PG4 (1)
PD6 (1)
I
TTL
UART module 2 receive.
U2Tx
50
144
PG5 (1)
PD7 (1)
O
TTL
UART module 2 transmit.
U3Rx
34
PC6 (1)
I
TTL
UART module 3 receive.
U3Tx
33
PC7 (1)
O
TTL
UART module 3 transmit.
U4Rx
36
120
PC4 (1)
PJ0 (1)
I
TTL
UART module 4 receive.
U4Tx
35
121
PC5 (1)
PJ1 (1)
O
TTL
UART module 4 transmit.
U5Rx
122
139
PJ2 (1)
PE4 (1)
I
TTL
UART module 5 receive.
1258
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Table 22-3. Signals by Signal Name (continued)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
U5Tx
123
140
PJ3 (1)
PE5 (1)
O
TTL
UART module 5 transmit.
U6Rx
127
141
PJ4 (1)
PD4 (1)
I
TTL
UART module 6 receive.
U6Tx
128
142
PJ5 (1)
PD5 (1)
O
TTL
UART module 6 transmit.
U7Rx
15
112
PE0 (1)
PK4 (1)
I
TTL
UART module 7 receive.
U7Tx
14
111
PE1 (1)
PK5 (1)
O
TTL
UART module 7 transmit.
VBAT
77
fixed
-
Power
Power source for the Hibernation module. It is
normally connected to the positive terminal of a
battery and serves as the battery
backup/Hibernation module power-source supply.
VDD
5
24
29
43
56
66
78
94
101
113
124
137
fixed
-
Power
Positive supply for I/O and some logic.
VDDA
7
fixed
-
Power
The positive supply for the analog circuits (ADC,
Analog Comparators, etc.). These are separated
from VDD to minimize the electrical noise contained
on VDD from affecting the analog functions. VDDA
pins must be supplied with a voltage that meets the
specification in Table 23-5 on page 1284, regardless
of system implementation.
VDDC
49
126
fixed
-
Power
Positive supply for most of the logic function,
including the processor core and most peripherals.
The voltage on this pin is 1.2 V and is supplied by
the on-chip LDO. The VDDC pins should only be
connected to each other and an external capacitor
as specified in Table 23-12 on page 1297 .
VREFA+
8
fixed
-
Analog
A reference voltage used to specify the voltage at
which the ADC converts to a maximum value. This
pin is used in conjunction with VREFA-, which
specifies the minimum value . The voltage that is
applied to VREFA+ is the voltage with which an
AINn signal is converted to 4095. The VREFA+
voltage is limited to the range specified in Table
23-32 on page 1314 .
June 12, 2014
1259
Texas Instruments-Production Data
Signal Tables
Table 22-3. Signals by Signal Name (continued)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
VREFA-
9
fixed
-
Analog
A reference voltage used to specify the input
voltage at which the ADC converts to a minimum
value. This pin is used in conjunction with VREFA+,
which specifies the maximum value. In other words,
the voltage that is applied to VREFA- is the voltage
with which an AINn signal is converted to 0, while
the voltage that is applied to VREFA+ is the voltage
with which an AINn signal is converted to 4095.
The VREFA- voltage is limited to the range specified
in Table 23-32 on page 1314 .
WAKE
72
fixed
I
TTL
An external input that brings the processor out of
Hibernate mode when asserted.
WT0CCP0
36
51
83
108
PC4 (7)
PG4 (7)
PM6 (7)
PL0 (8)
I/O
TTL
32/64-Bit Wide Timer 0 Capture/Compare/PWM 0.
WT0CCP1
35
50
82
107
PC5 (7)
PG5 (7)
PM7 (7)
PL1 (8)
I/O
TTL
32/64-Bit Wide Timer 0 Capture/Compare/PWM 1.
WT1CCP0
34
48
106
110
PC6 (7)
PG6 (7)
PL2 (8)
PK6 (7)
I/O
TTL
32/64-Bit Wide Timer 1 Capture/Compare/PWM 0.
WT1CCP1
33
47
105
109
PC7 (7)
PG7 (7)
PL3 (8)
PK7 (7)
I/O
TTL
32/64-Bit Wide Timer 1 Capture/Compare/PWM 1.
WT2CCP0
1
20
32
104
PD0 (7)
PN2 (7)
PH0 (7)
PL4 (8)
I/O
TTL
32/64-Bit Wide Timer 2 Capture/Compare/PWM 0.
WT2CCP1
2
31
103
119
PD1 (7)
PH1 (7)
PL5 (8)
PN3 (7)
I/O
TTL
32/64-Bit Wide Timer 2 Capture/Compare/PWM 1.
WT3CCP0
3
26
71
96
PD2 (7)
PH4 (7)
PN4 (7)
PL6 (8)
I/O
TTL
32/64-Bit Wide Timer 3 Capture/Compare/PWM 0.
WT3CCP1
4
23
70
95
PD3 (7)
PH5 (7)
PN5 (7)
PL7 (8)
I/O
TTL
32/64-Bit Wide Timer 3 Capture/Compare/PWM 1.
WT4CCP0
22
69
89
141
PH6 (7)
PN6 (7)
PM0 (8)
PD4 (7)
I/O
TTL
32/64-Bit Wide Timer 4 Capture/Compare/PWM 0.
WT4CCP1
21
68
88
142
PH7 (7)
PN7 (7)
PM1 (8)
PD5 (7)
I/O
TTL
32/64-Bit Wide Timer 4 Capture/Compare/PWM 1.
1260
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Table 22-3. Signals by Signal Name (continued)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
WT5CCP0
28
87
143
PH2 (7)
PM2 (8)
PD6 (7)
I/O
TTL
32/64-Bit Wide Timer 5 Capture/Compare/PWM 0.
WT5CCP1
27
86
144
PH3 (7)
PM3 (8)
PD7 (7)
I/O
TTL
32/64-Bit Wide Timer 5 Capture/Compare/PWM 1.
XOSC0
74
fixed
I
Analog
Hibernation module oscillator crystal input or an
external clock reference input. Note that this is
either a 32.768-kHz crystal or a 32.768-kHz
oscillator for the Hibernation module RTC.
XOSC1
76
fixed
O
Analog
Hibernation module oscillator crystal output. Leave
unconnected when using a single-ended clock
source.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
June 12, 2014
1261
Texas Instruments-Production Data
Signal Tables
22.3
Signals by Function, Except for GPIO
Table 22-4. Signals by Function, Except for GPIO
Function
ADC
Pin Name
a
Pin Number
Pin Type
Buffer Type
Description
AIN0
12
I
Analog
Analog-to-digital converter input 0.
AIN1
13
I
Analog
Analog-to-digital converter input 1.
AIN2
14
I
Analog
Analog-to-digital converter input 2.
AIN3
15
I
Analog
Analog-to-digital converter input 3.
AIN4
144
I
Analog
Analog-to-digital converter input 4.
AIN5
143
I
Analog
Analog-to-digital converter input 5.
AIN6
142
I
Analog
Analog-to-digital converter input 6.
AIN7
141
I
Analog
Analog-to-digital converter input 7.
AIN8
140
I
Analog
Analog-to-digital converter input 8.
AIN9
139
I
Analog
Analog-to-digital converter input 9.
AIN10
136
I
Analog
Analog-to-digital converter input 10.
AIN11
135
I
Analog
Analog-to-digital converter input 11.
AIN12
4
I
Analog
Analog-to-digital converter input 12.
AIN13
3
I
Analog
Analog-to-digital converter input 13.
AIN14
2
I
Analog
Analog-to-digital converter input 14.
AIN15
1
I
Analog
Analog-to-digital converter input 15.
AIN16
16
I
Analog
Analog-to-digital converter input 16.
AIN17
17
I
Analog
Analog-to-digital converter input 17.
AIN18
18
I
Analog
Analog-to-digital converter input 18.
AIN19
19
I
Analog
Analog-to-digital converter input 19.
AIN20
134
I
Analog
Analog-to-digital converter input 20.
AIN21
133
I
Analog
Analog-to-digital converter input 21.
AIN22
132
I
Analog
Analog-to-digital converter input 22.
AIN23
131
I
Analog
Analog-to-digital converter input 23.
VREFA+
8
-
Analog
A reference voltage used to specify the voltage at
which the ADC converts to a maximum value. This
pin is used in conjunction with VREFA-, which
specifies the minimum value . The voltage that is
applied to VREFA+ is the voltage with which an
AINn signal is converted to 4095. The VREFA+
voltage is limited to the range specified in Table
23-32 on page 1314 .
VREFA-
9
-
Analog
A reference voltage used to specify the input
voltage at which the ADC converts to a minimum
value. This pin is used in conjunction with VREFA+,
which specifies the maximum value. In other words,
the voltage that is applied to VREFA- is the voltage
with which an AINn signal is converted to 0, while
the voltage that is applied to VREFA+ is the voltage
with which an AINn signal is converted to 4095.
The VREFA- voltage is limited to the range specified
in Table 23-32 on page 1314 .
1262
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Table 22-4. Signals by Function, Except for GPIO (continued)
Function
Analog Comparators
Pin Name
Pin Type
Buffer Type
C0+
34
I
Analog
Analog comparator 0 positive input.
C0-
33
I
Analog
Analog comparator 0 negative input.
C0o
62
112
O
TTL
C1+
35
I
Analog
Analog comparator 1 positive input.
C1-
36
I
Analog
Analog comparator 1 negative input.
C1o
63
111
O
TTL
C2+
127
I
Analog
Analog comparator 2 positive input.
C2-
128
I
Analog
Analog comparator 2 negative input.
C2o
64
110
O
TTL
Analog comparator 2 output.
CAN0Rx
62
81
136
139
I
TTL
CAN module 0 receive.
CAN0Tx
65
80
135
140
O
TTL
CAN module 0 transmit.
CAN1Rx
37
133
I
TTL
CAN module 1 receive.
CAN1Tx
38
134
O
TTL
CAN module 1 transmit.
TRCLK
65
O
TTL
Trace clock.
TRD0
64
O
TTL
Trace data 0.
TRD1
63
O
TTL
Trace data 1.
TRD2
62
O
TTL
Trace data 2.
TRD3
61
O
TTL
Trace data 3.
Controller Area
Network
Core
a
Pin Number
Description
Analog comparator 0 output.
Analog comparator 1 output.
June 12, 2014
1263
Texas Instruments-Production Data
Signal Tables
Table 22-4. Signals by Function, Except for GPIO (continued)
Function
Pin Name
a
Pin Number
Pin Type
Buffer Type
T0CCP0
62
108
I/O
TTL
16/32-Bit Timer 0 Capture/Compare/PWM 0.
T0CCP1
63
107
I/O
TTL
16/32-Bit Timer 0 Capture/Compare/PWM 1.
T1CCP0
64
106
120
136
I/O
TTL
16/32-Bit Timer 1 Capture/Compare/PWM 0.
T1CCP1
65
105
121
135
I/O
TTL
16/32-Bit Timer 1 Capture/Compare/PWM 1.
T2CCP0
61
97
104
122
I/O
TTL
16/32-Bit Timer 2 Capture/Compare/PWM 0.
T2CCP1
60
98
103
123
I/O
TTL
16/32-Bit Timer 2 Capture/Compare/PWM 1.
T3CCP0
59
96
99
127
I/O
TTL
16/32-Bit Timer 3 Capture/Compare/PWM 0.
T3CCP1
58
95
100
128
I/O
TTL
16/32-Bit Timer 3 Capture/Compare/PWM 1.
T4CCP0
55
89
118
131
I/O
TTL
16/32-Bit Timer 4 Capture/Compare/PWM 0.
T4CCP1
54
88
117
132
I/O
TTL
16/32-Bit Timer 4 Capture/Compare/PWM 1.
T5CCP0
11
53
87
116
I/O
TTL
16/32-Bit Timer 5 Capture/Compare/PWM 0.
T5CCP1
52
86
115
I/O
TTL
16/32-Bit Timer 5 Capture/Compare/PWM 1.
WT0CCP0
36
51
83
108
I/O
TTL
32/64-Bit Wide Timer 0 Capture/Compare/PWM 0.
WT0CCP1
35
50
82
107
I/O
TTL
32/64-Bit Wide Timer 0 Capture/Compare/PWM 1.
I/O
TTL
32/64-Bit Wide Timer 1 Capture/Compare/PWM 0.
General-Purpose
Timers
WT1CCP0
Description
1264
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Table 22-4. Signals by Function, Except for GPIO (continued)
Function
Pin Name
Pin Number
a
Pin Type
Buffer Type
Description
34
48
106
110
WT1CCP1
33
47
105
109
I/O
TTL
32/64-Bit Wide Timer 1 Capture/Compare/PWM 1.
WT2CCP0
1
20
32
104
I/O
TTL
32/64-Bit Wide Timer 2 Capture/Compare/PWM 0.
WT2CCP1
2
31
103
119
I/O
TTL
32/64-Bit Wide Timer 2 Capture/Compare/PWM 1.
WT3CCP0
3
26
71
96
I/O
TTL
32/64-Bit Wide Timer 3 Capture/Compare/PWM 0.
WT3CCP1
4
23
70
95
I/O
TTL
32/64-Bit Wide Timer 3 Capture/Compare/PWM 1.
WT4CCP0
22
69
89
141
I/O
TTL
32/64-Bit Wide Timer 4 Capture/Compare/PWM 0.
WT4CCP1
21
68
88
142
I/O
TTL
32/64-Bit Wide Timer 4 Capture/Compare/PWM 1.
WT5CCP0
28
87
143
I/O
TTL
32/64-Bit Wide Timer 5 Capture/Compare/PWM 0.
WT5CCP1
27
86
144
I/O
TTL
32/64-Bit Wide Timer 5 Capture/Compare/PWM 1.
June 12, 2014
1265
Texas Instruments-Production Data
Signal Tables
Table 22-4. Signals by Function, Except for GPIO (continued)
Function
Pin Name
a
Pin Number
Pin Type
Buffer Type
Description
GNDX
75
-
Power
GND for the Hibernation oscillator. When using a
crystal clock source, this pin should be connected
to digital ground along with the crystal load
capacitors. When using an external oscillator, this
pin should be connected to digital ground.
HIB
73
O
TTL
An output that indicates the processor is in
Hibernate mode.
RTCCLK
112
O
TTL
Buffered version of the Hibernation module's
32.768-kHz clock. This signal is not output when
the part is in Hibernate mode.
VBAT
77
-
Power
Power source for the Hibernation module. It is
normally connected to the positive terminal of a
battery and serves as the battery
backup/Hibernation module power-source supply.
WAKE
72
I
TTL
An external input that brings the processor out of
Hibernate mode when asserted.
XOSC0
74
I
Analog
Hibernation module oscillator crystal input or an
external clock reference input. Note that this is
either a 32.768-kHz crystal or a 32.768-kHz
oscillator for the Hibernation module RTC.
XOSC1
76
O
Analog
Hibernation module oscillator crystal output. Leave
unconnected when using a single-ended clock
source.
I2C0SCL
99
I/O
OD
I2C module 0 clock. Note that this signal has an
active pull-up. The corresponding port pin should
not be configured as open drain.
I2C0SDA
100
I/O
OD
I2C module 0 data.
I2C1SCL
45
51
I/O
OD
I2C module 1 clock. Note that this signal has an
active pull-up. The corresponding port pin should
not be configured as open drain.
I2C1SDA
46
50
I/O
OD
I2C module 1 data.
I2C2SCL
59
139
I/O
OD
I2C module 2 clock. Note that this signal has an
active pull-up. The corresponding port pin should
not be configured as open drain.
I2C2SDA
58
140
I/O
OD
I2C module 2 data.
I2C3SCL
1
55
I/O
OD
I2C module 3 clock. Note that this signal has an
active pull-up. The corresponding port pin should
not be configured as open drain.
I2C3SDA
2
54
I/O
OD
I2C module 3 data.
I2C4SCL
53
I/O
OD
I2C module 4 clock. Note that this signal has an
active pull-up. The corresponding port pin should
not be configured as open drain.
I2C4SDA
52
I/O
OD
I2C module 4 data.
I2C5SCL
48
I/O
OD
I2C module 5 clock. Note that this signal has an
active pull-up. The corresponding port pin should
not be configured as open drain.
I2C5SDA
47
I/O
OD
I2C module 5 data.
Hibernate
I2C
1266
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Table 22-4. Signals by Function, Except for GPIO (continued)
Function
JTAG/SWD/SWO
Pin Name
Pin Number
a
Pin Type
Buffer Type
Description
SWCLK
118
I
TTL
JTAG/SWD CLK.
SWDIO
117
I/O
TTL
JTAG TMS and SWDIO.
SWO
115
O
TTL
JTAG TDO and SWO.
TCK
118
I
TTL
JTAG/SWD CLK.
TDI
116
I
TTL
JTAG TDI.
TDO
115
O
TTL
JTAG TDO and SWO.
TMS
117
I
TTL
JTAG TMS and SWDIO.
June 12, 2014
1267
Texas Instruments-Production Data
Signal Tables
Table 22-4. Signals by Function, Except for GPIO (continued)
Function
PWM
Pin Name
a
Pin Number
Pin Type
Buffer Type
Description
M0FAULT0
3
32
64
112
143
I
TTL
Motion Control Module 0 PWM Fault 0.
M0FAULT1
31
53
65
111
144
I
TTL
Motion Control Module 0 PWM Fault 1.
M0FAULT2
28
52
61
110
I
TTL
Motion Control Module 0 PWM Fault 2.
M0FAULT3
27
60
109
I
TTL
Motion Control Module 0 PWM Fault 3.
M0PWM0
32
131
O
TTL
Motion Control Module 0 PWM 0. This signal is
controlled by Module 0 PWM Generator 0.
M0PWM1
31
132
O
TTL
Motion Control Module 0 PWM 1. This signal is
controlled by Module 0 PWM Generator 0.
M0PWM2
11
28
136
O
TTL
Motion Control Module 0 PWM 2. This signal is
controlled by Module 0 PWM Generator 1.
M0PWM3
27
135
O
TTL
Motion Control Module 0 PWM 3. This signal is
controlled by Module 0 PWM Generator 1.
M0PWM4
26
51
83
139
O
TTL
Motion Control Module 0 PWM 4. This signal is
controlled by Module 0 PWM Generator 2.
M0PWM5
23
50
82
140
O
TTL
Motion Control Module 0 PWM 5. This signal is
controlled by Module 0 PWM Generator 2.
M0PWM6
1
20
22
36
48
O
TTL
Motion Control Module 0 PWM 6. This signal is
controlled by Module 0 PWM Generator 3.
M0PWM7
2
21
35
47
119
O
TTL
Motion Control Module 0 PWM 7. This signal is
controlled by Module 0 PWM Generator 3.
M1FAULT0
16
58
61
I
TTL
Motion Control Module 1 PWM Fault 0.
M1FAULT1
17
55
I
TTL
Motion Control Module 1 PWM Fault 1.
M1FAULT2
18
54
I
TTL
Motion Control Module 1 PWM Fault 2.
M1FAULT3
19
I
TTL
Motion Control Module 1 PWM Fault 3.
1268
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Table 22-4. Signals by Function, Except for GPIO (continued)
Function
Pin Name
a
Pin Number
Pin Type
Buffer Type
Description
M1PWM0
1
53
O
TTL
Motion Control Module 1 PWM 0. This signal is
controlled by Module 1 PWM Generator 0.
M1PWM1
2
52
O
TTL
Motion Control Module 1 PWM 1. This signal is
controlled by Module 1 PWM Generator 0.
M1PWM2
45
51
139
O
TTL
Motion Control Module 1 PWM 2. This signal is
controlled by Module 1 PWM Generator 1.
M1PWM3
46
50
140
O
TTL
Motion Control Module 1 PWM 3. This signal is
controlled by Module 1 PWM Generator 1.
M1PWM4
62
71
O
TTL
Motion Control Module 1 PWM 4. This signal is
controlled by Module 1 PWM Generator 2.
M1PWM5
63
70
O
TTL
Motion Control Module 1 PWM 5. This signal is
controlled by Module 1 PWM Generator 2.
M1PWM6
64
69
O
TTL
Motion Control Module 1 PWM 6. This signal is
controlled by Module 1 PWM Generator 3.
M1PWM7
65
68
O
TTL
Motion Control Module 1 PWM 7. This signal is
controlled by Module 1 PWM Generator 3.
June 12, 2014
1269
Texas Instruments-Production Data
Signal Tables
Table 22-4. Signals by Function, Except for GPIO (continued)
Function
Pin Name
a
Pin Number
Pin Type
Buffer Type
GND
6
25
30
44
57
67
79
91
102
114
125
138
-
Power
Ground reference for logic and I/O pins.
GNDA
10
-
Power
The ground reference for the analog circuits (ADC,
Analog Comparators, etc.). These are separated
from GND to minimize the electrical noise contained
on VDD from affecting the analog functions.
VDD
5
24
29
43
56
66
78
94
101
113
124
137
-
Power
Positive supply for I/O and some logic.
VDDA
7
-
Power
The positive supply for the analog circuits (ADC,
Analog Comparators, etc.). These are separated
from VDD to minimize the electrical noise contained
on VDD from affecting the analog functions. VDDA
pins must be supplied with a voltage that meets the
specification in Table 23-5 on page 1284, regardless
of system implementation.
VDDC
49
126
-
Power
Positive supply for most of the logic function,
including the processor core and most peripherals.
The voltage on this pin is 1.2 V and is supplied by
the on-chip LDO. The VDDC pins should only be
connected to each other and an external capacitor
as specified in Table 23-12 on page 1297 .
Power
Description
1270
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Table 22-4. Signals by Function, Except for GPIO (continued)
Function
Pin Name
Pin Type
Buffer Type
IDX0
4
31
61
122
I
TTL
QEI module 0 index.
IDX1
36
47
50
I
TTL
QEI module 1 index.
PhA0
26
62
143
I
TTL
QEI module 0 phase A.
PhA1
35
52
55
I
TTL
QEI module 1 phase A.
PhB0
23
63
144
I
TTL
QEI module 0 phase B.
PhB1
34
51
54
I
TTL
QEI module 1 phase B.
SSI0Clk
39
I/O
TTL
SSI module 0 clock
SSI0Fss
40
I/O
TTL
SSI module 0 frame signal
SSI0Rx
41
I
TTL
SSI module 0 receive
SSI0Tx
42
O
TTL
SSI module 0 transmit
SSI1Clk
1
64
I/O
TTL
SSI module 1 clock.
SSI1Fss
2
65
I/O
TTL
SSI module 1 frame signal.
SSI1Rx
3
62
I
TTL
SSI module 1 receive.
SSI1Tx
4
63
O
TTL
SSI module 1 transmit.
SSI2Clk
26
136
I/O
TTL
SSI module 2 clock.
SSI2Fss
23
135
I/O
TTL
SSI module 2 frame signal.
SSI2Rx
22
I
TTL
SSI module 2 receive.
SSI2Tx
21
O
TTL
SSI module 2 transmit.
SSI3Clk
1
16
32
I/O
TTL
SSI module 3 clock.
SSI3Fss
2
17
31
I/O
TTL
SSI module 3 frame signal.
SSI3Rx
3
18
28
I
TTL
SSI module 3 receive.
SSI3Tx
4
19
27
O
TTL
SSI module 3 transmit.
QEI
SSI
a
Pin Number
Description
June 12, 2014
1271
Texas Instruments-Production Data
Signal Tables
Table 22-4. Signals by Function, Except for GPIO (continued)
Function
Pin Name
a
Pin Number
Pin Type
Buffer Type
NMI
62
144
I
TTL
OSC0
92
I
Analog
Main oscillator crystal input or an external clock
reference input.
OSC1
93
O
Analog
Main oscillator crystal output. Leave unconnected
when using a single-ended clock source.
RST
90
I
TTL
System reset input.
U0Rx
37
I
TTL
UART module 0 receive.
U0Tx
38
O
TTL
UART module 0 transmit.
U1CTS
35
63
I
TTL
UART module 1 Clear To Send modem flow control
input signal.
U1DCD
64
I
TTL
UART module 1 Data Carrier Detect modem status
input signal.
U1DSR
65
I
TTL
UART module 1 Data Set Ready modem output
control line.
U1DTR
61
O
TTL
UART module 1 Data Terminal Ready modem
status input signal.
U1RI
134
I
TTL
UART module 1 Ring Indicator modem status input
signal.
U1RTS
36
62
O
TTL
UART module 1 Request to Send modem flow
control output line.
U1Rx
36
97
I
TTL
UART module 1 receive.
U1Tx
35
98
O
TTL
UART module 1 transmit.
U2Rx
51
143
I
TTL
UART module 2 receive.
U2Tx
50
144
O
TTL
UART module 2 transmit.
U3Rx
34
I
TTL
UART module 3 receive.
U3Tx
33
O
TTL
UART module 3 transmit.
U4Rx
36
120
I
TTL
UART module 4 receive.
U4Tx
35
121
O
TTL
UART module 4 transmit.
U5Rx
122
139
I
TTL
UART module 5 receive.
U5Tx
123
140
O
TTL
UART module 5 transmit.
U6Rx
127
141
I
TTL
UART module 6 receive.
U6Tx
128
142
O
TTL
UART module 6 transmit.
U7Rx
15
112
I
TTL
UART module 7 receive.
U7Tx
14
111
O
TTL
UART module 7 transmit.
System Control &
Clocks
UART
Description
Non-maskable interrupt.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
1272
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
22.4
GPIO Pins and Alternate Functions
Table 22-5. GPIO Pins and Alternate Functions
IO
Pin
Analog
Function
a
Digital Function (GPIOPCTL PMCx Bit Field Encoding)
1
2
3
4
5
6
7
8
9
14
15
PA0
37
-
U0Rx
-
-
-
-
-
-
CAN1Rx
-
-
-
PA1
38
-
U0Tx
-
-
-
-
-
-
CAN1Tx
-
-
-
PA2
39
-
-
SSI0Clk
-
-
-
-
-
-
-
-
-
PA3
40
-
-
SSI0Fss
-
-
-
-
-
-
-
-
-
PA4
41
-
-
SSI0Rx
-
-
-
-
-
-
-
-
-
PA5
42
-
-
SSI0Tx
-
-
-
-
-
-
-
-
-
PA6
45
-
-
-
I2C1SCL
-
M1PWM2
-
-
-
-
-
-
PA7
46
-
-
-
I2C1SDA
-
M1PWM3
-
-
-
-
-
-
PB0
97
-
U1Rx
-
-
-
-
-
T2CCP0
-
-
-
-
PB1
98
-
U1Tx
-
-
-
-
-
T2CCP1
-
-
-
-
PB2
99
-
-
-
I2C0SCL
-
-
-
T3CCP0
-
-
-
-
PB3
100
-
-
-
I2C0SDA
-
-
-
T3CCP1
-
-
-
-
PB4
136
AIN10
-
SSI2Clk
-
M0PWM2
-
-
T1CCP0 CAN0Rx
-
-
-
PB5
135
AIN11
-
SSI2Fss
-
M0PWM3
-
-
T1CCP1 CAN0Tx
-
-
-
PC0
118
-
TCK
SWCLK
-
-
-
-
-
T4CCP0
-
-
-
-
PC1
117
-
TMS
SWDIO
-
-
-
-
-
T4CCP1
-
-
-
-
PC2
116
-
TDI
-
-
-
-
-
T5CCP0
-
-
-
-
PC3
115
-
TDO
SWO
-
-
-
-
-
T5CCP1
-
-
-
-
PC4
36
C1-
U4Rx
U1Rx
-
M0PWM6
-
IDX1
WT0CCP0 U1RTS
-
-
-
PC5
35
C1+
U4Tx
U1Tx
-
M0PWM7
-
PhA1
WT0CCP1 U1CTS
-
-
-
PC6
34
C0+
U3Rx
-
-
-
-
PhB1
WT1CCP0
-
-
-
-
PC7
33
C0-
U3Tx
-
-
-
-
-
WT1CCP1
-
-
-
-
PD0
1
AIN15
SSI3Clk SSI1Clk I2C3SCL M0PWM6 M1PWM0
-
WT2CCP0
-
-
-
-
PD1
2
AIN14
SSI3Fss SSI1Fss I2C3SDA M0PWM7 M1PWM1
-
WT2CCP1
-
-
-
-
PD2
3
AIN13
SSI3Rx SSI1Rx
-
M0FAULT0
-
-
WT3CCP0
-
-
-
-
PD3
4
AIN12
SSI3Tx SSI1Tx
-
-
-
IDX0
WT3CCP1
-
-
-
-
PD4
141
AIN7
-
-
-
-
WT4CCP0
-
-
-
-
U6Rx
-
PD5
142
AIN6
U6Tx
-
-
-
-
-
WT4CCP1
-
-
-
-
PD6
143
AIN5
U2Rx
-
-
M0FAULT0
-
PhA0
WT5CCP0
-
-
-
-
PD7
144
AIN4
U2Tx
-
-
M0FAULT1
-
PhB0
WT5CCP1
NMI
-
-
-
PE0
15
AIN3
U7Rx
-
-
-
-
-
-
-
-
-
-
PE1
14
AIN2
U7Tx
-
-
-
-
-
-
-
-
-
-
PE2
13
AIN1
-
-
-
-
-
-
-
-
-
-
-
PE3
12
AIN0
-
-
-
-
-
-
-
-
-
-
-
PE4
139
AIN9
U5Rx
-
I2C2SCL M0PWM4 M1PWM2
-
-
CAN0Rx
-
-
-
PE5
140
AIN8
U5Tx
-
I2C2SDA M0PWM5 M1PWM3
-
-
CAN0Tx
-
-
-
June 12, 2014
1273
Texas Instruments-Production Data
Signal Tables
Table 22-5. GPIO Pins and Alternate Functions (continued)
a
Digital Function (GPIOPCTL PMCx Bit Field Encoding)
IO
Pin
Analog
Function
1
2
3
4
5
6
7
8
9
14
15
PE6
133
AIN21
-
-
-
-
-
-
-
CAN1Rx
-
-
-
PE7
134
AIN20
U1RI
-
-
-
-
-
-
CAN1Tx
-
-
-
-
M1PWM4
PhA0
T0CCP0
NMI
C0o
TRD2
-
-
M1PWM5
PhB0
T0CCP1
-
C1o
TRD1
-
PF0
62
-
U1RTS
SSI1Rx CAN0Rx
PF1
63
-
U1CTS
SSI1Tx
-
PF2
64
-
U1DCD
SSI1Clk
-
M0FAULT0 M1PWM6
-
T1CCP0
-
C2o
TRD0
-
PF3
65
-
U1DSR
SSI1Fss CAN0Tx M0FAULT1 M1PWM7
-
T1CCP1
-
-
TRCLK
-
PF4
61
-
U1DTR
IDX0
T2CCP0
-
-
TRD3
-
PF5
60
-
-
PF6
59
-
-
PF7
58
-
-
PG0
55
-
-
PG1
54
-
PG2
53
PG3
52
PG4
PG5
-
-
M0FAULT2 M1FAULT0
-
-
M0FAULT3
-
-
T2CCP1
-
-
-
-
-
I2C2SCL
-
-
-
T3CCP0
-
-
-
-
-
I2C2SDA
-
M1FAULT0
-
T3CCP1
-
-
-
-
-
I2C3SCL
-
M1FAULT1
PhA1
T4CCP0
-
-
-
-
-
-
I2C3SDA
-
M1FAULT2
PhB1
T4CCP1
-
-
-
-
-
-
-
I2C4SCL M0FAULT1 M1PWM0
-
T5CCP0
-
-
-
-
-
-
-
I2C4SDA M0FAULT2 M1PWM1
PhA1
T5CCP1
-
-
-
-
51
-
U2Rx
-
I2C1SCL M0PWM4 M1PWM2
PhB1
WT0CCP0
-
-
-
-
50
-
U2Tx
-
I2C1SDA M0PWM5 M1PWM3
IDX1
WT0CCP1
-
-
-
-
PG6
48
-
-
-
I2C5SCL M0PWM6
-
-
WT1CCP0
-
-
-
-
PG7
47
-
-
-
I2C5SDA M0PWM7
IDX1
-
WT1CCP1
-
-
-
-
PH0
32
-
-
SSI3Clk
-
M0PWM0
-
M0FAULT0 WT2CCP0
-
-
-
-
PH1
31
-
-
SSI3Fss
-
M0PWM1
IDX0
M0FAULT1 WT2CCP1
-
-
-
-
PH2
28
-
-
SSI3Rx
-
M0PWM2
-
M0FAULT2 WT5CCP0
-
-
-
-
PH3
27
-
-
SSI3Tx
-
M0PWM3
-
M0FAULT3 WT5CCP1
-
-
-
-
PH4
26
-
-
SSI2Clk
-
M0PWM4
PhA0
-
WT3CCP0
-
-
-
-
PH5
23
-
-
SSI2Fss
-
M0PWM5
PhB0
-
WT3CCP1
-
-
-
-
PH6
22
-
-
SSI2Rx
-
M0PWM6
-
-
WT4CCP0
-
-
-
-
PH7
21
-
-
SSI2Tx
-
M0PWM7
-
-
WT4CCP1
-
-
-
-
PJ0
120
-
U4Rx
-
-
-
-
-
T1CCP0
-
-
-
-
PJ1
121
-
U4Tx
-
-
-
-
-
T1CCP1
-
-
-
-
PJ2
122
-
U5Rx
-
-
-
IDX0
-
T2CCP0
-
-
-
-
PJ3
123
-
U5Tx
-
-
-
-
-
T2CCP1
-
-
-
-
PJ4
127
C2+
U6Rx
-
-
-
-
-
T3CCP0
-
-
-
-
PJ5
128
C2-
U6Tx
-
-
-
-
-
T3CCP1
-
-
-
-
PJ6
129
-
-
-
-
-
-
-
-
-
-
-
-
PJ7
130
-
-
-
-
-
-
-
-
-
-
-
-
PK0
16
AIN16
-
SSI3Clk
-
-
-
M1FAULT0
-
-
-
-
-
PK1
17
AIN17
-
SSI3Fss
-
-
-
M1FAULT1
-
-
-
-
-
PK2
18
AIN18
-
SSI3Rx
-
-
-
M1FAULT2
-
-
-
-
-
PK3
19
AIN19
-
SSI3Tx
-
-
-
M1FAULT3
-
PK4
112
-
U7Rx
-
-
-
-
M0FAULT0 RTCCLK
PK5
111
-
U7Tx
-
-
-
-
M0FAULT1
1274
-
-
-
-
-
C0o
-
-
-
C1o
-
-
-
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Table 22-5. GPIO Pins and Alternate Functions (continued)
a
Digital Function (GPIOPCTL PMCx Bit Field Encoding)
IO
Pin
Analog
Function
1
2
3
4
5
8
9
14
15
PK6
110
-
-
-
-
-
-
M0FAULT2 WT1CCP0
C2o
-
-
-
PK7
109
-
-
-
-
-
-
M0FAULT3 WT1CCP1
-
-
-
-
PL0
108
-
-
-
-
-
-
-
T0CCP0 WT0CCP0
-
-
-
PL1
107
-
-
-
-
-
-
-
T0CCP1 WT0CCP1
-
-
-
PL2
106
-
-
-
-
-
-
-
T1CCP0 WT1CCP0
-
-
-
PL3
105
-
-
-
-
-
-
-
T1CCP1 WT1CCP1
-
-
-
PL4
104
-
-
-
-
-
-
-
T2CCP0 WT2CCP0
-
-
-
PL5
103
-
-
-
-
-
-
-
T2CCP1 WT2CCP1
-
-
-
PL6
96
-
-
-
-
-
-
-
T3CCP0 WT3CCP0
-
-
-
PL7
95
-
-
-
-
-
-
-
T3CCP1 WT3CCP1
-
-
-
PM0
89
-
-
-
-
-
-
-
T4CCP0 WT4CCP0
-
-
-
PM1
88
-
-
-
-
-
-
-
T4CCP1 WT4CCP1
-
-
-
PM2
87
-
-
-
-
-
-
-
T5CCP0 WT5CCP0
-
-
-
PM3
86
-
-
-
-
-
-
-
T5CCP1 WT5CCP1
-
-
-
PM4
85
-
-
-
-
-
-
-
-
-
-
-
-
PM5
84
-
-
-
-
-
-
-
-
-
-
-
-
PM6
83
-
-
M0PWM4
-
-
-
-
WT0CCP0
-
-
-
-
6
7
PM7
82
-
-
M0PWM5
-
-
-
-
WT0CCP1
-
-
-
-
PN0
81
-
CAN0Rx
-
-
-
-
-
-
-
-
-
-
PN1
80
-
CAN0Tx
-
-
-
-
-
-
-
-
-
-
PN2
20
-
-
M0PWM6
-
-
-
-
WT2CCP0
-
-
-
-
PN3
119
-
-
M0PWM7
-
-
-
-
WT2CCP1
-
-
-
-
PN4
71
-
-
M1PWM4
-
-
-
-
WT3CCP0
-
-
-
-
PN5
70
-
-
M1PWM5
-
-
-
-
WT3CCP1
-
-
-
-
PN6
69
-
-
M1PWM6
-
-
-
-
WT4CCP0
-
-
-
-
PN7
68
-
-
M1PWM7
-
-
-
-
WT4CCP1
-
-
-
-
PP0
131
AIN23
M0PWM0
-
-
-
-
-
T4CCP0
-
-
-
-
PP1
132
AIN22
M0PWM1
-
-
-
-
-
T4CCP1
-
-
-
-
PP2
11
-
M0PWM2
-
-
-
-
-
T5CCP0
-
-
-
-
a. The digital signals that are shaded gray are the power-on default values for the corresponding GPIO pin. Encodings 10-13 are not used
on this device.
June 12, 2014
1275
Texas Instruments-Production Data
Signal Tables
22.5
Possible Pin Assignments for Alternate Functions
Table 22-6. Possible Pin Assignments for Alternate Functions
# of Possible Assignments
one
Alternate Function
GPIO Function
AIN0
PE3
AIN1
PE2
AIN10
PB4
AIN11
PB5
AIN12
PD3
AIN13
PD2
AIN14
PD1
AIN15
PD0
AIN16
PK0
AIN17
PK1
AIN18
PK2
AIN19
PK3
AIN2
PE1
AIN20
PE7
AIN21
PE6
AIN22
PP1
AIN23
PP0
AIN3
PE0
AIN4
PD7
AIN5
PD6
AIN6
PD5
AIN7
PD4
AIN8
PE5
AIN9
PE4
C0+
PC6
C0-
PC7
C1+
PC5
C1-
PC4
C2+
PJ4
C2-
PJ5
I2C0SCL
PB2
I2C0SDA
PB3
I2C4SCL
PG2
I2C4SDA
PG3
I2C5SCL
PG6
I2C5SDA
PG7
M1FAULT3
PK3
RTCCLK
PK4
SSI0Clk
PA2
1276
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Table 22-6. Possible Pin Assignments for Alternate Functions (continued)
# of Possible Assignments
Alternate Function
GPIO Function
SSI0Fss
PA3
SSI0Rx
PA4
SSI0Tx
PA5
SSI2Rx
PH6
SSI2Tx
PH7
SWCLK
PC0
SWDIO
PC1
SWO
PC3
TCK
PC0
TDI
PC2
TDO
PC3
TMS
PC1
TRCLK
PF3
TRD0
PF2
TRD1
PF1
TRD2
PF0
TRD3
PF4
U0Rx
PA0
U0Tx
PA1
U1DCD
PF2
U1DSR
PF3
U1DTR
PF4
U1RI
PE7
U3Rx
PC6
U3Tx
PC7
June 12, 2014
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Texas Instruments-Production Data
Signal Tables
Table 22-6. Possible Pin Assignments for Alternate Functions (continued)
# of Possible Assignments
two
Alternate Function
GPIO Function
C0o
PF0 PK4
C1o
PF1 PK5
C2o
PF2 PK6
CAN1Rx
PA0 PE6
CAN1Tx
PA1 PE7
I2C1SCL
PA6 PG4
I2C1SDA
PA7 PG5
I2C2SCL
PE4 PF6
I2C2SDA
PE5 PF7
I2C3SCL
PD0 PG0
I2C3SDA
PD1 PG1
M0PWM0
PH0 PP0
M0PWM1
PH1 PP1
M0PWM3
PB5 PH3
M1FAULT1
PG0 PK1
M1FAULT2
PG1 PK2
M1PWM0
PD0 PG2
M1PWM1
PD1 PG3
M1PWM4
PF0 PN4
M1PWM5
PF1 PN5
M1PWM6
PF2 PN6
M1PWM7
PF3 PN7
NMI
PD7 PF0
SSI1Clk
PD0 PF2
SSI1Fss
PD1 PF3
SSI1Rx
PD2 PF0
SSI1Tx
PD3 PF1
SSI2Clk
PB4 PH4
SSI2Fss
PB5 PH5
T0CCP0
PF0 PL0
T0CCP1
PF1 PL1
U1CTS
PC5 PF1
U1RTS
PC4 PF0
U1Rx
PB0 PC4
U1Tx
PB1 PC5
U2Rx
PD6 PG4
U2Tx
PD7 PG5
U4Rx
PC4 PJ0
U4Tx
PC5 PJ1
U5Rx
PE4 PJ2
U5Tx
PE5 PJ3
1278
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Table 22-6. Possible Pin Assignments for Alternate Functions (continued)
# of Possible Assignments
three
Alternate Function
GPIO Function
U6Rx
PD4 PJ4
U6Tx
PD5 PJ5
U7Rx
PE0 PK4
U7Tx
PE1 PK5
IDX1
PC4 PG5 PG7
M0FAULT3
PF5 PH3 PK7
M0PWM2
PB4 PH2 PP2
M1FAULT0
PF4 PF7 PK0
M1PWM2
PA6 PE4 PG4
M1PWM3
PA7 PE5 PG5
PhA0
PD6 PF0 PH4
PhA1
PC5 PG0 PG3
PhB0
PD7 PF1 PH5
PhB1
PC6 PG1 PG4
SSI3Clk
PD0 PH0 PK0
SSI3Fss
PD1 PH1 PK1
SSI3Rx
PD2 PH2 PK2
SSI3Tx
PD3 PH3 PK3
T5CCP1
PC3 PG3 PM3
WT5CCP0
PD6 PH2 PM2
WT5CCP1
PD7 PH3 PM3
June 12, 2014
1279
Texas Instruments-Production Data
Signal Tables
Table 22-6. Possible Pin Assignments for Alternate Functions (continued)
# of Possible Assignments
four
Alternate Function
GPIO Function
CAN0Rx
PB4 PE4 PF0 PN0
CAN0Tx
PB5 PE5 PF3 PN1
IDX0
PD3 PF4 PH1 PJ2
M0FAULT2
PF4 PG3 PH2 PK6
M0PWM4
PE4 PG4 PH4 PM6
M0PWM5
PE5 PG5 PH5 PM7
T1CCP0
PB4 PF2 PJ0 PL2
T1CCP1
PB5 PF3 PJ1 PL3
T2CCP0
PB0 PF4 PJ2 PL4
T2CCP1
PB1 PF5 PJ3 PL5
T3CCP0
PB2 PF6 PJ4 PL6
T3CCP1
PB3 PF7 PJ5 PL7
T4CCP0
PC0 PG0 PM0 PP0
T4CCP1
PC1 PG1 PM1 PP1
T5CCP0
PC2 PG2 PM2 PP2
WT0CCP0
PC4 PG4 PL0 PM6
WT0CCP1
PC5 PG5 PL1 PM7
WT1CCP0
PC6 PG6 PK6 PL2
WT1CCP1
PC7 PG7 PK7 PL3
WT2CCP0
PD0 PH0 PL4 PN2
WT2CCP1
PD1 PH1 PL5 PN3
WT3CCP0
PD2 PH4 PL6 PN4
WT3CCP1
PD3 PH5 PL7 PN5
WT4CCP0
PD4 PH6 PM0 PN6
WT4CCP1
PD5 PH7 PM1 PN7
M0FAULT0
PD2 PD6 PF2 PH0 PK4
M0FAULT1
PD7 PF3 PG2 PH1 PK5
M0PWM6
PC4 PD0 PG6 PH6 PN2
M0PWM7
PC5 PD1 PG7 PH7 PN3
five
22.6
Connections for Unused Signals
Table 22-7 on page 1280 shows how to handle signals for functions that are not used in a particular
system implementation for devices that are in a 144-pin LQFP package. Two options are shown in
the table: an acceptable practice and a preferred practice for reduced power consumption and
improved EMC characteristics. If a module is not used in a system, and its inputs are grounded, it
is important that the clock to the module is never enabled by setting the corresponding bit in the
RCGCx register.
Table 22-7. Connections for Unused Signals (144-Pin LQFP)
Function
GPIO
Signal Name
Pin Number
Acceptable Practice
Preferred Practice
All unused GPIOs
-
NC
GND
1280
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Table 22-7. Connections for Unused Signals (144-Pin LQFP) (continued)
Function
Signal Name
Pin Number
Acceptable Practice
HIB
73
NC
NC
VBAT
77
NC
VDD
WAKE
72
NC
GND
XOSC0
74
NC
GND
XOSC1
76
NC
NC
GNDX
75
GND
GND
NC
See NC pin numbers in
Table 22-3 on page 1249
NC
NC
OSC0
92
NC
GND
OSC1
93
NC
NC
RST
90
VDD
Pull up as shown in Figure
5-1 on page 211
Hibernate
No Connects
System Control
Preferred Practice
June 12, 2014
1281
Texas Instruments-Production Data
Electrical Characteristics
23
Electrical Characteristics
23.1
Maximum Ratings
The maximum ratings are the limits to which the device can be subjected without permanently
damaging the device. Device reliability may be adversely affected by exposure to absolute-maximum
ratings for extended periods.
Note:
The device is not guaranteed to operate properly at the maximum ratings.
Table 23-1. Absolute Maximum Ratings
Value
a
Parameter
Parameter Name
VDD
VDD supply voltage
b
Unit
Min
Max
0
4
V
VDDA
VDDA supply voltage
0
4
V
VBAT
VBAT battery supply voltage
0
4
V
VBAT battery supply voltage ramp time
0
0.7
V/µs
Input voltage on GPIOs, regardless of whether the
cde
microcontroller is powered
-0.3
5.5
V
Input voltage for PL6, PL7, PB0 and PB1 when
configured as GPIO
-0.3
VDD + 0.3
V
-
25
mA
-65
150
°C
-
150
°C
VBATRMP
VIN_GPIO
IGPIOMAX
TS
TJMAX
Maximum current per output pin
Unpowered storage temperature range
Maximum junction temperature
a. Voltages are measured with respect to GND.
b. To ensure proper operation, VDDA must be powered before VDD if sourced from different supplies, or connected to the
same supply as VDD. Note that the minimum operating voltage for VDD differs from the minimum operating voltage for
VDDA. This change should be accounted for in the system design if both are sourced from the same supply. There is
not a restriction on order for powering off.
c. Applies to static and dynamic signals including overshoot.
d. Refer to Figure 23-16 on page 1311 for a representation of the ESD protection on GPIOs.
e. For additional details, see the note on GPIO pad tolerance in “GPIO Module Characteristics” on page 1310.
Important: This device contains circuitry to protect the I/Os against damage due to high-static
voltages; however, it is advised that normal precautions be taken to avoid application
of any voltage higher than maximum-rated voltages to this high-impedance circuit.
Reliability of operation is enhanced if unused inputs are connected to an appropriate
logic voltage level (see “Connections for Unused Signals” on page 1280).
Table 23-2. ESD Absolute Maximum Ratings
Parameter
Component-Level ESD
a
Stress Voltage
Min
Nom
VESDHBM
b
Max
Unit
-
VESDCDM
c
-
-
2.0
kV
-
500
V
a. Electrostatic discharge (ESD) to measure device sensitivity/immunity to damage caused by electrostatic discharges in
device.
b. Level listed is passing level per ANSI/ESDA/JEDEC JS-001. JEDEC document JEP155 states that 500V HBM allows
safe manufacturing with a standard ESD control process.
c. Level listed is the passing level per EIA-JEDEC JESD22-C101E. JEDEC document JEP157 states that 250V CDM allows
safe manufacturing with a standard ESD control process.
1282
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
23.2
Operating Characteristics
Table 23-3. Temperature Characteristics
Characteristic
Symbol Value
Ambient operating temperature range
TA
Unit
-40 to +85
°C
Case operating temperature range
TC
-40 to +92
°C
Junction operating temperature range
TJ
-40 to +94
°C
a
Table 23-4. Thermal Characteristics
Characteristic
Symbol Value
b
Thermal resistance (junction to ambient) ΘJA
b
Unit
44.3
°C/W
Thermal resistance (junction to board)
ΘJB
25.2
°C/W
Thermal resistance (junction to case)
b
ΘJC
9.3
°C/W
Thermal metric (junction to top of
package)
ΨJT
0.2
°C/W
Thermal metric (junction to board)
ΨJB
24.7
°C/W
Junction temperature formula
TJ
TC + (P • ΨJT)
°C
c
TPCB + (P • ΨJB)
d
TA + (P • ΘJA)
ef
TB + (P • ΘJB)
a. For more details about thermal metrics and definitions, see the Semiconductor and IC Package Thermal Metrics Application
Report (literature number SPRA953).
b. Junction to ambient thermal resistance (ΘJA), junction to board thermal resistance (ΘJB), and junction to case thermal
resistance (ΘJC) numbers are determined by a package simulator.
c. TPCB is the temperature of the board acquired by following the steps listed in the EAI/JESD 51-8 standard summarized in
the Semiconductor and IC Package Thermal Metrics Application Report (literature number SPRA953).
d. Because ΘJA is highly variable and based on factors such as board design, chip/pad size, altitude, and external ambient
temperature, it is recommended that equations containing ΨJT and ΨJB be used for best results.
e. TB is temperature of the board.
f. ΘJB is not a pure reflection of the internal resistance of the package because it includes the resistance of the testing board
and environment. It is recommended that equations containing ΨJT and ΨJB be used for best results.
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23.3
Recommended Operating Conditions
For special high-current applications, the GPIO output buffers may be used with the following
restrictions. With the GPIO pins configured as 8-mA output drivers, a total of four GPIO outputs may
be used to sink current loads up to 18 mA each. At 18-mA sink current loading, the VOL value is
specified as 1.2 V. The high-current GPIO package pins must be selected such that there are only
a maximum of two per side of the physical package with the total number of high-current GPIO
outputs not exceeding four for the entire package.
Table 23-5. Recommended DC Operating Conditions
Parameter
Parameter Name
Min
Nom
Max
Unit
VDD
VDD supply voltage
3.15
3.3
3.63
V
VDDA
VDDA supply voltage
2.97
3.3
3.63
V
VDDC
VDDC supply voltage
1.08
1.2
1.32
V
VDDC supply voltage, Deep-sleep mode
1.08
-
1.32
V
ab
VDDCDS
a. These values are valid when LDO is in operation.
b. There are peripheral timing restrictions for SSI and LPC in Deep-sleep mode. Please refer to those peripheral characteristic
sections for more information.
Table 23-6. Recommended GPIO Pad Operating Conditions
Parameter
Parameter Name
Min
Nom
Max
Unit
VIH
GPIO high-level input voltage
0.65 * VDD
-
5.5
V
VIL
GPIO low-level input voltage
0
-
0.35 * VDD
V
-
V
VHYS
GPIO input hysteresis
0.2
-
VOH
GPIO high-level output voltage
2.4
-
-
V
VOL
GPIO low-level output voltage
-
-
0.4
V
2-mA Drive
2.0
-
-
mA
4-mA Drive
4.0
-
-
mA
8-mA Drive
8.0
-
-
mA
2-mA Drive
2.0
-
-
mA
4-mA Drive
4.0
-
-
mA
8-mA Drive
8.0
-
-
mA
8-mA Drive, VOL=1.2 V
18.0
-
-
mA
a
High-level source current, VOH=2.4 V
IOH
a
Low-level sink current, VOL=0.4 V
IOL
a. IO specifications reflect the maximum current where the corresponding output voltage meets the VOH/VOL thresholds. IO
current can exceed these limits (subject to absolute maximum ratings).
a
Table 23-7. GPIO Current Restrictions
Parameter
Min
Nom
Max
Unit
IMAXL
Parameter Name
Cumulative maximum GPIO current per side, left
-
-
110
mA
IMAXB
Cumulative maximum GPIO current per side,
b
bottom
-
-
105
mA
IMAXR
Cumulative maximum GPIO current per side, right
-
-
115
mA
IMAXT
b
-
-
135
mA
b
b
Cumulative maximum GPIO current per side, top
a. Based on design simulations, not tested in production.
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b. Sum of sink and source current for GPIOs as shown in Table 23-8 on page 1285.
Table 23-8. GPIO Package Side Assignments
Side
GPIOs
Left
PC[4-7], PD[0-3], PE[0-3], PH[0-7], PK[0-3], PN2, PP2
Bottom
PA[0-7], PF[0-7], PG[0-7], PN[4-7]
Right
PB[0-3], PL[0-7], PM[0-7], PN[0-1]
Top
PB[4-5], PC[0-3], PD[4-7], PE[4-7], PJ[0-7], PK[4-7], PN3, PP[0-1]
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23.4
Load Conditions
Unless otherwise specified, the following conditions are true for all timing measurements.
Figure 23-1. Load Conditions
CL = 50 pF
pin
GND
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23.5
JTAG and Boundary Scan
Table 23-9. JTAG Characteristics
Parameter
No.
Parameter
Parameter Name
J1
FTCK
TCK operational clock frequency
J2
TTCK
TCK operational clock period
a
Min
Nom
Max
Unit
0
-
10
MHz
100
-
-
ns
J3
TTCK_LOW
TCK clock Low time
-
tTCK/2
-
ns
J4
TTCK_HIGH
TCK clock High time
-
tTCK/2
-
ns
J5
TTCK_R
TCK rise time
0
-
10
ns
J6
TTCK_F
TCK fall time
0
-
10
ns
J7
TTMS_SU
TMS setup time to TCK rise
8
-
-
ns
J8
TTMS_HLD
TMS hold time from TCK rise
4
-
-
ns
J9
TTDI_SU
TDI setup time to TCK rise
18
-
-
ns
J10
TTDI_HLD
TDI hold time from TCK rise
4
TCK fall to Data Valid from High-Z, 2-mA drive
TCK fall to Data Valid from High-Z, 4-mA drive
J11
TTDO_ZDV
TCK fall to Data Valid from High-Z, 8-mA drive
-
TTDO_DV
TTDO_DVZ
ns
ns
9
26
ns
8
26
ns
10
29
ns
TCK fall to Data Valid from Data Valid, 2-mA drive
14
20
ns
10
26
ns
8
21
ns
TCK fall to Data Valid from Data Valid, 8-mA drive
with slew rate control
10
26
ns
TCK fall to High-Z from Data Valid, 2-mA drive
7
16
ns
7
16
ns
7
16
ns
8
19
ns
TCK fall to Data Valid from Data Valid, 8-mA drive
-
TCK fall to High-Z from Data Valid, 4-mA drive
J13
35
TCK fall to Data Valid from High-Z, 8-mA drive with
slew rate control
TCK fall to Data Valid from Data Valid, 4-mA drive
J12
13
TCK fall to High-Z from Data Valid, 8-mA drive
-
TCK fall to High-Z from Data Valid, 8-mA drive with
slew rate control
a. A ratio of at least 8:1 must be kept between the system clock and TCK.
Figure 23-2. JTAG Test Clock Input Timing
J2
J3
J4
TCK
J6
J5
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Figure 23-3. JTAG Test Access Port (TAP) Timing
TCK
J7
TMS
TDI
J8
J8
TMS Input Valid
TMS Input Valid
J9
J9
J10
TDI Input Valid
J11
TDO
J7
J10
TDI Input Valid
J12
TDO Output Valid
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23.6
Power and Brown-Out
Table 23-10. Power-On and Brown-Out Levels
Parameter
No.
Parameter
Parameter Name
P1
TVDDA_RISE
P2
TVDD_RISE
P3
a
TVDDC_RISE
P4
VPOR
P5
VVDDA_POK
b
Min
Nom
Max
Unit
Analog Supply Voltage (VDDA) Rise Time
-
-
∞
µs
I/O Supply Voltage (VDD) Rise Time
-
-
∞
µs
Core Supply Voltage (VDDC) Rise Time
10.00
-
150.00
µs
Power-On Reset Threshold
2.00
2.30
2.60
V
VDDA Power-OK Threshold (Rising Edge)
2.70
2.85
3.00
V
VDDA Power-OK Threshold (Falling Edge)
2.71
2.80
2.89
V
VDD Power-OK Threshold (Rising Edge)
2.85
3.00
3.15
V
P6
VVDD_POK
VDD Power-OK Threshold (Falling Edge)
2.70
2.78
2.87
V
P7
VVDD_BOR0
Brown-Out 0 Reset Threshold
2.93
3.02
3.11
V
P8
VVDD_BOR1
Brown-Out 1 Reset Threshold
2.83
2.92
3.01
V
P9
VVDDC_POK
VDDC Power-OK Threshold (Rising Edge)
0.80
0.95
1.10
V
VDDC Power-OK Threshold (Falling Edge)
0.71
0.80
0.89
V
a. The MIN and MAX values are guaranteed by design assuming the external filter capacitor load is within the range of
CLDO. Please refer to “On-Chip Low Drop-Out (LDO) Regulator” on page 1297 for the CLDO value.
b. Digital logic, Flash memory, and SRAM are all designed to operate at VDD voltages below 2.70 V. The internal POK reset
protects the device from unpredictable operation on power down.
23.6.1
VDDA Levels
The VDDA supply has two monitors:
■ Power-On Reset (POR)
■ Power-OK (POK)
The POR monitor is used to keep the analog circuitry in reset until the VDDA supply has reached
the correct range for the analog circuitry to begin operating. The POK monitor is used to keep the
digital circuitry in reset until the VDDA power supply is at an acceptable operational level. The digital
Power-On Reset (Digital POR) is only released when the Power-On Reset has deasserted and
all of the Power-OK monitors for each of the supplies indicate that power levels are in operational
ranges.
Once the VDDA POK monitor has released the digital Power-On Reset on the initial power-up, voltage
drops on the VDDA supply will only be reflected in the following bits. The digital Power-On Reset will
not be re-asserted.
■ VDDARIS bit in the Raw Interrupt Status (RIS) register (see page 239).
■ VDDAMIS bit in the Masked Interrupt Status and Clear (MISC) register (see page 243). This bit
is set only if the VDDAIM bit in the Interrupt Mask Control (IMC) register has been set.
Figure 23-4 on page 1290 shows the relationship between VDDA, POR, POK, and an interrupt event.
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Figure 23-4. Power Assertions versus VDDA Levels
P1
VDDAMIN
23.6.2
POR
1
POK
1
INT
VDDA
P5RISE
P4
1
P5FALL
P4
0
0
0
VDD Levels
The VDD supply has three monitors:
■ Power-OK (POK)
■ Brown-Out Reset0 (BOR0)
■ Brown-Out Reset1 (BOR1)
The POK monitor is used to keep the digital circuitry in reset until the VDD power supply is at an
acceptable operational level. The digital Power-On Reset (Digital POR) is only released when
the Power-On Reset has deasserted and all of the Power-OK monitors for each of the supplies
indicate that power levels are in operational ranges. The BOR0 and the BOR1 monitors are used
to generate a reset to the device or assert an interrupt if the VDD supply drops below its operational
range. The BOR1 monitor's threshold is in between the BOR0 and POK thresholds.
If either a BOR0 event or a BOR1 event occurs, the following bits are affected:
■ BOR0RIS or BOR1RIS bits in the Raw Interrupt Status (RIS) register (see page 239).
■ BOR0MIS or BOR1MIS bits in the Masked Interrupt Status and Clear (MISC) register (see
page 243). These bits are set only if the respective BOR0IM or BOR1IM bits in the Interrupt Mask
Control (IMC) register have been set.
■ BOR bit in the Reset Cause (RESC) register (see page 246). This bit is set only if either of the
BOR0 or BOR1 events have been configured to initiate a reset.
In addition, the following bits control both the BOR0 and BOR1 events:
■ BOR0IM or BOR1IM bits in the Interrupt Mask Control (IMC) register (see page 241).
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■ BOR0 or BOR1 bits in the Power-On and Brown-Out Reset Control (PBORCTL) register (see
page 238).
Figure 23-5 on page 1291 shows the relationship between:
■ VDD, POK, and a BOR0 event
■ VDD, POK, and a BOR1 event
Figure 23-5. Power and Brown-Out Assertions versus VDD Levels
P2
P6RISE
P7
BOR1
BOR0
POK
VDD
VDDMIN
23.6.3
P8
P6FALL
1
0
1
0
1
0
VDDC Levels
The VDDC supply has one monitor: the Power-OK (POK). The POK monitor is used to keep the
digital circuitry in reset until the VDDC power supply is at an acceptable operational level. The digital
Power-On Reset (Digital POR) is only released when the Power-On Reset has deasserted and
all of the Power-OK monitors for each of the supplies indicate that power levels are in operational
ranges. Figure 23-6 on page 1292 shows the relationship between POK and VDDC.
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Figure 23-6. POK assertion vs VDDC
POK
VDDC
P3
23.6.4
VDDCMIN
P9RISE
P9FALL
1
0
VDD Glitches
Figure 23-7 on page 1292 shows the response of the BOR0, BOR1, and the POR circuit to glitches
on the VDD supply.
Figure 23-7. POR-BOR0-BOR1 VDD Glitch Response
23.6.5
VDD Droop Response
Figure 23-8 on page 1293 shows the response of the BOR0, BOR1, and the POR monitors to a drop
on the VDD supply.
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Figure 23-8. POR-BOR0-BOR1 VDD Droop Response
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23.7
Reset
Table 23-11. Reset Characteristics
Parameter
No.
Parameter
R1
TDPORDLY
R2
TIRTOUT
R3
TBOR0DLY
Parameter Name
a
Digital POR to Internal Reset assertion delay
Standard Internal Reset time
Internal Reset time with recovery code repair
b
(program or erase)
Min
Nom
Max
Unit
0.80
-
5.35
µs
-
9
11.5
ms
c
-
-
6400
ms
a
0.25
-
1.95
µs
a
BOR0 to Internal Reset assertion delay
R3
TBOR1DLY
BOR1 to Internal Reset assertion delay
0.75
-
5.95
µs
R4
TRSTMIN
Minimum RST pulse width
-
250
-
ns
R5
TIRHWDLY
RST to Internal Reset assertion delay
-
250
-
ns
R6
TIRSWR
Internal reset timeout after software-initiated
system reset
-
2.07
-
µs
R7
TIRWDR
Internal reset timeout after Watchdog reset
-
2.10
-
µs
R8
TIRMFR
Internal reset timeout after MOSC failure reset
-
1.92
-
µs
a. Timing values are dependent on the VDD power-down ramp rate.
b. This parameter applies only in situations where a power-loss or brown-out event occurs during an EEPROM program or
erase operation, and EEPROM needs to be repaired (which is a rare case). For all other sequences, there is no impact
to normal Power-On Reset (POR) timing. This delay is in addition to other POR delays.
c. This value represents the maximum internal reset time when the EEPROM reaches its endurance limit.
Figure 23-9. Digital Power-On Reset Timing
Digital POR
R1
R2
Reset
(Internal)
Note:
The digital Power-On Reset is only released when the analog Power-On Reset has deasserted
and all of the Power-OK monitors for each of the supplies indicate that power levels are in operational
ranges.
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Figure 23-10. Brown-Out Reset Timing
BOR
R3
R2
Reset
(Internal)
Figure 23-11. External Reset Timing (RST)
R4
RST
(Package Pin)
R5
R2
Reset
(Internal)
Figure 23-12. Software Reset Timing
Software
Reset
R6
Reset
(Internal)
Figure 23-13. Watchdog Reset Timing
Watchdog
Reset
R7
Reset
(Internal)
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Figure 23-14. MOSC Failure Reset Timing
MOSC Fail
Reset
R8
Reset
(Internal)
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23.8
On-Chip Low Drop-Out (LDO) Regulator
Table 23-12. LDO Regulator Characteristics
Parameter
Parameter Name
Min
Nom
Max
Unit
CLDO
External filter capacitor size for internal power
a
supply
2.5
-
4.0
µF
ESR
Filter capacitor equivalent series resistance
10
-
100
mΩ
ESL
Filter capacitor equivalent series inductance
VLDO
LDO output voltage
IINRUSH
Inrush current
-
-
0.5
nH
1.08
1.2
1.32
V
50
-
250
mA
a. The capacitor should be connected as close as possible to pin 126.
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23.9
Clocks
The following sections provide specifications on the various clock sources and mode.
23.9.1
PLL Specifications
The following tables provide specifications for using the PLL.
Table 23-13. Phase Locked Loop (PLL) Characteristics
Parameter
FREF_XTAL
Parameter Name
External clock
PLL frequency
Max
Unit
-
25
MHz
5
-
25
MHz
-
400
-
5
a
referencea
FPLL
Nom
a
Crystal reference
FREF_EXT
TREADY
Min
b
MHz
c
reference clocks
c
reference clocks
PLL lock time, enabling the PLL
-
-
512 * (N+1)
PLL lock time, changing the XTAL field in the
RCC/RCC2 register or changing the OSCSRC
between MOSC and PIOSC
-
-
128 * (N+1)
d
d
a. If the PLL is not used, the minimum input frequency can be 4 MHz.
b. PLL frequency is automatically calculated by the hardware based on the XTAL field of the RCC register. The PLL frequency
that is set by the hardware can be calculated using the values in the PLLFREQ0 and PLLFREQ1 registers.
c. N is the value in the N field in the PLLFREQ1 register.
d. A reference clock is the clock period of the crystal being used, which can be MOSC or PIOSC. For example, a 16-MHz
crystal connected to MOSC yields a reference clock of 62.5 ns.
Table 23-14 on page 1298 shows the actual frequency of the PLL based on the crystal frequency used
(defined by the XTAL field in the RCC register).
Table 23-14. Actual PLL Frequency
XTAL
Crystal
Frequency
(MHz)
MINT
MFRAC
Q
N
PLL Multiplier
PLL
Frequency
(MHz)
Error
0x09
5.0
0x50
0x0
0x0
0x0
80
400
-
0x0A
5.12
0x9C
0x100
0x0
0x1
156.25
400
-
0x0B
6.0
0xC8
0x0
0x0
0x2
200
400
-
0x0C
6.144
0xC3
0x140
0x0
0x2
195.3125
400
-
0x0D
7.3728
0xA2
0x30A
0x0
0x2
162.7598
399.9984
0.0004%
0x0E
8.0
0x32
0x0
0x0
0x0
50
400
-
0x0F
8.192
0xC3
0x140
0x0
0x3
195.3125
400
-
0x10
10.0
0x50
0x0
0x0
0x1
80
400
-
0x11
12.0
0xC8
0x0
0x0
0x5
200
400
-
0x12
12.288
0xC3
0x140
0x0
0x5
195.3125
400
-
0x13
13.56
0xB0
0x3F6
0x0
0x5
176.9902
399.9979
0.0005%
0x14
14.318
0xC3
0x238
0x0
0x6
195.5547
399.9982
0.0005%
0x15
16.0
0x32
0x0
0x0
0x1
50
400
-
0x16
16.384
0xC3
0x140
0x0
0x7
195.3125
400
-
0x17
18
0xC8
0x0
0x0
0x8
200
400
-
0x18
20
0x50
0x0
0x0
0x3
80
400
-
0x19
24
0x32
0x0
0x0
0x2
50
400
-
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Table 23-14. Actual PLL Frequency (continued)
23.9.2
XTAL
Crystal
Frequency
(MHz)
MINT
MFRAC
Q
N
PLL Multiplier
PLL
Frequency
(MHz)
Error
0x1A
25
0x50
0x0
0x0
0x4
80
400
-
PIOSC Specifications
Table 23-15. PIOSC Clock Characteristics
Parameter
FPIOSC
Parameter Name
Min
Nom
Max
Unit
Factory calibration:
-
-
±3%
-
-
-
±1%
a
-
-
-
1
µs
Internal 16-MHz precision oscillator frequency variance across
the specified voltage and temperature range when factory
calibration is used
Recalibration:
Internal 16-MHz precision oscillator frequency variance when
7-bit recalibration is used
TSTART
b
PIOSC startup time
a. ±1% is only guaranteed at the specific voltage/temperature condition where the recalibration occurs.
b. PIOSC startup time is part of reset and is included in the internal reset timeout value (TIRTOUT) given in Table
23-11 on page 1294. Note that the TSTART value is based on simulation.
23.9.3
Low-Frequency Internal Oscillator (LFIOSC) Specifications
Table 23-16. Low-Frequency internal Oscillator Characteristics
Parameter
FLFIOSC
23.9.4
Parameter Name
Low-frequency internal oscillator (LFIOSC)
frequency
Min
Nom
Max
Unit
10
33
90
KHz
Hibernation Clock Source Specifications
Table 23-17. Hibernation Oscillator Input Characteristics
Parameter
Parameter Name
FHIBLFIOSC
Hibernation low frequency internal oscillator (HIB
LFIOSC) frequency
C1, C2
CINSE
CPKG
CPCB
CSHUNT
Min
Nom
Max
Unit
10
33
90
KHz
External load capacitance on XOSC0, XOSC1 pins
12
-
24
pF
Input capacitance of XOSC0 in single-ended mode
-
-
2
pF
-
0.5
-
pF
a
a
Device package stray shunt capacitance
a
PCB stray shunt capacitance
-
0.5
-
pF
-
-
4
pF
b
-
-
50
kΩ
b
Crystal effective series resistance, OSCDRV = 1
-
-
75
kΩ
Oscillator output drive level
-
-
0.25
µW
-
600
1500
ms
CMOS input high level, when using an external oscillator
with Supply > 3.3 V
2.64
-
-
V
CMOS input high level, when using an external oscillator
with 1.8 V ≤ Supply ≤ 3.3 V
0.8 *
Supply
-
-
V
a
Total shunt capacitance
Crystal effective series resistance, OSCDRV = 0
ESR
DL
TSTART
e
VIH
c
Oscillator startup time, when using a crystal
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Table 23-17. Hibernation Oscillator Input Characteristics (continued)
Parameter
e
VIL
e
VHYS
Parameter Name
Min
Nom
Max
Unit
CMOS input low level, when using an external oscillator
with 1.8 V ≤ Supply ≤ 3.63 V
-
-
0.2 * Supply
V
CMOS input buffer hysteresis, when using an external
oscillator with 1.8 V ≤ Supply ≤ 3.63 V
360
960
1390
mV
30
-
70
%
DCHIBOSC_EXT External clock reference duty cycle
a. See information below table.
b. Crystal ESR specified by crystal manufacturer.
c. Oscillator startup time is specified from the time the oscillator is enabled to when it reaches a stable point of oscillation
such that the internal clock is valid.
d. Only valid for recommended supply conditions. Measured with OSCDRV bit set (high drive strength enabled, 24 pF).
e. Specification is relative to the larger of VDD or VBAT.
The load capacitors added on the board, C1 and C2, should be chosen such that the following
equation is satisfied (see Table 23-17 on page 1299 for typical values).
■ CL = load capacitance specified by crystal manufacturer
■ CL = (C1*C2)/(C1+C2) + CPKG + CPCB
■ CSHUNT = CPKG + CPCB + C0 (total shunt capacitance seen across XOSC0, XOSC1)
■ CPKG, CPCB as measured across the XOSC0, XOSC1 pins excluding the crystal
■ Clear the OSCDRV bit in the Hibernation Control (HIBCTL) register for C1,2 ≤ 18 pF; set the
OSCDRV bit for C1,2 > 18 pF.
■ C0 = Shunt capacitance of crystal specified by the crystal manufacturer
23.9.5
Main Oscillator Specifications
Table 23-18. Main Oscillator Input Characteristics
Parameter
Parameter Name
Min
FMOSC
Parallel resonance frequency
C1, C2
External load capacitance on OSC0, OSC1 pins
CPKG
CPCB
CSHUNT
b
b
Device package stray shunt capacitance
b
PCB stray shunt capacitance
b
Total shunt capacitance
MHz
pF
0.5
-
pF
-
0.5
-
pF
-
-
4
pF
-
300
Ω
cd
-
-
200
Ω
cd
-
-
130
Ω
cd
-
-
120
Ω
cd
-
-
100
Ω
cd
-
-
50
Ω
-
OSCPWR
-
mW
-
-
18
ms
0.65 * VDD
-
VDD
V
Crystal effective series resistance, 12 MHz
Crystal effective series resistance, 16 MHz
Crystal effective series resistance, 25 MHz
VIH
25
24
-
Crystal effective series resistance, 8 MHz
TSTART
-
4
-
Crystal effective series resistance, 6 MHz
DL
Unit
10
Nom
cd
Crystal effective series resistance, 4 MHz
ESR
Max
a
e
Oscillator output drive level
f
Oscillator startup time, when using a crystal
CMOS input high level, when using an external
oscillator
1300
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Table 23-18. Main Oscillator Input Characteristics (continued)
Parameter
Parameter Name
Min
Nom
Max
VIL
CMOS input low level, when using an external oscillator
GND
-
0.35 * VDD
V
VHYS
CMOS input buffer hysteresis, when using an external
oscillator
150
-
-
mV
External clock reference duty cycle
45
-
55
%
DCOSC_EXT
Unit
a. 5 MHz is the minimum when using the PLL.
b. See information below table.
c. Crystal ESR specified by crystal manufacturer.
d. Crystal vendors can be contacted to confirm these specifications are met for a specific crystal part number if the vendors
generic crystal datasheet show limits outside of these specifications.
e. OSCPWR = (2 * pi * FP * CL * 2.5)2 * ESR / 2. An estimation of the typical power delivered to the crystal is based on the
CL, FP and ESR parameters of the crystal in the circuit as calculated by the OSCPWR equation. Ensure that the value
calculated for OSCPWR does not exceed the crystal's drive-level maximum.
f. Oscillator startup time is specified from the time the oscillator is enabled to when it reaches a stable point of oscillation
such that the internal clock is valid.
The load capacitors added on the board, C1 and C2, should be chosen such that the following
equation is satisfied (see Table 23-18 on page 1300 for typical values and Table 23-19 on page 1302
for detailed crystal parameter information).
■ CL = load capacitance specified by crystal manufacturer
■ CL = (C1*C2)/(C1+C2) + CSHUNT
■ CSHUNT = C0 + CPKG + CPCB (total shunt capacitance seen across OSC0, OSC1 crystal inputs)
■ CPKG, CPCB = the mutual caps as measured across the OSC0,OSC1 pins excluding the crystal.
■ C0 = Shunt capacitance of crystal specified by the crystal manufacturer
Table 23-19 on page 1302 lists part numbers of crystals that have been simulated and confirmed to
operate within the specifications in Table 23-18 on page 1300. Other crystals that have nearly identical
crystal parameters can be expected to work as well.
In the table below, the crystal parameters labeled C0, C1 and L1 are values that are obtained from
the crystal manufacturer. These numbers are usually a result of testing a relevant batch of crystals
on a network analyzer. The parameters labeled ESR, DL and CL are maximum numbers usually
available in the data sheet for a crystal.
The table also includes three columns of Recommended Component Values. These values apply
to system board components. C1 and C2 are the values in pico Farads of the load capacitors that
should be put on each leg of the crystal pins to ensure oscillation at the correct frequency. Rs is the
value in kΩ of a resistor that is placed in series with the crystal between the OSC1 pin and the crystal
pin. Rs dissipates some of the power so the Max Dl crystal parameter is not exceeded. Only use
the recommended C1, C2, and Rs values with the associated crystal part. The values in the table
were used in the simulation to ensure crystal startup and to determine the worst case drive level
(WC Dl). The value in the WC Dl column should not be greater than the Max Dl Crystal parameter.
The WC Dl value can be used to determine if a crystal with similar parameter values but a lower
Max Dl value is acceptable.
June 12, 2014
1301
Texas Instruments-Production Data
Electrical Characteristics
Crystal Spec
(Tolerance /
Stability)
Max Values
12
0
132
ESR (Ω)
Rs (kΩ)
12
C2 (pF)
8
C1 (pF)
500
CL (pf)
1.00 2.70 598.10 300
Max Dl (µW)
30/50 ppm
L1 (mH)
4
C1 (fF)
8 x 4.5
C0 (pF)
NX8045GB
PKG Size
Freq (MHz)
NX8045GB-
Typical Values
Recommended
Component
Values
(mm x mm)
NDK
Holder
MFG
MFG Part#
Crystal Parameters
WC Dl (μW)
Table 23-19. Crystal Parameters
4.000M-STDCJL-5
FOX
FQ1045A-4
2-SMD
10 x 4.5
4
30/30 ppm
1.18 4.05 396.00 150
500
10
14
14
0
103
NDK
NX8045GB-
NX8045GB
8 x 4.5
5
30/50 ppm
1.00 2.80 356.50 250
500
8
12
12
0
164
NX8045GB
8 x 4.5
6
30/50 ppm
1.30 4.10 173.20 250
500
8
12
12
0
214
5.000M-STDCSF-4
NDK
NX8045GB6.000M-STDCSF-4
FOX
FQ1045A-6
2-SMD
10 x 4.5
6
30/30 ppm
1.37 6.26 112.30 150
500
10
14
14
0
209
NDK
NX8045GB-
NX8045GB
8 x 4.5
8
30/50 ppm
1.00 2.80 139.30 200
500
8
12
12
0
277
4-SMD
7x5
8
30/30 ppm
1.95 6.69 59.10
80
500
10
14
14
0
217
8
50/30 ppm
1.82 4.90 85.70
80
500
16
24
24
0
298
7.2 x 5.2
12
10/20 ppm
2.37 8.85
50
500
10
12
12
2.0
a
124
NX3225GA 3.2 x 2.5
12
20/30 ppm
0.70 2.20 81.00 100
200
8
12
12
2.5
147
NX5032GA
5 x 3.2
12
30/50 ppm
0.93 3.12 56.40 120
500
8
12
12
0
362
4-SMD
5 x 3.2
12
30/30 ppm
1.16 4.16 42.30
500
10
14
14
0
8.000M-STDCSF-6
FOX
FQ7050B-8
ECS
ECS-80-16-
HC49/US 12.5 x 4.85
28A-TR
Abracon AABMM-
ABMM
20.5
12.0000MHz10-D-1-X-T
NDK
NX3225GA12.000MHZSTD-CRG-2
NDK
NX5032GA12.000MHZLN-CD-1
FOX
FQ5032B-12
Abracon AABMM-
ABMM
7.2 x 5.2
80
370
a
143
a
16
10/20 ppm
3.00 11.00 9.30
50
500
10
12
12
2.0
HC-49/UP 13.3 x 4.85
16
15/30 ppm
3.00 12.7
50
1000
10
12
12
2.0
139
NX3225GA 3.2 x 2.5
16
20/30 ppm
1.00 2.90 33.90
80
200
8
12
12
2
188
NX5032GA
16
30/50ppm
1.02 3.82 25.90 120
500
8
10
10
0
437
16.0000MHz10-D-1-X-T
Ecliptek ECX-6595-
8.1
16.000M
NDK
NX3225GA16.000MHZSTD-CRG-2
NDK
NX5032GA-
5 x 3.2
b
16.000MHZLN-CD-1
1302
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Table 23-19. Crystal Parameters (continued)
WC Dl (μW)
Max Values
289
ABMM
7.2 x 5.2
25
10/20 ppm
3.00 11.00 3.70
50
500
10
12
12
2.0
a
158
HC-49/UP 13.3 x 4.85
25
15/30 ppm
3.00 12.8
3.2
40
1000
10
12
12
1.5
a
159
NX3225GA 3.2 x 2.5
25
20/30 ppm
1.10 4.70
8.70
50
200
8
12
12
2
181
10
10
1.0
CL (pf)
C1 (fF)
Rs (kΩ)
0.5
C2 (pF)
12
C1 (pF)
12
Max Dl (µW)
9
ESR (Ω)
300
ECX-42
L1 (mH)
60
ECS-160-9-42-
C0 (pF)
1.47 3.90 25.84
ECS
PKG Size
10/10 ppm
Holder
16
MFG Part#
4 x 2.5
MFG
Freq (MHz)
Typical Values
Recommended
Component
Values
(mm x mm)
Crystal Spec
(Tolerance /
Stability)
Crystal Parameters
CKM-TR
Abracon AABMM25.0000MHz10-D-1-X-T
Ecliptek ECX-659325.000M
NDK
NX3225GA25.000MHZSTD-CRG-2
NX5032GA-
NDK
25.000MHZ-
a
c
216
NX5032GA
5 x 3.2
25
30/50 ppm
1.3
5.1
7.1
70
500
8
12
12
0.75
269
HC3225/4
3.2 x 2.5
25
30/30 ppm
1.58 5.01
8.34
50
500
12
16
16
1
331
4-SMD
5 x 3.2
25
30/30 ppm
1.69 7.92
5.13
50
500
10
14
14
0.5
433
12
c
124
LD-CD-1
AURIS Q-25.000MHC3225/4F-30-30-E-12-TR
FOX
TXC
FQ5032B-25
7A2570018
NX5032GA
5 x 3.2
25
20/25 ppm
2.0
6.7
6.1
30
350
10
12
2.0
a. RS values as low as 0 Ohms can be used. Using a lower RS value will result in the WC DL to increase towards the Max DL of the crystal.
b. Although this ESR value is outside of the recommended crystal ESR maximum for this frequency, this crystal has been simulated to
confirm proper operation and is valid for use with this device.
c. RS values as low as 500 Ohms can be used. Using a lower RS value will result in the WC DL to increase towards the Max DL of the
crystal.
Table 23-20. Supported MOSC Crystal Frequencies
Value
Crystal Frequency (MHz) Not Using the PLL
0x00-0x5
0x06
Crystal Frequency (MHz) Using the PLL
reserved
4 MHz
reserved
0x07
4.096 MHz
reserved
0x08
4.9152 MHz
reserved
0x09
5 MHz
0x0A
5.12 MHz
0x0B
6 MHz
0x0C
6.144 MHz
0x0D
7.3728 MHz
0x0E
8 MHz
0x0F
8.192 MHz
0x10
10.0 MHz
June 12, 2014
1303
Texas Instruments-Production Data
Electrical Characteristics
Table 23-20. Supported MOSC Crystal Frequencies (continued)
Value
23.9.6
Crystal Frequency (MHz) Not Using the PLL
Crystal Frequency (MHz) Using the PLL
0x11
12.0 MHz
0x12
12.288 MHz
0x13
13.56 MHz
0x14
14.31818 MHz
0x15
16.0 MHz (reset value)
0x16
16.384 MHz
0x17
18.0 MHz
0x18
20.0 MHz
0x19
24.0 MHz
0x1A
25.0 MHz
System Clock Specification with ADC Operation
Table 23-21. System Clock Characteristics with ADC Operation
Parameter
Fsysadc
Parameter Name
System clock frequency when the ADC
a
module is operating (when PLL is bypassed).
Min
Nom
Max
Unit
15.9952
16
16.0048
MHz
a. Clock frequency (plus jitter) must be stable inside specified range. ADC can be clocked from the PLL, directly from an
external clock source, or from the PIOSC, as long as frequency absolute precision is inside specified range.
1304
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
23.10
Sleep Modes
a
Table 23-22. Sleep Modes AC Characteristics
Parameter
No
Parameter
Min
Nom
Max
Unit
Time to wake from interrupt in sleep mode
-
-
2
system
clocks
Time to wake from interrupt in deep-sleep mode,
using PIOSC for both Run mode and Deep-sleep
bc
mode
-
1.25
-
µs
Time to wake from interrupt in deep-sleep mode,
using PIOSC for Run mode and LFIOSC for
bc
Deep-sleep mode
-
350
-
µs
TWAKE_PLL_DS Time to wake from interrupt in deep-sleep mode
b
when using the PLL
-
-
TREADY
ms
TWAKE_S
D1
TWAKE_DS
D2
Parameter Name
b
a. Values in this table assume the LFIOSC is the clock source during sleep or deep-sleep mode.
b. Specified from registering the interrupt to first instruction.
c. If the main oscillator is used for run mode, add the main oscillator startup time, TSTART.
ab
Table 23-23. Time to Wake with Respect to Low-Power Modes
Mode
Sleep/Deep-Sleep
Run Mode
Mode
FLASHPM SRAMPM
Clock/Frequency
Clock/Frequency
0x0
Sleep
MOSC, PLL on 80MHz
MOSC, PLL on 80MHz
0x2
Time to Wake
Unit
Min
Max
0x0
0.28
0.30
µs
0x1
33.57
35.00
µs
0x3
33.75
35.05
µs
0x0
105.02
109.23
µs
0x1
137.85
143.93
µs
0x3
138.06
143.86
µs
June 12, 2014
1305
Texas Instruments-Production Data
Electrical Characteristics
Table 23-23. Time to Wake with Respect to Low-Power Modes (continued)
Mode
Sleep/Deep-Sleep
Run Mode
Mode
FLASHPM SRAMPM
Clock/Frequency
Clock/Frequency
0x0
MOSC, PLL on 80MHz
PIOSC - 16MHz
0x2
0x0
PIOSC - 16MHz
PIOSC - 16MHz
0x2
Deep-Sleep
0x0
PIOSC - 16MHz
LFIOSC, PIOSC
c
off - 30kHz
0x2
0x0
MOSC, PLL on 80MHz
LFIOSC, PIOSC
c
off - 30kHz
0x2
Time to Wake
Unit
Min
Max
0x0
2.47
2.60
µs
0x1
35.31
36.35
µs
0x3
35.40
36.76
µs
0x0
107.05
111.54
µs
0x1
139.34
145.64
µs
0x3
140.41
145.53
µs
0x0
2.47
2.61
µs
0x1
35.25
36.65
µs
0x3
35.38
36.79
µs
0x0
107.43
111.52
µs
0x1
139.83
145.85
µs
0x3
139.35
145.54
µs
0x0
415.06
728.38
µs
0x1
436.60
740.88
µs
0x3
433.80
755.32
µs
0x0
503.73
812.82
µs
0x1
537.72
846.23
µs
0x3
536.10
839.25
µs
0x0
18.95
19.55
ms
0x1
18.94
19.54
ms
0x3
18.95
19.53
ms
0x0
18.95
19.54
ms
0x1
18.94
19.53
ms
0x3
18.95
19.54
ms
a. Time from wake event to first instruction of code execution.
b. If the LDO voltage is adjusted, it will take an extra 4 us to wake up from Sleep or Deep-sleep mode.
c. PIOSC is turned off by setting the PIOSCPD bit in the DSLPCLKCFG register.
1306
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
23.11
Hibernation Module
The Hibernation module requires special system implementation considerations because it is intended
to power down all other sections of its host device, refer to “Hibernation Module” on page 491.
Table 23-24. Hibernation Module Battery Characteristics
Parameter
VBAT
b
VBATRMP
VLOWBAT
Parameter Name
Min
Nominal
Max
Battery supply voltage
1.8
3.0
3.6
V
0
-
0.7
V/µs
Low battery detect voltage, VBATSEL=0x0
1.8
1.9
2.0
V
Low battery detect voltage, VBATSEL=0x1
2.0
2.1
2.2
V
Low battery detect voltage, VBATSEL=0x2
2.2
2.3
2.4
V
Low battery detect voltage, VBATSEL=0x3
2.4
2.5
2.6
V
VBAT battery supply voltage ramp time
a
Unit
a. To ensure proper functionality, any voltage input within the range of 3.6 V < VBAT ≤ 4 V must be connected through a
diode.
b. For recommended VBAT RC circuit values, refer to the diagrams located in“Hibernation Clock Source” on page 494.
Table 23-25. Hibernation Module AC Characteristics
Parameter
No
Parameter
H1
TWAKE
H2
Parameter Name
WAKE assertion time
Min
Nom
Max
Unit
100
-
-
ns
-
-
1
hibernation
clock period
TWAKE_TO_HIB WAKE assert to HIB desassert (wake up
time)
H3
TVDD_RAMP
VDD ramp to 3.0 V
-
Depends on
characteristics
of power supply
-
μs
H4
TVDD_CODE
VDD at 3.0 V to internal POR deassert; first
instruction executes
-
-
500
μs
Duty cycle for RTCCLK output signal, when
using a 32.768-kHz crystal
40
-
60
%
Duty cycle for RTCCLK output signal, when
using a 32.768-kHz single-ended clock
source
30
-
70
%
H5
DCRTCCLK
June 12, 2014
1307
Texas Instruments-Production Data
Electrical Characteristics
Figure 23-15. Hibernation Module Timing
H1
WAKE
H2
HIB
H3
VDD
H4
POR
1308
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
23.12
Flash Memory and EEPROM
Table 23-26. Flash Memory Characteristics
Parameter
PECYC
TRET
TPROG64
TERASE
TME
Parameter Name
a
Number of program/erase cycles before failure
Min
Nom
Max
Unit
100,000
-
-
cycles
Data retention, -40˚C to +85˚C
20
-
-
years
Program time for double-word-aligned 64 bits of
b
data
30
50
300
µs
Page erase time, 1.
b. If programming fewer than 64 bits of data, the programming time is the same. For example, if only 32 bits of data need
to be programmed, the other 32 bits are masked off.
a
Table 23-27. EEPROM Characteristics
Parameter Parameter Name
b
EPECYC
ETRET
ETPROG
ETREAD
ETME
Min
Number of mass program/erase cycles of a single word before 500,000
c
failure
Data retention, -40˚C to +85˚C
Nom
Max
Unit
-
-
cycles
20
-
-
years
Program time for 32 bits of data - space available
-
110
600
μs
Program time for 32 bits of data - requires a copy to the copy
buffer, copy buffer has space and less than 10% of EEPROM
endurance used
-
30
-
ms
Program time for 32 bits of data - requires a copy to the copy
buffer, copy buffer has space and greater than 90% of
EEPROM endurance used
-
-
900
ms
Program time for 32 bits of data - requires a copy to the copy
buffer, copy buffer requires an erase and less than 10% of
EEPROM endurance used
-
60
-
ms
Program time for 32 bits of data - requires a copy to the copy
buffer, copy buffer requires an erase and greater than 90% of
EEPROM endurance used
-
-
1800
ms
Read access time
-
4
-
system clocks
Mass erase time, 0 -> 1.
June 12, 2014
1309
Texas Instruments-Production Data
Electrical Characteristics
23.13
Input/Output Pin Characteristics
23.13.1
GPIO Module Characteristics
Note:
All GPIO signals are 5-V tolerant when configured as inputs except for PL6, PL7, PB0 and
PB1, which are limited to 3.6 V. See “Signal Description” on page 647 for more information
on GPIO configuration.
Note:
GPIO pads are tolerant to 5-V digital inputs without creating reliability issues, as long as
the supply voltage, VDD, is present. There are limitations to how long a 5-V input can be
present on any given I/O pad if VDD is not present. Not meeting these conditions will affect
reliability of the device and affect the GPIO characteristics specifications.
■ If the voltage applied to a GPIO pad is in the high voltage range (5V +/- 10%) while VDD
is not present, such condition should be allowed for a maximum of 10,000 hours at 27°C
or 5,000 hours at 85°C, over the lifetime of the device.
■ If the voltage applied to a GPIO pad is in the normal voltage range (3.3V +/- 10%) while
VDD is not present or if the voltage applied is in the high voltage range (5V +/- 10%)
while VDD is present, there are no constraints on the lifetime of the device.
a
Table 23-28. GPIO Module Characteristics
Parameter Parameter Name
CGPIO
Min
Max
Unit
-
8
-
pF
RGPIOPU
GPIO internal pull-up resistor
13
20
30
kΩ
RGPIOPD
GPIO internal pull-down resistor
13
20
35
kΩ
GPIO input leakage current, 0 V ≤ VIN ≤ VDD GPIO
b
pins
-
-
1.0
µA
GPIO input leakage current, 0 V < VIN ≤ VDD, GPIO
pins configured as ADC or analog comparator inputs
-
-
2.0
µA
14.2
16.1
ns
11.9
15.5
ns
8.1
11.2
ns
9.5
11.8
ns
25.2
29.4
ns
13.3
16.8
ns
8.6
11.2
ns
11.3
12.9
ns
ILKG+
GPIO Digital Input Capacitance
Nom
c
GPIO rise time, 2-mA drive
c
TGPIOR
GPIO rise time, 4-mA drive
-
c
GPIO rise time, 8-mA drive
c
GPIO rise time, 8-mA drive with slew rate control
d
GPIO fall time, 2-mA drive
d
TGPIOF
GPIO fall time, 4-mA drive
-
d
GPIO fall time, 8-mA drive
d
GPIO fall time, 8-mA drive with slew rate control
a. VDD must be within the range specified in Table 23-5 on page 1284.
b. The leakage current is measured with VIN applied to the corresponding pin(s). The leakage of digital port pins is measured
individually. The port pin is configured as an input and the pull-up/pull-down resistor is disabled.
c. Time measured from 20% to 80% of VDD.
d. Time measured from 80% to 20% of VDD.
23.13.2
Types of I/O Pins and ESD Protection
With respect to ESD and leakage current, three types of I/O pins exist on the device: Power I/O
pins, I/O pins with fail-safe ESD protection (GPIOs other than PL6 and PL7, and XOSCn pins) and
I/O pins with non-fail-safe ESD protection (any non-power, non-GPIO (other than PL6 and PL7) and
1310
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
non-XOSCn pins). This section covers I/O pins with fail-safe ESD protection and I/O pins with
non-fail-safe ESD protection. Power I/O pin voltage and current limitations are specified in
“Recommended Operating Conditions” on page 1284.
23.13.2.1 Fail-Safe Pins
GPIOs other than PL6 and PL7, inputs for the Hibernate 32-kHz oscillator (XOSCn), and Hibernate
inputs use ESD protection as shown in Figure 23-16 on page 1311.
An unpowered device cannot be parasitically powered through any of these pins. This ESD protection
prevents a direct path between these I/O pads and any power supply rails in the device. GPIO/XOSCn
pad input voltages should be kept inside the maximum ratings specified in Table 23-1 on page 1282
to ensure current leakage and current injections are within acceptable range. Current leakages and
current injection for these pins are specified in Table 23-28 on page 1310.
Figure 23-16 on page 1311 shows a diagram of the ESD protection on fail-safe pins.
Some GPIOs when configured as inputs require a strong pull-up resistor to maintain a threshold
above the minimum value of VIH during power-on. See Table 23-30 on page 1312.
Figure 23-16. ESD Protection on Fail-Safe Pins
VDD
I/O Pad
ESD
Clamp
GND
a
Table 23-29. Pad Voltage/Current Characteristics for Fail-Safe Pins
Parameter
Parameter Name
bb
ILKG+
GPIO input leakage current, VDD< VIN ≤ 4.5 V
bc
GPIO input leakage current, 4.5 V < VIN ≤ 5.5 V
bd
ILKGIINJ+
IINJ-
GPIO input leakage current, VIN < -0.3 V
b
GPIO input leakage current, -0.3 V ≤ VIN < 0 V
fg
DC injection current, VDD < VIN ≤ 5.5 V
g
DC injection current, VIN ≤ 0 V
Min
Nom
Max
Unit
-
-
700
µA
-
-
100
µA
-
-
e
-
µA
-
-
10
µA
-
-
ILKG+
µA
-
-
0.5
mA
a. VIN must be within the range specified in Table 23-1 on page 1282.
b. To protect internal circuitry from over-voltage, the GPIOs have an internal voltage clamp that limits internal swings to VDD
without affecting swing at the I/O pad. This internal clamp starts turning on while VDD < VIN < 4.5 V and causes a somewhat
larger (but bounded) current draw. To save power, static input voltages between VDD and 4.5 V should be avoided.
c. Leakage current above maximum voltage (VIN = 5.5V) is not guaranteed, this condition is not allowed and can result in
permanent damage to the device.
d. Leakage outside the minimum range (-0.3V) is unbounded and must be limited to IINJ- using an external resistor.
e. In this case, ILKG- is unbounded and must be limited to IINJ- using an external resistor.
June 12, 2014
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Electrical Characteristics
f. Current injection is internally bounded for GPIOs, and maximum current into the pin is given by ILKG+ for VDD < VIN < 5.5
V.
g. If the I/O pad is not voltage limited, it should be current limited (to IINJ+ and IINJ-) if there is any possibility of the pad
voltage exceeding the VIO limits (including transient behavior during supply ramp up, or at any time when the part is
unpowered).
Table 23-30. Fail-Safe GPIOs that Require an External Pull-up
GPIO
Pin
Pull-Up Resistor Value
Unit
PB0
97
1k ≤ R ≤ 10k
Ω
PB1
98
1k ≤ R ≤ 10k
Ω
PE3
12
1k ≤ R ≤ 10k
Ω
23.13.2.2 Non-Fail-Safe Pins
The ADC external voltage reference input pins, the Main Oscillator (MOSC) crystal connection pins
and GPIO pins PL6 and PL7 have ESD protection as shown in Figure 23-17 on page 1312. These
pins have a potential path between the I/O pad and an internal power rail if either one of the ESD
diodes is accidentally forward biased. The voltage and current of these pins should follow the
specifications in Table 23-31 on page 1312 to prevent potential damage to the device. In addition to
the specifications outlined in Table 23-31 on page 1312, it is recommended that the ADC external
reference specifications in Table 23-32 on page 1314 be adhered to in order to prevent any gain error.
Figure 23-17 on page 1312 shows a diagram of the ESD protection on non-fail-safe pins.
Figure 23-17. ESD Protection on Non-Fail-Safe Pins
VDD
I/O Pad
GND
abcd
Table 23-31. Non-Fail-Safe I/O Pad Voltage/Current Characteristics
Parameter
VIO
ILKG+
Parameter Name
Min
Nom
Max
Unit
-0.3
VDD
VDD+0.3
V
ef
-
-
10
µA
ef
-
-
10
µA
-
-
2
mA
-
-
-0.5
mA
IO pad voltage limits
Positive IO leakage for VIO Max
ILKG-
Negative IO leakage for VIO Min
IINJ+
Max positive injection
IINJ-
Max negative injection if not voltage protected
g
g
a. VIN must be within the range specified in Table 23-1 on page 1282. Leakage current outside of this maximum voltage is not
guaranteed and can result in permanent damage of the device.
b. VDD must be within the range specified in Table 23-5 on page 1284.
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c. To avoid potential damage to the part, either the voltage or current on the ESD-protected, non-Power, non-Hibernate/XOSC
input/outputs should be limited externally as shown in this table.
d. I/O pads should be protected if at any point the IO voltage has a possibility of going outside the limits shown in the table.
If the part is unpowered, the IO pad Voltage or Current must be limited (as shown in this table) to avoid powering the
part through the IO pad, causing potential irreversible damage.
e. This value applies to an I/O pin that is voltage-protected within the Min and Max VIO ratings. Leakage outside the specified
voltage range is unbounded and must be limited to IINJ- using an external resistor.
f. MIN and MAX leakage current for the case when the I/O is voltage-protected to VIO Min or VIO Max.
g. If an I/O pin is not voltage-limited, it should be current-limited (to IINJ+ and IINJ-) if there is any possibility of the pad voltage
exceeding the VIO limits (including transient behavior during supply ramp up, or at any time when the part is unpowered).
June 12, 2014
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Electrical Characteristics
23.14
Analog-to-Digital Converter (ADC)
ab
Table 23-32. ADC Electrical Characteristics
Parameter
Parameter Name
Min
Nom
Max
Unit
POWER SUPPLY REQUIREMENTS
VDDA
ADC supply voltage
2.97
3.3
3.63
V
GNDA
ADC ground voltage
-
0
-
V
-
1.0 // 0.01
-
μF
VDDA / GNDA VOLTAGE REFERENCE
CREF
Voltage reference decoupling capacitance
c
EXTERNAL VOLTAGE REFERENCE INPUT
VREFA+
Positive external voltage reference for ADC,
when VREF field in the ADCCTL register is not
d
0x0 -
2.4
VDDA
VDDA
V
VREFA-
Negative external voltage reference for ADC,
when VREF field in the ADCCTL register is not
d
0x0
GNDA
GNDA
0.3
V
IVREF
Current on VREF+ input, using external VREF+
= 3.3 V
-
330.5
440
µA
ILVREF
DC leakage current on VREF+ input when
external VREF disabled
-
-
2.0
µA
CREF
External reference decoupling capacitance
-
1.0 // 0.01
-
μF
0
-
VDDA
V
Differential, full-scale analog input voltage,
fh
internal reference
-VDDA
-
VVDDA
V
Single-ended, full-scale analog input voltage,
dg
external reference
VREFA-
-
VREFA+
V
- (VREFA+ VREFA-)
-
VREFA+ VREFA-
V
-
-
(VREFP +
VREFN) / 2
mV
d
e
ANALOG INPUT
Single-ended, full- scale analog input voltage,
fg
internal reference
VADCIN
Differential, full-scale analog input voltage,
di
external reference
VINCM
j
Input common mode voltage, differential mode
± 25
IL
k
ADC input leakage current
k
RADC
ADC equivalent input resistance
CADC
ADC equivalent input capacitance
RS
k
k
Analog source resistance
-
-
2.0
µA
-
-
2.5
kΩ
-
-
10
pF
-
-
500
Ω
-
16
-
MHz
SAMPLING DYNAMICS
l
FADC
ADC conversion clock frequency
FCONV
ADC conversion rate
1
TS
ADC sample time
TC
ADC conversion time
-
TLT
Latency from trigger to start of conversion
250
m
Msps
-
1
-
2
ns
µs
-
ADC clocks
no
SYSTEM PERFORMANCE when using external reference
N
INL
Resolution
12
Integral nonlinearity error, over full input range
-
1314
±1.5
bits
±3.0
LSB
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Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Table 23-32. ADC Electrical Characteristics (continued)
Parameter
DNL
Parameter Name
Min
Nom
Max
Unit
p
Differential nonlinearity error, over full input
range
-
±0.8
+2.0/-1.0
LSB
EO
Offset error
-
±1.0
±3.0
LSB
EG
Gain error
q
-
±2.0
±3.0
LSB
-
±2.5
±4.0
LSB
ET
r
Total unadjusted error, over full input range
SYSTEM PERFORMANCE when using internal reference
N
Resolution
12
bits
INL
Integral nonlinearity error, over full input range
-
±1.5
±3.0
DNL
Differential nonlinearity error, over full input
range
-
±0.8
+2.0/-1.0
LSB
LSB
p
EO
Offset error
-
±5.0
±15.0
LSB
EG
Gain error
q
-
±10.0
±30.0
LSB
-
±10.0
±30.0
LSB
ET
r
Total unadjusted error, over full input range
st
DYNAMIC CHARACTERISTICS
SNRD
Signal-to-noise-ratio, Differential input, VADCIN:
u
-20dB FS, 1KHz
70
72
-
dB
SDRD
Signal-to-distortion ratio, Differential input,
uvw
VADCIN: -3dB FS, 1KHz
72
75
-
dB
SNDRD
Signal-to-Noise+Distortion ratio, Differential
uxy
input, VADCIN: -3dB FS, 1KHz
68
70
-
dB
Signal-to-noise-ratio, Single-ended input,
VADCIN: -20dB FS, 1KHz
60
65
-
dB
SDRS
Signal-to-distortion ratio, Single-ended input,
vw
VADCIN: -3dB FS, 1KHz
70
72
-
dB
SNDRS
Signal-to-Noise+Distortion ratio, Single-ended
xyz
input, VADCIN: -3dB FS, 1KHz
60
63
-
dB
SNRS
z
TEMPERATURE SENSOR
VTSENS
Temperature sensor voltage, junction
temperature 25 °C
-
1.633
-
V
STSENS
Temperature sensor slope
-
-13.3
-
mV/°C
-
-
±5
°C
ETSENS
aa
Temperature sensor accuracy
a. VREF+= 3.3V, FADC=16 MHz unless otherwise noted.
b. Best design practices suggest that static or quiet digital I/O signals be configured adjacent to sensitive analog inputs to
reduce capacitive coupling and cross talk. Analog signals configured adjacent to ADC input channels should meet the
same source resistance and bandwidth limitations that apply to the ADC input signals.
c. Two capacitors in parallel.
d. Assumes external filtering network between VREFA+ and VREFA- as shown in Figure 23-18 on page 1316. External reference
noise level must be under 12bit (-74 dB) of Full Scale input, over input bandwidth, measured at VREFA+ - VREFA-.
e. Two capacitors in parallel.
f. Internal reference is connected directly between VDDA and GNDA (VREFi = VDDA - GNDA). In this mode, EO, EG, ET, and
dynamic specifications are adversely affected due to internal voltage drop and noise on VDDA and GNDA. Internal
reference voltage is selected when VREF field in the ADCCTL register is 0x0.
g. VADCIN = VINP - VINN
h. With signal common mode as VDDA/2.
i. With signal common mode as (VREF+ + VREF-)/2.
j. This parameter is defined as the average of the differential inputs.
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Electrical Characteristics
k. As shown in Figure 23-19 on page 1317, RADC is the total equivalent resistance in the input line all the way up to the sampling
node at the input of the ADC.
l. See “System Clock Specification with ADC Operation” on page 1304 for full ADC clock frequency specification.
m. ADC conversion time (Tc) includes the ADC sample time (Ts).
n. Low noise environment is assumed in order to obtain values close to spec. Board must have good ground isolation between
analog and digital grounds, a clean reference voltage is assumed, and input signal must be bandlimited to Nyquist
bandwidth. No anti-aliasing filter is provided internally.
o. ADC static measurements taken by averaging over several samples. At least 20-sample averaging is assumed to obtain
expected typical or maximum spec values.
p. 12-bit DNL
q. Gain error is measured at max code after compensating for offset. Gain error is equivalent to "Full Scale Error." It can be
given in % of slope error, or in LSB, as done here.
r. Total Unadjusted Error is the maximum error at any one code versus the ideal ADC curve. It includes all other errors (offset
error, gain error and INL) at any given ADC code.
s. A low-noise environment is assumed in order to obtain values close to spec. The board must have good ground isolation
between analog and digital grounds and a clean reference voltage. The input signal must be band-limited to Nyquist
bandwidth. No anti-aliasing filter is provided internally.
t. ADC dynamic characteristics are measured using low-noise board design, with low-noise reference voltage ( < -74dB noise
level in signal BW) and low-noise analog supply voltage. Board noise and ground bouncing couple into the ADC and
affect dynamic characteristics. Clean external reference must be used to achieve shown specs.
u. Differential signal with correct common mode, applied between two ADC inputs.
v. SDR = -THD in dB.
w. For higher frequency inputs, degradation in SDR should be expected.
x. SNDR = S/(N+D) = SINAD (in dB)
y. Effective number of bits (ENOB) can be calculated from SNDR: ENOB = (SNDR - 1.76) / 6.02.
z. Single-ended inputs are more sensitive to board and trace noise than differential inputs; SNR and SNDR measurements
on single-ended inputs are highly dependent on how clean the test set-up is. If the input signal is not well-isolated on
the board, higher noise than specified could potentially be seen at the ADC output.
aa. Note that this parameter does not include ADC error.
Figure 23-18. ADC External Reference Filtering
Tiva™ Microcontroller
VREFP
VREFA+
IVREF
VREFA+
CREF
ADC
VREFN
VREFA
VREF
VREFA
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Tiva™ TM4C123BH6PGE Microcontroller
Figure 23-19. ADC Input Equivalency Diagram
Tiva™ Microcontroller
Zs
Rs
VS
ESD clamps
to GND only
Input PAD
Equivalent
Circuit
ZADC
RADC
Pin
Cs
VADCIN
5V ESD
Clamp
12‐bit
SAR ADC
Converter
12‐bit
Word
IL
Pin
Input PAD
Equivalent
Circuit
Pin
Input PAD
Equivalent
Circuit
RADC
RADC
CADC
June 12, 2014
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Texas Instruments-Production Data
Electrical Characteristics
23.15
Synchronous Serial Interface (SSI)
Table 23-33. SSI Characteristics
Parameter
No.
Parameter
Parameter Name
Min
Nom
Max
Unit
S1
TCLK_PER
40
-
-
ns
SSIClk cycle time, as slave
150
-
-
ns
S2
TCLK_HIGH
SSIClk high time, as master
20
-
-
ns
SSIClk high time, as slave
75
-
-
ns
S3
TCLK_LOW
SSIClk low time, as master
20
-
-
ns
S4
TCLKR
SSIClk rise time
75
-
-
ns
1.25
-
-
S5
TCLKF
c
ns
1.25
-
-
ns
S6
TTXDMOV
Master Mode: Master Tx Data Output (to slave)
Valid Time from edge of SSIClk
-
-
15.7
ns
S7
TTXDMOH
Master Mode: Master Tx Data Output (to slave)
Hold Time from next SSIClk
0.31
-
-
ns
S8
TRXDMS
Master Mode: Master Rx Data In (from slave)
setup time
17.15
-
-
ns
S9
TRXDMH
Master Mode: Master Rx Data In (from slave) hold
time
0
-
-
ns
S10
TTXDSOV
Slave Mode: Master Tx Data Output (to Master)
Valid Time from edge of SSIClk
-
-
77.74
ns
S11
TTXDSOH
Slave Mode: Slave Tx Data Output (to Master)
Hold Time from next SSIClk
55.5
-
-
ns
S12
TRXDSSU
Slave Mode: Rx Data In (from master) setup time
-
-
ns
-
-
ns
a
S13
TRXDSH
SSIClk cycle time, as master
b
SSIClk low time, as slave
c
SSIClk fall time
Slave Mode: Rx Data In (from master) hold time
e
0
f
51.55
d
a. In master mode, the system clock must be at least twice as fast as the SSIClk.
b. In slave mode, the system clock must be at least 12 times faster than the SSIClk.
c. Note that the delays shown are using 8-mA drive strength.
d. This MAX value is for the minimum TSYSCLK (12.5 ns). To find the MAX TTXDSOV value for a larger TSYSCLK, use the
equation: 4*TSYSCLK+27.74.
e. This MIN value is for the minimum slave mode TSYSCLK (12.5 ns). To find the MIN TTXDSOH value for a larger TSYSCLK,
use the equation: 4*TSYSCLK+5.50.
f. This MIN value is for the minimum slave mode TSYSCLK (12.5 ns). To find the MIN TRXDSH value for a larger TSYSCLK, use
the equation: 4*TSYSCLK+1.55.
1318
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Tiva™ TM4C123BH6PGE Microcontroller
Figure 23-20. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement
S1
S2
S4
S5
SSIClk
S3
SSIFss
SSITx
SSIRx
MSB
LSB
4 to 16 bits
Figure 23-21. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer
S2
S1
S5
S4
SSIClk
S3
SSIFss
SSITx
MSB
LSB
8-bit control
SSIRx
0
MSB
LSB
4 to 16 bits output data
June 12, 2014
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Texas Instruments-Production Data
Electrical Characteristics
Figure 23-22. Master Mode SSI Timing for SPI Frame Format (FRF=00), with SPH=1
S1
S5
S2
S4
SSIClk
(SPO=1)
S3
SSIClk
(SPO=0)
S7
S6
SSITx
MSB
(to slave)
S8
SSIRx
LSB
S9
MSB
( from slave)
LSB
SSIFss
Figure 23-23. Slave Mode SSI Timing for SPI Frame Format (FRF=00), with SPH=1
S1
S5
S4
S2
SSIClk
(SPO=1)
S3
S3
SSIClk
(SPO=0)
S10
SSITx
S11
MSB
(to master)
LSB
S12
S13
SSIRx
( from master)
MSB
LSB
SSIFss
1320
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Tiva™ TM4C123BH6PGE Microcontroller
23.16
Inter-Integrated Circuit (I2C) Interface
Table 23-34. I2C Characteristics
Parameter
No.
Parameter Parameter Name
Min
Nom
Max
Unit
a
TSCH
Start condition hold time
36
-
-
system clocks
a
TLP
Clock Low period
36
-
-
system clocks
b
I3
TSRT
I2CSCL/I2CSDA rise time (VIL =0.5 V
to V IH =2.4 V)
-
-
(see note
b)
ns
I4
TDH
Data hold time (slave)
-
2
-
system clocks
Data hold time (master)
-
7
-
system clocks
c
TSFT
I2CSCL/I2CSDA fall time (VIH =2.4 V
to V IL =0.5 V)
-
9
10
ns
a
THT
Clock High time
24
-
-
system clocks
I1
I2
I5
I6
I7
Data setup time
18
-
-
system clocks
a
TSCSR
Start condition setup time (for
repeated start condition only)
36
-
-
system clocks
I9
a
TSCS
Stop condition setup time
24
-
-
system clocks
Data Valid (slave)
-
2
-
system clocks
I10
TDV
Data Valid (master)
-
(6 * (1 +
TPR)) + 1
-
system clocks
I8
TDS
a. Values depend on the value programmed into the TPR bit in the I2C Master Timer Period (I2CMTPR) register; a TPR
programmed for the maximum I2CSCL frequency (TPR=0x2) results in a minimum output timing as shown in the table
above. The I 2C interface is designed to scale the actual data transition time to move it to the middle of the I2CSCL Low
period. The actual position is affected by the value programmed into the TPR; however, the numbers given in the above
values are minimum values.
b. Because I2CSCL and I2CSDA operate as open-drain-type signals, which the controller can only actively drive Low, the
time I2CSCL or I2CSDA takes to reach a high level depends on external signal capacitance and pull-up resistor values.
c. Specified at a nominal 50 pF load.
Figure 23-24. I2C Timing
I2
I10
I6
I5
I2CSCL
I1
I4
I7
I8
I3
I9
I2CSDA
June 12, 2014
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Electrical Characteristics
23.17
Analog Comparator
ab
Table 23-35. Analog Comparator Characteristics
Parameter
Parameter Name
c
VINP,VINN
VCM
VOS
IINP,IINN
CMRR
Min
Nom
Max
Unit
Input voltage range
GNDA
-
VDDA
V
Input common mode voltage range
GNDA
-
VDDA
V
d
Input offset voltage
-
±10
±50
mV
Input leakage current over full voltage range
-
-
2.0
µA
Common mode rejection ratio
-
50
-
dB
e
TRT
Response time
-
-
1.0
µs
TMC
Comparator mode change to Output Valid
-
-
10
µs
a. Best design practices suggest that static or quiet digital I/O signals be configured adjacent to sensitive analog inputs to
reduce capacitive coupling and cross talk.
b. To achieve best analog results, the source resistance driving the analog inputs, VINP and VINN, should be kept low.
c. The external voltage inputs to the Analog Comparator are designed to be highly sensitive and can be affected by external
noise on the board. For this reason, VINP and VINN must be set to different voltage levels during idle states to ensure the
analog comparator triggers are not enabled. If an internal voltage reference is used, it should be set to a mid-supply
level. When operating in Sleep/Deep-Sleep modes, the Analog Comparator module external voltage inputs set to different
levels (greater than the input offset voltage) to achieve minimum current draw.
d. Measured at VREF=100 mV.
e. Measured at external VREF=100 mV, input signal switching from 75 mV to 125 mV.
Table 23-36. Analog Comparator Voltage Reference Characteristics
Parameter
Parameter Name
Min
Nom
Max
Unit
RHR
Resolution in high range
-
VDDA/29.4
-
V
RLR
Resolution in low range
-
VDDA/22.12
-
V
AHR
Absolute accuracy high range
-
-
±RHR/2
V
ALR
Absolute accuracy low range
-
-
±RLR/2
V
Table 23-37. Analog Comparator Voltage Reference Characteristics, VDDA = 3.3V, EN= 1, and
RNG = 0
VREF Value
VIREF Min
Ideal VIREF
VIREF Max
Unit
0x0
0.731
0.786
0.841
V
0x1
0.843
0.898
0.953
V
0x2
0.955
1.010
1.065
V
0x3
1.067
1.122
1.178
V
0x4
1.180
1.235
1.290
V
0x5
1.292
1.347
1.402
V
0x6
1.404
1.459
1.514
V
0x7
1.516
1.571
1.627
V
0x8
1.629
1.684
1.739
V
0x9
1.741
1.796
1.851
V
0xA
1.853
1.908
1.963
V
0xB
1.965
2.020
2.076
V
0xC
2.078
2.133
2.188
V
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Tiva™ TM4C123BH6PGE Microcontroller
Table 23-37. Analog Comparator Voltage Reference Characteristics, VDDA = 3.3V, EN= 1, and
RNG = 0 (continued)
VREF Value
VIREF Min
Ideal VIREF
VIREF Max
Unit
0xD
2.190
2.245
2.300
V
0xE
2.302
2.357
2.412
V
0xF
2.414
2.469
2.525
V
Table 23-38. Analog Comparator Voltage Reference Characteristics, VDDA = 3.3V, EN= 1, and
RNG = 1
23.18
VREF Value
VIREF Min
Ideal VIREF
VIREF Max
Unit
0x0
0.000
0.000
0.074
V
0x1
0.076
0.149
0.223
V
0x2
0.225
0.298
0.372
V
0x3
0.374
0.448
0.521
V
0x4
0.523
0.597
0.670
V
0x5
0.672
0.746
0.820
V
0x6
0.822
0.895
0.969
V
0x7
0.971
1.044
1.118
V
0x8
1.120
1.193
1.267
V
0x9
1.269
1.343
1.416
V
0xA
1.418
1.492
1.565
V
0xB
1.567
1.641
1.715
V
0xC
1.717
1.790
1.864
V
0xD
1.866
1.939
2.013
V
0xE
2.015
2.089
2.162
V
0xF
2.164
2.238
2.311
V
Pulse-Width Modulator (PWM)
Table 23-39. PWM Timing Characteristics
Parameter
TFLTW
Parameter Name
Minimum Fault Pulse Width
a
TFLTMAX
MnFAULTn Assertion to PWM Inactive
TFLTMIN
MnFAULTn De-Assertion to PWM Active
b
Min
Nom
Max
Unit
2
-
-
PWM clock periods
-
-
27 + (1 PWM
clock)
ns
5
-
-
ns
a. This parameter value can vary depending on the PWM clock frequency which is controlled by the System Clock and a
programmable divider field in the PWMCC register.
b. The latch and minimum fault period functions that can be enabled in the PWMnCTL register can change the timing of this
parameter.
June 12, 2014
1323
Texas Instruments-Production Data
Electrical Characteristics
23.19
Current Consumption
Table 23-40. Current Consumption
System Clock
Parameter
Parameter Name
Conditions
VDD = 3.3 V
VDDA = 3.3 V
VDD = 3.3 V
VDDA = 3.3 V
VDD = 3.3 V
VDDA = 3.3 V
VDD = 3.3 V
VDDA = 3.3 V
a
IDDA
VDD = 3.3 V
Deep-Sleep mode
Peripherals = All ON
Run, Sleep and
Deep-sleep mode
VDD = 3.3 V
Peripherals = All OFF
mA
32.0
32.7
40.6
mA
19.6
19.7
20.3
27.6
mA
PIOSC
17.5
17.6
18.0
25.3
mA
45.0
45.1
40 MHz
MOSC with
PLL
31.9
16 MHz
MOSC with
PLL
16 MHz
-40°C 25°C
85°C
1 MHz
PIOSC
10.0
10.1
10.5
17.5
mA
80 MHz
MOSC with
PLL
24.5
24.7
25.2
31.3
mA
40 MHz
MOSC with
PLL
19.6
19.7
20.4
25.9
mA
16 MHz
MOSC with
PLL
12.1
12.2
12.7
18.7
mA
16 MHz
PIOSC
10.1
10.1
10.5
16.4
mA
1 MHz
PIOSC
5.45
5.50
5.98
11.6
mA
80 MHz
MOSC with
PLL
34.7
34.9
35.5
44.2
mA
40 MHz
MOSC with
PLL
22.2
22.4
22.9
30.2
mA
16 MHz
MOSC with
PLL
14.7
14.8
15.3
21.8
mA
16 MHz
PIOSC
12.8
12.9
13.4
19.7
mA
1 MHz
PIOSC
8.07
8.16
8.61
14.6
mA
80 MHz
MOSC with
PLL
15.2
15.3
15.8
21.7
mA
40 MHz
MOSC with
PLL
10.3
10.5
10.9
16.2
mA
16 MHz
MOSC with
PLL
7.32
7.45
7.92
13.0
mA
16 MHz
PIOSC
5.87
5.96
6.35
13.7
mA
1 MHz
PIOSC
3.54
3.63
4.07
8.84
mA
-
MOSC with
PLL,
PIOSC
2.71
2.71
2.71
3.97
mA
30 kHz
LFIOSC
2.54
2.54
2.54
3.68
mA
-
MOSC with
PLL,
PIOSC,
LFIOSC
0.28
0.28
0.29
0.56
mA
VDDA = 3.3 V
VDDA = 3.3 V
54.9
MOSC with
PLL
Peripherals = All OFF
Run, Sleep and
Deep-sleep mode
45.7
80 MHz
Peripherals = All ON
Run mode (SRAM loop)
Unit
Clock
Source
Peripherals = All OFF
IDD_RUN
Max
85°C
Frequency
Peripherals = All ON
Run mode (Flash loop)
Nom
1324
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
Table 23-40. Current Consumption (continued)
System Clock
Parameter
Parameter Name
Conditions
VDD = 3.3 V
Sleep mode (FLASHPM
= 0x0)
VDD = 3.3 V
VDD = 3.3 V
VDD = 3.3 V
20.2
27.1
mA
13.6
13.8
14.2
20.6
mA
b
11.7
11.8
12.2
18.5
mA
b
40 MHz
MOSC with
PLL
19.5
16 MHz
MOSC with
PLL
16 MHz
PIOSC
-40°C 25°C
85°C
1 MHz
PIOSC
7.01
7.06
7.93
12.0
mA
80 MHz
MOSC with
PLL
9.60
9.73
10.2
15.4
mA
40 MHz
MOSC with
PLL
7.49
7.60
8.06
13.2
mA
16 MHz
MOSC with
PLL
6.22
6.33
6.78
11.7
mA
16 MHz
PIOSC
b
4.28
4.35
4.77
9.52
mA
b
1 MHz
PIOSC
3.52
3.59
4.01
8.70
mA
80 MHz
MOSC with
PLL
28.4
28.6
29.2
37.2
mA
40 MHz
MOSC with
PLL
18.6
18.8
19.3
26.2
mA
16 MHz
MOSC with
PLL
12.7
12.9
13.3
19.7
mA
16 MHz
PIOSC
b
10.8
10.9
11.3
17.5
mA
b
1 MHz
PIOSC
7.09
7.20
7.67
13.6
mA
80 MHz
MOSC with
PLL
8.66
8.82
9.31
14.5
mA
40 MHz
MOSC with
PLL
6.55
6.69
7.17
12.1
mA
16 MHz
MOSC with
PLL
5.27
5.41
5.89
10.7
mA
16 MHz
PIOSC
b
3.34
3.44
3.88
8.65
mA
1 MHz
PIOSC
b
2.58
2.67
3.13
7.85
mA
VDDA = 3.3 V
Peripherals = All OFF
19.7
29.5
LDO = 1.2 V
Sleep mode (FLASHPM
= 0x2)
mA
29.3
VDDA = 3.3 V
Peripherals = All ON
38.1
MOSC with
PLL
LDO = 1.2 V
IDD_SLEEP
30.0
80 MHz
VDDA = 3.3 V
Peripherals = All OFF
Unit
Clock
Source
LDO = 1.2 V
Max
85°C
Frequency
VDDA = 3.3 V
Peripherals = All ON
Nom
LDO = 1.2 V
June 12, 2014
1325
Texas Instruments-Production Data
Electrical Characteristics
Table 23-40. Current Consumption (continued)
System Clock
Parameter
Parameter Name
Nom
Conditions
Frequency
VDD = 3.3 V
16 MHz
PIOSC
9.29
9.29
VDDA = 3.3 V
30 kHz
LFIOSC
5.10
5.10
VDD = 3.3 V
16 MHz
PIOSC
3.51
VDDA = 3.3 V
30 kHz
LFIOSC
Clock
Source
Max
85°C
Unit
9.66
15.9
mA
5.48
11.2
mA
3.51
3.91
8.67
mA
2.00
2.00
2.39
7.24
mA
-40°C 25°C
85°C
Peripherals = All ON
Deep-sleep mode
(FLASHPM = 0x0)
LDO = 1.2 V
Peripherals = All OFF
LDO = 1.2 V
IDD_DEEPSLEEP
VDD = 3.3 V
16 MHz
PIOSC
8.34
8.36
8.77
14.9
mA
VDDA = 3.3 V
30 kHz
LFIOSC
4.14
4.18
4.59
10.4
mA
VDD = 3.3 V
16 MHz
PIOSC
2.56
2.60
3.02
7.79
mA
VDDA = 3.3 V
30 kHz
LFIOSC
1.04
1.07
1.49
6.48
mA
-
-
1.23
1.38
1.54
5.20
µA
-
-
1.27
1.40
1.69
5.24
µA
-
-
3.17
4.49
10.6
28.1
µA
-
-
3.16
4.33
10.4
27.7
µA
Peripherals = All ON
Deep-sleep mode
(FLASHPM = 0x2)
LDO = 1.2 V
Peripherals = All OFF
LDO = 1.2 V
IHIB_NORTC
Hibernate mode
(external wake, RTC
disabled)
VBAT = 3.0 V
VDD = 0 V
VDDA = 0 V
System Clock = OFF
Hibernate Module = 32.768
kHz
IHIB_RTC
Hibernate mode (RTC
enabled)
VBAT = 3.0 V
VDD = 0 V
VDDA = 0 V
System Clock = OFF
Hibernate Module = 32.768
kHz
Hibernate mode
(VDD3ON mode, RTC
on)
VBAT = 3.0 V
VDD = 3.3 V
VDDA = 3.3 V
System Clock = OFF
IHIB_VDD3ON
Hibernate Module = 32.768
kHz
Hibernate mode
(VDD3ON mode, RTC
off)
VBAT = 3.0 V
VDD = 3.3 V
VDDA = 3.3 V
System Clock = OFF
Hibernate Module = 32.768
kHz
a. The value for IDDA is included in the above values for IDD_RUN, IDD_SLEEP, and IDD_DEEPSLEEP.
b. Note that if the MOSC is the source of the Run-mode system clock and is powered down in Sleep mode, wake time is increased by
TMOSC_SETTLE.
1326
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
A
Package Information
A.1
Orderable Devices
The figure below defines the full set of orderable part numbers for the TM4C123x Series. See the
Package Option Addendum for the complete list of valid orderable part numbers for the
TM4C123BH6PGE microcontroller.
Figure A-1. Key to Part Numbers
T M4 C 1 SSS M Y PPP T XX Z R
Shipping Medium
R = Tape-and-reel
Omitted = Default shipping (tray or tube)
Prefix
T = Qualified Device
X = Experimental Device
Revision
Core
M4 = ARM® Cortex™-M4
Special Codes
Optional
Tiva Series
C = Connected MCUs
Temperature
I = –40°C to +85°C
T = –40°C to +105°C
Package
PM = 64-pin LQFP
PZ = 100-pin LQFP
PGE = 144-pin LQFP
ZRB = 157-ball BGA
Data Memory
3 = 12 KB
5 = 24 KB
6 = 32 KB
Family
Part Number
SSS = Series identifier
Program Memory
C = 32 KB
D = 64 KB
E = 128 KB
H = 256 KB
A.2
Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers
of all microcontroller (MCU) devices. Each Tiva™ C Series family member has one of two prefixes:
XM4C or TM4C. These prefixes represent evolutionary stages of product development from
engineering prototypes (XM4C) through fully qualified production devices (TM4C).
Device development evolutionary flow:
■ XM4C — Experimental device that is not necessarily representative of the final device's electrical
specifications and may not use production assembly flow.
■ TM4C — Production version of the silicon die that is fully qualified.
XM4C devices are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
TM4C devices have been characterized fully, and the quality and reliability of the device have been
demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (XM4C) have a greater failure rate than the standard
production devices. Texas Instruments recommends that these devices not be used in any production
system because their expected end-use failure rate still is undefined. Only qualified production
devices are to be used.
June 12, 2014
1327
Texas Instruments-Production Data
Package Information
A.3
Device Markings
The figure below shows an example of the Tiva™ microcontroller package symbolization.
$$
TM4C123G
H6PGEI7
YMLLLLS
G1
This identifying number contains the following information:
■ Lines 1 and 5: Internal tracking numbers
■ Lines 2 and 3: Part number
For example, TM4C123G on the second line followed by H6PGEI7 on the third line indicates
orderable part number TM4C123GH6PGEI7. The silicon revision number is the last number in
the part number, in this example, 7. The DID0 register also identifies the version of the
microcontroller, as shown in the table below. Combined, the MAJOR and MINOR bit fields indicate
the die revision and part revision numbers.
MAJOR Bitfield Value
MINOR Bitfield Value
Die Revision
Part Revision
0x0
0x0
A0
1
0x0
0x1
A1
2
0x0
0x2
A2
3
0x0
0x3
A3
4
0x1
0x0
B0
5
0x1
0x1
B1
6
0x1
0x2
B2
7
■ Line 4: Date code
The first two characters on the fourth line indicate the date code, followed by internal tracking
numbers. The two-digit date code YM indicates the last digit of the year, then the month. For
example, a 34 for the first two digits of the fourth line indicates a date code of April 2013.
1328
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C123BH6PGE Microcontroller
A.4
Packaging Diagram
Figure A-2. TM4C123BH6PGE 144-Pin LQFP Package Diagram
MECHANICAL DATA
MTQF017A – OCTOBER 1994 – REVISED DECEMBER 1996
PGE (S-PQFP-G144)
PLASTIC QUAD FLATPACK
108
73
109
72
0,27
0,17
0,08 M
0,50
144
0,13 NOM
37
1
36
Gage Plane
17,50 TYP
20,20 SQ
19,80
22,20
SQ
21,80
0,25
0,05 MIN
0°– 7°
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040147 / C 10/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
June 12, 2014
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
Texas Instruments-Production Data
1329
1
PACKAGE OPTION ADDENDUM
www.ti.com
2-Mar-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TM4C123BH6PGEI
ACTIVE
LQFP
PGE
144
60
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
TM4C123B
H6PGEI
TM4C123BH6PGEI7
ACTIVE
LQFP
PGE
144
60
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
TM4C123B
H6PGEI7
TM4C123BH6PGEI7R
ACTIVE
LQFP
PGE
144
500
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
TM4C123B
H6PGEI7
TM4C123BH6PGEIR
ACTIVE
LQFP
PGE
144
500
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
TM4C123B
H6PGEI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of